system
stringclasses 7
values | input
stringlengths 10
94.5k
| output
stringlengths 14
55.5k
|
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <iostream>
int main( int argc, char* argv[] )
{
// Size of vectors
int n = 10;
// Device input vectors
double *d_a;
// Size, in bytes, of each vector
size_t bytes = n*sizeof(double);
// Allocate memory for each vector on GPU
hipMalloc(&d_a, bytes);
// Free memory
hipFree(d_a);
return 0;
}
|
.text
.file "vector_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $80, %esi
callq hipMalloc
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00169a73_00000000-6_vector_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $80, %esi
call cudaMalloc@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "vector_add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
movl $80, %esi
callq hipMalloc
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <fstream>
#include <vector>
#include <cmath>
#define HANDLE_ERROR(err) \
do { if (err != cudaSuccess) { printf("ERROR: %s\n", cudaGetErrorString(err)); exit(0);} } while (0)
__constant__ double AVG[32][3];
__constant__ double COV[32][3][3];
__constant__ double COV_INV[32][3][3];
__constant__ double DETS[32];
__device__ double func(uchar4 p, int i)
{
double res = 0.0, p_avg[3], tmp[3];
for (int j = 0; j < 3; ++j) {
p_avg[j] = 0.0;
tmp[j] = 0.0;
}
p_avg[0] = p.x - AVG[i][0];
p_avg[1] = p.y - AVG[i][1];
p_avg[2] = p.z - AVG[i][2];
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
tmp[j] += -p_avg[k] * COV_INV[i][k][j];
}
res += tmp[j] * p_avg[j];
}
res -= std::log(std::abs(DETS[i]));
return res;
}
__device__ int getClass(uchar4 pixel, int nc)
{
double res[32];
for (int i = 0; i < nc; ++i) {
res[i] = func(pixel, i);
}
double maxEl = res[0];
int idx = 0;
for (int i = 0; i < nc; ++i) {
if (res[i] > maxEl) {
maxEl = res[i];
idx = i;
}
}
return idx;
}
__global__ void kernel(uchar4 *dst, int w, int h, int nc)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int offsetx = blockDim.x * gridDim.x;
int offsety = blockDim.y * gridDim.y;
for (int x = idx; x < w; x += offsetx) {
for (int y = idy; y < h; y += offsety) {
dst[x + y * w].w = getClass(dst[x + y * w], nc);
}
}
}
int main()
{
std::string input, output;
int w, h, nc, np;
uchar4 *data;
std::cin >> input >> output >> nc;
std::vector<std::vector<int2>> classes(nc);
for (int i = 0; i < nc; ++i) {
std::cin >> np;
classes[i].resize(np);
for (int j = 0; j < np; ++j) {
std::cin >> classes[i][j].x >> classes[i][j].y;
}
}
std::ifstream fsIn(input, std::ios::in | std::ios::binary);
if (fsIn.is_open()) {
fsIn.read((char *)&w, sizeof(w));
fsIn.read((char *)&h, sizeof(h));
data = new uchar4[w * h];
fsIn.read((char *)data, w * h * sizeof(data[0]));
fsIn.close();
} else {
return 1;
}
// дальше начинаются интересные вещи
double avg[32][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
avg[i][j] = 0.0;
}
}
for (int i = 0; i < nc; ++i) {
int np = classes[i].size();
for (int j = 0; j < np; ++j) {
int x = classes[i][j].x;
int y = classes[i][j].y;
uchar4 curPixel = data[x + y * w];
avg[i][0] += curPixel.x;
avg[i][1] += curPixel.y;
avg[i][2] += curPixel.z;
}
for (int k = 0; k < 3; ++k) {
avg[i][k] /= np;
}
}
double cov[32][3][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
cov[i][j][k] = 0.0;
}
}
}
for (int i = 0; i < nc; ++i) {
np = classes[i].size();
for (int j = 0; j < np; ++j) {
double tmp[3];
int x = classes[i][j].x;
int y = classes[i][j].y;
uchar4 curPixel = data[x + y * w];
tmp[0] = curPixel.x - avg[i][0];
tmp[1] = curPixel.y - avg[i][1];
tmp[2] = curPixel.z - avg[i][2];
for (int k = 0; k < 3; ++k) {
for (int l = 0; l < 3; ++l) {
cov[i][k][l] += tmp[k] * tmp[l];
}
}
}
for (int k = 0; k < 3; ++k) {
for (int l = 0; l < 3; ++l) {
cov[i][k][l] /= np - 1;
}
}
}
double cov_inv[32][3][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
cov_inv[i][j][k] = 0.0;
}
}
}
double dets[32];
for (int i = 0; i < nc; ++i) {
double det = 0;
for (int j = 0; j < 3; ++j) {
det += cov[i][0][j] * (cov[i][1][(j + 1) % 3] * cov[i][2][(j + 2) % 3] - cov[i][1][(j + 2) % 3] * cov[i][2][(j + 1) % 3]);
}
dets[i] = det;
}
// извините
for (int i = 0; i < nc; ++i) {
cov_inv[i][0][0] = (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) / dets[i];
cov_inv[i][0][1] = (cov[i][0][2] * cov[i][2][1] - cov[i][0][1] * cov[i][2][2]) / dets[i];
cov_inv[i][0][2] = (cov[i][0][1] * cov[i][1][2] - cov[i][0][2] * cov[i][1][1]) / dets[i];
cov_inv[i][1][0] = (cov[i][1][2] * cov[i][2][0] - cov[i][1][0] * cov[i][2][2]) / dets[i];
cov_inv[i][1][1] = (cov[i][0][0] * cov[i][2][2] - cov[i][0][2] * cov[i][2][0]) / dets[i];
cov_inv[i][1][2] = (cov[i][1][0] * cov[i][0][2] - cov[i][0][0] * cov[i][1][2]) / dets[i];
cov_inv[i][2][0] = (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]) / dets[i];
cov_inv[i][2][1] = (cov[i][2][0] * cov[i][0][1] - cov[i][0][0] * cov[i][2][1]) / dets[i];
cov_inv[i][2][2] = (cov[i][0][0] * cov[i][1][1] - cov[i][1][0] * cov[i][0][1]) / dets[i];
}
HANDLE_ERROR(cudaMemcpyToSymbol(AVG, avg, sizeof(double) * 32 * 3));
HANDLE_ERROR(cudaMemcpyToSymbol(COV, cov, sizeof(double) * 32 * 3 * 3));
HANDLE_ERROR(cudaMemcpyToSymbol(COV_INV, cov_inv, sizeof(double) * 32 * 3 * 3));
HANDLE_ERROR(cudaMemcpyToSymbol(DETS, dets, sizeof(double) * 32));
uchar4 *dev_data;
HANDLE_ERROR(cudaMalloc(&dev_data, sizeof(uchar4) * h * w));
HANDLE_ERROR(cudaMemcpy(dev_data, data, sizeof(uchar4) * h * w, cudaMemcpyHostToDevice));
kernel<<<dim3(16, 16), dim3(16, 16)>>>(dev_data, w, h, nc);
HANDLE_ERROR(cudaMemcpy(data, dev_data, sizeof(uchar4) * h * w, cudaMemcpyDeviceToHost));
std::ofstream fsOut(output, std::ios::out | std::ios::binary);
if (fsOut.is_open()) {
fsOut.write((char *)&w, sizeof(w));
fsOut.write((char *)&h, sizeof(h));
fsOut.write((char *)data, w * h * sizeof(data[0]));
fsOut.close();
} else {
return 1;
}
HANDLE_ERROR(cudaFree(dev_data));
delete[] data;
return 0;
}
|
.file "tmpxft_0017a0fd_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4169:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4169:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4func6uchar4i
.type _Z4func6uchar4i, @function
_Z4func6uchar4i:
.LFB4163:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4163:
.size _Z4func6uchar4i, .-_Z4func6uchar4i
.globl _Z8getClass6uchar4i
.type _Z8getClass6uchar4i, @function
_Z8getClass6uchar4i:
.LFB4164:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4164:
.size _Z8getClass6uchar4i, .-_Z8getClass6uchar4i
.globl _Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii
.type _Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii, @function
_Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii:
.LFB4191:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelP6uchar4iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4191:
.size _Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii, .-_Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii
.globl _Z6kernelP6uchar4iii
.type _Z6kernelP6uchar4iii, @function
_Z6kernelP6uchar4iii:
.LFB4192:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4192:
.size _Z6kernelP6uchar4iii, .-_Z6kernelP6uchar4iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelP6uchar4iii"
.LC1:
.string "AVG"
.LC2:
.string "COV"
.LC3:
.string "COV_INV"
.LC4:
.string "DETS"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4194:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelP6uchar4iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $768, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3AVG(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL3COV(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7COV_INV(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4DETS(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4194:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev,"axG",@progbits,_ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev
.type _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev, @function
_ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev:
.LFB4523:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq 8(%rdi), %rbp
movq (%rdi), %rbx
cmpq %rbx, %rbp
jne .L20
.L18:
movq (%r12), %rdi
testq %rdi, %rdi
je .L17
movq 16(%r12), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L17:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
addq $24, %rbx
cmpq %rbx, %rbp
je .L18
.L20:
movq (%rbx), %rdi
testq %rdi, %rdi
je .L19
movq 16(%rbx), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
jmp .L19
.cfi_endproc
.LFE4523:
.size _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev, .-_ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev
.weak _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED1Ev
.set _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED1Ev,_ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED2Ev
.section .rodata._ZNSt6vectorI4int2SaIS0_EE17_M_default_appendEm.str1.1,"aMS",@progbits,1
.LC5:
.string "vector::_M_default_append"
.section .text._ZNSt6vectorI4int2SaIS0_EE17_M_default_appendEm,"axG",@progbits,_ZNSt6vectorI4int2SaIS0_EE17_M_default_appendEm,comdat
.align 2
.weak _ZNSt6vectorI4int2SaIS0_EE17_M_default_appendEm
.type _ZNSt6vectorI4int2SaIS0_EE17_M_default_appendEm, @function
_ZNSt6vectorI4int2SaIS0_EE17_M_default_appendEm:
.LFB4712:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L38
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %rbx
movq 8(%rdi), %rdx
movq (%rdi), %r15
movq %rdx, %r14
subq %r15, %r14
movq %r14, %r13
sarq $3, %r13
movabsq $1152921504606846975, %rax
subq %r13, %rax
movq %rax, %rcx
movq 16(%rdi), %rax
subq %rdx, %rax
sarq $3, %rax
cmpq %rsi, %rax
jb .L26
movl $0, (%rdx)
movl $0, 4(%rdx)
leaq 8(%rdx), %rdi
subq $1, %rbx
je .L27
leaq (%rdi,%rbx,8), %rsi
movq %rdi, %rax
.L28:
movq (%rdx), %rcx
movq %rcx, (%rax)
addq $8, %rax
cmpq %rax, %rsi
jne .L28
subq %rdx, %rsi
leaq -8(%rdi,%rsi), %rdi
.L27:
movq %rdi, 8(%rbp)
.L24:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
cmpq %rsi, %rcx
jb .L41
cmpq %r13, %rsi
movq %r13, %rax
cmovnb %rsi, %rax
addq %r13, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
cmova %rdx, %rax
salq $3, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call _Znwm@PLT
movq %rax, %r12
leaq (%rax,%r14), %rdx
movl $0, (%rdx)
movl $0, 4(%rdx)
movq %rbx, %rcx
subq $1, %rcx
je .L30
leaq 8(%rdx), %rax
leaq (%rax,%rcx,8), %rsi
.L31:
movq (%rdx), %rcx
movq %rcx, (%rax)
addq $8, %rax
cmpq %rax, %rsi
jne .L31
.L30:
testq %r14, %r14
jg .L42
testq %r15, %r15
je .L34
movq 16(%rbp), %rsi
subq %r15, %rsi
jmp .L33
.L41:
leaq .LC5(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L42:
movq %r14, %rdx
movq %r15, %rsi
movq %r12, %rdi
call memmove@PLT
movq 16(%rbp), %rsi
subq %r15, %rsi
.L33:
movq %r15, %rdi
call _ZdlPvm@PLT
.L34:
movq %r12, 0(%rbp)
addq %r13, %rbx
leaq (%r12,%rbx,8), %rax
movq %rax, 8(%rbp)
movq 8(%rsp), %rax
addq %rax, %r12
movq %r12, 16(%rbp)
jmp .L24
.L38:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE4712:
.size _ZNSt6vectorI4int2SaIS0_EE17_M_default_appendEm, .-_ZNSt6vectorI4int2SaIS0_EE17_M_default_appendEm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "cannot create std::vector larger than max_size()"
.section .rodata.str1.1
.LC8:
.string "ERROR: %s\n"
.text
.globl main
.type main, @function
main:
.LFB4165:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4165
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $4096, %rsp
.cfi_def_cfa_offset 4152
orq $0, (%rsp)
subq $2776, %rsp
.cfi_def_cfa_offset 6928
movq %fs:40, %rax
movq %rax, 6856(%rsp)
xorl %eax, %eax
leaq 112(%rsp), %rsi
leaq 128(%rsp), %rax
movq %rax, 112(%rsp)
movq $0, 120(%rsp)
movb $0, 128(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
movq $0, 152(%rsp)
movb $0, 160(%rsp)
leaq _ZSt3cin(%rip), %rdi
.LEHB0:
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
movq %rax, %rdi
leaq 144(%rsp), %rsi
call _ZStrsIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EE@PLT
movq %rax, %rdi
leaq 40(%rsp), %rsi
call _ZNSirsERi@PLT
movslq 40(%rsp), %rax
movabsq $384307168202282325, %rdx
cmpq %rax, %rdx
jb .L120
movq $0, 88(%rsp)
movq $0, 96(%rsp)
testq %rax, %rax
je .L46
imulq $24, %rax, %rbx
movq %rbx, %rdi
call _Znwm@PLT
jmp .L121
.L120:
movq 6856(%rsp), %rax
subq %fs:40, %rax
jne .L122
leaq .LC7(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE0:
.L100:
endbr64
movq %rax, %rbx
jmp .L93
.L122:
call __stack_chk_fail@PLT
.L121:
movq %rax, 8(%rsp)
movq %rax, 80(%rsp)
leaq (%rax,%rbx), %rdx
movq %rdx, 96(%rsp)
.L47:
movq $0, (%rax)
movq $0, 8(%rax)
movq $0, 16(%rax)
addq $24, %rax
cmpq %rdx, %rax
jne .L47
.L95:
movq %rdx, 88(%rsp)
cmpl $0, 40(%rsp)
jle .L48
movq 8(%rsp), %r14
movl $0, %r15d
leaq _ZSt3cin(%rip), %r13
jmp .L53
.L125:
movq %r14, %r12
movslq 44(%rsp), %rsi
movq 8(%r14), %rdx
movq (%r14), %rcx
movq %rdx, %rax
subq %rcx, %rax
sarq $3, %rax
cmpq %rsi, %rax
jb .L123
cmpq %rax, %rsi
jnb .L50
leaq (%rcx,%rsi,8), %rax
cmpq %rax, %rdx
je .L50
movq %rax, 8(%r14)
.L50:
cmpl $0, 44(%rsp)
jle .L51
movl $0, %ebp
jmp .L52
.L123:
subq %rax, %rsi
movq %r14, %rdi
.LEHB1:
call _ZNSt6vectorI4int2SaIS0_EE17_M_default_appendEm
jmp .L50
.L124:
movq %rax, %rdi
addq (%r12), %rbx
leaq 4(%rbx), %rsi
call _ZNSirsERi@PLT
addq $1, %rbp
cmpl %ebp, 44(%rsp)
jle .L51
.L52:
leaq 0(,%rbp,8), %rbx
movq %rbx, %rsi
addq (%r12), %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
jmp .L124
.L51:
addl $1, %r15d
addq $24, %r14
cmpl %r15d, 40(%rsp)
jle .L48
.L53:
leaq 44(%rsp), %rsi
movq %r13, %rdi
call _ZNSirsERi@PLT
jmp .L125
.L48:
leaq 112(%rsp), %rsi
leaq 944(%rsp), %rdi
movl $12, %edx
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@PLT
.LEHE1:
leaq 1064(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
movl $1, %ebp
testb %al, %al
jne .L126
.L54:
leaq 944(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 80(%rsp), %rdi
call _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED1Ev
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 6856(%rsp), %rax
subq %fs:40, %rax
jne .L127
movl %ebp, %eax
addq $6872, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L126:
.cfi_restore_state
leaq 32(%rsp), %rsi
leaq 944(%rsp), %rdi
movl $4, %edx
.LEHB2:
call _ZNSi4readEPcl@PLT
leaq 36(%rsp), %rsi
leaq 944(%rsp), %rdi
movl $4, %edx
call _ZNSi4readEPcl@PLT
movl 32(%rsp), %eax
imull 36(%rsp), %eax
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L55
leaq 0(,%rax,4), %rdi
call _Znam@PLT
movq %rax, %rbx
movl 32(%rsp), %edx
imull 36(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
leaq 944(%rsp), %rdi
movq %rax, %rsi
call _ZNSi4readEPcl@PLT
jmp .L128
.L55:
movq 6856(%rsp), %rax
subq %fs:40, %rax
je .L57
call __stack_chk_fail@PLT
.L57:
call __cxa_throw_bad_array_new_length@PLT
.L102:
endbr64
movq %rax, %rbx
jmp .L91
.L128:
leaq 944(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq 1472(%rsp), %rdi
leaq 2240(%rsp), %rdx
movq %rdi, %rax
.L58:
movq $0x000000000, (%rax)
movq $0x000000000, 8(%rax)
movq $0x000000000, 16(%rax)
addq $24, %rax
cmpq %rdx, %rax
jne .L58
movl 40(%rsp), %edx
testl %edx, %edx
jle .L59
movl 32(%rsp), %r9d
movq 8(%rsp), %r11
movslq %edx, %rbp
imulq $24, %rbp, %rbp
addq %rdi, %rbp
movq %rdi, %rax
.L62:
movq (%r11), %rcx
movq 8(%r11), %r10
subq %rcx, %r10
sarq $3, %r10
testl %r10d, %r10d
jle .L60
movq %rcx, %rsi
leal -1(%r10), %r8d
leaq 8(%rcx,%r8,8), %r8
.L61:
movl %r9d, %ecx
imull 4(%rsi), %ecx
addl (%rsi), %ecx
movslq %ecx, %rcx
leaq (%rbx,%rcx,4), %rcx
movzbl (%rcx), %r12d
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
addsd (%rax), %xmm0
movsd %xmm0, (%rax)
movzbl 1(%rcx), %r12d
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
addsd 8(%rax), %xmm0
movsd %xmm0, 8(%rax)
movzbl 2(%rcx), %ecx
pxor %xmm0, %xmm0
cvtsi2sdl %ecx, %xmm0
addsd 16(%rax), %xmm0
movsd %xmm0, 16(%rax)
addq $8, %rsi
cmpq %r8, %rsi
jne .L61
.L60:
pxor %xmm1, %xmm1
cvtsi2sdl %r10d, %xmm1
movsd (%rax), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%rax)
movsd 8(%rax), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 8(%rax)
movsd 16(%rax), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 16(%rax)
addq $24, %r11
addq $24, %rax
cmpq %rbp, %rax
jne .L62
.L59:
leaq 2240(%rsp), %rax
leaq 4544(%rsp), %rsi
movq %rax, %rcx
.L63:
movq $0x000000000, (%rcx)
movq $0x000000000, 8(%rcx)
movq $0x000000000, 16(%rcx)
movq $0x000000000, 24(%rcx)
movq $0x000000000, 32(%rcx)
movq $0x000000000, 40(%rcx)
movq $0x000000000, 48(%rcx)
movq $0x000000000, 56(%rcx)
movq $0x000000000, 64(%rcx)
addq $72, %rcx
cmpq %rsi, %rcx
jne .L63
testl %edx, %edx
jle .L64
movl 32(%rsp), %r11d
movq 8(%rsp), %rbp
movslq %edx, %rcx
imulq $72, %rcx, %r14
movq %rax, %r9
movl $0, %r13d
leaq 4544(%rsp), %r8
leaq 4568(%rsp), %rsi
movq %rax, %r15
movl %edx, %r10d
jmp .L73
.L68:
addq $8, %rdx
cmpq %r12, %rdx
je .L129
.L69:
movl 8(%rsp), %eax
imull 4(%rdx), %eax
addl (%rdx), %eax
cltq
leaq (%rbx,%rax,4), %rax
movzbl (%rax), %r10d
pxor %xmm0, %xmm0
cvtsi2sdl %r10d, %xmm0
subsd %xmm4, %xmm0
movsd %xmm0, 4544(%rsp)
movzbl 1(%rax), %r10d
pxor %xmm0, %xmm0
cvtsi2sdl %r10d, %xmm0
subsd %xmm3, %xmm0
movsd %xmm0, 4552(%rsp)
movzbl 2(%rax), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
subsd %xmm2, %xmm0
movsd %xmm0, 4560(%rsp)
movq %r9, %r15
movq %r8, %r10
.L66:
movsd (%r10), %xmm1
movq %r8, %r11
movq %r15, %rax
.L67:
movapd %xmm1, %xmm0
mulsd (%r11), %xmm0
addsd (%rax), %xmm0
movsd %xmm0, (%rax)
addq $8, %rax
addq $8, %r11
cmpq %rsi, %r11
jne .L67
addq $8, %r10
addq $24, %r15
cmpq %rsi, %r10
jne .L66
jmp .L68
.L129:
movl 20(%rsp), %eax
movl 8(%rsp), %r11d
movq 24(%rsp), %r15
movl %ecx, %r10d
.L65:
movq %r9, %rdx
subl $1, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
addq $72, %r9
.L70:
movq %rdx, %rax
movl $3, %ecx
.L71:
movsd (%rax), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%rax)
addq $8, %rax
subl $1, %ecx
jne .L71
addq $24, %rdx
cmpq %r9, %rdx
jne .L70
addq $24, %rbp
addq $72, %r13
addq $24, %rdi
cmpq %r14, %r13
je .L130
.L73:
movq 0(%rbp), %r12
movq 8(%rbp), %rcx
subq %r12, %rcx
sarq $3, %rcx
movl %ecx, %eax
movl %ecx, 44(%rsp)
testl %ecx, %ecx
jle .L65
movsd (%rdi), %xmm4
movsd 8(%rdi), %xmm3
movsd 16(%rdi), %xmm2
movq %r12, %rdx
leal -1(%rcx), %ecx
leaq 8(%r12,%rcx,8), %r12
movl %eax, 20(%rsp)
movl %r11d, 8(%rsp)
movq %r15, 24(%rsp)
movl %r10d, %ecx
jmp .L69
.L130:
movq %r15, %rax
movl %r10d, %edx
.L64:
leaq 4544(%rsp), %rdi
leaq 6848(%rsp), %rsi
movq %rdi, %rcx
.L74:
movq $0x000000000, (%rcx)
movq $0x000000000, 8(%rcx)
movq $0x000000000, 16(%rcx)
movq $0x000000000, 24(%rcx)
movq $0x000000000, 32(%rcx)
movq $0x000000000, 40(%rcx)
movq $0x000000000, 48(%rcx)
movq $0x000000000, 56(%rcx)
movq $0x000000000, 64(%rcx)
addq $72, %rcx
cmpq %rcx, %rsi
jne .L74
testl %edx, %edx
jle .L75
movslq %edx, %r11
movq %rax, %r10
movl $0, %r9d
jmp .L76
.L131:
movsd %xmm2, 176(%rsp,%r9,8)
addq $1, %r9
addq $72, %r10
cmpq %r9, %r11
je .L78
.L76:
movl $1, %esi
pxor %xmm2, %xmm2
movslq %r9d, %rdx
leaq (%rdx,%rdx,8), %r8
.L77:
movslq %esi, %rdx
imulq $1431655766, %rdx, %rdx
shrq $32, %rdx
movl %esi, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,2), %ecx
movl %esi, %edx
subl %ecx, %edx
leal 1(%rsi), %ebp
movslq %ebp, %rcx
imulq $1431655766, %rcx, %rcx
shrq $32, %rcx
movl %ebp, %r12d
sarl $31, %r12d
subl %r12d, %ecx
leal (%rcx,%rcx,2), %r12d
movl %ebp, %ecx
subl %r12d, %ecx
movslq %edx, %rdx
addq %r8, %rdx
movslq %ecx, %rcx
addq %r8, %rcx
movsd 2264(%rsp,%rdx,8), %xmm0
mulsd 2288(%rsp,%rcx,8), %xmm0
movsd 2264(%rsp,%rcx,8), %xmm1
mulsd 2288(%rsp,%rdx,8), %xmm1
subsd %xmm1, %xmm0
mulsd -8(%r10,%rsi,8), %xmm0
addsd %xmm0, %xmm2
addq $1, %rsi
cmpq $4, %rsi
jne .L77
jmp .L131
.L78:
leaq 176(%rsp), %rdx
leaq (%rdx,%r9,8), %rcx
.L79:
movsd 32(%rax), %xmm0
movsd 64(%rax), %xmm3
movsd 56(%rax), %xmm8
movsd 40(%rax), %xmm9
movsd (%rdx), %xmm4
movapd %xmm0, %xmm1
mulsd %xmm3, %xmm1
movapd %xmm8, %xmm2
mulsd %xmm9, %xmm2
subsd %xmm2, %xmm1
divsd %xmm4, %xmm1
movsd %xmm1, (%rdi)
movsd 16(%rax), %xmm2
movsd 8(%rax), %xmm5
movapd %xmm8, %xmm1
mulsd %xmm2, %xmm1
movapd %xmm3, %xmm6
mulsd %xmm5, %xmm6
subsd %xmm6, %xmm1
divsd %xmm4, %xmm1
movsd %xmm1, 8(%rdi)
movapd %xmm9, %xmm1
mulsd %xmm5, %xmm1
movapd %xmm0, %xmm6
mulsd %xmm2, %xmm6
subsd %xmm6, %xmm1
divsd %xmm4, %xmm1
movsd %xmm1, 16(%rdi)
movsd 48(%rax), %xmm1
movsd 24(%rax), %xmm6
movapd %xmm9, %xmm7
mulsd %xmm1, %xmm7
movapd %xmm3, %xmm10
mulsd %xmm6, %xmm10
subsd %xmm10, %xmm7
divsd %xmm4, %xmm7
movsd %xmm7, 24(%rdi)
movsd (%rax), %xmm7
mulsd %xmm7, %xmm3
movapd %xmm2, %xmm10
mulsd %xmm1, %xmm10
subsd %xmm10, %xmm3
divsd %xmm4, %xmm3
movsd %xmm3, 32(%rdi)
mulsd %xmm6, %xmm2
mulsd %xmm7, %xmm9
subsd %xmm9, %xmm2
divsd %xmm4, %xmm2
movsd %xmm2, 40(%rdi)
movapd %xmm8, %xmm2
mulsd %xmm6, %xmm2
movapd %xmm0, %xmm3
mulsd %xmm1, %xmm3
subsd %xmm3, %xmm2
divsd %xmm4, %xmm2
movsd %xmm2, 48(%rdi)
mulsd %xmm5, %xmm1
mulsd %xmm7, %xmm8
subsd %xmm8, %xmm1
divsd %xmm4, %xmm1
movsd %xmm1, 56(%rdi)
mulsd %xmm7, %xmm0
mulsd %xmm6, %xmm5
subsd %xmm5, %xmm0
divsd %xmm4, %xmm0
movsd %xmm0, 64(%rdi)
addq $72, %rax
addq $8, %rdx
addq $72, %rdi
cmpq %rdx, %rcx
jne .L79
.L75:
leaq 1472(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $768, %edx
leaq _ZL3AVG(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
je .L80
leaq 1472(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $768, %edx
leaq _ZL3AVG(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L80:
leaq 2240(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $2304, %edx
leaq _ZL3COV(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
je .L81
leaq 2240(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $2304, %edx
leaq _ZL3COV(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L81:
leaq 4544(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $2304, %edx
leaq _ZL7COV_INV(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
je .L82
leaq 4544(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $2304, %edx
leaq _ZL7COV_INV(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L82:
leaq 176(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $256, %edx
leaq _ZL4DETS(%rip), %rdi
call cudaMemcpyToSymbol@PLT
testl %eax, %eax
je .L83
leaq 176(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $256, %edx
leaq _ZL4DETS(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L83:
movslq 36(%rsp), %rsi
movslq 32(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
je .L84
movslq 36(%rsp), %rsi
movslq 32(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L84:
movslq 36(%rsp), %rdx
movslq 32(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L85
movslq 36(%rsp), %rdx
movslq 32(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L85:
movl $16, 68(%rsp)
movl $16, 72(%rsp)
movl $16, 56(%rsp)
movl $16, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movl 40(%rsp), %ecx
movl 36(%rsp), %edx
movl 32(%rsp), %esi
movq 48(%rsp), %rdi
call _Z34__device_stub__Z6kernelP6uchar4iiiP6uchar4iii
.L86:
movslq 36(%rsp), %rdx
movslq 32(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
je .L87
movslq 36(%rsp), %rdx
movslq 32(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L87:
leaq 144(%rsp), %rsi
leaq 432(%rsp), %rdi
movl $20, %edx
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1ERKNSt7__cxx1112basic_stringIcS1_SaIcEEESt13_Ios_Openmode@PLT
.LEHE2:
leaq 544(%rsp), %rdi
call _ZNKSt12__basic_fileIcE7is_openEv@PLT
movl $1, %ebp
testb %al, %al
jne .L132
.L88:
leaq 432(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
jmp .L54
.L132:
leaq 32(%rsp), %rsi
leaq 432(%rsp), %rdi
movl $4, %edx
.LEHB3:
call _ZNSo5writeEPKcl@PLT
leaq 36(%rsp), %rsi
leaq 432(%rsp), %rdi
movl $4, %edx
call _ZNSo5writeEPKcl@PLT
movl 32(%rsp), %edx
imull 36(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
leaq 432(%rsp), %rdi
movq %rbx, %rsi
call _ZNSo5writeEPKcl@PLT
leaq 432(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L133
movq %rbx, %rdi
call _ZdaPv@PLT
movl $0, %ebp
jmp .L88
.L133:
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE3:
movl $0, %edi
call exit@PLT
.L103:
endbr64
movq %rax, %rbx
leaq 432(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
.L91:
leaq 944(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L92:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIS_I4int2SaIS0_EESaIS2_EED1Ev
.L93:
leaq 144(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 6856(%rsp), %rax
subq %fs:40, %rax
je .L94
call __stack_chk_fail@PLT
.L101:
endbr64
movq %rax, %rbx
jmp .L92
.L94:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L46:
movq $0, 80(%rsp)
movq $0, 96(%rsp)
movq $0, 8(%rsp)
movl $0, %edx
jmp .L95
.L127:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4165:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4165:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4165-.LLSDACSB4165
.LLSDACSB4165:
.uleb128 .LEHB0-.LFB4165
.uleb128 .LEHE0-.LEHB0
.uleb128 .L100-.LFB4165
.uleb128 0
.uleb128 .LEHB1-.LFB4165
.uleb128 .LEHE1-.LEHB1
.uleb128 .L101-.LFB4165
.uleb128 0
.uleb128 .LEHB2-.LFB4165
.uleb128 .LEHE2-.LEHB2
.uleb128 .L102-.LFB4165
.uleb128 0
.uleb128 .LEHB3-.LFB4165
.uleb128 .LEHE3-.LEHB3
.uleb128 .L103-.LFB4165
.uleb128 0
.uleb128 .LEHB4-.LFB4165
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4165:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL4DETS
.comm _ZL4DETS,256,32
.local _ZL7COV_INV
.comm _ZL7COV_INV,2304,32
.local _ZL3COV
.comm _ZL3COV,2304,32
.local _ZL3AVG
.comm _ZL3AVG,768,32
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <fstream>
#include <vector>
#include <cmath>
#define HANDLE_ERROR(err) \
do { if (err != cudaSuccess) { printf("ERROR: %s\n", cudaGetErrorString(err)); exit(0);} } while (0)
__constant__ double AVG[32][3];
__constant__ double COV[32][3][3];
__constant__ double COV_INV[32][3][3];
__constant__ double DETS[32];
__device__ double func(uchar4 p, int i)
{
double res = 0.0, p_avg[3], tmp[3];
for (int j = 0; j < 3; ++j) {
p_avg[j] = 0.0;
tmp[j] = 0.0;
}
p_avg[0] = p.x - AVG[i][0];
p_avg[1] = p.y - AVG[i][1];
p_avg[2] = p.z - AVG[i][2];
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
tmp[j] += -p_avg[k] * COV_INV[i][k][j];
}
res += tmp[j] * p_avg[j];
}
res -= std::log(std::abs(DETS[i]));
return res;
}
__device__ int getClass(uchar4 pixel, int nc)
{
double res[32];
for (int i = 0; i < nc; ++i) {
res[i] = func(pixel, i);
}
double maxEl = res[0];
int idx = 0;
for (int i = 0; i < nc; ++i) {
if (res[i] > maxEl) {
maxEl = res[i];
idx = i;
}
}
return idx;
}
__global__ void kernel(uchar4 *dst, int w, int h, int nc)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int offsetx = blockDim.x * gridDim.x;
int offsety = blockDim.y * gridDim.y;
for (int x = idx; x < w; x += offsetx) {
for (int y = idy; y < h; y += offsety) {
dst[x + y * w].w = getClass(dst[x + y * w], nc);
}
}
}
int main()
{
std::string input, output;
int w, h, nc, np;
uchar4 *data;
std::cin >> input >> output >> nc;
std::vector<std::vector<int2>> classes(nc);
for (int i = 0; i < nc; ++i) {
std::cin >> np;
classes[i].resize(np);
for (int j = 0; j < np; ++j) {
std::cin >> classes[i][j].x >> classes[i][j].y;
}
}
std::ifstream fsIn(input, std::ios::in | std::ios::binary);
if (fsIn.is_open()) {
fsIn.read((char *)&w, sizeof(w));
fsIn.read((char *)&h, sizeof(h));
data = new uchar4[w * h];
fsIn.read((char *)data, w * h * sizeof(data[0]));
fsIn.close();
} else {
return 1;
}
// дальше начинаются интересные вещи
double avg[32][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
avg[i][j] = 0.0;
}
}
for (int i = 0; i < nc; ++i) {
int np = classes[i].size();
for (int j = 0; j < np; ++j) {
int x = classes[i][j].x;
int y = classes[i][j].y;
uchar4 curPixel = data[x + y * w];
avg[i][0] += curPixel.x;
avg[i][1] += curPixel.y;
avg[i][2] += curPixel.z;
}
for (int k = 0; k < 3; ++k) {
avg[i][k] /= np;
}
}
double cov[32][3][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
cov[i][j][k] = 0.0;
}
}
}
for (int i = 0; i < nc; ++i) {
np = classes[i].size();
for (int j = 0; j < np; ++j) {
double tmp[3];
int x = classes[i][j].x;
int y = classes[i][j].y;
uchar4 curPixel = data[x + y * w];
tmp[0] = curPixel.x - avg[i][0];
tmp[1] = curPixel.y - avg[i][1];
tmp[2] = curPixel.z - avg[i][2];
for (int k = 0; k < 3; ++k) {
for (int l = 0; l < 3; ++l) {
cov[i][k][l] += tmp[k] * tmp[l];
}
}
}
for (int k = 0; k < 3; ++k) {
for (int l = 0; l < 3; ++l) {
cov[i][k][l] /= np - 1;
}
}
}
double cov_inv[32][3][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
cov_inv[i][j][k] = 0.0;
}
}
}
double dets[32];
for (int i = 0; i < nc; ++i) {
double det = 0;
for (int j = 0; j < 3; ++j) {
det += cov[i][0][j] * (cov[i][1][(j + 1) % 3] * cov[i][2][(j + 2) % 3] - cov[i][1][(j + 2) % 3] * cov[i][2][(j + 1) % 3]);
}
dets[i] = det;
}
// извините
for (int i = 0; i < nc; ++i) {
cov_inv[i][0][0] = (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) / dets[i];
cov_inv[i][0][1] = (cov[i][0][2] * cov[i][2][1] - cov[i][0][1] * cov[i][2][2]) / dets[i];
cov_inv[i][0][2] = (cov[i][0][1] * cov[i][1][2] - cov[i][0][2] * cov[i][1][1]) / dets[i];
cov_inv[i][1][0] = (cov[i][1][2] * cov[i][2][0] - cov[i][1][0] * cov[i][2][2]) / dets[i];
cov_inv[i][1][1] = (cov[i][0][0] * cov[i][2][2] - cov[i][0][2] * cov[i][2][0]) / dets[i];
cov_inv[i][1][2] = (cov[i][1][0] * cov[i][0][2] - cov[i][0][0] * cov[i][1][2]) / dets[i];
cov_inv[i][2][0] = (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]) / dets[i];
cov_inv[i][2][1] = (cov[i][2][0] * cov[i][0][1] - cov[i][0][0] * cov[i][2][1]) / dets[i];
cov_inv[i][2][2] = (cov[i][0][0] * cov[i][1][1] - cov[i][1][0] * cov[i][0][1]) / dets[i];
}
HANDLE_ERROR(cudaMemcpyToSymbol(AVG, avg, sizeof(double) * 32 * 3));
HANDLE_ERROR(cudaMemcpyToSymbol(COV, cov, sizeof(double) * 32 * 3 * 3));
HANDLE_ERROR(cudaMemcpyToSymbol(COV_INV, cov_inv, sizeof(double) * 32 * 3 * 3));
HANDLE_ERROR(cudaMemcpyToSymbol(DETS, dets, sizeof(double) * 32));
uchar4 *dev_data;
HANDLE_ERROR(cudaMalloc(&dev_data, sizeof(uchar4) * h * w));
HANDLE_ERROR(cudaMemcpy(dev_data, data, sizeof(uchar4) * h * w, cudaMemcpyHostToDevice));
kernel<<<dim3(16, 16), dim3(16, 16)>>>(dev_data, w, h, nc);
HANDLE_ERROR(cudaMemcpy(data, dev_data, sizeof(uchar4) * h * w, cudaMemcpyDeviceToHost));
std::ofstream fsOut(output, std::ios::out | std::ios::binary);
if (fsOut.is_open()) {
fsOut.write((char *)&w, sizeof(w));
fsOut.write((char *)&h, sizeof(h));
fsOut.write((char *)data, w * h * sizeof(data[0]));
fsOut.close();
} else {
return 1;
}
HANDLE_ERROR(cudaFree(dev_data));
delete[] data;
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <vector>
#include <cmath>
#define HANDLE_ERROR(err) \
do { if (err != hipSuccess) { printf("ERROR: %s\n", hipGetErrorString(err)); exit(0);} } while (0)
__constant__ double AVG[32][3];
__constant__ double COV[32][3][3];
__constant__ double COV_INV[32][3][3];
__constant__ double DETS[32];
__device__ double func(uchar4 p, int i)
{
double res = 0.0, p_avg[3], tmp[3];
for (int j = 0; j < 3; ++j) {
p_avg[j] = 0.0;
tmp[j] = 0.0;
}
p_avg[0] = p.x - AVG[i][0];
p_avg[1] = p.y - AVG[i][1];
p_avg[2] = p.z - AVG[i][2];
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
tmp[j] += -p_avg[k] * COV_INV[i][k][j];
}
res += tmp[j] * p_avg[j];
}
res -= std::log(std::abs(DETS[i]));
return res;
}
__device__ int getClass(uchar4 pixel, int nc)
{
double res[32];
for (int i = 0; i < nc; ++i) {
res[i] = func(pixel, i);
}
double maxEl = res[0];
int idx = 0;
for (int i = 0; i < nc; ++i) {
if (res[i] > maxEl) {
maxEl = res[i];
idx = i;
}
}
return idx;
}
__global__ void kernel(uchar4 *dst, int w, int h, int nc)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int offsetx = blockDim.x * gridDim.x;
int offsety = blockDim.y * gridDim.y;
for (int x = idx; x < w; x += offsetx) {
for (int y = idy; y < h; y += offsety) {
dst[x + y * w].w = getClass(dst[x + y * w], nc);
}
}
}
int main()
{
std::string input, output;
int w, h, nc, np;
uchar4 *data;
std::cin >> input >> output >> nc;
std::vector<std::vector<int2>> classes(nc);
for (int i = 0; i < nc; ++i) {
std::cin >> np;
classes[i].resize(np);
for (int j = 0; j < np; ++j) {
std::cin >> classes[i][j].x >> classes[i][j].y;
}
}
std::ifstream fsIn(input, std::ios::in | std::ios::binary);
if (fsIn.is_open()) {
fsIn.read((char *)&w, sizeof(w));
fsIn.read((char *)&h, sizeof(h));
data = new uchar4[w * h];
fsIn.read((char *)data, w * h * sizeof(data[0]));
fsIn.close();
} else {
return 1;
}
// дальше начинаются интересные вещи
double avg[32][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
avg[i][j] = 0.0;
}
}
for (int i = 0; i < nc; ++i) {
int np = classes[i].size();
for (int j = 0; j < np; ++j) {
int x = classes[i][j].x;
int y = classes[i][j].y;
uchar4 curPixel = data[x + y * w];
avg[i][0] += curPixel.x;
avg[i][1] += curPixel.y;
avg[i][2] += curPixel.z;
}
for (int k = 0; k < 3; ++k) {
avg[i][k] /= np;
}
}
double cov[32][3][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
cov[i][j][k] = 0.0;
}
}
}
for (int i = 0; i < nc; ++i) {
np = classes[i].size();
for (int j = 0; j < np; ++j) {
double tmp[3];
int x = classes[i][j].x;
int y = classes[i][j].y;
uchar4 curPixel = data[x + y * w];
tmp[0] = curPixel.x - avg[i][0];
tmp[1] = curPixel.y - avg[i][1];
tmp[2] = curPixel.z - avg[i][2];
for (int k = 0; k < 3; ++k) {
for (int l = 0; l < 3; ++l) {
cov[i][k][l] += tmp[k] * tmp[l];
}
}
}
for (int k = 0; k < 3; ++k) {
for (int l = 0; l < 3; ++l) {
cov[i][k][l] /= np - 1;
}
}
}
double cov_inv[32][3][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
cov_inv[i][j][k] = 0.0;
}
}
}
double dets[32];
for (int i = 0; i < nc; ++i) {
double det = 0;
for (int j = 0; j < 3; ++j) {
det += cov[i][0][j] * (cov[i][1][(j + 1) % 3] * cov[i][2][(j + 2) % 3] - cov[i][1][(j + 2) % 3] * cov[i][2][(j + 1) % 3]);
}
dets[i] = det;
}
// извините
for (int i = 0; i < nc; ++i) {
cov_inv[i][0][0] = (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) / dets[i];
cov_inv[i][0][1] = (cov[i][0][2] * cov[i][2][1] - cov[i][0][1] * cov[i][2][2]) / dets[i];
cov_inv[i][0][2] = (cov[i][0][1] * cov[i][1][2] - cov[i][0][2] * cov[i][1][1]) / dets[i];
cov_inv[i][1][0] = (cov[i][1][2] * cov[i][2][0] - cov[i][1][0] * cov[i][2][2]) / dets[i];
cov_inv[i][1][1] = (cov[i][0][0] * cov[i][2][2] - cov[i][0][2] * cov[i][2][0]) / dets[i];
cov_inv[i][1][2] = (cov[i][1][0] * cov[i][0][2] - cov[i][0][0] * cov[i][1][2]) / dets[i];
cov_inv[i][2][0] = (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]) / dets[i];
cov_inv[i][2][1] = (cov[i][2][0] * cov[i][0][1] - cov[i][0][0] * cov[i][2][1]) / dets[i];
cov_inv[i][2][2] = (cov[i][0][0] * cov[i][1][1] - cov[i][1][0] * cov[i][0][1]) / dets[i];
}
HANDLE_ERROR(hipMemcpyToSymbol(HIP_SYMBOL(AVG), avg, sizeof(double) * 32 * 3));
HANDLE_ERROR(hipMemcpyToSymbol(HIP_SYMBOL(COV), cov, sizeof(double) * 32 * 3 * 3));
HANDLE_ERROR(hipMemcpyToSymbol(HIP_SYMBOL(COV_INV), cov_inv, sizeof(double) * 32 * 3 * 3));
HANDLE_ERROR(hipMemcpyToSymbol(HIP_SYMBOL(DETS), dets, sizeof(double) * 32));
uchar4 *dev_data;
HANDLE_ERROR(hipMalloc(&dev_data, sizeof(uchar4) * h * w));
HANDLE_ERROR(hipMemcpy(dev_data, data, sizeof(uchar4) * h * w, hipMemcpyHostToDevice));
kernel<<<dim3(16, 16), dim3(16, 16)>>>(dev_data, w, h, nc);
HANDLE_ERROR(hipMemcpy(data, dev_data, sizeof(uchar4) * h * w, hipMemcpyDeviceToHost));
std::ofstream fsOut(output, std::ios::out | std::ios::binary);
if (fsOut.is_open()) {
fsOut.write((char *)&w, sizeof(w));
fsOut.write((char *)&h, sizeof(h));
fsOut.write((char *)data, w * h * sizeof(data[0]));
fsOut.close();
} else {
return 1;
}
HANDLE_ERROR(hipFree(dev_data));
delete[] data;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <vector>
#include <cmath>
#define HANDLE_ERROR(err) \
do { if (err != hipSuccess) { printf("ERROR: %s\n", hipGetErrorString(err)); exit(0);} } while (0)
__constant__ double AVG[32][3];
__constant__ double COV[32][3][3];
__constant__ double COV_INV[32][3][3];
__constant__ double DETS[32];
__device__ double func(uchar4 p, int i)
{
double res = 0.0, p_avg[3], tmp[3];
for (int j = 0; j < 3; ++j) {
p_avg[j] = 0.0;
tmp[j] = 0.0;
}
p_avg[0] = p.x - AVG[i][0];
p_avg[1] = p.y - AVG[i][1];
p_avg[2] = p.z - AVG[i][2];
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
tmp[j] += -p_avg[k] * COV_INV[i][k][j];
}
res += tmp[j] * p_avg[j];
}
res -= std::log(std::abs(DETS[i]));
return res;
}
__device__ int getClass(uchar4 pixel, int nc)
{
double res[32];
for (int i = 0; i < nc; ++i) {
res[i] = func(pixel, i);
}
double maxEl = res[0];
int idx = 0;
for (int i = 0; i < nc; ++i) {
if (res[i] > maxEl) {
maxEl = res[i];
idx = i;
}
}
return idx;
}
__global__ void kernel(uchar4 *dst, int w, int h, int nc)
{
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int idy = blockDim.y * blockIdx.y + threadIdx.y;
int offsetx = blockDim.x * gridDim.x;
int offsety = blockDim.y * gridDim.y;
for (int x = idx; x < w; x += offsetx) {
for (int y = idy; y < h; y += offsety) {
dst[x + y * w].w = getClass(dst[x + y * w], nc);
}
}
}
int main()
{
std::string input, output;
int w, h, nc, np;
uchar4 *data;
std::cin >> input >> output >> nc;
std::vector<std::vector<int2>> classes(nc);
for (int i = 0; i < nc; ++i) {
std::cin >> np;
classes[i].resize(np);
for (int j = 0; j < np; ++j) {
std::cin >> classes[i][j].x >> classes[i][j].y;
}
}
std::ifstream fsIn(input, std::ios::in | std::ios::binary);
if (fsIn.is_open()) {
fsIn.read((char *)&w, sizeof(w));
fsIn.read((char *)&h, sizeof(h));
data = new uchar4[w * h];
fsIn.read((char *)data, w * h * sizeof(data[0]));
fsIn.close();
} else {
return 1;
}
// дальше начинаются интересные вещи
double avg[32][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
avg[i][j] = 0.0;
}
}
for (int i = 0; i < nc; ++i) {
int np = classes[i].size();
for (int j = 0; j < np; ++j) {
int x = classes[i][j].x;
int y = classes[i][j].y;
uchar4 curPixel = data[x + y * w];
avg[i][0] += curPixel.x;
avg[i][1] += curPixel.y;
avg[i][2] += curPixel.z;
}
for (int k = 0; k < 3; ++k) {
avg[i][k] /= np;
}
}
double cov[32][3][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
cov[i][j][k] = 0.0;
}
}
}
for (int i = 0; i < nc; ++i) {
np = classes[i].size();
for (int j = 0; j < np; ++j) {
double tmp[3];
int x = classes[i][j].x;
int y = classes[i][j].y;
uchar4 curPixel = data[x + y * w];
tmp[0] = curPixel.x - avg[i][0];
tmp[1] = curPixel.y - avg[i][1];
tmp[2] = curPixel.z - avg[i][2];
for (int k = 0; k < 3; ++k) {
for (int l = 0; l < 3; ++l) {
cov[i][k][l] += tmp[k] * tmp[l];
}
}
}
for (int k = 0; k < 3; ++k) {
for (int l = 0; l < 3; ++l) {
cov[i][k][l] /= np - 1;
}
}
}
double cov_inv[32][3][3];
for (int i = 0; i < 32; ++i) {
for (int j = 0; j < 3; ++j) {
for (int k = 0; k < 3; ++k) {
cov_inv[i][j][k] = 0.0;
}
}
}
double dets[32];
for (int i = 0; i < nc; ++i) {
double det = 0;
for (int j = 0; j < 3; ++j) {
det += cov[i][0][j] * (cov[i][1][(j + 1) % 3] * cov[i][2][(j + 2) % 3] - cov[i][1][(j + 2) % 3] * cov[i][2][(j + 1) % 3]);
}
dets[i] = det;
}
// извините
for (int i = 0; i < nc; ++i) {
cov_inv[i][0][0] = (cov[i][1][1] * cov[i][2][2] - cov[i][2][1] * cov[i][1][2]) / dets[i];
cov_inv[i][0][1] = (cov[i][0][2] * cov[i][2][1] - cov[i][0][1] * cov[i][2][2]) / dets[i];
cov_inv[i][0][2] = (cov[i][0][1] * cov[i][1][2] - cov[i][0][2] * cov[i][1][1]) / dets[i];
cov_inv[i][1][0] = (cov[i][1][2] * cov[i][2][0] - cov[i][1][0] * cov[i][2][2]) / dets[i];
cov_inv[i][1][1] = (cov[i][0][0] * cov[i][2][2] - cov[i][0][2] * cov[i][2][0]) / dets[i];
cov_inv[i][1][2] = (cov[i][1][0] * cov[i][0][2] - cov[i][0][0] * cov[i][1][2]) / dets[i];
cov_inv[i][2][0] = (cov[i][1][0] * cov[i][2][1] - cov[i][2][0] * cov[i][1][1]) / dets[i];
cov_inv[i][2][1] = (cov[i][2][0] * cov[i][0][1] - cov[i][0][0] * cov[i][2][1]) / dets[i];
cov_inv[i][2][2] = (cov[i][0][0] * cov[i][1][1] - cov[i][1][0] * cov[i][0][1]) / dets[i];
}
HANDLE_ERROR(hipMemcpyToSymbol(HIP_SYMBOL(AVG), avg, sizeof(double) * 32 * 3));
HANDLE_ERROR(hipMemcpyToSymbol(HIP_SYMBOL(COV), cov, sizeof(double) * 32 * 3 * 3));
HANDLE_ERROR(hipMemcpyToSymbol(HIP_SYMBOL(COV_INV), cov_inv, sizeof(double) * 32 * 3 * 3));
HANDLE_ERROR(hipMemcpyToSymbol(HIP_SYMBOL(DETS), dets, sizeof(double) * 32));
uchar4 *dev_data;
HANDLE_ERROR(hipMalloc(&dev_data, sizeof(uchar4) * h * w));
HANDLE_ERROR(hipMemcpy(dev_data, data, sizeof(uchar4) * h * w, hipMemcpyHostToDevice));
kernel<<<dim3(16, 16), dim3(16, 16)>>>(dev_data, w, h, nc);
HANDLE_ERROR(hipMemcpy(data, dev_data, sizeof(uchar4) * h * w, hipMemcpyDeviceToHost));
std::ofstream fsOut(output, std::ios::out | std::ios::binary);
if (fsOut.is_open()) {
fsOut.write((char *)&w, sizeof(w));
fsOut.write((char *)&h, sizeof(h));
fsOut.write((char *)data, w * h * sizeof(data[0]));
fsOut.close();
} else {
return 1;
}
HANDLE_ERROR(hipFree(dev_data));
delete[] data;
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelP15HIP_vector_typeIhLj4EEiii
.globl _Z6kernelP15HIP_vector_typeIhLj4EEiii
.p2align 8
.type _Z6kernelP15HIP_vector_typeIhLj4EEiii,@function
_Z6kernelP15HIP_vector_typeIhLj4EEiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s33, s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[6:7], null, s14, s4, v[1:2]
v_cmpx_gt_i32_e64 s33, v6
s_cbranch_execz .LBB0_19
s_clause 0x1
s_load_b32 s5, s[2:3], 0xc
s_load_b64 s[2:3], s[2:3], 0x0
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0xc
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s17, 0
s_mov_b32 s19, 0x3fe55555
s_mov_b32 s18, 0x55555555
s_mov_b32 s21, 0x3fc38538
s_mov_b32 s20, 0x6b47b09a
s_mov_b32 s23, 0x3fc3ab76
s_mov_b32 s22, 0xbf559e2b
s_mov_b32 s25, 0x3fc7474d
s_mov_b32 s24, 0xd7f4df2e
s_mov_b32 s27, 0x3fcc71c0
s_mov_b32 s26, 0x16291751
s_mov_b32 s29, 0x3fd24924
s_mov_b32 s28, 0x9b27acf1
s_mov_b32 s31, 0x3fd99999
s_mov_b32 s30, 0x998ef7b6
s_waitcnt lgkmcnt(0)
s_lshr_b32 s0, s5, 16
s_mov_b32 s14, 0x55555780
v_mad_u64_u32 v[7:8], null, s15, s0, v[0:1]
s_mul_i32 s41, s3, s0
s_cmp_gt_i32 s13, 0
s_mov_b32 s35, 0x3fe62e42
s_mul_i32 s40, s2, s4
s_cselect_b32 s42, -1, 0
s_mov_b32 s34, 0xfefa39ef
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s12, v7
s_mov_b32 s37, 0x3c7abc9e
s_mov_b32 s36, 0x3b39803f
s_mov_b32 s43, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s44
v_add_nc_u32_e32 v6, s40, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s33, v6
s_or_b32 s43, vcc_lo, s43
s_and_not1_b32 exec_lo, exec_lo, s43
s_cbranch_execz .LBB0_19
.LBB0_3:
s_and_saveexec_b32 s44, s0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v26, v7
s_mov_b32 s45, 0
s_branch .LBB0_7
.LBB0_5:
v_mov_b32_e32 v2, 0
.LBB0_6:
v_add_nc_u32_e32 v26, s41, v26
global_store_b8 v[8:9], v2, off offset:3
v_cmp_le_i32_e32 vcc_lo, s12, v26
s_or_b32 s45, vcc_lo, s45
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s45
s_cbranch_execz .LBB0_2
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v26, s33, v[6:7]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v8, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v1, vcc_lo
s_and_not1_b32 vcc_lo, exec_lo, s42
s_cbranch_vccnz .LBB0_5
global_load_b32 v0, v[8:9], off
s_mov_b32 s16, 0
s_getpc_b64 s[38:39]
s_add_u32 s38, s38, COV_INV@rel32@lo+4
s_addc_u32 s39, s39, COV_INV@rel32@hi+12
s_waitcnt vmcnt(0)
v_and_b32_e32 v1, 0xff, v0
v_bfe_u32 v2, v0, 8, 8
v_bfe_u32 v0, v0, 16, 8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[10:11], v1
v_cvt_f64_i32_e32 v[12:13], v2
s_delay_alu instid0(VALU_DEP_3)
v_cvt_f64_i32_e32 v[14:15], v0
.LBB0_9:
s_mov_b64 s[2:3], 0
.LBB0_10:
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 2
s_cselect_b32 s9, 0, s9
s_cselect_b32 s8, 0, s8
s_cmp_eq_u32 s2, 1
s_cselect_b32 s7, 0, s7
s_cselect_b32 s6, 0, s6
s_cmp_eq_u32 s2, 0
s_cselect_b32 s5, 0, s5
s_cselect_b32 s4, 0, s4
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 3
s_cbranch_scc0 .LBB0_10
s_mul_i32 s1, s16, 24
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, AVG@rel32@lo+4
s_addc_u32 s3, s3, AVG@rel32@hi+12
s_mul_hi_u32 s15, s16, 24
s_add_u32 s2, s1, s2
s_addc_u32 s3, s15, s3
s_getpc_b64 s[46:47]
s_add_u32 s46, s46, AVG@rel32@lo+12
s_addc_u32 s47, s47, AVG@rel32@hi+20
s_add_u32 s46, s1, s46
s_addc_u32 s47, s15, s47
s_getpc_b64 s[48:49]
s_add_u32 s48, s48, AVG@rel32@lo+20
s_addc_u32 s49, s49, AVG@rel32@hi+28
s_add_u32 s48, s1, s48
s_addc_u32 s49, s15, s49
s_clause 0x2
s_load_b64 s[2:3], s[2:3], 0x0
s_load_b64 s[46:47], s[46:47], 0x0
s_load_b64 s[48:49], s[48:49], 0x0
v_mov_b32_e32 v16, 0
v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v0, s4
v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
v_dual_mov_b32 v3, s7 :: v_dual_mov_b32 v4, s8
v_mov_b32_e32 v5, s9
s_mov_b64 s[4:5], s[38:39]
s_waitcnt lgkmcnt(0)
v_add_f64 v[18:19], v[10:11], -s[2:3]
v_add_f64 v[20:21], v[12:13], -s[46:47]
v_add_f64 v[22:23], v[14:15], -s[48:49]
s_mov_b32 s3, 0
.LBB0_12:
s_mov_b64 s[6:7], 0
s_mov_b64 s[8:9], s[4:5]
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_13:
s_load_b64 s[46:47], s[8:9], 0x0
s_cmp_eq_u32 s6, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s6, 2
s_delay_alu instid0(VALU_DEP_2)
v_dual_cndmask_b32 v24, v19, v21 :: v_dual_cndmask_b32 v27, v18, v20
s_cselect_b32 s1, -1, 0
s_cmp_eq_u32 s3, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s3, 2
v_dual_cndmask_b32 v28, v1, v3 :: v_dual_cndmask_b32 v29, v0, v2
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v25, v24, v23, s1
v_cndmask_b32_e64 v24, v27, v22, s1
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v28, v28, v5, s2
v_cndmask_b32_e64 v27, v29, v4, s2
s_cmp_eq_u32 s3, 0
s_cselect_b32 s1, -1, 0
s_add_u32 s6, s6, 1
s_waitcnt lgkmcnt(0)
v_fma_f64 v[24:25], -v[24:25], s[46:47], v[27:28]
s_addc_u32 s7, s7, 0
s_add_u32 s8, s8, 24
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s6, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, v5, v25, s2
v_cndmask_b32_e64 v4, v4, v24, s2
v_dual_cndmask_b32 v3, v3, v25 :: v_dual_cndmask_b32 v2, v2, v24
v_cndmask_b32_e64 v1, v1, v25, s1
v_cndmask_b32_e64 v0, v0, v24, s1
s_cbranch_scc0 .LBB0_13
s_set_inst_prefetch_distance 0x2
s_cmp_eq_u32 s3, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s3, 2
v_cndmask_b32_e32 v27, v19, v21, vcc_lo
v_cndmask_b32_e32 v29, v18, v20, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_add_i32 s3, s3, 1
s_add_u32 s4, s4, 8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v28, v27, v23 :: v_dual_cndmask_b32 v27, v29, v22
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s3, 3
v_fma_f64 v[16:17], v[27:28], v[24:25], v[16:17]
s_cbranch_scc0 .LBB0_12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, DETS@rel32@lo+4
s_addc_u32 s3, s3, DETS@rel32@hi+12
s_lshl_b64 s[4:5], s[16:17], 3
s_mov_b32 s15, s19
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_frexp_mant_f64_e64 v[0:1], |s[2:3]|
v_cmp_class_f64_e64 s1, s[2:3], 0x204
s_and_b32 s4, s3, 0x7fffffff
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[18:19], v[0:1]
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
v_ldexp_f64 v[0:1], v[0:1], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[0:1], 1.0
v_add_f64 v[20:21], v[0:1], -1.0
v_rcp_f64_e32 v[4:5], v[2:3]
v_add_f64 v[22:23], v[2:3], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], -v[22:23]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[18:19], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[18:19], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[18:19], v[20:21], v[4:5]
v_mul_f64 v[24:25], v[2:3], v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[18:19], v[2:3], -v[24:25]
v_fma_f64 v[0:1], v[18:19], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[24:25], v[0:1]
v_add_f64 v[22:23], v[20:21], -v[2:3]
v_add_f64 v[24:25], v[2:3], -v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[20:21], v[20:21], -v[22:23]
v_add_f64 v[0:1], v[24:25], -v[0:1]
v_frexp_exp_i32_f64_e32 v24, s[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[20:21], -v[2:3]
v_add_f64 v[0:1], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[22:23], v[0:1]
v_mul_f64 v[0:1], v[4:5], v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[18:19], v[0:1]
v_mul_f64 v[4:5], v[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], v[4:5], s[22:23], s[20:21]
v_mul_f64 v[22:23], v[2:3], v[4:5]
v_fma_f64 v[20:21], v[4:5], v[20:21], s[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], v[4:5], v[20:21], s[26:27]
v_fma_f64 v[20:21], v[4:5], v[20:21], s[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[20:21], v[4:5], v[20:21], s[30:31]
v_fma_f64 v[4:5], v[4:5], v[20:21], s[14:15]
v_ldexp_f64 v[20:21], v[2:3], 1
v_add_f64 v[2:3], v[2:3], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f64 v[4:5], v[22:23], v[4:5]
v_subrev_co_ci_u32_e32 v22, vcc_lo, 0, v24, vcc_lo
v_add_f64 v[0:1], v[0:1], -v[2:3]
v_cmp_neq_f64_e64 vcc_lo, s[2:3], 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cvt_f64_i32_e32 v[22:23], v22
v_add_f64 v[18:19], v[20:21], v[4:5]
v_ldexp_f64 v[0:1], v[0:1], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f64 v[24:25], v[22:23], s[34:35]
v_add_f64 v[2:3], v[18:19], -v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], v[22:23], s[34:35], -v[24:25]
v_add_f64 v[2:3], v[4:5], -v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[4:5], v[22:23], s[36:37], v[20:21]
v_add_f64 v[0:1], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[24:25], v[4:5]
v_add_f64 v[20:21], v[18:19], v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[24:25], v[2:3], -v[24:25]
v_add_f64 v[22:23], v[2:3], v[20:21]
v_add_f64 v[18:19], v[20:21], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], -v[24:25]
v_add_f64 v[27:28], v[22:23], -v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[0:1], v[0:1], -v[18:19]
v_add_f64 v[29:30], v[22:23], -v[27:28]
v_add_f64 v[18:19], v[20:21], -v[27:28]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[20:21], v[4:5], v[0:1]
v_add_f64 v[2:3], v[2:3], -v[29:30]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[2:3], v[18:19], v[2:3]
v_add_f64 v[18:19], v[20:21], -v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[2:3], v[20:21], v[2:3]
v_add_f64 v[20:21], v[20:21], -v[18:19]
v_add_f64 v[0:1], v[0:1], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[24:25], v[22:23], v[2:3]
v_add_f64 v[4:5], v[4:5], -v[20:21]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[18:19], v[24:25], -v[22:23]
v_add_f64 v[0:1], v[0:1], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], -v[18:19]
v_add_f64 v[0:1], v[0:1], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[24:25], v[0:1]
v_cndmask_b32_e64 v0, v0, s2, s1
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v1, v1, s4, s1
s_lshl_b32 s1, s16, 3
s_add_i32 s16, s16, 1
s_add_i32 s1, s1, 16
v_cndmask_b32_e32 v0, 0, v0, vcc_lo
v_cndmask_b32_e32 v1, 0xfff00000, v1, vcc_lo
s_add_u32 s38, s38, 0x48
s_addc_u32 s39, s39, 0
s_cmp_eq_u32 s16, s13
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[16:17], -v[0:1]
scratch_store_b64 off, v[0:1], s1
s_cbranch_scc0 .LBB0_9
s_and_not1_b32 vcc_lo, exec_lo, s42
s_cbranch_vccnz .LBB0_5
scratch_load_b64 v[0:1], off, off offset:16
v_dual_mov_b32 v3, 16 :: v_dual_mov_b32 v2, 0
s_mov_b32 s1, 0
.LBB0_18:
scratch_load_b64 v[4:5], v3, off
s_waitcnt vmcnt(0)
v_cmp_gt_f64_e32 vcc_lo, v[4:5], v[0:1]
v_dual_cndmask_b32 v0, v0, v4 :: v_dual_add_nc_u32 v3, 8, v3
v_cndmask_b32_e32 v1, v1, v5, vcc_lo
v_cndmask_b32_e64 v2, v2, s1, vcc_lo
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s13, s1
s_cbranch_scc1 .LBB0_18
s_branch .LBB0_6
.LBB0_19:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelP15HIP_vector_typeIhLj4EEiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 272
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 31
.amdhsa_next_free_sgpr 50
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelP15HIP_vector_typeIhLj4EEiii, .Lfunc_end0-_Z6kernelP15HIP_vector_typeIhLj4EEiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected AVG
.type AVG,@object
.section .bss,"aw",@nobits
.globl AVG
.p2align 4, 0x0
AVG:
.zero 768
.size AVG, 768
.protected COV
.type COV,@object
.globl COV
.p2align 4, 0x0
COV:
.zero 2304
.size COV, 2304
.protected COV_INV
.type COV_INV,@object
.globl COV_INV
.p2align 4, 0x0
COV_INV:
.zero 2304
.size COV_INV, 2304
.protected DETS
.type DETS,@object
.globl DETS
.p2align 4, 0x0
DETS:
.zero 256
.size DETS, 256
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym AVG
.addrsig_sym COV
.addrsig_sym COV_INV
.addrsig_sym DETS
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelP15HIP_vector_typeIhLj4EEiii
.private_segment_fixed_size: 272
.sgpr_count: 52
.sgpr_spill_count: 0
.symbol: _Z6kernelP15HIP_vector_typeIhLj4EEiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 31
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
// A C / C++ program for Prim's Minimum
// Spanning Tree (MST) algorithm. The program is
// for adjacency matrix representation of the graph
#include <stdio.h>
#include <limits.h>
#include<stdbool.h>
#include <cstdlib>
#include <ctime>
#include <algorithm>
// Number of vertices in the graph
#define V 26
#define K 4
// A utility function to find the vertex with
// minimum key value, from the set of vertices
// not yet included in MST
int minKey(int key[], bool mstSet[])
{
// Initialize min value
int min = INT_MAX, min_index=0;
for (int v = 0; v < V; v++)
if (mstSet[v] == false && key[v] < min)
min = key[v], min_index = v;
return min_index;
}
/*
void sortGraph(int graph[V][V])
{
for (int xcord = 0; xcord<V; xcord++){
for (int ycord = xcord + 1; ycord<V; ycord++){
if (graph[xcord][0]>graph[ycord][0]){
int temp = graph[xcord][1];
int temp2 = graph[xcord][0];
graph[xcord][0] = graph[ycord][0];
graph[xcord][1] = graph[ycord][1];
graph[ycord][0] = temp2;
graph[ycord][1] = temp;
}
}
}
}
// A utility function to print the
// constructed MST stored in parent[]
void printMST(int parent[], int n, int graph[V][V])
{
//sortGraph(graph);
printf(" Edge \t\tWeight\n");
for (int i = 1; i < V; i++)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
}
*/
void kMstClusterPrint(int parent[], int n, int graph[V][V]) {
//k number of clusters, let k=5
int k[5] = { 0 };
//int clusterGraph[k][V][V];
//select random edges for removal
srand(time(NULL));
for (int i = 0; i < 5; i++) {
k[i] = (int)rand() % 26;
printf("%d\t", k[i]);
}
printf("\n\n");
bool flag = false;
for (int i = 1; i < V; i++) {
for (int j = 0; j < 5; j++)
{
if (i == k[j]) flag = true;
}
if (!flag)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
flag = false;
}
}
// Function to construct and print MST for
// a graph represented using adjacency
// matrix representation
void primMST(int graph[V][V])
{
// Array to store constructed MST
int parent[V];
// Key values used to pick minimum weight edge in cut
int key[V];
// To represent set of vertices not yet included in MST
bool mstSet[V];
// Initialize all keys as INFINITE
for (int i = 0; i < V; i++)
key[i] = INT_MAX, mstSet[i] = false;
// Always include first 1st vertex in MST.
// Make key 0 so that this vertex is picked as first vertex.
key[0] = 0;
parent[0] = -1; // First node is always root of MST
// The MST will have V vertices
for (int count = 0; count < V - 1; count++)
{
// Pick the minimum key vertex from the
// set of vertices not yet included in MST
int u = minKey(key, mstSet);
// Add the picked vertex to the MST Set
mstSet[u] = true;
// Update key value and parent index of
// the adjacent vertices of the picked vertex.
// Consider only those vertices which are not
// yet included in MST
for (int v = 0; v < V; v++)
// graph[u][v] is non zero only for adjacent vertices of m
// mstSet[v] is false for vertices not yet included in MST
// Update the key only if graph[u][v] is smaller than key[v]
if (graph[u][v] && mstSet[v] == false && graph[u][v] < key[v])
parent[v] = u, key[v] = graph[u][v];
}
// print the constructed MST
kMstClusterPrint(parent, V, graph);
//printMST(parent, V, graph);
}
// driver program to test above function
int main()
{
/* Let us create the following graph
2 3
(0)--(1)--(2)
| / \ |
6| 8/ \5 |7
| / \ |
(3)-------(4)
9 */
int graph[V][V] = {
{ 0, 4, 0, 0, 10, 0, 0, 0, 0, 9, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//a
{ 4, 0, 29, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//b
{ 0, 29, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//c
{ 0, 0, 8, 0, 6, 0, 0, 0, 0, 0, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//d
{ 10, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//e
{ 0, 0, 0, 0, 9, 0, 24, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//f
{ 0, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//g
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//h
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//i
{ 9, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//j
{ 0, 11, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0 },//k
{ 10, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0 },//l
{ 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0 },//m
{ 0, 0, 0, 0, 0, 12, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0 },//n
{ 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 17, 25, 0, 0 },//o
{ 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//p
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 9 },//q
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 24, 0, 0, 0, 0, 0, 0, 16 },//r
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 24, 0, 0, 13, 0, 0, 0, 0, 0 },//s
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13 },//t
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 13, 0, 0, 10, 0, 0, 0, 0 },//u
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 4, 0, 0, 23 },//v
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0 },//w
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//x
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30 },//y
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 16, 0, 13, 0, 23, 0, 0, 30, 0 }//z
};
// Print the solution
primMST(graph);
return 0;
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// A C / C++ program for Prim's Minimum
// Spanning Tree (MST) algorithm. The program is
// for adjacency matrix representation of the graph
#include <stdio.h>
#include <limits.h>
#include<stdbool.h>
#include <cstdlib>
#include <ctime>
#include <algorithm>
// Number of vertices in the graph
#define V 26
#define K 4
// A utility function to find the vertex with
// minimum key value, from the set of vertices
// not yet included in MST
int minKey(int key[], bool mstSet[])
{
// Initialize min value
int min = INT_MAX, min_index=0;
for (int v = 0; v < V; v++)
if (mstSet[v] == false && key[v] < min)
min = key[v], min_index = v;
return min_index;
}
/*
void sortGraph(int graph[V][V])
{
for (int xcord = 0; xcord<V; xcord++){
for (int ycord = xcord + 1; ycord<V; ycord++){
if (graph[xcord][0]>graph[ycord][0]){
int temp = graph[xcord][1];
int temp2 = graph[xcord][0];
graph[xcord][0] = graph[ycord][0];
graph[xcord][1] = graph[ycord][1];
graph[ycord][0] = temp2;
graph[ycord][1] = temp;
}
}
}
}
// A utility function to print the
// constructed MST stored in parent[]
void printMST(int parent[], int n, int graph[V][V])
{
//sortGraph(graph);
printf(" Edge \t\tWeight\n");
for (int i = 1; i < V; i++)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
}
*/
void kMstClusterPrint(int parent[], int n, int graph[V][V]) {
//k number of clusters, let k=5
int k[5] = { 0 };
//int clusterGraph[k][V][V];
//select random edges for removal
srand(time(NULL));
for (int i = 0; i < 5; i++) {
k[i] = (int)rand() % 26;
printf("%d\t", k[i]);
}
printf("\n\n");
bool flag = false;
for (int i = 1; i < V; i++) {
for (int j = 0; j < 5; j++)
{
if (i == k[j]) flag = true;
}
if (!flag)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
flag = false;
}
}
// Function to construct and print MST for
// a graph represented using adjacency
// matrix representation
void primMST(int graph[V][V])
{
// Array to store constructed MST
int parent[V];
// Key values used to pick minimum weight edge in cut
int key[V];
// To represent set of vertices not yet included in MST
bool mstSet[V];
// Initialize all keys as INFINITE
for (int i = 0; i < V; i++)
key[i] = INT_MAX, mstSet[i] = false;
// Always include first 1st vertex in MST.
// Make key 0 so that this vertex is picked as first vertex.
key[0] = 0;
parent[0] = -1; // First node is always root of MST
// The MST will have V vertices
for (int count = 0; count < V - 1; count++)
{
// Pick the minimum key vertex from the
// set of vertices not yet included in MST
int u = minKey(key, mstSet);
// Add the picked vertex to the MST Set
mstSet[u] = true;
// Update key value and parent index of
// the adjacent vertices of the picked vertex.
// Consider only those vertices which are not
// yet included in MST
for (int v = 0; v < V; v++)
// graph[u][v] is non zero only for adjacent vertices of m
// mstSet[v] is false for vertices not yet included in MST
// Update the key only if graph[u][v] is smaller than key[v]
if (graph[u][v] && mstSet[v] == false && graph[u][v] < key[v])
parent[v] = u, key[v] = graph[u][v];
}
// print the constructed MST
kMstClusterPrint(parent, V, graph);
//printMST(parent, V, graph);
}
// driver program to test above function
int main()
{
/* Let us create the following graph
2 3
(0)--(1)--(2)
| / \ |
6| 8/ \5 |7
| / \ |
(3)-------(4)
9 */
int graph[V][V] = {
{ 0, 4, 0, 0, 10, 0, 0, 0, 0, 9, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//a
{ 4, 0, 29, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//b
{ 0, 29, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//c
{ 0, 0, 8, 0, 6, 0, 0, 0, 0, 0, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//d
{ 10, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//e
{ 0, 0, 0, 0, 9, 0, 24, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//f
{ 0, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//g
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//h
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//i
{ 9, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//j
{ 0, 11, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0 },//k
{ 10, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0 },//l
{ 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0 },//m
{ 0, 0, 0, 0, 0, 12, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0 },//n
{ 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 17, 25, 0, 0 },//o
{ 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//p
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 9 },//q
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 24, 0, 0, 0, 0, 0, 0, 16 },//r
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 24, 0, 0, 13, 0, 0, 0, 0, 0 },//s
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13 },//t
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 13, 0, 0, 10, 0, 0, 0, 0 },//u
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 4, 0, 0, 23 },//v
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0 },//w
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//x
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30 },//y
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 16, 0, 13, 0, 23, 0, 0, 30, 0 }//z
};
// Print the solution
primMST(graph);
return 0;
}
|
.file "tmpxft_000cf4c1_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2343:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2343:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6minKeyPiPb
.type _Z6minKeyPiPb, @function
_Z6minKeyPiPb:
.LFB2337:
.cfi_startproc
endbr64
movl $0, %eax
movl $0, %r8d
movl $2147483647, %edx
jmp .L5
.L4:
addq $1, %rax
cmpq $26, %rax
je .L7
.L5:
cmpb $0, (%rsi,%rax)
jne .L4
movl (%rdi,%rax,4), %ecx
cmpl %edx, %ecx
cmovl %eax, %r8d
cmovl %ecx, %edx
jmp .L4
.L7:
movl %r8d, %eax
ret
.cfi_endproc
.LFE2337:
.size _Z6minKeyPiPb, .-_Z6minKeyPiPb
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\t"
.LC1:
.string "\n\n"
.LC2:
.string "%2d - %2d \t%3d \n"
.text
.globl _Z16kMstClusterPrintPiiPA26_i
.type _Z16kMstClusterPrintPiiPA26_i, @function
_Z16kMstClusterPrintPiiPA26_i:
.LFB2338:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
movaps %xmm0, (%rsp)
movl $0, 16(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %rsp, %r13
leaq 20(%rsp), %rbp
movq %r13, %rbx
leaq .LC0(%rip), %r15
.L9:
call rand@PLT
movslq %eax, %rdx
imulq $1321528399, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $26, %edx, %ecx
subl %ecx, %eax
movl %eax, %edx
movl %eax, (%rbx)
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $104, %r12
movl $1, %ebx
leaq .LC2(%rip), %r15
jmp .L10
.L13:
addq $1, %rbx
addq $104, %r12
cmpq $26, %rbx
je .L8
.L10:
movq %r13, %rax
movl $0, %edx
movl $1, %ecx
.L12:
cmpl %ebx, (%rax)
cmove %ecx, %edx
addq $4, %rax
cmpq %rbp, %rax
jne .L12
testb %dl, %dl
jne .L13
movl (%r14,%rbx,4), %edx
movslq %edx, %rax
movl (%r12,%rax,4), %r8d
movl %ebx, %ecx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L8:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2338:
.size _Z16kMstClusterPrintPiiPA26_i, .-_Z16kMstClusterPrintPiiPA26_i
.globl _Z7primMSTPA26_i
.type _Z7primMSTPA26_i, @function
_Z7primMSTPA26_i:
.LFB2339:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $264, %rsp
.cfi_def_cfa_offset 304
movq %rdi, %r13
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
.L22:
movl $2147483647, 144(%rsp,%rax,4)
movb $0, (%rsp,%rax)
addq $1, %rax
cmpq $26, %rax
jne .L22
movl $0, 144(%rsp)
movl $-1, 32(%rsp)
movl $25, %r12d
movq %rsp, %rbx
leaq 144(%rsp), %rbp
jmp .L25
.L23:
addq $1, %rdx
cmpq $26, %rdx
je .L31
.L24:
movl (%rsi,%rdx,4), %ecx
testl %ecx, %ecx
je .L23
cmpb $0, (%rdx,%rbx)
jne .L23
cmpl 0(%rbp,%rdx,4), %ecx
jge .L23
movl %eax, 32(%rsp,%rdx,4)
movl %ecx, 0(%rbp,%rdx,4)
jmp .L23
.L31:
subl $1, %r12d
je .L32
.L25:
movq %rbx, %rsi
movq %rbp, %rdi
call _Z6minKeyPiPb
movslq %eax, %rdx
movb $1, (%rsp,%rdx)
leaq (%rdx,%rdx,2), %rcx
leaq (%rdx,%rcx,4), %rdx
leaq 0(%r13,%rdx,8), %rsi
movl $0, %edx
jmp .L24
.L32:
leaq 32(%rsp), %rdi
movq %r13, %rdx
movl $26, %esi
call _Z16kMstClusterPrintPiiPA26_i
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2339:
.size _Z7primMSTPA26_i, .-_Z7primMSTPA26_i
.globl main
.type main, @function
main:
.LFB2340:
.cfi_startproc
endbr64
subq $2728, %rsp
.cfi_def_cfa_offset 2736
movq %fs:40, %rax
movq %rax, 2712(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $338, %ecx
rep stosq
movl $4, 4(%rsp)
movl $10, 16(%rsp)
movl $9, 36(%rsp)
movl $10, 44(%rsp)
movl $4, 104(%rsp)
movl $29, 112(%rsp)
movl $11, 144(%rsp)
movl $29, 212(%rsp)
movl $8, 220(%rsp)
movl $8, 320(%rsp)
movl $6, 328(%rsp)
movl $17, 352(%rsp)
movl $6, 356(%rsp)
movl $10, 416(%rsp)
movl $9, 436(%rsp)
movl $21, 464(%rsp)
movl $9, 536(%rsp)
movl $24, 544(%rsp)
movl $12, 572(%rsp)
movl $24, 644(%rsp)
movl $16, 680(%rsp)
movl $10, 780(%rsp)
movl $12, 788(%rsp)
movl $6, 868(%rsp)
movl $9, 936(%rsp)
movl $6, 968(%rsp)
movl $26, 1000(%rsp)
movl $11, 1044(%rsp)
movl $17, 1052(%rsp)
movl $3, 1116(%rsp)
movl $10, 1144(%rsp)
movl $6, 1156(%rsp)
movl $8, 1192(%rsp)
movl $27, 1216(%rsp)
movl $21, 1268(%rsp)
movl $8, 1292(%rsp)
movl $8, 1328(%rsp)
movl $12, 1372(%rsp)
movl $10, 1380(%rsp)
movl $16, 1428(%rsp)
movl $16, 1480(%rsp)
movl $3, 1516(%rsp)
movl $17, 1544(%rsp)
movl $25, 1548(%rsp)
movl $12, 1588(%rsp)
movl $3, 1616(%rsp)
movl $26, 1700(%rsp)
movl $19, 1732(%rsp)
movl $9, 1764(%rsp)
movl $19, 1832(%rsp)
movl $24, 1840(%rsp)
movl $16, 1868(%rsp)
movl $27, 1916(%rsp)
movl $24, 1940(%rsp)
movl $13, 1952(%rsp)
movl $3, 2016(%rsp)
movl $16, 2028(%rsp)
movl $13, 2076(%rsp)
movl $8, 2128(%rsp)
movl $13, 2152(%rsp)
movl $10, 2164(%rsp)
movl $10, 2264(%rsp)
movl $4, 2272(%rsp)
movl $23, 2284(%rsp)
movl $17, 2344(%rsp)
movl $4, 2372(%rsp)
movl $25, 2448(%rsp)
movl $30, 2596(%rsp)
movl $9, 2664(%rsp)
movl $16, 2668(%rsp)
movl $13, 2676(%rsp)
movl $23, 2684(%rsp)
movl $30, 2696(%rsp)
movq %rsp, %rdi
call _Z7primMSTPA26_i
movq 2712(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $2728, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2340:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2366:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2366:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// A C / C++ program for Prim's Minimum
// Spanning Tree (MST) algorithm. The program is
// for adjacency matrix representation of the graph
#include <stdio.h>
#include <limits.h>
#include<stdbool.h>
#include <cstdlib>
#include <ctime>
#include <algorithm>
// Number of vertices in the graph
#define V 26
#define K 4
// A utility function to find the vertex with
// minimum key value, from the set of vertices
// not yet included in MST
int minKey(int key[], bool mstSet[])
{
// Initialize min value
int min = INT_MAX, min_index=0;
for (int v = 0; v < V; v++)
if (mstSet[v] == false && key[v] < min)
min = key[v], min_index = v;
return min_index;
}
/*
void sortGraph(int graph[V][V])
{
for (int xcord = 0; xcord<V; xcord++){
for (int ycord = xcord + 1; ycord<V; ycord++){
if (graph[xcord][0]>graph[ycord][0]){
int temp = graph[xcord][1];
int temp2 = graph[xcord][0];
graph[xcord][0] = graph[ycord][0];
graph[xcord][1] = graph[ycord][1];
graph[ycord][0] = temp2;
graph[ycord][1] = temp;
}
}
}
}
// A utility function to print the
// constructed MST stored in parent[]
void printMST(int parent[], int n, int graph[V][V])
{
//sortGraph(graph);
printf(" Edge \t\tWeight\n");
for (int i = 1; i < V; i++)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
}
*/
void kMstClusterPrint(int parent[], int n, int graph[V][V]) {
//k number of clusters, let k=5
int k[5] = { 0 };
//int clusterGraph[k][V][V];
//select random edges for removal
srand(time(NULL));
for (int i = 0; i < 5; i++) {
k[i] = (int)rand() % 26;
printf("%d\t", k[i]);
}
printf("\n\n");
bool flag = false;
for (int i = 1; i < V; i++) {
for (int j = 0; j < 5; j++)
{
if (i == k[j]) flag = true;
}
if (!flag)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
flag = false;
}
}
// Function to construct and print MST for
// a graph represented using adjacency
// matrix representation
void primMST(int graph[V][V])
{
// Array to store constructed MST
int parent[V];
// Key values used to pick minimum weight edge in cut
int key[V];
// To represent set of vertices not yet included in MST
bool mstSet[V];
// Initialize all keys as INFINITE
for (int i = 0; i < V; i++)
key[i] = INT_MAX, mstSet[i] = false;
// Always include first 1st vertex in MST.
// Make key 0 so that this vertex is picked as first vertex.
key[0] = 0;
parent[0] = -1; // First node is always root of MST
// The MST will have V vertices
for (int count = 0; count < V - 1; count++)
{
// Pick the minimum key vertex from the
// set of vertices not yet included in MST
int u = minKey(key, mstSet);
// Add the picked vertex to the MST Set
mstSet[u] = true;
// Update key value and parent index of
// the adjacent vertices of the picked vertex.
// Consider only those vertices which are not
// yet included in MST
for (int v = 0; v < V; v++)
// graph[u][v] is non zero only for adjacent vertices of m
// mstSet[v] is false for vertices not yet included in MST
// Update the key only if graph[u][v] is smaller than key[v]
if (graph[u][v] && mstSet[v] == false && graph[u][v] < key[v])
parent[v] = u, key[v] = graph[u][v];
}
// print the constructed MST
kMstClusterPrint(parent, V, graph);
//printMST(parent, V, graph);
}
// driver program to test above function
int main()
{
/* Let us create the following graph
2 3
(0)--(1)--(2)
| / \ |
6| 8/ \5 |7
| / \ |
(3)-------(4)
9 */
int graph[V][V] = {
{ 0, 4, 0, 0, 10, 0, 0, 0, 0, 9, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//a
{ 4, 0, 29, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//b
{ 0, 29, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//c
{ 0, 0, 8, 0, 6, 0, 0, 0, 0, 0, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//d
{ 10, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//e
{ 0, 0, 0, 0, 9, 0, 24, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//f
{ 0, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//g
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//h
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//i
{ 9, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//j
{ 0, 11, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0 },//k
{ 10, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0 },//l
{ 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0 },//m
{ 0, 0, 0, 0, 0, 12, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0 },//n
{ 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 17, 25, 0, 0 },//o
{ 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//p
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 9 },//q
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 24, 0, 0, 0, 0, 0, 0, 16 },//r
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 24, 0, 0, 13, 0, 0, 0, 0, 0 },//s
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13 },//t
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 13, 0, 0, 10, 0, 0, 0, 0 },//u
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 4, 0, 0, 23 },//v
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0 },//w
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//x
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30 },//y
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 16, 0, 13, 0, 23, 0, 0, 30, 0 }//z
};
// Print the solution
primMST(graph);
return 0;
}
|
// A C / C++ program for Prim's Minimum
// Spanning Tree (MST) algorithm. The program is
// for adjacency matrix representation of the graph
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <limits.h>
#include<stdbool.h>
#include <cstdlib>
#include <ctime>
#include <algorithm>
// Number of vertices in the graph
#define V 26
#define K 4
// A utility function to find the vertex with
// minimum key value, from the set of vertices
// not yet included in MST
int minKey(int key[], bool mstSet[])
{
// Initialize min value
int min = INT_MAX, min_index=0;
for (int v = 0; v < V; v++)
if (mstSet[v] == false && key[v] < min)
min = key[v], min_index = v;
return min_index;
}
/*
void sortGraph(int graph[V][V])
{
for (int xcord = 0; xcord<V; xcord++){
for (int ycord = xcord + 1; ycord<V; ycord++){
if (graph[xcord][0]>graph[ycord][0]){
int temp = graph[xcord][1];
int temp2 = graph[xcord][0];
graph[xcord][0] = graph[ycord][0];
graph[xcord][1] = graph[ycord][1];
graph[ycord][0] = temp2;
graph[ycord][1] = temp;
}
}
}
}
// A utility function to print the
// constructed MST stored in parent[]
void printMST(int parent[], int n, int graph[V][V])
{
//sortGraph(graph);
printf(" Edge \t\tWeight\n");
for (int i = 1; i < V; i++)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
}
*/
void kMstClusterPrint(int parent[], int n, int graph[V][V]) {
//k number of clusters, let k=5
int k[5] = { 0 };
//int clusterGraph[k][V][V];
//select random edges for removal
srand(time(NULL));
for (int i = 0; i < 5; i++) {
k[i] = (int)rand() % 26;
printf("%d\t", k[i]);
}
printf("\n\n");
bool flag = false;
for (int i = 1; i < V; i++) {
for (int j = 0; j < 5; j++)
{
if (i == k[j]) flag = true;
}
if (!flag)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
flag = false;
}
}
// Function to construct and print MST for
// a graph represented using adjacency
// matrix representation
void primMST(int graph[V][V])
{
// Array to store constructed MST
int parent[V];
// Key values used to pick minimum weight edge in cut
int key[V];
// To represent set of vertices not yet included in MST
bool mstSet[V];
// Initialize all keys as INFINITE
for (int i = 0; i < V; i++)
key[i] = INT_MAX, mstSet[i] = false;
// Always include first 1st vertex in MST.
// Make key 0 so that this vertex is picked as first vertex.
key[0] = 0;
parent[0] = -1; // First node is always root of MST
// The MST will have V vertices
for (int count = 0; count < V - 1; count++)
{
// Pick the minimum key vertex from the
// set of vertices not yet included in MST
int u = minKey(key, mstSet);
// Add the picked vertex to the MST Set
mstSet[u] = true;
// Update key value and parent index of
// the adjacent vertices of the picked vertex.
// Consider only those vertices which are not
// yet included in MST
for (int v = 0; v < V; v++)
// graph[u][v] is non zero only for adjacent vertices of m
// mstSet[v] is false for vertices not yet included in MST
// Update the key only if graph[u][v] is smaller than key[v]
if (graph[u][v] && mstSet[v] == false && graph[u][v] < key[v])
parent[v] = u, key[v] = graph[u][v];
}
// print the constructed MST
kMstClusterPrint(parent, V, graph);
//printMST(parent, V, graph);
}
// driver program to test above function
int main()
{
/* Let us create the following graph
2 3
(0)--(1)--(2)
| / \ |
6| 8/ \5 |7
| / \ |
(3)-------(4)
9 */
int graph[V][V] = {
{ 0, 4, 0, 0, 10, 0, 0, 0, 0, 9, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//a
{ 4, 0, 29, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//b
{ 0, 29, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//c
{ 0, 0, 8, 0, 6, 0, 0, 0, 0, 0, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//d
{ 10, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//e
{ 0, 0, 0, 0, 9, 0, 24, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//f
{ 0, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//g
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//h
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//i
{ 9, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//j
{ 0, 11, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0 },//k
{ 10, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0 },//l
{ 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0 },//m
{ 0, 0, 0, 0, 0, 12, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0 },//n
{ 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 17, 25, 0, 0 },//o
{ 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//p
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 9 },//q
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 24, 0, 0, 0, 0, 0, 0, 16 },//r
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 24, 0, 0, 13, 0, 0, 0, 0, 0 },//s
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13 },//t
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 13, 0, 0, 10, 0, 0, 0, 0 },//u
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 4, 0, 0, 23 },//v
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0 },//w
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//x
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30 },//y
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 16, 0, 13, 0, 23, 0, 0, 30, 0 }//z
};
// Print the solution
primMST(graph);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
// A C / C++ program for Prim's Minimum
// Spanning Tree (MST) algorithm. The program is
// for adjacency matrix representation of the graph
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <limits.h>
#include<stdbool.h>
#include <cstdlib>
#include <ctime>
#include <algorithm>
// Number of vertices in the graph
#define V 26
#define K 4
// A utility function to find the vertex with
// minimum key value, from the set of vertices
// not yet included in MST
int minKey(int key[], bool mstSet[])
{
// Initialize min value
int min = INT_MAX, min_index=0;
for (int v = 0; v < V; v++)
if (mstSet[v] == false && key[v] < min)
min = key[v], min_index = v;
return min_index;
}
/*
void sortGraph(int graph[V][V])
{
for (int xcord = 0; xcord<V; xcord++){
for (int ycord = xcord + 1; ycord<V; ycord++){
if (graph[xcord][0]>graph[ycord][0]){
int temp = graph[xcord][1];
int temp2 = graph[xcord][0];
graph[xcord][0] = graph[ycord][0];
graph[xcord][1] = graph[ycord][1];
graph[ycord][0] = temp2;
graph[ycord][1] = temp;
}
}
}
}
// A utility function to print the
// constructed MST stored in parent[]
void printMST(int parent[], int n, int graph[V][V])
{
//sortGraph(graph);
printf(" Edge \t\tWeight\n");
for (int i = 1; i < V; i++)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
}
*/
void kMstClusterPrint(int parent[], int n, int graph[V][V]) {
//k number of clusters, let k=5
int k[5] = { 0 };
//int clusterGraph[k][V][V];
//select random edges for removal
srand(time(NULL));
for (int i = 0; i < 5; i++) {
k[i] = (int)rand() % 26;
printf("%d\t", k[i]);
}
printf("\n\n");
bool flag = false;
for (int i = 1; i < V; i++) {
for (int j = 0; j < 5; j++)
{
if (i == k[j]) flag = true;
}
if (!flag)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
flag = false;
}
}
// Function to construct and print MST for
// a graph represented using adjacency
// matrix representation
void primMST(int graph[V][V])
{
// Array to store constructed MST
int parent[V];
// Key values used to pick minimum weight edge in cut
int key[V];
// To represent set of vertices not yet included in MST
bool mstSet[V];
// Initialize all keys as INFINITE
for (int i = 0; i < V; i++)
key[i] = INT_MAX, mstSet[i] = false;
// Always include first 1st vertex in MST.
// Make key 0 so that this vertex is picked as first vertex.
key[0] = 0;
parent[0] = -1; // First node is always root of MST
// The MST will have V vertices
for (int count = 0; count < V - 1; count++)
{
// Pick the minimum key vertex from the
// set of vertices not yet included in MST
int u = minKey(key, mstSet);
// Add the picked vertex to the MST Set
mstSet[u] = true;
// Update key value and parent index of
// the adjacent vertices of the picked vertex.
// Consider only those vertices which are not
// yet included in MST
for (int v = 0; v < V; v++)
// graph[u][v] is non zero only for adjacent vertices of m
// mstSet[v] is false for vertices not yet included in MST
// Update the key only if graph[u][v] is smaller than key[v]
if (graph[u][v] && mstSet[v] == false && graph[u][v] < key[v])
parent[v] = u, key[v] = graph[u][v];
}
// print the constructed MST
kMstClusterPrint(parent, V, graph);
//printMST(parent, V, graph);
}
// driver program to test above function
int main()
{
/* Let us create the following graph
2 3
(0)--(1)--(2)
| / \ |
6| 8/ \5 |7
| / \ |
(3)-------(4)
9 */
int graph[V][V] = {
{ 0, 4, 0, 0, 10, 0, 0, 0, 0, 9, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//a
{ 4, 0, 29, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//b
{ 0, 29, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//c
{ 0, 0, 8, 0, 6, 0, 0, 0, 0, 0, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//d
{ 10, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//e
{ 0, 0, 0, 0, 9, 0, 24, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//f
{ 0, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//g
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//h
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//i
{ 9, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//j
{ 0, 11, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0 },//k
{ 10, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0 },//l
{ 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0 },//m
{ 0, 0, 0, 0, 0, 12, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0 },//n
{ 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 17, 25, 0, 0 },//o
{ 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//p
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 9 },//q
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 24, 0, 0, 0, 0, 0, 0, 16 },//r
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 24, 0, 0, 13, 0, 0, 0, 0, 0 },//s
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13 },//t
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 13, 0, 0, 10, 0, 0, 0, 0 },//u
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 4, 0, 0, 23 },//v
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0 },//w
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//x
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30 },//y
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 16, 0, 13, 0, 23, 0, 0, 30, 0 }//z
};
// Print the solution
primMST(graph);
return 0;
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
// A C / C++ program for Prim's Minimum
// Spanning Tree (MST) algorithm. The program is
// for adjacency matrix representation of the graph
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <limits.h>
#include<stdbool.h>
#include <cstdlib>
#include <ctime>
#include <algorithm>
// Number of vertices in the graph
#define V 26
#define K 4
// A utility function to find the vertex with
// minimum key value, from the set of vertices
// not yet included in MST
int minKey(int key[], bool mstSet[])
{
// Initialize min value
int min = INT_MAX, min_index=0;
for (int v = 0; v < V; v++)
if (mstSet[v] == false && key[v] < min)
min = key[v], min_index = v;
return min_index;
}
/*
void sortGraph(int graph[V][V])
{
for (int xcord = 0; xcord<V; xcord++){
for (int ycord = xcord + 1; ycord<V; ycord++){
if (graph[xcord][0]>graph[ycord][0]){
int temp = graph[xcord][1];
int temp2 = graph[xcord][0];
graph[xcord][0] = graph[ycord][0];
graph[xcord][1] = graph[ycord][1];
graph[ycord][0] = temp2;
graph[ycord][1] = temp;
}
}
}
}
// A utility function to print the
// constructed MST stored in parent[]
void printMST(int parent[], int n, int graph[V][V])
{
//sortGraph(graph);
printf(" Edge \t\tWeight\n");
for (int i = 1; i < V; i++)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
}
*/
void kMstClusterPrint(int parent[], int n, int graph[V][V]) {
//k number of clusters, let k=5
int k[5] = { 0 };
//int clusterGraph[k][V][V];
//select random edges for removal
srand(time(NULL));
for (int i = 0; i < 5; i++) {
k[i] = (int)rand() % 26;
printf("%d\t", k[i]);
}
printf("\n\n");
bool flag = false;
for (int i = 1; i < V; i++) {
for (int j = 0; j < 5; j++)
{
if (i == k[j]) flag = true;
}
if (!flag)
printf("%2d - %2d \t%3d \n", parent[i], i, graph[i][parent[i]]);
flag = false;
}
}
// Function to construct and print MST for
// a graph represented using adjacency
// matrix representation
void primMST(int graph[V][V])
{
// Array to store constructed MST
int parent[V];
// Key values used to pick minimum weight edge in cut
int key[V];
// To represent set of vertices not yet included in MST
bool mstSet[V];
// Initialize all keys as INFINITE
for (int i = 0; i < V; i++)
key[i] = INT_MAX, mstSet[i] = false;
// Always include first 1st vertex in MST.
// Make key 0 so that this vertex is picked as first vertex.
key[0] = 0;
parent[0] = -1; // First node is always root of MST
// The MST will have V vertices
for (int count = 0; count < V - 1; count++)
{
// Pick the minimum key vertex from the
// set of vertices not yet included in MST
int u = minKey(key, mstSet);
// Add the picked vertex to the MST Set
mstSet[u] = true;
// Update key value and parent index of
// the adjacent vertices of the picked vertex.
// Consider only those vertices which are not
// yet included in MST
for (int v = 0; v < V; v++)
// graph[u][v] is non zero only for adjacent vertices of m
// mstSet[v] is false for vertices not yet included in MST
// Update the key only if graph[u][v] is smaller than key[v]
if (graph[u][v] && mstSet[v] == false && graph[u][v] < key[v])
parent[v] = u, key[v] = graph[u][v];
}
// print the constructed MST
kMstClusterPrint(parent, V, graph);
//printMST(parent, V, graph);
}
// driver program to test above function
int main()
{
/* Let us create the following graph
2 3
(0)--(1)--(2)
| / \ |
6| 8/ \5 |7
| / \ |
(3)-------(4)
9 */
int graph[V][V] = {
{ 0, 4, 0, 0, 10, 0, 0, 0, 0, 9, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//a
{ 4, 0, 29, 0, 0, 0, 0, 0, 0, 0, 11, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//b
{ 0, 29, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//c
{ 0, 0, 8, 0, 6, 0, 0, 0, 0, 0, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//d
{ 10, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//e
{ 0, 0, 0, 0, 9, 0, 24, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//f
{ 0, 0, 0, 0, 0, 24, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//g
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//h
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//i
{ 9, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//j
{ 0, 11, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0 },//k
{ 10, 0, 0, 6, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 0, 0 },//l
{ 0, 0, 0, 0, 0, 21, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0 },//m
{ 0, 0, 0, 0, 0, 12, 0, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0 },//n
{ 0, 0, 0, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 17, 25, 0, 0 },//o
{ 0, 0, 0, 0, 0, 0, 0, 12, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//p
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 26, 0, 0, 0, 0, 0, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 9 },//q
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 0, 24, 0, 0, 0, 0, 0, 0, 16 },//r
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 0, 0, 0, 0, 0, 24, 0, 0, 13, 0, 0, 0, 0, 0 },//s
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13 },//t
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 13, 0, 0, 10, 0, 0, 0, 0 },//u
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 4, 0, 0, 23 },//v
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0 },//w
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },//x
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30 },//y
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 16, 0, 13, 0, 23, 0, 0, 30, 0 }//z
};
// Print the solution
primMST(graph);
return 0;
}
|
.text
.file "kernel.hip"
.globl _Z6minKeyPiPb # -- Begin function _Z6minKeyPiPb
.p2align 4, 0x90
.type _Z6minKeyPiPb,@function
_Z6minKeyPiPb: # @_Z6minKeyPiPb
.cfi_startproc
# %bb.0:
movl $2147483647, %ecx # imm = 0x7FFFFFFF
xorl %edx, %edx
xorl %eax, %eax
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_1 Depth=1
incq %rdx
cmpq $26, %rdx
je .LBB0_4
.LBB0_1: # =>This Inner Loop Header: Depth=1
cmpb $0, (%rsi,%rdx)
jne .LBB0_3
# %bb.2: # in Loop: Header=BB0_1 Depth=1
movl (%rdi,%rdx,4), %r8d
cmpl %ecx, %r8d
cmovll %r8d, %ecx
cmovll %edx, %eax
jmp .LBB0_3
.LBB0_4:
retq
.Lfunc_end0:
.size _Z6minKeyPiPb, .Lfunc_end0-_Z6minKeyPiPb
.cfi_endproc
# -- End function
.globl _Z16kMstClusterPrintPiiPA26_i # -- Begin function _Z16kMstClusterPrintPiiPA26_i
.p2align 4, 0x90
.type _Z16kMstClusterPrintPiiPA26_i,@function
_Z16kMstClusterPrintPiiPA26_i: # @_Z16kMstClusterPrintPiiPA26_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rdi, %r14
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movl $0, 16(%rsp)
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1321528399, %rsi, %rax # imm = 0x4EC4EC4F
movq %rax, %rcx
shrq $63, %rcx
sarq $35, %rax
addl %ecx, %eax
leal (%rax,%rax,4), %ecx
leal (%rcx,%rcx,4), %ecx
addl %eax, %ecx
subl %ecx, %esi
movl %esi, (%rsp,%r15,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r15
cmpq $5, %r15
jne .LBB1_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %r15d
movl $1, %ebp
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_3 Depth=1
incq %r15
cmpq $26, %r15
je .LBB1_8
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsp,%rax,4), %edx
cmpq %rdx, %r15
movzbl %cl, %ecx
cmovel %ebp, %ecx
incq %rax
cmpq $5, %rax
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
testb $1, %cl
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_3 Depth=1
movslq (%r14,%r15,4), %rsi
imulq $104, %r15, %rax
addq %rbx, %rax
movl (%rax,%rsi,4), %ecx
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
movl %r15d, %edx
xorl %eax, %eax
callq printf
jmp .LBB1_7
.LBB1_8:
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16kMstClusterPrintPiiPA26_i, .Lfunc_end1-_Z16kMstClusterPrintPiiPA26_i
.cfi_endproc
# -- End function
.globl _Z7primMSTPA26_i # -- Begin function _Z7primMSTPA26_i
.p2align 4, 0x90
.type _Z7primMSTPA26_i,@function
_Z7primMSTPA26_i: # @_Z7primMSTPA26_i
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, %rdx
xorps %xmm0, %xmm0
movups %xmm0, 10(%rsp)
movaps %xmm0, (%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $2147483647, 32(%rsp,%rax,4) # imm = 0x7FFFFFFF
incq %rax
cmpq $26, %rax
jne .LBB2_1
# %bb.2:
movl $0, 32(%rsp)
movl $-1, 144(%rsp)
xorl %eax, %eax
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_3 Depth=1
incl %eax
cmpl $25, %eax
je .LBB2_14
.LBB2_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_8 Depth 2
movl $2147483647, %esi # imm = 0x7FFFFFFF
xorl %edi, %edi
xorl %ecx, %ecx
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=2
incq %rdi
cmpq $26, %rdi
je .LBB2_7
.LBB2_4: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rsp,%rdi)
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=2
movl 32(%rsp,%rdi,4), %r8d
cmpl %esi, %r8d
cmovll %r8d, %esi
cmovll %edi, %ecx
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_7: # %_Z6minKeyPiPb.exit
# in Loop: Header=BB2_3 Depth=1
movslq %ecx, %rsi
movb $1, (%rsp,%rsi)
imulq $104, %rsi, %rsi
addq %rdx, %rsi
xorl %edi, %edi
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_8 Depth=2
incq %rdi
cmpq $26, %rdi
je .LBB2_13
.LBB2_8: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%rdi,4), %r8d
testl %r8d, %r8d
je .LBB2_12
# %bb.9: # in Loop: Header=BB2_8 Depth=2
cmpb $0, (%rsp,%rdi)
jne .LBB2_12
# %bb.10: # in Loop: Header=BB2_8 Depth=2
cmpl 32(%rsp,%rdi,4), %r8d
jge .LBB2_12
# %bb.11: # in Loop: Header=BB2_8 Depth=2
movl %ecx, 144(%rsp,%rdi,4)
movl %r8d, 32(%rsp,%rdi,4)
jmp .LBB2_12
.LBB2_14:
leaq 144(%rsp), %rdi
callq _Z16kMstClusterPrintPiiPA26_i
addq $248, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7primMSTPA26_i, .Lfunc_end2-_Z7primMSTPA26_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
xorps %xmm0, %xmm0
movups %xmm0, 10(%rsp)
movaps %xmm0, (%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $2147483647, 32(%rsp,%rax,4) # imm = 0x7FFFFFFF
incq %rax
cmpq $26, %rax
jne .LBB3_1
# %bb.2:
movl $0, 32(%rsp)
movl $-1, 144(%rsp)
xorl %eax, %eax
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_13: # in Loop: Header=BB3_3 Depth=1
incl %eax
cmpl $25, %eax
je .LBB3_14
.LBB3_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_8 Depth 2
movl $2147483647, %edx # imm = 0x7FFFFFFF
xorl %esi, %esi
xorl %ecx, %ecx
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
incq %rsi
cmpq $26, %rsi
je .LBB3_7
.LBB3_4: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rsp,%rsi)
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movl 32(%rsp,%rsi,4), %edi
cmpl %edx, %edi
cmovll %edi, %edx
cmovll %esi, %ecx
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_7: # %_Z6minKeyPiPb.exit.i
# in Loop: Header=BB3_3 Depth=1
movslq %ecx, %rdx
movb $1, (%rsp,%rdx)
imulq $104, %rdx, %rdx
xorl %esi, %esi
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_8 Depth=2
incq %rsi
cmpq $26, %rsi
je .LBB3_13
.LBB3_8: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movl .L__const.main.graph(%rdx,%rsi,4), %edi
testl %edi, %edi
je .LBB3_12
# %bb.9: # in Loop: Header=BB3_8 Depth=2
cmpb $0, (%rsp,%rsi)
jne .LBB3_12
# %bb.10: # in Loop: Header=BB3_8 Depth=2
cmpl 32(%rsp,%rsi,4), %edi
jge .LBB3_12
# %bb.11: # in Loop: Header=BB3_8 Depth=2
movl %ecx, 144(%rsp,%rsi,4)
movl %edi, 32(%rsp,%rsi,4)
jmp .LBB3_12
.LBB3_14: # %_Z7primMSTPA26_i.exit
leaq 144(%rsp), %rdi
movl $.L__const.main.graph, %edx
callq _Z16kMstClusterPrintPiiPA26_i
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\t"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%2d - %2d \t%3d \n"
.size .L.str.2, 17
.type .L__const.main.graph,@object # @__const.main.graph
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.graph:
.long 0 # 0x0
.long 4 # 0x4
.long 0 # 0x0
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 9 # 0x9
.long 0 # 0x0
.long 10 # 0xa
.zero 56
.long 4 # 0x4
.long 0 # 0x0
.long 29 # 0x1d
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 11 # 0xb
.zero 60
.long 0 # 0x0
.long 29 # 0x1d
.long 0 # 0x0
.long 8 # 0x8
.zero 88
.long 0 # 0x0
.long 0 # 0x0
.long 8 # 0x8
.long 0 # 0x0
.long 6 # 0x6
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 17 # 0x11
.long 6 # 0x6
.zero 56
.long 10 # 0xa
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 9 # 0x9
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 21 # 0x15
.zero 52
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 9 # 0x9
.long 0 # 0x0
.long 24 # 0x18
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 12 # 0xc
.zero 48
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 24 # 0x18
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 16 # 0x10
.zero 44
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 12 # 0xc
.zero 40
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 6 # 0x6
.zero 64
.long 9 # 0x9
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 6 # 0x6
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 26 # 0x1a
.zero 36
.long 0 # 0x0
.long 11 # 0xb
.long 0 # 0x0
.long 17 # 0x11
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 3 # 0x3
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 0 # 0x0
.long 6 # 0x6
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 8 # 0x8
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 27 # 0x1b
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 21 # 0x15
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 8 # 0x8
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 8 # 0x8
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 12 # 0xc
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 16 # 0x10
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 16 # 0x10
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 3 # 0x3
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 17 # 0x11
.long 25 # 0x19
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 12 # 0xc
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 3 # 0x3
.zero 44
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 26 # 0x1a
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 19 # 0x13
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 9 # 0x9
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 19 # 0x13
.long 0 # 0x0
.long 24 # 0x18
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 16 # 0x10
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 27 # 0x1b
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 24 # 0x18
.long 0 # 0x0
.long 0 # 0x0
.long 13 # 0xd
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 3 # 0x3
.long 0 # 0x0
.long 0 # 0x0
.long 16 # 0x10
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 13 # 0xd
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 8 # 0x8
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 13 # 0xd
.long 0 # 0x0
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 4 # 0x4
.long 0 # 0x0
.long 0 # 0x0
.long 23 # 0x17
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 17 # 0x11
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 4 # 0x4
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 25 # 0x19
.zero 44
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 30 # 0x1e
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 9 # 0x9
.long 16 # 0x10
.long 0 # 0x0
.long 13 # 0xd
.long 0 # 0x0
.long 23 # 0x17
.long 0 # 0x0
.long 0 # 0x0
.long 30 # 0x1e
.long 0 # 0x0
.size .L__const.main.graph, 2704
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000cf4c1_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2343:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2343:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6minKeyPiPb
.type _Z6minKeyPiPb, @function
_Z6minKeyPiPb:
.LFB2337:
.cfi_startproc
endbr64
movl $0, %eax
movl $0, %r8d
movl $2147483647, %edx
jmp .L5
.L4:
addq $1, %rax
cmpq $26, %rax
je .L7
.L5:
cmpb $0, (%rsi,%rax)
jne .L4
movl (%rdi,%rax,4), %ecx
cmpl %edx, %ecx
cmovl %eax, %r8d
cmovl %ecx, %edx
jmp .L4
.L7:
movl %r8d, %eax
ret
.cfi_endproc
.LFE2337:
.size _Z6minKeyPiPb, .-_Z6minKeyPiPb
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\t"
.LC1:
.string "\n\n"
.LC2:
.string "%2d - %2d \t%3d \n"
.text
.globl _Z16kMstClusterPrintPiiPA26_i
.type _Z16kMstClusterPrintPiiPA26_i, @function
_Z16kMstClusterPrintPiiPA26_i:
.LFB2338:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
movaps %xmm0, (%rsp)
movl $0, 16(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %rsp, %r13
leaq 20(%rsp), %rbp
movq %r13, %rbx
leaq .LC0(%rip), %r15
.L9:
call rand@PLT
movslq %eax, %rdx
imulq $1321528399, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $26, %edx, %ecx
subl %ecx, %eax
movl %eax, %edx
movl %eax, (%rbx)
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $104, %r12
movl $1, %ebx
leaq .LC2(%rip), %r15
jmp .L10
.L13:
addq $1, %rbx
addq $104, %r12
cmpq $26, %rbx
je .L8
.L10:
movq %r13, %rax
movl $0, %edx
movl $1, %ecx
.L12:
cmpl %ebx, (%rax)
cmove %ecx, %edx
addq $4, %rax
cmpq %rbp, %rax
jne .L12
testb %dl, %dl
jne .L13
movl (%r14,%rbx,4), %edx
movslq %edx, %rax
movl (%r12,%rax,4), %r8d
movl %ebx, %ecx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L8:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2338:
.size _Z16kMstClusterPrintPiiPA26_i, .-_Z16kMstClusterPrintPiiPA26_i
.globl _Z7primMSTPA26_i
.type _Z7primMSTPA26_i, @function
_Z7primMSTPA26_i:
.LFB2339:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $264, %rsp
.cfi_def_cfa_offset 304
movq %rdi, %r13
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
.L22:
movl $2147483647, 144(%rsp,%rax,4)
movb $0, (%rsp,%rax)
addq $1, %rax
cmpq $26, %rax
jne .L22
movl $0, 144(%rsp)
movl $-1, 32(%rsp)
movl $25, %r12d
movq %rsp, %rbx
leaq 144(%rsp), %rbp
jmp .L25
.L23:
addq $1, %rdx
cmpq $26, %rdx
je .L31
.L24:
movl (%rsi,%rdx,4), %ecx
testl %ecx, %ecx
je .L23
cmpb $0, (%rdx,%rbx)
jne .L23
cmpl 0(%rbp,%rdx,4), %ecx
jge .L23
movl %eax, 32(%rsp,%rdx,4)
movl %ecx, 0(%rbp,%rdx,4)
jmp .L23
.L31:
subl $1, %r12d
je .L32
.L25:
movq %rbx, %rsi
movq %rbp, %rdi
call _Z6minKeyPiPb
movslq %eax, %rdx
movb $1, (%rsp,%rdx)
leaq (%rdx,%rdx,2), %rcx
leaq (%rdx,%rcx,4), %rdx
leaq 0(%r13,%rdx,8), %rsi
movl $0, %edx
jmp .L24
.L32:
leaq 32(%rsp), %rdi
movq %r13, %rdx
movl $26, %esi
call _Z16kMstClusterPrintPiiPA26_i
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2339:
.size _Z7primMSTPA26_i, .-_Z7primMSTPA26_i
.globl main
.type main, @function
main:
.LFB2340:
.cfi_startproc
endbr64
subq $2728, %rsp
.cfi_def_cfa_offset 2736
movq %fs:40, %rax
movq %rax, 2712(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $338, %ecx
rep stosq
movl $4, 4(%rsp)
movl $10, 16(%rsp)
movl $9, 36(%rsp)
movl $10, 44(%rsp)
movl $4, 104(%rsp)
movl $29, 112(%rsp)
movl $11, 144(%rsp)
movl $29, 212(%rsp)
movl $8, 220(%rsp)
movl $8, 320(%rsp)
movl $6, 328(%rsp)
movl $17, 352(%rsp)
movl $6, 356(%rsp)
movl $10, 416(%rsp)
movl $9, 436(%rsp)
movl $21, 464(%rsp)
movl $9, 536(%rsp)
movl $24, 544(%rsp)
movl $12, 572(%rsp)
movl $24, 644(%rsp)
movl $16, 680(%rsp)
movl $10, 780(%rsp)
movl $12, 788(%rsp)
movl $6, 868(%rsp)
movl $9, 936(%rsp)
movl $6, 968(%rsp)
movl $26, 1000(%rsp)
movl $11, 1044(%rsp)
movl $17, 1052(%rsp)
movl $3, 1116(%rsp)
movl $10, 1144(%rsp)
movl $6, 1156(%rsp)
movl $8, 1192(%rsp)
movl $27, 1216(%rsp)
movl $21, 1268(%rsp)
movl $8, 1292(%rsp)
movl $8, 1328(%rsp)
movl $12, 1372(%rsp)
movl $10, 1380(%rsp)
movl $16, 1428(%rsp)
movl $16, 1480(%rsp)
movl $3, 1516(%rsp)
movl $17, 1544(%rsp)
movl $25, 1548(%rsp)
movl $12, 1588(%rsp)
movl $3, 1616(%rsp)
movl $26, 1700(%rsp)
movl $19, 1732(%rsp)
movl $9, 1764(%rsp)
movl $19, 1832(%rsp)
movl $24, 1840(%rsp)
movl $16, 1868(%rsp)
movl $27, 1916(%rsp)
movl $24, 1940(%rsp)
movl $13, 1952(%rsp)
movl $3, 2016(%rsp)
movl $16, 2028(%rsp)
movl $13, 2076(%rsp)
movl $8, 2128(%rsp)
movl $13, 2152(%rsp)
movl $10, 2164(%rsp)
movl $10, 2264(%rsp)
movl $4, 2272(%rsp)
movl $23, 2284(%rsp)
movl $17, 2344(%rsp)
movl $4, 2372(%rsp)
movl $25, 2448(%rsp)
movl $30, 2596(%rsp)
movl $9, 2664(%rsp)
movl $16, 2668(%rsp)
movl $13, 2676(%rsp)
movl $23, 2684(%rsp)
movl $30, 2696(%rsp)
movq %rsp, %rdi
call _Z7primMSTPA26_i
movq 2712(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $2728, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2340:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2366:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2366:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel.hip"
.globl _Z6minKeyPiPb # -- Begin function _Z6minKeyPiPb
.p2align 4, 0x90
.type _Z6minKeyPiPb,@function
_Z6minKeyPiPb: # @_Z6minKeyPiPb
.cfi_startproc
# %bb.0:
movl $2147483647, %ecx # imm = 0x7FFFFFFF
xorl %edx, %edx
xorl %eax, %eax
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_1 Depth=1
incq %rdx
cmpq $26, %rdx
je .LBB0_4
.LBB0_1: # =>This Inner Loop Header: Depth=1
cmpb $0, (%rsi,%rdx)
jne .LBB0_3
# %bb.2: # in Loop: Header=BB0_1 Depth=1
movl (%rdi,%rdx,4), %r8d
cmpl %ecx, %r8d
cmovll %r8d, %ecx
cmovll %edx, %eax
jmp .LBB0_3
.LBB0_4:
retq
.Lfunc_end0:
.size _Z6minKeyPiPb, .Lfunc_end0-_Z6minKeyPiPb
.cfi_endproc
# -- End function
.globl _Z16kMstClusterPrintPiiPA26_i # -- Begin function _Z16kMstClusterPrintPiiPA26_i
.p2align 4, 0x90
.type _Z16kMstClusterPrintPiiPA26_i,@function
_Z16kMstClusterPrintPiiPA26_i: # @_Z16kMstClusterPrintPiiPA26_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rdi, %r14
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movl $0, 16(%rsp)
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1321528399, %rsi, %rax # imm = 0x4EC4EC4F
movq %rax, %rcx
shrq $63, %rcx
sarq $35, %rax
addl %ecx, %eax
leal (%rax,%rax,4), %ecx
leal (%rcx,%rcx,4), %ecx
addl %eax, %ecx
subl %ecx, %esi
movl %esi, (%rsp,%r15,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r15
cmpq $5, %r15
jne .LBB1_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %r15d
movl $1, %ebp
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_3 Depth=1
incq %r15
cmpq $26, %r15
je .LBB1_8
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsp,%rax,4), %edx
cmpq %rdx, %r15
movzbl %cl, %ecx
cmovel %ebp, %ecx
incq %rax
cmpq $5, %rax
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
testb $1, %cl
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_3 Depth=1
movslq (%r14,%r15,4), %rsi
imulq $104, %r15, %rax
addq %rbx, %rax
movl (%rax,%rsi,4), %ecx
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
movl %r15d, %edx
xorl %eax, %eax
callq printf
jmp .LBB1_7
.LBB1_8:
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z16kMstClusterPrintPiiPA26_i, .Lfunc_end1-_Z16kMstClusterPrintPiiPA26_i
.cfi_endproc
# -- End function
.globl _Z7primMSTPA26_i # -- Begin function _Z7primMSTPA26_i
.p2align 4, 0x90
.type _Z7primMSTPA26_i,@function
_Z7primMSTPA26_i: # @_Z7primMSTPA26_i
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, %rdx
xorps %xmm0, %xmm0
movups %xmm0, 10(%rsp)
movaps %xmm0, (%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $2147483647, 32(%rsp,%rax,4) # imm = 0x7FFFFFFF
incq %rax
cmpq $26, %rax
jne .LBB2_1
# %bb.2:
movl $0, 32(%rsp)
movl $-1, 144(%rsp)
xorl %eax, %eax
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_3 Depth=1
incl %eax
cmpl $25, %eax
je .LBB2_14
.LBB2_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_8 Depth 2
movl $2147483647, %esi # imm = 0x7FFFFFFF
xorl %edi, %edi
xorl %ecx, %ecx
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=2
incq %rdi
cmpq $26, %rdi
je .LBB2_7
.LBB2_4: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rsp,%rdi)
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=2
movl 32(%rsp,%rdi,4), %r8d
cmpl %esi, %r8d
cmovll %r8d, %esi
cmovll %edi, %ecx
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_7: # %_Z6minKeyPiPb.exit
# in Loop: Header=BB2_3 Depth=1
movslq %ecx, %rsi
movb $1, (%rsp,%rsi)
imulq $104, %rsi, %rsi
addq %rdx, %rsi
xorl %edi, %edi
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_8 Depth=2
incq %rdi
cmpq $26, %rdi
je .LBB2_13
.LBB2_8: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rsi,%rdi,4), %r8d
testl %r8d, %r8d
je .LBB2_12
# %bb.9: # in Loop: Header=BB2_8 Depth=2
cmpb $0, (%rsp,%rdi)
jne .LBB2_12
# %bb.10: # in Loop: Header=BB2_8 Depth=2
cmpl 32(%rsp,%rdi,4), %r8d
jge .LBB2_12
# %bb.11: # in Loop: Header=BB2_8 Depth=2
movl %ecx, 144(%rsp,%rdi,4)
movl %r8d, 32(%rsp,%rdi,4)
jmp .LBB2_12
.LBB2_14:
leaq 144(%rsp), %rdi
callq _Z16kMstClusterPrintPiiPA26_i
addq $248, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7primMSTPA26_i, .Lfunc_end2-_Z7primMSTPA26_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
xorps %xmm0, %xmm0
movups %xmm0, 10(%rsp)
movaps %xmm0, (%rsp)
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $2147483647, 32(%rsp,%rax,4) # imm = 0x7FFFFFFF
incq %rax
cmpq $26, %rax
jne .LBB3_1
# %bb.2:
movl $0, 32(%rsp)
movl $-1, 144(%rsp)
xorl %eax, %eax
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_13: # in Loop: Header=BB3_3 Depth=1
incl %eax
cmpl $25, %eax
je .LBB3_14
.LBB3_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_8 Depth 2
movl $2147483647, %edx # imm = 0x7FFFFFFF
xorl %esi, %esi
xorl %ecx, %ecx
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
incq %rsi
cmpq $26, %rsi
je .LBB3_7
.LBB3_4: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
cmpb $0, (%rsp,%rsi)
jne .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
movl 32(%rsp,%rsi,4), %edi
cmpl %edx, %edi
cmovll %edi, %edx
cmovll %esi, %ecx
jmp .LBB3_6
.p2align 4, 0x90
.LBB3_7: # %_Z6minKeyPiPb.exit.i
# in Loop: Header=BB3_3 Depth=1
movslq %ecx, %rdx
movb $1, (%rsp,%rdx)
imulq $104, %rdx, %rdx
xorl %esi, %esi
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_12: # in Loop: Header=BB3_8 Depth=2
incq %rsi
cmpq $26, %rsi
je .LBB3_13
.LBB3_8: # Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movl .L__const.main.graph(%rdx,%rsi,4), %edi
testl %edi, %edi
je .LBB3_12
# %bb.9: # in Loop: Header=BB3_8 Depth=2
cmpb $0, (%rsp,%rsi)
jne .LBB3_12
# %bb.10: # in Loop: Header=BB3_8 Depth=2
cmpl 32(%rsp,%rsi,4), %edi
jge .LBB3_12
# %bb.11: # in Loop: Header=BB3_8 Depth=2
movl %ecx, 144(%rsp,%rsi,4)
movl %edi, 32(%rsp,%rsi,4)
jmp .LBB3_12
.LBB3_14: # %_Z7primMSTPA26_i.exit
leaq 144(%rsp), %rdi
movl $.L__const.main.graph, %edx
callq _Z16kMstClusterPrintPiiPA26_i
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\t"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%2d - %2d \t%3d \n"
.size .L.str.2, 17
.type .L__const.main.graph,@object # @__const.main.graph
.section .rodata,"a",@progbits
.p2align 4, 0x0
.L__const.main.graph:
.long 0 # 0x0
.long 4 # 0x4
.long 0 # 0x0
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 9 # 0x9
.long 0 # 0x0
.long 10 # 0xa
.zero 56
.long 4 # 0x4
.long 0 # 0x0
.long 29 # 0x1d
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 11 # 0xb
.zero 60
.long 0 # 0x0
.long 29 # 0x1d
.long 0 # 0x0
.long 8 # 0x8
.zero 88
.long 0 # 0x0
.long 0 # 0x0
.long 8 # 0x8
.long 0 # 0x0
.long 6 # 0x6
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 17 # 0x11
.long 6 # 0x6
.zero 56
.long 10 # 0xa
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 9 # 0x9
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 21 # 0x15
.zero 52
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 9 # 0x9
.long 0 # 0x0
.long 24 # 0x18
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 12 # 0xc
.zero 48
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 24 # 0x18
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 16 # 0x10
.zero 44
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 12 # 0xc
.zero 40
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 6 # 0x6
.zero 64
.long 9 # 0x9
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 6 # 0x6
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 26 # 0x1a
.zero 36
.long 0 # 0x0
.long 11 # 0xb
.long 0 # 0x0
.long 17 # 0x11
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 3 # 0x3
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 0 # 0x0
.long 6 # 0x6
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 8 # 0x8
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 27 # 0x1b
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 21 # 0x15
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 8 # 0x8
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 8 # 0x8
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 12 # 0xc
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 16 # 0x10
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 16 # 0x10
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 3 # 0x3
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 17 # 0x11
.long 25 # 0x19
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 12 # 0xc
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 3 # 0x3
.zero 44
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 26 # 0x1a
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 19 # 0x13
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 9 # 0x9
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 19 # 0x13
.long 0 # 0x0
.long 24 # 0x18
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 16 # 0x10
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 27 # 0x1b
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 24 # 0x18
.long 0 # 0x0
.long 0 # 0x0
.long 13 # 0xd
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 3 # 0x3
.long 0 # 0x0
.long 0 # 0x0
.long 16 # 0x10
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 13 # 0xd
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 8 # 0x8
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 13 # 0xd
.long 0 # 0x0
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 10 # 0xa
.long 0 # 0x0
.long 4 # 0x4
.long 0 # 0x0
.long 0 # 0x0
.long 23 # 0x17
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 17 # 0x11
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 4 # 0x4
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 25 # 0x19
.zero 44
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 30 # 0x1e
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 0 # 0x0
.long 9 # 0x9
.long 16 # 0x10
.long 0 # 0x0
.long 13 # 0xd
.long 0 # 0x0
.long 23 # 0x17
.long 0 # 0x0
.long 0 # 0x0
.long 30 # 0x1e
.long 0 # 0x0
.size .L__const.main.graph, 2704
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <sstream>
#include <fstream>
#include <set>
#include <iostream>
#include <map>
#include <vector>
#include <iostream>
#include <bits/stdc++.h>
#include <sstream>
#include <ctime>
#include <cstdint>
#include <stdint.h>
#define SQUEEZE 32
#define DELIMITR " "
#define IS_CHANGED 1
#define NOT_CHANGED 0
#define BLOCK_SIZE 32
using namespace std;
using String = std::string;
#include <assert.h>
#include <stdio.h>
#include <stdint.h>
#define CHANGED 1
#define NOT_CHANGED 0
#define lsb(i) ((i) & -(i)) // return least significant bit
#define BITS sizeof(__uint32_t) * 8// aka 32
uint32_t ** allocate_tables(int num_tables,int num_rows,int num_cols){
uint32_t ** d_ppcPtr, *d_pcPtr;
cudaMalloc(&d_ppcPtr, sizeof(uint32_t*) * num_tables);
for(int i = 0; i < num_tables; i ++)
{
cudaMalloc(&d_pcPtr, sizeof(uint32_t) * num_rows *num_cols );
cudaMemset(d_pcPtr, 0, sizeof(uint32_t) * num_rows *num_cols );
cudaMemcpy(&d_ppcPtr[i], &d_pcPtr, sizeof(uint32_t*), cudaMemcpyHostToDevice);
}
return d_ppcPtr;
}
void delete_tables(uint32_t**tables,int num_tables){
uint32_t *d_pcPtr;
for(int i = 0; i < num_tables; i ++)
{
//cudaMemcpy(&d_pcPtr,&tables[i], sizeof(uint32_t*), cudaMemcpyHostToDevice);
cudaMemcpy(&d_pcPtr,&tables[i], sizeof(uint32_t*), cudaMemcpyDeviceToHost);
cudaFree(d_pcPtr);
}
cudaFree(tables);
}
//return the next number with the same number of bits
__device__ int snoob(int i)
{
int least = lsb(i);
int ripple = i + least;
return (((ripple ^ i) >> 2) / least) | ripple;
}
#define K 8
#define BLOCK_SIZE 32
/*
* For C=AXB make part of table
* lookup_tables part table
* cols - cols for current cols size of part of table
* rows - rows in A,B,C
* tables_num in nums of tables
* real_cols cols in A,B,C
* offset - for what part of table
*/
__global__ void make_table(uint32_t *B, uint32_t ** lookup_tables, int cols, int rows, int tables_num, int real_cols, int offset) {
//каждый элемент считает часть таблицу (256 элементов) 8 элементов в матр-це б
int x_col = blockIdx.x * BLOCK_SIZE + threadIdx.x; // позиция в колонке этого потока
int y_row = (blockIdx.y * BLOCK_SIZE + threadIdx.y)*K; // позиция в строке в таблице B самая верхняя
int twokey = (1<<K);
int i;
int least,rest;
if(x_col >= cols || y_row >= rows ) {
// если поток выходит за рамки нашей таблицы по ширине, то ему ничего не надо делать
return;
}
uint32_t *T = lookup_tables[blockIdx.y * BLOCK_SIZE + threadIdx.y]; //pointer to table offset for case when too large num tables
T[x_col] = 0; // row with 000000000...
// fill when 1 bit
#pragma unroll
for(int j = 0; j < K; j++) {
i = 1<<(j);
T[i * cols + x_col] = B[ (y_row + j) * real_cols + x_col + offset];
}//kk
// fill when 2 and so on...
#pragma unroll
for(int h = 2;h <= K; h++) {
// iterate all integers with h bits, and < 2^k
i = (1 << h) - 1;
for (;i < twokey; i = snoob(i)) {
least = lsb(i);
rest = i - least;
//T[least] and T[rest] already calculated
T[i * cols + x_col ] = T[ least* cols + x_col] | T[ rest*cols + x_col];
}
}
}
#define BLOCK_SIZE_COL 32
#define BLOCK_SIZE_ROW 32
__device__ int get_actual_key(uint32_t composite_key,int j){
return (0xFF) & (composite_key >> (8 * j));
}
__device__ uint32_t is_changed_matrix = 0;
/*
* ВАЖНО: Если C и A одна и та же матрица, необходимо заменить одну из них копией, а потом поинетр перекинуть
* For C=AXB perform multiplication over subring F2
* lookup_tables part table
* rows - rows in A,B,C
* cols - cols in A,B,C
* full_steps nums of steps
* small_steps small_steps
* offset - for what part of C we calculate
* is_changed - flag that determine wheather matrix changed during multiplication
*
* настройка ядер для умножения
* dim3 dimBlock_m4ri(BLOCK_SIZE_COL,BLOCK_SIZE_ROW);
*
* настройка для умножения из полного цикла
* grid_x = table_cols_n /BLOCK_SIZE_COL;
* if(table_cols_n%BLOCK_SIZE_COL!=0)grid_x++;
* grid_y = rows/BLOCK_SIZE_ROW;
* if(rows%BLOCK_SIZE_ROW!=0)grid_y++;
* dim3 dimGrid_m4ri_nums(grid_x,grid_y);
*
* настройка для последнего умножения
* grid_x = table_cols_last/BLOCK_SIZE_COL;
* if(table_cols_last%BLOCK_SIZE_COL!=0)grid_x++;
* dim3 dimGrid_m4ri_last(grid_x,grid_y);
*
* Пример
* // full_step = table_cols_n/BLOCK_SIZE_COL;
* // small_step = table_cols_n%BLOCK_SIZE_COL;
* // offset = i*table_cols_n
* for(int i = 0;i < num_launches;i++){
* make_table<<<dimGrid_table_nums,dimBlock_table_kernel>>>(B,tables_n,table_cols_n,rows,num_tables,cols,i*table_cols_n);
* cudaDeviceSynchronize();
* m4ri_mul<<<dimGrid_m4ri_nums,dimBlock_m4ri>>>(A,C,tables_n,rows,cols,table_cols_n,table_cols_n/BLOCK_SIZE_COL,table_cols_n%BLOCK_SIZE_COL,i*table_cols_n,is_changed_device);
* cudaDeviceSynchronize();
* }
* // full_step = table_cols_last/BLOCK_SIZE_COL;
* // small_step = table_cols_last%BLOCK_SIZE_COL;
* // offset = num_launches*table_cols_n
* if(table_cols_last != 0){
*
* make_table<<<dimGrid_table_last,dimBlock_table_kernel>>>(B,tables_last,table_cols_last,rows,num_tables,cols,num_launches*table_cols_n);
* cudaDeviceSynchronize();
* m4ri_mul<<<dimGrid_m4ri_last,dimBlock_m4ri>>>(A,C,tables_last,rows,cols,table_cols_last,table_cols_last/BLOCK_SIZE_COL,table_cols_last%BLOCK_SIZE_COL,num_launches*table_cols_n,is_changed_device);
* cudaDeviceSynchronize();
* }
*
*/
__global__ void m4ri_mul(uint32_t *A, uint32_t *C, uint32_t **lookup_tables,int rows, int cols,int cols_table,int full_steps,int small_step,int offset) {
// каждый поток заполняет 1 элемент в в матрице С
__shared__ uint32_t local_A[BLOCK_SIZE_ROW][BLOCK_SIZE_COL];
int col_x = threadIdx.x + blockIdx.x * BLOCK_SIZE_COL + offset; // where in C
int row_y = threadIdx.y + blockIdx.y * BLOCK_SIZE_ROW; // where in C
int last = cols % BLOCK_SIZE_COL;// определяет сколько при неполном надо ключей набирать
int col_in_T = threadIdx.x + blockIdx.x * BLOCK_SIZE_COL;// по совместительству сколько эл-ов максимльно мы сейчас можем обработать
uint32_t *T;
uint32_t composite_key;
int actual_key;
uint32_t oldC;
if(col_x < cols && col_in_T < cols_table && row_y < rows) {
oldC = C[row_y * cols + col_x];
} else {
oldC = 0;
}
uint32_t tmp;
uint32_t value = 0;
#pragma unroll
for(int i = 0; i < full_steps; i++) {
// все полные прогоны по ключам
tmp = __brev(A[ row_y * cols + threadIdx.x + i * BLOCK_SIZE_COL]); // reverse
local_A[threadIdx.y][threadIdx.x] = tmp;
__syncthreads();
for(int t = 0; t < BLOCK_SIZE_COL; t++) {
composite_key = local_A[threadIdx.y][t];
for(int j = 0; j < 4;j++) {
T = lookup_tables[BLOCK_SIZE_COL * i*4 + t*4 + j];
actual_key = get_actual_key(composite_key,j);
value |= T[actual_key * cols_table + col_in_T];//add if вроде не надо
}
}
}
__syncthreads();
if(small_step) {
int cur_step = full_steps;
if(threadIdx.x + cur_step * BLOCK_SIZE_COL < cols && row_y < rows){
tmp = __brev(A[ row_y * cols + threadIdx.x + cur_step * BLOCK_SIZE_COL]); // reverse
local_A[threadIdx.y][threadIdx.x] = tmp;
}
__syncthreads();
//потоки которые выхлжят им нечего делать, свой вклад в загрузку они уже внесли
if(col_x >= cols || col_in_T >= cols_table || row_y >= rows) {
return;
}
for(int t = 0; t < last; t++) {
composite_key = local_A[threadIdx.y][t];
for(int j = 0; j < 4;j++) {
T = lookup_tables[cur_step * BLOCK_SIZE_COL * 4 + t*4 + j];
actual_key = get_actual_key(composite_key,j);
value |= T[actual_key * cols_table + col_in_T];
}
}
}
value = value|oldC;
if(is_changed_matrix == NOT_CHANGED && value!=oldC){
is_changed_matrix = CHANGED;
}
if(col_x < cols && row_y < rows && col_in_T < cols_table && value != oldC) {
C[row_y * cols + col_x] = oldC | value;
}
}
uint32_t * allocate_matrix_device(int rows,int cols){
uint32_t *matrix;
cudaMalloc((void **) &matrix, sizeof(uint32_t)*rows*cols);
return matrix;
}
uint32_t * allocate_matrix_host(int rows,int cols) {
// allocate memory in host RAM
uint32_t *matrix;
cudaMallocHost((void **) &matrix, sizeof(uint32_t)*rows * cols);
return matrix;
}
// a =cb и таков порядок аргубемнов
int wrapper_m4ri(uint32_t *a,uint32_t *c,uint32_t *b,int rows,int cols){
int table_cols_max = cols;
int num_tables = rows/K;
int num_launches = cols/table_cols_max;
int table_cols_n = table_cols_max;
int table_cols_last = cols % table_cols_max;
uint32_t * a_d = allocate_matrix_device(rows,cols);
uint32_t * b_d = allocate_matrix_device(rows,cols);
uint32_t * c_d = allocate_matrix_device(rows,cols);
cudaMemcpy( a_d,a, sizeof(uint32_t)*rows*cols, cudaMemcpyHostToDevice);
cudaMemcpy( b_d,b, sizeof(uint32_t)*rows*cols, cudaMemcpyHostToDevice);
cudaMemcpy( c_d,c, sizeof(uint32_t)*rows*cols, cudaMemcpyHostToDevice);
// указатель измененности
uint32_t *is_changed_host = allocate_matrix_host(1,1);
*is_changed_host = NOT_CHANGED;
cudaMemcpyToSymbol(is_changed_matrix, is_changed_host, sizeof(uint32_t),0,cudaMemcpyHostToDevice);
// настройка ядер для функции создания таблиц
dim3 dimBlock_table_kernel(BLOCK_SIZE,BLOCK_SIZE);// для всех вызовов создания таблиц
//настройка для таблиц из полного цикла
uint32_t grid_x = table_cols_n/BLOCK_SIZE;
if(table_cols_n%BLOCK_SIZE!=0) grid_x++;
uint32_t grid_y = rows/(BLOCK_SIZE*K);
if(rows%(BLOCK_SIZE*K)!=0) grid_y++;
dim3 dimGrid_table_nums(grid_x,grid_y); //для запуска по батчам создание таблиц
// настройка для последней таблицы
grid_x = table_cols_last/BLOCK_SIZE;
if(table_cols_last % BLOCK_SIZE!=0) grid_x++;
dim3 dimGrid_table_last(grid_x,grid_y);
// настройка ядер для умножения
dim3 dimBlock_m4ri(BLOCK_SIZE_COL,BLOCK_SIZE_ROW);
// настройка для умножения из полного цикла
grid_x = table_cols_n /BLOCK_SIZE_COL;
if(table_cols_n%BLOCK_SIZE_COL!=0)grid_x++;
grid_y = rows/BLOCK_SIZE_ROW;
if(rows%BLOCK_SIZE_ROW!=0)grid_y++;
dim3 dimGrid_m4ri_nums(grid_x,grid_y);
// настройка для последнего умножения
grid_x = table_cols_last/BLOCK_SIZE_COL;
if(table_cols_last%BLOCK_SIZE_COL!=0)grid_x++;
dim3 dimGrid_m4ri_last(grid_x,grid_y);
//allocate tables
uint32_t ** tables_n;// = allocate_tables(num_tables,257*table_cols_n);
uint32_t ** tables_last;// = allocate_tables(num_tables,257*table_cols_last);
if(num_launches != 0){
tables_n = allocate_tables(num_tables,256,table_cols_n);
}
if(table_cols_last != 0){
tables_last = allocate_tables(num_tables,256,table_cols_last);
}
for(int i = 0;i < num_launches;i++){
make_table<<<dimGrid_table_nums,dimBlock_table_kernel>>>
(b_d,tables_n,table_cols_n,rows,num_tables,cols,i*table_cols_n);
cudaDeviceSynchronize();
m4ri_mul<<<dimGrid_m4ri_nums,dimBlock_m4ri>>>
(c_d,a_d,tables_n,rows,cols,table_cols_n,cols/BLOCK_SIZE_COL,cols%BLOCK_SIZE_COL,i*table_cols_n);
cudaDeviceSynchronize();
}
if(table_cols_last != 0){
make_table<<<dimGrid_table_last,dimBlock_table_kernel>>>
(b_d,tables_last,table_cols_last,rows,num_tables,cols,num_launches*table_cols_n);
cudaDeviceSynchronize();
m4ri_mul<<<dimGrid_m4ri_last,dimBlock_m4ri>>>
(c_d,a_d,tables_last,rows,cols,table_cols_last,cols/BLOCK_SIZE_COL,cols%BLOCK_SIZE_COL,num_launches*table_cols_n);
cudaDeviceSynchronize();
}
if(num_launches!=0){
delete_tables(tables_n, num_launches);
}
if(table_cols_last!=0){
delete_tables(tables_last,table_cols_last);
}
cudaMemcpy( a,a_d, sizeof(uint32_t)*rows*cols, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
cudaMemcpyFromSymbol(is_changed_host,is_changed_matrix, sizeof(uint32_t), 0,cudaMemcpyDeviceToHost);
cudaFree(a_d);
cudaFree(b_d);
cudaFree(c_d);
int flag = *is_changed_host;
cudaFreeHost(is_changed_host);
return flag;
}
class Grammar {
public:
std::set<String> nonterminalSet;
std::set<String> terminalSet;
std::map<String, std::set<std::pair<String, String >>> productionsDouble;
std::map<std::pair<String, String>, std::set<String >> reverseProductionsDouble;
std::map<String, std::set<String>> productionsUnary;//NonTerminal-> Set of Terminal
std::map<String, std::set<String>> reverseProductionsUnary;// Terminal -> Set of non terminal
std::map<String, std::set<String>> nonTerminalToBodyOfProduction;// NonTerminal ->Set nont termianl aka nontermina+ eleme from set or vice versa is key for reverseProduction
void parse_grammar(const String &filename, const String &delimiter = " ") {
std::ifstream file(filename);
if (file.is_open()) {
std::string line;
while (getline(file, line)) {
process_grammar_line(line, delimiter);
}
file.close();
}
make_reverse_relations();
make_nonTerminalToBodyOfProduction();
}
private:
void make_reverse_relations() {
//reverseProductionUnary
make_unary_reverse_relation();
make_double_reverse_relation();
}
void process_grammar_line(String line, const String &delimiter = " ") {
size_t pos = 0;
std::string token[2];
int c = 0;
while ((pos = line.find(delimiter)) != std::string::npos) {
token[c] = line.substr(0, pos);
line.erase(0, pos + delimiter.length());
c++;
}
String head = token[0];
if (c == 2) {
String left_terminal = token[1];
String right_terminal = line;
auto tail = make_pair(left_terminal, right_terminal);
this->nonterminalSet.insert(head);// нетерминалы множество
this->nonterminalSet.insert(left_terminal);
this->nonterminalSet.insert(right_terminal);
if (this->productionsDouble.count(head) == 1) { // продукции
auto iter = this->productionsDouble.find(head);
iter->second.insert(tail);
} else {
this->productionsDouble.insert(make_pair(head, set<pair<String, String >>({tail})));
}
} else if (c == 1) {
const String &terminal = line;
this->nonterminalSet.insert(head);
if (this->productionsUnary.count(head) == 1) {
auto iter = this->productionsUnary.find(head);
iter->second.insert(terminal);
} else {
this->productionsUnary.insert(make_pair(head, set<String>({terminal})));
}
this->terminalSet.insert(terminal);
} else {
throw "Error while process line from grammar";
}
}
void make_unary_reverse_relation() {
for (auto nonterminal: this->productionsUnary) {
for (auto terminal: nonterminal.second) {
if (reverseProductionsUnary.count(terminal) == 1) {
reverseProductionsUnary.find(terminal)->second.insert(nonterminal.first);
} else {
reverseProductionsUnary.insert(make_pair(terminal, set<String>({nonterminal.first})));
}
}
}
}
void make_double_reverse_relation() {
for (auto head:this->productionsDouble) {
for (auto elem_pair:head.second) {
if (reverseProductionsDouble.count(elem_pair) == 1) {
reverseProductionsDouble.find(elem_pair)->second.insert(head.first);
} else {
reverseProductionsDouble.insert(make_pair(elem_pair, set<String>({head.first})));
}
}
}
}
void make_nonTerminalToBodyOfProduction() {
for (auto leftNonTerminal: nonterminalSet) {
for (auto rightNonTerminal:nonterminalSet) {
auto key = make_pair(leftNonTerminal, rightNonTerminal);
if (reverseProductionsDouble.count(key)) {
if (nonTerminalToBodyOfProduction.count(leftNonTerminal)) {
nonTerminalToBodyOfProduction.find(leftNonTerminal)->second.insert(rightNonTerminal);
} else {
nonTerminalToBodyOfProduction.insert(
make_pair(leftNonTerminal, set<String>({rightNonTerminal})));
}
if (nonTerminalToBodyOfProduction.count(rightNonTerminal)) {
nonTerminalToBodyOfProduction.find(rightNonTerminal)->second.insert(leftNonTerminal);
} else {
nonTerminalToBodyOfProduction.insert(
make_pair(rightNonTerminal, set<String>({leftNonTerminal})));
}
} else {
}
}
}
}
};
class Edge {
public:
int from;
set<String> label;
int to;
Edge(int from, int to) {
this->from = from;
this->to = to;
}
};
class Graph {
public:
vector<Edge> edges;
int max_number_of_vertex;
int multiple_by_32; // is maxnumber if maxnumber % 32=0 or max_number+ (32 -maxnumber % 32)
void parse_graph(const String &filename, const String &delimiter = " ") {
std::ifstream file(filename);
int max_vertex = 0;
if (file.is_open()) {
std::string line;
while (getline(file, line)) {
size_t pos = 0;
std::string token[2];
int c = 0;
while ((pos = line.find(delimiter)) != std::string::npos) {
token[c] = line.substr(0, pos);
line.erase(0, pos + delimiter.length());
c++;
}
if (c == 2) {
int l = std::stoi(token[0]);
int r = std::stoi(line);
max_vertex = std::max(std::max(l, r), max_vertex);
Edge edge = Edge(l, r);
edge.label.insert(token[1]);
edges.push_back(edge);
} else {
throw "Error while process line from graph";
}
}
file.close();
} else{
throw "Error File not found";
}
max_vertex+=1;// т.к у нас верщины присутствует от 0 до max_vertex включетельно
max_number_of_vertex = max_vertex;
if (max_vertex % SQUEEZE == 0) {
multiple_by_32 = max_vertex;
} else {
int quout = max_vertex % SQUEEZE;
multiple_by_32 = max_vertex + SQUEEZE - quout;
}
}
void replace_terminals_to_noterminals(Grammar &grammar) {
for (auto &edge : edges) {
set<String> tmp;
for (const String &key:edge.label) {
if (grammar.reverseProductionsUnary.count(key) == 1) {
tmp.insert(grammar.reverseProductionsUnary.find(key)->second.begin(),
grammar.reverseProductionsUnary.find(key)->second.end());
}
}
edge.label.clear();
edge.label.insert(tmp.begin(), tmp.end());
}
}
};
void delete_matrix_device(uint32_t * matrix) {
cudaFree(matrix);
}
void delete_matrix_host(uint32_t * matrix) {
cudaFreeHost(matrix);
}
struct Matrix {
uint32_t *matrix_host;
uint32_t *matrix_device;
uint32_t *matrix_squeezed_host;
uint32_t *is_changed_host;
};
struct Table {
uint32_t *table_n;
uint32_t *table_last;
};
class Solution {
public:
Graph graph;
Grammar grammar;
map<String, Matrix> nonTerminalToMatrix;
Table table;
Solution(const String &filename_grammar, const String &filename_graph, const String &delimiter = " ") {
// add table size as parameter
graph.parse_graph(filename_graph, delimiter);
grammar.parse_grammar(filename_grammar, delimiter);
graph.replace_terminals_to_noterminals(grammar);
construct_and_fill_matrices_for_nonterminal_test();
}
void output_in(String filename ) {ifstream input(filename);
vector<String > res(grammar.nonterminalSet.begin(),grammar.nonterminalSet.end());
sort(res.begin(),res.end());
ofstream outputfile;
outputfile.open(filename);
for (auto &nonterminal: res) {
auto & matrix = nonTerminalToMatrix.at(nonterminal);
outputfile << nonterminal;
bool *bitArray = Decompress(matrix.matrix_host, graph.max_number_of_vertex);
for (int i = 0; i < graph.max_number_of_vertex; ++i) {
for (int j = 0; j < graph.max_number_of_vertex; ++j) {
if (bitArray[i * graph.max_number_of_vertex + j] != 0) {
outputfile << ' ' << i << ' ' << j;
}
}
}
outputfile << endl;
}
outputfile.close();
}
void compute_result() {
// initial setup
set<String> changed_matrices = set<String>();
for (auto &elem: nonTerminalToMatrix) {
if (*elem.second.is_changed_host == IS_CHANGED) {
changed_matrices.insert(elem.first);
}
}
if (changed_matrices.empty()) {
return;//
}
while (true) {
set<String> new_changed_matrices = set<String>();
for (auto &nonterminal: changed_matrices) {
if (grammar.nonTerminalToBodyOfProduction.count(nonterminal)) {
auto const &possibly_second_key_set = grammar.nonTerminalToBodyOfProduction.find(
nonterminal)->second;
// перемножаем все пары матриц, в теле которых стоит этот нетерминал если он там присутствует
for (const auto &sec: possibly_second_key_set) {
auto key1 = make_pair(nonterminal, sec);
auto key2 = make_pair(sec, nonterminal);
if (grammar.reverseProductionsDouble.count(key1)) {
auto iter = grammar.reverseProductionsDouble.find(key1);
for (const auto &res: iter->second) {
auto is_changed = perform_matrix_mul(res, iter->first.first, iter->first.second);
if (is_changed) {
new_changed_matrices.insert(res);
}
}
}
if (grammar.reverseProductionsDouble.count(key2)) {
auto iter = grammar.reverseProductionsDouble.find(key2);
for (const auto &res: iter->second) {
auto is_changed = perform_matrix_mul(res, iter->first.first, iter->first.second);
if (is_changed) {
new_changed_matrices.insert(res);
}
}
}
}
}
}
if (new_changed_matrices.empty()) {
//copy
break;
} else {
changed_matrices = new_changed_matrices;
//update matrices
}
//transfer
}
}
int packedByBlocksNumber(int N, int size) {
return (N / size + (N % size == 0 ? 0 : 1));
}
bool * Decompress(uint32_t * c_arr, uint32_t N) {
// int num_rows = N;
int num_columns = packedByBlocksNumber(N, 32);
bool * arr = reinterpret_cast<bool *>(calloc(N * N, sizeof(bool)));
uint32_t el;
for (int r = 0; r < N; r++) {
for (int c = 0; c < N; c++) {
el = c_arr[r * num_columns + (c / 32)];
if (el & (1 << (31 - (c % 32)))) {
arr[r * N + c] = 1;
}
}
}
return arr;
}
private:
void construct_and_fill_matrices_for_nonterminal_test() {
int rows = this->graph.multiple_by_32;
int cols = this->graph.multiple_by_32/32;
for (auto nonterminal: grammar.nonterminalSet) {
Matrix matrix = Matrix();
matrix.matrix_host = allocate_matrix_host(rows,cols); //alloc_matrix_host_with_zeros(rows, cols);
matrix.is_changed_host = allocate_matrix_host(1,1);
*matrix.is_changed_host = NOT_CHANGED;
this->nonTerminalToMatrix.insert(make_pair(nonterminal, matrix));
}// заполнили нулями для хоста
for (auto &edge:graph.edges) {
auto i = edge.from;
auto j = edge.to;
for (const auto &nonterminal:edge.label) { // заполнилии 1 в i,j для матриц на метках из i в j есть этот нетерминал
auto &matrix = this->nonTerminalToMatrix.find(nonterminal)->second;
write_bit(matrix.matrix_host,i,j,cols);
if (*matrix.is_changed_host == NOT_CHANGED) {
*matrix.is_changed_host = IS_CHANGED;
}
}
}
}
void write_bit(uint32_t *m, int i, int j,int cols){
m[i * cols + (j / 32)] |= (1 << (31 - (j % 32)));
}
// A = C*B
int perform_matrix_mul(const String &head, const String &left, const String &right) {
int rows = graph.multiple_by_32;
int cols = graph.multiple_by_32/32;
auto &A = this->nonTerminalToMatrix.at(head);
auto &C = this->nonTerminalToMatrix.at(left);
auto &B = this->nonTerminalToMatrix.at(right);
*A.is_changed_host = 0;
// a =cb и таков порядок аргубемнов
int res = wrapper_m4ri(A.matrix_host,C.matrix_host,B.matrix_host,rows,cols);
*A.is_changed_host = res;
return res;
}
};
int main(int argc, char* argv[]) {
auto solution = Solution(argv[1], argv[2], DELIMITR);
clock_t begin = clock();
solution.compute_result();
clock_t end = clock();
double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
solution.output_in(argv[3]);
cout<<elapsed_secs<<endl;
}
|
#include <hip/hip_runtime.h>
#include <sstream>
#include <fstream>
#include <set>
#include <iostream>
#include <map>
#include <vector>
#include <iostream>
#include <bits/stdc++.h>
#include <sstream>
#include <ctime>
#include <cstdint>
#include <stdint.h>
#define SQUEEZE 32
#define DELIMITR " "
#define IS_CHANGED 1
#define NOT_CHANGED 0
#define BLOCK_SIZE 32
using namespace std;
using String = std::string;
#include <assert.h>
#include <stdio.h>
#include <stdint.h>
#define CHANGED 1
#define NOT_CHANGED 0
#define lsb(i) ((i) & -(i)) // return least significant bit
#define BITS sizeof(__uint32_t) * 8// aka 32
uint32_t ** allocate_tables(int num_tables,int num_rows,int num_cols){
uint32_t ** d_ppcPtr, *d_pcPtr;
hipMalloc(&d_ppcPtr, sizeof(uint32_t*) * num_tables);
for(int i = 0; i < num_tables; i ++)
{
hipMalloc(&d_pcPtr, sizeof(uint32_t) * num_rows *num_cols );
hipMemset(d_pcPtr, 0, sizeof(uint32_t) * num_rows *num_cols );
hipMemcpy(&d_ppcPtr[i], &d_pcPtr, sizeof(uint32_t*), hipMemcpyHostToDevice);
}
return d_ppcPtr;
}
void delete_tables(uint32_t**tables,int num_tables){
uint32_t *d_pcPtr;
for(int i = 0; i < num_tables; i ++)
{
//cudaMemcpy(&d_pcPtr,&tables[i], sizeof(uint32_t*), cudaMemcpyHostToDevice);
hipMemcpy(&d_pcPtr,&tables[i], sizeof(uint32_t*), hipMemcpyDeviceToHost);
hipFree(d_pcPtr);
}
hipFree(tables);
}
//return the next number with the same number of bits
__device__ int snoob(int i)
{
int least = lsb(i);
int ripple = i + least;
return (((ripple ^ i) >> 2) / least) | ripple;
}
#define K 8
#define BLOCK_SIZE 32
/*
* For C=AXB make part of table
* lookup_tables part table
* cols - cols for current cols size of part of table
* rows - rows in A,B,C
* tables_num in nums of tables
* real_cols cols in A,B,C
* offset - for what part of table
*/
__global__ void make_table(uint32_t *B, uint32_t ** lookup_tables, int cols, int rows, int tables_num, int real_cols, int offset) {
//каждый элемент считает часть таблицу (256 элементов) 8 элементов в матр-це б
int x_col = blockIdx.x * BLOCK_SIZE + threadIdx.x; // позиция в колонке этого потока
int y_row = (blockIdx.y * BLOCK_SIZE + threadIdx.y)*K; // позиция в строке в таблице B самая верхняя
int twokey = (1<<K);
int i;
int least,rest;
if(x_col >= cols || y_row >= rows ) {
// если поток выходит за рамки нашей таблицы по ширине, то ему ничего не надо делать
return;
}
uint32_t *T = lookup_tables[blockIdx.y * BLOCK_SIZE + threadIdx.y]; //pointer to table offset for case when too large num tables
T[x_col] = 0; // row with 000000000...
// fill when 1 bit
#pragma unroll
for(int j = 0; j < K; j++) {
i = 1<<(j);
T[i * cols + x_col] = B[ (y_row + j) * real_cols + x_col + offset];
}//kk
// fill when 2 and so on...
#pragma unroll
for(int h = 2;h <= K; h++) {
// iterate all integers with h bits, and < 2^k
i = (1 << h) - 1;
for (;i < twokey; i = snoob(i)) {
least = lsb(i);
rest = i - least;
//T[least] and T[rest] already calculated
T[i * cols + x_col ] = T[ least* cols + x_col] | T[ rest*cols + x_col];
}
}
}
#define BLOCK_SIZE_COL 32
#define BLOCK_SIZE_ROW 32
__device__ int get_actual_key(uint32_t composite_key,int j){
return (0xFF) & (composite_key >> (8 * j));
}
__device__ uint32_t is_changed_matrix = 0;
/*
* ВАЖНО: Если C и A одна и та же матрица, необходимо заменить одну из них копией, а потом поинетр перекинуть
* For C=AXB perform multiplication over subring F2
* lookup_tables part table
* rows - rows in A,B,C
* cols - cols in A,B,C
* full_steps nums of steps
* small_steps small_steps
* offset - for what part of C we calculate
* is_changed - flag that determine wheather matrix changed during multiplication
*
* настройка ядер для умножения
* dim3 dimBlock_m4ri(BLOCK_SIZE_COL,BLOCK_SIZE_ROW);
*
* настройка для умножения из полного цикла
* grid_x = table_cols_n /BLOCK_SIZE_COL;
* if(table_cols_n%BLOCK_SIZE_COL!=0)grid_x++;
* grid_y = rows/BLOCK_SIZE_ROW;
* if(rows%BLOCK_SIZE_ROW!=0)grid_y++;
* dim3 dimGrid_m4ri_nums(grid_x,grid_y);
*
* настройка для последнего умножения
* grid_x = table_cols_last/BLOCK_SIZE_COL;
* if(table_cols_last%BLOCK_SIZE_COL!=0)grid_x++;
* dim3 dimGrid_m4ri_last(grid_x,grid_y);
*
* Пример
* // full_step = table_cols_n/BLOCK_SIZE_COL;
* // small_step = table_cols_n%BLOCK_SIZE_COL;
* // offset = i*table_cols_n
* for(int i = 0;i < num_launches;i++){
* make_table<<<dimGrid_table_nums,dimBlock_table_kernel>>>(B,tables_n,table_cols_n,rows,num_tables,cols,i*table_cols_n);
* cudaDeviceSynchronize();
* m4ri_mul<<<dimGrid_m4ri_nums,dimBlock_m4ri>>>(A,C,tables_n,rows,cols,table_cols_n,table_cols_n/BLOCK_SIZE_COL,table_cols_n%BLOCK_SIZE_COL,i*table_cols_n,is_changed_device);
* cudaDeviceSynchronize();
* }
* // full_step = table_cols_last/BLOCK_SIZE_COL;
* // small_step = table_cols_last%BLOCK_SIZE_COL;
* // offset = num_launches*table_cols_n
* if(table_cols_last != 0){
*
* make_table<<<dimGrid_table_last,dimBlock_table_kernel>>>(B,tables_last,table_cols_last,rows,num_tables,cols,num_launches*table_cols_n);
* cudaDeviceSynchronize();
* m4ri_mul<<<dimGrid_m4ri_last,dimBlock_m4ri>>>(A,C,tables_last,rows,cols,table_cols_last,table_cols_last/BLOCK_SIZE_COL,table_cols_last%BLOCK_SIZE_COL,num_launches*table_cols_n,is_changed_device);
* cudaDeviceSynchronize();
* }
*
*/
__global__ void m4ri_mul(uint32_t *A, uint32_t *C, uint32_t **lookup_tables,int rows, int cols,int cols_table,int full_steps,int small_step,int offset) {
// каждый поток заполняет 1 элемент в в матрице С
__shared__ uint32_t local_A[BLOCK_SIZE_ROW][BLOCK_SIZE_COL];
int col_x = threadIdx.x + blockIdx.x * BLOCK_SIZE_COL + offset; // where in C
int row_y = threadIdx.y + blockIdx.y * BLOCK_SIZE_ROW; // where in C
int last = cols % BLOCK_SIZE_COL;// определяет сколько при неполном надо ключей набирать
int col_in_T = threadIdx.x + blockIdx.x * BLOCK_SIZE_COL;// по совместительству сколько эл-ов максимльно мы сейчас можем обработать
uint32_t *T;
uint32_t composite_key;
int actual_key;
uint32_t oldC;
if(col_x < cols && col_in_T < cols_table && row_y < rows) {
oldC = C[row_y * cols + col_x];
} else {
oldC = 0;
}
uint32_t tmp;
uint32_t value = 0;
#pragma unroll
for(int i = 0; i < full_steps; i++) {
// все полные прогоны по ключам
tmp = __brev(A[ row_y * cols + threadIdx.x + i * BLOCK_SIZE_COL]); // reverse
local_A[threadIdx.y][threadIdx.x] = tmp;
__syncthreads();
for(int t = 0; t < BLOCK_SIZE_COL; t++) {
composite_key = local_A[threadIdx.y][t];
for(int j = 0; j < 4;j++) {
T = lookup_tables[BLOCK_SIZE_COL * i*4 + t*4 + j];
actual_key = get_actual_key(composite_key,j);
value |= T[actual_key * cols_table + col_in_T];//add if вроде не надо
}
}
}
__syncthreads();
if(small_step) {
int cur_step = full_steps;
if(threadIdx.x + cur_step * BLOCK_SIZE_COL < cols && row_y < rows){
tmp = __brev(A[ row_y * cols + threadIdx.x + cur_step * BLOCK_SIZE_COL]); // reverse
local_A[threadIdx.y][threadIdx.x] = tmp;
}
__syncthreads();
//потоки которые выхлжят им нечего делать, свой вклад в загрузку они уже внесли
if(col_x >= cols || col_in_T >= cols_table || row_y >= rows) {
return;
}
for(int t = 0; t < last; t++) {
composite_key = local_A[threadIdx.y][t];
for(int j = 0; j < 4;j++) {
T = lookup_tables[cur_step * BLOCK_SIZE_COL * 4 + t*4 + j];
actual_key = get_actual_key(composite_key,j);
value |= T[actual_key * cols_table + col_in_T];
}
}
}
value = value|oldC;
if(is_changed_matrix == NOT_CHANGED && value!=oldC){
is_changed_matrix = CHANGED;
}
if(col_x < cols && row_y < rows && col_in_T < cols_table && value != oldC) {
C[row_y * cols + col_x] = oldC | value;
}
}
uint32_t * allocate_matrix_device(int rows,int cols){
uint32_t *matrix;
hipMalloc((void **) &matrix, sizeof(uint32_t)*rows*cols);
return matrix;
}
uint32_t * allocate_matrix_host(int rows,int cols) {
// allocate memory in host RAM
uint32_t *matrix;
hipHostMalloc((void **) &matrix, sizeof(uint32_t)*rows * cols, hipHostMallocDefault);
return matrix;
}
// a =cb и таков порядок аргубемнов
int wrapper_m4ri(uint32_t *a,uint32_t *c,uint32_t *b,int rows,int cols){
int table_cols_max = cols;
int num_tables = rows/K;
int num_launches = cols/table_cols_max;
int table_cols_n = table_cols_max;
int table_cols_last = cols % table_cols_max;
uint32_t * a_d = allocate_matrix_device(rows,cols);
uint32_t * b_d = allocate_matrix_device(rows,cols);
uint32_t * c_d = allocate_matrix_device(rows,cols);
hipMemcpy( a_d,a, sizeof(uint32_t)*rows*cols, hipMemcpyHostToDevice);
hipMemcpy( b_d,b, sizeof(uint32_t)*rows*cols, hipMemcpyHostToDevice);
hipMemcpy( c_d,c, sizeof(uint32_t)*rows*cols, hipMemcpyHostToDevice);
// указатель измененности
uint32_t *is_changed_host = allocate_matrix_host(1,1);
*is_changed_host = NOT_CHANGED;
hipMemcpyToSymbol(HIP_SYMBOL(is_changed_matrix), is_changed_host, sizeof(uint32_t),0,hipMemcpyHostToDevice);
// настройка ядер для функции создания таблиц
dim3 dimBlock_table_kernel(BLOCK_SIZE,BLOCK_SIZE);// для всех вызовов создания таблиц
//настройка для таблиц из полного цикла
uint32_t grid_x = table_cols_n/BLOCK_SIZE;
if(table_cols_n%BLOCK_SIZE!=0) grid_x++;
uint32_t grid_y = rows/(BLOCK_SIZE*K);
if(rows%(BLOCK_SIZE*K)!=0) grid_y++;
dim3 dimGrid_table_nums(grid_x,grid_y); //для запуска по батчам создание таблиц
// настройка для последней таблицы
grid_x = table_cols_last/BLOCK_SIZE;
if(table_cols_last % BLOCK_SIZE!=0) grid_x++;
dim3 dimGrid_table_last(grid_x,grid_y);
// настройка ядер для умножения
dim3 dimBlock_m4ri(BLOCK_SIZE_COL,BLOCK_SIZE_ROW);
// настройка для умножения из полного цикла
grid_x = table_cols_n /BLOCK_SIZE_COL;
if(table_cols_n%BLOCK_SIZE_COL!=0)grid_x++;
grid_y = rows/BLOCK_SIZE_ROW;
if(rows%BLOCK_SIZE_ROW!=0)grid_y++;
dim3 dimGrid_m4ri_nums(grid_x,grid_y);
// настройка для последнего умножения
grid_x = table_cols_last/BLOCK_SIZE_COL;
if(table_cols_last%BLOCK_SIZE_COL!=0)grid_x++;
dim3 dimGrid_m4ri_last(grid_x,grid_y);
//allocate tables
uint32_t ** tables_n;// = allocate_tables(num_tables,257*table_cols_n);
uint32_t ** tables_last;// = allocate_tables(num_tables,257*table_cols_last);
if(num_launches != 0){
tables_n = allocate_tables(num_tables,256,table_cols_n);
}
if(table_cols_last != 0){
tables_last = allocate_tables(num_tables,256,table_cols_last);
}
for(int i = 0;i < num_launches;i++){
make_table<<<dimGrid_table_nums,dimBlock_table_kernel>>>
(b_d,tables_n,table_cols_n,rows,num_tables,cols,i*table_cols_n);
hipDeviceSynchronize();
m4ri_mul<<<dimGrid_m4ri_nums,dimBlock_m4ri>>>
(c_d,a_d,tables_n,rows,cols,table_cols_n,cols/BLOCK_SIZE_COL,cols%BLOCK_SIZE_COL,i*table_cols_n);
hipDeviceSynchronize();
}
if(table_cols_last != 0){
make_table<<<dimGrid_table_last,dimBlock_table_kernel>>>
(b_d,tables_last,table_cols_last,rows,num_tables,cols,num_launches*table_cols_n);
hipDeviceSynchronize();
m4ri_mul<<<dimGrid_m4ri_last,dimBlock_m4ri>>>
(c_d,a_d,tables_last,rows,cols,table_cols_last,cols/BLOCK_SIZE_COL,cols%BLOCK_SIZE_COL,num_launches*table_cols_n);
hipDeviceSynchronize();
}
if(num_launches!=0){
delete_tables(tables_n, num_launches);
}
if(table_cols_last!=0){
delete_tables(tables_last,table_cols_last);
}
hipMemcpy( a,a_d, sizeof(uint32_t)*rows*cols, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
hipMemcpyFromSymbol(is_changed_host,HIP_SYMBOL(is_changed_matrix), sizeof(uint32_t), 0,hipMemcpyDeviceToHost);
hipFree(a_d);
hipFree(b_d);
hipFree(c_d);
int flag = *is_changed_host;
hipHostFree(is_changed_host);
return flag;
}
class Grammar {
public:
std::set<String> nonterminalSet;
std::set<String> terminalSet;
std::map<String, std::set<std::pair<String, String >>> productionsDouble;
std::map<std::pair<String, String>, std::set<String >> reverseProductionsDouble;
std::map<String, std::set<String>> productionsUnary;//NonTerminal-> Set of Terminal
std::map<String, std::set<String>> reverseProductionsUnary;// Terminal -> Set of non terminal
std::map<String, std::set<String>> nonTerminalToBodyOfProduction;// NonTerminal ->Set nont termianl aka nontermina+ eleme from set or vice versa is key for reverseProduction
void parse_grammar(const String &filename, const String &delimiter = " ") {
std::ifstream file(filename);
if (file.is_open()) {
std::string line;
while (getline(file, line)) {
process_grammar_line(line, delimiter);
}
file.close();
}
make_reverse_relations();
make_nonTerminalToBodyOfProduction();
}
private:
void make_reverse_relations() {
//reverseProductionUnary
make_unary_reverse_relation();
make_double_reverse_relation();
}
void process_grammar_line(String line, const String &delimiter = " ") {
size_t pos = 0;
std::string token[2];
int c = 0;
while ((pos = line.find(delimiter)) != std::string::npos) {
token[c] = line.substr(0, pos);
line.erase(0, pos + delimiter.length());
c++;
}
String head = token[0];
if (c == 2) {
String left_terminal = token[1];
String right_terminal = line;
auto tail = make_pair(left_terminal, right_terminal);
this->nonterminalSet.insert(head);// нетерминалы множество
this->nonterminalSet.insert(left_terminal);
this->nonterminalSet.insert(right_terminal);
if (this->productionsDouble.count(head) == 1) { // продукции
auto iter = this->productionsDouble.find(head);
iter->second.insert(tail);
} else {
this->productionsDouble.insert(make_pair(head, set<pair<String, String >>({tail})));
}
} else if (c == 1) {
const String &terminal = line;
this->nonterminalSet.insert(head);
if (this->productionsUnary.count(head) == 1) {
auto iter = this->productionsUnary.find(head);
iter->second.insert(terminal);
} else {
this->productionsUnary.insert(make_pair(head, set<String>({terminal})));
}
this->terminalSet.insert(terminal);
} else {
throw "Error while process line from grammar";
}
}
void make_unary_reverse_relation() {
for (auto nonterminal: this->productionsUnary) {
for (auto terminal: nonterminal.second) {
if (reverseProductionsUnary.count(terminal) == 1) {
reverseProductionsUnary.find(terminal)->second.insert(nonterminal.first);
} else {
reverseProductionsUnary.insert(make_pair(terminal, set<String>({nonterminal.first})));
}
}
}
}
void make_double_reverse_relation() {
for (auto head:this->productionsDouble) {
for (auto elem_pair:head.second) {
if (reverseProductionsDouble.count(elem_pair) == 1) {
reverseProductionsDouble.find(elem_pair)->second.insert(head.first);
} else {
reverseProductionsDouble.insert(make_pair(elem_pair, set<String>({head.first})));
}
}
}
}
void make_nonTerminalToBodyOfProduction() {
for (auto leftNonTerminal: nonterminalSet) {
for (auto rightNonTerminal:nonterminalSet) {
auto key = make_pair(leftNonTerminal, rightNonTerminal);
if (reverseProductionsDouble.count(key)) {
if (nonTerminalToBodyOfProduction.count(leftNonTerminal)) {
nonTerminalToBodyOfProduction.find(leftNonTerminal)->second.insert(rightNonTerminal);
} else {
nonTerminalToBodyOfProduction.insert(
make_pair(leftNonTerminal, set<String>({rightNonTerminal})));
}
if (nonTerminalToBodyOfProduction.count(rightNonTerminal)) {
nonTerminalToBodyOfProduction.find(rightNonTerminal)->second.insert(leftNonTerminal);
} else {
nonTerminalToBodyOfProduction.insert(
make_pair(rightNonTerminal, set<String>({leftNonTerminal})));
}
} else {
}
}
}
}
};
class Edge {
public:
int from;
set<String> label;
int to;
Edge(int from, int to) {
this->from = from;
this->to = to;
}
};
class Graph {
public:
vector<Edge> edges;
int max_number_of_vertex;
int multiple_by_32; // is maxnumber if maxnumber % 32=0 or max_number+ (32 -maxnumber % 32)
void parse_graph(const String &filename, const String &delimiter = " ") {
std::ifstream file(filename);
int max_vertex = 0;
if (file.is_open()) {
std::string line;
while (getline(file, line)) {
size_t pos = 0;
std::string token[2];
int c = 0;
while ((pos = line.find(delimiter)) != std::string::npos) {
token[c] = line.substr(0, pos);
line.erase(0, pos + delimiter.length());
c++;
}
if (c == 2) {
int l = std::stoi(token[0]);
int r = std::stoi(line);
max_vertex = std::max(std::max(l, r), max_vertex);
Edge edge = Edge(l, r);
edge.label.insert(token[1]);
edges.push_back(edge);
} else {
throw "Error while process line from graph";
}
}
file.close();
} else{
throw "Error File not found";
}
max_vertex+=1;// т.к у нас верщины присутствует от 0 до max_vertex включетельно
max_number_of_vertex = max_vertex;
if (max_vertex % SQUEEZE == 0) {
multiple_by_32 = max_vertex;
} else {
int quout = max_vertex % SQUEEZE;
multiple_by_32 = max_vertex + SQUEEZE - quout;
}
}
void replace_terminals_to_noterminals(Grammar &grammar) {
for (auto &edge : edges) {
set<String> tmp;
for (const String &key:edge.label) {
if (grammar.reverseProductionsUnary.count(key) == 1) {
tmp.insert(grammar.reverseProductionsUnary.find(key)->second.begin(),
grammar.reverseProductionsUnary.find(key)->second.end());
}
}
edge.label.clear();
edge.label.insert(tmp.begin(), tmp.end());
}
}
};
void delete_matrix_device(uint32_t * matrix) {
hipFree(matrix);
}
void delete_matrix_host(uint32_t * matrix) {
hipHostFree(matrix);
}
struct Matrix {
uint32_t *matrix_host;
uint32_t *matrix_device;
uint32_t *matrix_squeezed_host;
uint32_t *is_changed_host;
};
struct Table {
uint32_t *table_n;
uint32_t *table_last;
};
class Solution {
public:
Graph graph;
Grammar grammar;
map<String, Matrix> nonTerminalToMatrix;
Table table;
Solution(const String &filename_grammar, const String &filename_graph, const String &delimiter = " ") {
// add table size as parameter
graph.parse_graph(filename_graph, delimiter);
grammar.parse_grammar(filename_grammar, delimiter);
graph.replace_terminals_to_noterminals(grammar);
construct_and_fill_matrices_for_nonterminal_test();
}
void output_in(String filename ) {ifstream input(filename);
vector<String > res(grammar.nonterminalSet.begin(),grammar.nonterminalSet.end());
sort(res.begin(),res.end());
ofstream outputfile;
outputfile.open(filename);
for (auto &nonterminal: res) {
auto & matrix = nonTerminalToMatrix.at(nonterminal);
outputfile << nonterminal;
bool *bitArray = Decompress(matrix.matrix_host, graph.max_number_of_vertex);
for (int i = 0; i < graph.max_number_of_vertex; ++i) {
for (int j = 0; j < graph.max_number_of_vertex; ++j) {
if (bitArray[i * graph.max_number_of_vertex + j] != 0) {
outputfile << ' ' << i << ' ' << j;
}
}
}
outputfile << endl;
}
outputfile.close();
}
void compute_result() {
// initial setup
set<String> changed_matrices = set<String>();
for (auto &elem: nonTerminalToMatrix) {
if (*elem.second.is_changed_host == IS_CHANGED) {
changed_matrices.insert(elem.first);
}
}
if (changed_matrices.empty()) {
return;//
}
while (true) {
set<String> new_changed_matrices = set<String>();
for (auto &nonterminal: changed_matrices) {
if (grammar.nonTerminalToBodyOfProduction.count(nonterminal)) {
auto const &possibly_second_key_set = grammar.nonTerminalToBodyOfProduction.find(
nonterminal)->second;
// перемножаем все пары матриц, в теле которых стоит этот нетерминал если он там присутствует
for (const auto &sec: possibly_second_key_set) {
auto key1 = make_pair(nonterminal, sec);
auto key2 = make_pair(sec, nonterminal);
if (grammar.reverseProductionsDouble.count(key1)) {
auto iter = grammar.reverseProductionsDouble.find(key1);
for (const auto &res: iter->second) {
auto is_changed = perform_matrix_mul(res, iter->first.first, iter->first.second);
if (is_changed) {
new_changed_matrices.insert(res);
}
}
}
if (grammar.reverseProductionsDouble.count(key2)) {
auto iter = grammar.reverseProductionsDouble.find(key2);
for (const auto &res: iter->second) {
auto is_changed = perform_matrix_mul(res, iter->first.first, iter->first.second);
if (is_changed) {
new_changed_matrices.insert(res);
}
}
}
}
}
}
if (new_changed_matrices.empty()) {
//copy
break;
} else {
changed_matrices = new_changed_matrices;
//update matrices
}
//transfer
}
}
int packedByBlocksNumber(int N, int size) {
return (N / size + (N % size == 0 ? 0 : 1));
}
bool * Decompress(uint32_t * c_arr, uint32_t N) {
// int num_rows = N;
int num_columns = packedByBlocksNumber(N, 32);
bool * arr = reinterpret_cast<bool *>(calloc(N * N, sizeof(bool)));
uint32_t el;
for (int r = 0; r < N; r++) {
for (int c = 0; c < N; c++) {
el = c_arr[r * num_columns + (c / 32)];
if (el & (1 << (31 - (c % 32)))) {
arr[r * N + c] = 1;
}
}
}
return arr;
}
private:
void construct_and_fill_matrices_for_nonterminal_test() {
int rows = this->graph.multiple_by_32;
int cols = this->graph.multiple_by_32/32;
for (auto nonterminal: grammar.nonterminalSet) {
Matrix matrix = Matrix();
matrix.matrix_host = allocate_matrix_host(rows,cols); //alloc_matrix_host_with_zeros(rows, cols);
matrix.is_changed_host = allocate_matrix_host(1,1);
*matrix.is_changed_host = NOT_CHANGED;
this->nonTerminalToMatrix.insert(make_pair(nonterminal, matrix));
}// заполнили нулями для хоста
for (auto &edge:graph.edges) {
auto i = edge.from;
auto j = edge.to;
for (const auto &nonterminal:edge.label) { // заполнилии 1 в i,j для матриц на метках из i в j есть этот нетерминал
auto &matrix = this->nonTerminalToMatrix.find(nonterminal)->second;
write_bit(matrix.matrix_host,i,j,cols);
if (*matrix.is_changed_host == NOT_CHANGED) {
*matrix.is_changed_host = IS_CHANGED;
}
}
}
}
void write_bit(uint32_t *m, int i, int j,int cols){
m[i * cols + (j / 32)] |= (1 << (31 - (j % 32)));
}
// A = C*B
int perform_matrix_mul(const String &head, const String &left, const String &right) {
int rows = graph.multiple_by_32;
int cols = graph.multiple_by_32/32;
auto &A = this->nonTerminalToMatrix.at(head);
auto &C = this->nonTerminalToMatrix.at(left);
auto &B = this->nonTerminalToMatrix.at(right);
*A.is_changed_host = 0;
// a =cb и таков порядок аргубемнов
int res = wrapper_m4ri(A.matrix_host,C.matrix_host,B.matrix_host,rows,cols);
*A.is_changed_host = res;
return res;
}
};
int main(int argc, char* argv[]) {
auto solution = Solution(argv[1], argv[2], DELIMITR);
clock_t begin = clock();
solution.compute_result();
clock_t end = clock();
double elapsed_secs = double(end - begin) / CLOCKS_PER_SEC;
solution.output_in(argv[3]);
cout<<elapsed_secs<<endl;
}
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
|
code for sm_80
Function : _Z18transposeGlobalRowPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0004 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x174], R5 ; /* 0x00005d0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0004 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
|
.file "tmpxft_000480da_00000000-6_transposeGlobalRow.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii
.type _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii, @function
_Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18transposeGlobalRowPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii, .-_Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii
.globl _Z18transposeGlobalRowPfS_ii
.type _Z18transposeGlobalRowPfS_ii, @function
_Z18transposeGlobalRowPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18transposeGlobalRowPfS_ii, .-_Z18transposeGlobalRowPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18transposeGlobalRowPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeGlobalRowPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18transposeGlobalRowPfS_ii
.globl _Z18transposeGlobalRowPfS_ii
.p2align 8
.type _Z18transposeGlobalRowPfS_ii,@function
_Z18transposeGlobalRowPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v0, s5, v[1:2]
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeGlobalRowPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18transposeGlobalRowPfS_ii, .Lfunc_end0-_Z18transposeGlobalRowPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeGlobalRowPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeGlobalRowPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeGlobalRow(float *in, float *out, const int nx, const int ny)
{
unsigned int i = threadIdx.x+blockDim.x*blockIdx.x;
unsigned int j = threadIdx.y+blockDim.y*blockIdx.y;
if (i<nx && j<ny)
{
out[i*ny+j] = in[j*nx+i];
}
}
|
.text
.file "transposeGlobalRow.hip"
.globl _Z33__device_stub__transposeGlobalRowPfS_ii # -- Begin function _Z33__device_stub__transposeGlobalRowPfS_ii
.p2align 4, 0x90
.type _Z33__device_stub__transposeGlobalRowPfS_ii,@function
_Z33__device_stub__transposeGlobalRowPfS_ii: # @_Z33__device_stub__transposeGlobalRowPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18transposeGlobalRowPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__transposeGlobalRowPfS_ii, .Lfunc_end0-_Z33__device_stub__transposeGlobalRowPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeGlobalRowPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18transposeGlobalRowPfS_ii,@object # @_Z18transposeGlobalRowPfS_ii
.section .rodata,"a",@progbits
.globl _Z18transposeGlobalRowPfS_ii
.p2align 3, 0x0
_Z18transposeGlobalRowPfS_ii:
.quad _Z33__device_stub__transposeGlobalRowPfS_ii
.size _Z18transposeGlobalRowPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18transposeGlobalRowPfS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__transposeGlobalRowPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18transposeGlobalRowPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z18transposeGlobalRowPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x174], PT ; /* 0x00005d0005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x170], R0 ; /* 0x00005c0005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0004 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x174], R5 ; /* 0x00005d0000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0004 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18transposeGlobalRowPfS_ii
.globl _Z18transposeGlobalRowPfS_ii
.p2align 8
.type _Z18transposeGlobalRowPfS_ii,@function
_Z18transposeGlobalRowPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[4:5], null, v0, s5, v[1:2]
v_mov_b32_e32 v5, v3
v_lshlrev_b64 v[0:1], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18transposeGlobalRowPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18transposeGlobalRowPfS_ii, .Lfunc_end0-_Z18transposeGlobalRowPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18transposeGlobalRowPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18transposeGlobalRowPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000480da_00000000-6_transposeGlobalRow.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii
.type _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii, @function
_Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18transposeGlobalRowPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii, .-_Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii
.globl _Z18transposeGlobalRowPfS_ii
.type _Z18transposeGlobalRowPfS_ii, @function
_Z18transposeGlobalRowPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18transposeGlobalRowPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18transposeGlobalRowPfS_ii, .-_Z18transposeGlobalRowPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18transposeGlobalRowPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18transposeGlobalRowPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "transposeGlobalRow.hip"
.globl _Z33__device_stub__transposeGlobalRowPfS_ii # -- Begin function _Z33__device_stub__transposeGlobalRowPfS_ii
.p2align 4, 0x90
.type _Z33__device_stub__transposeGlobalRowPfS_ii,@function
_Z33__device_stub__transposeGlobalRowPfS_ii: # @_Z33__device_stub__transposeGlobalRowPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18transposeGlobalRowPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__transposeGlobalRowPfS_ii, .Lfunc_end0-_Z33__device_stub__transposeGlobalRowPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18transposeGlobalRowPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18transposeGlobalRowPfS_ii,@object # @_Z18transposeGlobalRowPfS_ii
.section .rodata,"a",@progbits
.globl _Z18transposeGlobalRowPfS_ii
.p2align 3, 0x0
_Z18transposeGlobalRowPfS_ii:
.quad _Z33__device_stub__transposeGlobalRowPfS_ii
.size _Z18transposeGlobalRowPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18transposeGlobalRowPfS_ii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__transposeGlobalRowPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18transposeGlobalRowPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#define DEFAULT_BLOCK_COUNT 128
#define DEFAULT_TPB_COUNT 128
using namespace std;
int blockCnt = DEFAULT_BLOCK_COUNT;
int tpbCnt = DEFAULT_TPB_COUNT;
int totalThreads;
int * id;
//Declaration of pointers to CPU memory (host)
int * blockx_h;
int * idx_h;
//Declaration of pointers to GPU memory (device)
int * blockx_d;
int * idx_d;
__global__ void MyFirstKernel(int * blkx, int * idx) {
int threadId = (blockIdx.x * blockDim.x) + threadIdx.x;
blkx[threadId] = blockIdx.x;
idx[threadId] = threadIdx.x;
}
int ParseArguments(int argc, char ** argv) {
if (argc == 1)
return 0;
if (argc != 3) {
cout << "Error: Not enough arguments specified." << endl;
return -1;
}
for (int i=1;i<3;i++) {
if (atoi(argv[i]) <= 0) {
cout << "Error: Invalid arguments" << endl;
return -1;
}
}
blockCnt = atoi(argv[1]);
tpbCnt = atoi(argv[2]);
if (tpbCnt > 1024) {
cout << "Error: Too many threads per block (<= 1024)" << endl;
return -1;
}
return 0;
}
void CheckCudaError(cudaError_t ce) {
if (ce == cudaSuccess)
return;
cout << "Error: " << cudaGetErrorString(ce) << endl;
exit(-1);
}
int AllocateHostMemory(int totalThreads) {
try {
blockx_h = new int[totalThreads];
idx_h = new int[totalThreads];
}
catch(bad_alloc e) {
return -1;
}
return 0;
}
int main(int argc, char ** argv) {
if (ParseArguments(argc, argv))
exit(-1);
totalThreads = blockCnt * tpbCnt;
int totalMem = totalThreads * sizeof(int);
if (AllocateHostMemory(totalThreads)) {
cout << "Error: Memory allocation on host failed." << endl;
exit(-1);
}
//Allocate memory on GPU to store block identifiers
CheckCudaError( cudaMalloc(&blockx_d, totalMem));
//Allocate memory on GPU to store thread identifiers
CheckCudaError( cudaMalloc(&idx_d, totalMem));
//Clear allocated memory block on GPU for storing block identifiers to 0
CheckCudaError( cudaMemset(blockx_d, 0, totalMem));
//Clear allocated memory block on GPU for storing thread identifiers to 0
CheckCudaError( cudaMemset(idx_d, 0, totalMem));
//Invoke the kernel
MyFirstKernel <<<blockCnt, tpbCnt>>>(blockx_d, idx_d);
cudaDeviceSynchronize();
//Copying data generated by the kernel from GPU back to CPU
CheckCudaError(
cudaMemcpy(blockx_h, blockx_d, totalMem, cudaMemcpyDeviceToHost));
CheckCudaError(
cudaMemcpy(idx_h, idx_d, totalMem, cudaMemcpyDeviceToHost));
for (int i=0;i<totalThreads;i++)
cout << "[" << i << "]\t" <<
blockx_h[i] << "\t" <<
idx_h[i] << endl;
return 0;
}
|
code for sm_80
Function : _Z13MyFirstKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R7, c[0x0][0x0], R0 ; /* 0x0000000007047a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0090*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#define DEFAULT_BLOCK_COUNT 128
#define DEFAULT_TPB_COUNT 128
using namespace std;
int blockCnt = DEFAULT_BLOCK_COUNT;
int tpbCnt = DEFAULT_TPB_COUNT;
int totalThreads;
int * id;
//Declaration of pointers to CPU memory (host)
int * blockx_h;
int * idx_h;
//Declaration of pointers to GPU memory (device)
int * blockx_d;
int * idx_d;
__global__ void MyFirstKernel(int * blkx, int * idx) {
int threadId = (blockIdx.x * blockDim.x) + threadIdx.x;
blkx[threadId] = blockIdx.x;
idx[threadId] = threadIdx.x;
}
int ParseArguments(int argc, char ** argv) {
if (argc == 1)
return 0;
if (argc != 3) {
cout << "Error: Not enough arguments specified." << endl;
return -1;
}
for (int i=1;i<3;i++) {
if (atoi(argv[i]) <= 0) {
cout << "Error: Invalid arguments" << endl;
return -1;
}
}
blockCnt = atoi(argv[1]);
tpbCnt = atoi(argv[2]);
if (tpbCnt > 1024) {
cout << "Error: Too many threads per block (<= 1024)" << endl;
return -1;
}
return 0;
}
void CheckCudaError(cudaError_t ce) {
if (ce == cudaSuccess)
return;
cout << "Error: " << cudaGetErrorString(ce) << endl;
exit(-1);
}
int AllocateHostMemory(int totalThreads) {
try {
blockx_h = new int[totalThreads];
idx_h = new int[totalThreads];
}
catch(bad_alloc e) {
return -1;
}
return 0;
}
int main(int argc, char ** argv) {
if (ParseArguments(argc, argv))
exit(-1);
totalThreads = blockCnt * tpbCnt;
int totalMem = totalThreads * sizeof(int);
if (AllocateHostMemory(totalThreads)) {
cout << "Error: Memory allocation on host failed." << endl;
exit(-1);
}
//Allocate memory on GPU to store block identifiers
CheckCudaError( cudaMalloc(&blockx_d, totalMem));
//Allocate memory on GPU to store thread identifiers
CheckCudaError( cudaMalloc(&idx_d, totalMem));
//Clear allocated memory block on GPU for storing block identifiers to 0
CheckCudaError( cudaMemset(blockx_d, 0, totalMem));
//Clear allocated memory block on GPU for storing thread identifiers to 0
CheckCudaError( cudaMemset(idx_d, 0, totalMem));
//Invoke the kernel
MyFirstKernel <<<blockCnt, tpbCnt>>>(blockx_d, idx_d);
cudaDeviceSynchronize();
//Copying data generated by the kernel from GPU back to CPU
CheckCudaError(
cudaMemcpy(blockx_h, blockx_d, totalMem, cudaMemcpyDeviceToHost));
CheckCudaError(
cudaMemcpy(idx_h, idx_d, totalMem, cudaMemcpyDeviceToHost));
for (int i=0;i<totalThreads;i++)
cout << "[" << i << "]\t" <<
blockx_h[i] << "\t" <<
idx_h[i] << endl;
return 0;
}
|
.file "tmpxft_001a1a94_00000000-6_tid_basic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3681:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3681:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: Not enough arguments specified."
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error: Invalid arguments"
.section .rodata.str1.8
.align 8
.LC2:
.string "Error: Too many threads per block (<= 1024)"
.text
.globl _Z14ParseArgumentsiPPc
.type _Z14ParseArgumentsiPPc, @function
_Z14ParseArgumentsiPPc:
.LFB3669:
.cfi_startproc
endbr64
cmpl $1, %edi
je .L17
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
cmpl $3, %edi
jne .L23
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %eax, %eax
jle .L9
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %eax, %eax
jle .L9
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, blockCnt(%rip)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, tpbCnt(%rip)
cmpl $1024, %eax
jg .L24
movl $0, %eax
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $38, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L25
cmpb $0, 56(%rbx)
je .L7
movzbl 67(%rbx), %esi
.L8:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $-1, %eax
jmp .L3
.L25:
call _ZSt16__throw_bad_castv@PLT
.L7:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L9:
movl $24, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L26
cmpb $0, 56(%rbx)
je .L12
movzbl 67(%rbx), %esi
.L13:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $-1, %eax
jmp .L3
.L26:
call _ZSt16__throw_bad_castv@PLT
.L12:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L13
.L24:
movl $43, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L27
cmpb $0, 56(%rbx)
je .L15
movzbl 67(%rbx), %eax
.L16:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $-1, %eax
jmp .L3
.L27:
call _ZSt16__throw_bad_castv@PLT
.L15:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L16
.L17:
.cfi_def_cfa_offset 8
.cfi_restore 3
movl $0, %eax
ret
.cfi_endproc
.LFE3669:
.size _Z14ParseArgumentsiPPc, .-_Z14ParseArgumentsiPPc
.section .rodata.str1.1
.LC3:
.string "Error: "
.text
.globl _Z14CheckCudaError9cudaError
.type _Z14CheckCudaError9cudaError, @function
_Z14CheckCudaError9cudaError:
.LFB3670:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L34
ret
.L34:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z14CheckCudaError9cudaError, .-_Z14CheckCudaError9cudaError
.globl _Z18AllocateHostMemoryi
.type _Z18AllocateHostMemoryi, @function
_Z18AllocateHostMemoryi:
.LFB3671:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3671
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %edi, %rbx
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L36
salq $2, %rbx
movq %rbx, %rdi
.LEHB0:
call _Znam@PLT
movq %rax, blockx_h(%rip)
movq %rbx, %rdi
call _Znam@PLT
jmp .L47
.L36:
movq 8(%rsp), %rax
subq %fs:40, %rax
je .L38
call __stack_chk_fail@PLT
.L38:
call __cxa_throw_bad_array_new_length@PLT
.LEHE0:
.L44:
endbr64
movq %rax, %rdi
cmpq $1, %rdx
je .L40
movq 8(%rsp), %rax
subq %fs:40, %rax
je .L41
call __stack_chk_fail@PLT
.L47:
movq %rax, idx_h(%rip)
movl $0, %eax
.L35:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L48
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L40:
leaq 16+_ZTVSt9bad_alloc(%rip), %rax
movq %rax, (%rsp)
call __cxa_begin_catch@PLT
movq %rsp, %rdi
call _ZNSt9bad_allocD1Ev@PLT
call __cxa_end_catch@PLT
movl $-1, %eax
jmp .L35
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA3671:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3671-.LLSDATTD3671
.LLSDATTD3671:
.byte 0x1
.uleb128 .LLSDACSE3671-.LLSDACSB3671
.LLSDACSB3671:
.uleb128 .LEHB0-.LFB3671
.uleb128 .LEHE0-.LEHB0
.uleb128 .L44-.LFB3671
.uleb128 0x1
.uleb128 .LEHB1-.LFB3671
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE3671:
.byte 0x1
.byte 0
.align 4
.long DW.ref._ZTISt9bad_alloc-.
.LLSDATT3671:
.text
.size _Z18AllocateHostMemoryi, .-_Z18AllocateHostMemoryi
.globl _Z35__device_stub__Z13MyFirstKernelPiS_PiS_
.type _Z35__device_stub__Z13MyFirstKernelPiS_PiS_, @function
_Z35__device_stub__Z13MyFirstKernelPiS_PiS_:
.LFB3703:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13MyFirstKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z35__device_stub__Z13MyFirstKernelPiS_PiS_, .-_Z35__device_stub__Z13MyFirstKernelPiS_PiS_
.globl _Z13MyFirstKernelPiS_
.type _Z13MyFirstKernelPiS_, @function
_Z13MyFirstKernelPiS_:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13MyFirstKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z13MyFirstKernelPiS_, .-_Z13MyFirstKernelPiS_
.section .rodata.str1.8
.align 8
.LC4:
.string "Error: Memory allocation on host failed."
.section .rodata.str1.1
.LC5:
.string "["
.LC6:
.string "]\t"
.LC7:
.string "\t"
.text
.globl main
.type main, @function
main:
.LFB3678:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
call _Z14ParseArgumentsiPPc
testl %eax, %eax
jne .L68
movl blockCnt(%rip), %edi
imull tpbCnt(%rip), %edi
movl %edi, totalThreads(%rip)
leal 0(,%rdi,4), %ebx
call _Z18AllocateHostMemoryi
testl %eax, %eax
jne .L69
movslq %ebx, %rbx
movq %rbx, %rsi
leaq blockx_d(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
movq %rbx, %rsi
leaq idx_d(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
movq %rbx, %rdx
movl $0, %esi
movq blockx_d(%rip), %rdi
call cudaMemset@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
movq %rbx, %rdx
movl $0, %esi
movq idx_d(%rip), %rdi
call cudaMemset@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
movl tpbCnt(%rip), %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl blockCnt(%rip), %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L60:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq blockx_d(%rip), %rsi
movq blockx_h(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
movl $2, %ecx
movq %rbx, %rdx
movq idx_d(%rip), %rsi
movq idx_h(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
cmpl $0, totalThreads(%rip)
jle .L61
movl $0, %ebx
leaq .LC5(%rip), %r15
leaq _ZSt4cout(%rip), %r13
leaq .LC6(%rip), %r14
jmp .L65
.L68:
movl $-1, %edi
call exit@PLT
.L69:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %edi
call exit@PLT
.L70:
movq idx_d(%rip), %rsi
movq blockx_d(%rip), %rdi
call _Z35__device_stub__Z13MyFirstKernelPiS_PiS_
jmp .L60
.L71:
call _ZSt16__throw_bad_castv@PLT
.L63:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L64:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpl %ebx, totalThreads(%rip)
jle .L61
.L65:
movl $1, %edx
movq %r15, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq blockx_h(%rip), %rax
movl (%rax,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq idx_h(%rip), %rax
movl (%rax,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L71
cmpb $0, 56(%r12)
je .L63
movzbl 67(%r12), %esi
jmp .L64
.L61:
movl $0, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z13MyFirstKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13MyFirstKernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl idx_d
.bss
.align 8
.type idx_d, @object
.size idx_d, 8
idx_d:
.zero 8
.globl blockx_d
.align 8
.type blockx_d, @object
.size blockx_d, 8
blockx_d:
.zero 8
.globl idx_h
.align 8
.type idx_h, @object
.size idx_h, 8
idx_h:
.zero 8
.globl blockx_h
.align 8
.type blockx_h, @object
.size blockx_h, 8
blockx_h:
.zero 8
.globl id
.align 8
.type id, @object
.size id, 8
id:
.zero 8
.globl totalThreads
.align 4
.type totalThreads, @object
.size totalThreads, 4
totalThreads:
.zero 4
.globl tpbCnt
.data
.align 4
.type tpbCnt, @object
.size tpbCnt, 4
tpbCnt:
.long 128
.globl blockCnt
.align 4
.type blockCnt, @object
.size blockCnt, 4
blockCnt:
.long 128
.hidden DW.ref._ZTISt9bad_alloc
.weak DW.ref._ZTISt9bad_alloc
.section .data.rel.local.DW.ref._ZTISt9bad_alloc,"awG",@progbits,DW.ref._ZTISt9bad_alloc,comdat
.align 8
.type DW.ref._ZTISt9bad_alloc, @object
.size DW.ref._ZTISt9bad_alloc, 8
DW.ref._ZTISt9bad_alloc:
.quad _ZTISt9bad_alloc
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#define DEFAULT_BLOCK_COUNT 128
#define DEFAULT_TPB_COUNT 128
using namespace std;
int blockCnt = DEFAULT_BLOCK_COUNT;
int tpbCnt = DEFAULT_TPB_COUNT;
int totalThreads;
int * id;
//Declaration of pointers to CPU memory (host)
int * blockx_h;
int * idx_h;
//Declaration of pointers to GPU memory (device)
int * blockx_d;
int * idx_d;
__global__ void MyFirstKernel(int * blkx, int * idx) {
int threadId = (blockIdx.x * blockDim.x) + threadIdx.x;
blkx[threadId] = blockIdx.x;
idx[threadId] = threadIdx.x;
}
int ParseArguments(int argc, char ** argv) {
if (argc == 1)
return 0;
if (argc != 3) {
cout << "Error: Not enough arguments specified." << endl;
return -1;
}
for (int i=1;i<3;i++) {
if (atoi(argv[i]) <= 0) {
cout << "Error: Invalid arguments" << endl;
return -1;
}
}
blockCnt = atoi(argv[1]);
tpbCnt = atoi(argv[2]);
if (tpbCnt > 1024) {
cout << "Error: Too many threads per block (<= 1024)" << endl;
return -1;
}
return 0;
}
void CheckCudaError(cudaError_t ce) {
if (ce == cudaSuccess)
return;
cout << "Error: " << cudaGetErrorString(ce) << endl;
exit(-1);
}
int AllocateHostMemory(int totalThreads) {
try {
blockx_h = new int[totalThreads];
idx_h = new int[totalThreads];
}
catch(bad_alloc e) {
return -1;
}
return 0;
}
int main(int argc, char ** argv) {
if (ParseArguments(argc, argv))
exit(-1);
totalThreads = blockCnt * tpbCnt;
int totalMem = totalThreads * sizeof(int);
if (AllocateHostMemory(totalThreads)) {
cout << "Error: Memory allocation on host failed." << endl;
exit(-1);
}
//Allocate memory on GPU to store block identifiers
CheckCudaError( cudaMalloc(&blockx_d, totalMem));
//Allocate memory on GPU to store thread identifiers
CheckCudaError( cudaMalloc(&idx_d, totalMem));
//Clear allocated memory block on GPU for storing block identifiers to 0
CheckCudaError( cudaMemset(blockx_d, 0, totalMem));
//Clear allocated memory block on GPU for storing thread identifiers to 0
CheckCudaError( cudaMemset(idx_d, 0, totalMem));
//Invoke the kernel
MyFirstKernel <<<blockCnt, tpbCnt>>>(blockx_d, idx_d);
cudaDeviceSynchronize();
//Copying data generated by the kernel from GPU back to CPU
CheckCudaError(
cudaMemcpy(blockx_h, blockx_d, totalMem, cudaMemcpyDeviceToHost));
CheckCudaError(
cudaMemcpy(idx_h, idx_d, totalMem, cudaMemcpyDeviceToHost));
for (int i=0;i<totalThreads;i++)
cout << "[" << i << "]\t" <<
blockx_h[i] << "\t" <<
idx_h[i] << endl;
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#define DEFAULT_BLOCK_COUNT 128
#define DEFAULT_TPB_COUNT 128
using namespace std;
int blockCnt = DEFAULT_BLOCK_COUNT;
int tpbCnt = DEFAULT_TPB_COUNT;
int totalThreads;
int * id;
//Declaration of pointers to CPU memory (host)
int * blockx_h;
int * idx_h;
//Declaration of pointers to GPU memory (device)
int * blockx_d;
int * idx_d;
__global__ void MyFirstKernel(int * blkx, int * idx) {
int threadId = (blockIdx.x * blockDim.x) + threadIdx.x;
blkx[threadId] = blockIdx.x;
idx[threadId] = threadIdx.x;
}
int ParseArguments(int argc, char ** argv) {
if (argc == 1)
return 0;
if (argc != 3) {
cout << "Error: Not enough arguments specified." << endl;
return -1;
}
for (int i=1;i<3;i++) {
if (atoi(argv[i]) <= 0) {
cout << "Error: Invalid arguments" << endl;
return -1;
}
}
blockCnt = atoi(argv[1]);
tpbCnt = atoi(argv[2]);
if (tpbCnt > 1024) {
cout << "Error: Too many threads per block (<= 1024)" << endl;
return -1;
}
return 0;
}
void CheckCudaError(hipError_t ce) {
if (ce == hipSuccess)
return;
cout << "Error: " << hipGetErrorString(ce) << endl;
exit(-1);
}
int AllocateHostMemory(int totalThreads) {
try {
blockx_h = new int[totalThreads];
idx_h = new int[totalThreads];
}
catch(bad_alloc e) {
return -1;
}
return 0;
}
int main(int argc, char ** argv) {
if (ParseArguments(argc, argv))
exit(-1);
totalThreads = blockCnt * tpbCnt;
int totalMem = totalThreads * sizeof(int);
if (AllocateHostMemory(totalThreads)) {
cout << "Error: Memory allocation on host failed." << endl;
exit(-1);
}
//Allocate memory on GPU to store block identifiers
CheckCudaError( hipMalloc(&blockx_d, totalMem));
//Allocate memory on GPU to store thread identifiers
CheckCudaError( hipMalloc(&idx_d, totalMem));
//Clear allocated memory block on GPU for storing block identifiers to 0
CheckCudaError( hipMemset(blockx_d, 0, totalMem));
//Clear allocated memory block on GPU for storing thread identifiers to 0
CheckCudaError( hipMemset(idx_d, 0, totalMem));
//Invoke the kernel
MyFirstKernel <<<blockCnt, tpbCnt>>>(blockx_d, idx_d);
hipDeviceSynchronize();
//Copying data generated by the kernel from GPU back to CPU
CheckCudaError(
hipMemcpy(blockx_h, blockx_d, totalMem, hipMemcpyDeviceToHost));
CheckCudaError(
hipMemcpy(idx_h, idx_d, totalMem, hipMemcpyDeviceToHost));
for (int i=0;i<totalThreads;i++)
cout << "[" << i << "]\t" <<
blockx_h[i] << "\t" <<
idx_h[i] << endl;
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#define DEFAULT_BLOCK_COUNT 128
#define DEFAULT_TPB_COUNT 128
using namespace std;
int blockCnt = DEFAULT_BLOCK_COUNT;
int tpbCnt = DEFAULT_TPB_COUNT;
int totalThreads;
int * id;
//Declaration of pointers to CPU memory (host)
int * blockx_h;
int * idx_h;
//Declaration of pointers to GPU memory (device)
int * blockx_d;
int * idx_d;
__global__ void MyFirstKernel(int * blkx, int * idx) {
int threadId = (blockIdx.x * blockDim.x) + threadIdx.x;
blkx[threadId] = blockIdx.x;
idx[threadId] = threadIdx.x;
}
int ParseArguments(int argc, char ** argv) {
if (argc == 1)
return 0;
if (argc != 3) {
cout << "Error: Not enough arguments specified." << endl;
return -1;
}
for (int i=1;i<3;i++) {
if (atoi(argv[i]) <= 0) {
cout << "Error: Invalid arguments" << endl;
return -1;
}
}
blockCnt = atoi(argv[1]);
tpbCnt = atoi(argv[2]);
if (tpbCnt > 1024) {
cout << "Error: Too many threads per block (<= 1024)" << endl;
return -1;
}
return 0;
}
void CheckCudaError(hipError_t ce) {
if (ce == hipSuccess)
return;
cout << "Error: " << hipGetErrorString(ce) << endl;
exit(-1);
}
int AllocateHostMemory(int totalThreads) {
try {
blockx_h = new int[totalThreads];
idx_h = new int[totalThreads];
}
catch(bad_alloc e) {
return -1;
}
return 0;
}
int main(int argc, char ** argv) {
if (ParseArguments(argc, argv))
exit(-1);
totalThreads = blockCnt * tpbCnt;
int totalMem = totalThreads * sizeof(int);
if (AllocateHostMemory(totalThreads)) {
cout << "Error: Memory allocation on host failed." << endl;
exit(-1);
}
//Allocate memory on GPU to store block identifiers
CheckCudaError( hipMalloc(&blockx_d, totalMem));
//Allocate memory on GPU to store thread identifiers
CheckCudaError( hipMalloc(&idx_d, totalMem));
//Clear allocated memory block on GPU for storing block identifiers to 0
CheckCudaError( hipMemset(blockx_d, 0, totalMem));
//Clear allocated memory block on GPU for storing thread identifiers to 0
CheckCudaError( hipMemset(idx_d, 0, totalMem));
//Invoke the kernel
MyFirstKernel <<<blockCnt, tpbCnt>>>(blockx_d, idx_d);
hipDeviceSynchronize();
//Copying data generated by the kernel from GPU back to CPU
CheckCudaError(
hipMemcpy(blockx_h, blockx_d, totalMem, hipMemcpyDeviceToHost));
CheckCudaError(
hipMemcpy(idx_h, idx_d, totalMem, hipMemcpyDeviceToHost));
for (int i=0;i<totalThreads;i++)
cout << "[" << i << "]\t" <<
blockx_h[i] << "\t" <<
idx_h[i] << endl;
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13MyFirstKernelPiS_
.globl _Z13MyFirstKernelPiS_
.p2align 8
.type _Z13MyFirstKernelPiS_,@function
_Z13MyFirstKernelPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v5, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[3:4], v5, off
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13MyFirstKernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13MyFirstKernelPiS_, .Lfunc_end0-_Z13MyFirstKernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13MyFirstKernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13MyFirstKernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#define DEFAULT_BLOCK_COUNT 128
#define DEFAULT_TPB_COUNT 128
using namespace std;
int blockCnt = DEFAULT_BLOCK_COUNT;
int tpbCnt = DEFAULT_TPB_COUNT;
int totalThreads;
int * id;
//Declaration of pointers to CPU memory (host)
int * blockx_h;
int * idx_h;
//Declaration of pointers to GPU memory (device)
int * blockx_d;
int * idx_d;
__global__ void MyFirstKernel(int * blkx, int * idx) {
int threadId = (blockIdx.x * blockDim.x) + threadIdx.x;
blkx[threadId] = blockIdx.x;
idx[threadId] = threadIdx.x;
}
int ParseArguments(int argc, char ** argv) {
if (argc == 1)
return 0;
if (argc != 3) {
cout << "Error: Not enough arguments specified." << endl;
return -1;
}
for (int i=1;i<3;i++) {
if (atoi(argv[i]) <= 0) {
cout << "Error: Invalid arguments" << endl;
return -1;
}
}
blockCnt = atoi(argv[1]);
tpbCnt = atoi(argv[2]);
if (tpbCnt > 1024) {
cout << "Error: Too many threads per block (<= 1024)" << endl;
return -1;
}
return 0;
}
void CheckCudaError(hipError_t ce) {
if (ce == hipSuccess)
return;
cout << "Error: " << hipGetErrorString(ce) << endl;
exit(-1);
}
int AllocateHostMemory(int totalThreads) {
try {
blockx_h = new int[totalThreads];
idx_h = new int[totalThreads];
}
catch(bad_alloc e) {
return -1;
}
return 0;
}
int main(int argc, char ** argv) {
if (ParseArguments(argc, argv))
exit(-1);
totalThreads = blockCnt * tpbCnt;
int totalMem = totalThreads * sizeof(int);
if (AllocateHostMemory(totalThreads)) {
cout << "Error: Memory allocation on host failed." << endl;
exit(-1);
}
//Allocate memory on GPU to store block identifiers
CheckCudaError( hipMalloc(&blockx_d, totalMem));
//Allocate memory on GPU to store thread identifiers
CheckCudaError( hipMalloc(&idx_d, totalMem));
//Clear allocated memory block on GPU for storing block identifiers to 0
CheckCudaError( hipMemset(blockx_d, 0, totalMem));
//Clear allocated memory block on GPU for storing thread identifiers to 0
CheckCudaError( hipMemset(idx_d, 0, totalMem));
//Invoke the kernel
MyFirstKernel <<<blockCnt, tpbCnt>>>(blockx_d, idx_d);
hipDeviceSynchronize();
//Copying data generated by the kernel from GPU back to CPU
CheckCudaError(
hipMemcpy(blockx_h, blockx_d, totalMem, hipMemcpyDeviceToHost));
CheckCudaError(
hipMemcpy(idx_h, idx_d, totalMem, hipMemcpyDeviceToHost));
for (int i=0;i<totalThreads;i++)
cout << "[" << i << "]\t" <<
blockx_h[i] << "\t" <<
idx_h[i] << endl;
return 0;
}
|
.text
.file "tid_basic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__MyFirstKernelPiS_ # -- Begin function _Z28__device_stub__MyFirstKernelPiS_
.p2align 4, 0x90
.type _Z28__device_stub__MyFirstKernelPiS_,@function
_Z28__device_stub__MyFirstKernelPiS_: # @_Z28__device_stub__MyFirstKernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13MyFirstKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__MyFirstKernelPiS_, .Lfunc_end0-_Z28__device_stub__MyFirstKernelPiS_
.cfi_endproc
# -- End function
.globl _Z14ParseArgumentsiPPc # -- Begin function _Z14ParseArgumentsiPPc
.p2align 4, 0x90
.type _Z14ParseArgumentsiPPc,@function
_Z14ParseArgumentsiPPc: # @_Z14ParseArgumentsiPPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
je .LBB1_10
# %bb.1:
cmpl $3, %edi
jne .LBB1_11
# %bb.2: # %.preheader.preheader
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
jle .LBB1_7
# %bb.3: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $1, %r14
je .LBB1_16
# %bb.5: # %.preheader
# in Loop: Header=BB1_4 Depth=1
movq 16(%rbx,%r14,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
incq %r14
testl %eax, %eax
jg .LBB1_4
# %bb.6: # %.preheader._crit_edge
cmpq $2, %r14
setae %r15b
.LBB1_7:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_23
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i13
cmpb $0, 56(%r14)
je .LBB1_14
# %bb.9:
movzbl 67(%r14), %eax
jmp .LBB1_15
.LBB1_10:
xorl %r14d, %r14d
jmp .LBB1_22
.LBB1_11:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_20
.LBB1_13:
movzbl 67(%rbx), %eax
jmp .LBB1_21
.LBB1_14:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit16
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %r14d
testb %r15b, %r15b
je .LBB1_22
.LBB1_16: # %.critedge
movq 8(%rbx), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, blockCnt(%rip)
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, tpbCnt(%rip)
cmpl $1025, %eax # imm = 0x401
jl .LBB1_22
# %bb.17:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $43, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%rbx)
jne .LBB1_13
.LBB1_20:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_21: # %.sink.split
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %r14d
.LBB1_22:
movl %r14d, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z14ParseArgumentsiPPc, .Lfunc_end1-_Z14ParseArgumentsiPPc
.cfi_endproc
# -- End function
.globl _Z14CheckCudaError10hipError_t # -- Begin function _Z14CheckCudaError10hipError_t
.p2align 4, 0x90
.type _Z14CheckCudaError10hipError_t,@function
_Z14CheckCudaError10hipError_t: # @_Z14CheckCudaError10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB2_2
# %bb.1:
retq
.LBB2_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z14CheckCudaError10hipError_t, .Lfunc_end2-_Z14CheckCudaError10hipError_t
.cfi_endproc
# -- End function
.globl _Z18AllocateHostMemoryi # -- Begin function _Z18AllocateHostMemoryi
.p2align 4, 0x90
.type _Z18AllocateHostMemoryi,@function
_Z18AllocateHostMemoryi: # @_Z18AllocateHostMemoryi
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movslq %edi, %rax
leaq (,%rax,4), %rcx
testl %eax, %eax
movq $-1, %rbx
cmovnsq %rcx, %rbx
.Ltmp0:
movq %rbx, %rdi
callq _Znam
.Ltmp1:
# %bb.1:
movq %rax, blockx_h(%rip)
.Ltmp2:
movq %rbx, %rdi
callq _Znam
.Ltmp3:
# %bb.2:
movq %rax, idx_h(%rip)
xorl %eax, %eax
.LBB3_4:
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 32
.Ltmp4:
movq %rax, %rbx
movq %rax, %rdi
callq __cxa_get_exception_ptr
movq $_ZTVSt9bad_alloc+16, 8(%rsp)
movq %rbx, %rdi
callq __cxa_begin_catch
leaq 8(%rsp), %rdi
callq _ZNSt9bad_allocD1Ev
callq __cxa_end_catch
movl $-1, %eax
jmp .LBB3_4
.Lfunc_end3:
.size _Z18AllocateHostMemoryi, .Lfunc_end3-_Z18AllocateHostMemoryi
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 1 # On action: 1
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Lfunc_end3-.Ltmp3 # Call between .Ltmp3 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long _ZTISt9bad_alloc # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _Z14ParseArgumentsiPPc
testl %eax, %eax
jne .LBB4_21
# %bb.1:
movl tpbCnt(%rip), %ebx
imull blockCnt(%rip), %ebx
movl %ebx, totalThreads(%rip)
movl %ebx, %edi
callq _Z18AllocateHostMemoryi
testl %eax, %eax
jne .LBB4_22
# %bb.2:
shll $2, %ebx
movslq %ebx, %rbx
movl $blockx_d, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_19
# %bb.3: # %_Z14CheckCudaError10hipError_t.exit
movl $idx_d, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_19
# %bb.4: # %_Z14CheckCudaError10hipError_t.exit16
movq blockx_d(%rip), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
testl %eax, %eax
jne .LBB4_19
# %bb.5: # %_Z14CheckCudaError10hipError_t.exit17
movq idx_d(%rip), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
testl %eax, %eax
jne .LBB4_19
# %bb.6: # %_Z14CheckCudaError10hipError_t.exit18
movl blockCnt(%rip), %edi
movl tpbCnt(%rip), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq blockx_d(%rip), %rax
movq idx_d(%rip), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13MyFirstKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movq blockx_h(%rip), %rdi
movq blockx_d(%rip), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_19
# %bb.9: # %_Z14CheckCudaError10hipError_t.exit19
movq idx_h(%rip), %rdi
movq idx_d(%rip), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_19
# %bb.10: # %_Z14CheckCudaError10hipError_t.exit20.preheader
cmpl $0, totalThreads(%rip)
jle .LBB4_17
# %bb.11: # %.lr.ph.preheader
xorl %ebx, %ebx
jmp .LBB4_14
.p2align 4, 0x90
.LBB4_12: # in Loop: Header=BB4_14 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB4_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB4_14 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
movslq totalThreads(%rip), %rax
cmpq %rax, %rbx
jge .LBB4_17
.LBB4_14: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.6, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq blockx_h(%rip), %rax
movl (%rax,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq idx_h(%rip), %rax
movl (%rax,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_18
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB4_14 Depth=1
cmpb $0, 56(%r14)
je .LBB4_12
# %bb.16: # in Loop: Header=BB4_14 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB4_13
.LBB4_17: # %_Z14CheckCudaError10hipError_t.exit20._crit_edge
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_18:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.LBB4_19:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
.LBB4_20:
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.LBB4_21:
movl $-1, %edi
callq exit
.LBB4_22:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
jmp .LBB4_20
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13MyFirstKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type blockCnt,@object # @blockCnt
.data
.globl blockCnt
.p2align 2, 0x0
blockCnt:
.long 128 # 0x80
.size blockCnt, 4
.type tpbCnt,@object # @tpbCnt
.globl tpbCnt
.p2align 2, 0x0
tpbCnt:
.long 128 # 0x80
.size tpbCnt, 4
.type totalThreads,@object # @totalThreads
.bss
.globl totalThreads
.p2align 2, 0x0
totalThreads:
.long 0 # 0x0
.size totalThreads, 4
.type id,@object # @id
.globl id
.p2align 3, 0x0
id:
.quad 0
.size id, 8
.type blockx_h,@object # @blockx_h
.globl blockx_h
.p2align 3, 0x0
blockx_h:
.quad 0
.size blockx_h, 8
.type idx_h,@object # @idx_h
.globl idx_h
.p2align 3, 0x0
idx_h:
.quad 0
.size idx_h, 8
.type blockx_d,@object # @blockx_d
.globl blockx_d
.p2align 3, 0x0
blockx_d:
.quad 0
.size blockx_d, 8
.type idx_d,@object # @idx_d
.globl idx_d
.p2align 3, 0x0
idx_d:
.quad 0
.size idx_d, 8
.type _Z13MyFirstKernelPiS_,@object # @_Z13MyFirstKernelPiS_
.section .rodata,"a",@progbits
.globl _Z13MyFirstKernelPiS_
.p2align 3, 0x0
_Z13MyFirstKernelPiS_:
.quad _Z28__device_stub__MyFirstKernelPiS_
.size _Z13MyFirstKernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: Not enough arguments specified."
.size .L.str, 39
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: Invalid arguments"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error: Too many threads per block (<= 1024)"
.size .L.str.2, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error: "
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error: Memory allocation on host failed."
.size .L.str.4, 41
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "["
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "]\t"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\t"
.size .L.str.7, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13MyFirstKernelPiS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__MyFirstKernelPiS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym blockx_d
.addrsig_sym idx_d
.addrsig_sym _Z13MyFirstKernelPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZTISt9bad_alloc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z13MyFirstKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R7, c[0x0][0x0], R0 ; /* 0x0000000007047a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*0080*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0090*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13MyFirstKernelPiS_
.globl _Z13MyFirstKernelPiS_
.p2align 8
.type _Z13MyFirstKernelPiS_,@function
_Z13MyFirstKernelPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v5, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_store_b32 v[3:4], v5, off
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13MyFirstKernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13MyFirstKernelPiS_, .Lfunc_end0-_Z13MyFirstKernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13MyFirstKernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13MyFirstKernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001a1a94_00000000-6_tid_basic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3681:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3681:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error: Not enough arguments specified."
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error: Invalid arguments"
.section .rodata.str1.8
.align 8
.LC2:
.string "Error: Too many threads per block (<= 1024)"
.text
.globl _Z14ParseArgumentsiPPc
.type _Z14ParseArgumentsiPPc, @function
_Z14ParseArgumentsiPPc:
.LFB3669:
.cfi_startproc
endbr64
cmpl $1, %edi
je .L17
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
cmpl $3, %edi
jne .L23
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %eax, %eax
jle .L9
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %eax, %eax
jle .L9
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, blockCnt(%rip)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, tpbCnt(%rip)
cmpl $1024, %eax
jg .L24
movl $0, %eax
.L3:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $38, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L25
cmpb $0, 56(%rbx)
je .L7
movzbl 67(%rbx), %esi
.L8:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $-1, %eax
jmp .L3
.L25:
call _ZSt16__throw_bad_castv@PLT
.L7:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L9:
movl $24, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L26
cmpb $0, 56(%rbx)
je .L12
movzbl 67(%rbx), %esi
.L13:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $-1, %eax
jmp .L3
.L26:
call _ZSt16__throw_bad_castv@PLT
.L12:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L13
.L24:
movl $43, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L27
cmpb $0, 56(%rbx)
je .L15
movzbl 67(%rbx), %eax
.L16:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $-1, %eax
jmp .L3
.L27:
call _ZSt16__throw_bad_castv@PLT
.L15:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L16
.L17:
.cfi_def_cfa_offset 8
.cfi_restore 3
movl $0, %eax
ret
.cfi_endproc
.LFE3669:
.size _Z14ParseArgumentsiPPc, .-_Z14ParseArgumentsiPPc
.section .rodata.str1.1
.LC3:
.string "Error: "
.text
.globl _Z14CheckCudaError9cudaError
.type _Z14CheckCudaError9cudaError, @function
_Z14CheckCudaError9cudaError:
.LFB3670:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L34
ret
.L34:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z14CheckCudaError9cudaError, .-_Z14CheckCudaError9cudaError
.globl _Z18AllocateHostMemoryi
.type _Z18AllocateHostMemoryi, @function
_Z18AllocateHostMemoryi:
.LFB3671:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3671
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %edi, %rbx
movabsq $2305843009213693950, %rax
cmpq %rbx, %rax
jb .L36
salq $2, %rbx
movq %rbx, %rdi
.LEHB0:
call _Znam@PLT
movq %rax, blockx_h(%rip)
movq %rbx, %rdi
call _Znam@PLT
jmp .L47
.L36:
movq 8(%rsp), %rax
subq %fs:40, %rax
je .L38
call __stack_chk_fail@PLT
.L38:
call __cxa_throw_bad_array_new_length@PLT
.LEHE0:
.L44:
endbr64
movq %rax, %rdi
cmpq $1, %rdx
je .L40
movq 8(%rsp), %rax
subq %fs:40, %rax
je .L41
call __stack_chk_fail@PLT
.L47:
movq %rax, idx_h(%rip)
movl $0, %eax
.L35:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L48
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L40:
leaq 16+_ZTVSt9bad_alloc(%rip), %rax
movq %rax, (%rsp)
call __cxa_begin_catch@PLT
movq %rsp, %rdi
call _ZNSt9bad_allocD1Ev@PLT
call __cxa_end_catch@PLT
movl $-1, %eax
jmp .L35
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.align 4
.LLSDA3671:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT3671-.LLSDATTD3671
.LLSDATTD3671:
.byte 0x1
.uleb128 .LLSDACSE3671-.LLSDACSB3671
.LLSDACSB3671:
.uleb128 .LEHB0-.LFB3671
.uleb128 .LEHE0-.LEHB0
.uleb128 .L44-.LFB3671
.uleb128 0x1
.uleb128 .LEHB1-.LFB3671
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE3671:
.byte 0x1
.byte 0
.align 4
.long DW.ref._ZTISt9bad_alloc-.
.LLSDATT3671:
.text
.size _Z18AllocateHostMemoryi, .-_Z18AllocateHostMemoryi
.globl _Z35__device_stub__Z13MyFirstKernelPiS_PiS_
.type _Z35__device_stub__Z13MyFirstKernelPiS_PiS_, @function
_Z35__device_stub__Z13MyFirstKernelPiS_PiS_:
.LFB3703:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13MyFirstKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z35__device_stub__Z13MyFirstKernelPiS_PiS_, .-_Z35__device_stub__Z13MyFirstKernelPiS_PiS_
.globl _Z13MyFirstKernelPiS_
.type _Z13MyFirstKernelPiS_, @function
_Z13MyFirstKernelPiS_:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13MyFirstKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z13MyFirstKernelPiS_, .-_Z13MyFirstKernelPiS_
.section .rodata.str1.8
.align 8
.LC4:
.string "Error: Memory allocation on host failed."
.section .rodata.str1.1
.LC5:
.string "["
.LC6:
.string "]\t"
.LC7:
.string "\t"
.text
.globl main
.type main, @function
main:
.LFB3678:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
call _Z14ParseArgumentsiPPc
testl %eax, %eax
jne .L68
movl blockCnt(%rip), %edi
imull tpbCnt(%rip), %edi
movl %edi, totalThreads(%rip)
leal 0(,%rdi,4), %ebx
call _Z18AllocateHostMemoryi
testl %eax, %eax
jne .L69
movslq %ebx, %rbx
movq %rbx, %rsi
leaq blockx_d(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
movq %rbx, %rsi
leaq idx_d(%rip), %rdi
call cudaMalloc@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
movq %rbx, %rdx
movl $0, %esi
movq blockx_d(%rip), %rdi
call cudaMemset@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
movq %rbx, %rdx
movl $0, %esi
movq idx_d(%rip), %rdi
call cudaMemset@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
movl tpbCnt(%rip), %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl blockCnt(%rip), %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L60:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq blockx_d(%rip), %rsi
movq blockx_h(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
movl $2, %ecx
movq %rbx, %rdx
movq idx_d(%rip), %rsi
movq idx_h(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14CheckCudaError9cudaError
cmpl $0, totalThreads(%rip)
jle .L61
movl $0, %ebx
leaq .LC5(%rip), %r15
leaq _ZSt4cout(%rip), %r13
leaq .LC6(%rip), %r14
jmp .L65
.L68:
movl $-1, %edi
call exit@PLT
.L69:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $-1, %edi
call exit@PLT
.L70:
movq idx_d(%rip), %rsi
movq blockx_d(%rip), %rdi
call _Z35__device_stub__Z13MyFirstKernelPiS_PiS_
jmp .L60
.L71:
call _ZSt16__throw_bad_castv@PLT
.L63:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L64:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpl %ebx, totalThreads(%rip)
jle .L61
.L65:
movl $1, %edx
movq %r15, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $2, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq blockx_h(%rip), %rax
movl (%rax,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC7(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq idx_h(%rip), %rax
movl (%rax,%rbx,4), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L71
cmpb $0, 56(%r12)
je .L63
movzbl 67(%r12), %esi
jmp .L64
.L61:
movl $0, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z13MyFirstKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13MyFirstKernelPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl idx_d
.bss
.align 8
.type idx_d, @object
.size idx_d, 8
idx_d:
.zero 8
.globl blockx_d
.align 8
.type blockx_d, @object
.size blockx_d, 8
blockx_d:
.zero 8
.globl idx_h
.align 8
.type idx_h, @object
.size idx_h, 8
idx_h:
.zero 8
.globl blockx_h
.align 8
.type blockx_h, @object
.size blockx_h, 8
blockx_h:
.zero 8
.globl id
.align 8
.type id, @object
.size id, 8
id:
.zero 8
.globl totalThreads
.align 4
.type totalThreads, @object
.size totalThreads, 4
totalThreads:
.zero 4
.globl tpbCnt
.data
.align 4
.type tpbCnt, @object
.size tpbCnt, 4
tpbCnt:
.long 128
.globl blockCnt
.align 4
.type blockCnt, @object
.size blockCnt, 4
blockCnt:
.long 128
.hidden DW.ref._ZTISt9bad_alloc
.weak DW.ref._ZTISt9bad_alloc
.section .data.rel.local.DW.ref._ZTISt9bad_alloc,"awG",@progbits,DW.ref._ZTISt9bad_alloc,comdat
.align 8
.type DW.ref._ZTISt9bad_alloc, @object
.size DW.ref._ZTISt9bad_alloc, 8
DW.ref._ZTISt9bad_alloc:
.quad _ZTISt9bad_alloc
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "tid_basic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__MyFirstKernelPiS_ # -- Begin function _Z28__device_stub__MyFirstKernelPiS_
.p2align 4, 0x90
.type _Z28__device_stub__MyFirstKernelPiS_,@function
_Z28__device_stub__MyFirstKernelPiS_: # @_Z28__device_stub__MyFirstKernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13MyFirstKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__MyFirstKernelPiS_, .Lfunc_end0-_Z28__device_stub__MyFirstKernelPiS_
.cfi_endproc
# -- End function
.globl _Z14ParseArgumentsiPPc # -- Begin function _Z14ParseArgumentsiPPc
.p2align 4, 0x90
.type _Z14ParseArgumentsiPPc,@function
_Z14ParseArgumentsiPPc: # @_Z14ParseArgumentsiPPc
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
je .LBB1_10
# %bb.1:
cmpl $3, %edi
jne .LBB1_11
# %bb.2: # %.preheader.preheader
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
jle .LBB1_7
# %bb.3: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $1, %r14
je .LBB1_16
# %bb.5: # %.preheader
# in Loop: Header=BB1_4 Depth=1
movq 16(%rbx,%r14,8), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
incq %r14
testl %eax, %eax
jg .LBB1_4
# %bb.6: # %.preheader._crit_edge
cmpq $2, %r14
setae %r15b
.LBB1_7:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_23
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i13
cmpb $0, 56(%r14)
je .LBB1_14
# %bb.9:
movzbl 67(%r14), %eax
jmp .LBB1_15
.LBB1_10:
xorl %r14d, %r14d
jmp .LBB1_22
.LBB1_11:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $38, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_20
.LBB1_13:
movzbl 67(%rbx), %eax
jmp .LBB1_21
.LBB1_14:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit16
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %r14d
testb %r15b, %r15b
je .LBB1_22
.LBB1_16: # %.critedge
movq 8(%rbx), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, blockCnt(%rip)
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, tpbCnt(%rip)
cmpl $1025, %eax # imm = 0x401
jl .LBB1_22
# %bb.17:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $43, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i18
cmpb $0, 56(%rbx)
jne .LBB1_13
.LBB1_20:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_21: # %.sink.split
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $-1, %r14d
.LBB1_22:
movl %r14d, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z14ParseArgumentsiPPc, .Lfunc_end1-_Z14ParseArgumentsiPPc
.cfi_endproc
# -- End function
.globl _Z14CheckCudaError10hipError_t # -- Begin function _Z14CheckCudaError10hipError_t
.p2align 4, 0x90
.type _Z14CheckCudaError10hipError_t,@function
_Z14CheckCudaError10hipError_t: # @_Z14CheckCudaError10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB2_2
# %bb.1:
retq
.LBB2_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $-1, %edi
callq exit
.Lfunc_end2:
.size _Z14CheckCudaError10hipError_t, .Lfunc_end2-_Z14CheckCudaError10hipError_t
.cfi_endproc
# -- End function
.globl _Z18AllocateHostMemoryi # -- Begin function _Z18AllocateHostMemoryi
.p2align 4, 0x90
.type _Z18AllocateHostMemoryi,@function
_Z18AllocateHostMemoryi: # @_Z18AllocateHostMemoryi
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
movslq %edi, %rax
leaq (,%rax,4), %rcx
testl %eax, %eax
movq $-1, %rbx
cmovnsq %rcx, %rbx
.Ltmp0:
movq %rbx, %rdi
callq _Znam
.Ltmp1:
# %bb.1:
movq %rax, blockx_h(%rip)
.Ltmp2:
movq %rbx, %rdi
callq _Znam
.Ltmp3:
# %bb.2:
movq %rax, idx_h(%rip)
xorl %eax, %eax
.LBB3_4:
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB3_3:
.cfi_def_cfa_offset 32
.Ltmp4:
movq %rax, %rbx
movq %rax, %rdi
callq __cxa_get_exception_ptr
movq $_ZTVSt9bad_alloc+16, 8(%rsp)
movq %rbx, %rdi
callq __cxa_begin_catch
leaq 8(%rsp), %rdi
callq _ZNSt9bad_allocD1Ev
callq __cxa_end_catch
movl $-1, %eax
jmp .LBB3_4
.Lfunc_end3:
.size _Z18AllocateHostMemoryi, .Lfunc_end3-_Z18AllocateHostMemoryi
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp4-.Lfunc_begin0 # jumps to .Ltmp4
.byte 1 # On action: 1
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Lfunc_end3-.Ltmp3 # Call between .Ltmp3 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long _ZTISt9bad_alloc # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _Z14ParseArgumentsiPPc
testl %eax, %eax
jne .LBB4_21
# %bb.1:
movl tpbCnt(%rip), %ebx
imull blockCnt(%rip), %ebx
movl %ebx, totalThreads(%rip)
movl %ebx, %edi
callq _Z18AllocateHostMemoryi
testl %eax, %eax
jne .LBB4_22
# %bb.2:
shll $2, %ebx
movslq %ebx, %rbx
movl $blockx_d, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_19
# %bb.3: # %_Z14CheckCudaError10hipError_t.exit
movl $idx_d, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB4_19
# %bb.4: # %_Z14CheckCudaError10hipError_t.exit16
movq blockx_d(%rip), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
testl %eax, %eax
jne .LBB4_19
# %bb.5: # %_Z14CheckCudaError10hipError_t.exit17
movq idx_d(%rip), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
testl %eax, %eax
jne .LBB4_19
# %bb.6: # %_Z14CheckCudaError10hipError_t.exit18
movl blockCnt(%rip), %edi
movl tpbCnt(%rip), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq blockx_d(%rip), %rax
movq idx_d(%rip), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13MyFirstKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movq blockx_h(%rip), %rdi
movq blockx_d(%rip), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_19
# %bb.9: # %_Z14CheckCudaError10hipError_t.exit19
movq idx_h(%rip), %rdi
movq idx_d(%rip), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_19
# %bb.10: # %_Z14CheckCudaError10hipError_t.exit20.preheader
cmpl $0, totalThreads(%rip)
jle .LBB4_17
# %bb.11: # %.lr.ph.preheader
xorl %ebx, %ebx
jmp .LBB4_14
.p2align 4, 0x90
.LBB4_12: # in Loop: Header=BB4_14 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB4_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB4_14 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %rbx
movslq totalThreads(%rip), %rax
cmpq %rax, %rbx
jge .LBB4_17
.LBB4_14: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.6, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq blockx_h(%rip), %rax
movl (%rax,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq idx_h(%rip), %rax
movl (%rax,%rbx,4), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB4_18
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB4_14 Depth=1
cmpb $0, 56(%r14)
je .LBB4_12
# %bb.16: # in Loop: Header=BB4_14 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB4_13
.LBB4_17: # %_Z14CheckCudaError10hipError_t.exit20._crit_edge
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_18:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.LBB4_19:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
.LBB4_20:
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.LBB4_21:
movl $-1, %edi
callq exit
.LBB4_22:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
jmp .LBB4_20
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13MyFirstKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type blockCnt,@object # @blockCnt
.data
.globl blockCnt
.p2align 2, 0x0
blockCnt:
.long 128 # 0x80
.size blockCnt, 4
.type tpbCnt,@object # @tpbCnt
.globl tpbCnt
.p2align 2, 0x0
tpbCnt:
.long 128 # 0x80
.size tpbCnt, 4
.type totalThreads,@object # @totalThreads
.bss
.globl totalThreads
.p2align 2, 0x0
totalThreads:
.long 0 # 0x0
.size totalThreads, 4
.type id,@object # @id
.globl id
.p2align 3, 0x0
id:
.quad 0
.size id, 8
.type blockx_h,@object # @blockx_h
.globl blockx_h
.p2align 3, 0x0
blockx_h:
.quad 0
.size blockx_h, 8
.type idx_h,@object # @idx_h
.globl idx_h
.p2align 3, 0x0
idx_h:
.quad 0
.size idx_h, 8
.type blockx_d,@object # @blockx_d
.globl blockx_d
.p2align 3, 0x0
blockx_d:
.quad 0
.size blockx_d, 8
.type idx_d,@object # @idx_d
.globl idx_d
.p2align 3, 0x0
idx_d:
.quad 0
.size idx_d, 8
.type _Z13MyFirstKernelPiS_,@object # @_Z13MyFirstKernelPiS_
.section .rodata,"a",@progbits
.globl _Z13MyFirstKernelPiS_
.p2align 3, 0x0
_Z13MyFirstKernelPiS_:
.quad _Z28__device_stub__MyFirstKernelPiS_
.size _Z13MyFirstKernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: Not enough arguments specified."
.size .L.str, 39
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: Invalid arguments"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error: Too many threads per block (<= 1024)"
.size .L.str.2, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error: "
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error: Memory allocation on host failed."
.size .L.str.4, 41
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "["
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "]\t"
.size .L.str.6, 3
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\t"
.size .L.str.7, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13MyFirstKernelPiS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__MyFirstKernelPiS_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym blockx_d
.addrsig_sym idx_d
.addrsig_sym _Z13MyFirstKernelPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZTISt9bad_alloc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
// nvcc matrixNorm_CUDA.cu -lm -o norm.out
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 6000 /* Matrix size */
// pointers to the device arrays
float *a_d, *b_d;
/* Matrices */
volatile float A[N][N], B[N][N];
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row][col] = (float)rand() / 32768.0;
B[row][col] = 0.0;
}
}
}
// printing parts of the larger matrices for testing
void print_A() {
printf("\nA = ");
int printing = 10;
if (N < 99) {
printing = N;
}
for (int row = 0; row < printing; row++) {
printf("\n[ ");
for (int col = 0; col < printing; col++) {
printf(" %5.2f ", A[row][col]);
}
printf("]\n");
}
}
void print_B() {
printf("\nB = ");
int printing = 10;
if (N < 99) {
printing = N;
}
for (int row = 0; row < printing; row++) {
printf("\n[ ");
for (int col = 0; col < printing; col++) {
printf(" %5.2f ", B[row][col]);
}
printf("]\n");
}
}
/* Kernel function */
// variables are used to indentify and differentiate between GPU threads
// blockDim -> dimensions of each thread block
// blockIdx -> index of thread block within grid
// threadIdx -> index of thread withing thread block
__global__ void matrixNorm(float *temp_a, float *temp_b) {
// i is the unique thread id
int i = blockDim.x * blockIdx.x + threadIdx.x;
int row;
float mu, sigma; // Mean and Standard Deviation
// if (i == 1) {
// for (int k = 0; k < 10; k++) {
// printf(" %5.2f ", temp_a[k]);
// }
// printf("\n");
// }
// since i is used in array access only allow those
// less than N so no out-of-bounds access happens
if (i < N) {
// printf("Thread num -> %d\n", i);
mu = 0.0;
// temp_a is the one-dimensional form of A
// row * N is used as the starting point for each of the rows
// + i would access the individual elements in each section
for (row=0; row < N; row++)
mu += temp_a[row * N + i];
mu /= (float) N;
sigma = 0.0;
for (row=0; row < N; row++)
sigma += powf(temp_a[row * N + i] - mu, 2.0);
sigma /= (float) N;
sigma = sqrt(sigma);
for (row=0; row < N; row++) {
if (sigma == 0.0)
temp_b[row * N + i] = 0.0;
else
temp_b[row * N + i] = (temp_a[row * N + i] - mu) / sigma;
}
}
__syncthreads();
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval start, stop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
unsigned long long runtime;
/* Initialize A and B */
initialize_inputs();
// size would be an N by N matrix of floats
float size = N*N*sizeof(float);
// print_A();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&start, &tzdummy);
cudaEvent_t st, sp;
cudaEventCreate(&st);
cudaEventCreate(&sp);
// Begin the timer
cudaEventRecord(st);
// allocate memory for the device arrays
cudaMalloc((void **) &a_d, size);
cudaMalloc((void **) &b_d, size);
// copy A to device array which would be a one dimensional array
cudaMemcpy(a_d, (void **) A, size, cudaMemcpyHostToDevice);
/* Matrix Normalization */
// <<<number of thread blocks, number of threads per block>>>
// (N + 255)/256 would get the number of thread blocks needed
// to access the elements in the array and in case
// its not evenly divided -> floor()
matrixNorm<<<floor((N+255)/256), 256>>>(a_d, b_d);
// copy device b_d to B
cudaMemcpy((void **) B, b_d, size, cudaMemcpyDeviceToHost);
// End the timer
cudaEventRecord(sp);
// Free the device arrays
cudaFree(a_d);
cudaFree(b_d);
/* Stop Clock */
gettimeofday(&stop, &tzdummy);
runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
// print_B();
float milliseconds = 0;
// return time elapsed between st and sp
cudaEventElapsedTime(&milliseconds, st, sp);
/* Display timing results */
printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("CUDA Timer = %g ms.\n", milliseconds);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
exit(0);
}
|
.file "tmpxft_000f6f76_00000000-6_matrixNorm_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17initialize_inputsv
.type _Z17initialize_inputsv, @function
_Z17initialize_inputsv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %r14d
leaq A(%rip), %r13
leaq B(%rip), %r12
.L4:
movl $0, %ebx
movslq %r14d, %rbp
imulq $6000, %rbp, %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movslq %ebx, %rax
addq %rbp, %rax
movss %xmm0, 0(%r13,%rax,4)
movl $0x00000000, (%r12,%rax,4)
addl $1, %ebx
cmpl $6000, %ebx
jne .L5
addl $1, %r14d
cmpl $6000, %r14d
jne .L4
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z17initialize_inputsv, .-_Z17initialize_inputsv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\nA = "
.LC3:
.string "\n[ "
.LC4:
.string " %5.2f "
.LC5:
.string "]\n"
.text
.globl _Z7print_Av
.type _Z7print_Av, @function
_Z7print_Av:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC3(%rip), %r15
leaq A(%rip), %r13
leaq .LC4(%rip), %r12
.L11:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
movslq %r14d, %rbp
imulq $6000, %rbp, %rbp
.L10:
movslq %ebx, %rax
addq %rbp, %rax
movss 0(%r13,%rax,4), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl $10, %ebx
jne .L10
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
cmpl $10, %r14d
jne .L11
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7print_Av, .-_Z7print_Av
.section .rodata.str1.1
.LC6:
.string "\nB = "
.text
.globl _Z7print_Bv
.type _Z7print_Bv, @function
_Z7print_Bv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC3(%rip), %r15
leaq B(%rip), %r13
leaq .LC4(%rip), %r12
.L17:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
movslq %r14d, %rbp
imulq $6000, %rbp, %rbp
.L16:
movslq %ebx, %rax
addq %rbp, %rax
movss 0(%r13,%rax,4), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl $10, %ebx
jne .L16
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
cmpl $10, %r14d
jne .L17
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7print_Bv, .-_Z7print_Bv
.globl _Z32__device_stub__Z10matrixNormPfS_PfS_
.type _Z32__device_stub__Z10matrixNormPfS_PfS_, @function
_Z32__device_stub__Z10matrixNormPfS_PfS_:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10matrixNormPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z32__device_stub__Z10matrixNormPfS_PfS_, .-_Z32__device_stub__Z10matrixNormPfS_PfS_
.globl _Z10matrixNormPfS_
.type _Z10matrixNormPfS_, @function
_Z10matrixNormPfS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10matrixNormPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10matrixNormPfS_, .-_Z10matrixNormPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "\n---------------------------------------------\n"
.section .rodata.str1.1
.LC8:
.string "Matrix size N = %d"
.LC9:
.string "\nStarting clock.\n\n"
.LC11:
.string "Runtime = %g ms.\n"
.LC12:
.string "CUDA Timer = %g ms.\n"
.LC13:
.string "\nStopped clock."
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $96, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
call _Z17initialize_inputsv
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $6000, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $144000000, %esi
leaq a_d(%rip), %rdi
call cudaMalloc@PLT
movl $144000000, %esi
leaq b_d(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $144000000, %edx
leaq A(%rip), %rsi
movq a_d(%rip), %rdi
call cudaMemcpy@PLT
movl $256, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $24, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
movl $2, %ecx
movl $144000000, %edx
movq b_d(%rip), %rsi
leaq B(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq a_d(%rip), %rdi
call cudaFree@PLT
movq b_d(%rip), %rdi
call cudaFree@PLT
leaq 28(%rsp), %rsi
leaq 64(%rsp), %rdi
call gettimeofday@PLT
movq 64(%rsp), %rbx
subq 48(%rsp), %rbx
imulq $1000000, %rbx, %rbx
addq 72(%rsp), %rbx
subq 56(%rsp), %rbx
movl $0x00000000, 36(%rsp)
leaq 36(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
testq %rbx, %rbx
js .L31
pxor %xmm0, %xmm0
cvtsi2ssq %rbx, %xmm0
.L32:
divss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L35:
movq b_d(%rip), %rsi
movq a_d(%rip), %rdi
call _Z32__device_stub__Z10matrixNormPfS_PfS_
jmp .L30
.L31:
movq %rbx, %rax
shrq %rax
andl $1, %ebx
orq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L32
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z10matrixNormPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixNormPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl B
.bss
.align 32
.type B, @object
.size B, 144000000
B:
.zero 144000000
.globl A
.align 32
.type A, @object
.size A, 144000000
A:
.zero 144000000
.globl b_d
.align 8
.type b_d, @object
.size b_d, 8
b_d:
.zero 8
.globl a_d
.align 8
.type a_d, @object
.size a_d, 8
a_d:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 939524096
.align 4
.LC10:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
// nvcc matrixNorm_CUDA.cu -lm -o norm.out
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 6000 /* Matrix size */
// pointers to the device arrays
float *a_d, *b_d;
/* Matrices */
volatile float A[N][N], B[N][N];
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row][col] = (float)rand() / 32768.0;
B[row][col] = 0.0;
}
}
}
// printing parts of the larger matrices for testing
void print_A() {
printf("\nA = ");
int printing = 10;
if (N < 99) {
printing = N;
}
for (int row = 0; row < printing; row++) {
printf("\n[ ");
for (int col = 0; col < printing; col++) {
printf(" %5.2f ", A[row][col]);
}
printf("]\n");
}
}
void print_B() {
printf("\nB = ");
int printing = 10;
if (N < 99) {
printing = N;
}
for (int row = 0; row < printing; row++) {
printf("\n[ ");
for (int col = 0; col < printing; col++) {
printf(" %5.2f ", B[row][col]);
}
printf("]\n");
}
}
/* Kernel function */
// variables are used to indentify and differentiate between GPU threads
// blockDim -> dimensions of each thread block
// blockIdx -> index of thread block within grid
// threadIdx -> index of thread withing thread block
__global__ void matrixNorm(float *temp_a, float *temp_b) {
// i is the unique thread id
int i = blockDim.x * blockIdx.x + threadIdx.x;
int row;
float mu, sigma; // Mean and Standard Deviation
// if (i == 1) {
// for (int k = 0; k < 10; k++) {
// printf(" %5.2f ", temp_a[k]);
// }
// printf("\n");
// }
// since i is used in array access only allow those
// less than N so no out-of-bounds access happens
if (i < N) {
// printf("Thread num -> %d\n", i);
mu = 0.0;
// temp_a is the one-dimensional form of A
// row * N is used as the starting point for each of the rows
// + i would access the individual elements in each section
for (row=0; row < N; row++)
mu += temp_a[row * N + i];
mu /= (float) N;
sigma = 0.0;
for (row=0; row < N; row++)
sigma += powf(temp_a[row * N + i] - mu, 2.0);
sigma /= (float) N;
sigma = sqrt(sigma);
for (row=0; row < N; row++) {
if (sigma == 0.0)
temp_b[row * N + i] = 0.0;
else
temp_b[row * N + i] = (temp_a[row * N + i] - mu) / sigma;
}
}
__syncthreads();
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval start, stop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
unsigned long long runtime;
/* Initialize A and B */
initialize_inputs();
// size would be an N by N matrix of floats
float size = N*N*sizeof(float);
// print_A();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&start, &tzdummy);
cudaEvent_t st, sp;
cudaEventCreate(&st);
cudaEventCreate(&sp);
// Begin the timer
cudaEventRecord(st);
// allocate memory for the device arrays
cudaMalloc((void **) &a_d, size);
cudaMalloc((void **) &b_d, size);
// copy A to device array which would be a one dimensional array
cudaMemcpy(a_d, (void **) A, size, cudaMemcpyHostToDevice);
/* Matrix Normalization */
// <<<number of thread blocks, number of threads per block>>>
// (N + 255)/256 would get the number of thread blocks needed
// to access the elements in the array and in case
// its not evenly divided -> floor()
matrixNorm<<<floor((N+255)/256), 256>>>(a_d, b_d);
// copy device b_d to B
cudaMemcpy((void **) B, b_d, size, cudaMemcpyDeviceToHost);
// End the timer
cudaEventRecord(sp);
// Free the device arrays
cudaFree(a_d);
cudaFree(b_d);
/* Stop Clock */
gettimeofday(&stop, &tzdummy);
runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
// print_B();
float milliseconds = 0;
// return time elapsed between st and sp
cudaEventElapsedTime(&milliseconds, st, sp);
/* Display timing results */
printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("CUDA Timer = %g ms.\n", milliseconds);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
exit(0);
}
|
// nvcc matrixNorm_CUDA.cu -lm -o norm.out
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 6000 /* Matrix size */
// pointers to the device arrays
float *a_d, *b_d;
/* Matrices */
volatile float A[N][N], B[N][N];
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row][col] = (float)rand() / 32768.0;
B[row][col] = 0.0;
}
}
}
// printing parts of the larger matrices for testing
void print_A() {
printf("\nA = ");
int printing = 10;
if (N < 99) {
printing = N;
}
for (int row = 0; row < printing; row++) {
printf("\n[ ");
for (int col = 0; col < printing; col++) {
printf(" %5.2f ", A[row][col]);
}
printf("]\n");
}
}
void print_B() {
printf("\nB = ");
int printing = 10;
if (N < 99) {
printing = N;
}
for (int row = 0; row < printing; row++) {
printf("\n[ ");
for (int col = 0; col < printing; col++) {
printf(" %5.2f ", B[row][col]);
}
printf("]\n");
}
}
/* Kernel function */
// variables are used to indentify and differentiate between GPU threads
// blockDim -> dimensions of each thread block
// blockIdx -> index of thread block within grid
// threadIdx -> index of thread withing thread block
__global__ void matrixNorm(float *temp_a, float *temp_b) {
// i is the unique thread id
int i = blockDim.x * blockIdx.x + threadIdx.x;
int row;
float mu, sigma; // Mean and Standard Deviation
// if (i == 1) {
// for (int k = 0; k < 10; k++) {
// printf(" %5.2f ", temp_a[k]);
// }
// printf("\n");
// }
// since i is used in array access only allow those
// less than N so no out-of-bounds access happens
if (i < N) {
// printf("Thread num -> %d\n", i);
mu = 0.0;
// temp_a is the one-dimensional form of A
// row * N is used as the starting point for each of the rows
// + i would access the individual elements in each section
for (row=0; row < N; row++)
mu += temp_a[row * N + i];
mu /= (float) N;
sigma = 0.0;
for (row=0; row < N; row++)
sigma += powf(temp_a[row * N + i] - mu, 2.0);
sigma /= (float) N;
sigma = sqrt(sigma);
for (row=0; row < N; row++) {
if (sigma == 0.0)
temp_b[row * N + i] = 0.0;
else
temp_b[row * N + i] = (temp_a[row * N + i] - mu) / sigma;
}
}
__syncthreads();
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval start, stop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
unsigned long long runtime;
/* Initialize A and B */
initialize_inputs();
// size would be an N by N matrix of floats
float size = N*N*sizeof(float);
// print_A();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&start, &tzdummy);
hipEvent_t st, sp;
hipEventCreate(&st);
hipEventCreate(&sp);
// Begin the timer
hipEventRecord(st);
// allocate memory for the device arrays
hipMalloc((void **) &a_d, size);
hipMalloc((void **) &b_d, size);
// copy A to device array which would be a one dimensional array
hipMemcpy(a_d, (void **) A, size, hipMemcpyHostToDevice);
/* Matrix Normalization */
// <<<number of thread blocks, number of threads per block>>>
// (N + 255)/256 would get the number of thread blocks needed
// to access the elements in the array and in case
// its not evenly divided -> floor()
matrixNorm<<<floor((N+255)/256), 256>>>(a_d, b_d);
// copy device b_d to B
hipMemcpy((void **) B, b_d, size, hipMemcpyDeviceToHost);
// End the timer
hipEventRecord(sp);
// Free the device arrays
hipFree(a_d);
hipFree(b_d);
/* Stop Clock */
gettimeofday(&stop, &tzdummy);
runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
// print_B();
float milliseconds = 0;
// return time elapsed between st and sp
hipEventElapsedTime(&milliseconds, st, sp);
/* Display timing results */
printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("CUDA Timer = %g ms.\n", milliseconds);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
exit(0);
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
// nvcc matrixNorm_CUDA.cu -lm -o norm.out
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 6000 /* Matrix size */
// pointers to the device arrays
float *a_d, *b_d;
/* Matrices */
volatile float A[N][N], B[N][N];
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row][col] = (float)rand() / 32768.0;
B[row][col] = 0.0;
}
}
}
// printing parts of the larger matrices for testing
void print_A() {
printf("\nA = ");
int printing = 10;
if (N < 99) {
printing = N;
}
for (int row = 0; row < printing; row++) {
printf("\n[ ");
for (int col = 0; col < printing; col++) {
printf(" %5.2f ", A[row][col]);
}
printf("]\n");
}
}
void print_B() {
printf("\nB = ");
int printing = 10;
if (N < 99) {
printing = N;
}
for (int row = 0; row < printing; row++) {
printf("\n[ ");
for (int col = 0; col < printing; col++) {
printf(" %5.2f ", B[row][col]);
}
printf("]\n");
}
}
/* Kernel function */
// variables are used to indentify and differentiate between GPU threads
// blockDim -> dimensions of each thread block
// blockIdx -> index of thread block within grid
// threadIdx -> index of thread withing thread block
__global__ void matrixNorm(float *temp_a, float *temp_b) {
// i is the unique thread id
int i = blockDim.x * blockIdx.x + threadIdx.x;
int row;
float mu, sigma; // Mean and Standard Deviation
// if (i == 1) {
// for (int k = 0; k < 10; k++) {
// printf(" %5.2f ", temp_a[k]);
// }
// printf("\n");
// }
// since i is used in array access only allow those
// less than N so no out-of-bounds access happens
if (i < N) {
// printf("Thread num -> %d\n", i);
mu = 0.0;
// temp_a is the one-dimensional form of A
// row * N is used as the starting point for each of the rows
// + i would access the individual elements in each section
for (row=0; row < N; row++)
mu += temp_a[row * N + i];
mu /= (float) N;
sigma = 0.0;
for (row=0; row < N; row++)
sigma += powf(temp_a[row * N + i] - mu, 2.0);
sigma /= (float) N;
sigma = sqrt(sigma);
for (row=0; row < N; row++) {
if (sigma == 0.0)
temp_b[row * N + i] = 0.0;
else
temp_b[row * N + i] = (temp_a[row * N + i] - mu) / sigma;
}
}
__syncthreads();
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval start, stop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
unsigned long long runtime;
/* Initialize A and B */
initialize_inputs();
// size would be an N by N matrix of floats
float size = N*N*sizeof(float);
// print_A();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&start, &tzdummy);
hipEvent_t st, sp;
hipEventCreate(&st);
hipEventCreate(&sp);
// Begin the timer
hipEventRecord(st);
// allocate memory for the device arrays
hipMalloc((void **) &a_d, size);
hipMalloc((void **) &b_d, size);
// copy A to device array which would be a one dimensional array
hipMemcpy(a_d, (void **) A, size, hipMemcpyHostToDevice);
/* Matrix Normalization */
// <<<number of thread blocks, number of threads per block>>>
// (N + 255)/256 would get the number of thread blocks needed
// to access the elements in the array and in case
// its not evenly divided -> floor()
matrixNorm<<<floor((N+255)/256), 256>>>(a_d, b_d);
// copy device b_d to B
hipMemcpy((void **) B, b_d, size, hipMemcpyDeviceToHost);
// End the timer
hipEventRecord(sp);
// Free the device arrays
hipFree(a_d);
hipFree(b_d);
/* Stop Clock */
gettimeofday(&stop, &tzdummy);
runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
// print_B();
float milliseconds = 0;
// return time elapsed between st and sp
hipEventElapsedTime(&milliseconds, st, sp);
/* Display timing results */
printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("CUDA Timer = %g ms.\n", milliseconds);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
exit(0);
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixNormPfS_
.globl _Z10matrixNormPfS_
.p2align 8
.type _Z10matrixNormPfS_,@function
_Z10matrixNormPfS_:
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cmpx_gt_i32_e32 0x1770, v1
s_cbranch_execz .LBB0_9
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s2, v1
s_addk_i32 s2, 0x1770
s_cmp_lg_u32 s2, 0x2255100
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v2
s_cbranch_scc1 .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v2, null, 0x45bb8000, 0x45bb8000, v0
v_div_scale_f32 v5, vcc_lo, v0, 0x45bb8000, v0
s_mov_b32 s7, 0
v_rcp_f32_e32 v3, v2
s_mov_b32 s8, 0x3e76c4e1
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v3
v_mul_f32_e32 v4, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v2, v4, v5
v_fmac_f32_e32 v4, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v4, v5
v_div_fmas_f32 v2, v2, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v0, v2, 0x45bb8000, v0
v_mov_b32_e32 v2, 0
.LBB0_4:
v_add_nc_u32_e32 v3, s7, v1
s_addk_i32 s7, 0x1770
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v3, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e64 v4, |v3|
v_frexp_exp_i32_f32_e32 v5, v3
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_ldexp_f32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v5, v5
v_add_f32_e32 v6, 1.0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v10, 0x3f317218, v5
v_cmp_eq_f32_e32 vcc_lo, 1.0, v3
v_rcp_f32_e32 v8, v6
v_add_f32_e32 v9, -1.0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_dual_add_f32 v7, -1.0, v4 :: v_dual_sub_f32 v4, v4, v9
v_fma_f32 v9, v5, 0x3f317218, -v10
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v11, v7, v8
v_fmac_f32_e32 v9, 0xb102e308, v5
v_mul_f32_e32 v5, v6, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v11, v6, -v5
v_fmac_f32_e32 v6, v11, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v5, v6
v_dual_sub_f32 v12, v7, v4 :: v_dual_sub_f32 v5, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v7, v12
v_dual_sub_f32 v5, v5, v6 :: v_dual_sub_f32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v5, v4
v_add_f32_e32 v4, v12, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v8, v4
v_add_f32_e32 v5, v11, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v5, v11
v_dual_mul_f32 v7, v5, v5 :: v_dual_sub_f32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v6, v5, v5, -v7
v_ldexp_f32 v8, v5, 1
v_add_f32_e32 v11, v4, v4
v_ldexp_f32 v12, v4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v5, v11
v_add_f32_e32 v11, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmaak_f32 v13, s8, v11, 0x3e91f4c4
v_sub_f32_e32 v7, v11, v7
v_dual_fmaak_f32 v13, v11, v13, 0x3ecccdef :: v_dual_mul_f32 v14, v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v6, v6, v7 :: v_dual_mul_f32 v15, v11, v13
v_fma_f32 v7, v11, v5, -v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v7, v11, v4
v_fma_f32 v4, v11, v13, -v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v7, v6, v5
v_fmac_f32_e32 v4, v6, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v15, v4
v_sub_f32_e32 v13, v6, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v13
v_dual_add_f32 v4, 0x31739010, v4 :: v_dual_add_f32 v5, v14, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v11, v5, v14
v_dual_add_f32 v14, 0x3f2aaaaa, v6 :: v_dual_sub_f32 v7, v7, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, 0xbf2aaaaa, v14
v_sub_f32_e32 v6, v6, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v6
v_add_f32_e32 v6, v14, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v11, v14, v6
v_dual_mul_f32 v13, v5, v6 :: v_dual_add_f32 v4, v4, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, v5, v6, -v13
v_fmac_f32_e32 v11, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, v7, v6
v_add_f32_e32 v4, v13, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v8, v4
v_sub_f32_e32 v6, v4, v13
v_dual_sub_f32 v6, v11, v6 :: v_dual_sub_f32 v7, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v12, v6
v_dual_sub_f32 v4, v4, v7 :: v_dual_add_f32 v7, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v6, v4
v_sub_f32_e32 v6, v7, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v5, v4
v_dual_sub_f32 v6, v9, v6 :: v_dual_add_f32 v9, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v5, v8, v5 :: v_dual_sub_f32 v10, v9, v7
v_dual_sub_f32 v4, v4, v5 :: v_dual_sub_f32 v5, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v8, v10 :: v_dual_sub_f32 v5, v7, v5
v_dual_add_f32 v10, v6, v4 :: v_dual_add_f32 v5, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v10, v6
v_dual_add_f32 v5, v10, v5 :: v_dual_sub_f32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v10, v7 :: v_dual_add_f32 v7, v9, v5
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v7, v9
v_dual_add_f32 v4, v4, v6 :: v_dual_sub_f32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v4, v5
v_cndmask_b32_e64 v5, 2.0, 1.0, vcc_lo
v_add_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v7, v6, v7 :: v_dual_mul_f32 v8, v5, v6
v_sub_f32_e32 v4, v4, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v6, v5, v6, -v8
v_cmp_class_f32_e64 vcc_lo, v8, 0x204
v_fmac_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v8, v6
v_cndmask_b32_e32 v7, v4, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v7
v_cndmask_b32_e64 v9, 0, 0x37000000, vcc_lo
v_sub_f32_e32 v10, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v11, 0x3fb8aa3b, v10
v_fma_f32 v12, v10, 0x3fb8aa3b, -v11
v_rndne_f32_e32 v13, v11
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v12, 0x32a5705f, v10 :: v_dual_sub_f32 v11, v11, v13
v_sub_f32_e32 v4, v4, v8
v_cvt_i32_f32_e32 v8, v13
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v7|
v_trunc_f32_e32 v7, v5
v_add_f32_e32 v11, v11, v12
v_sub_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_exp_f32_e32 v11, v11
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v9, v4
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v11, v8
v_mul_f32_e32 v8, 0.5, v5
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_trunc_f32_e32 v11, v8
v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, v7, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_neq_f32_e64 s2, v11, v8
v_fma_f32 v4, v6, v4, v6
v_cmp_eq_f32_e64 s3, 0x7f800000, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
v_cndmask_b32_e64 v5, 1.0, v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v4, v4, v6, s3
v_cmp_eq_f32_e64 s3, 0, v3
v_cndmask_b32_e64 v6, 0, v3, s2
v_cmp_class_f32_e64 s2, v3, 0x204
v_bfi_b32 v4, 0x7fffffff, v4, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, 0x7f800000, 0, s3
v_cndmask_b32_e32 v7, 0x7fc00000, v4, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v5, 0x7fffffff, v5, v6
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
s_or_b32 vcc_lo, s3, s2
s_cmp_lg_u32 s7, 0x2255100
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v3, v3
v_cndmask_b32_e32 v3, 0x7fc00000, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v2, v2, v3
s_cbranch_scc1 .LBB0_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, 0x45bb8000, 0x45bb8000, v2
v_div_scale_f32 v6, vcc_lo, v2, 0x45bb8000, v2
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v3, 0x45bb8000, v2
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v3, v2
v_fma_f32 v7, -v5, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v3, v3, v4, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v7
v_cndmask_b32_e64 v3, v3, v5, s2
s_load_b64 s[2:3], s[0:1], 0x8
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x37800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v3, v2, vcc_lo
v_cmp_neq_f32_e64 s0, 0, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_7
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_addk_i32 s1, 0x1770
s_cmp_lg_u32 s1, 0x2255100
global_store_b32 v[2:3], v5, off
s_cbranch_scc0 .LBB0_9
.LBB0_7:
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v2, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_and_saveexec_b32 s7, s0
s_cbranch_execz .LBB0_6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v5, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v6, null, v4, v4, v5
v_rcp_f32_e32 v7, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_div_scale_f32 v8, vcc_lo, v5, v4, v5
v_mul_f32_e32 v9, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v6, v9, v8
v_fmac_f32_e32 v9, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v9, v8
v_div_fmas_f32 v6, v6, v7, v9
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v5, v6, v4, v5
s_branch .LBB0_6
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixNormPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixNormPfS_, .Lfunc_end0-_Z10matrixNormPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixNormPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixNormPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
// nvcc matrixNorm_CUDA.cu -lm -o norm.out
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <math.h>
/* Program Parameters */
#define N 6000 /* Matrix size */
// pointers to the device arrays
float *a_d, *b_d;
/* Matrices */
volatile float A[N][N], B[N][N];
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
srand((unsigned)time(NULL));
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row][col] = (float)rand() / 32768.0;
B[row][col] = 0.0;
}
}
}
// printing parts of the larger matrices for testing
void print_A() {
printf("\nA = ");
int printing = 10;
if (N < 99) {
printing = N;
}
for (int row = 0; row < printing; row++) {
printf("\n[ ");
for (int col = 0; col < printing; col++) {
printf(" %5.2f ", A[row][col]);
}
printf("]\n");
}
}
void print_B() {
printf("\nB = ");
int printing = 10;
if (N < 99) {
printing = N;
}
for (int row = 0; row < printing; row++) {
printf("\n[ ");
for (int col = 0; col < printing; col++) {
printf(" %5.2f ", B[row][col]);
}
printf("]\n");
}
}
/* Kernel function */
// variables are used to indentify and differentiate between GPU threads
// blockDim -> dimensions of each thread block
// blockIdx -> index of thread block within grid
// threadIdx -> index of thread withing thread block
__global__ void matrixNorm(float *temp_a, float *temp_b) {
// i is the unique thread id
int i = blockDim.x * blockIdx.x + threadIdx.x;
int row;
float mu, sigma; // Mean and Standard Deviation
// if (i == 1) {
// for (int k = 0; k < 10; k++) {
// printf(" %5.2f ", temp_a[k]);
// }
// printf("\n");
// }
// since i is used in array access only allow those
// less than N so no out-of-bounds access happens
if (i < N) {
// printf("Thread num -> %d\n", i);
mu = 0.0;
// temp_a is the one-dimensional form of A
// row * N is used as the starting point for each of the rows
// + i would access the individual elements in each section
for (row=0; row < N; row++)
mu += temp_a[row * N + i];
mu /= (float) N;
sigma = 0.0;
for (row=0; row < N; row++)
sigma += powf(temp_a[row * N + i] - mu, 2.0);
sigma /= (float) N;
sigma = sqrt(sigma);
for (row=0; row < N; row++) {
if (sigma == 0.0)
temp_b[row * N + i] = 0.0;
else
temp_b[row * N + i] = (temp_a[row * N + i] - mu) / sigma;
}
}
__syncthreads();
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval start, stop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
unsigned long long runtime;
/* Initialize A and B */
initialize_inputs();
// size would be an N by N matrix of floats
float size = N*N*sizeof(float);
// print_A();
/* Start Clock */
printf("\n---------------------------------------------\n");
printf("Matrix size N = %d", N);
printf("\nStarting clock.\n\n");
gettimeofday(&start, &tzdummy);
hipEvent_t st, sp;
hipEventCreate(&st);
hipEventCreate(&sp);
// Begin the timer
hipEventRecord(st);
// allocate memory for the device arrays
hipMalloc((void **) &a_d, size);
hipMalloc((void **) &b_d, size);
// copy A to device array which would be a one dimensional array
hipMemcpy(a_d, (void **) A, size, hipMemcpyHostToDevice);
/* Matrix Normalization */
// <<<number of thread blocks, number of threads per block>>>
// (N + 255)/256 would get the number of thread blocks needed
// to access the elements in the array and in case
// its not evenly divided -> floor()
matrixNorm<<<floor((N+255)/256), 256>>>(a_d, b_d);
// copy device b_d to B
hipMemcpy((void **) B, b_d, size, hipMemcpyDeviceToHost);
// End the timer
hipEventRecord(sp);
// Free the device arrays
hipFree(a_d);
hipFree(b_d);
/* Stop Clock */
gettimeofday(&stop, &tzdummy);
runtime = (unsigned long long)(stop.tv_sec - start.tv_sec) * 1000000 + (stop.tv_usec - start.tv_usec);
// print_B();
float milliseconds = 0;
// return time elapsed between st and sp
hipEventElapsedTime(&milliseconds, st, sp);
/* Display timing results */
printf("Runtime = %g ms.\n", (float)runtime/(float)1000);
printf("CUDA Timer = %g ms.\n", milliseconds);
printf("\nStopped clock.");
printf("\n---------------------------------------------\n");
exit(0);
}
|
.text
.file "matrixNorm_cuda.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17initialize_inputsv
.LCPI0_0:
.long 0x38000000 # float 3.05175781E-5
.text
.globl _Z17initialize_inputsv
.p2align 4, 0x90
.type _Z17initialize_inputsv,@function
_Z17initialize_inputsv: # @_Z17initialize_inputsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
movq $-24000, %r15 # imm = 0xA240
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, A+24000(%rbx,%r15)
movl $0, B+24000(%rbx,%r15)
addq $4, %r15
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r14
addq $24000, %rbx # imm = 0x5DC0
cmpq $6000, %r14 # imm = 0x1770
jne .LBB0_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z17initialize_inputsv, .Lfunc_end0-_Z17initialize_inputsv
.cfi_endproc
# -- End function
.globl _Z7print_Av # -- Begin function _Z7print_Av
.p2align 4, 0x90
.type _Z7print_Av,@function
_Z7print_Av: # @_Z7print_Av
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $A, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
incq %r14
addq $24000, %rbx # imm = 0x5DC0
cmpq $10, %r14
jne .LBB1_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7print_Av, .Lfunc_end1-_Z7print_Av
.cfi_endproc
# -- End function
.globl _Z7print_Bv # -- Begin function _Z7print_Bv
.p2align 4, 0x90
.type _Z7print_Bv,@function
_Z7print_Bv: # @_Z7print_Bv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $B, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
incq %r14
addq $24000, %rbx # imm = 0x5DC0
cmpq $10, %r14
jne .LBB2_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7print_Bv, .Lfunc_end2-_Z7print_Bv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrixNormPfS_ # -- Begin function _Z25__device_stub__matrixNormPfS_
.p2align 4, 0x90
.type _Z25__device_stub__matrixNormPfS_,@function
_Z25__device_stub__matrixNormPfS_: # @_Z25__device_stub__matrixNormPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10matrixNormPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z25__device_stub__matrixNormPfS_, .Lfunc_end3-_Z25__device_stub__matrixNormPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x38000000 # float 3.05175781E-5
.LCPI4_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
movq $-24000, %r15 # imm = 0xA240
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, A+24000(%rbx,%r15)
movl $0, B+24000(%rbx,%r15)
addq $4, %r15
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %r14
addq $24000, %rbx # imm = 0x5DC0
cmpq $6000, %r14 # imm = 0x1770
jne .LBB4_1
# %bb.4: # %_Z17initialize_inputsv.exit
movl $.Lstr.4, %edi
callq puts@PLT
movl $.L.str.6, %edi
movl $6000, %esi # imm = 0x1770
xorl %eax, %eax
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
leaq 112(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $a_d, %edi
movl $144000000, %esi # imm = 0x8954400
callq hipMalloc
movl $b_d, %edi
movl $144000000, %esi # imm = 0x8954400
callq hipMalloc
movq a_d(%rip), %rdi
movl $A, %esi
movl $144000000, %edx # imm = 0x8954400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967320, %rdi # imm = 0x100000018
leaq 232(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq a_d(%rip), %rax
movq b_d(%rip), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
movq %rsp, %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10matrixNormPfS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
movq b_d(%rip), %rsi
movl $B, %edi
movl $144000000, %edx # imm = 0x8954400
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq a_d(%rip), %rdi
callq hipFree
movq b_d(%rip), %rdi
callq hipFree
leaq 16(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
movq 16(%rsp), %rax
subq 112(%rsp), %rax
movq 24(%rsp), %rbx
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 120(%rsp), %rbx
addq %rax, %rbx
movl $0, (%rsp)
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
movq %rsp, %rdi
callq hipEventElapsedTime
testq %rbx, %rbx
js .LBB4_7
# %bb.8:
cvtsi2ss %rbx, %xmm0
jmp .LBB4_9
.LBB4_7:
movq %rbx, %rax
shrq %rax
andl $1, %ebx
orq %rax, %rbx
cvtsi2ss %rbx, %xmm0
addss %xmm0, %xmm0
.LBB4_9:
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixNormPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type a_d,@object # @a_d
.bss
.globl a_d
.p2align 3, 0x0
a_d:
.quad 0
.size a_d, 8
.type b_d,@object # @b_d
.globl b_d
.p2align 3, 0x0
b_d:
.quad 0
.size b_d, 8
.type A,@object # @A
.globl A
.p2align 4, 0x0
A:
.zero 144000000
.size A, 144000000
.type B,@object # @B
.globl B
.p2align 4, 0x0
B:
.zero 144000000
.size B, 144000000
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nA = "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n[ "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " %5.2f "
.size .L.str.2, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nB = "
.size .L.str.4, 6
.type _Z10matrixNormPfS_,@object # @_Z10matrixNormPfS_
.section .rodata,"a",@progbits
.globl _Z10matrixNormPfS_
.p2align 3, 0x0
_Z10matrixNormPfS_:
.quad _Z25__device_stub__matrixNormPfS_
.size _Z10matrixNormPfS_, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "Matrix size N = %d"
.size .L.str.6, 19
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Runtime = %g ms.\n"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "CUDA Timer = %g ms.\n"
.size .L.str.9, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nStopped clock."
.size .L.str.10, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixNormPfS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "]"
.size .Lstr.1, 2
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nStarting clock.\n"
.size .Lstr.3, 18
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\n---------------------------------------------"
.size .Lstr.4, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixNormPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym a_d
.addrsig_sym b_d
.addrsig_sym A
.addrsig_sym B
.addrsig_sym _Z10matrixNormPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000f6f76_00000000-6_matrixNorm_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17initialize_inputsv
.type _Z17initialize_inputsv, @function
_Z17initialize_inputsv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0, %r14d
leaq A(%rip), %r13
leaq B(%rip), %r12
.L4:
movl $0, %ebx
movslq %r14d, %rbp
imulq $6000, %rbp, %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movslq %ebx, %rax
addq %rbp, %rax
movss %xmm0, 0(%r13,%rax,4)
movl $0x00000000, (%r12,%rax,4)
addl $1, %ebx
cmpl $6000, %ebx
jne .L5
addl $1, %r14d
cmpl $6000, %r14d
jne .L4
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z17initialize_inputsv, .-_Z17initialize_inputsv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\nA = "
.LC3:
.string "\n[ "
.LC4:
.string " %5.2f "
.LC5:
.string "]\n"
.text
.globl _Z7print_Av
.type _Z7print_Av, @function
_Z7print_Av:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC3(%rip), %r15
leaq A(%rip), %r13
leaq .LC4(%rip), %r12
.L11:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
movslq %r14d, %rbp
imulq $6000, %rbp, %rbp
.L10:
movslq %ebx, %rax
addq %rbp, %rax
movss 0(%r13,%rax,4), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl $10, %ebx
jne .L10
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
cmpl $10, %r14d
jne .L11
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7print_Av, .-_Z7print_Av
.section .rodata.str1.1
.LC6:
.string "\nB = "
.text
.globl _Z7print_Bv
.type _Z7print_Bv, @function
_Z7print_Bv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq .LC3(%rip), %r15
leaq B(%rip), %r13
leaq .LC4(%rip), %r12
.L17:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
movslq %r14d, %rbp
imulq $6000, %rbp, %rbp
.L16:
movslq %ebx, %rax
addq %rbp, %rax
movss 0(%r13,%rax,4), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl $10, %ebx
jne .L16
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
cmpl $10, %r14d
jne .L17
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7print_Bv, .-_Z7print_Bv
.globl _Z32__device_stub__Z10matrixNormPfS_PfS_
.type _Z32__device_stub__Z10matrixNormPfS_PfS_, @function
_Z32__device_stub__Z10matrixNormPfS_PfS_:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10matrixNormPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z32__device_stub__Z10matrixNormPfS_PfS_, .-_Z32__device_stub__Z10matrixNormPfS_PfS_
.globl _Z10matrixNormPfS_
.type _Z10matrixNormPfS_, @function
_Z10matrixNormPfS_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10matrixNormPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10matrixNormPfS_, .-_Z10matrixNormPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "\n---------------------------------------------\n"
.section .rodata.str1.1
.LC8:
.string "Matrix size N = %d"
.LC9:
.string "\nStarting clock.\n\n"
.LC11:
.string "Runtime = %g ms.\n"
.LC12:
.string "CUDA Timer = %g ms.\n"
.LC13:
.string "\nStopped clock."
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $96, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
call _Z17initialize_inputsv
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $6000, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $144000000, %esi
leaq a_d(%rip), %rdi
call cudaMalloc@PLT
movl $144000000, %esi
leaq b_d(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movl $144000000, %edx
leaq A(%rip), %rsi
movq a_d(%rip), %rdi
call cudaMemcpy@PLT
movl $256, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $24, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
movl $2, %ecx
movl $144000000, %edx
movq b_d(%rip), %rsi
leaq B(%rip), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq a_d(%rip), %rdi
call cudaFree@PLT
movq b_d(%rip), %rdi
call cudaFree@PLT
leaq 28(%rsp), %rsi
leaq 64(%rsp), %rdi
call gettimeofday@PLT
movq 64(%rsp), %rbx
subq 48(%rsp), %rbx
imulq $1000000, %rbx, %rbx
addq 72(%rsp), %rbx
subq 56(%rsp), %rbx
movl $0x00000000, 36(%rsp)
leaq 36(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
testq %rbx, %rbx
js .L31
pxor %xmm0, %xmm0
cvtsi2ssq %rbx, %xmm0
.L32:
divss .LC10(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L35:
movq b_d(%rip), %rsi
movq a_d(%rip), %rdi
call _Z32__device_stub__Z10matrixNormPfS_PfS_
jmp .L30
.L31:
movq %rbx, %rax
shrq %rax
andl $1, %ebx
orq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
addss %xmm0, %xmm0
jmp .L32
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC14:
.string "_Z10matrixNormPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixNormPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl B
.bss
.align 32
.type B, @object
.size B, 144000000
B:
.zero 144000000
.globl A
.align 32
.type A, @object
.size A, 144000000
A:
.zero 144000000
.globl b_d
.align 8
.type b_d, @object
.size b_d, 8
b_d:
.zero 8
.globl a_d
.align 8
.type a_d, @object
.size a_d, 8
a_d:
.zero 8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 939524096
.align 4
.LC10:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matrixNorm_cuda.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17initialize_inputsv
.LCPI0_0:
.long 0x38000000 # float 3.05175781E-5
.text
.globl _Z17initialize_inputsv
.p2align 4, 0x90
.type _Z17initialize_inputsv,@function
_Z17initialize_inputsv: # @_Z17initialize_inputsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
movq $-24000, %r15 # imm = 0xA240
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, A+24000(%rbx,%r15)
movl $0, B+24000(%rbx,%r15)
addq $4, %r15
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %r14
addq $24000, %rbx # imm = 0x5DC0
cmpq $6000, %r14 # imm = 0x1770
jne .LBB0_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z17initialize_inputsv, .Lfunc_end0-_Z17initialize_inputsv
.cfi_endproc
# -- End function
.globl _Z7print_Av # -- Begin function _Z7print_Av
.p2align 4, 0x90
.type _Z7print_Av,@function
_Z7print_Av: # @_Z7print_Av
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $A, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
incq %r14
addq $24000, %rbx # imm = 0x5DC0
cmpq $10, %r14
jne .LBB1_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7print_Av, .Lfunc_end1-_Z7print_Av
.cfi_endproc
# -- End function
.globl _Z7print_Bv # -- Begin function _Z7print_Bv
.p2align 4, 0x90
.type _Z7print_Bv,@function
_Z7print_Bv: # @_Z7print_Bv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $B, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_1: # =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
incq %r14
addq $24000, %rbx # imm = 0x5DC0
cmpq $10, %r14
jne .LBB2_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7print_Bv, .Lfunc_end2-_Z7print_Bv
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrixNormPfS_ # -- Begin function _Z25__device_stub__matrixNormPfS_
.p2align 4, 0x90
.type _Z25__device_stub__matrixNormPfS_,@function
_Z25__device_stub__matrixNormPfS_: # @_Z25__device_stub__matrixNormPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10matrixNormPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z25__device_stub__matrixNormPfS_, .Lfunc_end3-_Z25__device_stub__matrixNormPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x38000000 # float 3.05175781E-5
.LCPI4_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
movq $-24000, %r15 # imm = 0xA240
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, A+24000(%rbx,%r15)
movl $0, B+24000(%rbx,%r15)
addq $4, %r15
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %r14
addq $24000, %rbx # imm = 0x5DC0
cmpq $6000, %r14 # imm = 0x1770
jne .LBB4_1
# %bb.4: # %_Z17initialize_inputsv.exit
movl $.Lstr.4, %edi
callq puts@PLT
movl $.L.str.6, %edi
movl $6000, %esi # imm = 0x1770
xorl %eax, %eax
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
leaq 112(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $a_d, %edi
movl $144000000, %esi # imm = 0x8954400
callq hipMalloc
movl $b_d, %edi
movl $144000000, %esi # imm = 0x8954400
callq hipMalloc
movq a_d(%rip), %rdi
movl $A, %esi
movl $144000000, %edx # imm = 0x8954400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967320, %rdi # imm = 0x100000018
leaq 232(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq a_d(%rip), %rax
movq b_d(%rip), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 24(%rsp)
movq %rsp, %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10matrixNormPfS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6:
movq b_d(%rip), %rsi
movl $B, %edi
movl $144000000, %edx # imm = 0x8954400
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq a_d(%rip), %rdi
callq hipFree
movq b_d(%rip), %rdi
callq hipFree
leaq 16(%rsp), %rdi
leaq 104(%rsp), %rsi
callq gettimeofday
movq 16(%rsp), %rax
subq 112(%rsp), %rax
movq 24(%rsp), %rbx
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 120(%rsp), %rbx
addq %rax, %rbx
movl $0, (%rsp)
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
movq %rsp, %rdi
callq hipEventElapsedTime
testq %rbx, %rbx
js .LBB4_7
# %bb.8:
cvtsi2ss %rbx, %xmm0
jmp .LBB4_9
.LBB4_7:
movq %rbx, %rax
shrq %rax
andl $1, %ebx
orq %rax, %rbx
cvtsi2ss %rbx, %xmm0
addss %xmm0, %xmm0
.LBB4_9:
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.4, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixNormPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type a_d,@object # @a_d
.bss
.globl a_d
.p2align 3, 0x0
a_d:
.quad 0
.size a_d, 8
.type b_d,@object # @b_d
.globl b_d
.p2align 3, 0x0
b_d:
.quad 0
.size b_d, 8
.type A,@object # @A
.globl A
.p2align 4, 0x0
A:
.zero 144000000
.size A, 144000000
.type B,@object # @B
.globl B
.p2align 4, 0x0
B:
.zero 144000000
.size B, 144000000
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nA = "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n[ "
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " %5.2f "
.size .L.str.2, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nB = "
.size .L.str.4, 6
.type _Z10matrixNormPfS_,@object # @_Z10matrixNormPfS_
.section .rodata,"a",@progbits
.globl _Z10matrixNormPfS_
.p2align 3, 0x0
_Z10matrixNormPfS_:
.quad _Z25__device_stub__matrixNormPfS_
.size _Z10matrixNormPfS_, 8
.type .L.str.6,@object # @.str.6
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.6:
.asciz "Matrix size N = %d"
.size .L.str.6, 19
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Runtime = %g ms.\n"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "CUDA Timer = %g ms.\n"
.size .L.str.9, 21
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nStopped clock."
.size .L.str.10, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10matrixNormPfS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "]"
.size .Lstr.1, 2
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "\nStarting clock.\n"
.size .Lstr.3, 18
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "\n---------------------------------------------"
.size .Lstr.4, 47
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixNormPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym a_d
.addrsig_sym b_d
.addrsig_sym A
.addrsig_sym B
.addrsig_sym _Z10matrixNormPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void Float(float * x, int* y, size_t idxf, size_t idxi, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
x[(idxf)*N + i] = float(y[(idxi-1)*N + i]);
return;
}
|
code for sm_80
Function : _Z5FloatPfPimmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x184], PT, P0 ; /* 0x0000610002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R8, c[0x0][0x17c] ; /* 0x00005f0000087a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0002 */
/*00b0*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe20000000f00 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IADD3 R11, P0, -R11, c[0x0][0x178], RZ ; /* 0x00005e000b0b7a10 */
/* 0x000fc80007f1e1ff */
/*00e0*/ IADD3.X R8, R8, -0x1, RZ, P0, !PT ; /* 0xffffffff08087810 */
/* 0x000fca00007fe4ff */
/*00f0*/ IMAD R2, R8, c[0x0][0x180], RZ ; /* 0x0000600008027a24 */
/* 0x001fc800078e02ff */
/*0100*/ IMAD R7, R11.reuse, c[0x0][0x184], R2 ; /* 0x000061000b077a24 */
/* 0x040fe400078e0202 */
/*0110*/ IMAD.WIDE.U32 R2, R11, c[0x0][0x180], R4 ; /* 0x000060000b027a25 */
/* 0x000fc800078e0004 */
/*0120*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fe200078e0207 */
/*0130*/ LEA R6, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002067a11 */
/* 0x000fc800078010ff */
/*0140*/ LEA.HI.X R7, R2, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0002077a11 */
/* 0x000fca00000f1403 */
/*0150*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0160*/ MOV R3, c[0x0][0x170] ; /* 0x00005c0000037a02 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0d7624 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R2, R3.reuse, c[0x0][0x184], RZ ; /* 0x0000610003027a24 */
/* 0x040fe400078e02ff */
/*0190*/ IMAD.WIDE.U32 R4, R3, c[0x0][0x180], R4 ; /* 0x0000600003047a25 */
/* 0x000fc800078e0004 */
/*01a0*/ IMAD R3, R13, c[0x0][0x174], R2 ; /* 0x00005d000d037a24 */
/* 0x000fe200078e0202 */
/*01b0*/ LEA R2, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004027a11 */
/* 0x000fc800078010ff */
/*01c0*/ IADD3 R3, R5, R3, RZ ; /* 0x0000000305037210 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fc600078e00ff */
/*01e0*/ LEA.HI.X R3, R4, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590004037a11 */
/* 0x000fe200000f1403 */
/*01f0*/ IMAD R4, R5, c[0x0][0xc], R0 ; /* 0x0000030005047a24 */
/* 0x000fca00078e0200 */
/*0200*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fe40003f06070 */
/*0210*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*0220*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*0230*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x184], PT, P0 ; /* 0x0000610005007a0c */
/* 0x000fe20003f06100 */
/*0240*/ I2F R9, R6 ; /* 0x0000000600097306 */
/* 0x004e240000201400 */
/*0250*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0011f4000c101904 */
/*0260*/ @!P0 BRA 0xf0 ; /* 0xfffffe8000008947 */
/* 0x000fea000383ffff */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void Float(float * x, int* y, size_t idxf, size_t idxi, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
x[(idxf)*N + i] = float(y[(idxi-1)*N + i]);
return;
}
|
.file "tmpxft_0008e06a_00000000-6_Float.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5FloatPfPimmmPfPimmm
.type _Z29__device_stub__Z5FloatPfPimmmPfPimmm, @function
_Z29__device_stub__Z5FloatPfPimmmPfPimmm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5FloatPfPimmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5FloatPfPimmmPfPimmm, .-_Z29__device_stub__Z5FloatPfPimmmPfPimmm
.globl _Z5FloatPfPimmm
.type _Z5FloatPfPimmm, @function
_Z5FloatPfPimmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5FloatPfPimmmPfPimmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5FloatPfPimmm, .-_Z5FloatPfPimmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5FloatPfPimmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5FloatPfPimmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void Float(float * x, int* y, size_t idxf, size_t idxi, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
x[(idxf)*N + i] = float(y[(idxi-1)*N + i]);
return;
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Float(float * x, int* y, size_t idxf, size_t idxi, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
x[(idxf)*N + i] = float(y[(idxi-1)*N + i]);
return;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Float(float * x, int* y, size_t idxf, size_t idxi, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
x[(idxf)*N + i] = float(y[(idxi-1)*N + i]);
return;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5FloatPfPimmm
.globl _Z5FloatPfPimmm
.p2align 8
.type _Z5FloatPfPimmm,@function
_Z5FloatPfPimmm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b256 s[16:23], s[0:1], 0x0
s_load_b32 s10, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s22, -1
s_addc_u32 s1, s23, -1
s_mul_i32 s4, s0, s3
s_mul_hi_u32 s5, s0, s2
s_mul_i32 s1, s1, s2
s_add_i32 s4, s5, s4
s_mul_i32 s0, s0, s2
s_add_i32 s1, s4, s1
s_mul_i32 s7, s2, s21
s_lshl_b64 s[4:5], s[0:1], 2
s_mul_hi_u32 s8, s2, s20
s_add_u32 s1, s18, s4
s_mul_i32 s0, s3, s20
s_addc_u32 s4, s19, s5
s_add_i32 s5, s8, s7
s_mul_i32 s8, s2, s20
s_add_i32 s9, s5, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_add_u32 s5, s16, s8
s_addc_u32 s7, s17, s9
s_add_i32 s15, s15, s10
s_mov_b32 s8, 0
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mul_i32 s6, s10, s6
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v0, vcc_lo, s1, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s4, v6, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
global_load_b32 v0, v[0:1], off
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_co_u32 v4, s0, s5, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s7, v6, s0
v_add_nc_u32_e32 v3, s6, v3
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v0, v0
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5FloatPfPimmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5FloatPfPimmm, .Lfunc_end0-_Z5FloatPfPimmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5FloatPfPimmm
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z5FloatPfPimmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Float(float * x, int* y, size_t idxf, size_t idxi, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
x[(idxf)*N + i] = float(y[(idxi-1)*N + i]);
return;
}
|
.text
.file "Float.hip"
.globl _Z20__device_stub__FloatPfPimmm # -- Begin function _Z20__device_stub__FloatPfPimmm
.p2align 4, 0x90
.type _Z20__device_stub__FloatPfPimmm,@function
_Z20__device_stub__FloatPfPimmm: # @_Z20__device_stub__FloatPfPimmm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5FloatPfPimmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z20__device_stub__FloatPfPimmm, .Lfunc_end0-_Z20__device_stub__FloatPfPimmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5FloatPfPimmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5FloatPfPimmm,@object # @_Z5FloatPfPimmm
.section .rodata,"a",@progbits
.globl _Z5FloatPfPimmm
.p2align 3, 0x0
_Z5FloatPfPimmm:
.quad _Z20__device_stub__FloatPfPimmm
.size _Z5FloatPfPimmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5FloatPfPimmm"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__FloatPfPimmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5FloatPfPimmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z5FloatPfPimmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x184], PT, P0 ; /* 0x0000610002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R11, RZ, RZ, 0x1 ; /* 0x00000001ff0b7424 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R8, c[0x0][0x17c] ; /* 0x00005f0000087a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0002 */
/*00b0*/ MOV R4, R0 ; /* 0x0000000000047202 */
/* 0x000fe20000000f00 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IADD3 R11, P0, -R11, c[0x0][0x178], RZ ; /* 0x00005e000b0b7a10 */
/* 0x000fc80007f1e1ff */
/*00e0*/ IADD3.X R8, R8, -0x1, RZ, P0, !PT ; /* 0xffffffff08087810 */
/* 0x000fca00007fe4ff */
/*00f0*/ IMAD R2, R8, c[0x0][0x180], RZ ; /* 0x0000600008027a24 */
/* 0x001fc800078e02ff */
/*0100*/ IMAD R7, R11.reuse, c[0x0][0x184], R2 ; /* 0x000061000b077a24 */
/* 0x040fe400078e0202 */
/*0110*/ IMAD.WIDE.U32 R2, R11, c[0x0][0x180], R4 ; /* 0x000060000b027a25 */
/* 0x000fc800078e0004 */
/*0120*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fe200078e0207 */
/*0130*/ LEA R6, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002067a11 */
/* 0x000fc800078010ff */
/*0140*/ LEA.HI.X R7, R2, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0002077a11 */
/* 0x000fca00000f1403 */
/*0150*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0160*/ MOV R3, c[0x0][0x170] ; /* 0x00005c0000037a02 */
/* 0x000fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0d7624 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R2, R3.reuse, c[0x0][0x184], RZ ; /* 0x0000610003027a24 */
/* 0x040fe400078e02ff */
/*0190*/ IMAD.WIDE.U32 R4, R3, c[0x0][0x180], R4 ; /* 0x0000600003047a25 */
/* 0x000fc800078e0004 */
/*01a0*/ IMAD R3, R13, c[0x0][0x174], R2 ; /* 0x00005d000d037a24 */
/* 0x000fe200078e0202 */
/*01b0*/ LEA R2, P0, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004027a11 */
/* 0x000fc800078010ff */
/*01c0*/ IADD3 R3, R5, R3, RZ ; /* 0x0000000305037210 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fc600078e00ff */
/*01e0*/ LEA.HI.X R3, R4, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590004037a11 */
/* 0x000fe200000f1403 */
/*01f0*/ IMAD R4, R5, c[0x0][0xc], R0 ; /* 0x0000030005047a24 */
/* 0x000fca00078e0200 */
/*0200*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fe40003f06070 */
/*0210*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*0220*/ MOV R0, R4 ; /* 0x0000000400007202 */
/* 0x000fe40000000f00 */
/*0230*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x184], PT, P0 ; /* 0x0000610005007a0c */
/* 0x000fe20003f06100 */
/*0240*/ I2F R9, R6 ; /* 0x0000000600097306 */
/* 0x004e240000201400 */
/*0250*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0011f4000c101904 */
/*0260*/ @!P0 BRA 0xf0 ; /* 0xfffffe8000008947 */
/* 0x000fea000383ffff */
/*0270*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0280*/ BRA 0x280; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5FloatPfPimmm
.globl _Z5FloatPfPimmm
.p2align 8
.type _Z5FloatPfPimmm,@function
_Z5FloatPfPimmm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b256 s[16:23], s[0:1], 0x0
s_load_b32 s10, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s22, -1
s_addc_u32 s1, s23, -1
s_mul_i32 s4, s0, s3
s_mul_hi_u32 s5, s0, s2
s_mul_i32 s1, s1, s2
s_add_i32 s4, s5, s4
s_mul_i32 s0, s0, s2
s_add_i32 s1, s4, s1
s_mul_i32 s7, s2, s21
s_lshl_b64 s[4:5], s[0:1], 2
s_mul_hi_u32 s8, s2, s20
s_add_u32 s1, s18, s4
s_mul_i32 s0, s3, s20
s_addc_u32 s4, s19, s5
s_add_i32 s5, s8, s7
s_mul_i32 s8, s2, s20
s_add_i32 s9, s5, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_add_u32 s5, s16, s8
s_addc_u32 s7, s17, s9
s_add_i32 s15, s15, s10
s_mov_b32 s8, 0
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mul_i32 s6, s10, s6
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v0, vcc_lo, s1, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s4, v6, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
global_load_b32 v0, v[0:1], off
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
v_add_co_u32 v4, s0, s5, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s7, v6, s0
v_add_nc_u32_e32 v3, s6, v3
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v0, v0
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5FloatPfPimmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5FloatPfPimmm, .Lfunc_end0-_Z5FloatPfPimmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5FloatPfPimmm
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z5FloatPfPimmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0008e06a_00000000-6_Float.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z5FloatPfPimmmPfPimmm
.type _Z29__device_stub__Z5FloatPfPimmmPfPimmm, @function
_Z29__device_stub__Z5FloatPfPimmmPfPimmm:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5FloatPfPimmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z5FloatPfPimmmPfPimmm, .-_Z29__device_stub__Z5FloatPfPimmmPfPimmm
.globl _Z5FloatPfPimmm
.type _Z5FloatPfPimmm, @function
_Z5FloatPfPimmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z5FloatPfPimmmPfPimmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5FloatPfPimmm, .-_Z5FloatPfPimmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5FloatPfPimmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5FloatPfPimmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "Float.hip"
.globl _Z20__device_stub__FloatPfPimmm # -- Begin function _Z20__device_stub__FloatPfPimmm
.p2align 4, 0x90
.type _Z20__device_stub__FloatPfPimmm,@function
_Z20__device_stub__FloatPfPimmm: # @_Z20__device_stub__FloatPfPimmm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5FloatPfPimmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z20__device_stub__FloatPfPimmm, .Lfunc_end0-_Z20__device_stub__FloatPfPimmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5FloatPfPimmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5FloatPfPimmm,@object # @_Z5FloatPfPimmm
.section .rodata,"a",@progbits
.globl _Z5FloatPfPimmm
.p2align 3, 0x0
_Z5FloatPfPimmm:
.quad _Z20__device_stub__FloatPfPimmm
.size _Z5FloatPfPimmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5FloatPfPimmm"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__FloatPfPimmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5FloatPfPimmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
extern "C"
// don't forget to compile with "nvcc -ptx cudaKernel.cu -o cudaKernel.ptx
// And to move the ptx file in the resources !
__global__ void add(int n, float* a, float* b, float* sum) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
sum[i] = a[i] + b[i];
}
|
code for sm_80
Function : add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe40000000f00 */
/*0240*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.WIDE R4, R3, R8, c[0x0][0x178] ; /* 0x00005e0003047625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R6, R3, R8, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0290*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fc800078e0208 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0300*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x280 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0360*/ IMAD.WIDE R6, R3, R8, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x0c0fe200078e0208 */
/*0380*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*03c0*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*03d0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03e0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0420*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0440*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0450*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0490*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fc800078e0204 */
/*04b0*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*04c0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*0530*/ FADD R15, R12, R9 ; /* 0x000000090c0f7221 */
/* 0x002fca0000000000 */
/*0540*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ee000c101904 */
/*0550*/ @!P0 BRA 0x350 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
extern "C"
// don't forget to compile with "nvcc -ptx cudaKernel.cu -o cudaKernel.ptx
// And to move the ptx file in the resources !
__global__ void add(int n, float* a, float* b, float* sum) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
sum[i] = a[i] + b[i];
}
|
.file "tmpxft_0014056e_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addiPfS_S_iPfS_S_
.type _Z27__device_stub__Z3addiPfS_S_iPfS_S_, @function
_Z27__device_stub__Z3addiPfS_S_iPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addiPfS_S_iPfS_S_, .-_Z27__device_stub__Z3addiPfS_S_iPfS_S_
.globl add
.type add, @function
add:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add, .-add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
extern "C"
// don't forget to compile with "nvcc -ptx cudaKernel.cu -o cudaKernel.ptx
// And to move the ptx file in the resources !
__global__ void add(int n, float* a, float* b, float* sum) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
sum[i] = a[i] + b[i];
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
// don't forget to compile with "nvcc -ptx cudaKernel.cu -o cudaKernel.ptx
// And to move the ptx file in the resources !
__global__ void add(int n, float* a, float* b, float* sum) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
sum[i] = a[i] + b[i];
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
// don't forget to compile with "nvcc -ptx cudaKernel.cu -o cudaKernel.ptx
// And to move the ptx file in the resources !
__global__ void add(int n, float* a, float* b, float* sum) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
sum[i] = a[i] + b[i];
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add
.globl add
.p2align 8
.type add,@function
add:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add, .Lfunc_end0-add
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
// don't forget to compile with "nvcc -ptx cudaKernel.cu -o cudaKernel.ptx
// And to move the ptx file in the resources !
__global__ void add(int n, float* a, float* b, float* sum) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride)
sum[i] = a[i] + b[i];
}
|
.text
.file "add.hip"
.globl __device_stub__add # -- Begin function __device_stub__add
.p2align 4, 0x90
.type __device_stub__add,@function
__device_stub__add: # @__device_stub__add
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__add, .Lfunc_end0-__device_stub__add
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add,@object # @add
.section .rodata,"a",@progbits
.globl add
.p2align 3, 0x0
add:
.quad __device_stub__add
.size add, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : add
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x340 ; /* 0x000002b000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R6, R0 ; /* 0x0000000000067306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R9, RZ, -R0, RZ ; /* 0x80000000ff097210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ IADD3 R2, R0.reuse, R3, RZ ; /* 0x0000000300027210 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45070 */
/*00e0*/ LOP3.LUT R7, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff077212 */
/* 0x000fc800078e33ff */
/*00f0*/ IADD3 R7, R7, c[0x0][0x160], R0 ; /* 0x0000580007077a10 */
/* 0x000fe20007ffe000 */
/*0100*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0130*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0140*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0150*/ IMAD.HI.U32 R2, R5, R9, R4 ; /* 0x0000000905027227 */
/* 0x000fcc00078e0004 */
/*0160*/ IMAD.HI.U32 R2, R2, R7, RZ ; /* 0x0000000702027227 */
/* 0x000fca00078e00ff */
/*0170*/ IADD3 R4, -R2, RZ, RZ ; /* 0x000000ff02047210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R7, R0, R4, R7 ; /* 0x0000000400077224 */
/* 0x000fca00078e0207 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R7, -R0, R7, RZ ; /* 0x0000000700070210 */
/* 0x000fe40007ffe1ff */
/*01b0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01d0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ @!P2 LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff02a212 */
/* 0x000fc800078e33ff */
/*01f0*/ IADD3 R4, R2.reuse, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x040fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f26070 */
/*0210*/ LOP3.LUT P0, R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fda000780c0ff */
/*0220*/ @!P0 BRA 0x330 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0230*/ MOV R8, 0x4 ; /* 0x0000000400087802 */
/* 0x000fe40000000f00 */
/*0240*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD.WIDE R4, R3, R8, c[0x0][0x178] ; /* 0x00005e0003047625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R6, R3, R8, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e0208 */
/*0280*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000a8000c1e1900 */
/*0290*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0002a2000c1e1900 */
/*02a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*02c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fc800078e0208 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x004fca0000000000 */
/*0300*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*0310*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*0320*/ @P0 BRA 0x280 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0330*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0340*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0350*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0360*/ IMAD.WIDE R6, R3, R8, c[0x0][0x170] ; /* 0x00005c0003067625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R4, R3.reuse, R8.reuse, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x0c0fe200078e0208 */
/*0380*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0390*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x001ea2000c1e1900 */
/*03a0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fc800078e0208 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*03c0*/ FADD R19, R2, R11 ; /* 0x0000000b02137221 */
/* 0x004fe40000000000 */
/*03d0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03e0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03f0*/ LDG.E R2, [R12.64] ; /* 0x000000040c027981 */
/* 0x000ea8000c1e1900 */
/*0400*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0420*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fc800078e020c */
/*0430*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0440*/ FADD R21, R2, R17 ; /* 0x0000001102157221 */
/* 0x004fca0000000000 */
/*0450*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0460*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R23, [R4.64] ; /* 0x0000000404177981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0490*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0206 */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fc800078e0204 */
/*04b0*/ FADD R23, R2, R23 ; /* 0x0000001702177221 */
/* 0x004fca0000000000 */
/*04c0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04d0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000e68000c1e1900 */
/*04e0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000e62000c1e1900 */
/*04f0*/ IMAD.WIDE R10, R0.reuse, 0x4, R16 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0210 */
/*0500*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0510*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*0520*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x160], PT ; /* 0x0000580003007a0c */
/* 0x000fe20003f06270 */
/*0530*/ FADD R15, R12, R9 ; /* 0x000000090c0f7221 */
/* 0x002fca0000000000 */
/*0540*/ STG.E [R10.64], R15 ; /* 0x0000000f0a007986 */
/* 0x0001ee000c101904 */
/*0550*/ @!P0 BRA 0x350 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected add
.globl add
.p2align 8
.type add,@function
add:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v6
v_cmp_le_i32_e64 s0, s12, v1
global_store_b32 v[4:5], v0, off
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel add
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size add, .Lfunc_end0-add
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: add
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: add.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0014056e_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addiPfS_S_iPfS_S_
.type _Z27__device_stub__Z3addiPfS_S_iPfS_S_, @function
_Z27__device_stub__Z3addiPfS_S_iPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq add(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z3addiPfS_S_iPfS_S_, .-_Z27__device_stub__Z3addiPfS_S_iPfS_S_
.globl add
.type add, @function
add:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size add, .-add
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "add"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq add(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "add.hip"
.globl __device_stub__add # -- Begin function __device_stub__add
.p2align 4, 0x90
.type __device_stub__add,@function
__device_stub__add: # @__device_stub__add
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $add, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__add, .Lfunc_end0-__device_stub__add
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $add, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type add,@object # @add
.section .rodata,"a",@progbits
.globl add
.p2align 3, 0x0
add:
.quad __device_stub__add
.size add, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "add"
.size .L__unnamed_1, 4
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__add
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym add
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float* var_13,float* var_14,float var_15,float var_16,float var_17,float var_18,float* var_19,float var_20,float var_21,float var_22) {
comp = +1.9693E-12f * (-1.6217E-27f - var_3);
float tmp_1 = -1.1476E20f;
float tmp_2 = -1.4052E17f;
comp = tmp_2 - tmp_1 + atan2f(+1.0054E35f, -1.1269E16f);
if (comp >= (var_4 / +0.0f - -1.2436E25f)) {
comp += (+1.3861E-17f / var_5 - var_6);
comp += (+1.4150E35f + +1.4644E26f - (var_7 - (var_8 - acosf(var_9 + var_10))));
float tmp_3 = -1.5285E35f;
comp += tmp_3 * var_11 / var_12;
}
for (int i=0; i < var_1; ++i) {
var_13[i] = logf((+1.9498E-22f - (var_15 - (+0.0f - -0.0f + (+1.0670E34f - var_16)))));
var_14[i] = +0.0f;
comp += var_14[i] - var_13[i] - var_17 * coshf((var_18 - +1.3579E-36f + +1.9518E-43f));
}
for (int i=0; i < var_2; ++i) {
var_19[i] = +1.0360E-42f;
comp += var_19[i] / var_20 + var_21 / (var_22 + -1.4828E-36f);
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float* tmp_14 = initPointer( atof(argv[14]) );
float* tmp_15 = initPointer( atof(argv[15]) );
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float* tmp_20 = initPointer( atof(argv[20]) );
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
cudaDeviceSynchronize();
return 0;
}
|
.file "tmpxft_0006182e_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff
.type _Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff, @function
_Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff:
.LFB2083:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movl %esi, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm2, 44(%rsp)
movss %xmm3, 40(%rsp)
movss %xmm4, 36(%rsp)
movss %xmm5, 32(%rsp)
movss %xmm6, 28(%rsp)
movss %xmm7, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 8(%rsp), %rax
movq %rax, 240(%rsp)
leaq 360(%rsp), %rax
movq %rax, 248(%rsp)
leaq 368(%rsp), %rax
movq %rax, 256(%rsp)
leaq 376(%rsp), %rax
movq %rax, 264(%rsp)
leaq 384(%rsp), %rax
movq %rax, 272(%rsp)
movq %rsp, %rax
movq %rax, 280(%rsp)
leaq 392(%rsp), %rax
movq %rax, 288(%rsp)
leaq 400(%rsp), %rax
movq %rax, 296(%rsp)
leaq 408(%rsp), %rax
movq %rax, 304(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 344
pushq 72(%rsp)
.cfi_def_cfa_offset 352
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefiiffffffffffPfS_ffffS_fff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff, .-_Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff
.globl _Z7computefiiffffffffffPfS_ffffS_fff
.type _Z7computefiiffffffffffPfS_ffffS_fff, @function
_Z7computefiiffffffffffPfS_ffffS_fff:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movss 168(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 104(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 96(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiiffffffffffPfS_ffffS_fff, .-_Z7computefiiffffffffffPfS_ffffS_fff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r15
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 136(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -80(%rsp), %rsp
.cfi_def_cfa_offset 320
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 88(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 96(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r15, %r8
movq %r14, %rcx
movq %r13, %rdx
pxor %xmm7, %xmm7
cvtsd2ss 160(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 168(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 176(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 184(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 192(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 200(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movl %r12d, %esi
movl %ebp, %edi
call _Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff
addq $80, %rsp
.cfi_def_cfa_offset 240
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiiffffffffffPfS_ffffS_fff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiiffffffffffPfS_ffffS_fff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float* var_13,float* var_14,float var_15,float var_16,float var_17,float var_18,float* var_19,float var_20,float var_21,float var_22) {
comp = +1.9693E-12f * (-1.6217E-27f - var_3);
float tmp_1 = -1.1476E20f;
float tmp_2 = -1.4052E17f;
comp = tmp_2 - tmp_1 + atan2f(+1.0054E35f, -1.1269E16f);
if (comp >= (var_4 / +0.0f - -1.2436E25f)) {
comp += (+1.3861E-17f / var_5 - var_6);
comp += (+1.4150E35f + +1.4644E26f - (var_7 - (var_8 - acosf(var_9 + var_10))));
float tmp_3 = -1.5285E35f;
comp += tmp_3 * var_11 / var_12;
}
for (int i=0; i < var_1; ++i) {
var_13[i] = logf((+1.9498E-22f - (var_15 - (+0.0f - -0.0f + (+1.0670E34f - var_16)))));
var_14[i] = +0.0f;
comp += var_14[i] - var_13[i] - var_17 * coshf((var_18 - +1.3579E-36f + +1.9518E-43f));
}
for (int i=0; i < var_2; ++i) {
var_19[i] = +1.0360E-42f;
comp += var_19[i] / var_20 + var_21 / (var_22 + -1.4828E-36f);
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float* tmp_14 = initPointer( atof(argv[14]) );
float* tmp_15 = initPointer( atof(argv[15]) );
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float* tmp_20 = initPointer( atof(argv[20]) );
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
cudaDeviceSynchronize();
return 0;
}
|
/* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float* var_13,float* var_14,float var_15,float var_16,float var_17,float var_18,float* var_19,float var_20,float var_21,float var_22) {
comp = +1.9693E-12f * (-1.6217E-27f - var_3);
float tmp_1 = -1.1476E20f;
float tmp_2 = -1.4052E17f;
comp = tmp_2 - tmp_1 + atan2f(+1.0054E35f, -1.1269E16f);
if (comp >= (var_4 / +0.0f - -1.2436E25f)) {
comp += (+1.3861E-17f / var_5 - var_6);
comp += (+1.4150E35f + +1.4644E26f - (var_7 - (var_8 - acosf(var_9 + var_10))));
float tmp_3 = -1.5285E35f;
comp += tmp_3 * var_11 / var_12;
}
for (int i=0; i < var_1; ++i) {
var_13[i] = logf((+1.9498E-22f - (var_15 - (+0.0f - -0.0f + (+1.0670E34f - var_16)))));
var_14[i] = +0.0f;
comp += var_14[i] - var_13[i] - var_17 * coshf((var_18 - +1.3579E-36f + +1.9518E-43f));
}
for (int i=0; i < var_2; ++i) {
var_19[i] = +1.0360E-42f;
comp += var_19[i] / var_20 + var_21 / (var_22 + -1.4828E-36f);
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float* tmp_14 = initPointer( atof(argv[14]) );
float* tmp_15 = initPointer( atof(argv[15]) );
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float* tmp_20 = initPointer( atof(argv[20]) );
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
hipDeviceSynchronize();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,float var_3,float var_4,float var_5,float var_6,float var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float* var_13,float* var_14,float var_15,float var_16,float var_17,float var_18,float* var_19,float var_20,float var_21,float var_22) {
comp = +1.9693E-12f * (-1.6217E-27f - var_3);
float tmp_1 = -1.1476E20f;
float tmp_2 = -1.4052E17f;
comp = tmp_2 - tmp_1 + atan2f(+1.0054E35f, -1.1269E16f);
if (comp >= (var_4 / +0.0f - -1.2436E25f)) {
comp += (+1.3861E-17f / var_5 - var_6);
comp += (+1.4150E35f + +1.4644E26f - (var_7 - (var_8 - acosf(var_9 + var_10))));
float tmp_3 = -1.5285E35f;
comp += tmp_3 * var_11 / var_12;
}
for (int i=0; i < var_1; ++i) {
var_13[i] = logf((+1.9498E-22f - (var_15 - (+0.0f - -0.0f + (+1.0670E34f - var_16)))));
var_14[i] = +0.0f;
comp += var_14[i] - var_13[i] - var_17 * coshf((var_18 - +1.3579E-36f + +1.9518E-43f));
}
for (int i=0; i < var_2; ++i) {
var_19[i] = +1.0360E-42f;
comp += var_19[i] / var_20 + var_21 / (var_22 + -1.4828E-36f);
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float* tmp_14 = initPointer( atof(argv[14]) );
float* tmp_15 = initPointer( atof(argv[15]) );
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float* tmp_20 = initPointer( atof(argv[20]) );
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23);
hipDeviceSynchronize();
return 0;
}
|
.text
.file "test.hip"
.globl _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff # -- Begin function _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.p2align 4, 0x90
.type _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff,@function
_Z22__device_stub__computefiiffffffffffPfS_ffffS_fff: # @_Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movss %xmm0, 36(%rsp)
movl %edi, 32(%rsp)
movl %esi, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 104(%rsp), %rax
movq %rax, 216(%rsp)
leaq 96(%rsp), %rax
movq %rax, 224(%rsp)
leaq 328(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
leaq 352(%rsp), %rax
movq %rax, 256(%rsp)
leaq 88(%rsp), %rax
movq %rax, 264(%rsp)
leaq 360(%rsp), %rax
movq %rax, 272(%rsp)
leaq 368(%rsp), %rax
movq %rax, 280(%rsp)
leaq 376(%rsp), %rax
movq %rax, 288(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefiiffffffffffPfS_ffffS_fff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff, .Lfunc_end0-_Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 224(%rsp) # 8-byte Spill
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 80(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 80(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $10, %r13
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 120(%r15), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 80(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 80(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit50
movq 128(%r15), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 80(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 80(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %rbp
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_5
# %bb.6: # %_Z11initPointerf.exit54
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 80(%rsp) # 4-byte Spill
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 88(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 72(%rsp)
movss %xmm9, 64(%rsp)
movss %xmm10, 56(%rsp)
movss %xmm11, 48(%rsp)
movss %xmm12, 40(%rsp)
movss %xmm13, 32(%rsp)
movss %xmm14, 24(%rsp)
movss %xmm15, 16(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, (%rsp)
movq 224(%rsp), %rdi # 8-byte Reload
# kill: def $edi killed $edi killed $rdi
movl %r14d, %esi
movaps %xmm5, %xmm3
movaps %xmm6, %xmm4
movaps %xmm7, %xmm5
movss 88(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 80(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r12, %rdx
movq %r13, %rcx
movq %rbp, %r8
callq _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.LBB2_8:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiiffffffffffPfS_ffffS_fff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiiffffffffffPfS_ffffS_fff,@object # @_Z7computefiiffffffffffPfS_ffffS_fff
.section .rodata,"a",@progbits
.globl _Z7computefiiffffffffffPfS_ffffS_fff
.p2align 3, 0x0
_Z7computefiiffffffffffPfS_ffffS_fff:
.quad _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.size _Z7computefiiffffffffffPfS_ffffS_fff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiiffffffffffPfS_ffffS_fff"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiiffffffffffPfS_ffffS_fff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0006182e_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff
.type _Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff, @function
_Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff:
.LFB2083:
.cfi_startproc
endbr64
subq $328, %rsp
.cfi_def_cfa_offset 336
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movl %esi, 52(%rsp)
movss %xmm1, 48(%rsp)
movss %xmm2, 44(%rsp)
movss %xmm3, 40(%rsp)
movss %xmm4, 36(%rsp)
movss %xmm5, 32(%rsp)
movss %xmm6, 28(%rsp)
movss %xmm7, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 24(%rsp), %rax
movq %rax, 200(%rsp)
leaq 336(%rsp), %rax
movq %rax, 208(%rsp)
leaq 344(%rsp), %rax
movq %rax, 216(%rsp)
leaq 352(%rsp), %rax
movq %rax, 224(%rsp)
leaq 16(%rsp), %rax
movq %rax, 232(%rsp)
leaq 8(%rsp), %rax
movq %rax, 240(%rsp)
leaq 360(%rsp), %rax
movq %rax, 248(%rsp)
leaq 368(%rsp), %rax
movq %rax, 256(%rsp)
leaq 376(%rsp), %rax
movq %rax, 264(%rsp)
leaq 384(%rsp), %rax
movq %rax, 272(%rsp)
movq %rsp, %rax
movq %rax, 280(%rsp)
leaq 392(%rsp), %rax
movq %rax, 288(%rsp)
leaq 400(%rsp), %rax
movq %rax, 296(%rsp)
leaq 408(%rsp), %rax
movq %rax, 304(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 344
pushq 72(%rsp)
.cfi_def_cfa_offset 352
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefiiffffffffffPfS_ffffS_fff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff, .-_Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff
.globl _Z7computefiiffffffffffPfS_ffffS_fff
.type _Z7computefiiffffffffffPfS_ffffS_fff, @function
_Z7computefiiffffffffffPfS_ffffS_fff:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movss 168(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 160(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 152(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 144(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 136(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 128(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 120(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 112(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 104(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 96(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff
addq $88, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiiffffffffffPfS_ffffS_fff, .-_Z7computefiiffffffffffPfS_ffffS_fff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r13
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r15
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 152(%rsp)
movl $1, 156(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 136(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -80(%rsp), %rsp
.cfi_def_cfa_offset 320
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 88(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 96(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 104(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 112(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 120(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 128(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 136(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 144(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 152(%rsp), %xmm1
movss %xmm1, (%rsp)
movq %r15, %r8
movq %r14, %rcx
movq %r13, %rdx
pxor %xmm7, %xmm7
cvtsd2ss 160(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 168(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 176(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 184(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 192(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 200(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movl %r12d, %esi
movl %ebp, %edi
call _Z50__device_stub__Z7computefiiffffffffffPfS_ffffS_ffffiiffffffffffPfS_ffffS_fff
addq $80, %rsp
.cfi_def_cfa_offset 240
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiiffffffffffPfS_ffffS_fff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiiffffffffffPfS_ffffS_fff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "test.hip"
.globl _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff # -- Begin function _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.p2align 4, 0x90
.type _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff,@function
_Z22__device_stub__computefiiffffffffffPfS_ffffS_fff: # @_Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movss %xmm0, 36(%rsp)
movl %edi, 32(%rsp)
movl %esi, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movss %xmm4, 12(%rsp)
movss %xmm5, 8(%rsp)
movss %xmm6, 4(%rsp)
movss %xmm7, (%rsp)
movq %rdx, 104(%rsp)
movq %rcx, 96(%rsp)
movq %r8, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 304(%rsp), %rax
movq %rax, 192(%rsp)
leaq 312(%rsp), %rax
movq %rax, 200(%rsp)
leaq 320(%rsp), %rax
movq %rax, 208(%rsp)
leaq 104(%rsp), %rax
movq %rax, 216(%rsp)
leaq 96(%rsp), %rax
movq %rax, 224(%rsp)
leaq 328(%rsp), %rax
movq %rax, 232(%rsp)
leaq 336(%rsp), %rax
movq %rax, 240(%rsp)
leaq 344(%rsp), %rax
movq %rax, 248(%rsp)
leaq 352(%rsp), %rax
movq %rax, 256(%rsp)
leaq 88(%rsp), %rax
movq %rax, 264(%rsp)
leaq 360(%rsp), %rax
movq %rax, 272(%rsp)
leaq 368(%rsp), %rax
movq %rax, 280(%rsp)
leaq 376(%rsp), %rax
movq %rax, 288(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefiiffffffffffPfS_ffffS_fff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff, .Lfunc_end0-_Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 224(%rsp) # 8-byte Spill
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 64(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 88(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 144(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 80(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 80(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $10, %r13
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 120(%r15), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 80(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 80(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r13
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r13,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit50
movq 128(%r15), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
movsd %xmm0, 136(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 128(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 120(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 112(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 80(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 80(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %rbp
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_5
# %bb.6: # %_Z11initPointerf.exit54
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 80(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 104(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 96(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movsd 96(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 104(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 80(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 120(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 136(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 144(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 80(%rsp) # 4-byte Spill
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 88(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 72(%rsp)
movss %xmm9, 64(%rsp)
movss %xmm10, 56(%rsp)
movss %xmm11, 48(%rsp)
movss %xmm12, 40(%rsp)
movss %xmm13, 32(%rsp)
movss %xmm14, 24(%rsp)
movss %xmm15, 16(%rsp)
movss %xmm3, 8(%rsp)
movss %xmm4, (%rsp)
movq 224(%rsp), %rdi # 8-byte Reload
# kill: def $edi killed $edi killed $rdi
movl %r14d, %esi
movaps %xmm5, %xmm3
movaps %xmm6, %xmm4
movaps %xmm7, %xmm5
movss 88(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 80(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
movq %r12, %rdx
movq %r13, %rcx
movq %rbp, %r8
callq _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.LBB2_8:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiiffffffffffPfS_ffffS_fff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiiffffffffffPfS_ffffS_fff,@object # @_Z7computefiiffffffffffPfS_ffffS_fff
.section .rodata,"a",@progbits
.globl _Z7computefiiffffffffffPfS_ffffS_fff
.p2align 3, 0x0
_Z7computefiiffffffffffPfS_ffffS_fff:
.quad _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.size _Z7computefiiffffffffffPfS_ffffS_fff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiiffffffffffPfS_ffffS_fff"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiiffffffffffPfS_ffffS_fff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiiffffffffffPfS_ffffS_fff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/*
============================================================================
Filename : algorithm.c
Author : Your name goes here
SCIPER : Your SCIPER number
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <cuda_runtime.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void gpu_calculation(double* input, double* output, int length)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int index = y * length + x;
if(x > 1 && x < length - 1 && y > 1 && y < length - 1) {
output[index] = 0;/*(input[(x-1)*(length)+(y-1)] +
input[(x-1)*(length)+(y)] +
input[(x-1)*(length)+(y+1)] +
input[(x)*(length)+(y-1)] +
input[(x)*(length)+(y)] +
input[(x)*(length)+(y+1)] +
input[(x+1)*(length)+(y-1)] +
input[(x+1)*(length)+(y)] +
input[(x+1)*(length)+(y+1)]) / 9;*/
}
/*if(x == length / 2 - 1 && y == length / 2 - 1) {
return;
}
if(x == length / 2 && y == length / 2 - 1) {
return;
}
if(x == length / 2 - 1 && y == length / 2) {
return;
}
if(x == length / 2 && y == length / 2) {
return;
}*/
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
cudaEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
cudaEventCreate(&cpy_H2D_start);
cudaEventCreate(&cpy_H2D_end);
cudaEventCreate(&cpy_D2H_start);
cudaEventCreate(&cpy_D2H_end);
cudaEventCreate(&comp_start);
cudaEventCreate(&comp_end);
/* Preprocessing goes here */
size_t size = length*length*sizeof(double);
double* gpu_input;
double* gpu_output;
cout<<cudaSuccess<<endl;
cudaEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
cout<<cudaMalloc( (void**)&gpu_input, size)<<endl;
cout<<cudaMalloc( (void**)&gpu_output, size)<<endl;
cout<<cudaMemcpy((void*)gpu_input, (void*)input, size, cudaMemcpyHostToDevice)<<endl;
cout<<cudaMemcpy((void*)gpu_output, (void*)output, size, cudaMemcpyHostToDevice)<<endl;
cudaDeviceSynchronize();
cudaEventRecord(cpy_H2D_end);
cudaEventSynchronize(cpy_H2D_end);
//Copy array from host to device
cudaEventRecord(comp_start);
/* GPU calculation goes here */
int thrsPerBlock(64);
int nBlks(length/64 + 1);
/*for(int i = 0; i < iterations-1; i++){
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
cudaDeviceSynchronize();
cout<<cudaGetLastError()<<endl;
double * temp = gpu_output;
gpu_output = gpu_input;
gpu_input = temp;
}*/
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
cudaDeviceSynchronize();
cudaEventRecord(comp_end);
cudaEventSynchronize(comp_end);
cudaEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cout<<cudaMemcpy((void*)output, (void*)gpu_output, size, cudaMemcpyDeviceToHost)<<endl;
cudaDeviceSynchronize();
cudaEventRecord(cpy_D2H_end);
cudaEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
cudaFree(gpu_input);
cudaFree(gpu_output);
float time;
cudaEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
}
|
code for sm_80
Function : _Z15gpu_calculationPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06070 */
/*0090*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc600078e0205 */
/*00a0*/ ISETP.LT.U32.OR P0, PT, R0, 0x2, P0 ; /* 0x000000020000780c */
/* 0x000fc80000701470 */
/*00b0*/ ISETP.LT.U32.OR P0, PT, R3, 0x2, P0 ; /* 0x000000020300780c */
/* 0x000fc80000701470 */
/*00c0*/ ISETP.GE.U32.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fda0008706470 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0200 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0110*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0002 */
/*0120*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b04 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
============================================================================
Filename : algorithm.c
Author : Your name goes here
SCIPER : Your SCIPER number
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <cuda_runtime.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void gpu_calculation(double* input, double* output, int length)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int index = y * length + x;
if(x > 1 && x < length - 1 && y > 1 && y < length - 1) {
output[index] = 0;/*(input[(x-1)*(length)+(y-1)] +
input[(x-1)*(length)+(y)] +
input[(x-1)*(length)+(y+1)] +
input[(x)*(length)+(y-1)] +
input[(x)*(length)+(y)] +
input[(x)*(length)+(y+1)] +
input[(x+1)*(length)+(y-1)] +
input[(x+1)*(length)+(y)] +
input[(x+1)*(length)+(y+1)]) / 9;*/
}
/*if(x == length / 2 - 1 && y == length / 2 - 1) {
return;
}
if(x == length / 2 && y == length / 2 - 1) {
return;
}
if(x == length / 2 - 1 && y == length / 2) {
return;
}
if(x == length / 2 && y == length / 2) {
return;
}*/
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
cudaEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
cudaEventCreate(&cpy_H2D_start);
cudaEventCreate(&cpy_H2D_end);
cudaEventCreate(&cpy_D2H_start);
cudaEventCreate(&cpy_D2H_end);
cudaEventCreate(&comp_start);
cudaEventCreate(&comp_end);
/* Preprocessing goes here */
size_t size = length*length*sizeof(double);
double* gpu_input;
double* gpu_output;
cout<<cudaSuccess<<endl;
cudaEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
cout<<cudaMalloc( (void**)&gpu_input, size)<<endl;
cout<<cudaMalloc( (void**)&gpu_output, size)<<endl;
cout<<cudaMemcpy((void*)gpu_input, (void*)input, size, cudaMemcpyHostToDevice)<<endl;
cout<<cudaMemcpy((void*)gpu_output, (void*)output, size, cudaMemcpyHostToDevice)<<endl;
cudaDeviceSynchronize();
cudaEventRecord(cpy_H2D_end);
cudaEventSynchronize(cpy_H2D_end);
//Copy array from host to device
cudaEventRecord(comp_start);
/* GPU calculation goes here */
int thrsPerBlock(64);
int nBlks(length/64 + 1);
/*for(int i = 0; i < iterations-1; i++){
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
cudaDeviceSynchronize();
cout<<cudaGetLastError()<<endl;
double * temp = gpu_output;
gpu_output = gpu_input;
gpu_input = temp;
}*/
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
cudaDeviceSynchronize();
cudaEventRecord(comp_end);
cudaEventSynchronize(comp_end);
cudaEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cout<<cudaMemcpy((void*)output, (void*)gpu_output, size, cudaMemcpyDeviceToHost)<<endl;
cudaDeviceSynchronize();
cudaEventRecord(cpy_D2H_end);
cudaEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
cudaFree(gpu_input);
cudaFree(gpu_output);
float time;
cudaEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
}
|
.file "tmpxft_0008219e_00000000-6_implementation.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13array_processPdS_ii
.type _Z13array_processPdS_ii, @function
_Z13array_processPdS_ii:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movl %ecx, -28(%rsp)
testl %ecx, %ecx
jle .L3
movq %rsi, %r8
movl %edx, %r10d
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
leal -1(%rax), %ecx
movl %ecx, %edx
imull %r10d, %edx
leal (%rcx,%rdx), %r13d
movslq %r13d, %r13
salq $3, %r13
leal (%rdx,%r10), %esi
addl %esi, %ecx
movslq %ecx, %rcx
leaq 0(,%rcx,8), %r14
addl %eax, %edx
movslq %edx, %rdx
leaq 0(,%rdx,8), %r15
addl %esi, %eax
cltq
salq $3, %rax
movq %rax, -40(%rsp)
movslq %r10d, %rbp
leaq 0(,%rbp,8), %r11
leal -3(%r10), %eax
salq $4, %rbp
movl $0, %edx
leaq 8(,%rax,8), %rax
movq %rax, -8(%rsp)
leal -1(%r10), %r12d
movsd .LC0(%rip), %xmm1
movsd .LC1(%rip), %xmm2
movq %r13, -24(%rsp)
movq %r14, -16(%rsp)
movl %r10d, %ebx
jmp .L5
.L8:
leaq (%rax,%rbp), %r14
leaq (%rax,%r13), %rcx
movq %r14, %rsi
.L6:
movsd (%rax), %xmm0
addsd 8(%rax), %xmm0
addsd 16(%rax), %xmm0
addsd (%rdi,%rcx), %xmm0
addsd 8(%rdi,%rcx), %xmm0
addsd 16(%rdi,%rcx), %xmm0
addsd (%rsi), %xmm0
addsd 8(%rsi), %xmm0
addsd 16(%rsi), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 8(%r8,%rcx)
addq $8, %rax
addq $8, %rsi
addq $8, %rcx
cmpq %r9, %rax
jne .L6
addl $1, %r10d
movq %r14, %rax
subq %r11, %rax
addq %r11, %r9
cmpl %r12d, %r10d
jne .L8
.L7:
movq -24(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movq -16(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movsd %xmm2, (%r8,%r15)
movq -40(%rsp), %rax
movsd %xmm2, (%r8,%rax)
addl $1, %edx
movq %r8, %rax
movq %rdi, %r8
cmpl %edx, -28(%rsp)
je .L3
movq %rax, %rdi
.L5:
cmpl $2, %ebx
jle .L7
movq %rdi, %rax
movq -8(%rsp), %rsi
leaq (%rsi,%rdi), %r9
movq %r11, %r13
subq %rdi, %r13
movl $1, %r10d
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z13array_processPdS_ii, .-_Z13array_processPdS_ii
.globl _Z38__device_stub__Z15gpu_calculationPdS_iPdS_i
.type _Z38__device_stub__Z15gpu_calculationPdS_iPdS_i, @function
_Z38__device_stub__Z15gpu_calculationPdS_iPdS_i:
.LFB3975:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15gpu_calculationPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z38__device_stub__Z15gpu_calculationPdS_iPdS_i, .-_Z38__device_stub__Z15gpu_calculationPdS_iPdS_i
.globl _Z15gpu_calculationPdS_i
.type _Z15gpu_calculationPdS_i, @function
_Z15gpu_calculationPdS_i:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15gpu_calculationPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z15gpu_calculationPdS_i, .-_Z15gpu_calculationPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Host to Device MemCpy takes "
.LC4:
.string "s"
.LC5:
.string "Computation takes "
.LC6:
.string "Device to Host MemCpy takes "
.text
.globl _Z17GPU_array_processPdS_ii
.type _Z17GPU_array_processPdS_ii, @function
_Z17GPU_array_processPdS_ii:
.LFB3950:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r14
movq %rsi, %r13
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %r12d, %ebx
imull %r12d, %ebx
movslq %ebx, %rbx
salq $3, %rbx
movl $0, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L60
cmpb $0, 56(%r15)
je .L23
movzbl 67(%r15), %esi
.L24:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L61
cmpb $0, 56(%r15)
je .L27
movzbl 67(%r15), %esi
.L28:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L62
cmpb $0, 56(%r15)
je .L31
movzbl 67(%r15), %esi
.L32:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L63
cmpb $0, 56(%r14)
je .L35
movzbl 67(%r14), %esi
.L36:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L64
cmpb $0, 56(%r14)
je .L39
movzbl 67(%r14), %esi
.L40:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2048, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $2048, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L41:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L66
cmpb $0, 56(%rbp)
je .L44
movzbl 67(%rbp), %esi
.L45:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq 76(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 76(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L67
cmpb $0, 56(%rbp)
je .L48
movzbl 67(%rbp), %esi
.L49:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 76(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $18, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 76(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L68
cmpb $0, 56(%rbp)
je .L52
movzbl 67(%rbp), %esi
.L53:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 76(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 76(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L69
cmpb $0, 56(%rbp)
je .L56
movzbl 67(%rbp), %esi
.L57:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L70
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L71
call _ZSt16__throw_bad_castv@PLT
.L71:
call __stack_chk_fail@PLT
.L23:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L61:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L72
call _ZSt16__throw_bad_castv@PLT
.L72:
call __stack_chk_fail@PLT
.L27:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L28
.L62:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L73
call _ZSt16__throw_bad_castv@PLT
.L73:
call __stack_chk_fail@PLT
.L31:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L63:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L74
call _ZSt16__throw_bad_castv@PLT
.L74:
call __stack_chk_fail@PLT
.L35:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L64:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L75
call _ZSt16__throw_bad_castv@PLT
.L75:
call __stack_chk_fail@PLT
.L39:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L40
.L65:
movl %r12d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z38__device_stub__Z15gpu_calculationPdS_iPdS_i
jmp .L41
.L66:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L76
call _ZSt16__throw_bad_castv@PLT
.L76:
call __stack_chk_fail@PLT
.L44:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L45
.L67:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L77
call _ZSt16__throw_bad_castv@PLT
.L77:
call __stack_chk_fail@PLT
.L48:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L49
.L68:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L78
call _ZSt16__throw_bad_castv@PLT
.L78:
call __stack_chk_fail@PLT
.L52:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L53
.L69:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L79
call _ZSt16__throw_bad_castv@PLT
.L79:
call __stack_chk_fail@PLT
.L56:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L57
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size _Z17GPU_array_processPdS_ii, .-_Z17GPU_array_processPdS_ii
.section .rodata.str1.1
.LC7:
.string "_Z15gpu_calculationPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15gpu_calculationPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1075970048
.align 8
.LC1:
.long 0
.long 1083129856
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
============================================================================
Filename : algorithm.c
Author : Your name goes here
SCIPER : Your SCIPER number
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <cuda_runtime.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void gpu_calculation(double* input, double* output, int length)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int index = y * length + x;
if(x > 1 && x < length - 1 && y > 1 && y < length - 1) {
output[index] = 0;/*(input[(x-1)*(length)+(y-1)] +
input[(x-1)*(length)+(y)] +
input[(x-1)*(length)+(y+1)] +
input[(x)*(length)+(y-1)] +
input[(x)*(length)+(y)] +
input[(x)*(length)+(y+1)] +
input[(x+1)*(length)+(y-1)] +
input[(x+1)*(length)+(y)] +
input[(x+1)*(length)+(y+1)]) / 9;*/
}
/*if(x == length / 2 - 1 && y == length / 2 - 1) {
return;
}
if(x == length / 2 && y == length / 2 - 1) {
return;
}
if(x == length / 2 - 1 && y == length / 2) {
return;
}
if(x == length / 2 && y == length / 2) {
return;
}*/
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
cudaEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
cudaEventCreate(&cpy_H2D_start);
cudaEventCreate(&cpy_H2D_end);
cudaEventCreate(&cpy_D2H_start);
cudaEventCreate(&cpy_D2H_end);
cudaEventCreate(&comp_start);
cudaEventCreate(&comp_end);
/* Preprocessing goes here */
size_t size = length*length*sizeof(double);
double* gpu_input;
double* gpu_output;
cout<<cudaSuccess<<endl;
cudaEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
cout<<cudaMalloc( (void**)&gpu_input, size)<<endl;
cout<<cudaMalloc( (void**)&gpu_output, size)<<endl;
cout<<cudaMemcpy((void*)gpu_input, (void*)input, size, cudaMemcpyHostToDevice)<<endl;
cout<<cudaMemcpy((void*)gpu_output, (void*)output, size, cudaMemcpyHostToDevice)<<endl;
cudaDeviceSynchronize();
cudaEventRecord(cpy_H2D_end);
cudaEventSynchronize(cpy_H2D_end);
//Copy array from host to device
cudaEventRecord(comp_start);
/* GPU calculation goes here */
int thrsPerBlock(64);
int nBlks(length/64 + 1);
/*for(int i = 0; i < iterations-1; i++){
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
cudaDeviceSynchronize();
cout<<cudaGetLastError()<<endl;
double * temp = gpu_output;
gpu_output = gpu_input;
gpu_input = temp;
}*/
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
cudaDeviceSynchronize();
cudaEventRecord(comp_end);
cudaEventSynchronize(comp_end);
cudaEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cout<<cudaMemcpy((void*)output, (void*)gpu_output, size, cudaMemcpyDeviceToHost)<<endl;
cudaDeviceSynchronize();
cudaEventRecord(cpy_D2H_end);
cudaEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
cudaFree(gpu_input);
cudaFree(gpu_output);
float time;
cudaEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
}
|
/*
============================================================================
Filename : algorithm.c
Author : Your name goes here
SCIPER : Your SCIPER number
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <hip/hip_runtime.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void gpu_calculation(double* input, double* output, int length)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int index = y * length + x;
if(x > 1 && x < length - 1 && y > 1 && y < length - 1) {
output[index] = 0;/*(input[(x-1)*(length)+(y-1)] +
input[(x-1)*(length)+(y)] +
input[(x-1)*(length)+(y+1)] +
input[(x)*(length)+(y-1)] +
input[(x)*(length)+(y)] +
input[(x)*(length)+(y+1)] +
input[(x+1)*(length)+(y-1)] +
input[(x+1)*(length)+(y)] +
input[(x+1)*(length)+(y+1)]) / 9;*/
}
/*if(x == length / 2 - 1 && y == length / 2 - 1) {
return;
}
if(x == length / 2 && y == length / 2 - 1) {
return;
}
if(x == length / 2 - 1 && y == length / 2) {
return;
}
if(x == length / 2 && y == length / 2) {
return;
}*/
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
hipEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
hipEventCreate(&cpy_H2D_start);
hipEventCreate(&cpy_H2D_end);
hipEventCreate(&cpy_D2H_start);
hipEventCreate(&cpy_D2H_end);
hipEventCreate(&comp_start);
hipEventCreate(&comp_end);
/* Preprocessing goes here */
size_t size = length*length*sizeof(double);
double* gpu_input;
double* gpu_output;
cout<<hipSuccess<<endl;
hipEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
cout<<hipMalloc( (void**)&gpu_input, size)<<endl;
cout<<hipMalloc( (void**)&gpu_output, size)<<endl;
cout<<hipMemcpy((void*)gpu_input, (void*)input, size, hipMemcpyHostToDevice)<<endl;
cout<<hipMemcpy((void*)gpu_output, (void*)output, size, hipMemcpyHostToDevice)<<endl;
hipDeviceSynchronize();
hipEventRecord(cpy_H2D_end);
hipEventSynchronize(cpy_H2D_end);
//Copy array from host to device
hipEventRecord(comp_start);
/* GPU calculation goes here */
int thrsPerBlock(64);
int nBlks(length/64 + 1);
/*for(int i = 0; i < iterations-1; i++){
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
cudaDeviceSynchronize();
cout<<cudaGetLastError()<<endl;
double * temp = gpu_output;
gpu_output = gpu_input;
gpu_input = temp;
}*/
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
hipDeviceSynchronize();
hipEventRecord(comp_end);
hipEventSynchronize(comp_end);
hipEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cout<<hipMemcpy((void*)output, (void*)gpu_output, size, hipMemcpyDeviceToHost)<<endl;
hipDeviceSynchronize();
hipEventRecord(cpy_D2H_end);
hipEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
hipFree(gpu_input);
hipFree(gpu_output);
float time;
hipEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
/*
============================================================================
Filename : algorithm.c
Author : Your name goes here
SCIPER : Your SCIPER number
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <hip/hip_runtime.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void gpu_calculation(double* input, double* output, int length)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int index = y * length + x;
if(x > 1 && x < length - 1 && y > 1 && y < length - 1) {
output[index] = 0;/*(input[(x-1)*(length)+(y-1)] +
input[(x-1)*(length)+(y)] +
input[(x-1)*(length)+(y+1)] +
input[(x)*(length)+(y-1)] +
input[(x)*(length)+(y)] +
input[(x)*(length)+(y+1)] +
input[(x+1)*(length)+(y-1)] +
input[(x+1)*(length)+(y)] +
input[(x+1)*(length)+(y+1)]) / 9;*/
}
/*if(x == length / 2 - 1 && y == length / 2 - 1) {
return;
}
if(x == length / 2 && y == length / 2 - 1) {
return;
}
if(x == length / 2 - 1 && y == length / 2) {
return;
}
if(x == length / 2 && y == length / 2) {
return;
}*/
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
hipEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
hipEventCreate(&cpy_H2D_start);
hipEventCreate(&cpy_H2D_end);
hipEventCreate(&cpy_D2H_start);
hipEventCreate(&cpy_D2H_end);
hipEventCreate(&comp_start);
hipEventCreate(&comp_end);
/* Preprocessing goes here */
size_t size = length*length*sizeof(double);
double* gpu_input;
double* gpu_output;
cout<<hipSuccess<<endl;
hipEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
cout<<hipMalloc( (void**)&gpu_input, size)<<endl;
cout<<hipMalloc( (void**)&gpu_output, size)<<endl;
cout<<hipMemcpy((void*)gpu_input, (void*)input, size, hipMemcpyHostToDevice)<<endl;
cout<<hipMemcpy((void*)gpu_output, (void*)output, size, hipMemcpyHostToDevice)<<endl;
hipDeviceSynchronize();
hipEventRecord(cpy_H2D_end);
hipEventSynchronize(cpy_H2D_end);
//Copy array from host to device
hipEventRecord(comp_start);
/* GPU calculation goes here */
int thrsPerBlock(64);
int nBlks(length/64 + 1);
/*for(int i = 0; i < iterations-1; i++){
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
cudaDeviceSynchronize();
cout<<cudaGetLastError()<<endl;
double * temp = gpu_output;
gpu_output = gpu_input;
gpu_input = temp;
}*/
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
hipDeviceSynchronize();
hipEventRecord(comp_end);
hipEventSynchronize(comp_end);
hipEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cout<<hipMemcpy((void*)output, (void*)gpu_output, size, hipMemcpyDeviceToHost)<<endl;
hipDeviceSynchronize();
hipEventRecord(cpy_D2H_end);
hipEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
hipFree(gpu_input);
hipFree(gpu_output);
float time;
hipEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15gpu_calculationPdS_i
.globl _Z15gpu_calculationPdS_i
.p2align 8
.type _Z15gpu_calculationPdS_i,@function
_Z15gpu_calculationPdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_add_i32 s2, s3, -1
v_max_u32_e32 v2, v0, v1
v_min_u32_e32 v3, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
v_cmp_lt_u32_e64 s2, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15gpu_calculationPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15gpu_calculationPdS_i, .Lfunc_end0-_Z15gpu_calculationPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15gpu_calculationPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15gpu_calculationPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
/*
============================================================================
Filename : algorithm.c
Author : Your name goes here
SCIPER : Your SCIPER number
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <hip/hip_runtime.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__
void gpu_calculation(double* input, double* output, int length)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
unsigned int index = y * length + x;
if(x > 1 && x < length - 1 && y > 1 && y < length - 1) {
output[index] = 0;/*(input[(x-1)*(length)+(y-1)] +
input[(x-1)*(length)+(y)] +
input[(x-1)*(length)+(y+1)] +
input[(x)*(length)+(y-1)] +
input[(x)*(length)+(y)] +
input[(x)*(length)+(y+1)] +
input[(x+1)*(length)+(y-1)] +
input[(x+1)*(length)+(y)] +
input[(x+1)*(length)+(y+1)]) / 9;*/
}
/*if(x == length / 2 - 1 && y == length / 2 - 1) {
return;
}
if(x == length / 2 && y == length / 2 - 1) {
return;
}
if(x == length / 2 - 1 && y == length / 2) {
return;
}
if(x == length / 2 && y == length / 2) {
return;
}*/
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
hipEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
hipEventCreate(&cpy_H2D_start);
hipEventCreate(&cpy_H2D_end);
hipEventCreate(&cpy_D2H_start);
hipEventCreate(&cpy_D2H_end);
hipEventCreate(&comp_start);
hipEventCreate(&comp_end);
/* Preprocessing goes here */
size_t size = length*length*sizeof(double);
double* gpu_input;
double* gpu_output;
cout<<hipSuccess<<endl;
hipEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
cout<<hipMalloc( (void**)&gpu_input, size)<<endl;
cout<<hipMalloc( (void**)&gpu_output, size)<<endl;
cout<<hipMemcpy((void*)gpu_input, (void*)input, size, hipMemcpyHostToDevice)<<endl;
cout<<hipMemcpy((void*)gpu_output, (void*)output, size, hipMemcpyHostToDevice)<<endl;
hipDeviceSynchronize();
hipEventRecord(cpy_H2D_end);
hipEventSynchronize(cpy_H2D_end);
//Copy array from host to device
hipEventRecord(comp_start);
/* GPU calculation goes here */
int thrsPerBlock(64);
int nBlks(length/64 + 1);
/*for(int i = 0; i < iterations-1; i++){
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
cudaDeviceSynchronize();
cout<<cudaGetLastError()<<endl;
double * temp = gpu_output;
gpu_output = gpu_input;
gpu_input = temp;
}*/
gpu_calculation <<< 2048, 2048 >>>(gpu_input, gpu_output, length);
hipDeviceSynchronize();
hipEventRecord(comp_end);
hipEventSynchronize(comp_end);
hipEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cout<<hipMemcpy((void*)output, (void*)gpu_output, size, hipMemcpyDeviceToHost)<<endl;
hipDeviceSynchronize();
hipEventRecord(cpy_D2H_end);
hipEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
hipFree(gpu_input);
hipFree(gpu_output);
float time;
hipEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
}
|
.text
.file "implementation.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13array_processPdS_ii
.LCPI0_0:
.quad 0x4022000000000000 # double 9
.text
.globl _Z13array_processPdS_ii
.p2align 4, 0x90
.type _Z13array_processPdS_ii,@function
_Z13array_processPdS_ii: # @_Z13array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rdx, -48(%rsp) # 8-byte Spill
movl %ecx, -52(%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB0_8
# %bb.1: # %.preheader72.lr.ph
movq -48(%rsp), %r10 # 8-byte Reload
leal -1(%r10), %eax
movl %r10d, %ecx
shrl $31, %ecx
addl %r10d, %ecx
sarl %ecx
leal -1(%rcx), %edx
imull %r10d, %edx
leal (%rdx,%rcx), %r8d
decl %r8d
movslq %r8d, %r8
movq %r8, -8(%rsp) # 8-byte Spill
movl %ecx, %r8d
imull %r10d, %r8d
leal (%r8,%rcx), %r9d
decl %r9d
movslq %r9d, %r9
movq %r9, -16(%rsp) # 8-byte Spill
addl %ecx, %edx
movslq %edx, %rdx
addl %ecx, %r8d
movslq %r8d, %r11
movslq %r10d, %rcx
leaq (,%rcx,8), %rbx
leaq 8(,%rcx,8), %r8
movq %r8, -24(%rsp) # 8-byte Spill
leaq 16(,%rcx,8), %r8
movq %r8, -32(%rsp) # 8-byte Spill
shlq $4, %rcx
addq $16, %rcx
movq %rcx, -40(%rsp) # 8-byte Spill
leaq -8(,%rax,8), %r13
xorl %ebp, %ebp
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movabsq $4652007308841189376, %r14 # imm = 0x408F400000000000
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_7: # %._crit_edge75
# in Loop: Header=BB0_2 Depth=1
movq -8(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq -16(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq %r14, (%rsi,%rdx,8)
movq %r14, (%rsi,%r11,8)
incl %ebp
movq %rsi, %rdi
movq %r15, %rsi
cmpl -52(%rsp), %ebp # 4-byte Folded Reload
je .LBB0_8
.LBB0_2: # %.preheader72
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_5 Depth 3
movq %rdi, %r15
cmpl $3, -48(%rsp) # 4-byte Folded Reload
jl .LBB0_7
# %bb.3: # %.preheader.preheader
# in Loop: Header=BB0_2 Depth=1
movq -40(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %rdi
movq -24(%rsp), %rcx # 8-byte Reload
leaq (%rsi,%rcx), %r12
movq -32(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %r8
leaq 16(%r15), %rcx
movl $1, %r9d
.p2align 4, 0x90
.LBB0_4: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_5 Depth 3
incq %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_5: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Inner Loop Header: Depth=3
movsd -16(%rcx,%r10), %xmm1 # xmm1 = mem[0],zero
addsd -8(%rcx,%r10), %xmm1
addsd (%rcx,%r10), %xmm1
addsd -16(%r8,%r10), %xmm1
addsd -8(%r8,%r10), %xmm1
addsd (%r8,%r10), %xmm1
addsd -16(%rdi,%r10), %xmm1
addsd -8(%rdi,%r10), %xmm1
addsd (%rdi,%r10), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, (%r12,%r10)
addq $8, %r10
cmpq %r10, %r13
jne .LBB0_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB0_4 Depth=2
addq %rbx, %rdi
addq %rbx, %r12
addq %rbx, %r8
addq %rbx, %rcx
cmpq %rax, %r9
jne .LBB0_4
jmp .LBB0_7
.LBB0_8: # %._crit_edge79
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13array_processPdS_ii, .Lfunc_end0-_Z13array_processPdS_ii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gpu_calculationPdS_i # -- Begin function _Z30__device_stub__gpu_calculationPdS_i
.p2align 4, 0x90
.type _Z30__device_stub__gpu_calculationPdS_i,@function
_Z30__device_stub__gpu_calculationPdS_i: # @_Z30__device_stub__gpu_calculationPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gpu_calculationPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z30__device_stub__gpu_calculationPdS_i, .Lfunc_end1-_Z30__device_stub__gpu_calculationPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17GPU_array_processPdS_ii
.LCPI2_0:
.long 0x447a0000 # float 1000
.text
.globl _Z17GPU_array_processPdS_ii
.p2align 4, 0x90
.type _Z17GPU_array_processPdS_ii,@function
_Z17GPU_array_processPdS_ii: # @_Z17GPU_array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r15
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 80(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $_ZSt4cout, %edi
xorl %esi, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_39
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
movl %ebp, %r14d
imull %r14d, %r14d
shlq $3, %r14
cmpb $0, 56(%r12)
je .LBB2_3
# %bb.2:
movzbl 67(%r12), %ecx
jmp .LBB2_4
.LBB2_3:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_39
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%r12)
je .LBB2_7
# %bb.6:
movzbl 67(%r12), %ecx
jmp .LBB2_8
.LBB2_7:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_39
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%r12)
je .LBB2_11
# %bb.10:
movzbl 67(%r12), %ecx
jmp .LBB2_12
.LBB2_11:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_39
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%r15)
je .LBB2_15
# %bb.14:
movzbl 67(%r15), %ecx
jmp .LBB2_16
.LBB2_15:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_39
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%r15)
je .LBB2_19
# %bb.18:
movzbl 67(%r15), %ecx
jmp .LBB2_20
.LBB2_19:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294969344, %rdi # imm = 0x100000800
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_22
# %bb.21:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movl %ebp, 44(%rsp)
leaq 160(%rsp), %rax
movq %rax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15gpu_calculationPdS_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_22:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_39
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%rbx)
je .LBB2_25
# %bb.24:
movzbl 67(%rbx), %ecx
jmp .LBB2_26
.LBB2_25:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 96(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_39
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%r14)
je .LBB2_29
# %bb.28:
movzbl 67(%r14), %eax
jmp .LBB2_30
.LBB2_29:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 88(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_39
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
cmpb $0, 56(%r14)
je .LBB2_33
# %bb.32:
movzbl 67(%r14), %eax
jmp .LBB2_34
.LBB2_33:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 80(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_39
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i52
cmpb $0, 56(%r14)
je .LBB2_37
# %bb.36:
movzbl 67(%r14), %eax
jmp .LBB2_38
.LBB2_37:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit55
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_39:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z17GPU_array_processPdS_ii, .Lfunc_end2-_Z17GPU_array_processPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gpu_calculationPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15gpu_calculationPdS_i,@object # @_Z15gpu_calculationPdS_i
.section .rodata,"a",@progbits
.globl _Z15gpu_calculationPdS_i
.p2align 3, 0x0
_Z15gpu_calculationPdS_i:
.quad _Z30__device_stub__gpu_calculationPdS_i
.size _Z15gpu_calculationPdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Host to Device MemCpy takes "
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "s"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Computation takes "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device to Host MemCpy takes "
.size .L.str.3, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15gpu_calculationPdS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__gpu_calculationPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15gpu_calculationPdS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z15gpu_calculationPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06070 */
/*0090*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc600078e0205 */
/*00a0*/ ISETP.LT.U32.OR P0, PT, R0, 0x2, P0 ; /* 0x000000020000780c */
/* 0x000fc80000701470 */
/*00b0*/ ISETP.LT.U32.OR P0, PT, R3, 0x2, P0 ; /* 0x000000020300780c */
/* 0x000fc80000701470 */
/*00c0*/ ISETP.GE.U32.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fda0008706470 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0200 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0110*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0002 */
/*0120*/ STG.E.64 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101b04 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15gpu_calculationPdS_i
.globl _Z15gpu_calculationPdS_i
.p2align 8
.type _Z15gpu_calculationPdS_i,@function
_Z15gpu_calculationPdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_add_i32 s2, s3, -1
v_max_u32_e32 v2, v0, v1
v_min_u32_e32 v3, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
v_cmp_lt_u32_e64 s2, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15gpu_calculationPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15gpu_calculationPdS_i, .Lfunc_end0-_Z15gpu_calculationPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15gpu_calculationPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15gpu_calculationPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0008219e_00000000-6_implementation.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13array_processPdS_ii
.type _Z13array_processPdS_ii, @function
_Z13array_processPdS_ii:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movl %ecx, -28(%rsp)
testl %ecx, %ecx
jle .L3
movq %rsi, %r8
movl %edx, %r10d
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
leal -1(%rax), %ecx
movl %ecx, %edx
imull %r10d, %edx
leal (%rcx,%rdx), %r13d
movslq %r13d, %r13
salq $3, %r13
leal (%rdx,%r10), %esi
addl %esi, %ecx
movslq %ecx, %rcx
leaq 0(,%rcx,8), %r14
addl %eax, %edx
movslq %edx, %rdx
leaq 0(,%rdx,8), %r15
addl %esi, %eax
cltq
salq $3, %rax
movq %rax, -40(%rsp)
movslq %r10d, %rbp
leaq 0(,%rbp,8), %r11
leal -3(%r10), %eax
salq $4, %rbp
movl $0, %edx
leaq 8(,%rax,8), %rax
movq %rax, -8(%rsp)
leal -1(%r10), %r12d
movsd .LC0(%rip), %xmm1
movsd .LC1(%rip), %xmm2
movq %r13, -24(%rsp)
movq %r14, -16(%rsp)
movl %r10d, %ebx
jmp .L5
.L8:
leaq (%rax,%rbp), %r14
leaq (%rax,%r13), %rcx
movq %r14, %rsi
.L6:
movsd (%rax), %xmm0
addsd 8(%rax), %xmm0
addsd 16(%rax), %xmm0
addsd (%rdi,%rcx), %xmm0
addsd 8(%rdi,%rcx), %xmm0
addsd 16(%rdi,%rcx), %xmm0
addsd (%rsi), %xmm0
addsd 8(%rsi), %xmm0
addsd 16(%rsi), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 8(%r8,%rcx)
addq $8, %rax
addq $8, %rsi
addq $8, %rcx
cmpq %r9, %rax
jne .L6
addl $1, %r10d
movq %r14, %rax
subq %r11, %rax
addq %r11, %r9
cmpl %r12d, %r10d
jne .L8
.L7:
movq -24(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movq -16(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movsd %xmm2, (%r8,%r15)
movq -40(%rsp), %rax
movsd %xmm2, (%r8,%rax)
addl $1, %edx
movq %r8, %rax
movq %rdi, %r8
cmpl %edx, -28(%rsp)
je .L3
movq %rax, %rdi
.L5:
cmpl $2, %ebx
jle .L7
movq %rdi, %rax
movq -8(%rsp), %rsi
leaq (%rsi,%rdi), %r9
movq %r11, %r13
subq %rdi, %r13
movl $1, %r10d
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z13array_processPdS_ii, .-_Z13array_processPdS_ii
.globl _Z38__device_stub__Z15gpu_calculationPdS_iPdS_i
.type _Z38__device_stub__Z15gpu_calculationPdS_iPdS_i, @function
_Z38__device_stub__Z15gpu_calculationPdS_iPdS_i:
.LFB3975:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15gpu_calculationPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z38__device_stub__Z15gpu_calculationPdS_iPdS_i, .-_Z38__device_stub__Z15gpu_calculationPdS_iPdS_i
.globl _Z15gpu_calculationPdS_i
.type _Z15gpu_calculationPdS_i, @function
_Z15gpu_calculationPdS_i:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15gpu_calculationPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z15gpu_calculationPdS_i, .-_Z15gpu_calculationPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Host to Device MemCpy takes "
.LC4:
.string "s"
.LC5:
.string "Computation takes "
.LC6:
.string "Device to Host MemCpy takes "
.text
.globl _Z17GPU_array_processPdS_ii
.type _Z17GPU_array_processPdS_ii, @function
_Z17GPU_array_processPdS_ii:
.LFB3950:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %r14
movq %rsi, %r13
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %r12d, %ebx
imull %r12d, %ebx
movslq %ebx, %rbx
salq $3, %rbx
movl $0, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L60
cmpb $0, 56(%r15)
je .L23
movzbl 67(%r15), %esi
.L24:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L61
cmpb $0, 56(%r15)
je .L27
movzbl 67(%r15), %esi
.L28:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L62
cmpb $0, 56(%r15)
je .L31
movzbl 67(%r15), %esi
.L32:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L63
cmpb $0, 56(%r14)
je .L35
movzbl 67(%r14), %esi
.L36:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L64
cmpb $0, 56(%r14)
je .L39
movzbl 67(%r14), %esi
.L40:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2048, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $2048, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L41:
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L66
cmpb $0, 56(%rbp)
je .L44
movzbl 67(%rbp), %esi
.L45:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call cudaDeviceSynchronize@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq 76(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 76(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L67
cmpb $0, 56(%rbp)
je .L48
movzbl 67(%rbp), %esi
.L49:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 76(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $18, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 76(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L68
cmpb $0, 56(%rbp)
je .L52
movzbl 67(%rbp), %esi
.L53:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 76(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 76(%rsp), %xmm0
divss .LC3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L69
cmpb $0, 56(%rbp)
je .L56
movzbl 67(%rbp), %esi
.L57:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L70
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L71
call _ZSt16__throw_bad_castv@PLT
.L71:
call __stack_chk_fail@PLT
.L23:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L61:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L72
call _ZSt16__throw_bad_castv@PLT
.L72:
call __stack_chk_fail@PLT
.L27:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L28
.L62:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L73
call _ZSt16__throw_bad_castv@PLT
.L73:
call __stack_chk_fail@PLT
.L31:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L63:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L74
call _ZSt16__throw_bad_castv@PLT
.L74:
call __stack_chk_fail@PLT
.L35:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L64:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L75
call _ZSt16__throw_bad_castv@PLT
.L75:
call __stack_chk_fail@PLT
.L39:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L40
.L65:
movl %r12d, %edx
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z38__device_stub__Z15gpu_calculationPdS_iPdS_i
jmp .L41
.L66:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L76
call _ZSt16__throw_bad_castv@PLT
.L76:
call __stack_chk_fail@PLT
.L44:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L45
.L67:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L77
call _ZSt16__throw_bad_castv@PLT
.L77:
call __stack_chk_fail@PLT
.L48:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L49
.L68:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L78
call _ZSt16__throw_bad_castv@PLT
.L78:
call __stack_chk_fail@PLT
.L52:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L53
.L69:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L79
call _ZSt16__throw_bad_castv@PLT
.L79:
call __stack_chk_fail@PLT
.L56:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L57
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size _Z17GPU_array_processPdS_ii, .-_Z17GPU_array_processPdS_ii
.section .rodata.str1.1
.LC7:
.string "_Z15gpu_calculationPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z15gpu_calculationPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1075970048
.align 8
.LC1:
.long 0
.long 1083129856
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "implementation.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13array_processPdS_ii
.LCPI0_0:
.quad 0x4022000000000000 # double 9
.text
.globl _Z13array_processPdS_ii
.p2align 4, 0x90
.type _Z13array_processPdS_ii,@function
_Z13array_processPdS_ii: # @_Z13array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rdx, -48(%rsp) # 8-byte Spill
movl %ecx, -52(%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB0_8
# %bb.1: # %.preheader72.lr.ph
movq -48(%rsp), %r10 # 8-byte Reload
leal -1(%r10), %eax
movl %r10d, %ecx
shrl $31, %ecx
addl %r10d, %ecx
sarl %ecx
leal -1(%rcx), %edx
imull %r10d, %edx
leal (%rdx,%rcx), %r8d
decl %r8d
movslq %r8d, %r8
movq %r8, -8(%rsp) # 8-byte Spill
movl %ecx, %r8d
imull %r10d, %r8d
leal (%r8,%rcx), %r9d
decl %r9d
movslq %r9d, %r9
movq %r9, -16(%rsp) # 8-byte Spill
addl %ecx, %edx
movslq %edx, %rdx
addl %ecx, %r8d
movslq %r8d, %r11
movslq %r10d, %rcx
leaq (,%rcx,8), %rbx
leaq 8(,%rcx,8), %r8
movq %r8, -24(%rsp) # 8-byte Spill
leaq 16(,%rcx,8), %r8
movq %r8, -32(%rsp) # 8-byte Spill
shlq $4, %rcx
addq $16, %rcx
movq %rcx, -40(%rsp) # 8-byte Spill
leaq -8(,%rax,8), %r13
xorl %ebp, %ebp
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movabsq $4652007308841189376, %r14 # imm = 0x408F400000000000
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_7: # %._crit_edge75
# in Loop: Header=BB0_2 Depth=1
movq -8(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq -16(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq %r14, (%rsi,%rdx,8)
movq %r14, (%rsi,%r11,8)
incl %ebp
movq %rsi, %rdi
movq %r15, %rsi
cmpl -52(%rsp), %ebp # 4-byte Folded Reload
je .LBB0_8
.LBB0_2: # %.preheader72
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_5 Depth 3
movq %rdi, %r15
cmpl $3, -48(%rsp) # 4-byte Folded Reload
jl .LBB0_7
# %bb.3: # %.preheader.preheader
# in Loop: Header=BB0_2 Depth=1
movq -40(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %rdi
movq -24(%rsp), %rcx # 8-byte Reload
leaq (%rsi,%rcx), %r12
movq -32(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %r8
leaq 16(%r15), %rcx
movl $1, %r9d
.p2align 4, 0x90
.LBB0_4: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_5 Depth 3
incq %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_5: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Inner Loop Header: Depth=3
movsd -16(%rcx,%r10), %xmm1 # xmm1 = mem[0],zero
addsd -8(%rcx,%r10), %xmm1
addsd (%rcx,%r10), %xmm1
addsd -16(%r8,%r10), %xmm1
addsd -8(%r8,%r10), %xmm1
addsd (%r8,%r10), %xmm1
addsd -16(%rdi,%r10), %xmm1
addsd -8(%rdi,%r10), %xmm1
addsd (%rdi,%r10), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, (%r12,%r10)
addq $8, %r10
cmpq %r10, %r13
jne .LBB0_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB0_4 Depth=2
addq %rbx, %rdi
addq %rbx, %r12
addq %rbx, %r8
addq %rbx, %rcx
cmpq %rax, %r9
jne .LBB0_4
jmp .LBB0_7
.LBB0_8: # %._crit_edge79
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13array_processPdS_ii, .Lfunc_end0-_Z13array_processPdS_ii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gpu_calculationPdS_i # -- Begin function _Z30__device_stub__gpu_calculationPdS_i
.p2align 4, 0x90
.type _Z30__device_stub__gpu_calculationPdS_i,@function
_Z30__device_stub__gpu_calculationPdS_i: # @_Z30__device_stub__gpu_calculationPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gpu_calculationPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z30__device_stub__gpu_calculationPdS_i, .Lfunc_end1-_Z30__device_stub__gpu_calculationPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17GPU_array_processPdS_ii
.LCPI2_0:
.long 0x447a0000 # float 1000
.text
.globl _Z17GPU_array_processPdS_ii
.p2align 4, 0x90
.type _Z17GPU_array_processPdS_ii,@function
_Z17GPU_array_processPdS_ii: # @_Z17GPU_array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r15
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 80(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $_ZSt4cout, %edi
xorl %esi, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_39
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
movl %ebp, %r14d
imull %r14d, %r14d
shlq $3, %r14
cmpb $0, 56(%r12)
je .LBB2_3
# %bb.2:
movzbl 67(%r12), %ecx
jmp .LBB2_4
.LBB2_3:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_39
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%r12)
je .LBB2_7
# %bb.6:
movzbl 67(%r12), %ecx
jmp .LBB2_8
.LBB2_7:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_39
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%r12)
je .LBB2_11
# %bb.10:
movzbl 67(%r12), %ecx
jmp .LBB2_12
.LBB2_11:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_39
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%r15)
je .LBB2_15
# %bb.14:
movzbl 67(%r15), %ecx
jmp .LBB2_16
.LBB2_15:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_39
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%r15)
je .LBB2_19
# %bb.18:
movzbl 67(%r15), %ecx
jmp .LBB2_20
.LBB2_19:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294969344, %rdi # imm = 0x100000800
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_22
# %bb.21:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movl %ebp, 44(%rsp)
leaq 160(%rsp), %rax
movq %rax, 48(%rsp)
leaq 152(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z15gpu_calculationPdS_i, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_22:
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 80(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_39
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%rbx)
je .LBB2_25
# %bb.24:
movzbl 67(%rbx), %ecx
jmp .LBB2_26
.LBB2_25:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq 96(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_39
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%r14)
je .LBB2_29
# %bb.28:
movzbl 67(%r14), %eax
jmp .LBB2_30
.LBB2_29:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 88(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_39
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
cmpb $0, 56(%r14)
je .LBB2_33
# %bb.32:
movzbl 67(%r14), %eax
jmp .LBB2_34
.LBB2_33:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 80(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_39
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i52
cmpb $0, 56(%r14)
je .LBB2_37
# %bb.36:
movzbl 67(%r14), %eax
jmp .LBB2_38
.LBB2_37:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit55
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_39:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z17GPU_array_processPdS_ii, .Lfunc_end2-_Z17GPU_array_processPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gpu_calculationPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15gpu_calculationPdS_i,@object # @_Z15gpu_calculationPdS_i
.section .rodata,"a",@progbits
.globl _Z15gpu_calculationPdS_i
.p2align 3, 0x0
_Z15gpu_calculationPdS_i:
.quad _Z30__device_stub__gpu_calculationPdS_i
.size _Z15gpu_calculationPdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Host to Device MemCpy takes "
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "s"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Computation takes "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device to Host MemCpy takes "
.size .L.str.3, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15gpu_calculationPdS_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__gpu_calculationPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15gpu_calculationPdS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void matrixMult(int* m,int* n, int* p, int size)
{
// matrixMult<<< grid_size,block_size >>>(d_m,d_n,d_p,n);
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int p_sum;
for(int i=0;i<size;i++){
p_sum += m[row*size+i] * n[col*size+i];
}
p[row*size+col]=p_sum;
}
|
code for sm_80
Function : _Z10matrixMultPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ MOV R6, c[0x0][0x178] ; /* 0x00005e0000067a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0050*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f06270 */
/*0060*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R7, R7, c[0x0][0x4], R0 ; /* 0x0000010007077a24 */
/* 0x001fc800078e0200 */
/*0090*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x000fe400078e02ff */
/*00a0*/ IMAD R0, R2, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x002fe200078e0203 */
/*00b0*/ @!P0 BRA 0xab0 ; /* 0x000009f000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*00e0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0x960 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R6, c[0x0][0x178], RZ ; /* 0x00005e0006087a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0130*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IMAD R9, R0, c[0x0][0x178], RZ ; /* 0x00005e0000097a24 */
/* 0x000fe200078e02ff */
/*0150*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fe200078e0202 */
/*0170*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd60000000f00 */
/*0180*/ @!P0 BRA 0x7e0 ; /* 0x0000065000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01b0*/ @!P1 BRA 0x580 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01d0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*01e0*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*01f0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea6000c1e1900 */
/*0200*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe200078e0204 */
/*0210*/ LDG.E R25, [R2.64+0x4] ; /* 0x0000040402197981 */
/* 0x000ee8000c1e1900 */
/*0220*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R22, [R4.64+0xc] ; /* 0x00000c0404167981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100402177981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R24, [R4.64+0x10] ; /* 0x0000100404187981 */
/* 0x000f68000c1e1900 */
/*02a0*/ LDG.E R19, [R2.64+0x14] ; /* 0x0000140402137981 */
/* 0x000f68000c1e1900 */
/*02b0*/ LDG.E R20, [R4.64+0x14] ; /* 0x0000140404147981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001804020b7981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R26, [R4.64+0x3c] ; /* 0x00003c04041a7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IMAD R15, R14, R15, R13 ; /* 0x0000000f0e0f7224 */
/* 0x004fc600078e020d */
/*0300*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c04020d7981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IMAD R25, R16, R25, R15 ; /* 0x0000001910197224 */
/* 0x008fc600078e020f */
/*0330*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002004020f7981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000ee2000c1e1900 */
/*0350*/ IMAD R25, R18, R17, R25 ; /* 0x0000001112197224 */
/* 0x010fc600078e0219 */
/*0360*/ LDG.E R17, [R2.64+0x24] ; /* 0x0000240402117981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R18, [R4.64+0x24] ; /* 0x0000240404127981 */
/* 0x000f22000c1e1900 */
/*0380*/ IMAD R25, R22, R21, R25 ; /* 0x0000001516197224 */
/* 0x020fc600078e0219 */
/*0390*/ LDG.E R22, [R2.64+0x28] ; /* 0x0000280402167981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R21, [R4.64+0x28] ; /* 0x0000280404157981 */
/* 0x000f62000c1e1900 */
/*03b0*/ IMAD R25, R24, R23, R25 ; /* 0x0000001718197224 */
/* 0x000fc600078e0219 */
/*03c0*/ LDG.E R24, [R2.64+0x2c] ; /* 0x00002c0402187981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R23, [R4.64+0x2c] ; /* 0x00002c0404177981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IMAD R25, R20, R19, R25 ; /* 0x0000001314197224 */
/* 0x000fc600078e0219 */
/*03f0*/ LDG.E R20, [R2.64+0x30] ; /* 0x0000300402147981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R19, [R4.64+0x30] ; /* 0x0000300404137981 */
/* 0x000f62000c1e1900 */
/*0410*/ IMAD R25, R12, R11, R25 ; /* 0x0000000b0c197224 */
/* 0x000fc600078e0219 */
/*0420*/ LDG.E R12, [R2.64+0x34] ; /* 0x00003404020c7981 */
/* 0x000168000c1e1900 */
/*0430*/ LDG.E R11, [R4.64+0x34] ; /* 0x00003404040b7981 */
/* 0x000f62000c1e1900 */
/*0440*/ IMAD R27, R14, R13, R25 ; /* 0x0000000d0e1b7224 */
/* 0x004fc600078e0219 */
/*0450*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x0000a8000c1e1900 */
/*0460*/ LDG.E R13, [R4.64+0x38] ; /* 0x00003804040d7981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R25, [R2.64+0x3c] ; /* 0x00003c0402197981 */
/* 0x0000a2000c1e1900 */
/*0480*/ IMAD R15, R16, R15, R27 ; /* 0x0000000f100f7224 */
/* 0x008fc800078e021b */
/*0490*/ IMAD R15, R18, R17, R15 ; /* 0x00000011120f7224 */
/* 0x010fe200078e020f */
/*04a0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*04b0*/ IMAD R15, R21, R22, R15 ; /* 0x00000016150f7224 */
/* 0x020fe200078e020f */
/*04c0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*04d0*/ IMAD R15, R23, R24, R15 ; /* 0x00000018170f7224 */
/* 0x000fe200078e020f */
/*04e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fc6000ff1e03f */
/*04f0*/ IMAD R15, R19, R20, R15 ; /* 0x00000014130f7224 */
/* 0x000fe200078e020f */
/*0500*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe20007f5e0ff */
/*0510*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0520*/ IMAD R11, R11, R12, R15 ; /* 0x0000000c0b0b7224 */
/* 0x000fe200078e020f */
/*0530*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*0540*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD R13, R13, R14, R11 ; /* 0x0000000e0d0d7224 */
/* 0x004fc800078e020b */
/*0560*/ IMAD R13, R26, R25, R13 ; /* 0x000000191a0d7224 */
/* 0x000fe200078e020d */
/*0570*/ @P1 BRA 0x1d0 ; /* 0xfffffc5000001947 */
/* 0x000fea000383ffff */
/*0580*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0590*/ @!P1 BRA 0x7c0 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*05a0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*05b0*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*05c0*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x0000a6000c1e1900 */
/*05d0*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe200078e0204 */
/*05e0*/ LDG.E R24, [R2.64+0x4] ; /* 0x0000040402187981 */
/* 0x0000e8000c1e1900 */
/*05f0*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R25, [R4.64+0x4] ; /* 0x0000040404197981 */
/* 0x000ee8000c1e1900 */
/*0610*/ LDG.E R26, [R2.64+0x8] ; /* 0x00000804021a7981 */
/* 0x000128000c1e1900 */
/*0620*/ LDG.E R27, [R4.64+0x8] ; /* 0x00000804041b7981 */
/* 0x000f28000c1e1900 */
/*0630*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000168000c1e1900 */
/*0640*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*0650*/ LDG.E R17, [R2.64+0x10] ; /* 0x0000100402117981 */
/* 0x000168000c1e1900 */
/*0660*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f68000c1e1900 */
/*0670*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x000168000c1e1900 */
/*0680*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000f68000c1e1900 */
/*0690*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000168000c1e1900 */
/*06a0*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000f68000c1e1900 */
/*06b0*/ LDG.E R21, [R4.64+0x1c] ; /* 0x00001c0404157981 */
/* 0x000f68000c1e1900 */
/*06c0*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000162000c1e1900 */
/*06d0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*06e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*06f0*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe40007ffe0ff */
/*0710*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x001fe20007f3e0ff */
/*0720*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fc600087fe43f */
/*0730*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*0740*/ IMAD R22, R22, R23, R13 ; /* 0x0000001716167224 */
/* 0x004fc800078e020d */
/*0750*/ IMAD R22, R25, R24, R22 ; /* 0x0000001819167224 */
/* 0x008fc800078e0216 */
/*0760*/ IMAD R22, R27, R26, R22 ; /* 0x0000001a1b167224 */
/* 0x010fc800078e0216 */
/*0770*/ IMAD R18, R18, R19, R22 ; /* 0x0000001312127224 */
/* 0x020fc800078e0216 */
/*0780*/ IMAD R16, R16, R17, R18 ; /* 0x0000001110107224 */
/* 0x000fc800078e0212 */
/*0790*/ IMAD R14, R14, R15, R16 ; /* 0x0000000f0e0e7224 */
/* 0x000fc800078e0210 */
/*07a0*/ IMAD R11, R11, R12, R14 ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e020e */
/*07b0*/ IMAD R13, R21, R20, R11 ; /* 0x00000014150d7224 */
/* 0x000fe400078e020b */
/*07c0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*07d0*/ @!P0 BRA 0x960 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*07e0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*07f0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0800*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fc60008000f00 */
/*0810*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ee4000c1e1900 */
/*0820*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe400078e0204 */
/*0830*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*0840*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000f28000c1e1900 */
/*0870*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*0880*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000162000c1e1900 */
/*0890*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*08a0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*08b0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*08c0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ IMAD R11, R12, R11, R13 ; /* 0x0000000b0c0b7224 */
/* 0x004fe200078e020d */
/*08f0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fc60007f3e0ff */
/*0900*/ IMAD R11, R14, R15, R11 ; /* 0x0000000f0e0b7224 */
/* 0x008fc800078e020b */
/*0910*/ IMAD R11, R16, R17, R11 ; /* 0x00000011100b7224 */
/* 0x010fe200078e020b */
/*0920*/ MOV R2, R12 ; /* 0x0000000c00027202 */
/* 0x001fe20000000f00 */
/*0930*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe400008e0603 */
/*0940*/ IMAD R13, R18, R19, R11 ; /* 0x00000013120d7224 */
/* 0x020fe200078e020b */
/*0950*/ @P0 BRA 0x7e0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0960*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0970*/ @!P0 BRA 0xab0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0980*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0990*/ IMAD R2, R0, c[0x0][0x178], R10 ; /* 0x00005e0000027a24 */
/* 0x000fe200078e020a */
/*09a0*/ IADD3 R4, R7, R10, RZ ; /* 0x0000000a07047210 */
/* 0x000fd00007ffe0ff */
/*09b0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*09c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*09d0*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*09e0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*09f0*/ MOV R2, R9 ; /* 0x0000000900027202 */
/* 0x000fe40000000f00 */
/*0a00*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fc80000000f00 */
/*0a10*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a8000c1e1900 */
/*0a20*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0a30*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007f3e0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0a60*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007f5e0ff */
/*0a70*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fc600008e0603 */
/*0a80*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x002fe200017fe4ff */
/*0a90*/ IMAD R13, R2, R4, R13 ; /* 0x00000004020d7224 */
/* 0x004fcc00078e020d */
/*0aa0*/ @P0 BRA 0x9f0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0ab0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0ac0*/ IADD3 R2, R0, R7, RZ ; /* 0x0000000700027210 */
/* 0x000fd20007ffe0ff */
/*0ad0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0ae0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void matrixMult(int* m,int* n, int* p, int size)
{
// matrixMult<<< grid_size,block_size >>>(d_m,d_n,d_p,n);
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int p_sum;
for(int i=0;i<size;i++){
p_sum += m[row*size+i] * n[col*size+i];
}
p[row*size+col]=p_sum;
}
|
.file "tmpxft_001368de_00000000-6_matrixMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.globl _Z10matrixMultPiS_S_i
.type _Z10matrixMultPiS_S_i, @function
_Z10matrixMultPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10matrixMultPiS_S_i, .-_Z10matrixMultPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10matrixMultPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void matrixMult(int* m,int* n, int* p, int size)
{
// matrixMult<<< grid_size,block_size >>>(d_m,d_n,d_p,n);
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int p_sum;
for(int i=0;i<size;i++){
p_sum += m[row*size+i] * n[col*size+i];
}
p[row*size+col]=p_sum;
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMult(int* m,int* n, int* p, int size)
{
// matrixMult<<< grid_size,block_size >>>(d_m,d_n,d_p,n);
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int p_sum;
for(int i=0;i<size;i++){
p_sum += m[row*size+i] * n[col*size+i];
}
p[row*size+col]=p_sum;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMult(int* m,int* n, int* p, int size)
{
// matrixMult<<< grid_size,block_size >>>(d_m,d_n,d_p,n);
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int p_sum;
for(int i=0;i<size;i++){
p_sum += m[row*size+i] * n[col*size+i];
}
p[row*size+col]=p_sum;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPiS_S_i
.globl _Z10matrixMultPiS_S_i
.p2align 8
.type _Z10matrixMultPiS_S_i,@function
_Z10matrixMultPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s2
v_mul_lo_u32 v4, v0, s2
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v9, vcc_lo
.p2align 6
.LBB0_2:
global_load_b32 v9, v[5:6], off
global_load_b32 v10, v[3:4], off
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v10, v9, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_mov_b32_e32 v2, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPiS_S_i, .Lfunc_end0-_Z10matrixMultPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixMult(int* m,int* n, int* p, int size)
{
// matrixMult<<< grid_size,block_size >>>(d_m,d_n,d_p,n);
int row=blockIdx.y*blockDim.y+threadIdx.y;
int col=blockIdx.x*blockDim.x+threadIdx.x;
int p_sum;
for(int i=0;i<size;i++){
p_sum += m[row*size+i] * n[col*size+i];
}
p[row*size+col]=p_sum;
}
|
.text
.file "matrixMult.hip"
.globl _Z25__device_stub__matrixMultPiS_S_i # -- Begin function _Z25__device_stub__matrixMultPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPiS_S_i,@function
_Z25__device_stub__matrixMultPiS_S_i: # @_Z25__device_stub__matrixMultPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixMultPiS_S_i, .Lfunc_end0-_Z25__device_stub__matrixMultPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPiS_S_i,@object # @_Z10matrixMultPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10matrixMultPiS_S_i
.p2align 3, 0x0
_Z10matrixMultPiS_S_i:
.quad _Z25__device_stub__matrixMultPiS_S_i
.size _Z10matrixMultPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10matrixMultPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z10matrixMultPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e220000002600 */
/*0020*/ MOV R6, c[0x0][0x178] ; /* 0x00005e0000067a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0050*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fc60003f06270 */
/*0060*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0070*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0080*/ IMAD R7, R7, c[0x0][0x4], R0 ; /* 0x0000010007077a24 */
/* 0x001fc800078e0200 */
/*0090*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x000fe400078e02ff */
/*00a0*/ IMAD R0, R2, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x002fe200078e0203 */
/*00b0*/ @!P0 BRA 0xab0 ; /* 0x000009f000008947 */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*00e0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0x960 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R8, -R6, c[0x0][0x178], RZ ; /* 0x00005e0006087a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0130*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IMAD R9, R0, c[0x0][0x178], RZ ; /* 0x00005e0000097a24 */
/* 0x000fe200078e02ff */
/*0150*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0160*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fe200078e0202 */
/*0170*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fd60000000f00 */
/*0180*/ @!P0 BRA 0x7e0 ; /* 0x0000065000008947 */
/* 0x000fea0003800000 */
/*0190*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01b0*/ @!P1 BRA 0x580 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01d0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*01e0*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*01f0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea6000c1e1900 */
/*0200*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe200078e0204 */
/*0210*/ LDG.E R25, [R2.64+0x4] ; /* 0x0000040402197981 */
/* 0x000ee8000c1e1900 */
/*0220*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ee8000c1e1900 */
/*0240*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R21, [R2.64+0xc] ; /* 0x00000c0402157981 */
/* 0x000f68000c1e1900 */
/*0270*/ LDG.E R22, [R4.64+0xc] ; /* 0x00000c0404167981 */
/* 0x000f68000c1e1900 */
/*0280*/ LDG.E R23, [R2.64+0x10] ; /* 0x0000100402177981 */
/* 0x000f68000c1e1900 */
/*0290*/ LDG.E R24, [R4.64+0x10] ; /* 0x0000100404187981 */
/* 0x000f68000c1e1900 */
/*02a0*/ LDG.E R19, [R2.64+0x14] ; /* 0x0000140402137981 */
/* 0x000f68000c1e1900 */
/*02b0*/ LDG.E R20, [R4.64+0x14] ; /* 0x0000140404147981 */
/* 0x000f68000c1e1900 */
/*02c0*/ LDG.E R11, [R2.64+0x18] ; /* 0x00001804020b7981 */
/* 0x000f68000c1e1900 */
/*02d0*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000f68000c1e1900 */
/*02e0*/ LDG.E R26, [R4.64+0x3c] ; /* 0x00003c04041a7981 */
/* 0x000f62000c1e1900 */
/*02f0*/ IMAD R15, R14, R15, R13 ; /* 0x0000000f0e0f7224 */
/* 0x004fc600078e020d */
/*0300*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c04020d7981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R14, [R4.64+0x1c] ; /* 0x00001c04040e7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IMAD R25, R16, R25, R15 ; /* 0x0000001910197224 */
/* 0x008fc600078e020f */
/*0330*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002004020f7981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R16, [R4.64+0x20] ; /* 0x0000200404107981 */
/* 0x000ee2000c1e1900 */
/*0350*/ IMAD R25, R18, R17, R25 ; /* 0x0000001112197224 */
/* 0x010fc600078e0219 */
/*0360*/ LDG.E R17, [R2.64+0x24] ; /* 0x0000240402117981 */
/* 0x000f28000c1e1900 */
/*0370*/ LDG.E R18, [R4.64+0x24] ; /* 0x0000240404127981 */
/* 0x000f22000c1e1900 */
/*0380*/ IMAD R25, R22, R21, R25 ; /* 0x0000001516197224 */
/* 0x020fc600078e0219 */
/*0390*/ LDG.E R22, [R2.64+0x28] ; /* 0x0000280402167981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R21, [R4.64+0x28] ; /* 0x0000280404157981 */
/* 0x000f62000c1e1900 */
/*03b0*/ IMAD R25, R24, R23, R25 ; /* 0x0000001718197224 */
/* 0x000fc600078e0219 */
/*03c0*/ LDG.E R24, [R2.64+0x2c] ; /* 0x00002c0402187981 */
/* 0x000f68000c1e1900 */
/*03d0*/ LDG.E R23, [R4.64+0x2c] ; /* 0x00002c0404177981 */
/* 0x000f62000c1e1900 */
/*03e0*/ IMAD R25, R20, R19, R25 ; /* 0x0000001314197224 */
/* 0x000fc600078e0219 */
/*03f0*/ LDG.E R20, [R2.64+0x30] ; /* 0x0000300402147981 */
/* 0x000f68000c1e1900 */
/*0400*/ LDG.E R19, [R4.64+0x30] ; /* 0x0000300404137981 */
/* 0x000f62000c1e1900 */
/*0410*/ IMAD R25, R12, R11, R25 ; /* 0x0000000b0c197224 */
/* 0x000fc600078e0219 */
/*0420*/ LDG.E R12, [R2.64+0x34] ; /* 0x00003404020c7981 */
/* 0x000168000c1e1900 */
/*0430*/ LDG.E R11, [R4.64+0x34] ; /* 0x00003404040b7981 */
/* 0x000f62000c1e1900 */
/*0440*/ IMAD R27, R14, R13, R25 ; /* 0x0000000d0e1b7224 */
/* 0x004fc600078e0219 */
/*0450*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x0000a8000c1e1900 */
/*0460*/ LDG.E R13, [R4.64+0x38] ; /* 0x00003804040d7981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R25, [R2.64+0x3c] ; /* 0x00003c0402197981 */
/* 0x0000a2000c1e1900 */
/*0480*/ IMAD R15, R16, R15, R27 ; /* 0x0000000f100f7224 */
/* 0x008fc800078e021b */
/*0490*/ IMAD R15, R18, R17, R15 ; /* 0x00000011120f7224 */
/* 0x010fe200078e020f */
/*04a0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*04b0*/ IMAD R15, R21, R22, R15 ; /* 0x00000016150f7224 */
/* 0x020fe200078e020f */
/*04c0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fc60003f24270 */
/*04d0*/ IMAD R15, R23, R24, R15 ; /* 0x00000018170f7224 */
/* 0x000fe200078e020f */
/*04e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fc6000ff1e03f */
/*04f0*/ IMAD R15, R19, R20, R15 ; /* 0x00000014130f7224 */
/* 0x000fe200078e020f */
/*0500*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fe20007f5e0ff */
/*0510*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0520*/ IMAD R11, R11, R12, R15 ; /* 0x0000000c0b0b7224 */
/* 0x000fe200078e020f */
/*0530*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe400017fe4ff */
/*0540*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD R13, R13, R14, R11 ; /* 0x0000000e0d0d7224 */
/* 0x004fc800078e020b */
/*0560*/ IMAD R13, R26, R25, R13 ; /* 0x000000191a0d7224 */
/* 0x000fe200078e020d */
/*0570*/ @P1 BRA 0x1d0 ; /* 0xfffffc5000001947 */
/* 0x000fea000383ffff */
/*0580*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0590*/ @!P1 BRA 0x7c0 ; /* 0x0000022000009947 */
/* 0x000fea0003800000 */
/*05a0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*05b0*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*05c0*/ LDG.E R23, [R2.64] ; /* 0x0000000402177981 */
/* 0x0000a6000c1e1900 */
/*05d0*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe200078e0204 */
/*05e0*/ LDG.E R24, [R2.64+0x4] ; /* 0x0000040402187981 */
/* 0x0000e8000c1e1900 */
/*05f0*/ LDG.E R22, [R4.64] ; /* 0x0000000404167981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R25, [R4.64+0x4] ; /* 0x0000040404197981 */
/* 0x000ee8000c1e1900 */
/*0610*/ LDG.E R26, [R2.64+0x8] ; /* 0x00000804021a7981 */
/* 0x000128000c1e1900 */
/*0620*/ LDG.E R27, [R4.64+0x8] ; /* 0x00000804041b7981 */
/* 0x000f28000c1e1900 */
/*0630*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000168000c1e1900 */
/*0640*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*0650*/ LDG.E R17, [R2.64+0x10] ; /* 0x0000100402117981 */
/* 0x000168000c1e1900 */
/*0660*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000f68000c1e1900 */
/*0670*/ LDG.E R15, [R2.64+0x14] ; /* 0x00001404020f7981 */
/* 0x000168000c1e1900 */
/*0680*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000f68000c1e1900 */
/*0690*/ LDG.E R12, [R2.64+0x18] ; /* 0x00001804020c7981 */
/* 0x000168000c1e1900 */
/*06a0*/ LDG.E R11, [R4.64+0x18] ; /* 0x00001804040b7981 */
/* 0x000f68000c1e1900 */
/*06b0*/ LDG.E R21, [R4.64+0x1c] ; /* 0x00001c0404157981 */
/* 0x000f68000c1e1900 */
/*06c0*/ LDG.E R20, [R2.64+0x1c] ; /* 0x00001c0402147981 */
/* 0x000162000c1e1900 */
/*06d0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*06e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*06f0*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe40007ffe0ff */
/*0710*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x001fe20007f3e0ff */
/*0720*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fc600087fe43f */
/*0730*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*0740*/ IMAD R22, R22, R23, R13 ; /* 0x0000001716167224 */
/* 0x004fc800078e020d */
/*0750*/ IMAD R22, R25, R24, R22 ; /* 0x0000001819167224 */
/* 0x008fc800078e0216 */
/*0760*/ IMAD R22, R27, R26, R22 ; /* 0x0000001a1b167224 */
/* 0x010fc800078e0216 */
/*0770*/ IMAD R18, R18, R19, R22 ; /* 0x0000001312127224 */
/* 0x020fc800078e0216 */
/*0780*/ IMAD R16, R16, R17, R18 ; /* 0x0000001110107224 */
/* 0x000fc800078e0212 */
/*0790*/ IMAD R14, R14, R15, R16 ; /* 0x0000000f0e0e7224 */
/* 0x000fc800078e0210 */
/*07a0*/ IMAD R11, R11, R12, R14 ; /* 0x0000000c0b0b7224 */
/* 0x000fc800078e020e */
/*07b0*/ IMAD R13, R21, R20, R11 ; /* 0x00000014150d7224 */
/* 0x000fe400078e020b */
/*07c0*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*07d0*/ @!P0 BRA 0x960 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*07e0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*07f0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1900 */
/*0800*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fc60008000f00 */
/*0810*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000ee4000c1e1900 */
/*0820*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fe400078e0204 */
/*0830*/ LDG.E R17, [R2.64+0x8] ; /* 0x0000080402117981 */
/* 0x000f28000c1e1900 */
/*0840*/ LDG.E R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R14, [R4.64+0x4] ; /* 0x00000404040e7981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000f28000c1e1900 */
/*0870*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000f68000c1e1900 */
/*0880*/ LDG.E R19, [R2.64+0xc] ; /* 0x00000c0402137981 */
/* 0x000162000c1e1900 */
/*0890*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*08a0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*08b0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*08c0*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ IMAD R11, R12, R11, R13 ; /* 0x0000000b0c0b7224 */
/* 0x004fe200078e020d */
/*08f0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fc60007f3e0ff */
/*0900*/ IMAD R11, R14, R15, R11 ; /* 0x0000000f0e0b7224 */
/* 0x008fc800078e020b */
/*0910*/ IMAD R11, R16, R17, R11 ; /* 0x00000011100b7224 */
/* 0x010fe200078e020b */
/*0920*/ MOV R2, R12 ; /* 0x0000000c00027202 */
/* 0x001fe20000000f00 */
/*0930*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe400008e0603 */
/*0940*/ IMAD R13, R18, R19, R11 ; /* 0x00000013120d7224 */
/* 0x020fe200078e020b */
/*0950*/ @P0 BRA 0x7e0 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*0960*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0970*/ @!P0 BRA 0xab0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0980*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0990*/ IMAD R2, R0, c[0x0][0x178], R10 ; /* 0x00005e0000027a24 */
/* 0x000fe200078e020a */
/*09a0*/ IADD3 R4, R7, R10, RZ ; /* 0x0000000a07047210 */
/* 0x000fd00007ffe0ff */
/*09b0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fc800078e0205 */
/*09c0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*09d0*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*09e0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*09f0*/ MOV R2, R9 ; /* 0x0000000900027202 */
/* 0x000fe40000000f00 */
/*0a00*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fc80000000f00 */
/*0a10*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a8000c1e1900 */
/*0a20*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0a30*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ IADD3 R9, P1, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe40007f3e0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0a60*/ IADD3 R8, P2, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007f5e0ff */
/*0a70*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fc600008e0603 */
/*0a80*/ IADD3.X R5, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff057210 */
/* 0x002fe200017fe4ff */
/*0a90*/ IMAD R13, R2, R4, R13 ; /* 0x00000004020d7224 */
/* 0x004fcc00078e020d */
/*0aa0*/ @P0 BRA 0x9f0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0ab0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0ac0*/ IADD3 R2, R0, R7, RZ ; /* 0x0000000700027210 */
/* 0x000fd20007ffe0ff */
/*0ad0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0ae0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101904 */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matrixMultPiS_S_i
.globl _Z10matrixMultPiS_S_i
.p2align 8
.type _Z10matrixMultPiS_S_i,@function
_Z10matrixMultPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v2, v1, s2
v_mul_lo_u32 v4, v0, s2
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v9, vcc_lo
.p2align 6
.LBB0_2:
global_load_b32 v9, v[5:6], off
global_load_b32 v10, v[3:4], off
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v10, v9, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_mov_b32_e32 v2, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matrixMultPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matrixMultPiS_S_i, .Lfunc_end0-_Z10matrixMultPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matrixMultPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10matrixMultPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001368de_00000000-6_matrixMult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixMultPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
.globl _Z10matrixMultPiS_S_i
.type _Z10matrixMultPiS_S_i, @function
_Z10matrixMultPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10matrixMultPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10matrixMultPiS_S_i, .-_Z10matrixMultPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10matrixMultPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixMultPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matrixMult.hip"
.globl _Z25__device_stub__matrixMultPiS_S_i # -- Begin function _Z25__device_stub__matrixMultPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__matrixMultPiS_S_i,@function
_Z25__device_stub__matrixMultPiS_S_i: # @_Z25__device_stub__matrixMultPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixMultPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__matrixMultPiS_S_i, .Lfunc_end0-_Z25__device_stub__matrixMultPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixMultPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matrixMultPiS_S_i,@object # @_Z10matrixMultPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10matrixMultPiS_S_i
.p2align 3, 0x0
_Z10matrixMultPiS_S_i:
.quad _Z25__device_stub__matrixMultPiS_S_i
.size _Z10matrixMultPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10matrixMultPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matrixMultPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matrixMultPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define ARR_SIZE 102400
#define THREADS 512
#define ARR_BYTE sizeof(int) * ARR_SIZE
__global__ void gpuSort(int * d_arr, size_t maxSize);
int main(int argv, char ** argc)
{
int * h_arr;
int * d_arr;
int temp;
int blockSize;
size_t i;
cudaEvent_t start, stop;
float milliseconds;
cudaEventCreate(&start);
cudaEventCreate(&stop);
h_arr = (int *)malloc(ARR_BYTE);
cudaMalloc((void **)&d_arr, ARR_BYTE);
for (i = 0; i < ARR_SIZE; i++)
h_arr[i] = rand() % 1024;
cudaMemcpy(d_arr, h_arr, ARR_BYTE, cudaMemcpyHostToDevice);
blockSize = ARR_SIZE / THREADS;
blockSize += (ARR_SIZE%THREADS ? 1 : 0);
blockSize += (blockSize / 2) + (blockSize % 2);
cudaEventRecord(start);
for (i = 0; i < ARR_SIZE/2+1; i++) {
gpuSort <<< blockSize, THREADS >>> (d_arr, ARR_SIZE);
}
cudaEventRecord(stop);
cudaMemcpy(h_arr, d_arr, ARR_BYTE, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
for (i = 1; i < ARR_SIZE; i++) {
if (h_arr[i - 1] > h_arr[i]) {
printf("\nNot sorted\n\n");
break;
}
}
if (i == ARR_SIZE) {
printf("\nSorted\n");
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Time taken : %llf\n", milliseconds / 1000);
}
cudaFree(d_arr);
free(h_arr);
}
__global__ void gpuSort(int * d_arr, size_t maxSize)
{
int temp;
size_t threadIndex = threadIdx.x + blockDim.x*blockIdx.x;
threadIndex *= 2;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex++;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex--;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
}
|
code for sm_80
Function : _Z7gpuSortPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x170 ; /* 0x0000013000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R4, R2, 0x2, RZ ; /* 0x0000000202047825 */
/* 0x000fca00078e00ff */
/*0070*/ LOP3.LUT R3, R4.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x0000000104037812 */
/* 0x040fe400078efcff */
/*0080*/ IADD3 R0, P2, R4, 0x2, RZ ; /* 0x0000000204007810 */
/* 0x000fe40007f5e0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f06070 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f26070 */
/*00c0*/ IMAD.X R0, RZ, RZ, R5, P2 ; /* 0x000000ffff007224 */
/* 0x000fe200010e0605 */
/*00d0*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x16c], PT, P0 ; /* 0x00005b0005007a0c */
/* 0x000fe20003f06100 */
/*00e0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0003 */
/*00f0*/ ISETP.GE.U32.AND.EX P1, PT, R0, c[0x0][0x16c], PT, P1 ; /* 0x00005b0000007a0c */
/* 0x000fd20003f26110 */
/*0100*/ @P0 BRA 0x160 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0130*/ ISETP.GT.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f44270 */
/*0140*/ @P2 STG.E [R2.64], R0 ; /* 0x0000000002002986 */
/* 0x0001e8000c101904 */
/*0150*/ @P2 STG.E [R2.64+0x4], R5 ; /* 0x0000040502002986 */
/* 0x0001e4000c101904 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ BSSY B0, 0x1f0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0180*/ @P1 BRA 0x1e0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x001ea8000c1e1900 */
/*01a0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ ISETP.GT.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f24270 */
/*01c0*/ @P1 STG.E [R2.64+0x4], R5 ; /* 0x0000040502001986 */
/* 0x0001e8000c101904 */
/*01d0*/ @P1 STG.E [R2.64+0x8], R0 ; /* 0x0000080002001986 */
/* 0x0001e4000c101904 */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea8000c1e1900 */
/*0210*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0220*/ ISETP.GT.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f04270 */
/*0230*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0240*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*0250*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define ARR_SIZE 102400
#define THREADS 512
#define ARR_BYTE sizeof(int) * ARR_SIZE
__global__ void gpuSort(int * d_arr, size_t maxSize);
int main(int argv, char ** argc)
{
int * h_arr;
int * d_arr;
int temp;
int blockSize;
size_t i;
cudaEvent_t start, stop;
float milliseconds;
cudaEventCreate(&start);
cudaEventCreate(&stop);
h_arr = (int *)malloc(ARR_BYTE);
cudaMalloc((void **)&d_arr, ARR_BYTE);
for (i = 0; i < ARR_SIZE; i++)
h_arr[i] = rand() % 1024;
cudaMemcpy(d_arr, h_arr, ARR_BYTE, cudaMemcpyHostToDevice);
blockSize = ARR_SIZE / THREADS;
blockSize += (ARR_SIZE%THREADS ? 1 : 0);
blockSize += (blockSize / 2) + (blockSize % 2);
cudaEventRecord(start);
for (i = 0; i < ARR_SIZE/2+1; i++) {
gpuSort <<< blockSize, THREADS >>> (d_arr, ARR_SIZE);
}
cudaEventRecord(stop);
cudaMemcpy(h_arr, d_arr, ARR_BYTE, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
for (i = 1; i < ARR_SIZE; i++) {
if (h_arr[i - 1] > h_arr[i]) {
printf("\nNot sorted\n\n");
break;
}
}
if (i == ARR_SIZE) {
printf("\nSorted\n");
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Time taken : %llf\n", milliseconds / 1000);
}
cudaFree(d_arr);
free(h_arr);
}
__global__ void gpuSort(int * d_arr, size_t maxSize)
{
int temp;
size_t threadIndex = threadIdx.x + blockDim.x*blockIdx.x;
threadIndex *= 2;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex++;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex--;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
}
|
.file "tmpxft_00130519_00000000-6_bubblesort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7gpuSortPimPim
.type _Z27__device_stub__Z7gpuSortPimPim, @function
_Z27__device_stub__Z7gpuSortPimPim:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7gpuSortPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z7gpuSortPimPim, .-_Z27__device_stub__Z7gpuSortPimPim
.globl _Z7gpuSortPim
.type _Z7gpuSortPim, @function
_Z7gpuSortPim:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7gpuSortPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7gpuSortPim, .-_Z7gpuSortPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nNot sorted\n\n"
.LC1:
.string "\nSorted\n"
.LC3:
.string "Time taken : %llf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $409600, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $409600, %esi
call cudaMalloc@PLT
movq %r12, %rbx
leaq 409600(%r12), %rbp
.L12:
call rand@PLT
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
movl $1, %ecx
movl $409600, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $51201, %ebx
jmp .L14
.L13:
subq $1, %rbx
je .L23
.L14:
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $300, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $102400, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7gpuSortPimPim
jmp .L13
.L23:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $409600, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $1, %eax
.L17:
movl (%r12,%rax,4), %ecx
cmpl %ecx, -4(%r12,%rax,4)
jg .L24
addq $1, %rax
cmpq $102400, %rax
jne .L17
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 44(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L16
.L24:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7gpuSortPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7gpuSortPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define ARR_SIZE 102400
#define THREADS 512
#define ARR_BYTE sizeof(int) * ARR_SIZE
__global__ void gpuSort(int * d_arr, size_t maxSize);
int main(int argv, char ** argc)
{
int * h_arr;
int * d_arr;
int temp;
int blockSize;
size_t i;
cudaEvent_t start, stop;
float milliseconds;
cudaEventCreate(&start);
cudaEventCreate(&stop);
h_arr = (int *)malloc(ARR_BYTE);
cudaMalloc((void **)&d_arr, ARR_BYTE);
for (i = 0; i < ARR_SIZE; i++)
h_arr[i] = rand() % 1024;
cudaMemcpy(d_arr, h_arr, ARR_BYTE, cudaMemcpyHostToDevice);
blockSize = ARR_SIZE / THREADS;
blockSize += (ARR_SIZE%THREADS ? 1 : 0);
blockSize += (blockSize / 2) + (blockSize % 2);
cudaEventRecord(start);
for (i = 0; i < ARR_SIZE/2+1; i++) {
gpuSort <<< blockSize, THREADS >>> (d_arr, ARR_SIZE);
}
cudaEventRecord(stop);
cudaMemcpy(h_arr, d_arr, ARR_BYTE, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
for (i = 1; i < ARR_SIZE; i++) {
if (h_arr[i - 1] > h_arr[i]) {
printf("\nNot sorted\n\n");
break;
}
}
if (i == ARR_SIZE) {
printf("\nSorted\n");
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Time taken : %llf\n", milliseconds / 1000);
}
cudaFree(d_arr);
free(h_arr);
}
__global__ void gpuSort(int * d_arr, size_t maxSize)
{
int temp;
size_t threadIndex = threadIdx.x + blockDim.x*blockIdx.x;
threadIndex *= 2;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex++;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex--;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
}
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define ARR_SIZE 102400
#define THREADS 512
#define ARR_BYTE sizeof(int) * ARR_SIZE
__global__ void gpuSort(int * d_arr, size_t maxSize);
int main(int argv, char ** argc)
{
int * h_arr;
int * d_arr;
int temp;
int blockSize;
size_t i;
hipEvent_t start, stop;
float milliseconds;
hipEventCreate(&start);
hipEventCreate(&stop);
h_arr = (int *)malloc(ARR_BYTE);
hipMalloc((void **)&d_arr, ARR_BYTE);
for (i = 0; i < ARR_SIZE; i++)
h_arr[i] = rand() % 1024;
hipMemcpy(d_arr, h_arr, ARR_BYTE, hipMemcpyHostToDevice);
blockSize = ARR_SIZE / THREADS;
blockSize += (ARR_SIZE%THREADS ? 1 : 0);
blockSize += (blockSize / 2) + (blockSize % 2);
hipEventRecord(start);
for (i = 0; i < ARR_SIZE/2+1; i++) {
gpuSort <<< blockSize, THREADS >>> (d_arr, ARR_SIZE);
}
hipEventRecord(stop);
hipMemcpy(h_arr, d_arr, ARR_BYTE, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
for (i = 1; i < ARR_SIZE; i++) {
if (h_arr[i - 1] > h_arr[i]) {
printf("\nNot sorted\n\n");
break;
}
}
if (i == ARR_SIZE) {
printf("\nSorted\n");
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time taken : %llf\n", milliseconds / 1000);
}
hipFree(d_arr);
free(h_arr);
}
__global__ void gpuSort(int * d_arr, size_t maxSize)
{
int temp;
size_t threadIndex = threadIdx.x + blockDim.x*blockIdx.x;
threadIndex *= 2;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex++;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex--;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define ARR_SIZE 102400
#define THREADS 512
#define ARR_BYTE sizeof(int) * ARR_SIZE
__global__ void gpuSort(int * d_arr, size_t maxSize);
int main(int argv, char ** argc)
{
int * h_arr;
int * d_arr;
int temp;
int blockSize;
size_t i;
hipEvent_t start, stop;
float milliseconds;
hipEventCreate(&start);
hipEventCreate(&stop);
h_arr = (int *)malloc(ARR_BYTE);
hipMalloc((void **)&d_arr, ARR_BYTE);
for (i = 0; i < ARR_SIZE; i++)
h_arr[i] = rand() % 1024;
hipMemcpy(d_arr, h_arr, ARR_BYTE, hipMemcpyHostToDevice);
blockSize = ARR_SIZE / THREADS;
blockSize += (ARR_SIZE%THREADS ? 1 : 0);
blockSize += (blockSize / 2) + (blockSize % 2);
hipEventRecord(start);
for (i = 0; i < ARR_SIZE/2+1; i++) {
gpuSort <<< blockSize, THREADS >>> (d_arr, ARR_SIZE);
}
hipEventRecord(stop);
hipMemcpy(h_arr, d_arr, ARR_BYTE, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
for (i = 1; i < ARR_SIZE; i++) {
if (h_arr[i - 1] > h_arr[i]) {
printf("\nNot sorted\n\n");
break;
}
}
if (i == ARR_SIZE) {
printf("\nSorted\n");
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time taken : %llf\n", milliseconds / 1000);
}
hipFree(d_arr);
free(h_arr);
}
__global__ void gpuSort(int * d_arr, size_t maxSize)
{
int temp;
size_t threadIndex = threadIdx.x + blockDim.x*blockIdx.x;
threadIndex *= 2;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex++;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex--;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7gpuSortPim
.globl _Z7gpuSortPim
.p2align 8
.type _Z7gpuSortPim,@function
_Z7gpuSortPim:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[2:3], 1, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v1, v3
v_or_b32_e32 v0, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[0:1]
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s4, v4
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
s_clause 0x1
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e64 s0, v8, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s0
s_clause 0x1
global_store_b32 v[4:5], v9, off
global_store_b32 v[6:7], v8, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s1
v_add_co_u32 v4, s0, v2, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, 0, v3, s0
s_mov_b32 s1, exec_lo
v_cmpx_gt_u64_e64 s[6:7], v[4:5]
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s4, v6
v_add_co_ci_u32_e64 v5, s0, s5, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v8
v_add_co_ci_u32_e64 v7, s0, s5, v9, s0
s_clause 0x1
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e64 s0, v8, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s0
s_clause 0x1
global_store_b32 v[4:5], v9, off
global_store_b32 v[6:7], v8, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_9
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v4, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7gpuSortPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7gpuSortPim, .Lfunc_end0-_Z7gpuSortPim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7gpuSortPim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7gpuSortPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#define ARR_SIZE 102400
#define THREADS 512
#define ARR_BYTE sizeof(int) * ARR_SIZE
__global__ void gpuSort(int * d_arr, size_t maxSize);
int main(int argv, char ** argc)
{
int * h_arr;
int * d_arr;
int temp;
int blockSize;
size_t i;
hipEvent_t start, stop;
float milliseconds;
hipEventCreate(&start);
hipEventCreate(&stop);
h_arr = (int *)malloc(ARR_BYTE);
hipMalloc((void **)&d_arr, ARR_BYTE);
for (i = 0; i < ARR_SIZE; i++)
h_arr[i] = rand() % 1024;
hipMemcpy(d_arr, h_arr, ARR_BYTE, hipMemcpyHostToDevice);
blockSize = ARR_SIZE / THREADS;
blockSize += (ARR_SIZE%THREADS ? 1 : 0);
blockSize += (blockSize / 2) + (blockSize % 2);
hipEventRecord(start);
for (i = 0; i < ARR_SIZE/2+1; i++) {
gpuSort <<< blockSize, THREADS >>> (d_arr, ARR_SIZE);
}
hipEventRecord(stop);
hipMemcpy(h_arr, d_arr, ARR_BYTE, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
for (i = 1; i < ARR_SIZE; i++) {
if (h_arr[i - 1] > h_arr[i]) {
printf("\nNot sorted\n\n");
break;
}
}
if (i == ARR_SIZE) {
printf("\nSorted\n");
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time taken : %llf\n", milliseconds / 1000);
}
hipFree(d_arr);
free(h_arr);
}
__global__ void gpuSort(int * d_arr, size_t maxSize)
{
int temp;
size_t threadIndex = threadIdx.x + blockDim.x*blockIdx.x;
threadIndex *= 2;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex++;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
threadIndex--;
if (threadIndex + 1 < maxSize) {
if (d_arr[threadIndex] > d_arr[threadIndex + 1]) {
temp = d_arr[threadIndex];
d_arr[threadIndex] = d_arr[threadIndex + 1];
d_arr[threadIndex + 1] = temp;
}
}
}
|
.text
.file "bubblesort.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $409600, %edi # imm = 0x64000
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $409600, %esi # imm = 0x64000
callq hipMalloc
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $102400, %r14 # imm = 0x19000
jne .LBB0_1
# %bb.2:
movabsq $4294967596, %r14 # imm = 0x10000012C
movq 8(%rsp), %rdi
movl $409600, %edx # imm = 0x64000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $51201, %ebp # imm = 0xC801
leaq 212(%r14), %r15
leaq 56(%rsp), %r12
leaq 32(%rsp), %r13
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_3 Depth=1
decq %rbp
je .LBB0_6
.LBB0_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_5
# %bb.4: # in Loop: Header=BB0_3 Depth=1
movq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq $102400, 104(%rsp) # imm = 0x19000
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 40(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z7gpuSortPim, %edi
movq %r13, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_5
.LBB0_6:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movl $409600, %edx # imm = 0x64000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $1, %r14d
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movl -4(%rbx,%r14,4), %eax
cmpl (%rbx,%r14,4), %eax
jg .LBB0_8
# %bb.9: # in Loop: Header=BB0_7 Depth=1
incq %r14
cmpq $102400, %r14 # imm = 0x19000
jne .LBB0_7
jmp .LBB0_10
.LBB0_8: # %.loopexit
movl $.Lstr, %edi
callq puts@PLT
cmpq $102400, %r14 # imm = 0x19000
jne .LBB0_11
.LBB0_10: # %.critedge
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
.LBB0_11:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z22__device_stub__gpuSortPim # -- Begin function _Z22__device_stub__gpuSortPim
.p2align 4, 0x90
.type _Z22__device_stub__gpuSortPim,@function
_Z22__device_stub__gpuSortPim: # @_Z22__device_stub__gpuSortPim
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7gpuSortPim, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__gpuSortPim, .Lfunc_end1-_Z22__device_stub__gpuSortPim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7gpuSortPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7gpuSortPim,@object # @_Z7gpuSortPim
.section .rodata,"a",@progbits
.globl _Z7gpuSortPim
.p2align 3, 0x0
_Z7gpuSortPim:
.quad _Z22__device_stub__gpuSortPim
.size _Z7gpuSortPim, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Time taken : %llf\n"
.size .L.str.2, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7gpuSortPim"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nNot sorted\n"
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nSorted"
.size .Lstr.1, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__gpuSortPim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7gpuSortPim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z7gpuSortPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x170 ; /* 0x0000013000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R4, R2, 0x2, RZ ; /* 0x0000000202047825 */
/* 0x000fca00078e00ff */
/*0070*/ LOP3.LUT R3, R4.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x0000000104037812 */
/* 0x040fe400078efcff */
/*0080*/ IADD3 R0, P2, R4, 0x2, RZ ; /* 0x0000000204007810 */
/* 0x000fe40007f5e0ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f06070 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe200078e00ff */
/*00b0*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f26070 */
/*00c0*/ IMAD.X R0, RZ, RZ, R5, P2 ; /* 0x000000ffff007224 */
/* 0x000fe200010e0605 */
/*00d0*/ ISETP.GE.U32.AND.EX P0, PT, R5, c[0x0][0x16c], PT, P0 ; /* 0x00005b0005007a0c */
/* 0x000fe20003f06100 */
/*00e0*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc600078e0003 */
/*00f0*/ ISETP.GE.U32.AND.EX P1, PT, R0, c[0x0][0x16c], PT, P1 ; /* 0x00005b0000007a0c */
/* 0x000fd20003f26110 */
/*0100*/ @P0 BRA 0x160 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0130*/ ISETP.GT.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f44270 */
/*0140*/ @P2 STG.E [R2.64], R0 ; /* 0x0000000002002986 */
/* 0x0001e8000c101904 */
/*0150*/ @P2 STG.E [R2.64+0x4], R5 ; /* 0x0000040502002986 */
/* 0x0001e4000c101904 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ BSSY B0, 0x1f0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0180*/ @P1 BRA 0x1e0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x001ea8000c1e1900 */
/*01a0*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ ISETP.GT.AND P1, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f24270 */
/*01c0*/ @P1 STG.E [R2.64+0x4], R5 ; /* 0x0000040502001986 */
/* 0x0001e8000c101904 */
/*01d0*/ @P1 STG.E [R2.64+0x8], R0 ; /* 0x0000080002001986 */
/* 0x0001e4000c101904 */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x001ea8000c1e1900 */
/*0210*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea4000c1e1900 */
/*0220*/ ISETP.GT.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f04270 */
/*0230*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0240*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe8000c101904 */
/*0250*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7gpuSortPim
.globl _Z7gpuSortPim
.p2align 8
.type _Z7gpuSortPim,@function
_Z7gpuSortPim:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[2:3], 1, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v1, v3
v_or_b32_e32 v0, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[0:1]
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_3
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s4, v4
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v6
v_add_co_ci_u32_e64 v7, s0, s5, v7, s0
s_clause 0x1
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e64 s0, v8, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s0
s_clause 0x1
global_store_b32 v[4:5], v9, off
global_store_b32 v[6:7], v8, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s1
v_add_co_u32 v4, s0, v2, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, 0, v3, s0
s_mov_b32 s1, exec_lo
v_cmpx_gt_u64_e64 s[6:7], v[4:5]
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[6:7], 2, v[0:1]
v_lshlrev_b64 v[8:9], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s4, v6
v_add_co_ci_u32_e64 v5, s0, s5, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s4, v8
v_add_co_ci_u32_e64 v7, s0, s5, v9, s0
s_clause 0x1
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e64 s0, v8, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 exec_lo, exec_lo, s0
s_clause 0x1
global_store_b32 v[4:5], v9, off
global_store_b32 v[6:7], v8, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_9
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_clause 0x1
global_store_b32 v[0:1], v5, off
global_store_b32 v[2:3], v4, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7gpuSortPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7gpuSortPim, .Lfunc_end0-_Z7gpuSortPim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7gpuSortPim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7gpuSortPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00130519_00000000-6_bubblesort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7gpuSortPimPim
.type _Z27__device_stub__Z7gpuSortPimPim, @function
_Z27__device_stub__Z7gpuSortPimPim:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7gpuSortPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z7gpuSortPimPim, .-_Z27__device_stub__Z7gpuSortPimPim
.globl _Z7gpuSortPim
.type _Z7gpuSortPim, @function
_Z7gpuSortPim:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7gpuSortPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7gpuSortPim, .-_Z7gpuSortPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\nNot sorted\n\n"
.LC1:
.string "\nSorted\n"
.LC3:
.string "Time taken : %llf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $409600, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $409600, %esi
call cudaMalloc@PLT
movq %r12, %rbx
leaq 409600(%r12), %rbp
.L12:
call rand@PLT
cltd
shrl $22, %edx
addl %edx, %eax
andl $1023, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
movl $1, %ecx
movl $409600, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $51201, %ebx
jmp .L14
.L13:
subq $1, %rbx
je .L23
.L14:
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $300, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl $102400, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7gpuSortPimPim
jmp .L13
.L23:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $409600, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $1, %eax
.L17:
movl (%r12,%rax,4), %ecx
cmpl %ecx, -4(%r12,%rax,4)
jg .L24
addq $1, %rax
cmpq $102400, %rax
jne .L17
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 44(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L16
.L24:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7gpuSortPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7gpuSortPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "bubblesort.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $409600, %edi # imm = 0x64000
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $409600, %esi # imm = 0x64000
callq hipMalloc
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
callq rand
# kill: def $eax killed $eax def $rax
leal 1023(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-1024, %ecx # imm = 0xFC00
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $102400, %r14 # imm = 0x19000
jne .LBB0_1
# %bb.2:
movabsq $4294967596, %r14 # imm = 0x10000012C
movq 8(%rsp), %rdi
movl $409600, %edx # imm = 0x64000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $51201, %ebp # imm = 0xC801
leaq 212(%r14), %r15
leaq 56(%rsp), %r12
leaq 32(%rsp), %r13
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_3 Depth=1
decq %rbp
je .LBB0_6
.LBB0_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_5
# %bb.4: # in Loop: Header=BB0_3 Depth=1
movq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq $102400, 104(%rsp) # imm = 0x19000
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 40(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z7gpuSortPim, %edi
movq %r13, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_5
.LBB0_6:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movl $409600, %edx # imm = 0x64000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $1, %r14d
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movl -4(%rbx,%r14,4), %eax
cmpl (%rbx,%r14,4), %eax
jg .LBB0_8
# %bb.9: # in Loop: Header=BB0_7 Depth=1
incq %r14
cmpq $102400, %r14 # imm = 0x19000
jne .LBB0_7
jmp .LBB0_10
.LBB0_8: # %.loopexit
movl $.Lstr, %edi
callq puts@PLT
cmpq $102400, %r14 # imm = 0x19000
jne .LBB0_11
.LBB0_10: # %.critedge
movl $.Lstr.1, %edi
callq puts@PLT
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
.LBB0_11:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z22__device_stub__gpuSortPim # -- Begin function _Z22__device_stub__gpuSortPim
.p2align 4, 0x90
.type _Z22__device_stub__gpuSortPim,@function
_Z22__device_stub__gpuSortPim: # @_Z22__device_stub__gpuSortPim
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7gpuSortPim, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__gpuSortPim, .Lfunc_end1-_Z22__device_stub__gpuSortPim
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7gpuSortPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7gpuSortPim,@object # @_Z7gpuSortPim
.section .rodata,"a",@progbits
.globl _Z7gpuSortPim
.p2align 3, 0x0
_Z7gpuSortPim:
.quad _Z22__device_stub__gpuSortPim
.size _Z7gpuSortPim, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Time taken : %llf\n"
.size .L.str.2, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7gpuSortPim"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nNot sorted\n"
.size .Lstr, 13
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nSorted"
.size .Lstr.1, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__gpuSortPim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7gpuSortPim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void KerSortDataParticles(unsigned n,unsigned pini,const unsigned *sortpart,const float3 *a,float3 *a2)
{
const unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Particle number.
if(p<n){
const unsigned oldpos=(p<pini? p: sortpart[p]);
a2[p]=a[oldpos];
}
}
|
code for sm_80
Function : _Z20KerSortDataParticlesjjPKjPK6float3PS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @P0 LEA R4, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000040a11 */
/* 0x000fc800078210ff */
/*0090*/ @P0 LEA.HI.X R5, R0, c[0x0][0x16c], RZ, 0x2, P1 ; /* 0x00005b0000050a11 */
/* 0x000fca00008f14ff */
/*00a0*/ @P0 LDG.E R4, [R4.64] ; /* 0x0000000604040981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ HFMA2.MMA R13, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff0d7435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0000 */
/*00e0*/ @P0 MOV R3, RZ ; /* 0x000000ff00030202 */
/* 0x000fca0000000f00 */
/*00f0*/ IMAD R7, R3, 0xc, RZ ; /* 0x0000000c03077824 */
/* 0x000fe400078e02ff */
/*0100*/ @P0 IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff020224 */
/* 0x004fc800078e0004 */
/*0110*/ IMAD.WIDE.U32 R2, R2, R13, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e000d */
/*0120*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fca00078e0207 */
/*0130*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040602097981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000806020b7981 */
/* 0x000f22000c1e1900 */
/*0160*/ IMAD.WIDE.U32 R4, R0, R13, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e000d */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc80008000000 */
/*0180*/ IADD3 R5, R5, UR4, RZ ; /* 0x0000000405057c10 */
/* 0x000fca000fffe0ff */
/*0190*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c101906 */
/*01a0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x008fe8000c101906 */
/*01b0*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x010fe2000c101906 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void KerSortDataParticles(unsigned n,unsigned pini,const unsigned *sortpart,const float3 *a,float3 *a2)
{
const unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Particle number.
if(p<n){
const unsigned oldpos=(p<pini? p: sortpart[p]);
a2[p]=a[oldpos];
}
}
|
.file "tmpxft_0000dfdb_00000000-6_KerSortDataParticles.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_
.type _Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_, @function
_Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20KerSortDataParticlesjjPKjPK6float3PS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_, .-_Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_
.globl _Z20KerSortDataParticlesjjPKjPK6float3PS1_
.type _Z20KerSortDataParticlesjjPKjPK6float3PS1_, @function
_Z20KerSortDataParticlesjjPKjPK6float3PS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20KerSortDataParticlesjjPKjPK6float3PS1_, .-_Z20KerSortDataParticlesjjPKjPK6float3PS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20KerSortDataParticlesjjPKjPK6float3PS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20KerSortDataParticlesjjPKjPK6float3PS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void KerSortDataParticles(unsigned n,unsigned pini,const unsigned *sortpart,const float3 *a,float3 *a2)
{
const unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Particle number.
if(p<n){
const unsigned oldpos=(p<pini? p: sortpart[p]);
a2[p]=a[oldpos];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KerSortDataParticles(unsigned n,unsigned pini,const unsigned *sortpart,const float3 *a,float3 *a2)
{
const unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Particle number.
if(p<n){
const unsigned oldpos=(p<pini? p: sortpart[p]);
a2[p]=a[oldpos];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KerSortDataParticles(unsigned n,unsigned pini,const unsigned *sortpart,const float3 *a,float3 *a2)
{
const unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Particle number.
if(p<n){
const unsigned oldpos=(p<pini? p: sortpart[p]);
a2[p]=a[oldpos];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.globl _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.p2align 8
.type _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_,@function
_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_mov_b32_e32 v0, v1
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
v_cmp_le_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x10
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, 12, s[0:1]
v_mad_u64_u32 v[4:5], null, v1, 12, s[2:3]
global_load_b32 v0, v[2:3], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v0, off offset:8
global_load_b64 v[0:1], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[4:5], v[0:1], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_, .Lfunc_end0-_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void KerSortDataParticles(unsigned n,unsigned pini,const unsigned *sortpart,const float3 *a,float3 *a2)
{
const unsigned p=blockIdx.x*blockDim.x + threadIdx.x; //-Particle number.
if(p<n){
const unsigned oldpos=(p<pini? p: sortpart[p]);
a2[p]=a[oldpos];
}
}
|
.text
.file "KerSortDataParticles.hip"
.globl _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_ # -- Begin function _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.p2align 4, 0x90
.type _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_,@function
_Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_: # @_Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_, .Lfunc_end0-_Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_,@object # @_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.section .rodata,"a",@progbits
.globl _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.p2align 3, 0x0
_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_:
.quad _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.size _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_"
.size .L__unnamed_1, 60
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z20KerSortDataParticlesjjPKjPK6float3PS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fe20003f06070 */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd80000000a00 */
/*0080*/ @P0 LEA R4, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000040a11 */
/* 0x000fc800078210ff */
/*0090*/ @P0 LEA.HI.X R5, R0, c[0x0][0x16c], RZ, 0x2, P1 ; /* 0x00005b0000050a11 */
/* 0x000fca00008f14ff */
/*00a0*/ @P0 LDG.E R4, [R4.64] ; /* 0x0000000604040981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ HFMA2.MMA R13, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff0d7435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0000 */
/*00e0*/ @P0 MOV R3, RZ ; /* 0x000000ff00030202 */
/* 0x000fca0000000f00 */
/*00f0*/ IMAD R7, R3, 0xc, RZ ; /* 0x0000000c03077824 */
/* 0x000fe400078e02ff */
/*0100*/ @P0 IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff020224 */
/* 0x004fc800078e0004 */
/*0110*/ IMAD.WIDE.U32 R2, R2, R13, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e000d */
/*0120*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fca00078e0207 */
/*0130*/ LDG.E R7, [R2.64] ; /* 0x0000000602077981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040602097981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000806020b7981 */
/* 0x000f22000c1e1900 */
/*0160*/ IMAD.WIDE.U32 R4, R0, R13, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e000d */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc80008000000 */
/*0180*/ IADD3 R5, R5, UR4, RZ ; /* 0x0000000405057c10 */
/* 0x000fca000fffe0ff */
/*0190*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c101906 */
/*01a0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x008fe8000c101906 */
/*01b0*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x010fe2000c101906 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.globl _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.p2align 8
.type _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_,@function
_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_mov_b32_e32 v0, v1
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
v_cmp_le_u32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x10
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, 12, s[0:1]
v_mad_u64_u32 v[4:5], null, v1, 12, s[2:3]
global_load_b32 v0, v[2:3], off offset:8
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v0, off offset:8
global_load_b64 v[0:1], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[4:5], v[0:1], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_, .Lfunc_end0-_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0000dfdb_00000000-6_KerSortDataParticles.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_
.type _Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_, @function
_Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20KerSortDataParticlesjjPKjPK6float3PS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_, .-_Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_
.globl _Z20KerSortDataParticlesjjPKjPK6float3PS1_
.type _Z20KerSortDataParticlesjjPKjPK6float3PS1_, @function
_Z20KerSortDataParticlesjjPKjPK6float3PS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z20KerSortDataParticlesjjPKjPK6float3PS1_jjPKjPK6float3PS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20KerSortDataParticlesjjPKjPK6float3PS1_, .-_Z20KerSortDataParticlesjjPKjPK6float3PS1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20KerSortDataParticlesjjPKjPK6float3PS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20KerSortDataParticlesjjPKjPK6float3PS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "KerSortDataParticles.hip"
.globl _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_ # -- Begin function _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.p2align 4, 0x90
.type _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_,@function
_Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_: # @_Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_, .Lfunc_end0-_Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_,@object # @_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.section .rodata,"a",@progbits
.globl _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.p2align 3, 0x0
_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_:
.quad _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.size _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_"
.size .L__unnamed_1, 60
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20KerSortDataParticlesjjPKjPK15HIP_vector_typeIfLj3EEPS2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
// set start node same as destination
int startNode;
scanf("%d",&startNode);
FILE* fgraph = fopen("graph.txt","r");
int N,edge_size;
fscanf(fgraph,"%d %d\n",&N,&edge_size);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*edge_size);
for(int i=0;i<edge_size;i++){
fscanf(fgraph,"%d",&H_edges[i]);
}
for(int i=0;i<N;i++){
fscanf(fgraph,"%d",&H_offset[i]);
}
fclose(fgraph);
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
cudaMalloc(&D_offset,sizeof(int)*N);
cudaMalloc(&D_visited,sizeof(int)*N);
cudaMalloc(&D_edges,sizeof(int)*edge_size);
cudaMalloc(&D_current_node1,sizeof(int)*edge_size);
cudaMalloc(&D_c_size1,sizeof(int));
cudaMalloc(&D_current_node2,sizeof(int)*edge_size);
cudaMalloc(&D_c_size2,sizeof(int));
cudaMemcpy(D_offset,H_offset,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_edges,H_edges,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_visited,H_visited,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size1,a1,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
int i=1;
cudaEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
cudaMemcpy(H_c_size,D_c_size2, sizeof(int),cudaMemcpyDeviceToHost);
// reset the index
cudaMemcpy(D_c_size1,a0,sizeof(int),cudaMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
cudaMemcpy(H_c_size,D_c_size1, sizeof(int),cudaMemcpyDeviceToHost);
//reset index
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
}
i++;
}
cudaEventRecord(stop);
cudaMemcpy(H_visited,D_visited, sizeof(int)*N,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
FILE* fptr = fopen("Hx.txt","w");
int count_unreachable = 0;
int farthest_val = 0;
int farthest_node = 0;
for(int i=0;i<N;i++){
if(H_visited[i]==-1)
count_unreachable++;
if(H_visited[i]>=farthest_val){
farthest_val = H_visited[i];
farthest_node = i;
}
fprintf(fptr,"%d ",H_visited[i]);
}
fclose(fptr);
printf("unreachable %d , %f\n",count_unreachable,count_unreachable/(N*1.0));
printf("farthest node: %d val: %d\n",farthest_node,farthest_val);
return 0;
}
|
code for sm_80
Function : _Z3BFSPiS_S_S_iiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0080*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R2, R5, R4, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x000fcc00078e0204 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff007624 */
/* 0x000fe200078e00ff */
/*00f0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0100*/ ISETP.NE.AND P0, PT, R3.reuse, UR4, PT ; /* 0x0000000403007c0c */
/* 0x044fe2000bf05270 */
/*0110*/ IMAD.WIDE R6, R3, R4, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0204 */
/*0120*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000eae000c1e1900 */
/*0130*/ @P0 LDG.E R0, [R6.64+0x4] ; /* 0x0000040606000981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GT.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x004fda0003f04270 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.IADD R5, R0, 0x1, -R9 ; /* 0x0000000100057824 */
/* 0x000fe200078e0a09 */
/*0170*/ SHF.R.S32.HI R6, RZ, 0x1f, R3 ; /* 0x0000001fff067819 */
/* 0x000fe20000011403 */
/*0180*/ BSSY B0, 0x420 ; /* 0x0000029000007945 */
/* 0x000fe20003800000 */
/*0190*/ LEA R2, P1, R3, c[0x0][0x198], 0x2 ; /* 0x0000660003027a11 */
/* 0x000fe400078210ff */
/*01a0*/ LOP3.LUT P0, R8, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305087812 */
/* 0x000fe2000780c0ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*01c0*/ LEA.HI.X R3, R3, c[0x0][0x19c], R6, 0x2, P1 ; /* 0x0000670003037a11 */
/* 0x000fd600008f1406 */
/*01d0*/ @!P0 BRA 0x410 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.WIDE R10, R9, R4, c[0x0][0x168] ; /* 0x00005a00090a7625 */
/* 0x000fc800078e0204 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0009 */
/*0200*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x001ea2000c1e1900 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R6, R21, R4, c[0x0][0x198] ; /* 0x0000660015067625 */
/* 0x004fca00078e0204 */
/*0230*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0250*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0260*/ BSSY B1, 0x3e0 ; /* 0x0000017000017945 */
/* 0x000fe20003800000 */
/*0270*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007f3e0ff */
/*0280*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0290*/ ISETP.GT.AND P2, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x004fda0003f44270 */
/*02a0*/ @P2 BRA 0x3d0 ; /* 0x0000012000002947 */
/* 0x000fea0003800000 */
/*02b0*/ LDG.E R12, [R2.64] ; /* 0x00000006020c7981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*02d0*/ FLO.U32 R16, UR4 ; /* 0x0000000400107d00 */
/* 0x000e2200080e0000 */
/*02e0*/ S2R R13, SR_LANEID ; /* 0x00000000000d7919 */
/* 0x000e2e0000000000 */
/*02f0*/ POPC R19, UR4 ; /* 0x0000000400137d09 */
/* 0x000e620008000000 */
/*0300*/ ISETP.EQ.U32.AND P2, PT, R16, R13, PT ; /* 0x0000000d1000720c */
/* 0x001fe20003f42070 */
/*0310*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0d7624 */
/* 0x000fe200078e00ff */
/*0320*/ IADD3 R17, R12, 0x1, RZ ; /* 0x000000010c117810 */
/* 0x004fe20007ffe0ff */
/*0330*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0c7624 */
/* 0x000fc800078e00ff */
/*0340*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x000fec000c101906 */
/*0350*/ @P2 ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R19 ; /* 0x000000130c0d29a8 */
/* 0x002ea800081ee1c6 */
/*0360*/ S2R R14, SR_LTMASK ; /* 0x00000000000e7919 */
/* 0x000e240000003900 */
/*0370*/ LOP3.LUT R18, R14, UR4, RZ, 0xc0, !PT ; /* 0x000000040e127c12 */
/* 0x001fcc000f8ec0ff */
/*0380*/ POPC R18, R18 ; /* 0x0000001200127309 */
/* 0x000e220000000000 */
/*0390*/ SHFL.IDX PT, R15, R13, R16, 0x1f ; /* 0x00001f100d0f7589 */
/* 0x004e2400000e0000 */
/*03a0*/ IADD3 R15, R15, R18, RZ ; /* 0x000000120f0f7210 */
/* 0x001fca0007ffe0ff */
/*03b0*/ IMAD.WIDE R14, R15, R4, c[0x0][0x188] ; /* 0x000062000f0e7625 */
/* 0x000fca00078e0204 */
/*03c0*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0001e4000c101906 */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*03f0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e060b */
/*0400*/ @P0 BRA 0x200 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ LOP3.LUT R7, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff077212 */
/* 0x000fca00078e33ff */
/*0430*/ IMAD.IADD R7, R7, 0x1, R0 ; /* 0x0000000107077824 */
/* 0x000fca00078e0200 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fda0003f06070 */
/*0450*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0460*/ IMAD.WIDE R8, R5, R4, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x000fc800078e0204 */
/*0470*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff067624 */
/* 0x000fe400078e00ff */
/*0480*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff077624 */
/* 0x000fe400078e00ff */
/*0490*/ LDG.E R19, [R8.64] ; /* 0x0000000608137981 */
/* 0x001ea2000c1e1900 */
/*04a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*04b0*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*04c0*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*04e0*/ BSSY B0, 0x620 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*04f0*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0500*/ @P0 BRA 0x610 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0510*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0520*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0530*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x001e2200080e0000 */
/*0540*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*0550*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*0560*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*0570*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*0580*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0590*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*05a0*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*05b0*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*05c0*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*05d0*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*05e0*/ IADD3 R11, R11, R16, RZ ; /* 0x000000100b0b7210 */
/* 0x001fca0007ffe0ff */
/*05f0*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0600*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040608137981 */
/* 0x001ea4000c1e1900 */
/*0630*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*0640*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*0650*/ BSSY B0, 0x790 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0660*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0670*/ @P0 BRA 0x780 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0680*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0690*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*06a0*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*06b0*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*06c0*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*06d0*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*06e0*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*06f0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0700*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*0710*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0720*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*0730*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*0740*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*0750*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*0760*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0770*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R19, [R8.64+0x8] ; /* 0x0000080608137981 */
/* 0x001ea4000c1e1900 */
/*07a0*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*07b0*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*07c0*/ BSSY B0, 0x900 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*07d0*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*07e0*/ @P0 BRA 0x8f0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*07f0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0800*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0810*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*0820*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*0830*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*0840*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*0850*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*0860*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0870*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*0880*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0890*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*08a0*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*08b0*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*08c0*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*08d0*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*08e0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*08f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0900*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0608137981 */
/* 0x001ea4000c1e1900 */
/*0910*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*0920*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*0930*/ BSSY B0, 0xa70 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0940*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0950*/ @P0 BRA 0xa60 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0960*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0970*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0980*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*0990*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*09a0*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*09b0*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*09c0*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*09d0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*09e0*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*09f0*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0a00*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*0a10*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*0a20*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*0a30*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*0a40*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0a50*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0a60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a70*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007f3e0ff */
/*0a90*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fc60003f06270 */
/*0aa0*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fd400008e0609 */
/*0ab0*/ @!P0 BRA 0x490 ; /* 0xfffff9d000008947 */
/* 0x000fea000383ffff */
/*0ac0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
// set start node same as destination
int startNode;
scanf("%d",&startNode);
FILE* fgraph = fopen("graph.txt","r");
int N,edge_size;
fscanf(fgraph,"%d %d\n",&N,&edge_size);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*edge_size);
for(int i=0;i<edge_size;i++){
fscanf(fgraph,"%d",&H_edges[i]);
}
for(int i=0;i<N;i++){
fscanf(fgraph,"%d",&H_offset[i]);
}
fclose(fgraph);
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
cudaMalloc(&D_offset,sizeof(int)*N);
cudaMalloc(&D_visited,sizeof(int)*N);
cudaMalloc(&D_edges,sizeof(int)*edge_size);
cudaMalloc(&D_current_node1,sizeof(int)*edge_size);
cudaMalloc(&D_c_size1,sizeof(int));
cudaMalloc(&D_current_node2,sizeof(int)*edge_size);
cudaMalloc(&D_c_size2,sizeof(int));
cudaMemcpy(D_offset,H_offset,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_edges,H_edges,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_visited,H_visited,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size1,a1,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
int i=1;
cudaEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
cudaMemcpy(H_c_size,D_c_size2, sizeof(int),cudaMemcpyDeviceToHost);
// reset the index
cudaMemcpy(D_c_size1,a0,sizeof(int),cudaMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
cudaMemcpy(H_c_size,D_c_size1, sizeof(int),cudaMemcpyDeviceToHost);
//reset index
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
}
i++;
}
cudaEventRecord(stop);
cudaMemcpy(H_visited,D_visited, sizeof(int)*N,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
FILE* fptr = fopen("Hx.txt","w");
int count_unreachable = 0;
int farthest_val = 0;
int farthest_node = 0;
for(int i=0;i<N;i++){
if(H_visited[i]==-1)
count_unreachable++;
if(H_visited[i]>=farthest_val){
farthest_val = H_visited[i];
farthest_node = i;
}
fprintf(fptr,"%d ",H_visited[i]);
}
fclose(fptr);
printf("unreachable %d , %f\n",count_unreachable,count_unreachable/(N*1.0));
printf("farthest node: %d val: %d\n",farthest_node,farthest_val);
return 0;
}
|
.file "tmpxft_00007c4f_00000000-6_bfs_hx.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
.type _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_, @function
_Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z3BFSPiS_S_S_iiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_, .-_Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
.globl _Z3BFSPiS_S_S_iiS_S_S_
.type _Z3BFSPiS_S_S_iiS_S_S_, @function
_Z3BFSPiS_S_S_iiS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3BFSPiS_S_S_iiS_S_S_, .-_Z3BFSPiS_S_S_iiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "r"
.LC2:
.string "graph.txt"
.LC3:
.string "%d %d\n"
.LC4:
.string "completed input\n"
.LC6:
.string "max-level: %d\n"
.LC7:
.string "time: %f\n"
.LC8:
.string "w"
.LC9:
.string "Hx.txt"
.LC10:
.string "%d "
.LC11:
.string "unreachable %d , %f\n"
.LC12:
.string "farthest node: %d val: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %r12
leaq 36(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movslq 32(%rsp), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r13
movl 36(%rsp), %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
jle .L12
movq %rax, %rbp
movl $0, %ebx
leaq .LC0(%rip), %r14
.L13:
movq %rbp, %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 36(%rsp)
jg .L13
.L12:
cmpl $0, 32(%rsp)
jle .L14
movq %r13, %rbp
movl $0, %ebx
leaq .LC0(%rip), %r14
.L15:
movq %rbp, %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 32(%rsp)
jg .L15
.L14:
movq %r12, %rdi
call fclose@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 36(%rsp), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movl 28(%rsp), %r15d
movl %r15d, (%rax)
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $1, (%rax)
movslq 32(%rsp), %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rcx
movq %rbp, %rdx
movl $-1, %esi
movq %rax, %rdi
call __memset_chk@PLT
movslq %r15d, %r15
movl $0, (%r14,%r15,4)
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, (%rax)
movl $4, %edi
call malloc@PLT
movq %rax, %r15
movl $1, (%rax)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movslq 32(%rsp), %rsi
salq $2, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movslq 32(%rsp), %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq 36(%rsp), %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movslq 36(%rsp), %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movslq 36(%rsp), %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movslq 36(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movslq 36(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r15, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl (%rbx), %eax
testl %eax, %eax
jle .L16
movl $1, %r12d
jmp .L21
.L38:
movl $512, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl %edx, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L18:
movl $2, %ecx
movl $4, %edx
movq 104(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L19
.L37:
subq $8, %rsp
.cfi_def_cfa_offset 216
pushq 80(%rsp)
.cfi_def_cfa_offset 224
pushq 120(%rsp)
.cfi_def_cfa_offset 232
pushq 120(%rsp)
.cfi_def_cfa_offset 240
movl 68(%rsp), %r9d
movl 64(%rsp), %r8d
movq 120(%rsp), %rcx
movq 112(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 208
jmp .L18
.L20:
movl $2, %ecx
movl $4, %edx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
.L19:
addl $1, %r12d
movl (%rbx), %eax
testl %eax, %eax
jle .L16
.L21:
leal 1022(%rax), %edx
addl $511, %eax
cmovs %edx, %eax
sarl $9, %eax
movl %eax, %edx
movl %r12d, %ecx
shrl $31, %ecx
leal (%r12,%rcx), %eax
andl $1, %eax
subl %ecx, %eax
cmpl $1, %eax
je .L38
movl $512, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl %edx, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L20
subq $8, %rsp
.cfi_def_cfa_offset 216
pushq 80(%rsp)
.cfi_def_cfa_offset 224
pushq 104(%rsp)
.cfi_def_cfa_offset 232
pushq 104(%rsp)
.cfi_def_cfa_offset 240
movl 68(%rsp), %r9d
movl 64(%rsp), %r8d
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 208
jmp .L20
.L16:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 72(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 124(%rsp)
leaq 124(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 32(%rsp), %edx
testl %edx, %edx
jle .L29
movq %r14, %rax
movslq %edx, %rdx
leaq (%r14,%rdx,4), %rsi
movl $0, %edx
.L23:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L23
.L22:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 124(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
leaq .LC9(%rip), %rdi
call fopen@PLT
movq %rax, %r15
cmpl $0, 32(%rsp)
jle .L30
movl $0, %ebx
movl $0, %r13d
movl $0, %ebp
movl $0, %r12d
.L27:
movl (%r14,%rbx,4), %ecx
cmpl $-1, %ecx
sete %al
movzbl %al, %eax
addl %eax, %r12d
cmpl %ebp, %ecx
cmovge %ebx, %r13d
cmovge %ecx, %ebp
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r15, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, 32(%rsp)
jg .L27
.L24:
movq %r15, %rdi
call fclose@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 32(%rsp), %xmm1
divsd %xmm1, %xmm0
movl %r12d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebp, %ecx
movl %r13d, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $0, %edx
jmp .L22
.L30:
movl $0, %r13d
movl $0, %ebp
movl $0, %r12d
jmp .L24
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z3BFSPiS_S_S_iiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z3BFSPiS_S_S_iiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
// set start node same as destination
int startNode;
scanf("%d",&startNode);
FILE* fgraph = fopen("graph.txt","r");
int N,edge_size;
fscanf(fgraph,"%d %d\n",&N,&edge_size);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*edge_size);
for(int i=0;i<edge_size;i++){
fscanf(fgraph,"%d",&H_edges[i]);
}
for(int i=0;i<N;i++){
fscanf(fgraph,"%d",&H_offset[i]);
}
fclose(fgraph);
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
cudaMalloc(&D_offset,sizeof(int)*N);
cudaMalloc(&D_visited,sizeof(int)*N);
cudaMalloc(&D_edges,sizeof(int)*edge_size);
cudaMalloc(&D_current_node1,sizeof(int)*edge_size);
cudaMalloc(&D_c_size1,sizeof(int));
cudaMalloc(&D_current_node2,sizeof(int)*edge_size);
cudaMalloc(&D_c_size2,sizeof(int));
cudaMemcpy(D_offset,H_offset,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_edges,H_edges,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,cudaMemcpyHostToDevice);
cudaMemcpy(D_visited,H_visited,sizeof(int)*N,cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size1,a1,sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
int i=1;
cudaEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
cudaMemcpy(H_c_size,D_c_size2, sizeof(int),cudaMemcpyDeviceToHost);
// reset the index
cudaMemcpy(D_c_size1,a0,sizeof(int),cudaMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
cudaMemcpy(H_c_size,D_c_size1, sizeof(int),cudaMemcpyDeviceToHost);
//reset index
cudaMemcpy(D_c_size2,a0,sizeof(int),cudaMemcpyHostToDevice);
}
i++;
}
cudaEventRecord(stop);
cudaMemcpy(H_visited,D_visited, sizeof(int)*N,cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
FILE* fptr = fopen("Hx.txt","w");
int count_unreachable = 0;
int farthest_val = 0;
int farthest_node = 0;
for(int i=0;i<N;i++){
if(H_visited[i]==-1)
count_unreachable++;
if(H_visited[i]>=farthest_val){
farthest_val = H_visited[i];
farthest_node = i;
}
fprintf(fptr,"%d ",H_visited[i]);
}
fclose(fptr);
printf("unreachable %d , %f\n",count_unreachable,count_unreachable/(N*1.0));
printf("farthest node: %d val: %d\n",farthest_node,farthest_val);
return 0;
}
|
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
// set start node same as destination
int startNode;
scanf("%d",&startNode);
FILE* fgraph = fopen("graph.txt","r");
int N,edge_size;
fscanf(fgraph,"%d %d\n",&N,&edge_size);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*edge_size);
for(int i=0;i<edge_size;i++){
fscanf(fgraph,"%d",&H_edges[i]);
}
for(int i=0;i<N;i++){
fscanf(fgraph,"%d",&H_offset[i]);
}
fclose(fgraph);
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
hipMalloc(&D_offset,sizeof(int)*N);
hipMalloc(&D_visited,sizeof(int)*N);
hipMalloc(&D_edges,sizeof(int)*edge_size);
hipMalloc(&D_current_node1,sizeof(int)*edge_size);
hipMalloc(&D_c_size1,sizeof(int));
hipMalloc(&D_current_node2,sizeof(int)*edge_size);
hipMalloc(&D_c_size2,sizeof(int));
hipMemcpy(D_offset,H_offset,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_edges,H_edges,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_visited,H_visited,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_c_size1,a1,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
int i=1;
hipEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
hipMemcpy(H_c_size,D_c_size2, sizeof(int),hipMemcpyDeviceToHost);
// reset the index
hipMemcpy(D_c_size1,a0,sizeof(int),hipMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
hipMemcpy(H_c_size,D_c_size1, sizeof(int),hipMemcpyDeviceToHost);
//reset index
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
}
i++;
}
hipEventRecord(stop);
hipMemcpy(H_visited,D_visited, sizeof(int)*N,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
FILE* fptr = fopen("Hx.txt","w");
int count_unreachable = 0;
int farthest_val = 0;
int farthest_node = 0;
for(int i=0;i<N;i++){
if(H_visited[i]==-1)
count_unreachable++;
if(H_visited[i]>=farthest_val){
farthest_val = H_visited[i];
farthest_node = i;
}
fprintf(fptr,"%d ",H_visited[i]);
}
fclose(fptr);
printf("unreachable %d , %f\n",count_unreachable,count_unreachable/(N*1.0));
printf("farthest node: %d val: %d\n",farthest_node,farthest_val);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
// set start node same as destination
int startNode;
scanf("%d",&startNode);
FILE* fgraph = fopen("graph.txt","r");
int N,edge_size;
fscanf(fgraph,"%d %d\n",&N,&edge_size);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*edge_size);
for(int i=0;i<edge_size;i++){
fscanf(fgraph,"%d",&H_edges[i]);
}
for(int i=0;i<N;i++){
fscanf(fgraph,"%d",&H_offset[i]);
}
fclose(fgraph);
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
hipMalloc(&D_offset,sizeof(int)*N);
hipMalloc(&D_visited,sizeof(int)*N);
hipMalloc(&D_edges,sizeof(int)*edge_size);
hipMalloc(&D_current_node1,sizeof(int)*edge_size);
hipMalloc(&D_c_size1,sizeof(int));
hipMalloc(&D_current_node2,sizeof(int)*edge_size);
hipMalloc(&D_c_size2,sizeof(int));
hipMemcpy(D_offset,H_offset,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_edges,H_edges,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_visited,H_visited,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_c_size1,a1,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
int i=1;
hipEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
hipMemcpy(H_c_size,D_c_size2, sizeof(int),hipMemcpyDeviceToHost);
// reset the index
hipMemcpy(D_c_size1,a0,sizeof(int),hipMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
hipMemcpy(H_c_size,D_c_size1, sizeof(int),hipMemcpyDeviceToHost);
//reset index
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
}
i++;
}
hipEventRecord(stop);
hipMemcpy(H_visited,D_visited, sizeof(int)*N,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
FILE* fptr = fopen("Hx.txt","w");
int count_unreachable = 0;
int farthest_val = 0;
int farthest_node = 0;
for(int i=0;i<N;i++){
if(H_visited[i]==-1)
count_unreachable++;
if(H_visited[i]>=farthest_val){
farthest_val = H_visited[i];
farthest_node = i;
}
fprintf(fptr,"%d ",H_visited[i]);
}
fclose(fptr);
printf("unreachable %d , %f\n",count_unreachable,count_unreachable/(N*1.0));
printf("farthest node: %d val: %d\n",farthest_node,farthest_val);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3BFSPiS_S_S_iiS_S_S_
.globl _Z3BFSPiS_S_S_iiS_S_S_
.p2align 8
.type _Z3BFSPiS_S_S_iiS_S_S_,@function
_Z3BFSPiS_S_S_iiS_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[4:5], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v8, s5
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_add_i32 s2, s4, -1
v_cmp_ne_u32_e32 vcc_lo, s2, v2
global_load_b32 v0, v[4:5], off
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
global_load_b32 v8, v[4:5], off offset:4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_10
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x28
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_mov_b32_e32 v9, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
s_branch .LBB0_7
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s8, v10
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_store_b32 v[6:7], v5, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v3, s0, v3, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v8
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_10
.LBB0_7:
global_load_b32 v5, v[3:4], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v10, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e32 0, v10
s_cbranch_execz .LBB0_6
global_load_b32 v11, v[1:2], off
s_mov_b32 s8, exec_lo
s_mov_b32 s9, exec_lo
v_mbcnt_lo_u32_b32 v10, s8, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, 1, v11
global_store_b32 v[6:7], v11, off
v_cmpx_eq_u32_e32 0, v10
s_cbranch_execz .LBB0_5
s_bcnt1_i32_b32 s8, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v6, s8
global_atomic_add_u32 v6, v9, v6, s[6:7] glc
s_branch .LBB0_5
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3BFSPiS_S_S_iiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3BFSPiS_S_S_iiS_S_S_, .Lfunc_end0-_Z3BFSPiS_S_S_iiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3BFSPiS_S_S_iiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3BFSPiS_S_S_iiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <string.h>
#include <limits.h>
#include <stdbool.h>
#define MAX_EDGE 100000000
__global__ void BFS(int* off,int* edge,int* current,int* size,int N,int E,int* c_arr,int* c_size,int* dist){
int id = blockIdx.x*blockDim.x+threadIdx.x;
if(id < *size){
// printf("inside kernel %d %d\n",id,*size);
int node = current[id];
//extend this node
int start = off[node];
int end = E;
if(node!=N-1)
end = off[node+1];
while(start<end){
// add in list atomically in c_arr
int child = edge[start];
// printf("c %d \n",child);
if ( dist[child] < 0){
dist[child] = dist[node] + 1;
int index = atomicAdd(c_size,1);
c_arr[index]= child;
}
start++;
}
// printf("s %d\n",*c_size);
}
}
int main(){
// set start node same as destination
int startNode;
scanf("%d",&startNode);
FILE* fgraph = fopen("graph.txt","r");
int N,edge_size;
fscanf(fgraph,"%d %d\n",&N,&edge_size);
int* H_offset = (int*)malloc(sizeof(int)*N);
int* H_edges = (int*)malloc(sizeof(int)*edge_size);
for(int i=0;i<edge_size;i++){
fscanf(fgraph,"%d",&H_edges[i]);
}
for(int i=0;i<N;i++){
fscanf(fgraph,"%d",&H_offset[i]);
}
fclose(fgraph);
printf("completed input\n");
int* H_current_node = (int*)malloc(sizeof(int)*edge_size);
H_current_node[0]=startNode;
int* H_c_size = (int*)malloc(sizeof(int));
*H_c_size = 1;
int* H_visited = (int*)malloc(sizeof(int)*N);
memset(H_visited,-1,sizeof(int)*N);
H_visited[startNode]=0;
int* a0 = (int*)malloc(sizeof(int));
*a0=0;
int* a1 = (int*)malloc(sizeof(int));
*a1=1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int* D_offset;
int* D_edges;
int* D_visited;
int* D_current_node1;
int* D_c_size1;
int* D_current_node2;
int* D_c_size2;
hipMalloc(&D_offset,sizeof(int)*N);
hipMalloc(&D_visited,sizeof(int)*N);
hipMalloc(&D_edges,sizeof(int)*edge_size);
hipMalloc(&D_current_node1,sizeof(int)*edge_size);
hipMalloc(&D_c_size1,sizeof(int));
hipMalloc(&D_current_node2,sizeof(int)*edge_size);
hipMalloc(&D_c_size2,sizeof(int));
hipMemcpy(D_offset,H_offset,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_edges,H_edges,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_current_node1,H_current_node,sizeof(int)*edge_size,hipMemcpyHostToDevice);
hipMemcpy(D_visited,H_visited,sizeof(int)*N,hipMemcpyHostToDevice);
hipMemcpy(D_c_size1,a1,sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
int i=1;
hipEventRecord(start);
while(*H_c_size>0){
int numThreads = 512;
int numBlocks = (*H_c_size+numThreads-1)/numThreads;
if(i%2==1){
//use array 1
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node1,D_c_size1,N,edge_size,D_current_node2,D_c_size2,D_visited);
hipMemcpy(H_c_size,D_c_size2, sizeof(int),hipMemcpyDeviceToHost);
// reset the index
hipMemcpy(D_c_size1,a0,sizeof(int),hipMemcpyHostToDevice);
}
else{
//use array 2
BFS<<<numBlocks,numThreads>>>(D_offset,D_edges,D_current_node2,D_c_size2,N,edge_size,D_current_node1,D_c_size1,D_visited);
hipMemcpy(H_c_size,D_c_size1, sizeof(int),hipMemcpyDeviceToHost);
//reset index
hipMemcpy(D_c_size2,a0,sizeof(int),hipMemcpyHostToDevice);
}
i++;
}
hipEventRecord(stop);
hipMemcpy(H_visited,D_visited, sizeof(int)*N,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
int max_level = 0;
for(int i=0;i<N;i++){
if(H_visited[i]>max_level){
max_level = H_visited[i];
}
// printf("%d, %d\n",i,H_visited[i]);
}
printf("max-level: %d\n",max_level);
printf("time: %f\n",milliseconds);
FILE* fptr = fopen("Hx.txt","w");
int count_unreachable = 0;
int farthest_val = 0;
int farthest_node = 0;
for(int i=0;i<N;i++){
if(H_visited[i]==-1)
count_unreachable++;
if(H_visited[i]>=farthest_val){
farthest_val = H_visited[i];
farthest_node = i;
}
fprintf(fptr,"%d ",H_visited[i]);
}
fclose(fptr);
printf("unreachable %d , %f\n",count_unreachable,count_unreachable/(N*1.0));
printf("farthest node: %d val: %d\n",farthest_node,farthest_val);
return 0;
}
|
.text
.file "bfs_hx.hip"
.globl _Z18__device_stub__BFSPiS_S_S_iiS_S_S_ # -- Begin function _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.p2align 4, 0x90
.type _Z18__device_stub__BFSPiS_S_S_iiS_S_S_,@function
_Z18__device_stub__BFSPiS_S_S_iiS_S_S_: # @_Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z18__device_stub__BFSPiS_S_S_iiS_S_S_, .Lfunc_end0-_Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 188(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %rbx
leaq 8(%rsp), %rdx
leaq 12(%rsp), %rcx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq 8(%rsp), %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r13
movslq 12(%rsp), %r14
leaq (,%r14,4), %rdi
callq malloc
movq %rax, %r12
testq %r14, %r14
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r12, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r15
movslq 12(%rsp), %rax
addq $4, %r14
cmpq %rax, %r15
jl .LBB1_2
.LBB1_3: # %.preheader
movq %r12, 288(%rsp) # 8-byte Spill
cmpl $0, 8(%rsp)
jle .LBB1_6
# %bb.4: # %.lr.ph106.preheader
movq %r13, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph106
# =>This Inner Loop Header: Depth=1
movl $.L.str, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r15
movslq 8(%rsp), %rax
addq $4, %r14
cmpq %rax, %r15
jl .LBB1_5
.LBB1_6: # %._crit_edge
movq %rbx, %rdi
callq fclose
movl $.Lstr, %edi
callq puts@PLT
movslq 12(%rsp), %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r12
movq %r13, 280(%rsp) # 8-byte Spill
movslq 188(%rsp), %r13
movl %r13d, (%rax)
movl $4, %edi
callq malloc
movq %rax, %r14
movl $1, (%rax)
movslq 8(%rsp), %r15
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movl $255, %esi
movq %r15, %rdx
callq memset@PLT
movl $0, (%rbx,%r13,4)
movl $4, %edi
callq malloc
movq %rax, %r15
movl $0, (%rax)
movl $4, %edi
callq malloc
movq %rax, %rbp
movl $1, (%rax)
leaq 200(%rsp), %rdi
callq hipEventCreate
leaq 72(%rsp), %rdi
callq hipEventCreate
movslq 8(%rsp), %rsi
shlq $2, %rsi
leaq 64(%rsp), %rdi
callq hipMalloc
movslq 8(%rsp), %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 192(%rsp), %rdi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 64(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movl $1, %r13d
movq 280(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq 288(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4, %edx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 200(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movl (%r14), %edi
testl %edi, %edi
jle .LBB1_16
# %bb.7: # %.lr.ph109
movabsq $4294967296, %rax # imm = 0x100000000
leaq 512(%rax), %r12
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_8 Depth=1
testl %eax, %eax
je .LBB1_13
.LBB1_14: # in Loop: Header=BB1_8 Depth=1
movq 32(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 24(%rsp), %rax
.LBB1_15: # in Loop: Header=BB1_8 Depth=1
movq (%rax), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
incl %r13d
movl (%r14), %edi
testl %edi, %edi
jle .LBB1_16
.LBB1_8: # =>This Inner Loop Header: Depth=1
addl $511, %edi # imm = 0x1FF
shrl $9, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, %r13b
je .LBB1_12
# %bb.9: # in Loop: Header=BB1_8 Depth=1
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_8 Depth=1
movq 64(%rsp), %rax
movq %rax, 176(%rsp)
movq 56(%rsp), %rax
movq %rax, 168(%rsp)
movq 48(%rsp), %rax
movq %rax, 160(%rsp)
movq 32(%rsp), %rax
movq %rax, 152(%rsp)
movl 8(%rsp), %eax
movl %eax, 20(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 144(%rsp)
movq 24(%rsp), %rax
movq %rax, 136(%rsp)
movq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 176(%rsp), %rax
movq %rax, 208(%rsp)
leaq 168(%rsp), %rax
movq %rax, 216(%rsp)
leaq 160(%rsp), %rax
movq %rax, 224(%rsp)
leaq 152(%rsp), %rax
movq %rax, 232(%rsp)
leaq 20(%rsp), %rax
movq %rax, 240(%rsp)
leaq 16(%rsp), %rax
movq %rax, 248(%rsp)
leaq 144(%rsp), %rax
movq %rax, 256(%rsp)
leaq 136(%rsp), %rax
movq %rax, 264(%rsp)
leaq 128(%rsp), %rax
movq %rax, 272(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
leaq 208(%rsp), %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11: # in Loop: Header=BB1_8 Depth=1
movq 24(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 32(%rsp), %rax
jmp .LBB1_15
.LBB1_13: # in Loop: Header=BB1_8 Depth=1
movq 64(%rsp), %rax
movq %rax, 176(%rsp)
movq 56(%rsp), %rax
movq %rax, 168(%rsp)
movq 192(%rsp), %rax
movq %rax, 160(%rsp)
movq 24(%rsp), %rax
movq %rax, 152(%rsp)
movl 8(%rsp), %eax
movl %eax, 20(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movq 32(%rsp), %rax
movq %rax, 136(%rsp)
movq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 176(%rsp), %rax
movq %rax, 208(%rsp)
leaq 168(%rsp), %rax
movq %rax, 216(%rsp)
leaq 160(%rsp), %rax
movq %rax, 224(%rsp)
leaq 152(%rsp), %rax
movq %rax, 232(%rsp)
leaq 20(%rsp), %rax
movq %rax, 240(%rsp)
leaq 16(%rsp), %rax
movq %rax, 248(%rsp)
leaq 144(%rsp), %rax
movq %rax, 256(%rsp)
leaq 136(%rsp), %rax
movq %rax, 264(%rsp)
leaq 128(%rsp), %rax
movq %rax, 272(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
leaq 208(%rsp), %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_14
.LBB1_16: # %._crit_edge110
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rsi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
callq hipEventSynchronize
movl $0, 208(%rsp)
movq 200(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 208(%rsp), %rdi
callq hipEventElapsedTime
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_19
# %bb.17: # %.lr.ph114.preheader
xorl %ecx, %ecx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_18: # %.lr.ph114
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rcx,4), %edx
cmpl %ebp, %edx
cmovgl %edx, %ebp
incq %rcx
cmpq %rcx, %rax
jne .LBB1_18
.LBB1_19: # %._crit_edge115
xorl %r14d, %r14d
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movss 208(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.7, %edi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r12
cmpl $0, 8(%rsp)
movl $0, %ebp
movl $0, %r15d
jle .LBB1_22
# %bb.20: # %.lr.ph121.preheader
xorl %r13d, %r13d
xorl %r15d, %r15d
xorl %ebp, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_21: # %.lr.ph121
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r13,4), %edx
xorl %eax, %eax
cmpl $-1, %edx
sete %al
addl %eax, %r14d
cmpl %ebp, %edx
cmovgl %edx, %ebp
cmovgel %r13d, %r15d
movl $.L.str.9, %esi
movq %r12, %rdi
xorl %eax, %eax
callq fprintf
incq %r13
movslq 8(%rsp), %rax
cmpq %rax, %r13
jl .LBB1_21
.LBB1_22: # %._crit_edge122
movq %r12, %rdi
callq fclose
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
cvtsi2sdl 8(%rsp), %xmm1
divsd %xmm1, %xmm0
movl $.L.str.10, %edi
movl %r14d, %esi
movb $1, %al
callq printf
movl $.L.str.11, %edi
movl %r15d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3BFSPiS_S_S_iiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3BFSPiS_S_S_iiS_S_S_,@object # @_Z3BFSPiS_S_S_iiS_S_S_
.section .rodata,"a",@progbits
.globl _Z3BFSPiS_S_S_iiS_S_S_
.p2align 3, 0x0
_Z3BFSPiS_S_S_iiS_S_S_:
.quad _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.size _Z3BFSPiS_S_S_iiS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "graph.txt"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d\n"
.size .L.str.3, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "max-level: %d\n"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "time: %f\n"
.size .L.str.6, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Hx.txt"
.size .L.str.7, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "w"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d "
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "unreachable %d , %f\n"
.size .L.str.10, 21
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "farthest node: %d val: %d\n"
.size .L.str.11, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3BFSPiS_S_S_iiS_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "completed input"
.size .Lstr, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3BFSPiS_S_S_iiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z3BFSPiS_S_S_iiS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0080*/ ISETP.GE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R2, R5, R4, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x000fcc00078e0204 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ ULDC UR4, c[0x0][0x180] ; /* 0x0000600000047ab9 */
/* 0x000fe20000000800 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff007624 */
/* 0x000fe200078e00ff */
/*00f0*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fcc000fffe03f */
/*0100*/ ISETP.NE.AND P0, PT, R3.reuse, UR4, PT ; /* 0x0000000403007c0c */
/* 0x044fe2000bf05270 */
/*0110*/ IMAD.WIDE R6, R3, R4, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0204 */
/*0120*/ LDG.E R9, [R6.64] ; /* 0x0000000606097981 */
/* 0x000eae000c1e1900 */
/*0130*/ @P0 LDG.E R0, [R6.64+0x4] ; /* 0x0000040606000981 */
/* 0x000ea4000c1e1900 */
/*0140*/ ISETP.GT.AND P0, PT, R0, R9, PT ; /* 0x000000090000720c */
/* 0x004fda0003f04270 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.IADD R5, R0, 0x1, -R9 ; /* 0x0000000100057824 */
/* 0x000fe200078e0a09 */
/*0170*/ SHF.R.S32.HI R6, RZ, 0x1f, R3 ; /* 0x0000001fff067819 */
/* 0x000fe20000011403 */
/*0180*/ BSSY B0, 0x420 ; /* 0x0000029000007945 */
/* 0x000fe20003800000 */
/*0190*/ LEA R2, P1, R3, c[0x0][0x198], 0x2 ; /* 0x0000660003027a11 */
/* 0x000fe400078210ff */
/*01a0*/ LOP3.LUT P0, R8, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305087812 */
/* 0x000fe2000780c0ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*01c0*/ LEA.HI.X R3, R3, c[0x0][0x19c], R6, 0x2, P1 ; /* 0x0000670003037a11 */
/* 0x000fd600008f1406 */
/*01d0*/ @!P0 BRA 0x410 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.WIDE R10, R9, R4, c[0x0][0x168] ; /* 0x00005a00090a7625 */
/* 0x000fc800078e0204 */
/*01f0*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0009 */
/*0200*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x001ea2000c1e1900 */
/*0210*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R6, R21, R4, c[0x0][0x198] ; /* 0x0000660015067625 */
/* 0x004fca00078e0204 */
/*0230*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0250*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0260*/ BSSY B1, 0x3e0 ; /* 0x0000017000017945 */
/* 0x000fe20003800000 */
/*0270*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe40007f3e0ff */
/*0280*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*0290*/ ISETP.GT.AND P2, PT, R12, -0x1, PT ; /* 0xffffffff0c00780c */
/* 0x004fda0003f44270 */
/*02a0*/ @P2 BRA 0x3d0 ; /* 0x0000012000002947 */
/* 0x000fea0003800000 */
/*02b0*/ LDG.E R12, [R2.64] ; /* 0x00000006020c7981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*02d0*/ FLO.U32 R16, UR4 ; /* 0x0000000400107d00 */
/* 0x000e2200080e0000 */
/*02e0*/ S2R R13, SR_LANEID ; /* 0x00000000000d7919 */
/* 0x000e2e0000000000 */
/*02f0*/ POPC R19, UR4 ; /* 0x0000000400137d09 */
/* 0x000e620008000000 */
/*0300*/ ISETP.EQ.U32.AND P2, PT, R16, R13, PT ; /* 0x0000000d1000720c */
/* 0x001fe20003f42070 */
/*0310*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff0d7624 */
/* 0x000fe200078e00ff */
/*0320*/ IADD3 R17, R12, 0x1, RZ ; /* 0x000000010c117810 */
/* 0x004fe20007ffe0ff */
/*0330*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff0c7624 */
/* 0x000fc800078e00ff */
/*0340*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x000fec000c101906 */
/*0350*/ @P2 ATOMG.E.ADD.STRONG.GPU PT, R13, [R12.64], R19 ; /* 0x000000130c0d29a8 */
/* 0x002ea800081ee1c6 */
/*0360*/ S2R R14, SR_LTMASK ; /* 0x00000000000e7919 */
/* 0x000e240000003900 */
/*0370*/ LOP3.LUT R18, R14, UR4, RZ, 0xc0, !PT ; /* 0x000000040e127c12 */
/* 0x001fcc000f8ec0ff */
/*0380*/ POPC R18, R18 ; /* 0x0000001200127309 */
/* 0x000e220000000000 */
/*0390*/ SHFL.IDX PT, R15, R13, R16, 0x1f ; /* 0x00001f100d0f7589 */
/* 0x004e2400000e0000 */
/*03a0*/ IADD3 R15, R15, R18, RZ ; /* 0x000000120f0f7210 */
/* 0x001fca0007ffe0ff */
/*03b0*/ IMAD.WIDE R14, R15, R4, c[0x0][0x188] ; /* 0x000062000f0e7625 */
/* 0x000fca00078e0204 */
/*03c0*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0001e4000c101906 */
/*03d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03e0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*03f0*/ IMAD.X R11, RZ, RZ, R11, P1 ; /* 0x000000ffff0b7224 */
/* 0x000fe200008e060b */
/*0400*/ @P0 BRA 0x200 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0410*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0420*/ LOP3.LUT R7, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff077212 */
/* 0x000fca00078e33ff */
/*0430*/ IMAD.IADD R7, R7, 0x1, R0 ; /* 0x0000000107077824 */
/* 0x000fca00078e0200 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fda0003f06070 */
/*0450*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0460*/ IMAD.WIDE R8, R5, R4, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x000fc800078e0204 */
/*0470*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff067624 */
/* 0x000fe400078e00ff */
/*0480*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x194] ; /* 0x00006500ff077624 */
/* 0x000fe400078e00ff */
/*0490*/ LDG.E R19, [R8.64] ; /* 0x0000000608137981 */
/* 0x001ea2000c1e1900 */
/*04a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*04b0*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*04c0*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*04d0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*04e0*/ BSSY B0, 0x620 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*04f0*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0500*/ @P0 BRA 0x610 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0510*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0520*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0530*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x001e2200080e0000 */
/*0540*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*0550*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*0560*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*0570*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*0580*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0590*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*05a0*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*05b0*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*05c0*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*05d0*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*05e0*/ IADD3 R11, R11, R16, RZ ; /* 0x000000100b0b7210 */
/* 0x001fca0007ffe0ff */
/*05f0*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0600*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0610*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0620*/ LDG.E R19, [R8.64+0x4] ; /* 0x0000040608137981 */
/* 0x001ea4000c1e1900 */
/*0630*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*0640*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*0650*/ BSSY B0, 0x790 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0660*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0670*/ @P0 BRA 0x780 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0680*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0690*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*06a0*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*06b0*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*06c0*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*06d0*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*06e0*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*06f0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0700*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*0710*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0720*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*0730*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*0740*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*0750*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*0760*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0770*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0780*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0790*/ LDG.E R19, [R8.64+0x8] ; /* 0x0000080608137981 */
/* 0x001ea4000c1e1900 */
/*07a0*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*07b0*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*07c0*/ BSSY B0, 0x900 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*07d0*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*07e0*/ @P0 BRA 0x8f0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*07f0*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0800*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0810*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*0820*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*0830*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*0840*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*0850*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*0860*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*0870*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*0880*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0890*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*08a0*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*08b0*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*08c0*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*08d0*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*08e0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*08f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0900*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0608137981 */
/* 0x001ea4000c1e1900 */
/*0910*/ IMAD.WIDE R12, R19, R4, c[0x0][0x198] ; /* 0x00006600130c7625 */
/* 0x004fca00078e0204 */
/*0920*/ LDG.E R10, [R12.64] ; /* 0x000000060c0a7981 */
/* 0x000ea2000c1e1900 */
/*0930*/ BSSY B0, 0xa70 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0940*/ ISETP.GT.AND P0, PT, R10, -0x1, PT ; /* 0xffffffff0a00780c */
/* 0x004fda0003f04270 */
/*0950*/ @P0 BRA 0xa60 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0960*/ LDG.E R10, [R2.64] ; /* 0x00000006020a7981 */
/* 0x000ea2000c1e1900 */
/*0970*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0980*/ FLO.U32 R14, UR4 ; /* 0x00000004000e7d00 */
/* 0x000e2200080e0000 */
/*0990*/ S2R R11, SR_LANEID ; /* 0x00000000000b7919 */
/* 0x000e2e0000000000 */
/*09a0*/ POPC R17, UR4 ; /* 0x0000000400117d09 */
/* 0x000e620008000000 */
/*09b0*/ ISETP.EQ.U32.AND P0, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x001fc40003f02070 */
/*09c0*/ IADD3 R15, R10, 0x1, RZ ; /* 0x000000010a0f7810 */
/* 0x004fca0007ffe0ff */
/*09d0*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x000fec000c101906 */
/*09e0*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R17, [R6.64], R17 ; /* 0x00000011061109a8 */
/* 0x002ea800081ee1c6 */
/*09f0*/ S2R R16, SR_LTMASK ; /* 0x0000000000107919 */
/* 0x000e240000003900 */
/*0a00*/ LOP3.LUT R16, R16, UR4, RZ, 0xc0, !PT ; /* 0x0000000410107c12 */
/* 0x001fcc000f8ec0ff */
/*0a10*/ POPC R16, R16 ; /* 0x0000001000107309 */
/* 0x000e220000000000 */
/*0a20*/ SHFL.IDX PT, R11, R17, R14, 0x1f ; /* 0x00001f0e110b7589 */
/* 0x004e2400000e0000 */
/*0a30*/ IMAD.IADD R11, R11, 0x1, R16 ; /* 0x000000010b0b7824 */
/* 0x001fc800078e0210 */
/*0a40*/ IMAD.WIDE R10, R11, R4, c[0x0][0x188] ; /* 0x000062000b0a7625 */
/* 0x000fca00078e0204 */
/*0a50*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0001e4000c101906 */
/*0a60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a70*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ IADD3 R8, P1, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe40007f3e0ff */
/*0a90*/ ISETP.GE.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fc60003f06270 */
/*0aa0*/ IMAD.X R9, RZ, RZ, R9, P1 ; /* 0x000000ffff097224 */
/* 0x000fd400008e0609 */
/*0ab0*/ @!P0 BRA 0x490 ; /* 0xfffff9d000008947 */
/* 0x000fea000383ffff */
/*0ac0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3BFSPiS_S_S_iiS_S_S_
.globl _Z3BFSPiS_S_S_iiS_S_S_
.p2align 8
.type _Z3BFSPiS_S_S_iiS_S_S_,@function
_Z3BFSPiS_S_S_iiS_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s4, s[0:1], 0x4c
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[4:5], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v8, s5
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
s_add_i32 s2, s4, -1
v_cmp_ne_u32_e32 vcc_lo, s2, v2
global_load_b32 v0, v[4:5], off
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
global_load_b32 v8, v[4:5], off offset:4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v0, v8
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_10
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x38
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x28
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_mov_b32_e32 v9, 0
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v5, vcc_lo
s_branch .LBB0_7
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s9
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, s8, v10
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_store_b32 v[6:7], v5, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v3, s0, v3, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s0, 0, v4, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v8
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_10
.LBB0_7:
global_load_b32 v5, v[3:4], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v10, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e32 0, v10
s_cbranch_execz .LBB0_6
global_load_b32 v11, v[1:2], off
s_mov_b32 s8, exec_lo
s_mov_b32 s9, exec_lo
v_mbcnt_lo_u32_b32 v10, s8, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, 1, v11
global_store_b32 v[6:7], v11, off
v_cmpx_eq_u32_e32 0, v10
s_cbranch_execz .LBB0_5
s_bcnt1_i32_b32 s8, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v6, s8
global_atomic_add_u32 v6, v9, v6, s[6:7] glc
s_branch .LBB0_5
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3BFSPiS_S_S_iiS_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3BFSPiS_S_S_iiS_S_S_, .Lfunc_end0-_Z3BFSPiS_S_S_iiS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3BFSPiS_S_S_iiS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3BFSPiS_S_S_iiS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00007c4f_00000000-6_bfs_hx.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
.type _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_, @function
_Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 232(%rsp), %rax
movq %rax, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z3BFSPiS_S_S_iiS_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_, .-_Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
.globl _Z3BFSPiS_S_S_iiS_S_S_
.type _Z3BFSPiS_S_S_iiS_S_S_, @function
_Z3BFSPiS_S_S_iiS_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3BFSPiS_S_S_iiS_S_S_, .-_Z3BFSPiS_S_S_iiS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "r"
.LC2:
.string "graph.txt"
.LC3:
.string "%d %d\n"
.LC4:
.string "completed input\n"
.LC6:
.string "max-level: %d\n"
.LC7:
.string "time: %f\n"
.LC8:
.string "w"
.LC9:
.string "Hx.txt"
.LC10:
.string "%d "
.LC11:
.string "unreachable %d , %f\n"
.LC12:
.string "farthest node: %d val: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %r12
leaq 36(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movslq 32(%rsp), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r13
movl 36(%rsp), %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testl %ebx, %ebx
jle .L12
movq %rax, %rbp
movl $0, %ebx
leaq .LC0(%rip), %r14
.L13:
movq %rbp, %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 36(%rsp)
jg .L13
.L12:
cmpl $0, 32(%rsp)
jle .L14
movq %r13, %rbp
movl $0, %ebx
leaq .LC0(%rip), %r14
.L15:
movq %rbp, %rdx
movq %r14, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 32(%rsp)
jg .L15
.L14:
movq %r12, %rdi
call fclose@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 36(%rsp), %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movl 28(%rsp), %r15d
movl %r15d, (%rax)
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $1, (%rax)
movslq 32(%rsp), %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %rcx
movq %rbp, %rdx
movl $-1, %esi
movq %rax, %rdi
call __memset_chk@PLT
movslq %r15d, %r15
movl $0, (%r14,%r15,4)
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, (%rax)
movl $4, %edi
call malloc@PLT
movq %rax, %r15
movl $1, (%rax)
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movslq 32(%rsp), %rsi
salq $2, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movslq 32(%rsp), %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
movslq 36(%rsp), %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
movslq 36(%rsp), %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movslq 36(%rsp), %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movslq 36(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movslq 36(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r15, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl (%rbx), %eax
testl %eax, %eax
jle .L16
movl $1, %r12d
jmp .L21
.L38:
movl $512, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl %edx, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L18:
movl $2, %ecx
movl $4, %edx
movq 104(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L19
.L37:
subq $8, %rsp
.cfi_def_cfa_offset 216
pushq 80(%rsp)
.cfi_def_cfa_offset 224
pushq 120(%rsp)
.cfi_def_cfa_offset 232
pushq 120(%rsp)
.cfi_def_cfa_offset 240
movl 68(%rsp), %r9d
movl 64(%rsp), %r8d
movq 120(%rsp), %rcx
movq 112(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 208
jmp .L18
.L20:
movl $2, %ecx
movl $4, %edx
movq 88(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %rbp, %rsi
movq 104(%rsp), %rdi
call cudaMemcpy@PLT
.L19:
addl $1, %r12d
movl (%rbx), %eax
testl %eax, %eax
jle .L16
.L21:
leal 1022(%rax), %edx
addl $511, %eax
cmovs %edx, %eax
sarl $9, %eax
movl %eax, %edx
movl %r12d, %ecx
shrl $31, %ecx
leal (%r12,%rcx), %eax
andl $1, %eax
subl %ecx, %eax
cmpl $1, %eax
je .L38
movl $512, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl %edx, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 124(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L20
subq $8, %rsp
.cfi_def_cfa_offset 216
pushq 80(%rsp)
.cfi_def_cfa_offset 224
pushq 104(%rsp)
.cfi_def_cfa_offset 232
pushq 104(%rsp)
.cfi_def_cfa_offset 240
movl 68(%rsp), %r9d
movl 64(%rsp), %r8d
movq 136(%rsp), %rcx
movq 128(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z36__device_stub__Z3BFSPiS_S_S_iiS_S_S_PiS_S_S_iiS_S_S_
addq $32, %rsp
.cfi_def_cfa_offset 208
jmp .L20
.L16:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movslq 32(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 72(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 124(%rsp)
leaq 124(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 32(%rsp), %edx
testl %edx, %edx
jle .L29
movq %r14, %rax
movslq %edx, %rdx
leaq (%r14,%rdx,4), %rsi
movl $0, %edx
.L23:
movl (%rax), %ecx
cmpl %ecx, %edx
cmovl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L23
.L22:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 124(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
leaq .LC9(%rip), %rdi
call fopen@PLT
movq %rax, %r15
cmpl $0, 32(%rsp)
jle .L30
movl $0, %ebx
movl $0, %r13d
movl $0, %ebp
movl $0, %r12d
.L27:
movl (%r14,%rbx,4), %ecx
cmpl $-1, %ecx
sete %al
movzbl %al, %eax
addl %eax, %r12d
cmpl %ebp, %ecx
cmovge %ebx, %r13d
cmovge %ecx, %ebp
leaq .LC10(%rip), %rdx
movl $2, %esi
movq %r15, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl %ebx, 32(%rsp)
jg .L27
.L24:
movq %r15, %rdi
call fclose@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 32(%rsp), %xmm1
divsd %xmm1, %xmm0
movl %r12d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebp, %ecx
movl %r13d, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl $0, %edx
jmp .L22
.L30:
movl $0, %r13d
movl $0, %ebp
movl $0, %r12d
jmp .L24
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z3BFSPiS_S_S_iiS_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z3BFSPiS_S_S_iiS_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "bfs_hx.hip"
.globl _Z18__device_stub__BFSPiS_S_S_iiS_S_S_ # -- Begin function _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.p2align 4, 0x90
.type _Z18__device_stub__BFSPiS_S_S_iiS_S_S_,@function
_Z18__device_stub__BFSPiS_S_S_iiS_S_S_: # @_Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z18__device_stub__BFSPiS_S_S_iiS_S_S_, .Lfunc_end0-_Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 188(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %rbx
leaq 8(%rsp), %rdx
leaq 12(%rsp), %rcx
movl $.L.str.3, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq 8(%rsp), %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r13
movslq 12(%rsp), %r14
leaq (,%r14,4), %rdi
callq malloc
movq %rax, %r12
testq %r14, %r14
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movq %r12, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r15
movslq 12(%rsp), %rax
addq $4, %r14
cmpq %rax, %r15
jl .LBB1_2
.LBB1_3: # %.preheader
movq %r12, 288(%rsp) # 8-byte Spill
cmpl $0, 8(%rsp)
jle .LBB1_6
# %bb.4: # %.lr.ph106.preheader
movq %r13, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph106
# =>This Inner Loop Header: Depth=1
movl $.L.str, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %r15
movslq 8(%rsp), %rax
addq $4, %r14
cmpq %rax, %r15
jl .LBB1_5
.LBB1_6: # %._crit_edge
movq %rbx, %rdi
callq fclose
movl $.Lstr, %edi
callq puts@PLT
movslq 12(%rsp), %rdi
shlq $2, %rdi
callq malloc
movq %rax, %r12
movq %r13, 280(%rsp) # 8-byte Spill
movslq 188(%rsp), %r13
movl %r13d, (%rax)
movl $4, %edi
callq malloc
movq %rax, %r14
movl $1, (%rax)
movslq 8(%rsp), %r15
shlq $2, %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movq %rax, %rdi
movl $255, %esi
movq %r15, %rdx
callq memset@PLT
movl $0, (%rbx,%r13,4)
movl $4, %edi
callq malloc
movq %rax, %r15
movl $0, (%rax)
movl $4, %edi
callq malloc
movq %rax, %rbp
movl $1, (%rax)
leaq 200(%rsp), %rdi
callq hipEventCreate
leaq 72(%rsp), %rdi
callq hipEventCreate
movslq 8(%rsp), %rsi
shlq $2, %rsi
leaq 64(%rsp), %rdi
callq hipMalloc
movslq 8(%rsp), %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 56(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 48(%rsp), %rdi
callq hipMalloc
leaq 32(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 192(%rsp), %rdi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 64(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movl $1, %r13d
movq 280(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq 288(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $4, %edx
movq %rbp, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 200(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movl (%r14), %edi
testl %edi, %edi
jle .LBB1_16
# %bb.7: # %.lr.ph109
movabsq $4294967296, %rax # imm = 0x100000000
leaq 512(%rax), %r12
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_8 Depth=1
testl %eax, %eax
je .LBB1_13
.LBB1_14: # in Loop: Header=BB1_8 Depth=1
movq 32(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 24(%rsp), %rax
.LBB1_15: # in Loop: Header=BB1_8 Depth=1
movq (%rax), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
incl %r13d
movl (%r14), %edi
testl %edi, %edi
jle .LBB1_16
.LBB1_8: # =>This Inner Loop Header: Depth=1
addl $511, %edi # imm = 0x1FF
shrl $9, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testb $1, %r13b
je .LBB1_12
# %bb.9: # in Loop: Header=BB1_8 Depth=1
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_8 Depth=1
movq 64(%rsp), %rax
movq %rax, 176(%rsp)
movq 56(%rsp), %rax
movq %rax, 168(%rsp)
movq 48(%rsp), %rax
movq %rax, 160(%rsp)
movq 32(%rsp), %rax
movq %rax, 152(%rsp)
movl 8(%rsp), %eax
movl %eax, 20(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 144(%rsp)
movq 24(%rsp), %rax
movq %rax, 136(%rsp)
movq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 176(%rsp), %rax
movq %rax, 208(%rsp)
leaq 168(%rsp), %rax
movq %rax, 216(%rsp)
leaq 160(%rsp), %rax
movq %rax, 224(%rsp)
leaq 152(%rsp), %rax
movq %rax, 232(%rsp)
leaq 20(%rsp), %rax
movq %rax, 240(%rsp)
leaq 16(%rsp), %rax
movq %rax, 248(%rsp)
leaq 144(%rsp), %rax
movq %rax, 256(%rsp)
leaq 136(%rsp), %rax
movq %rax, 264(%rsp)
leaq 128(%rsp), %rax
movq %rax, 272(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
leaq 208(%rsp), %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_11: # in Loop: Header=BB1_8 Depth=1
movq 24(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 32(%rsp), %rax
jmp .LBB1_15
.LBB1_13: # in Loop: Header=BB1_8 Depth=1
movq 64(%rsp), %rax
movq %rax, 176(%rsp)
movq 56(%rsp), %rax
movq %rax, 168(%rsp)
movq 192(%rsp), %rax
movq %rax, 160(%rsp)
movq 24(%rsp), %rax
movq %rax, 152(%rsp)
movl 8(%rsp), %eax
movl %eax, 20(%rsp)
movl 12(%rsp), %eax
movl %eax, 16(%rsp)
movq 48(%rsp), %rax
movq %rax, 144(%rsp)
movq 32(%rsp), %rax
movq %rax, 136(%rsp)
movq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 176(%rsp), %rax
movq %rax, 208(%rsp)
leaq 168(%rsp), %rax
movq %rax, 216(%rsp)
leaq 160(%rsp), %rax
movq %rax, 224(%rsp)
leaq 152(%rsp), %rax
movq %rax, 232(%rsp)
leaq 20(%rsp), %rax
movq %rax, 240(%rsp)
leaq 16(%rsp), %rax
movq %rax, 248(%rsp)
leaq 144(%rsp), %rax
movq %rax, 256(%rsp)
leaq 136(%rsp), %rax
movq %rax, 264(%rsp)
leaq 128(%rsp), %rax
movq %rax, 272(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z3BFSPiS_S_S_iiS_S_S_, %edi
leaq 208(%rsp), %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_14
.LBB1_16: # %._crit_edge110
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rsi
movslq 8(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 72(%rsp), %rdi
callq hipEventSynchronize
movl $0, 208(%rsp)
movq 200(%rsp), %rsi
movq 72(%rsp), %rdx
leaq 208(%rsp), %rdi
callq hipEventElapsedTime
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB1_19
# %bb.17: # %.lr.ph114.preheader
xorl %ecx, %ecx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_18: # %.lr.ph114
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rcx,4), %edx
cmpl %ebp, %edx
cmovgl %edx, %ebp
incq %rcx
cmpq %rcx, %rax
jne .LBB1_18
.LBB1_19: # %._crit_edge115
xorl %r14d, %r14d
movl $.L.str.5, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movss 208(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.7, %edi
movl $.L.str.8, %esi
callq fopen
movq %rax, %r12
cmpl $0, 8(%rsp)
movl $0, %ebp
movl $0, %r15d
jle .LBB1_22
# %bb.20: # %.lr.ph121.preheader
xorl %r13d, %r13d
xorl %r15d, %r15d
xorl %ebp, %ebp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_21: # %.lr.ph121
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r13,4), %edx
xorl %eax, %eax
cmpl $-1, %edx
sete %al
addl %eax, %r14d
cmpl %ebp, %edx
cmovgl %edx, %ebp
cmovgel %r13d, %r15d
movl $.L.str.9, %esi
movq %r12, %rdi
xorl %eax, %eax
callq fprintf
incq %r13
movslq 8(%rsp), %rax
cmpq %rax, %r13
jl .LBB1_21
.LBB1_22: # %._crit_edge122
movq %r12, %rdi
callq fclose
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
cvtsi2sdl 8(%rsp), %xmm1
divsd %xmm1, %xmm0
movl $.L.str.10, %edi
movl %r14d, %esi
movb $1, %al
callq printf
movl $.L.str.11, %edi
movl %r15d, %esi
movl %ebp, %edx
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3BFSPiS_S_S_iiS_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3BFSPiS_S_S_iiS_S_S_,@object # @_Z3BFSPiS_S_S_iiS_S_S_
.section .rodata,"a",@progbits
.globl _Z3BFSPiS_S_S_iiS_S_S_
.p2align 3, 0x0
_Z3BFSPiS_S_S_iiS_S_S_:
.quad _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.size _Z3BFSPiS_S_S_iiS_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "graph.txt"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d %d\n"
.size .L.str.3, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "max-level: %d\n"
.size .L.str.5, 15
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "time: %f\n"
.size .L.str.6, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Hx.txt"
.size .L.str.7, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "w"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d "
.size .L.str.9, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "unreachable %d , %f\n"
.size .L.str.10, 21
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "farthest node: %d val: %d\n"
.size .L.str.11, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3BFSPiS_S_S_iiS_S_S_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "completed input"
.size .Lstr, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__BFSPiS_S_S_iiS_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3BFSPiS_S_S_iiS_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
int NPTS = 20000;
__global__ void kernel (float *a, float *b, int dimx, int dimy)
{
// Compute the index variable
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
//a[idx] = a[idx]+1;
float r, xdiff, ydiff;
for (int i=idx;i<dimx;i++)
{
if (i != idx)
{
xdiff = a[idx] - a[i];
ydiff = b[idx] - b[i];
r = sqrt(xdiff*xdiff + ydiff*ydiff);
}
}
}
int main()
{
float xmax = 10.0;
float ymax = 10.0;
int num_bytes = NPTS*sizeof(float);
float *d_x=0, *d_y=0, *h_x=0, *h_y=0; // device and host pointers
// Allocate memory on host (CPU)
h_x = (float*)malloc(num_bytes);
h_y = (float*)malloc(num_bytes);
// Allocate memory on device (GPU)
cudaMalloc((void**)&d_x,num_bytes);
cudaMalloc((void**)&d_y,num_bytes);
// Check to see that there was enough memory for both
// allocations.
// If the memory allocation fails, it doesn't change the
// pointer value. That is why we set them to be 0 at declaration,
// and then see if they have changed or stayed the same.
if (0==h_x || 0==d_x || 0==h_y || 0==d_y)
{
printf("couldn't allocate memory\n");
return 1;
}
// Fill the universe with random stuff
for (int i=0;i<NPTS;i++)
{
h_x[i] = 2.0*xmax*rand() - xmax;
h_y[i] = 2.0*ymax*rand() - ymax;
}
// Initialize array to all 0's
cudaMemset(d_x,0,num_bytes);
cudaMemset(d_y,0,num_bytes);
//-----------------------------------------------------------------------//
dim3 grid,block;
block.x = 4;
block.y = 4;
grid.x = NPTS/block.x;
grid.y = NPTS/block.y;
cudaMemcpy(d_x,h_x,num_bytes,cudaMemcpyHostToDevice);
cudaMemcpy(d_y,h_y,num_bytes,cudaMemcpyHostToDevice);
kernel<<<grid,block>>>(d_x,d_y,NPTS,NPTS);
/*
// Copy it back over
cudaMemcpy(h_a,d_a,num_bytes,cudaMemcpyDeviceToHost);
for (int row=0;row<dimy;row++)
{
for (int col=0;col<dimx;col++)
{
printf("%d",h_a[row*dimx+col]);
}
printf("\n");
}
*/
free(h_x);
free(h_y);
cudaFree(d_x);
cudaFree(d_y);
return 0;
}
|
code for sm_80
Function : _Z6kernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
int NPTS = 20000;
__global__ void kernel (float *a, float *b, int dimx, int dimy)
{
// Compute the index variable
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
//a[idx] = a[idx]+1;
float r, xdiff, ydiff;
for (int i=idx;i<dimx;i++)
{
if (i != idx)
{
xdiff = a[idx] - a[i];
ydiff = b[idx] - b[i];
r = sqrt(xdiff*xdiff + ydiff*ydiff);
}
}
}
int main()
{
float xmax = 10.0;
float ymax = 10.0;
int num_bytes = NPTS*sizeof(float);
float *d_x=0, *d_y=0, *h_x=0, *h_y=0; // device and host pointers
// Allocate memory on host (CPU)
h_x = (float*)malloc(num_bytes);
h_y = (float*)malloc(num_bytes);
// Allocate memory on device (GPU)
cudaMalloc((void**)&d_x,num_bytes);
cudaMalloc((void**)&d_y,num_bytes);
// Check to see that there was enough memory for both
// allocations.
// If the memory allocation fails, it doesn't change the
// pointer value. That is why we set them to be 0 at declaration,
// and then see if they have changed or stayed the same.
if (0==h_x || 0==d_x || 0==h_y || 0==d_y)
{
printf("couldn't allocate memory\n");
return 1;
}
// Fill the universe with random stuff
for (int i=0;i<NPTS;i++)
{
h_x[i] = 2.0*xmax*rand() - xmax;
h_y[i] = 2.0*ymax*rand() - ymax;
}
// Initialize array to all 0's
cudaMemset(d_x,0,num_bytes);
cudaMemset(d_y,0,num_bytes);
//-----------------------------------------------------------------------//
dim3 grid,block;
block.x = 4;
block.y = 4;
grid.x = NPTS/block.x;
grid.y = NPTS/block.y;
cudaMemcpy(d_x,h_x,num_bytes,cudaMemcpyHostToDevice);
cudaMemcpy(d_y,h_y,num_bytes,cudaMemcpyHostToDevice);
kernel<<<grid,block>>>(d_x,d_y,NPTS,NPTS);
/*
// Copy it back over
cudaMemcpy(h_a,d_a,num_bytes,cudaMemcpyDeviceToHost);
for (int row=0;row<dimy;row++)
{
for (int col=0;col<dimx;col++)
{
printf("%d",h_a[row*dimx+col]);
}
printf("\n");
}
*/
free(h_x);
free(h_y);
cudaFree(d_x);
cudaFree(d_y);
return 0;
}
|
.file "tmpxft_001227b5_00000000-6_calc_distances_Matt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6kernelPfS_iiPfS_ii
.type _Z29__device_stub__Z6kernelPfS_iiPfS_ii, @function
_Z29__device_stub__Z6kernelPfS_iiPfS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6kernelPfS_iiPfS_ii, .-_Z29__device_stub__Z6kernelPfS_iiPfS_ii
.globl _Z6kernelPfS_ii
.type _Z6kernelPfS_ii, @function
_Z6kernelPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPfS_ii, .-_Z6kernelPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "couldn't allocate memory\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl NPTS(%rip), %eax
leal 0(,%rax,4), %ebp
movq $0, (%rsp)
movq $0, 8(%rsp)
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testq %r12, %r12
je .L12
cmpq $0, (%rsp)
je .L12
testq %r13, %r13
je .L12
cmpq $0, 8(%rsp)
je .L12
movl $0, %ebx
cmpl $0, NPTS(%rip)
jle .L14
.L13:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
subsd .LC2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rbx,4)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
subsd .LC2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%r13,%rbx,4)
addq $1, %rbx
cmpl %ebx, NPTS(%rip)
jg .L13
.L14:
movq %rbp, %rdx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movq %rbp, %rdx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl $1, 24(%rsp)
movl $1, 36(%rsp)
movl NPTS(%rip), %eax
shrl $2, %eax
movl %eax, 16(%rsp)
movl %eax, 20(%rsp)
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 28(%rsp)
movl $4, 32(%rsp)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L23
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L22:
movl NPTS(%rip), %edx
movl %edx, %ecx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6kernelPfS_iiPfS_ii
jmp .L16
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6kernelPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl NPTS
.data
.align 4
.type NPTS, @object
.size NPTS, 4
NPTS:
.long 20000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1077149696
.align 8
.LC2:
.long 0
.long 1076101120
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
int NPTS = 20000;
__global__ void kernel (float *a, float *b, int dimx, int dimy)
{
// Compute the index variable
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
//a[idx] = a[idx]+1;
float r, xdiff, ydiff;
for (int i=idx;i<dimx;i++)
{
if (i != idx)
{
xdiff = a[idx] - a[i];
ydiff = b[idx] - b[i];
r = sqrt(xdiff*xdiff + ydiff*ydiff);
}
}
}
int main()
{
float xmax = 10.0;
float ymax = 10.0;
int num_bytes = NPTS*sizeof(float);
float *d_x=0, *d_y=0, *h_x=0, *h_y=0; // device and host pointers
// Allocate memory on host (CPU)
h_x = (float*)malloc(num_bytes);
h_y = (float*)malloc(num_bytes);
// Allocate memory on device (GPU)
cudaMalloc((void**)&d_x,num_bytes);
cudaMalloc((void**)&d_y,num_bytes);
// Check to see that there was enough memory for both
// allocations.
// If the memory allocation fails, it doesn't change the
// pointer value. That is why we set them to be 0 at declaration,
// and then see if they have changed or stayed the same.
if (0==h_x || 0==d_x || 0==h_y || 0==d_y)
{
printf("couldn't allocate memory\n");
return 1;
}
// Fill the universe with random stuff
for (int i=0;i<NPTS;i++)
{
h_x[i] = 2.0*xmax*rand() - xmax;
h_y[i] = 2.0*ymax*rand() - ymax;
}
// Initialize array to all 0's
cudaMemset(d_x,0,num_bytes);
cudaMemset(d_y,0,num_bytes);
//-----------------------------------------------------------------------//
dim3 grid,block;
block.x = 4;
block.y = 4;
grid.x = NPTS/block.x;
grid.y = NPTS/block.y;
cudaMemcpy(d_x,h_x,num_bytes,cudaMemcpyHostToDevice);
cudaMemcpy(d_y,h_y,num_bytes,cudaMemcpyHostToDevice);
kernel<<<grid,block>>>(d_x,d_y,NPTS,NPTS);
/*
// Copy it back over
cudaMemcpy(h_a,d_a,num_bytes,cudaMemcpyDeviceToHost);
for (int row=0;row<dimy;row++)
{
for (int col=0;col<dimx;col++)
{
printf("%d",h_a[row*dimx+col]);
}
printf("\n");
}
*/
free(h_x);
free(h_y);
cudaFree(d_x);
cudaFree(d_y);
return 0;
}
|
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
int NPTS = 20000;
__global__ void kernel (float *a, float *b, int dimx, int dimy)
{
// Compute the index variable
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
//a[idx] = a[idx]+1;
float r, xdiff, ydiff;
for (int i=idx;i<dimx;i++)
{
if (i != idx)
{
xdiff = a[idx] - a[i];
ydiff = b[idx] - b[i];
r = sqrt(xdiff*xdiff + ydiff*ydiff);
}
}
}
int main()
{
float xmax = 10.0;
float ymax = 10.0;
int num_bytes = NPTS*sizeof(float);
float *d_x=0, *d_y=0, *h_x=0, *h_y=0; // device and host pointers
// Allocate memory on host (CPU)
h_x = (float*)malloc(num_bytes);
h_y = (float*)malloc(num_bytes);
// Allocate memory on device (GPU)
hipMalloc((void**)&d_x,num_bytes);
hipMalloc((void**)&d_y,num_bytes);
// Check to see that there was enough memory for both
// allocations.
// If the memory allocation fails, it doesn't change the
// pointer value. That is why we set them to be 0 at declaration,
// and then see if they have changed or stayed the same.
if (0==h_x || 0==d_x || 0==h_y || 0==d_y)
{
printf("couldn't allocate memory\n");
return 1;
}
// Fill the universe with random stuff
for (int i=0;i<NPTS;i++)
{
h_x[i] = 2.0*xmax*rand() - xmax;
h_y[i] = 2.0*ymax*rand() - ymax;
}
// Initialize array to all 0's
hipMemset(d_x,0,num_bytes);
hipMemset(d_y,0,num_bytes);
//-----------------------------------------------------------------------//
dim3 grid,block;
block.x = 4;
block.y = 4;
grid.x = NPTS/block.x;
grid.y = NPTS/block.y;
hipMemcpy(d_x,h_x,num_bytes,hipMemcpyHostToDevice);
hipMemcpy(d_y,h_y,num_bytes,hipMemcpyHostToDevice);
kernel<<<grid,block>>>(d_x,d_y,NPTS,NPTS);
/*
// Copy it back over
cudaMemcpy(h_a,d_a,num_bytes,cudaMemcpyDeviceToHost);
for (int row=0;row<dimy;row++)
{
for (int col=0;col<dimx;col++)
{
printf("%d",h_a[row*dimx+col]);
}
printf("\n");
}
*/
free(h_x);
free(h_y);
hipFree(d_x);
hipFree(d_y);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
int NPTS = 20000;
__global__ void kernel (float *a, float *b, int dimx, int dimy)
{
// Compute the index variable
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
//a[idx] = a[idx]+1;
float r, xdiff, ydiff;
for (int i=idx;i<dimx;i++)
{
if (i != idx)
{
xdiff = a[idx] - a[i];
ydiff = b[idx] - b[i];
r = sqrt(xdiff*xdiff + ydiff*ydiff);
}
}
}
int main()
{
float xmax = 10.0;
float ymax = 10.0;
int num_bytes = NPTS*sizeof(float);
float *d_x=0, *d_y=0, *h_x=0, *h_y=0; // device and host pointers
// Allocate memory on host (CPU)
h_x = (float*)malloc(num_bytes);
h_y = (float*)malloc(num_bytes);
// Allocate memory on device (GPU)
hipMalloc((void**)&d_x,num_bytes);
hipMalloc((void**)&d_y,num_bytes);
// Check to see that there was enough memory for both
// allocations.
// If the memory allocation fails, it doesn't change the
// pointer value. That is why we set them to be 0 at declaration,
// and then see if they have changed or stayed the same.
if (0==h_x || 0==d_x || 0==h_y || 0==d_y)
{
printf("couldn't allocate memory\n");
return 1;
}
// Fill the universe with random stuff
for (int i=0;i<NPTS;i++)
{
h_x[i] = 2.0*xmax*rand() - xmax;
h_y[i] = 2.0*ymax*rand() - ymax;
}
// Initialize array to all 0's
hipMemset(d_x,0,num_bytes);
hipMemset(d_y,0,num_bytes);
//-----------------------------------------------------------------------//
dim3 grid,block;
block.x = 4;
block.y = 4;
grid.x = NPTS/block.x;
grid.y = NPTS/block.y;
hipMemcpy(d_x,h_x,num_bytes,hipMemcpyHostToDevice);
hipMemcpy(d_y,h_y,num_bytes,hipMemcpyHostToDevice);
kernel<<<grid,block>>>(d_x,d_y,NPTS,NPTS);
/*
// Copy it back over
cudaMemcpy(h_a,d_a,num_bytes,cudaMemcpyDeviceToHost);
for (int row=0;row<dimy;row++)
{
for (int col=0;col<dimx;col++)
{
printf("%d",h_a[row*dimx+col]);
}
printf("\n");
}
*/
free(h_x);
free(h_y);
hipFree(d_x);
hipFree(d_y);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_ii
.globl _Z6kernelPfS_ii
.p2align 8
.type _Z6kernelPfS_ii,@function
_Z6kernelPfS_ii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_ii, .Lfunc_end0-_Z6kernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<cmath>
int NPTS = 20000;
__global__ void kernel (float *a, float *b, int dimx, int dimy)
{
// Compute the index variable
int ix = blockIdx.x*blockDim.x + threadIdx.x;
int iy = blockIdx.y*blockDim.y + threadIdx.y;
int idx = iy*dimx + ix;
//a[idx] = a[idx]+1;
float r, xdiff, ydiff;
for (int i=idx;i<dimx;i++)
{
if (i != idx)
{
xdiff = a[idx] - a[i];
ydiff = b[idx] - b[i];
r = sqrt(xdiff*xdiff + ydiff*ydiff);
}
}
}
int main()
{
float xmax = 10.0;
float ymax = 10.0;
int num_bytes = NPTS*sizeof(float);
float *d_x=0, *d_y=0, *h_x=0, *h_y=0; // device and host pointers
// Allocate memory on host (CPU)
h_x = (float*)malloc(num_bytes);
h_y = (float*)malloc(num_bytes);
// Allocate memory on device (GPU)
hipMalloc((void**)&d_x,num_bytes);
hipMalloc((void**)&d_y,num_bytes);
// Check to see that there was enough memory for both
// allocations.
// If the memory allocation fails, it doesn't change the
// pointer value. That is why we set them to be 0 at declaration,
// and then see if they have changed or stayed the same.
if (0==h_x || 0==d_x || 0==h_y || 0==d_y)
{
printf("couldn't allocate memory\n");
return 1;
}
// Fill the universe with random stuff
for (int i=0;i<NPTS;i++)
{
h_x[i] = 2.0*xmax*rand() - xmax;
h_y[i] = 2.0*ymax*rand() - ymax;
}
// Initialize array to all 0's
hipMemset(d_x,0,num_bytes);
hipMemset(d_y,0,num_bytes);
//-----------------------------------------------------------------------//
dim3 grid,block;
block.x = 4;
block.y = 4;
grid.x = NPTS/block.x;
grid.y = NPTS/block.y;
hipMemcpy(d_x,h_x,num_bytes,hipMemcpyHostToDevice);
hipMemcpy(d_y,h_y,num_bytes,hipMemcpyHostToDevice);
kernel<<<grid,block>>>(d_x,d_y,NPTS,NPTS);
/*
// Copy it back over
cudaMemcpy(h_a,d_a,num_bytes,cudaMemcpyDeviceToHost);
for (int row=0;row<dimy;row++)
{
for (int col=0;col<dimx;col++)
{
printf("%d",h_a[row*dimx+col]);
}
printf("\n");
}
*/
free(h_x);
free(h_y);
hipFree(d_x);
hipFree(d_y);
return 0;
}
|
.text
.file "calc_distances_Matt.hip"
.globl _Z21__device_stub__kernelPfS_ii # -- Begin function _Z21__device_stub__kernelPfS_ii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_ii,@function
_Z21__device_stub__kernelPfS_ii: # @_Z21__device_stub__kernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_ii, .Lfunc_end0-_Z21__device_stub__kernelPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4034000000000000 # double 20
.LCPI1_1:
.quad 0xc024000000000000 # double -10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl NPTS(%rip), %eax
shll $2, %eax
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testq %r14, %r14
je .LBB1_11
# %bb.1:
testq %rbx, %rbx
je .LBB1_11
# %bb.2:
cmpq $0, 16(%rsp)
je .LBB1_11
# %bb.3:
cmpq $0, 8(%rsp)
je .LBB1_11
# %bb.4: # %.preheader
cmpl $0, NPTS(%rip)
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
movslq NPTS(%rip), %rax
cmpq %rax, %r15
jl .LBB1_6
.LBB1_7: # %._crit_edge
movq 16(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movq %r12, %rdx
callq hipMemset
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %r12, %rdx
callq hipMemset
movl NPTS(%rip), %eax
shrl $2, %eax
movq %rax, %r13
shlq $32, %r13
orq %rax, %r13
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $17179869188, %rdx # imm = 0x400000004
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl NPTS(%rip), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
movl %edx, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB1_10
.LBB1_11:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %r15d
.LBB1_10:
movl %r15d, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type NPTS,@object # @NPTS
.data
.globl NPTS
.p2align 2, 0x0
NPTS:
.long 20000 # 0x4e20
.size NPTS, 4
.type _Z6kernelPfS_ii,@object # @_Z6kernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_ii
.p2align 3, 0x0
_Z6kernelPfS_ii:
.quad _Z21__device_stub__kernelPfS_ii
.size _Z6kernelPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPfS_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z6kernelPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_ii
.globl _Z6kernelPfS_ii
.p2align 8
.type _Z6kernelPfS_ii,@function
_Z6kernelPfS_ii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_ii, .Lfunc_end0-_Z6kernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001227b5_00000000-6_calc_distances_Matt.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6kernelPfS_iiPfS_ii
.type _Z29__device_stub__Z6kernelPfS_iiPfS_ii, @function
_Z29__device_stub__Z6kernelPfS_iiPfS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6kernelPfS_iiPfS_ii, .-_Z29__device_stub__Z6kernelPfS_iiPfS_ii
.globl _Z6kernelPfS_ii
.type _Z6kernelPfS_ii, @function
_Z6kernelPfS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPfS_ii, .-_Z6kernelPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "couldn't allocate memory\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl NPTS(%rip), %eax
leal 0(,%rax,4), %ebp
movq $0, (%rsp)
movq $0, 8(%rsp)
movslq %ebp, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rsp, %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testq %r12, %r12
je .L12
cmpq $0, (%rsp)
je .L12
testq %r13, %r13
je .L12
cmpq $0, 8(%rsp)
je .L12
movl $0, %ebx
cmpl $0, NPTS(%rip)
jle .L14
.L13:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
subsd .LC2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rbx,4)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC1(%rip), %xmm0
subsd .LC2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%r13,%rbx,4)
addq $1, %rbx
cmpl %ebx, NPTS(%rip)
jg .L13
.L14:
movq %rbp, %rdx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movq %rbp, %rdx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl $1, 24(%rsp)
movl $1, 36(%rsp)
movl NPTS(%rip), %eax
shrl $2, %eax
movl %eax, 16(%rsp)
movl %eax, 20(%rsp)
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 28(%rsp)
movl $4, 32(%rsp)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L23
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L22:
movl NPTS(%rip), %edx
movl %edx, %ecx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z29__device_stub__Z6kernelPfS_iiPfS_ii
jmp .L16
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6kernelPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl NPTS
.data
.align 4
.type NPTS, @object
.size NPTS, 4
NPTS:
.long 20000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1077149696
.align 8
.LC2:
.long 0
.long 1076101120
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "calc_distances_Matt.hip"
.globl _Z21__device_stub__kernelPfS_ii # -- Begin function _Z21__device_stub__kernelPfS_ii
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_ii,@function
_Z21__device_stub__kernelPfS_ii: # @_Z21__device_stub__kernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_ii, .Lfunc_end0-_Z21__device_stub__kernelPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4034000000000000 # double 20
.LCPI1_1:
.quad 0xc024000000000000 # double -10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl NPTS(%rip), %eax
shll $2, %eax
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testq %r14, %r14
je .LBB1_11
# %bb.1:
testq %rbx, %rbx
je .LBB1_11
# %bb.2:
cmpq $0, 16(%rsp)
je .LBB1_11
# %bb.3:
cmpq $0, 8(%rsp)
je .LBB1_11
# %bb.4: # %.preheader
cmpl $0, NPTS(%rip)
jle .LBB1_7
# %bb.5: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r15,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
movslq NPTS(%rip), %rax
cmpq %rax, %r15
jl .LBB1_6
.LBB1_7: # %._crit_edge
movq 16(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movq %r12, %rdx
callq hipMemset
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %r12, %rdx
callq hipMemset
movl NPTS(%rip), %eax
shrl $2, %eax
movq %rax, %r13
shlq $32, %r13
orq %rax, %r13
movq 16(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $17179869188, %rdx # imm = 0x400000004
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl NPTS(%rip), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
movl %edx, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6kernelPfS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
jmp .LBB1_10
.LBB1_11:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %r15d
.LBB1_10:
movl %r15d, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type NPTS,@object # @NPTS
.data
.globl NPTS
.p2align 2, 0x0
NPTS:
.long 20000 # 0x4e20
.size NPTS, 4
.type _Z6kernelPfS_ii,@object # @_Z6kernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_ii
.p2align 3, 0x0
_Z6kernelPfS_ii:
.quad _Z21__device_stub__kernelPfS_ii
.size _Z6kernelPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelPfS_ii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <cstdlib>
#include <chrono>
__global__ void test() {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
printf("Test %d\n", idx);
}
int main(int argc, char const *argv[]) {
int block_size = 1024;
int grid_size = 1024;
test<<<grid_size, block_size>>>();
cudaDeviceSynchronize();
return 0;
}
|
code for sm_80
Function : _Z4testv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <cstdlib>
#include <chrono>
__global__ void test() {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
printf("Test %d\n", idx);
}
int main(int argc, char const *argv[]) {
int block_size = 1024;
int grid_size = 1024;
test<<<grid_size, block_size>>>();
cudaDeviceSynchronize();
return 0;
}
|
.file "tmpxft_000bfb59_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3771:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3771:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4testvv
.type _Z22__device_stub__Z4testvv, @function
_Z22__device_stub__Z4testvv:
.LFB3793:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4testv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3793:
.size _Z22__device_stub__Z4testvv, .-_Z22__device_stub__Z4testvv
.globl _Z4testv
.type _Z4testv, @function
_Z4testv:
.LFB3794:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4testvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3794:
.size _Z4testv, .-_Z4testv
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1024, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4testvv
jmp .L12
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4testv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3796:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3796:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <cstdlib>
#include <chrono>
__global__ void test() {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
printf("Test %d\n", idx);
}
int main(int argc, char const *argv[]) {
int block_size = 1024;
int grid_size = 1024;
test<<<grid_size, block_size>>>();
cudaDeviceSynchronize();
return 0;
}
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <cstdlib>
#include <chrono>
__global__ void test() {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
printf("Test %d\n", idx);
}
int main(int argc, char const *argv[]) {
int block_size = 1024;
int grid_size = 1024;
test<<<grid_size, block_size>>>();
hipDeviceSynchronize();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <stdio.h>
#include <cstdlib>
#include <chrono>
__global__ void test() {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
printf("Test %d\n", idx);
}
int main(int argc, char const *argv[]) {
int block_size = 1024;
int grid_size = 1024;
test<<<grid_size, block_size>>>();
hipDeviceSynchronize();
return 0;
}
|
.text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__testv # -- Begin function _Z19__device_stub__testv
.p2align 4, 0x90
.type _Z19__device_stub__testv,@function
_Z19__device_stub__testv: # @_Z19__device_stub__testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__testv, .Lfunc_end0-_Z19__device_stub__testv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294968320, %rdi # imm = 0x100000400
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testv,@object # @_Z4testv
.section .rodata,"a",@progbits
.globl _Z4testv
.p2align 3, 0x0
_Z4testv:
.quad _Z19__device_stub__testv
.size _Z4testv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4testv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000bfb59_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3771:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3771:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4testvv
.type _Z22__device_stub__Z4testvv, @function
_Z22__device_stub__Z4testvv:
.LFB3793:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4testv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3793:
.size _Z22__device_stub__Z4testvv, .-_Z22__device_stub__Z4testvv
.globl _Z4testv
.type _Z4testv, @function
_Z4testv:
.LFB3794:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4testvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3794:
.size _Z4testv, .-_Z4testv
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1024, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4testvv
jmp .L12
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4testv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3796:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3796:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z19__device_stub__testv # -- Begin function _Z19__device_stub__testv
.p2align 4, 0x90
.type _Z19__device_stub__testv,@function
_Z19__device_stub__testv: # @_Z19__device_stub__testv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__testv, .Lfunc_end0-_Z19__device_stub__testv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294968320, %rdi # imm = 0x100000400
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4testv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testv,@object # @_Z4testv
.section .rodata,"a",@progbits
.globl _Z4testv
.p2align 3, 0x0
_Z4testv:
.quad _Z19__device_stub__testv
.size _Z4testv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4testv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
extern "C" {
/*
#define BLOCK_SIZE 16
__global__ void matrix_multiply(const float* a, size_t lda, const float* b, size_t ldb, float* c, size_t ldc, int n)
{
__shared__ float matA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float matB[BLOCK_SIZE][BLOCK_SIZE];
const int tidc = threadIdx.x;
const int tidr = threadIdx.y;
const int bidc = blockIdx.x * BLOCK_SIZE;
const int bidr = blockIdx.y * BLOCK_SIZE;
int i, j;
float results = 0;
float comp = 0;
for(j = 0; j < n; j += BLOCK_SIZE) {
matA[tidr][tidc] = a[(tidr + bidr) * lda + tidc + j];
matB[tidr][tidc] = b[(tidr + j) * ldb + tidc + bidc];
__syncthreads();
for(i = 0; i < BLOCK_SIZE; i++) {
float t;
comp -= matA[tidr][i] * matB[i][tidc];
t = results - comp;
comp = (t - results) + comp;
results = t;
}
__syncthreads();
}
c[(tidr + bidr) * ldc + tidc + bidc] = results;
}
*/
__global__ void matrix_multiply_0(const float* _A,const float *_B,float* _C,int _wa,int _wb)
{
float sum = 0;
//找出该线程所在的行列
int row = blockIdx.y*blockDim.y + threadIdx.y; // X 对应矩阵row, Y对应举证col
int col = blockIdx.x*blockDim.x + threadIdx.x;
//线程Thread(row,col)负责计算C(row,col)
for (int i = 0; i < _wa; ++i)
{
sum += _A[row*_wa + i]*_B[i*_wb + col];
}
_C[row*_wb + col] = sum;
}
__global__ void matrix_multiply_1(float *A, float *B, float *C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
float sum = 0.0f;
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if(row < numCRows && col < numCColumns){
for (int i = 0; i < numAColumns; ++i)
{
sum += A[row*numAColumns + i] * B[i*numBColumns + col];
}
C[row*numBColumns + col] = sum;
}
//printf("C = %f\n",C[row*numBColumns + col]);
}
__global__ void matrix_elementwise_multiply(float * A,float * B,float *C,int width,int height){
int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
int idx = xIndex + yIndex * width;
if(xIndex < width && yIndex < height){
C[idx] = A[idx] * B[idx];
}
}
}
|
.file "tmpxft_000937b3_00000000-6_10-matrix-multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii
.type _Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii, @function
_Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq matrix_multiply_0(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii, .-_Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii
.globl matrix_multiply_0
.type matrix_multiply_0, @function
matrix_multiply_0:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17matrix_multiply_0PKfS0_PfiiPKfS0_Pfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size matrix_multiply_0, .-matrix_multiply_0
.globl _Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii
.type _Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii, @function
_Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 224(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq matrix_multiply_1(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii, .-_Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii
.globl matrix_multiply_1
.type matrix_multiply_1, @function
matrix_multiply_1:
.LFB2054:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z47__device_stub__Z17matrix_multiply_1PfS_S_iiiiiiPfS_S_iiiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size matrix_multiply_1, .-matrix_multiply_1
.globl _Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii
.type _Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii, @function
_Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii:
.LFB2055:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq matrix_elementwise_multiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii, .-_Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii
.globl matrix_elementwise_multiply
.type matrix_elementwise_multiply, @function
matrix_elementwise_multiply:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z27matrix_elementwise_multiplyPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size matrix_elementwise_multiply, .-matrix_elementwise_multiply
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrix_elementwise_multiply"
.LC1:
.string "matrix_multiply_1"
.LC2:
.string "matrix_multiply_0"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq matrix_elementwise_multiply(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq matrix_multiply_1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq matrix_multiply_0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
extern "C" {
/*
#define BLOCK_SIZE 16
__global__ void matrix_multiply(const float* a, size_t lda, const float* b, size_t ldb, float* c, size_t ldc, int n)
{
__shared__ float matA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float matB[BLOCK_SIZE][BLOCK_SIZE];
const int tidc = threadIdx.x;
const int tidr = threadIdx.y;
const int bidc = blockIdx.x * BLOCK_SIZE;
const int bidr = blockIdx.y * BLOCK_SIZE;
int i, j;
float results = 0;
float comp = 0;
for(j = 0; j < n; j += BLOCK_SIZE) {
matA[tidr][tidc] = a[(tidr + bidr) * lda + tidc + j];
matB[tidr][tidc] = b[(tidr + j) * ldb + tidc + bidc];
__syncthreads();
for(i = 0; i < BLOCK_SIZE; i++) {
float t;
comp -= matA[tidr][i] * matB[i][tidc];
t = results - comp;
comp = (t - results) + comp;
results = t;
}
__syncthreads();
}
c[(tidr + bidr) * ldc + tidc + bidc] = results;
}
*/
__global__ void matrix_multiply_0(const float* _A,const float *_B,float* _C,int _wa,int _wb)
{
float sum = 0;
//找出该线程所在的行列
int row = blockIdx.y*blockDim.y + threadIdx.y; // X 对应矩阵row, Y对应举证col
int col = blockIdx.x*blockDim.x + threadIdx.x;
//线程Thread(row,col)负责计算C(row,col)
for (int i = 0; i < _wa; ++i)
{
sum += _A[row*_wa + i]*_B[i*_wb + col];
}
_C[row*_wb + col] = sum;
}
__global__ void matrix_multiply_1(float *A, float *B, float *C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
float sum = 0.0f;
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if(row < numCRows && col < numCColumns){
for (int i = 0; i < numAColumns; ++i)
{
sum += A[row*numAColumns + i] * B[i*numBColumns + col];
}
C[row*numBColumns + col] = sum;
}
//printf("C = %f\n",C[row*numBColumns + col]);
}
__global__ void matrix_elementwise_multiply(float * A,float * B,float *C,int width,int height){
int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
int idx = xIndex + yIndex * width;
if(xIndex < width && yIndex < height){
C[idx] = A[idx] * B[idx];
}
}
}
|
#include <hip/hip_runtime.h>
extern "C" {
/*
#define BLOCK_SIZE 16
__global__ void matrix_multiply(const float* a, size_t lda, const float* b, size_t ldb, float* c, size_t ldc, int n)
{
__shared__ float matA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float matB[BLOCK_SIZE][BLOCK_SIZE];
const int tidc = threadIdx.x;
const int tidr = threadIdx.y;
const int bidc = blockIdx.x * BLOCK_SIZE;
const int bidr = blockIdx.y * BLOCK_SIZE;
int i, j;
float results = 0;
float comp = 0;
for(j = 0; j < n; j += BLOCK_SIZE) {
matA[tidr][tidc] = a[(tidr + bidr) * lda + tidc + j];
matB[tidr][tidc] = b[(tidr + j) * ldb + tidc + bidc];
__syncthreads();
for(i = 0; i < BLOCK_SIZE; i++) {
float t;
comp -= matA[tidr][i] * matB[i][tidc];
t = results - comp;
comp = (t - results) + comp;
results = t;
}
__syncthreads();
}
c[(tidr + bidr) * ldc + tidc + bidc] = results;
}
*/
__global__ void matrix_multiply_0(const float* _A,const float *_B,float* _C,int _wa,int _wb)
{
float sum = 0;
//找出该线程所在的行列
int row = blockIdx.y*blockDim.y + threadIdx.y; // X 对应矩阵row, Y对应举证col
int col = blockIdx.x*blockDim.x + threadIdx.x;
//线程Thread(row,col)负责计算C(row,col)
for (int i = 0; i < _wa; ++i)
{
sum += _A[row*_wa + i]*_B[i*_wb + col];
}
_C[row*_wb + col] = sum;
}
__global__ void matrix_multiply_1(float *A, float *B, float *C, int numARows,
int numAColumns, int numBRows, int numBColumns,
int numCRows, int numCColumns) {
//@@ Insert code to implement matrix multiplication here
float sum = 0.0f;
int row = blockIdx.y*blockDim.y + threadIdx.y;
int col = blockIdx.x*blockDim.x + threadIdx.x;
if(row < numCRows && col < numCColumns){
for (int i = 0; i < numAColumns; ++i)
{
sum += A[row*numAColumns + i] * B[i*numBColumns + col];
}
C[row*numBColumns + col] = sum;
}
//printf("C = %f\n",C[row*numBColumns + col]);
}
__global__ void matrix_elementwise_multiply(float * A,float * B,float *C,int width,int height){
int xIndex = threadIdx.x + blockIdx.x * blockDim.x;
int yIndex = threadIdx.y + blockIdx.y * blockDim.y;
int idx = xIndex + yIndex * width;
if(xIndex < width && yIndex < height){
C[idx] = A[idx] * B[idx];
}
}
}
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