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myriadrf/A2300 | hdl/wca/hal/FiFo512Core32W32R/simulation/FiFo512Core32W32R_tb.vhd | 1 | 6,345 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.FiFo512Core32W32R_pkg.ALL;
ENTITY FiFo512Core32W32R_tb IS
END ENTITY;
ARCHITECTURE FiFo512Core32W32R_arch OF FiFo512Core32W32R_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 400 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from FiFo512Core32W32R_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of FiFo512Core32W32R_synth
FiFo512Core32W32R_synth_inst:FiFo512Core32W32R_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 32
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 | 13041571c4994315f7dfafd352f6f92e | 0.600315 | 4.031131 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/async_fifo_fg.vhd | 2 | 129,226 | -------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- async_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009, 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: async_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Async FIFO interface to the new
-- FIFO Generator async FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- async_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/15/2008$
--
-- History:
-- DET 1/15/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added parameter C_ALLOW_2N_DEPTH to enable use of FIFO Generator
-- feature of specifing 2**N depth of FIFO, Legacy CoreGen Async FIFOs
-- only allowed (2**N)-1 depth specification. Parameter is defalted to
-- the legacy CoreGen method so current users are not impacted.
-- - Incorporated calculation and assignment corrections for the Read and
-- Write Pointer Widths.
-- - Upgraded to FIFO Generator Version 4.3.
-- - Corrected a swap of the Rd_Err and the Wr_Err connections on the FIFO
-- Generator instance.
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to 6_1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.coregen_comp_defs.all;
use proc_common_v3_00_a.family_support.all;
-- synopsys translate_off
library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity async_fifo_fg is
generic (
C_ALLOW_2N_DEPTH : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH : integer := 16;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in FG
C_FIFO_DEPTH : integer := 15;
C_HAS_ALMOST_EMPTY : integer := 1 ;
C_HAS_ALMOST_FULL : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_COUNT : integer := 1 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_COUNT : integer := 1 ;
C_HAS_WR_ERR : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_RD_COUNT_WIDTH : integer := 3 ;
C_RD_ERR_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ; -- Valid only for BRAM based FIFO, otherwise needs to be set to 0
C_PRELOAD_REGS : integer := 0 ;
C_PRELOAD_LATENCY : integer := 1 ; -- needs to be set 2 when C_USE_EMBEDDED_REG = 1
C_USE_BLOCKMEM : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
C_WR_ACK_LOW : integer := 0 ;
C_WR_COUNT_WIDTH : integer := 3 ;
C_WR_ERR_LOW : integer := 0
);
port (
Din : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en : in std_logic := '1';
Wr_clk : in std_logic := '1';
Rd_en : in std_logic := '0';
Rd_clk : in std_logic := '1';
Ainit : in std_logic := '1';
Dout : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full : out std_logic;
Empty : out std_logic;
Almost_full : out std_logic;
Almost_empty : out std_logic;
Wr_count : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack : out std_logic;
Rd_err : out std_logic;
Wr_ack : out std_logic;
Wr_err : out std_logic
);
end entity async_fifo_fg;
architecture implementation of async_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_USE_BLOCKMEM.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
FAMILY_IS_SUPPORTED;
Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
FAMILY_IS_SUPPORTED;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_USE_BLOCKMEM);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 2;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising wr clock edge to issue assertion
Wait until Wr_clk = '1';
wait until Wr_clk = '0';
Wait until Wr_clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait; -- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Almost_full <= '0' ; -- : out std_logic;
Almost_empty <= '0' ; -- : out std_logic;
Wr_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_count <= (others => '0'); -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
Rd_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: LEGACY_COREGEN_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User specified depth and count widths follow the
-- legacy CoreGen Async FIFO requirements of depth being
-- (2**N)-1 and the count widths set to reflect the (2**N)-1
-- FIFO depth.
--
-- Special Note:
-- The legacy CoreGen Async FIFOs would only support fifo depths of (2**n)-1
-- and the Dcount widths were 1 less than if a full 2**n depth were supported.
-- Thus legacy IP will be calling this wrapper with the (2**n)-1 FIFo depths
-- specified and the Dcount widths smaller by 1 bit.
-- This wrapper file has to account for this since the new FIFO Generator
-- does not follow this convention for Async FIFOs and expects depths to
-- be specified in full 2**n values.
--
------------------------------------------------------------
LEGACY_COREGEN_DEPTH : if (C_ALLOW_2N_DEPTH = 0 and
FAMILY_IS_SUPPORTED) generate
-- IfGen Constant Declarations -------------
-- See Special Note above for reasoning behind
-- this adjustment of the requested FIFO depth and data count
-- widths.
Constant ADJUSTED_AFIFO_DEPTH : integer := C_FIFO_DEPTH+1;
Constant ADJUSTED_RDCNT_WIDTH : integer := C_RD_COUNT_WIDTH;
Constant ADJUSTED_WRCNT_WIDTH : integer := C_WR_COUNT_WIDTH;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := ADJUSTED_AFIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := ADJUSTED_AFIFO_DEPTH-4;
-- The parameters C_RD_PNTR_WIDTH and C_WR_PNTR_WIDTH for Fifo_generator_v4_3 core
-- must be in the range of 4 thru 22. The setting is dependant upon the
-- log2 function of the MIN and MAX FIFO DEPTH settings in coregen. Since Async FIFOs
-- previous to development of fifo generator do not support separate read and
-- write fifo widths (and depths dependant upon the widths) both of the pointer value
-- calculations below will use the parameter ADJUSTED_AFIFO_DEPTH. The valid range for
-- the ADJUSTED_AFIFO_DEPTH is 16 to 65536 (the async FIFO range is 15 to 65,535...it
-- must be equal to (2^N-1;, N = 4 to 16) per DS232 November 11, 2004 -
-- Asynchronous FIFO v6.1)
Constant ADJUSTED_RD_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
Constant ADJUSTED_WR_PNTR_WIDTH : integer range 4 to 22 := log2(ADJUSTED_AFIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
Constant PROG_RDTHRESH_ZEROS : std_logic_vector(ADJUSTED_RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
Constant PROG_WRTHRESH_ZEROS : std_logic_vector(ADJUSTED_WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- IfGen Signal Declarations --------------
Signal sig_full_fifo_rdcnt : std_logic_vector(ADJUSTED_RDCNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(ADJUSTED_WRCNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V5_AND_EARLIER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using FIFO Generator 4.3
-- for FPGA Families earlier than Virtex-6 and Spartan-6.
--
------------------------------------------------------------
V5_AND_EARLIER : if (FAM_IS_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : fifo_generator_v4_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_USE_ECC => 0,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_INT_CLK => 0,
C_MSGON_VAL => 1 --cannot find info on this, leave at default : integer := 1
)
port map (
CLK => '0',
BACKUP => '0',
BACKUP_MARKER => '0',
DIN => Din,
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS,
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS,
RD_CLK => Rd_clk,
RD_EN => Rd_en,
RD_RST => Ainit,
RST => Ainit,
SRST => '0',
WR_CLK => Wr_clk,
WR_EN => Wr_en,
WR_RST => Ainit,
INT_CLK => '0',
ALMOST_EMPTY => Almost_empty,
ALMOST_FULL => Almost_full,
DATA_COUNT => open,
DOUT => Dout,
EMPTY => Empty,
FULL => Full,
OVERFLOW => Wr_err,
PROG_EMPTY => open,
PROG_FULL => open,
VALID => Rd_ack,
RD_DATA_COUNT => sig_full_fifo_rdcnt,
UNDERFLOW => Rd_err,
WR_ACK => Wr_ack,
WR_DATA_COUNT => sig_full_fifo_wrcnt,
SBITERR => open,
DBITERR => open
);
end generate V5_AND_EARLIER;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : fifo_generator_v9_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJUSTED_RDCNT_WIDTH,
C_RD_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJUSTED_RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJUSTED_WRCNT_WIDTH,
C_WR_DEPTH => ADJUSTED_AFIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJUSTED_WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
BACKUP => '0',
BACKUP_MARKER => '0',
CLK => '0',
RST => Ainit,
SRST => '0',
WR_CLK => Wr_clk,
WR_RST => Ainit,
RD_CLK => Rd_clk,
RD_RST => Ainit,
DIN => Din,
WR_EN => Wr_en,
RD_EN => Rd_en,
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS,
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS,
INT_CLK => '0',
INJECTDBITERR => '0', -- new FG 5.1/5.2
INJECTSBITERR => '0', -- new FG 5.1/5.2
DOUT => Dout,
FULL => Full,
ALMOST_FULL => Almost_full,
WR_ACK => Wr_ack,
OVERFLOW => Wr_err,
EMPTY => Empty,
ALMOST_EMPTY => Almost_empty,
VALID => Rd_ack,
UNDERFLOW => Rd_err,
DATA_COUNT => open,
RD_DATA_COUNT => sig_full_fifo_rdcnt,
WR_DATA_COUNT => sig_full_fifo_wrcnt,
PROG_FULL => open,
PROG_EMPTY => open,
SBITERR => open,
DBITERR => open,
-- AXI Global Signal
M_ACLK => '0', -- : IN std_logic := '0';
S_ACLK => '0', -- : IN std_logic := '0';
S_ARESETN => '0', -- : IN std_logic := '0';
M_ACLK_EN => '0', -- : IN std_logic := '0';
S_ACLK_EN => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID => '0', -- : IN std_logic := '0';
S_AXI_AWREADY => open, -- : OUT std_logic;
S_AXI_WID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST => '0', -- : IN std_logic := '0';
S_AXI_WUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID => '0', -- : IN std_logic := '0';
S_AXI_WREADY => open, -- : OUT std_logic;
S_AXI_BID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER => open, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID => open, -- : OUT std_logic;
S_AXI_BREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER => open, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID => open, -- : OUT std_logic;
M_AXI_AWREADY => '0', -- : IN std_logic := '0';
M_AXI_WID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST => open, -- : OUT std_logic;
M_AXI_WUSER => open, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID => open, -- : OUT std_logic;
M_AXI_WREADY => '0', -- : IN std_logic := '0';
M_AXI_BID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID => '0', -- : IN std_logic := '0';
M_AXI_BREADY => open, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID => '0', -- : IN std_logic := '0';
S_AXI_ARREADY => open, -- : OUT std_logic;
S_AXI_RID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST => open, -- : OUT std_logic;
S_AXI_RUSER => open, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID => open, -- : OUT std_logic;
S_AXI_RREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER => open, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID => open, -- : OUT std_logic;
M_AXI_ARREADY => '0', -- : IN std_logic := '0';
M_AXI_RID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST => '0', -- : IN std_logic := '0';
M_AXI_RUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID => '0', -- : IN std_logic := '0';
M_AXI_RREADY => open, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID => '0', -- : IN std_logic := '0';
S_AXIS_TREADY => open, -- : OUT std_logic;
S_AXIS_TDATA => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB => (others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP => (others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST => '0', -- : IN std_logic := '0';
S_AXIS_TID => (others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER => (others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID => open, -- : OUT std_logic;
M_AXIS_TREADY => '0', -- : IN std_logic := '0';
M_AXIS_TDATA => open, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB => open, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP => open, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST => open, -- : OUT std_logic;
M_AXIS_TID => open, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST => open, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER => open, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AW_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR => open, -- : OUT std_logic;
AXI_AW_DBITERR => open, -- : OUT std_logic;
AXI_AW_OVERFLOW => open, -- : OUT std_logic;
AXI_AW_UNDERFLOW => open, -- : OUT std_logic;
AXI_AW_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_W_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR => open, -- : OUT std_logic;
AXI_W_DBITERR => open, -- : OUT std_logic;
AXI_W_OVERFLOW => open, -- : OUT std_logic;
AXI_W_UNDERFLOW => open, -- : OUT std_logic;
AXI_W_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_B_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR => open, -- : OUT std_logic;
AXI_B_DBITERR => open, -- : OUT std_logic;
AXI_B_OVERFLOW => open, -- : OUT std_logic;
AXI_B_UNDERFLOW => open, -- : OUT std_logic;
AXI_B_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AR_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR => open, -- : OUT std_logic;
AXI_AR_DBITERR => open, -- : OUT std_logic;
AXI_AR_OVERFLOW => open, -- : OUT std_logic;
AXI_AR_UNDERFLOW => open, -- : OUT std_logic;
AXI_AR_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_R_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR => open, -- : OUT std_logic;
AXI_R_DBITERR => open, -- : OUT std_logic;
AXI_R_OVERFLOW => open, -- : OUT std_logic;
AXI_R_UNDERFLOW => open, -- : OUT std_logic;
AXI_R_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXIS_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXIS_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR => open, -- : OUT std_logic;
AXIS_DBITERR => open, -- : OUT std_logic;
AXIS_OVERFLOW => open, -- : OUT std_logic;
AXIS_UNDERFLOW => open, -- : OUT std_logic
AXIS_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY => open -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate LEGACY_COREGEN_DEPTH;
------------------------------------------------------------
-- If Generate
--
-- Label: USE_2N_DEPTH
--
-- If Generate Description:
-- This IfGen implements the FIFO Generator call where
-- the User may specify depth and count widths of 2**N
-- for Async FIFOs The associated count widths are set to
-- reflect the 2**N FIFO depth.
--
------------------------------------------------------------
USE_2N_DEPTH : if (C_ALLOW_2N_DEPTH = 1 and
FAMILY_IS_SUPPORTED) generate
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := C_FIFO_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := C_FIFO_DEPTH-4;
Constant RD_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
Constant WR_PNTR_WIDTH : integer range 4 to 22 := log2(C_FIFO_DEPTH);
-- Constant zeros for programmable threshold inputs
Constant PROG_RDTHRESH_ZEROS : std_logic_vector(RD_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
Constant PROG_WRTHRESH_ZEROS : std_logic_vector(WR_PNTR_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals Declarations
Signal sig_full_fifo_rdcnt : std_logic_vector(C_RD_COUNT_WIDTH-1 DOWNTO 0);
Signal sig_full_fifo_wrcnt : std_logic_vector(C_WR_COUNT_WIDTH-1 DOWNTO 0);
begin
-- Rip the LS bits of the write data count and assign to Write Count
-- output port
Wr_count <= sig_full_fifo_wrcnt(C_WR_COUNT_WIDTH-1 downto 0);
-- Rip the LS bits of the read data count and assign to Read Count
-- output port
Rd_count <= sig_full_fifo_rdcnt(C_RD_COUNT_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: V5_AND_EARLIER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using FIFO Generator 4.3
-- for FPGA Families earlier than Virtex-6 and Spartan-6.
--
------------------------------------------------------------
V5_AND_EARLIER : if (FAM_IS_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : fifo_generator_v4_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_USE_ECC => 0,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_INT_CLK => 0,
C_MSGON_VAL => 1
)
port map (
CLK => '0', -- : IN std_logic := '0';
BACKUP => '0', -- : IN std_logic := '0';
BACKUP_MARKER => '0', -- : IN std_logic := '0';
DIN => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_CLK => Rd_clk, -- : IN std_logic := '0';
RD_EN => Rd_en, -- : IN std_logic := '0';
RD_RST => Ainit, -- : IN std_logic := '0';
RST => Ainit, -- : IN std_logic := '0';
SRST => '0', -- : IN std_logic := '0';
WR_CLK => Wr_clk, -- : IN std_logic := '0';
WR_EN => Wr_en, -- : IN std_logic := '0';
WR_RST => Ainit, -- : IN std_logic := '0';
INT_CLK => '0', -- : IN std_logic := '0';
ALMOST_EMPTY => Almost_empty, -- : OUT std_logic;
ALMOST_FULL => Almost_full, -- : OUT std_logic;
DATA_COUNT => open, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
EMPTY => Empty, -- : OUT std_logic;
FULL => Full, -- : OUT std_logic;
OVERFLOW => Rd_err, -- : OUT std_logic;
PROG_EMPTY => open, -- : OUT std_logic;
PROG_FULL => open, -- : OUT std_logic;
VALID => Rd_ack, -- : OUT std_logic;
RD_DATA_COUNT => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
UNDERFLOW => Wr_err, -- : OUT std_logic;
WR_ACK => Wr_ack, -- : OUT std_logic;
WR_DATA_COUNT => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
SBITERR => open, -- : OUT std_logic;
DBITERR => open -- : OUT std_logic
);
end generate V5_AND_EARLIER;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the FIFO using fifo_generator_v9_3
-- for FPGA Families that are Virtex-6, Spartan-6, and later.
--
------------------------------------------------------------
V6_S6_AND_LATER : if (FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- legacy BRAM implementations of an Async FIFo.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFO_BRAM : fifo_generator_v9_3
generic map(
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DATA_WIDTH,
C_ENABLE_RLOCS => C_ENABLE_RLOCS,
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => C_HAS_RD_COUNT,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => C_HAS_WR_COUNT,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, ----1, Fixed CR#658129
C_PRELOAD_REGS => C_PRELOAD_REGS, ----0, Fixed CR#658129
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_RD_COUNT_WIDTH,
C_RD_DEPTH => C_FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => RD_PNTR_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => C_WR_COUNT_WIDTH,
C_WR_DEPTH => C_FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => WR_PNTR_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map (
BACKUP => '0', -- : IN std_logic := '0';
BACKUP_MARKER => '0', -- : IN std_logic := '0';
CLK => '0', -- : IN std_logic := '0';
RST => Ainit, -- : IN std_logic := '0';
SRST => '0', -- : IN std_logic := '0';
WR_CLK => Wr_clk, -- : IN std_logic := '0';
WR_RST => Ainit, -- : IN std_logic := '0';
RD_CLK => Rd_clk, -- : IN std_logic := '0';
RD_RST => Ainit, -- : IN std_logic := '0';
DIN => Din, -- : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
WR_EN => Wr_en, -- : IN std_logic := '0';
RD_EN => Rd_en, -- : IN std_logic := '0';
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS, -- : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS, -- : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
INT_CLK => '0', -- : IN std_logic := '0';
INJECTDBITERR => '0', -- new FG 5.1 -- : IN std_logic := '0';
INJECTSBITERR => '0', -- new FG 5.1 -- : IN std_logic := '0';
DOUT => Dout, -- : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0);
FULL => Full, -- : OUT std_logic;
ALMOST_FULL => Almost_full, -- : OUT std_logic;
WR_ACK => Wr_ack, -- : OUT std_logic;
OVERFLOW => Rd_err, -- : OUT std_logic;
EMPTY => Empty, -- : OUT std_logic;
ALMOST_EMPTY => Almost_empty, -- : OUT std_logic;
VALID => Rd_ack, -- : OUT std_logic;
UNDERFLOW => Wr_err, -- : OUT std_logic;
DATA_COUNT => open, -- : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
RD_DATA_COUNT => sig_full_fifo_rdcnt, -- : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0);
WR_DATA_COUNT => sig_full_fifo_wrcnt, -- : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0);
PROG_FULL => open, -- : OUT std_logic;
PROG_EMPTY => open, -- : OUT std_logic;
SBITERR => open, -- : OUT std_logic;
DBITERR => open, -- : OUT std_logic
-- AXI Global Signal
M_ACLK => '0', -- : IN std_logic := '0';
S_ACLK => '0', -- : IN std_logic := '0';
S_ARESETN => '0', -- : IN std_logic := '0';
M_ACLK_EN => '0', -- : IN std_logic := '0';
S_ACLK_EN => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID => '0', -- : IN std_logic := '0';
S_AXI_AWREADY => open, -- : OUT std_logic;
S_AXI_WID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST => '0', -- : IN std_logic := '0';
S_AXI_WUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID => '0', -- : IN std_logic := '0';
S_AXI_WREADY => open, -- : OUT std_logic;
S_AXI_BID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER => open, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID => open, -- : OUT std_logic;
S_AXI_BREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER => open, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID => open, -- : OUT std_logic;
M_AXI_AWREADY => '0', -- : IN std_logic := '0';
M_AXI_WID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST => open, -- : OUT std_logic;
M_AXI_WUSER => open, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID => open, -- : OUT std_logic;
M_AXI_WREADY => '0', -- : IN std_logic := '0';
M_AXI_BID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID => '0', -- : IN std_logic := '0';
M_AXI_BREADY => open, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID => '0', -- : IN std_logic := '0';
S_AXI_ARREADY => open, -- : OUT std_logic;
S_AXI_RID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST => open, -- : OUT std_logic;
S_AXI_RUSER => open, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID => open, -- : OUT std_logic;
S_AXI_RREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER => open, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID => open, -- : OUT std_logic;
M_AXI_ARREADY => '0', -- : IN std_logic := '0';
M_AXI_RID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST => '0', -- : IN std_logic := '0';
M_AXI_RUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID => '0', -- : IN std_logic := '0';
M_AXI_RREADY => open, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID => '0', -- : IN std_logic := '0';
S_AXIS_TREADY => open, -- : OUT std_logic;
S_AXIS_TDATA => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB => (others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP => (others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST => '0', -- : IN std_logic := '0';
S_AXIS_TID => (others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER => (others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID => open, -- : OUT std_logic;
M_AXIS_TREADY => '0', -- : IN std_logic := '0';
M_AXIS_TDATA => open, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB => open, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP => open, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST => open, -- : OUT std_logic;
M_AXIS_TID => open, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST => open, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER => open, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AW_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR => open, -- : OUT std_logic;
AXI_AW_DBITERR => open, -- : OUT std_logic;
AXI_AW_OVERFLOW => open, -- : OUT std_logic;
AXI_AW_UNDERFLOW => open, -- : OUT std_logic;
AXI_AW_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_W_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR => open, -- : OUT std_logic;
AXI_W_DBITERR => open, -- : OUT std_logic;
AXI_W_OVERFLOW => open, -- : OUT std_logic;
AXI_W_UNDERFLOW => open, -- : OUT std_logic;
AXI_W_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_B_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR => open, -- : OUT std_logic;
AXI_B_DBITERR => open, -- : OUT std_logic;
AXI_B_OVERFLOW => open, -- : OUT std_logic;
AXI_B_UNDERFLOW => open, -- : OUT std_logic;
AXI_B_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AR_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR => open, -- : OUT std_logic;
AXI_AR_DBITERR => open, -- : OUT std_logic;
AXI_AR_OVERFLOW => open, -- : OUT std_logic;
AXI_AR_UNDERFLOW => open, -- : OUT std_logic;
AXI_AR_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_R_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR => open, -- : OUT std_logic;
AXI_R_DBITERR => open, -- : OUT std_logic;
AXI_R_OVERFLOW => open, -- : OUT std_logic;
AXI_R_UNDERFLOW => open, -- : OUT std_logic;
AXI_R_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXIS_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXIS_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR => open, -- : OUT std_logic;
AXIS_DBITERR => open, -- : OUT std_logic;
AXIS_OVERFLOW => open, -- : OUT std_logic;
AXIS_UNDERFLOW => open, -- : OUT std_logic
AXIS_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY => open -- : OUT STD_LOGIC := '1';
);
end generate V6_S6_AND_LATER;
end generate USE_2N_DEPTH;
-----------------------------------------------------------------------
end implementation;
| bsd-3-clause | 5d93cfc9d2814b72c6ed64c9ecbc94bc | 0.360307 | 4.220727 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/count_fsm.vhd | 11 | 5,764 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common.all;
entity count_fsm is
generic
(
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 32;
C_TWIDTH : integer := 8;
C_MWIDTH : integer := 6;
C_CWIDTH : integer := 8
);
port
(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
finish : out std_logic;
data : out std_logic_vector(0 to C_DWIDTH-1);
mutex : in std_logic_vector(0 to C_MWIDTH-1);
thread : in std_logic_vector(0 to C_TWIDTH-1);
miowner : in std_logic_vector(0 to C_TWIDTH-1);
minext : in std_logic_vector(0 to C_TWIDTH-1);
milast : in std_logic_vector(0 to C_TWIDTH-1);
micount : in std_logic_vector(0 to C_CWIDTH-1);
mikind : in std_logic_vector(0 to 1);
tinext : in std_logic_vector(0 to C_TWIDTH-1);
moaddr : out std_logic_vector(0 to C_MWIDTH-1);
moena : out std_logic;
mowea : out std_logic;
moowner : out std_logic_vector(0 to C_TWIDTH-1);
monext : out std_logic_vector(0 to C_TWIDTH-1);
molast : out std_logic_vector(0 to C_TWIDTH-1);
mocount : out std_logic_vector(0 to C_CWIDTH-1);
mokind : out std_logic_vector(0 to 1);
sysrst : in std_logic;
rstdone : out std_logic;
toaddr : out std_logic_vector(0 to C_TWIDTH-1);
toena : out std_logic;
towea : out std_logic;
tonext : out std_logic_vector(0 to C_TWIDTH-1)
);
end count_fsm;
architecture behavioral of count_fsm is
-- A type for the states in the count fsm
type count_state is
(
IDLE,
READ,
DONE
);
-- Declare signals for the count fsm
signal count_cs : count_state;
signal count_ns : count_state;
-- Alias the location to store the count information
alias cdata : std_logic_vector(0 to C_CWIDTH-1) is data(C_DWIDTH-C_CWIDTH to C_DWIDTH-1);
begin
-- This core resets in one clock cycle so it is always "done"
rstdone <= '1';
count_update : process(clk,rst,sysrst,count_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' or sysrst = '1' ) then
count_cs <= IDLE;
else
count_cs <= count_ns;
end if;
end if;
end process count_update;
count_controller : process(count_cs,start,mutex,micount) is
begin
count_ns <= count_cs;
finish <= '0';
data <= (others => '0');
moaddr <= (others => '0');
moena <= '0';
mowea <= '0';
moowner <= (others => '0');
monext <= (others => '0');
molast <= (others => '0');
mokind <= (others => '0');
mocount <= (others => '0');
toaddr <= (others => '0');
toena <= '0';
towea <= '0';
tonext <= (others => '0');
case count_cs is
when IDLE =>
if( start = '1' ) then
moaddr <= mutex;
moena <= '1';
mowea <= '0';
count_ns <= READ;
end if;
when READ =>
count_ns <= DONE;
when DONE =>
finish <= '1';
cdata <= micount;
count_ns <= IDLE;
end case;
end process count_controller;
end behavioral;
| bsd-3-clause | 20833bb2c17e42dcefbeaf4e653f9f21 | 0.534178 | 4.188953 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/attr_init_2.vhd | 2 | 17,321 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: attr_init_2.c
-- reg2 = * attr
-- reg3 = * function
-- reg4 = thread[i]
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of attr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
-- hthread_attr_init( data->attr );
when STATE_3 =>
reg3_next <= intrfc2thrd_value;
-- Push the argument to hthread_attr_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- Call hthread_attr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
-- hthread_create( &data->thread, &data->attr, data->function, NULL );
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- push &data->attr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_10;
next_state <= WAIT_STATE;
-- retVal = hthread_join( data->thread, NULL );
when STATE_10 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
reg4_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_14;
next_state <= WAIT_STATE;
when STATE_14 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 14eb34d510ae6ad1061694b115a36426 | 0.55043 | 3.738614 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_malloc.vhd | 2 | 12,465 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
STATE1a,
STATE1,
STATE2,
STATE3,
STATE4,
STATE5,
STATE6,
STATE7,
STATE8,
STATE9,
STATE10,
FUNCTION_EXIT,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE10 : std_logic_vector(0 to 15) := x"0110";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
-- constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
-- constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
-- constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
-- constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
-- constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
-- constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
reg1 <= reg1_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE2 =>
current_state <= STATE2;
when U_STATE5 =>
current_state <= STATE5;
when U_STATE7 =>
current_state <= STATE7;
when U_STATE10 =>
current_state <= STATE10;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
reg1_next <= reg1;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
-- Push number of bytes to allocate
thrd2intrfc_value <= x"00000008";
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= STATE1a;
when STATE1a =>
-- Push number of bytes to allocate
thrd2intrfc_value <= x"00000004";
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= STATE1;
when STATE1 =>
-- Call malloc
thrd2intrfc_function <= FUNCTION_CALLOC;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE2;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when STATE2 =>
-- Read the value HWTI gave us
reg1_next <= intrfc2thrd_value;
next_state <= STATE5;
when STATE3 =>
thrd2intrfc_value <= reg1;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= STATE4;
when STATE4 =>
thrd2intrfc_function <= FUNCTION_FREE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE5;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when STATE5 =>
thrd2intrfc_value <= x"00000008";
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= STATE6;
when STATE6 =>
thrd2intrfc_function <= FUNCTION_MALLOC;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE7;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when STATE7 =>
reg1_next <= reg1(16 to 31) & intrfc2thrd_value(16 to 31);
next_state <= STATE8;
when STATE8 =>
thrd2intrfc_value <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= STATE9;
when STATE9 =>
thrd2intrfc_function <= FUNCTION_FREE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE10;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when STATE10 =>
thrd2intrfc_value <= reg1;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 23f84e7de165f61bb34dfc4ebe1db671 | 0.570156 | 3.861524 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_ctrl.vhd | 1 | 78,573 | --------------------------------------------------------------------------------
-- Title : VME IP Core Toplevel
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_ctrl.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 15/12/16
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_ctrl
-- vme_du
-- vme_au
-- vme_locmon
-- vme_mailbox
-- vme_master
-- vme_slave
-- vme_requester
-- vme_bustimer
-- vme_sys_arbiter
-- vme_arbiter
-- vme_wbm
-- vme_wbs
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.10 $
--
-- $Log: vme_ctrl.vhd,v $
-- Revision 1.10 2015/09/16 09:20:07 mwawrik
-- Added generics A16_REG_MAPPING and USE_LONGADD
--
-- Revision 1.9 2015/04/07 14:30:14 AGeissler
-- R1: New signals sl_acc_valid and asn_in_sl_reg
-- M1: Connected these signals to the corresponding component
--
-- Revision 1.8 2014/04/17 07:35:27 MMiehling
-- added generic LONGADD_SIZE
-- added signal prevent_sysrst
--
-- Revision 1.7 2013/09/12 08:45:32 mmiehling
-- added bit 8 of tga for address modifier extension (supervisory, non-privileged data/program)
--
-- Revision 1.6 2012/11/22 09:20:43 MMiehling
-- removed dummy signal
--
-- Revision 1.5 2012/11/15 09:43:55 MMiehling
-- connected each interrupt source to interface in order to support edge triggered msi
--
-- Revision 1.4 2012/11/12 08:13:13 MMiehling
-- changed comments
--
-- Revision 1.3 2012/09/25 11:21:47 MMiehling
-- removed unused signals
--
-- Revision 1.2 2012/08/27 12:57:20 MMiehling
-- general rework
--
-- Revision 1.1 2012/03/29 10:14:49 MMiehling
-- Initial Revision
--
-- Revision 1.14 2010/03/12 13:38:20 mmiehling
-- changed commments
--
-- Revision 1.13 2006/06/02 15:48:57 MMiehling
-- changed comment
--
-- Revision 1.12 2006/05/18 14:29:05 MMiehling
-- added sl_acc for mailbox
--
-- Revision 1.11 2005/02/04 13:44:14 mmiehling
-- added generic simulation; added combinations of addr3+4
--
-- Revision 1.10 2004/11/02 11:29:55 mmiehling
-- moved dma_reg to vme_du
--
-- Revision 1.9 2004/07/27 17:15:39 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.8 2004/06/17 13:02:29 MMiehling
-- removed clr_hit and sl_acc_reg
--
-- Revision 1.7 2003/12/17 15:51:45 MMiehling
-- byte swapping in "not swapped" mode was wrong
--
-- Revision 1.6 2003/12/01 10:03:53 MMiehling
-- changed all
--
-- Revision 1.5 2003/07/14 08:38:08 MMiehling
-- changed rst_counter; added lwordn
--
-- Revision 1.4 2003/06/24 13:47:08 MMiehling
-- removed burst; added loc_keep and rst_aonly
--
-- Revision 1.3 2003/06/13 10:06:35 MMiehling
-- improved
--
-- Revision 1.2 2003/04/22 11:03:00 MMiehling
-- added locmon and mailbox
--
-- Revision 1.1 2003/04/01 13:04:42 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.vme_pkg.all;
ENTITY vme_ctrl IS
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
-- If TRUE, number of bits allocated to vme_adr_out depends on GENERIC LONGADD_SIZE
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
postwr : OUT std_logic; -- posted write indication
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
test_vec : OUT test_vec_type;
-- dma
dma_sta : OUT std_logic_vector(9 DOWNTO 0);
clr_dma_en : IN std_logic;
set_dma_err : IN std_logic;
dma_act_bd : IN std_logic_vector(7 DOWNTO 4);
-- mensb slave
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- mensb master
wbm_stb_o : OUT std_logic;
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_we_o : OUT std_logic;
wbm_sel_o : OUT std_logic_vector(3 DOWNTO 0);
vme_cyc_sram : OUT std_logic;
vme_cyc_pci : OUT std_logic;
wbm_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- the VME signals:
va : INOUT std_logic_vector(31 DOWNTO 0); -- address
vd : INOUT std_logic_vector(31 DOWNTO 0); -- data
vam : INOUT std_logic_vector(5 DOWNTO 0); -- address modifier
writen : INOUT std_logic; -- write enable
iackn : INOUT std_logic; -- Handler's output
irq_i_n : IN std_logic_vector(7 DOWNTO 1); -- interrupt request inputs
irq_o_n : OUT std_logic_vector(7 DOWNTO 1); -- interrupt request outputs
as_o_n : OUT std_logic; -- address strobe out
as_oe_n : OUT std_logic; -- address strobe output enable
as_i_n : IN std_logic; -- address strobe in
sysresn : OUT std_logic; -- system reset out
sysresin : IN std_logic; -- system reset in
ds_o_n : OUT std_logic_vector(1 DOWNTO 0); -- data strobe outputs
ds_i_n : IN std_logic_vector(1 DOWNTO 0); -- data strobe inputs
ds_oe_n : OUT std_logic; -- data strobe output enable
berrn : OUT std_logic; -- bus error out
berrin : IN std_logic; -- bus error in
dtackn : OUT std_logic; -- dtack out
dtackin : IN std_logic; -- dtack in
slot01n : OUT std_logic; -- indicates whether controller has detected position in slot 1 (low active)
sysfail_i_n : IN std_logic; -- system failure interrupt input
sysfail_o_n : OUT std_logic; -- system failure interrupt output
bbsyn : OUT std_logic; -- bus busy out
bbsyin : IN std_logic; -- bus busy in
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus request inputs
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request outputs
iackin : IN std_logic; -- Interrupter's input
iackoutn : OUT std_logic; -- Interrupter's output
acfailn : IN std_logic; -- from Power Supply
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus grant input
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus grant output
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
-- vme status signals
vme_berr : OUT std_logic; -- indicates vme bus error (=MSTR(2)), must be cleared by sw
vme_mstr_busy : OUT std_logic; -- indicates vme bus master is active
--data bus bus control signals for vmebus drivers
d_dir : OUT std_logic; -- external driver control data direction (1: drive to vmebus 0: drive to fpga)
d_oe_n : OUT std_logic; -- external driver control data output enable low active
am_dir : OUT std_logic; -- external driver control address modifier direction (1: drive to vmebus 0: drive to fpga)
am_oe_n : OUT std_logic; -- external driver control address modifier output enable low activ
a_dir : OUT std_logic; -- external driver control address direction (1: drive to vmebus 0: drive to fpga)
a_oe_n : OUT std_logic; -- external driver control address output enable low activ
v2p_rst : OUT std_logic -- Reset between VMEbus and Host CPU
);
END vme_ctrl;
ARCHITECTURE vme_ctrl_arch OF vme_ctrl IS
COMPONENT vme_du
GENERIC (
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
-- If TRUE, number of bits allocated to vme_adr_out depends on GENERIC LONGADD_SIZE
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
-- dma
dma_sta : OUT std_logic_vector(9 DOWNTO 0);
clr_dma_en : IN std_logic;
set_dma_err : IN std_logic;
dma_act_bd : IN std_logic_vector(7 DOWNTO 4);
-- arbiter
sel_reg_data_in : IN std_logic; -- mux select signal for wbb/vme register access
sel_loc_data_out : IN std_logic_vector(1 DOWNTO 0); -- mux select signal for 0=reg, 1=vme data_out
en_wbm_dat_o : IN std_logic; -- enable for wbm_dat_o
-- requester
brl : OUT std_logic_vector(1 DOWNTO 0); -- bus request leve
-- vme_au
int_adr : IN std_logic_vector(18 DOWNTO 0); -- internal adress for reg
int_be : IN std_logic_vector(3 DOWNTO 0); -- internal byte enables
vme_adr_out : IN std_logic_vector(31 DOWNTO 0); -- vme adress lines
byte_routing : IN std_logic; -- mux select for byte routing
vme_adr_in : OUT std_logic_vector(31 DOWNTO 0); -- vme adress input lines
my_iack : IN std_logic;
d64 : IN std_logic; -- indicates d64 mblt
vam_reg : IN std_logic_vector(5 DOWNTO 0); -- registered vam_in for location monitoring and berr_adr (registered with en_vme_adr_in)
vme_adr_in_reg : IN std_logic_vector(31 DOWNTO 2); -- vme adress for location monitoring and berr_adr (registered with en_vme_adr_in)
sl_writen_reg : IN std_logic; -- vme read/wrtie signal (registered with en_vme_adr_in)
iackn_in_reg : IN std_logic; -- iack signal (registered with en_vme_adr_in)
-- sys_arbiter
lwordn : IN std_logic; -- stored for vme slave access
-- ctrl_mux
write_flag : IN std_logic; -- write flag for register write access
-- master
oe_vd : IN std_logic; -- output enable for vme data
oe_va : IN std_logic; -- output enable for vme adress
second_word : IN std_logic; -- indicates data phase of d64
-- slave
sel_vme_data_out : IN std_logic_vector(1 DOWNTO 0); -- mux select for vme data out
en_vme_data_out_reg : IN std_logic; -- register enable for vme data out
en_vme_data_out_reg_high: IN std_logic; -- register enable for vme data out high long
en_vme_data_in_reg : IN std_logic; -- register enable for vme data in
en_vme_data_in_reg_high : IN std_logic; -- register enable for vme data in high long
clr_intreq : IN std_logic; -- clear interrupt request (intr(3) <= '0'
-- wbb_slave
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0); -- indicates dma(1) or normal(0) access
swap : IN std_logic; -- swapps bytes when enabled
-- wbb_master
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_i : IN std_logic_vector(31 DOWNTO 0);
sel_wbm_dat_o : IN std_logic; -- selects between low and high d32
-- register out
longadd : OUT std_logic_vector(7 DOWNTO 0); -- upper 3 address bits for A32 mode or dependent on LONGADD_SIZE
mstr_reg : OUT std_logic_vector(13 DOWNTO 0); -- master register (aonly, postwr, iberr, berr, req, rmw, A16_MODE, A24_MODE, A32_MODE) sysc_reg : OUT std_logic_vector(2 DOWNTO 0); -- system control register (ato, sysr, sysc)
sysc_reg : OUT std_logic_vector(2 DOWNTO 0); -- system control register (ato, sysr, sysc)
slv16_reg : OUT std_logic_vector(4 DOWNTO 0); -- slave A16 base address register
slv24_reg : OUT std_logic_vector(15 DOWNTO 0); -- slave A24 base address register
slv32_reg : OUT std_logic_vector(23 DOWNTO 0); -- slave A32 base address register
slv24_pci_q : OUT std_logic_vector(15 DOWNTO 0); -- slave A24 base address register for PCI
slv32_pci_q : OUT std_logic_vector(23 DOWNTO 0); -- slave A32 base address register for PCI
intr_reg : OUT std_logic_vector(3 DOWNTO 0); -- interrupt request register
pci_offset_q : OUT std_logic_vector(31 DOWNTO 2); -- pci offset address for vme to pci access
-- register bits
set_berr : IN std_logic; -- if bit is set => berr bit will be set
rst_rmw : IN std_logic; -- if bit is set => rmw bit will be cleared
set_sysc : IN std_logic; -- if bit is set => sysc bit will be set
set_ato : IN std_logic; -- if bit is set => ato bit will be set
clr_sysr : IN std_logic; -- if bit is set => sysr bit will be cleared
mail_irq : IN std_logic_vector(7 DOWNTO 0); -- mailbox interrupt flags
loc_am_0 : OUT std_logic_vector(1 DOWNTO 0); -- loc-monitor #0 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_am_1 : OUT std_logic_vector(1 DOWNTO 0); -- loc-monitor #1 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_irq_0 : IN std_logic; -- loc-monitor #0 - irq
loc_irq_1 : IN std_logic; -- loc-monitor #1 - irq
loc_rw_0 : OUT std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_rw_1 : OUT std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_adr_0 : OUT std_logic_vector(31 DOWNTO 0); -- location monitor #0 adress
loc_adr_1 : OUT std_logic_vector(31 DOWNTO 0); -- location monitor #1 adress
loc_sel : IN std_logic_vector(1 DOWNTO 0); -- these bits are loaded with combinations of address bits [4:3] if locmon hit address
rst_aonly : IN std_logic; -- resets aonly bit
clr_locmon : OUT std_logic_vector(1 DOWNTO 0); -- clear address combination bits when clear status bit
-- irq pins
irq_i_n : IN std_logic_vector(7 DOWNTO 1);
irq_o_n : OUT std_logic_vector(7 DOWNTO 1);
acfailn : IN std_logic; -- ACFAIL# input from Power Supply
--vme
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
vd : INOUT std_logic_vector(31 DOWNTO 0);
va : INOUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT vme_sys_arbiter
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
io_ctrl : OUT io_ctrl_type;
ma_io_ctrl : IN io_ctrl_type;
sl_io_ctrl : IN io_ctrl_type;
mensb_req : IN std_logic; -- request signal for mensb slave access
slave_req : IN std_logic; -- request signal for slave access
mstr_busy : IN std_logic; -- master busy
mstr_vme_req : IN std_logic; -- master request VME interface
mensb_active : OUT std_logic; -- acknoledge/active signal for mensb slave access
slave_active : OUT std_logic; -- acknoledge/active signal for slave access
lwordn_slv : IN std_logic; -- stored for vme slave access
lwordn_mstr : IN std_logic; -- master access lwordn
lwordn : OUT std_logic; -- lwordn for vme_du multiplexer
write_flag : OUT std_logic; -- write flag for register access dependent on arbitration
ma_byte_routing : IN std_logic;
sl_byte_routing : IN std_logic;
byte_routing : OUT std_logic;
sl_sel_vme_data_out : IN std_logic_vector(1 DOWNTO 0); -- mux select: 00=wbm_dat_i 01=wbs_dat_i 10=reg_data
sel_vme_data_out : OUT std_logic_vector(1 DOWNTO 0);
ma_oe_vd : IN std_logic; -- master output enable signal for VAD
sl_oe_vd : IN std_logic; -- slave output enable signal for VAD
oe_vd : OUT std_logic; -- output enable signal for VAD
ma_oe_va : IN std_logic; -- master output enable signal for VAD
sl_oe_va : IN std_logic; -- slave output enable signal for VAD
oe_va : OUT std_logic; -- output enable signal for VAD
ma_second_word : IN std_logic; -- differs between address and data phase in d64
sl_second_word : IN std_logic; -- differs between address and data phase in d64
second_word : OUT std_logic; -- differs between address and data phase in d64
ma_en_vme_data_out_reg : IN std_logic;
sl_en_vme_data_out_reg : IN std_logic;
reg_en_vme_data_out_reg : IN std_logic;
en_vme_data_out_reg : OUT std_logic;
ma_en_vme_data_out_reg_high : IN std_logic;
sl_en_vme_data_out_reg_high : IN std_logic;
en_vme_data_out_reg_high : OUT std_logic;
swap : OUT std_logic; -- swapping of data bytes on/off
ma_swap : IN std_logic;
sl_d64 : IN std_logic; -- indicates a d64 burst transmission
ma_d64 : IN std_logic;
d64 : OUT std_logic; -- indicates d64 master access
ma_en_vme_data_in_reg : IN std_logic; -- master enable of vme data in registers
sl_en_vme_data_in_reg : IN std_logic; -- slave enable of vme data in registers
en_vme_data_in_reg : OUT std_logic; -- enable of vme data in registers
ma_en_vme_data_in_reg_high : IN std_logic; -- master enable of vme data high in registers
sl_en_vme_data_in_reg_high : IN std_logic; -- slave enable of vme data high in registers
en_vme_data_in_reg_high : OUT std_logic; -- enable of vme data high in registers
vme_adr_locmon : OUT std_logic_vector(31 DOWNTO 2); -- adress for location monitor (either vme_adr_in or vme_adr_out)
vme_adr_in_reg : IN std_logic_vector(31 DOWNTO 2); -- vme adress sampled with en_vme_adr_in
vme_adr_out : IN std_logic_vector(31 DOWNTO 2); -- vme adress for master access
loc_write_flag : IN std_logic; -- write flag for register access from mensb side
sl_write_flag : IN std_logic -- write flag for register access from vme side
);
END COMPONENT;
COMPONENT vme_wbs
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
-- wbs
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_sel_int : OUT std_logic_vector(3 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
loc_write_flag : OUT std_logic; -- write flag for register
ma_en_vme_data_out_reg : OUT std_logic; -- for normal d32 or d64 low
ma_en_vme_data_out_reg_high: OUT std_logic; -- for d64 high
set_berr : IN std_logic;
wb_dma_acc : OUT std_logic; -- indicates dma_access
mensb_req : OUT std_logic; -- request line for reg access
mensb_active : IN std_logic; -- acknoledge line
vme_acc_type : OUT std_logic_vector(8 DOWNTO 0); -- signal indicates the type of VME access
run_mstr : OUT std_logic; -- starts vme master
mstr_ack : IN std_logic; -- this pulse indicates the end of Master transaction
mstr_busy : IN std_logic; -- if master is busy => 1
burst : OUT std_logic; -- indicates a burst transfer from dma to vme
sel_loc_data_out : OUT std_logic_vector(1 DOWNTO 0) -- mux select signal for 0=reg, 1=vme data_out
);
END COMPONENT;
COMPONENT vme_au
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
-- If TRUE, number of bits allocated to vme_adr_out depends on GENERIC LONGADD_SIZE
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
test : OUT std_logic;
-- mensb slave
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0); -- mensb slave adress lines
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0); -- mensb slave byte enable lines
wbs_we_i : IN std_logic; -- mensb slave read/write
vme_acc_type : IN std_logic_vector(8 DOWNTO 0); -- signal indicates the type of VME slave access
ma_en_vme_data_out_reg : IN std_logic; -- enable of vme_adr_out
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- mensb master
wbm_adr_o : OUT std_logic_vector(31 DOWNTO 0); -- mensb master adress lines
wbm_sel_o : OUT std_logic_vector(3 DOWNTO 0); -- mensb master byte enable lines
wbm_we_o : OUT std_logic; -- mensb master read/write
sram_acc : OUT std_logic; -- sram access is requested by vmebus
pci_acc : OUT std_logic; -- pci access is requested by vmebus
reg_acc : OUT std_logic; -- reg access is requested by vmebus
sl_acc_wb : OUT std_logic_vector(4 DOWNTO 0); -- sampled with ld_loc_adr_cnt
-- vme
vme_adr_in : IN std_logic_vector(31 DOWNTO 0); -- vme address input lines
vme_adr_out : OUT std_logic_vector(31 DOWNTO 0); -- vme address output lines
---------------------------------------------------------------------------------------------------
-- pins to vmebus
asn_in : IN std_logic; -- vme adress strobe input
vam : INOUT std_logic_vector(5 DOWNTO 0); -- vme address modifier
dsan_out : OUT std_logic; -- data strobe byte(0) out
dsbn_out : OUT std_logic; -- data strobe byte(1) out
dsan_in : IN std_logic; -- data strobe byte(0) in
dsbn_in : IN std_logic; -- data strobe byte(1) in
writen : INOUT std_logic; -- write enable tco = tbd. tsu <= tbd. PIN tbd.
iackn : INOUT std_logic; -- handler's output ! PIN tbd.
iackin : IN std_logic; -- vme daisy chain interrupt acknoledge input
iackoutn : OUT std_logic; -- vme daisy chain interrupt acknoledge output
---------------------------------------------------------------------------------------------------
mensb_active : IN std_logic; -- acknoledge/active signal for mensb slave access
-- vme master
mstr_cycle : OUT std_logic; -- number of master cycles should be done (0=1x, 1=2x)
second_word : IN std_logic; -- indicates the second transmission if in D16 mode and 32bit should be transmitted
dsn_ena : IN std_logic; -- signal switches dsan_out and dsbn_out on and off
vam_oe : IN std_logic; -- vam output enable
ma_d64 : OUT std_logic; -- indicates a d64 burst transmission
sl_d64 : OUT std_logic; -- indicates a d64 burst transmission
-- vme slave
sl_acc : OUT std_logic_vector(4 DOWNTO 0); -- slave access hits and burst data transmission type
sl_acc_valid : OUT std_logic; -- sl_acc has been calculated and is valid
asn_in_sl_reg : IN std_logic; -- registered asn signal
ld_loc_adr_m_cnt : IN std_logic; -- load address counter
inc_loc_adr_m_cnt : IN std_logic; -- increment address counter
sl_inc_loc_adr_m_cnt : IN std_logic; -- increment address counter
sl_writen_reg : OUT std_logic;
iackn_in_reg : OUT std_logic; -- iack signal (registered with en_vme_adr_in)
my_iack : OUT std_logic;
clr_intreq : IN std_logic; -- clear interrupt request (intr(3) <= '0'
sl_en_vme_data_in_reg : IN std_logic; -- register enable for vme data in
en_vme_adr_in : IN std_logic; -- samples adress and am after asn goes low
-- vme_sys_arbiter
sl_byte_routing : OUT std_logic; -- to mensb byte routing
ma_byte_routing : OUT std_logic; -- signal for byte swapping
sl_sel_vme_data_out : OUT std_logic_vector(1 DOWNTO 0); -- mux select: 00=loc_data_in_m 01=loc_data_in_s 10=reg_data
lwordn_slv : OUT std_logic; -- stored for vme slave access
lwordn_mstr : OUT std_logic; -- master access lwordn
-- locmon
vam_reg : OUT std_logic_vector(5 DOWNTO 0); -- registered vam_in for location monitoring and berr_adr (registered with en_vme_adr_in)
vme_adr_in_reg : OUT std_logic_vector(31 DOWNTO 2); -- vme adress for location monitoring and berr_adr (registered with en_vme_adr_in)
-- vme_du
mstr_reg : IN std_logic_vector(13 DOWNTO 0); -- master register (aonly, postwr, iberr, berr, req, rmw, A16_MODE, A24_MODE, A32_MODE)
longadd : IN std_logic_vector(7 DOWNTO 0); -- upper 3 address bits for A32 mode or dependent on LONGADD_SIZE
slv16_reg : IN std_logic_vector(4 DOWNTO 0); -- slave A16 base address register
slv24_reg : IN std_logic_vector(15 DOWNTO 0); -- slave A24 base address register
slv32_reg : IN std_logic_vector(23 DOWNTO 0); -- slave A32 base address register
slv24_pci_q : IN std_logic_vector(15 DOWNTO 0); -- slave A24 base address register for PCI
slv32_pci_q : IN std_logic_vector(23 DOWNTO 0); -- slave A32 base address register for PCI
intr_reg : IN std_logic_vector(3 DOWNTO 0); -- interrupt request register
sysc_reg : IN std_logic_vector(2 DOWNTO 0); -- system control register (ato, sysr, sysc)
pci_offset_q : IN std_logic_vector(31 DOWNTO 2); -- pci offset address for vme to pci access
int_be : OUT std_logic_vector(3 DOWNTO 0); -- internal byte enables
int_adr : OUT std_logic_vector(18 DOWNTO 0) -- internal adress
);
END COMPONENT;
COMPONENT vme_master
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic;
test_c : OUT std_logic;
-- control signals from/to mensb_slave
run_mstr : IN std_logic; -- this pulse triggers start of Master
mstr_ack : OUT std_logic; -- this pulse indicates the end of Master transaction
mstr_busy : OUT std_logic; -- master busy, set when running
vme_req : out std_logic; -- request VME interface access
burst : IN std_logic; -- indicates a vme burst request
ma_en_vme_data_in_reg : OUT std_logic; -- load register signal in data switch unit for rd vme
ma_en_vme_data_in_reg_high : OUT std_logic; -- load high register signal in data switch unit for rd vme
brel : OUT std_logic; -- release signal for Requester
wbs_we_i : IN std_logic; -- read /write
wb_dma_acc : IN std_logic; -- indicates dma_access
-- requester
dwb : OUT std_logic; -- device wants vme bus
dgb : IN std_logic; -- device gets vme bus
-------------------------------------------------------------------------------
-- PINs:
-- control signals from VMEbus:
berrn_in : IN std_logic; -- vme bus error signal
dtackn_in : IN std_logic; -- vme bus data acknoledge signal
-- control signals to VMEbus
asn_out : OUT std_logic;
-------------------------------------------------------------------------------
-- connected with vme_du:
rst_rmw : OUT std_logic; -- if bit is set => berr bit will be set
set_berr : OUT std_logic; -- if bit is set => rmw bit will be cleared
ma_oe_vd : OUT std_logic; -- output enable for vme data
ma_oe_va : OUT std_logic; -- output enable for vme adress
mstr_reg : IN std_logic_vector(5 DOWNTO 0); -- master configuration register(BERR-bit, REQ-bit, RMW-bit)
rst_aonly : OUT std_logic; -- resets aonly bit
-- connected with vme_au
dsn_ena : OUT std_logic; -- signal switches dsan and dsbn on and off
mstr_cycle : IN std_logic; -- signal indicates one or two cycles must be done
second_word : OUT std_logic; -- signal indicates the actual master cycle
vam_oe : OUT std_logic; -- vam output enable
d64 : IN std_logic; -- indicates a d64 burst transmission
-- connected with slave:
asn_in : IN std_logic; -- to detect a transaction
--data bus bus control signals for vmebus drivers
ma_io_ctrl : OUT io_ctrl_type
);
END COMPONENT;
COMPONENT vme_requester
PORT (
clk : IN std_logic;
rst : IN std_logic;
-------------------------------------------------------------------------------
-- PINS:
-- Requesters Pins:
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus requests monitored (FAIR)
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- passed in idle state
bbsyn_in : IN std_logic;
bbsyn : OUT std_logic; -- bus busy signal
-------------------------------------------------------------------------------
-- connected with PowerPC Access
dwb : IN std_logic;
dgb : OUT std_logic;
FairReqEn : IN std_logic;
brl : IN std_logic_vector(1 DOWNTO 0); -- bus request level
-- from Arbiter:
bgintn : IN std_logic_vector(3 DOWNTO 0); -- from internal Arbiter if in Slot 1,
-- else outside from VMEbus
-- connected with master unit:
req_bit : IN std_logic; -- '0'= release on request; '1'= release when done
brel : IN std_logic -- indicates whether the bus arbitration can be released
);
END COMPONENT;
COMPONENT vme_arbiter
PORT (
clk : IN std_logic;
rst : IN std_logic;
bgintn : OUT std_logic_vector(3 DOWNTO 0); -- bus grant for all levels
-- vme_du
set_ato : OUT std_logic; -- if bit is set => ato bit will be set
sysc_bit : IN std_logic; -- '1' if board is in slot 1 => enables this vme arbiter
bgouten : IN std_logic; -- enables SGL and bg3out signal
-- PINs:
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus requests monitored (FAIR)
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- passed in idle state
bbsyn_in : IN std_logic
);
END COMPONENT;
COMPONENT vme_bustimer
PORT (
clk : IN std_logic; -- global clock
rst : IN std_logic; -- global reset
startup_rst : IN std_logic; -- powerup reset
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
set_sysc : OUT std_logic; -- if set sysc-bit will be set
sysc_bit : IN std_logic; -- 1=slot1 0=slotx
clr_sysr : OUT std_logic; -- if set sysr-bit will be cleared
sysr_bit : IN std_logic; -- 1=system reset
-- connected with Slave Unit
dsain : IN std_logic; -- data strobe a in
dsbin : IN std_logic; -- data strobe b in
bgouten : OUT std_logic; -- enables SGL and bg3out signal
-- bus grant daisy chain is driven through requester in Access VME:
-----------------------------------------------------------------------
-- PINs:
sysfailn : OUT std_logic; -- indicates when A15 is not ready or in reset
sysrstn_in : IN std_logic;
sysrstn_out : OUT std_logic;
v2p_rst : OUT std_logic; -- Reset between VMEbus and Host CPU
bg3n_in : IN std_logic; -- bus grant signal in (if not connected => slot01)
slot01n : OUT std_logic; -- enables V_SYSCLK (16 MHz)
berrn_out : OUT std_logic -- bus error
);
END COMPONENT;
COMPONENT vme_slave
PORT (
clk : IN std_logic; -- this Unit works at 66 MHz
rst : IN std_logic;
-------------------------------------------------------------------------------
-- PINS (VMEbus, inputs asynchronous !):
asn_in : IN std_logic; -- vme adress strobe input
dsan_in : IN std_logic; -- vme data strobe A input
dsbn_in : IN std_logic; -- vme data strobe B input
dtackn_out : OUT std_logic; -- vme data acknowledge output
sl_writen_reg : IN std_logic; -- vme read/write
-------------------------------------------------------------------------------
-- vme-mstr
mstr_busy : IN std_logic; -- if set, vme-master is busy
-- vme_au
sl_acc : IN std_logic_vector(4 DOWNTO 0); -- A16 hit, A24 hit, A32 hit, D32 blt, D64 blt
sl_acc_valid : IN std_logic; -- sl_acc has been calculated and is valid
my_iack : IN std_logic;
wbm_we_o : IN std_logic; -- mensb master read/write
reg_acc : IN std_logic; -- reg access is requested by vmebus
en_vme_adr_in : OUT std_logic; -- samples adress and am after asn goes low
asn_in_sl_reg : OUT std_logic; -- registered asn signal
-- sys_arbiter
slave_req : OUT std_logic; -- request signal for slave access
slave_active : IN std_logic; -- acknowledge/active signal for slave access
sl_write_flag : OUT std_logic; -- write flag for register access from vme side
sl_second_word : OUT std_logic; -- differs between address and data phase in d64 accesses
-- vme_du
sl_en_vme_data_in_reg : OUT std_logic; -- enable vme input reg
sl_en_vme_data_in_reg_high : OUT std_logic; -- slave enable of vme data high in registers
sl_oe_vd : OUT std_logic; -- output enable for vme data
sl_oe_va : OUT std_logic; -- output enable for vme adress
reg_en_vme_data_out_reg : OUT std_logic; -- enable vme output reg
sl_io_ctrl : OUT io_ctrl_type;
ld_loc_adr_m_cnt : OUT std_logic; -- load address counter
sl_inc_loc_adr_m_cnt : OUT std_logic; -- increment address counter
clr_intreq : OUT std_logic; -- clear interrupt request (intr(3) <= '0'
-- mensb_master
loc_keep : OUT std_logic; -- if '1', csn remains active (keeps bus)
mensb_mstr_req : OUT std_logic; -- mensb master request
mensb_mstr_ack : IN std_logic -- mensb master acknowledge
);
END COMPONENT;
COMPONENT vme_wbm
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- mensb master
loc_keep : IN std_logic; -- if '1', csn remains active (keeps bus)
wbm_stb_o : OUT std_logic;
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_we_o : IN std_logic;
vme_cyc_sram : OUT std_logic; -- keeps bus arbitration to sram as long as active
vme_cyc_pci : OUT std_logic; -- keeps bus arbitration to pci as long as active
-- vme_slave
mensb_mstr_req : IN std_logic; -- mensb master request
mensb_mstr_ack : OUT std_logic; -- mensb master acknoledge
-- vme_du
sel_wbm_dat_o : OUT std_logic;
en_wbm_dat_o : OUT std_logic;
sl_en_vme_data_out_reg : OUT std_logic; -- for normal d32 or d64 low
sl_en_vme_data_out_reg_high : OUT std_logic; -- for d64 high
-- vme_au
inc_loc_adr_m_cnt : OUT std_logic;
sl_acc_wb : IN std_logic_vector(4 DOWNTO 0); -- slave access hits and burst data transmission type
pci_acc : IN std_logic; -- pci access is requested by vmebus
sram_acc : IN std_logic -- sram access is requested by vmebus
);
END COMPONENT;
COMPONENT vme_mailbox
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
sl_acc : IN std_logic_vector(4 DOWNTO 0); -- slave access address type (sl16_hit, sl24_hit, sl32_hit, sl_blt32, sl_blt64)
wbm_adr_o : IN std_logic_vector(19 DOWNTO 2); -- mensb master adress lines
wbm_we_o : IN std_logic; -- mensb master read/write
mensb_mstr_req : IN std_logic; -- mensb master request
ram_acc : IN std_logic; -- external ram access
mail_irq : OUT std_logic_vector(7 DOWNTO 0) -- mailbox interrupt requests (flags)
);
END COMPONENT;
COMPONENT vme_locmon
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
en_vme_adr_in : IN std_logic; -- samples adress and am after asn goes low
ma_en_vme_data_out_reg : IN std_logic; -- enable of vme_adr_out
sl_writen_reg : IN std_logic; -- vme write/read
vme_adr_locmon : IN std_logic_vector(31 DOWNTO 2); -- vme adress for location monitoring (registered with en_vme_adr_in)
vam_reg : IN std_logic_vector(5 DOWNTO 0); -- vme registered vam_in
clr_locmon : IN std_logic_vector(1 DOWNTO 0); -- clear address combination bits when clear status bit
loc_sel : OUT std_logic_vector(1 DOWNTO 0); -- these bits are loaded with combinations of address bits [4:3] if locmon hit address
loc_am_0 : IN std_logic_vector(1 DOWNTO 0); -- loc-monitor #0 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_am_1 : IN std_logic_vector(1 DOWNTO 0); -- loc-monitor #1 - adress modus "00"-A32, "10"-A16, "11"-A24
loc_irq_0 : OUT std_logic; -- loc-monitor #0 - irq
loc_irq_1 : OUT std_logic; -- loc-monitor #1 - irq
loc_rw_0 : IN std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_rw_1 : IN std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
loc_adr_0 : IN std_logic_vector(31 DOWNTO 0); -- location monitor #0 adress
loc_adr_1 : IN std_logic_vector(31 DOWNTO 0) -- location monitor #1 adress
);
END COMPONENT;
SIGNAL oe_vme_an : std_logic; -- data output enable A->B
SIGNAL oe_vme_dn : std_logic; -- data latch enable A->B
SIGNAL l_fpga_an : std_logic; -- address output enable B->A
SIGNAL oe_fpga_an : std_logic; -- address output enable A->B
SIGNAL dir_vam : std_logic;
-- vme_wbs
SIGNAL loc_write_flag : std_logic;
SIGNAL sel_loc_data_out : std_logic_vector(1 DOWNTO 0);
SIGNAL mensb_req : std_logic;
SIGNAL vme_acc_type : std_logic_vector(8 DOWNTO 0); -- signal indicates the type of VME access
SIGNAL ma_en_vme_data_out_reg : std_logic;
SIGNAL wb_dma_acc : std_logic; -- indicates dma_access
-- mensb_mstr
SIGNAL mensb_mstr_ack : std_logic;
SIGNAL wbs_sel_int : std_logic_vector(3 DOWNTO 0);
SIGNAL burst : std_logic;
SIGNAL sel_wbm_dat_o : std_logic;
-- vme_du
SIGNAL clr_locmon : std_logic_vector(1 DOWNTO 0); -- clear address combination bits when clear status bit
SIGNAL vme_adr_out : std_logic_vector(31 DOWNTO 0);
SIGNAL mstr_reg : std_logic_vector(13 DOWNTO 0);
SIGNAL sysc_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL longadd : std_logic_vector(7 DOWNTO 0);
SIGNAL slv16_reg : std_logic_vector(4 DOWNTO 0);
SIGNAL slv24_reg : std_logic_vector(15 DOWNTO 0);
SIGNAL slv32_reg : std_logic_vector(23 DOWNTO 0);
SIGNAL slv24_pci_q : std_logic_vector(15 DOWNTO 0); -- slave A24 base address register
SIGNAL slv32_pci_q : std_logic_vector(23 DOWNTO 0); -- slave A32 base address register
SIGNAL intr_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL loc_am_0 : std_logic_vector(1 DOWNTO 0); -- loc-monitor #0 - adress modus "00"-A32, "10"-A16, "11"-A24
SIGNAL loc_am_1 : std_logic_vector(1 DOWNTO 0); -- loc-monitor #1 - adress modus "00"-A32, "10"-A16, "11"-A24
SIGNAL loc_irq_0 : std_logic; -- loc-monitor #0 - irq
SIGNAL loc_irq_1 : std_logic; -- loc-monitor #1 - irq
SIGNAL loc_rw_0 : std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
SIGNAL loc_rw_1 : std_logic_vector(1 DOWNTO 0); -- [0]: read; [1]: write
SIGNAL loc_adr_0 : std_logic_vector(31 DOWNTO 0); -- location monitor #0 adress
SIGNAL loc_adr_1 : std_logic_vector(31 DOWNTO 0); -- location monitor #1 adress
SIGNAL loc_sel : std_logic_vector(1 DOWNTO 0); -- these bits are loaded with address bits [4:3] if locmon hit address
SIGNAL pci_offset_q : std_logic_vector(31 DOWNTO 2); -- pci offset address for vme to pci access
SIGNAL FairReqEn : std_logic;
SIGNAL brl : std_logic_vector(1 DOWNTO 0);
-- vme_au
SIGNAL sl_acc_wb : std_logic_vector(4 DOWNTO 0); -- sampled with ld_loc_adr_cnt
SIGNAL ma_d64 : std_logic;
SIGNAL sl_d64 : std_logic;
SIGNAL vam_reg : std_logic_vector(5 DOWNTO 0);
SIGNAL int_adr : std_logic_vector(18 DOWNTO 0);
SIGNAL vme_adr_in : std_logic_vector(31 DOWNTO 0);
SIGNAL wbm_adr_o_int : std_logic_vector(31 DOWNTO 0);
SIGNAL sl_sel_vme_data_out : std_logic_vector(1 DOWNTO 0);
SIGNAL int_be : std_logic_vector(3 DOWNTO 0);
SIGNAL ma_byte_routing : std_logic;
SIGNAL sl_byte_routing : std_logic;
SIGNAL sl_acc : std_logic_vector(4 DOWNTO 0);
SIGNAL sl_writen_reg : std_logic;
SIGNAL iackn_in_reg : std_logic; -- iack signal (registered with en_vme_adr_in)
SIGNAL reg_acc : std_logic;
SIGNAL sram_acc : std_logic;
SIGNAL pci_acc : std_logic;
SIGNAL clr_intreq : std_logic;
SIGNAL my_iack : std_logic;
SIGNAL wbm_we_o_int : std_logic;
SIGNAL lwordn_slv : std_logic; -- stored for vme slave access
SIGNAL lwordn_mstr : std_logic; -- master access lwordn
SIGNAL vme_adr_in_reg : std_logic_vector(31 DOWNTO 2);
-- vme_sys_arbiter
SIGNAL d64 : std_logic;
SIGNAL vme_adr_locmon : std_logic_vector(31 DOWNTO 2);
SIGNAL en_wbm_dat_o : std_logic; -- enable for wbm_dat_o
SIGNAL sel_vme_data_out : std_logic_vector(1 DOWNTO 0);
SIGNAL mensb_active : std_logic;
SIGNAL slave_active : std_logic;
SIGNAL write_flag : std_logic;
SIGNAL byte_routing : std_logic;
SIGNAL oe_va : std_logic;
SIGNAL oe_vd : std_logic;
SIGNAL en_vme_data_out_reg : std_logic;
SIGNAL ma_en_vme_data_out_reg_high : std_logic:='0';
SIGNAL sl_en_vme_data_out_reg_high : std_logic;
SIGNAL en_vme_data_out_reg_high : std_logic:='0';
SIGNAL en_vme_data_in_reg : std_logic;
SIGNAL lwordn : std_logic; -- lwordn for vme_du multiplexer
SIGNAL swap : std_logic;
SIGNAL en_vme_data_in_reg_high : std_logic:='0';
SIGNAL l_fpga_an_int : std_logic;
-- vme_master
SIGNAL ma_oe_va : std_logic;
SIGNAL ma_oe_vd : std_logic;
SIGNAL ma_en_vme_data_in_reg : std_logic;
SIGNAL ma_en_vme_data_in_reg_high : std_logic; -- load high register signal in data switch unit for rd vme
SIGNAL dwb : std_logic;
SIGNAL run_mstr : std_logic;
SIGNAL mstr_busy : std_logic;
SIGNAL mstr_vme_req : std_logic;
SIGNAL mstr_ack : std_logic;
SIGNAL brel : std_logic;
SIGNAL rst_rmw : std_logic;
SIGNAL set_berr : std_logic;
SIGNAL dsn_ena : std_logic;
SIGNAL mstr_cycle : std_logic;
SIGNAL sl_second_word : std_logic;
SIGNAL ma_second_word : std_logic;
SIGNAL second_word : std_logic;
SIGNAL vam_oe : std_logic;
SIGNAL oe_vme_an_m : std_logic;
SIGNAL oe_vme_dn_m : std_logic;
SIGNAL oe_fpga_an_m : std_logic;
SIGNAL l_fpga_an_m : std_logic;
SIGNAL rst_aonly : std_logic;
SIGNAL asn_out : std_logic;
SIGNAL ds_o_n_int : std_logic_vector(1 DOWNTO 0);
-- vme_slave
SIGNAL sl_acc_valid : std_logic;
SIGNAL asn_in_sl_reg : std_logic;
SIGNAL sl_en_vme_data_out_reg : std_logic;
SIGNAL reg_en_vme_data_out_reg : std_logic;
SIGNAL sl_write_flag : std_logic;
SIGNAL sl_oe_va : std_logic;
SIGNAL sl_oe_vd : std_logic;
SIGNAL sl_en_vme_data_in_reg : std_logic;
SIGNAL sl_en_vme_data_in_reg_high : std_logic;
SIGNAL slave_req : std_logic;
SIGNAL ld_loc_adr_m_cnt : std_logic;
SIGNAL inc_loc_adr_m_cnt : std_logic;
SIGNAL sl_inc_loc_adr_m_cnt : std_logic;
SIGNAL mensb_mstr_req : std_logic;
SIGNAL loc_keep : std_logic; -- if '1', csn remains active (keeps bus)
SIGNAL en_vme_adr_in : std_logic; -- samples adress and am after asn goes low
-- bustimer
SIGNAL set_sysc : std_logic:='0';
SIGNAL bgouten : std_logic;
SIGNAL clr_sysr : std_logic;
-- location
-- vmearbiter
SIGNAL bgintn : std_logic_vector(3 DOWNTO 0);
SIGNAL set_ato : std_logic;
-- interrupter
-- handler
-- requester
SIGNAL dgb : std_logic;
-- mailbox
SIGNAL mail_irq : std_logic_vector(7 DOWNTO 0);
SIGNAL io_ctrl : io_ctrl_type;
SIGNAL ma_io_ctrl : io_ctrl_type;
SIGNAL sl_io_ctrl : io_ctrl_type;
BEGIN
d_dir <= io_ctrl.d_dir ; -- NOT oe_fpga_dn_int;
d_oe_n <= io_ctrl.d_oe_n ; -- '0';
am_dir <= io_ctrl.am_dir ; -- dir_vam;
am_oe_n <= io_ctrl.am_oe_n; -- '0';
a_dir <= io_ctrl.a_dir ; -- ;
a_oe_n <= io_ctrl.a_oe_n ; -- '0';
test_vec.ato <= sysc_reg(2);
ds_oe_n <= '0' WHEN ds_o_n_int(0) = '0' OR ds_o_n_int(1) = '0' ELSE '1';
ds_o_n <= ds_o_n_int;
as_o_n <= asn_out;
as_oe_n <= asn_out;
vme_mstr_busy <= mstr_busy;
vme_berr <= mstr_reg(2);
postwr <= mstr_reg(4);
FairReqEn <= mstr_reg(6);
wbm_we_o <= wbm_we_o_int;
wbm_adr_o <= wbm_adr_o_int;
du : vme_du
GENERIC MAP (
LONGADD_SIZE => LONGADD_SIZE,
USE_LONGADD => USE_LONGADD
)
PORT MAP (
clk => clk,
rst => rst,
dma_sta => dma_sta,
clr_dma_en => clr_dma_en,
set_dma_err => set_dma_err,
dma_act_bd => dma_act_bd,
wbm_err_i => wbm_err_i,
wbm_ack_i => wbm_ack_i,
startup_rst => startup_rst,
vme_irq => vme_irq,
berr_irq => berr_irq,
locmon_irq => locmon_irq ,
mailbox_irq => mailbox_irq,
write_flag => write_flag,
d64 => d64,
vam_reg => vam_reg,
vme_adr_in_reg => vme_adr_in_reg,
sl_writen_reg => sl_writen_reg,
iackn_in_reg => iackn_in_reg,
sel_reg_data_in => mensb_active,
sel_loc_data_out => sel_loc_data_out,
en_wbm_dat_o => en_wbm_dat_o,
brl => brl,
second_word => second_word,
sel_wbm_dat_o => sel_wbm_dat_o,
wbs_tga_i => wbs_tga_i,
swap => swap,
lwordn => lwordn,
int_adr => int_adr,
int_be => int_be,
clr_intreq => clr_intreq,
vme_adr_out => vme_adr_out,
byte_routing => byte_routing,
vme_adr_in => vme_adr_in,
oe_va => oe_va,
oe_vd => oe_vd,
sel_vme_data_out => sel_vme_data_out,
en_vme_data_out_reg => en_vme_data_out_reg,
en_vme_data_out_reg_high => en_vme_data_out_reg_high,
en_vme_data_in_reg => en_vme_data_in_reg,
en_vme_data_in_reg_high => en_vme_data_in_reg_high,
clr_locmon => clr_locmon,
longadd => longadd,
mstr_reg => mstr_reg,
sysc_reg => sysc_reg,
set_berr => set_berr,
my_iack => my_iack,
rst_rmw => rst_rmw,
set_sysc => set_sysc,
set_ato => set_ato,
clr_sysr => clr_sysr,
wbs_dat_o => wbs_dat_o,
wbs_dat_i => wbs_dat_i,
wbm_dat_o => wbm_dat_o,
wbm_dat_i => wbm_dat_i,
slv16_reg => slv16_reg,
slv24_reg => slv24_reg,
slv32_reg => slv32_reg,
slv24_pci_q => slv24_pci_q,
slv32_pci_q => slv32_pci_q,
mail_irq => mail_irq,
loc_am_0 => loc_am_0,
loc_am_1 => loc_am_1,
loc_irq_0 => loc_irq_0,
loc_irq_1 => loc_irq_1,
loc_rw_0 => loc_rw_0,
loc_rw_1 => loc_rw_1,
loc_adr_0 => loc_adr_0,
loc_adr_1 => loc_adr_1,
loc_sel => loc_sel,
intr_reg => intr_reg,
pci_offset_q => pci_offset_q,
rst_aonly => rst_aonly,
irq_i_n => irq_i_n,
irq_o_n => irq_o_n,
acfailn => acfailn,
ga => ga,
gap => gap,
vd => vd,
va => va
);
sys_arbiter : vme_sys_arbiter
PORT MAP (
clk => clk,
rst => rst,
io_ctrl => io_ctrl,
ma_io_ctrl => ma_io_ctrl,
sl_io_ctrl => sl_io_ctrl,
mensb_req => mensb_req,
slave_req => slave_req,
mstr_busy => mstr_busy,
mstr_vme_req => mstr_vme_req,
mensb_active => mensb_active,
slave_active => slave_active,
lwordn_slv => lwordn_slv,
lwordn_mstr => lwordn_mstr,
lwordn => lwordn,
write_flag => write_flag,
ma_byte_routing => ma_byte_routing,
sl_byte_routing => sl_byte_routing,
byte_routing => byte_routing,
sl_sel_vme_data_out => sl_sel_vme_data_out,
sel_vme_data_out => sel_vme_data_out,
oe_vd => oe_vd,
ma_oe_vd => ma_oe_vd,
sl_oe_vd => sl_oe_vd,
oe_va => oe_va,
ma_oe_va => ma_oe_va,
sl_oe_va => sl_oe_va,
ma_second_word => ma_second_word,
sl_second_word => sl_second_word,
second_word => second_word,
ma_en_vme_data_out_reg => ma_en_vme_data_out_reg,
sl_en_vme_data_out_reg => sl_en_vme_data_out_reg,
reg_en_vme_data_out_reg => reg_en_vme_data_out_reg,
en_vme_data_out_reg => en_vme_data_out_reg,
ma_en_vme_data_out_reg_high => ma_en_vme_data_out_reg_high,
sl_en_vme_data_out_reg_high => sl_en_vme_data_out_reg_high,
en_vme_data_out_reg_high => en_vme_data_out_reg_high,
swap => swap,
ma_swap => vme_acc_type(5),
ma_d64 => ma_d64,
sl_d64 => sl_d64,
d64 => d64,
ma_en_vme_data_in_reg => ma_en_vme_data_in_reg,
sl_en_vme_data_in_reg => sl_en_vme_data_in_reg,
en_vme_data_in_reg => en_vme_data_in_reg,
ma_en_vme_data_in_reg_high => ma_en_vme_data_in_reg_high,
sl_en_vme_data_in_reg_high => sl_en_vme_data_in_reg_high,
en_vme_data_in_reg_high => en_vme_data_in_reg_high,
vme_adr_locmon => vme_adr_locmon,
vme_adr_in_reg => vme_adr_in_reg,
vme_adr_out => vme_adr_out(31 DOWNTO 2),
loc_write_flag => loc_write_flag,
sl_write_flag => sl_write_flag
);
wbs : vme_wbs
PORT MAP (
clk => clk,
rst => rst,
set_berr => set_berr,
wbs_stb_i => wbs_stb_i,
wbs_ack_o => wbs_ack_o,
wbs_err_o => wbs_err_o,
wbs_we_i => wbs_we_i,
wbs_cyc_i => wbs_cyc_i,
wbs_adr_i => wbs_adr_i,
wbs_sel_i => wbs_sel_i,
wbs_sel_int => wbs_sel_int,
wbs_tga_i => wbs_tga_i,
wb_dma_acc => wb_dma_acc,
loc_write_flag => loc_write_flag,
ma_en_vme_data_out_reg => ma_en_vme_data_out_reg,
ma_en_vme_data_out_reg_high => ma_en_vme_data_out_reg_high,
mensb_req => mensb_req,
mensb_active => mensb_active,
vme_acc_type => vme_acc_type,
run_mstr => run_mstr,
mstr_ack => mstr_ack,
mstr_busy => mstr_busy,
burst => burst,
sel_loc_data_out => sel_loc_data_out
);
au : vme_au
GENERIC MAP (
A16_REG_MAPPING => A16_REG_MAPPING,
LONGADD_SIZE => LONGADD_SIZE,
USE_LONGADD => USE_LONGADD
)
PORT MAP (
clk => clk,
rst => rst,
test => open,
wbs_adr_i => wbs_adr_i,
wbs_sel_i => wbs_sel_int,
wbs_we_i => wbs_we_i,
wbs_tga_i => wbs_tga_i,
vme_adr_in => vme_adr_in,
vme_adr_out => vme_adr_out,
vme_adr_in_reg => vme_adr_in_reg,
sl_acc_wb => sl_acc_wb,
ma_en_vme_data_out_reg => ma_en_vme_data_out_reg,
asn_in => as_i_n,
mensb_active => mensb_active,
int_be => int_be,
int_adr => int_adr,
clr_intreq => clr_intreq,
iackn => iackn,
iackin => iackin,
iackoutn => iackoutn,
vam_oe => vam_oe,
vam => vam,
vme_acc_type => vme_acc_type,
second_word => second_word,
dsn_ena => dsn_ena,
mstr_reg => mstr_reg,
longadd => longadd,
mstr_cycle => mstr_cycle,
ma_byte_routing => ma_byte_routing,
sysc_reg => sysc_reg,
sl_sel_vme_data_out => sl_sel_vme_data_out,
sl_byte_routing => sl_byte_routing,
ld_loc_adr_m_cnt => ld_loc_adr_m_cnt,
inc_loc_adr_m_cnt => inc_loc_adr_m_cnt,
sl_inc_loc_adr_m_cnt => sl_inc_loc_adr_m_cnt,
sl_en_vme_data_in_reg => sl_en_vme_data_in_reg,
writen => writen,
sram_acc => sram_acc,
pci_acc => pci_acc,
ma_d64 => ma_d64,
sl_d64 => sl_d64,
reg_acc => reg_acc,
intr_reg => intr_reg,
lwordn_slv => lwordn_slv,
lwordn_mstr => lwordn_mstr,
en_vme_adr_in => en_vme_adr_in,
my_iack => my_iack,
wbm_adr_o => wbm_adr_o_int,
wbm_sel_o => wbm_sel_o,
wbm_we_o => wbm_we_o_int,
vam_reg => vam_reg,
dsan_out => ds_o_n_int(0),
dsbn_out => ds_o_n_int(1),
dsan_in => ds_i_n(0),
dsbn_in => ds_i_n(1),
sl_writen_reg => sl_writen_reg,
iackn_in_reg => iackn_in_reg,
sl_acc => sl_acc,
sl_acc_valid => sl_acc_valid,
pci_offset_q => pci_offset_q,
asn_in_sl_reg => asn_in_sl_reg,
slv24_pci_q => slv24_pci_q,
slv32_pci_q => slv32_pci_q,
slv16_reg => slv16_reg,
slv24_reg => slv24_reg,
slv32_reg => slv32_reg
);
master : vme_master
PORT MAP(
clk => clk,
rst => rst,
test_c => OPEN,
run_mstr => run_mstr,
mstr_ack => mstr_ack,
mstr_busy => mstr_busy,
vme_req => mstr_vme_req,
burst => burst,
ma_en_vme_data_in_reg => ma_en_vme_data_in_reg,
ma_en_vme_data_in_reg_high => ma_en_vme_data_in_reg_high,
wb_dma_acc => wb_dma_acc,
brel => brel,
wbs_we_i => wbs_we_i,
dwb => dwb,
dgb => dgb,
berrn_in => berrin,
dtackn_in => dtackin,
d64 => ma_d64,
asn_out => asn_out,
rst_aonly => rst_aonly,
rst_rmw => rst_rmw,
set_berr => set_berr,
vam_oe => vam_oe,
ma_oe_va => ma_oe_va,
ma_oe_vd => ma_oe_vd,
dsn_ena => dsn_ena,
mstr_cycle => mstr_cycle,
second_word => ma_second_word,
asn_in => as_i_n,
mstr_reg => mstr_reg(5 DOWNTO 0),
ma_io_ctrl => ma_io_ctrl
);
requester : vme_requester
PORT MAP (
clk => clk,
rst => rst,
br_i_n => br_i_n,
br_o_n => br_o_n,
bg_o_n => bg_o_n,
bbsyn_in => bbsyin,
bbsyn => bbsyn,
dwb => dwb,
dgb => dgb,
FairReqEn => FairReqEn,
brl => brl,
bgintn => bgintn,
req_bit => mstr_reg(1),
brel => brel
);
arbiter : vme_arbiter
PORT MAP (
clk => clk,
rst => rst,
bgintn => bgintn,
set_ato => set_ato,
sysc_bit => sysc_reg(0),
bgouten => bgouten,
br_i_n => br_i_n,
bbsyn_in => bbsyin,
bg_i_n => bg_i_n
);
bustimer : vme_bustimer
PORT MAP (
clk => clk,
rst => rst,
startup_rst => startup_rst,
prevent_sysrst => prevent_sysrst,
set_sysc => set_sysc,
sysc_bit => sysc_reg(0),
clr_sysr => clr_sysr,
sysr_bit => sysc_reg(1),
dsain => ds_i_n(0),
dsbin => ds_i_n(1),
bgouten => bgouten,
sysfailn => sysfail_o_n,
sysrstn_in => sysresin,
sysrstn_out => sysresn,
v2p_rst => v2p_rst,
bg3n_in => bg_i_n(3),
slot01n => slot01n,
berrn_out => berrn
);
slave : vme_slave
PORT MAP (
clk => clk,
rst => rst,
loc_keep => loc_keep,
mstr_busy => mstr_busy,
asn_in => as_i_n,
dsan_in => ds_i_n(0),
dsbn_in => ds_i_n(1),
reg_acc => reg_acc,
sl_writen_reg => sl_writen_reg,
en_vme_adr_in => en_vme_adr_in,
wbm_we_o => wbm_we_o_int,
dtackn_out => dtackn,
slave_req => slave_req,
slave_active => slave_active,
sl_write_flag => sl_write_flag,
sl_second_word => sl_second_word,
clr_intreq => clr_intreq,
sl_acc => sl_acc,
sl_acc_valid => sl_acc_valid,
asn_in_sl_reg => asn_in_sl_reg,
my_iack => my_iack,
sl_en_vme_data_in_reg => sl_en_vme_data_in_reg,
sl_en_vme_data_in_reg_high => sl_en_vme_data_in_reg_high,
sl_oe_va => sl_oe_va,
sl_oe_vd => sl_oe_vd,
reg_en_vme_data_out_reg => reg_en_vme_data_out_reg,
sl_io_ctrl => sl_io_ctrl,
ld_loc_adr_m_cnt => ld_loc_adr_m_cnt,
sl_inc_loc_adr_m_cnt => sl_inc_loc_adr_m_cnt,
mensb_mstr_req => mensb_mstr_req,
mensb_mstr_ack => mensb_mstr_ack
);
wbm : vme_wbm
PORT MAP (
clk => clk,
rst => rst,
loc_keep => loc_keep,
vme_cyc_sram => vme_cyc_sram,
vme_cyc_pci => vme_cyc_pci,
wbm_stb_o => wbm_stb_o,
wbm_err_i => wbm_err_i,
wbm_ack_i => wbm_ack_i,
wbm_we_o => wbm_we_o_int,
sl_en_vme_data_out_reg => sl_en_vme_data_out_reg,
sl_en_vme_data_out_reg_high => sl_en_vme_data_out_reg_high,
mensb_mstr_req => mensb_mstr_req,
mensb_mstr_ack => mensb_mstr_ack,
sel_wbm_dat_o => sel_wbm_dat_o,
en_wbm_dat_o => en_wbm_dat_o,
inc_loc_adr_m_cnt => inc_loc_adr_m_cnt,
sl_acc_wb => sl_acc_wb,
pci_acc => pci_acc,
sram_acc => sram_acc
);
mailbox : vme_mailbox
PORT MAP(
clk => clk,
rst => rst,
sl_acc => sl_acc,
wbm_adr_o => wbm_adr_o_int(19 DOWNTO 2),
wbm_we_o => wbm_we_o_int,
mensb_mstr_req => mensb_mstr_req,
ram_acc => sram_acc,
mail_irq => mail_irq
);
locmon : vme_locmon
PORT MAP(
clk => clk,
rst => rst,
en_vme_adr_in => en_vme_adr_in,
ma_en_vme_data_out_reg => ma_en_vme_data_out_reg,
sl_writen_reg => sl_writen_reg,
vme_adr_locmon => vme_adr_locmon,
vam_reg => vam_reg,
clr_locmon => clr_locmon,
loc_sel => loc_sel,
loc_am_0 => loc_am_0,
loc_am_1 => loc_am_1,
loc_irq_0 => loc_irq_0,
loc_irq_1 => loc_irq_1,
loc_rw_0 => loc_rw_0,
loc_rw_1 => loc_rw_1,
loc_adr_0 => loc_adr_0,
loc_adr_1 => loc_adr_1
);
END vme_ctrl_arch;
| gpl-3.0 | 96ade0689079f7b82617d5084b7ec7f5 | 0.446464 | 4.117434 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_destroy_2.vhd | 2 | 15,570 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- cond_destroy_2.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_cond_t * cond = (hthread_cond_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_cond_init( cond, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = hthread_cond_destroy( cond );
when STATE_4 =>
-- Push the argument to hthread_cond_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_cond_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
when STATE_6 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | c5fa3d37dccbbc4416cd59e8e1e5fbcc | 0.540912 | 3.825553 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pf_counter_bit.vhd | 2 | 10,938 | -------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- ** of this text at all times. **
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - Changed the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed to call out proc_common v2_00_a library.
-- ^^^^^^
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v3_00_a;
Use proc_common_v3_00_a.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_bit is
port (
Clk : in std_logic;
Rst : In std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
component inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component inferred_lut4;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"36C6"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => count_AddSub,
--- xst wrk around I0 => Count_In,
--- xst wrk around I1 => Count_Down,
--- xst wrk around I2 => Count_Load,
--- xst wrk around I3 => Load_In);
I_ALU_LUT : inferred_lut4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub,
I0 => Count_In,
I1 => Count_Down,
I2 => Count_Load,
I3 => Load_In);
MUXCY_I : MUXCY
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg,
C => Clk,
CE => Clock_Enable,
D => count_Result,
R => Rst
);
Result <= count_Result_Reg;
end implementation;
| bsd-3-clause | 2bb3ec569353d93d5a7f29f5e3d1d8ab | 0.414701 | 4.87216 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/slave_attachment.vhd | 3 | 80,167 | -------------------------------------------------------------------------------
-- $Id: slave_attachment.vhd,v 1.17 2007/03/30 16:44:50 gburch Exp $
-------------------------------------------------------------------------------
-- Slave attachment entity and architecture
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename slave_attachment.vhd
--
-- Description: OPB slave attachment for accessing arbitray byte(s) within
-- word boundary aligned addresses on the OPB side. Addresses
-- are required to be contiguous word addresses starting at
-- C_SLAVE_ATT_BAR with all lsbs are zero to C_SLAVE_ATT_BAR
-- with all lsbs ones. This module has the master attachment
-- functionality. This module is written to IEEE-93 vhdl specs.
--
-- When supporting OPB sequential-address transactions
-- (bursts), this implementation requires
-- that OPB_seqAddr be negated for
-- the last transfer of the burst. (This is more restrictive
-- than the original OPB, which *recommends* early negation of
-- OPB_seqAddr and OPB_busLock to allow overlapped
-- arbitration.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- slave_attachment.vhd
-------------------------------------------------------------------------------
-- Author: ML
-- History:
-- ML 04/20/01 -- First version
--
-- ALS 08/21/01
-- ^^^^^^
-- Changed addr_sel_int to be of type integer. Addr_sel is then the
-- result of CONV_std_logic_vector function using addr_sel_int and the
-- C_SL_ATT_ADDR_SEL_WIDTH generic.
--
-- Also changed the implementation of the master data buffer from registers
-- to SRL16 fifos.
-- ~~~~~~
--
-- ALS 08/24/01
-- ^^^^^^
-- Implemented Slave Only - No Burst logic using a state machine.
-- ~~~~~~
--
-- ALS 08/30/01
-- ^^^^^^
-- Added registers for OPB bus signals. Bus2IP address bus is no longer
-- zero'd as the address mux is a true mux.
-- Added pselect module for address decode.
-- ~~~~~~
--
-- ALS 09/10/01
-- ^^^^^^
-- Modified SLAVE ONLY NO BURST mode:
-- Pulled generation of Sln_Dbus_gtd_cmb from state machine. Instead,
-- state machine just generates sln_dbus_rst. Sln_DBus_gtd is now
-- registered with IP2Bus_Data_mx as the D input, sln_dbus_rst as the
-- synchronous reset, and IP2Bus_RdAck_mx as the CE.
-- ~~~~~~
--
-- ALS 09/11/01
-- ^^^^^^
-- Modified SLAVE ONLY, BURST mode:
-- Implemented this logic as a state machine. Added bus registers.
-- ~~~~~~
--
-- ALS 09/13/01
-- ^^^^^^
-- Fixed implementation of Sln_ErrAck in both SLAVE ONLY BURST and NO
-- BURST modes. IP must assert IP2Bus_RdAck or IP2Bus_WrAck when
-- asserting IP2Bus_ErrAck. Changed sln_dbus_rst to sln_rst since this
-- signal will be used to reset both Sln_DBus and Sln_ErrAck.
-- ~~~~~~
--
-- ALS 09/18-19/01
-- ^^^^^^
-- Modified SLAVE ONLY BURST mode:
-- Implemented necessary changes to allow bursts to operate correctly.
-- ~~~~~~
--
-- ALS 09/25/01
-- ^^^^^^
-- Merged slv_attach.vhd and slave_attachment.vhd files. Incorporated new
-- generics and renamed generics as needed. Extended address bus to include
-- lower two bits. NO MODIFICATIONS TO THE SLAVE/MASTER module have been
-- made at this time.
-- ~~~~~~
--
-- ALS 09/28/01
-- ^^^^^^
-- Moved SRL_FIFOs to processor common library. Added library statement
-- and updated SRL_FIFO component declaration.
-- ~~~~~~
--
-- ALS 10/02/01
-- ^^^^^^
-- Modified SLAVE FULL mode to extend the address bus to include lower
-- two bits.
-- ~~~~~~
-- ALS 10/03/01
-- ^^^^^^
-- Implemented SLAVE FULL mode in a state machine. Added outputs
-- SA2MA_Retry and SA2MA_Error.
-- ~~~~~~
-- ALS 10/22-26/01
-- ^^^^^^
-- Actual code implementation and debug
-- ~~~~~~
-- ALS 10/28-29/01
-- ^^^^^^
-- Combined the read burst and master burst counters. Worked on arbitration
-- between the two state machines.
-- ~~~~~~
-- ALS 11/10/01
-- ^^^^^^
-- Reviewed use of asynchronous resets in the code and cleaned up where
-- necessary. In most cases, the asynchronous resets were stable, but were
-- removed anyway.
-- ~~~~~~
-- ALS 12/08/01
-- ^^^^^^
-- Removed reset on master burst counter, counter gets correct value loaded
-- Added negation of bus2ip_devicesel_mstr on transitions to MSTR_ACK state
-- so that bus2ip_devicesel_mstr correctly negates. Signal bus2ip_burst_reg
-- now uses bus2ip_burst_opb instead of bus2ip_burst_opb_reg so that it
-- negates properly. Bus2ip_burst_sa will now also negate with mstr_burst_fe.
-- Added synchronous reset of OPB_SeqAddr falling edge
-- to read request register.
-- ~~~~~~
-- ALS 12/10/01
-- ^^^^^^
-- ma2sa_rd_flag is now reset from mstr state machine during SET_REQ state
-- instead of being reset by sa2ma_rdrdy.
-- ~~~~~~
-- ALS 12/12/01
-- ^^^^^^
-- Qualified falling edge of OPB_SeqAddr with opb_busy to sequential reset
-- of Bus2IP_RdReq.
-- ~~~~~~
-- ALS 12/12/01
-- ^^^^^^
-- Changed the synchronous reset of bus2ip_rdreq_dec to also include
-- reset on the falling edge of OPB_SeqAddr.
-- Changed the synchronous reset of bus2ip_devicesel_dec to include
-- Valid_decode instead of valid_decode_d1.
-- (Change logged by FO)
-- ~~~~~~
-- FLO 1/2/02
-- ^^^^^^
-- Renamed Sln_DBus_gtd to the external name, Sln_DBus.
-- Removed the C_SL_ATT_ADDR_SEL_WIDTH parameter.
-- Some _sa signals go to _i suffix.
-- ~~~~~~
-- FLO Since v1_23_d
-- ^^^^^^
-- Several name changes to signals and generics as part of effort
-- to improve consistency of naming throughout the OPB IPIF.
-- ~~~~~~
-- ALS 03/22/02
-- ^^^^^^
-- Changed signals
-- Sln_Retry <= sln_retry_i when OPB_Select='1' else '0';
-- Sln_XferAck <= sln_xferack_i when OPB_Select='1' else '0';
-- Sln_ErrAck <= sln_errack_i when OPB_Select='1' else '0';
-- to not rely on asynchronous reset for negation when OPB_Select
-- becomes '0';
-- (Change logged by FO)
-- ~~~~~~
-- ALS, SH 04/18/02
-- ^^^^^^
-- Last change mentioned above, not actually done. Now it is
-- done, along with that which follows.
--
-- Process SLVONLY_NOBURST_SLN_REG,
-- incorrectly had assignments to Sln_XferAck and Sln_ErrAck,
-- instead of to Sln_XferAck_i and Sln_ErrAck_i.
-- (Change logged by FO)
-- ~~~~~~
-- FLO 05/14/02
-- ^^^^^^
-- A couple of changes were needed to support the retained-state
-- retry mode implemented in the master attachment.
-- ~~~~~~
-- FLO 05/29/02
-- ^^^^^^
-- Removed defunct "Sln_retry <= sln_retry_i" signal assignments.
-- ~~~~~~
-- FLO 06/14/02
-- ^^^^^^
-- Implemented capability to inhibit slave-mode posted writes.
-- Since all slave-mode posted writes were due to OPB sequential
-- address (burst) transactions, the implementation was done
-- done in terms of masking the OPB_SeqAddr signal.
-- ~~~~~~
-- FLO 06/24/02
-- ^^^^^^
-- Implemented dynamic byte-enable capability.
-- ~~~~~~
-- FLO 07/17/02
-- ^^^^^^
-- Fix to zero Sln_Dbus upon retry response to local master.
-- ~~~~~~
-- FLO 08/12/02
-- ^^^^^^
-- Changed to Bus2IP_Burst to have same validity window as
-- Bus2IP_RdReq or Bus2IP_WrReq.
--
-- Added MA2SA_Retry to sensitivity list of SLN_DBUS_RST_PROCESS.
-- ~~~~~~
-- FLO 08/20/02
-- ^^^^^^
-- Fixed the "WrCE fallout" bug by adding
-- bus2ip_devicesel_dec_cmb <= '1';
-- under the SET_REQ state when other conditions are, write, non-burst,
-- ack not yet received and the next state going to WAIT_ACK.
-- ~~~~~~
-- FLO 09/04/02
-- ^^^^^^
-- Added capability to abort IPIC transaction if termination
-- is by OPB_timeout. Done for each of the versions, mstr,
-- slave-only-burst, and slave-only-no-burst.
--
-- ~~~~~~
-- FLO 09/10/02
-- ^^^^^^
-- Added port signal Bus2IP_LocalMstTrans. This signal is a qualifier
-- valid during any IPIC transfer. It is asserted during an IPIC
-- transfer if and only if the transfer is taking place as part of
-- a locally initiated master transaction. Local master transactions
-- can be initiated either by an IPIF DMA[SG] engine or a IP-core
-- master, if either or both are present. If there is no IPIC
-- transfer in progress, the value of Bus2IP_LocalMstTrans may be
-- arbitrary.
-- ~~~~~~
-- FLO 09/11/02
-- ^^^^^^
-- Corrected write burst addressing by adding pipe stage on
-- Bus2IP_Addr_sa to match the Bus2IP_Data pipe stage. (Also
-- similarly pipelined Bus2IP_BE and Bus2IP_RNW for consistency
-- in the pipeline model.)
-- ~~~~~~
-- FLO 09/11/02
-- ^^^^^^
-- Added gating of sln_xferack by non-falling-edge
-- of obp_burst. This was needed to supress a spurious sln_xferack
-- generated when an opb seqaddr write sequence is followed immediately
-- by a new transaction without negation of OPB_select, i.e. when there
-- is no arbitration cycle.
-- ~~~~~~
-- FLO 09/13/02
-- ^^^^^^
-- Changed the cycle on which IP2Bus_PostedWrInh is interpreted to
-- be the first cycle after a rising edge on OPB_SeqAddr instead of
-- the cycle prior to this. IP2Bus_postedWrInh will have a long
-- logic path in the slave_attachment, so, from a performance
-- point of view (although not from a correctness point of
-- view), it should be registered in the IP core.
-- ~~~~~~
-- FLO 09/19/02
-- ^^^^^^
-- Reworked the "full slave" opb state machine and the generation
-- of the Bus2IP_RdReq signal to get correct behavior when a
-- read burst is not acknowledged immediately and the SM
-- goes into the WAIT_ACK state.
-- ~~~~~~
-- FLO 09/21/02
-- ^^^^^^
-- Corrected the timing for the Addr_Cntr_ClkEn and Addr_Sel signals
-- on opb read bursts. These were coming a cycle too late, causing
-- Bus2IP_Addr to be a cycle late for the second an later transfers.
-- ~~~~~~
-- FLO 09/27/02
-- ^^^^^^
-- Unified on just one OPB state machine, eliminating the independent
-- slave-only-with-burst and slave-only-no-burst state machines.
-- The slave-only modes have been broken since v2_00_d sp3
-- as a result of a need to make a succesion of quick changes to the
-- state machine supporting master operation for a core project facing a
-- deadline. The slave-only state machines, therefore, fell behind.
-- Unifying on a single state machine has the advantages of
-- bringing slave-only operation up to date with enhancements and
-- fixes and of making future maintenence easier.
-- The code to support master-operation is placed in an
-- if-generate and the no-burst mode ties signal en_seqaddr low.
-- These measures result in logic resources being trimmed for the
-- slave-only-with-burst and slave-only-no-burst cases.
-- ~~~~~~
-- FLO 11/01/02
-- ^^^^^^
-- - Changed Bus2IP_RdReq on bursts to not negate until
-- Sln_xferAck with not OPB_seqAddr. This, in turn,
-- requires a combinatorial gate-off by falling edge
-- of OPB_seqAddr for the bus2ip_rdreq_rfifo for
-- the read FIFO.
-- - Deleted some unused signals.
-- - Added opbsm state FIN_WR_BURST so that control does not
-- artificially stay in state ACK for an extra cycle as
-- a write burst terminates. Goal is to remove the "gating"
-- code that served to reverse the side-effects of staying
-- in ACK for the extra cycle.
-- - Sln_xferAck is now just sln_xferack_i without gating.
-- - Removed some no-longer-pertinent comments.
-- - Changed opb_burst to bracket all included IPIC transfers;
-- adjusted code relying on former opb_burst timing.
-- - Changed mstr_burst to bracket all included IPIC transfers;
-- adjusted code relying on former mstr_burst timing.
-- - Changed Bus2IP_Burst to be the OR of opb_burst and mstr_burst;
-- Bus2IP_Burst now should act correctly as a qualifer for each
-- IPIC transfer.
-- - The slave attachment, when performing a single read on
-- behalf of a local master doing a single OPB write, will
-- now respond to IP2Bus_Retry by retrying the single read.
-- - Added note in description that early negation of OPB_seqAddr
-- is required.
-- ~~~~~~
-- FLO 11/05/02
-- ^^^^^^
-- - Fixed master SM termination for write bursts; Bus2IP_WrReq
-- was held too long.
-- - Fixed master SM termination for read bursts; for read bursts
-- not getting ack every cycle, Bus2IP_RdReq was negated early
-- and Bus2IP_RdCE was negated late.
-- ~~~~~~
-- FLO 11/06/02
-- ^^^^^^
-- Renamed devicesel_rst to devicesel_inh_opb and added devicesel_inh_mstr.
-- Devicesel_inh_mstr and devicesel_inh_opb are then applied
-- to cause negation of CS and CE assertions the cycle after
-- ip2bus_retry_mx.
-- ~~~~~~
-- FLO 11/19/02
-- ^^^^^^
-- Added output port SA2MA_PostedWrInh.
-- ~~~~~~
-- FLO 12/05/02
-- ^^^^^^
-- When doing an IPIC read on behalf of a master doing an OPB write,
-- if the read (or the first read of an attempted burst) gets
-- IP2Bus_Retry, then SA2MA_Retry is returned to the master_attachment
-- and the transaction terminates.
-- ~~~~~~
-- FLO 01/06/03
-- ^^^^^^
-- Fixed three cases where
-- Bus2IP_RdReq was deasserted 1 clock before RdCE vector was deasserted.
-- ~~~~~~
-- FLO 01/09/03
-- ^^^^^^
-- Removed signals addrcntr_ce_mstr_cmb and addrcntr_ce_mstr_cmb_d1.
-- Now generating Addr_Cntr_ClkEn as
-- Addr_Cntr_ClkEn <= IP2Bus_RdAck_mx or Bus2IP_WrReq_i;
-- With this clock enable, the Bus2IP_amux.vhd address counter
-- increments for slave burst reads and master burst reads and
-- burst writes, as required, since these are the cases for which
-- the address counter is used. The address counter will also increment
-- harmlessly for others cases where the address counter is not used.
-- ~~~~~~
-- FLO 05/15/03
-- ^^^^^^
-- Added the C_ARD_ADDR_RANGE_ARRAY generic.
-- Changed the device-select behavior such that valid_decode is generated
-- and Bus2IP_DeviceSel asserted only if the bus address lies with in one
-- of the ARD address ranges. This is in contrast to the former behavior
-- behavior where the device was considered to be selected if the bus
-- address was inside the smallest power-of-two envelope that included
-- all of the ARD address ranges.
-- ~~~~~~
-- FLO 05/23/04
-- ^^^^^^
-- This failure mode was found during channelized HDLC integration, and fixed
-- between revisions 1.6 and 1.8 of opb_ipif_v2_05_a (see note, below). The
-- fix is now being applied also here to opb_ipif_v2_00_h.
--
-- The scenario was a dma write being started by the local ch_dma_sg. While
-- the IPIC read phase was going on, a software slave write to an IPIF
-- register occured. The a retry of the slave write started soon enough
-- that it was active when an IP2Bus_RdAck (for the read in support of the
-- DMA master transaction) occured. An error in the logic caused the
-- sln_dbus_ce to assert, which resulted in the master write data being
-- driven to the bus and being ORed with the slave data.
-- The fix implemented in the generation of sln_dbus_ce was to replace
-- valid_decode_d1 by opb_busy in the logic that enables sln_dbus to
-- take slave read data.
--
-- Note: opb_ipif_v2_05_a was later reverted to an earlier revision as
-- head but first opb_ipif_v2_06_a was created from opb_ipif_v2_05_a.
-- Thus, the place to see the change as a small delta is
-- between 1.6 and 1.8 (1.7 is a discontinuity)
-- of opb_ipif_v2_05_a, even though it is
-- not published in opb_ipif_v2_05_a but rather in opb_ipif_v2_06_a.
-- ~~~~~~
-- FLO 05/26/04
-- ^^^^^^
-- - An IPIC read timeout function was added to the slave_attachment.
-- New signal SA2MA_TimeOut communicates the timeout condition
-- to the master_attachment. The timeout can detect a hung
-- IPIC read occurring as the slave attachment reads into its read
-- buffer in support of a local master write OPB transaction.
-- The timeout function can be supressed by assertion of IP2Bus_ToutSup.
-- ~~~~~~
-- FLO 08/11/2004
-- ^^^^^^
-- Added input port MA2SA_RSRA (retained_state_retry_active).
-- Qualify mstr_burstcntr_ld by this signal.
-- ~~~~~~
-- FLO 08/20/2004
-- ^^^^^^
-- Changed way that bus2ip_devicesel gets delayed by a cycle for slave
-- burst writes. The former way was suceptible to an erroneous delay
-- during locally mastered transactions. An observed failure mode was
-- the CE for a single IPIC read of data for master write was correspondingly
-- delayed and, therefore, not asserted concurrently with the RdReq pulse.
-- ~~~~~
-- FLO 08/25/2004
-- ^^^^^^
-- Added port Bus2IP_RdReq_rfifo so that this signal, qualified by opb_busy,
-- can be generated here and passed up.
-- ~~~~~
-- FLO 09/22/2004
-- ^^^^^^
-- OPT 12c Deterministic departure from the slv_mstrsm MSTR_IDLE state
-- rather than possibly needing to return to the MSTR_IDLE state from
-- the MSTR_DEV_SEL state because it is detected that the slv_opbsm
-- started a transation on the same cycle. (see v2_05_a SA 11/11/03 and
-- 12/19/03, diff 1.3 1.5)
-- ~~~~~
-- FLO 09/22/2004
-- ^^^^^^
-- OPT 12b Simplified method of generating addr_sel address mux select signals.
-- BUG 12 Moved assertion of mstr_starting forward one cycle (into state MSTR_IDLE).
-- ~~~~~
-- FLO 09/22/04
-- ^^^^^^
-- BUG 10. When master state machine goes from state MSTR_SET_REQ to MSTR_IDLE--because
-- of either of ma2sa_select_d2 or MA2SA_Rd going low--then
-- bus2ip_devicesel_mstr_cmb is negated so that Bus2IP_Burst does not negate
-- before the CS/CE signals negate. (The CS/CE signals negate two cycles
-- after bus2ip_devicesel_mstr_cmb negates.) With this change, Bus2IP_Burst
-- and the CS/CE signals are expected to negate on the same cycle.
-- Issue was discovered relative to HDLC's generation of acceptable wrreq
-- signals to the write channel fifo for burst and non burst.
-- ~~~~~~
-- FLO 09/23/04
-- ^^^^^^
-- Timing optimizations:
-- - Replaced the ld_arith_reg for mstr_burstcntr_ce by ld_arith_reg2,
-- to get MA2SA_XferAck off the path through the MULTAND.
-- - Structured generation of mstr_burstcntr_ce to make MA2SA_XferAck
-- a late-arriving signal.
-- ~~~~~~
-- FLO 09/24/2004
-- ^^^^^^
-- -Added port SA2MA_BufOccMinus1, which gives the occupancy of the outgoing
-- FIFO that supports master write transactions.
-- -SA2MA_Retry now qualifies SA2MA_RdRdy.
-- -The master state machine now allows IPIC read retries on arbitrary beats,
-- not just on the first beat, as previously.
-- -Removed defunct signal sln_rst_mstr.
-- -Removed state MSTR_ACK, which wasn't really adding value, and
-- adjusted the mstr state machine accordingly.
-- -Removed states MSTR_WAIT_ACK and MSTR_RETRY and
-- adjusted the mstr state machine accordingly.
-- ~~~~~~
-- FLO 09/24/04
-- ^^^^^^
-- OPT 13. CR184349 In slvopb_sm_cs state SET_REQ, which is active
-- for exactly one cycle before moving on, neither bus2ip_rdreq or
-- bus2ip_wrreq could be asserted. Nevertheless, there was logic in this state to
-- respond to IPIC response signals. This response logic was eliminated to reduce
-- code in this state.
-- ~~~~~~
-- FLO 10/27/2004
-- ^^^^^^
-- - For locally mastered writes, sln_dbus_rst now tied to OPB_xferAck of
-- the last element from the output buffer instead of the last of
-- Mst_Num beats, i.e. keyed to the amount of data actually moved
-- instead of the amount requested.
-- ~~~~~~
-- GAB 3/30/2007
-- ^^^^^^
-- Added sln_dbus_fifo_empty to the sensitivity list of SLN_DBUS_RST_PROCESS
-- process. This fixes CR435879.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; -- provides conv_std_logic_vector function
use ieee.std_logic_arith.conv_std_logic_vector;
-- PROC_COMMON library contains the pselect and srl_fifo components
library proc_common_v1_00_b;
use proc_common_v1_00_b.all;
use proc_common_v1_00_b.proc_common_pkg.log2;
use proc_common_v1_00_b.ld_arith_reg;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics
-- C_OPB_ABUS_WIDTH -- OPB address bus width
-- C_OPB_DBUS_WIDTH -- OPB data bus width
-- C_IPIF_ABUS_WIDTH -- IPIF address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF data bus width
-- C_DEV_ADDR_DECODE_WIDTH -- number of upper address bits to decode
-- C_DEV_BASEADDR -- base address of slave attachment
-- C_DEV_BURST_ENABLE -- indicates if burst is supported
-- C_DEV_IS_SLAVE_ONLY -- indicates if device is slave only
-- C_MA2SA_NUM_WIDTH -- width of master to slave number
-- C_ARD_ADDR_RANGE_ARRAY -- The set of address ranges for decode
--
--
-- Definition of Ports
-- in Reset
--
-- --OPB ports
-- in OPB_Clk
-- in OPB_select
-- in OPB_RNW
-- in OPB_SeqAddr
-- in OPB_BE
-- in OPB_ABus
-- in OPB_DBus
-- in OPB_timeout
--
-- out Sln_DBus_gtd
-- out Sln_xferAck
-- out Sln_errAck
-- out Sln_toutSup
-- out Sln_retry
--
-- --Master Attachment ports
-- in Bus_MnGrant
-- in MA2SA_Select
-- in MA2SA_XferAck
-- in MA2SA_Rd
-- in MA2SA_Num
--
-- out SA2MA_RdRdy
-- out SA2MA_WrAck
-- out SA2MA_Retry
-- out SA2MA_Error
-- out SA2MA_FifoRd
-- out SA2MA_FifoWr
-- out SA2MA_FifoBu
-- out SA2MA_PostedWrInh
--
-- -Address MUX ports
-- out Addr_Sel
-- out Addr_Cntr_ClkEn
--
-- -IP ports
-- out Bus2IP_Burst
-- out Bus2IP_RNW
--
-- out Bus2IP_BE_sa
-- out Bus2IP_Addr_sa
-- out Bus2IP_Data
-- out Bus2IP_DeviceSel
-- out Bus2IP_WrReq
-- out Bus2IP_RdReq
-- out Bus2IP_LocalMstTrans
--
-- in IP2Bus_Data_mx
-- in IP2Bus_WrAck_mx
-- in IP2Bus_RdAck_mx
-- in IP2Bus_Error_mx
-- in IP2Bus_ToutSup_mx
-- in IP2Bus_Retry_mx
-- in IP2Bus_PostedWrInh
-------------------------------------------------------------------------------
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.SLV64_ARRAY_TYPE;
entity slave_attachment is
generic (
C_OPB_ABUS_WIDTH : integer := 32;
C_OPB_DBUS_WIDTH : integer := 32;
C_IPIF_ABUS_WIDTH : integer := 24;
C_IPIF_DBUS_WIDTH : integer := 32;
C_DEV_ADDR_DECODE_WIDTH : integer := 8;
C_DEV_BASEADDR : std_logic_vector := x"80000000";
C_DEV_BURST_ENABLE : boolean := true;
C_DEV_IS_SLAVE_ONLY : boolean := false;
C_MA2SA_NUM_WIDTH : integer := 4;
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:=
( -- This is just a representative set included
-- here so that the slave_attachment entity can be
-- independently synthesized. This default is not
-- intended to be useful for any particular application.
X"0000_0000_7000_1100",
X"0000_0000_7000_113F",
X"0000_0000_7000_1000",
X"0000_0000_7000_10FF",
X"0000_0000_7000_2100",
X"0000_0000_7000_21FF",
X"0000_0000_7000_2200",
X"0000_0000_7000_22FF",
X"0000_0000_7000_2000",
X"0000_0000_7000_2007",
X"0000_0000_7000_2010",
X"0000_0000_7000_2017",
X"0000_0000_7000_2300",
X"0000_0000_7000_23FF",
X"0000_0000_7000_0000",
X"0000_0000_7000_003F",
X"0000_0000_7000_0040",
X"0000_0000_7000_0043",
X"0000_0000_7000_1200",
X"0000_0000_7000_12FF"
)
);
port(
Reset : in std_logic;
OPB_Clk : in std_logic;
OPB_select : in std_logic;
OPB_RNW : in std_logic;
OPB_SeqAddr : in std_logic;
OPB_BE : in std_logic_vector (0 to C_OPB_DBUS_WIDTH/8-1);
OPB_ABus : in std_logic_vector (0 to C_OPB_ABUS_WIDTH-1);
OPB_DBus : in std_logic_vector (0 to C_OPB_DBUS_WIDTH-1);
OPB_timeout : in std_logic;
Sln_DBus : out std_logic_vector (0 to C_OPB_DBUS_WIDTH-1);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_toutSup : out std_logic;
Sln_retry : out std_logic;
Bus_MnGrant : in std_logic := '0';
MA2SA_Select : in std_logic := '0';
MA2SA_XferAck : in std_logic := '0';
MA2SA_Retry : in std_logic := '0';
MA2SA_RSRA : in std_logic := '0';
MA2SA_Rd : in std_logic := '0';
MA2SA_Num : in std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1)
:= (others => '0');
SA2MA_RdRdy : out std_logic; -- Cycle pulse indicating rd complete
SA2MA_WrAck : out std_logic;
SA2MA_Retry : out std_logic; -- Cycle pulse; qualifies SA2MA_RdRdy
SA2MA_Error : out std_logic;
SA2MA_FifoRd : out std_logic; -- Rd the output fifo for mstr writes
SA2MA_FifoWr : out std_logic; -- Wr the output fifo for mstr writes
SA2MA_FifoBu : out std_logic; -- Read back up signal, output fifo
SA2MA_PostedWrInh:out std_logic; -- IPIC cannot currently take posted wr
SA2MA_TimeOut : out std_logic;
SA2MA_BufOccMinus1 : out std_logic_vector(0 to 4); -- The occupancy
-- of the output buffer (sln_dbus_fifo) minus 1, as a signed
-- number. Valid values are -1 to 15. Since the only negative value
-- is when the occupancy is -1+1=0, SA2MA_BufOccMius1(0) can be
-- used as a "fifo empty" indicator.
Addr_Sel : out std_logic_vector (0 to 1);
Addr_Cntr_ClkEn : out std_logic;
Bus2IP_Burst : out std_logic;
Bus2IP_RNW : out std_logic;
Bus2IP_BE_sa : out std_logic_vector (0 to C_IPIF_DBUS_WIDTH/8-1);
Bus2IP_Addr_sa : out std_logic_vector (0 to C_IPIF_ABUS_WIDTH-1);
Bus2IP_Data : out std_logic_vector (0 to C_IPIF_DBUS_WIDTH-1);
Bus2IP_DeviceSel: out std_logic;
Bus2IP_WrReq : out std_logic;
Bus2IP_RdReq : out std_logic;
Bus2IP_RdReq_rfifo : out std_logic;
Bus2IP_LocalMstTrans: out std_logic;
IP2Bus_Data_mx : in std_logic_vector (0 to C_IPIF_DBUS_WIDTH-1);
IP2Bus_WrAck_mx : in std_logic;
IP2Bus_RdAck_mx : in std_logic;
IP2Bus_Error_mx : in std_logic;
IP2Bus_ToutSup_mx: in std_logic;
IP2Bus_Retry_mx : in std_logic;
IP2Bus_PostedWrInh: in std_logic;
Devicesel_inh_opb_out : out std_logic;
Devicesel_inh_mstr_out : out std_logic
);
end slave_attachment;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture implementation of slave_attachment is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1';
constant ZEROES : std_logic_vector(0 to 256)
:= (others=>'0');
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
function num_bits_to_designate_ar(ar_idx: natural) return natural is
constant LI: natural := C_ARD_ADDR_RANGE_ARRAY(0)'length-C_OPB_ABUS_WIDTH;
constant RI: natural := C_ARD_ADDR_RANGE_ARRAY(0)'length-1;
variable j: natural := LI;
begin
while j <= RI and
C_ARD_ADDR_RANGE_ARRAY(2*ar_idx )(j) =
C_ARD_ADDR_RANGE_ARRAY(2*ar_idx+1)(j)
loop
j := j+1;
end loop;
return j-LI;
end num_bits_to_designate_ar;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal opb_abus_d1 : std_logic_vector(0 to C_OPB_ABUS_WIDTH-1);
signal opb_dbus_d1 : std_logic_vector (0 to C_OPB_DBUS_WIDTH-1);
signal opb_rnw_d1 : std_logic;
signal opb_select_d1 : std_logic;
signal opb_be_d1 : std_logic_vector(0 to C_OPB_DBUS_WIDTH/8-1);
signal opb_rnw_d2 : std_logic;
--------------------------------------------------------------------------------
-- These signals are used to implement the IP2Bus_PostedWrInh functionality.
-- This implementation of the functionality follows the strategy of inhibiting
-- the posted-write burst behavior that is normally performed when
-- an OPB transaction is qualified by assertion of OPB_SeqAddr. This
-- strategy is chosen for a low-risk enhancement to a working slave attachment.
-- If IP2Bus_PostedWrInh is asserted during the first cycle of the OPB
-- transaction--which will allways be the cycle following a OPB_SeqAddr
-- rising edge, any posted-write IPIC burst behavior from that
-- transactions will be inhibited by the slave attachment.
-- Thus, the "and" combination of OPB_SeqAddr and en_seqaddr becomes the
-- effective OPB_SeqAddr. It is false, masking out OPB_SeqAddr whenever
-- posted writes are to be inhibited, and is identical to OPB_SeqAddr (within
-- propagation delay), otherwise.
--------------------------------------------------------------------------------
signal opb_seqaddr_d1 : std_logic; -- OPB_SeqAddr delayed by one clock
signal eff_seqaddr_d1 : std_logic; -- Effective value of opb_seqaddr_d1
-- after considering the possibility
-- that IP2Bus_PosterDrInh might
-- disable burst behavior.
signal en_seqaddr : std_logic; -- OPB_SeqAddr and en_seqaddr are
-- the effective OPB_SeqAddr after
-- accouting for possible inhibit.
-- sln_dbus fifo signals
signal sln_dbus_rst : std_logic := '0';
signal sln_dbus_ce : std_logic := '0';
signal sln_dbus_data : std_logic_vector(0 to C_OPB_DBUS_WIDTH-1);
signal sln_dbus_fifo_rst : std_logic := '0';
signal sln_dbus_fifo_wr : std_logic := '0';
signal sln_dbus_fifo_rd : std_logic := '0';
signal sln_dbus_fifo_bu : std_logic_vector(0 to 3
) := "0000";
signal sln_dbus_fifo_empty : std_logic := '1';
-- Full slave state machine signals
type SLVFULL_MSTRSMTYPE is (MSTR_IDLE,MSTR_DEVICE_SEL,MSTR_SET_REQ);
signal slv_mstrsm_cs, slv_mstrsm_ns : SLVFULL_MSTRSMTYPE;
type SLVFULL_OPBSMTYPE is (OPB_IDLE,ACK,RETRY,SET_DEVICESEL,SET_REQ,WAIT_ACK,FIN_WR_BURST);
signal slv_opbsm_cs, slv_opbsm_ns : SLVFULL_OPBSMTYPE;
signal sln_retry_i : std_logic := '0';
signal sln_retry_cmb : std_logic := '0';
signal sln_xferack_i : std_logic := '0';
signal sln_xferack_cmb : std_logic := '0';
signal sln_errack_i : std_logic := '0';
signal sln_rst_cmb : std_logic := '0'; -- used to reset Sln_Dbus and Sln_errAck
signal sln_dbus_i : std_logic_vector(0 to C_OPB_DBUS_WIDTH-1 );
signal opb_burst : std_logic;
signal opb_burst_set : std_logic;
signal opb_burst_rst : std_logic;
signal mstr_burst : std_logic;
signal mstr_burst_set : std_logic;
signal mstr_burst_rst : std_logic;
signal mstr_burst_cnt : std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1);
signal mstr_burstcntr_ld_n : std_logic := '0';
signal mstr_burstcntr_ce : std_logic := '0';
signal mstr_burstcntr_cehlp : std_logic := '0';
signal read_buf_data : std_logic_vector(0 to C_OPB_DBUS_WIDTH-1);
signal addr_sel_i : std_logic_vector (0 to 1);
signal addr_cntr_clken_i : std_logic := '0';
signal bus2ip_rdreq_mstr_cmb : std_logic := '0';
signal bus2ip_rdreq_mstr : std_logic := '0';
signal bus2ip_rdreq_opb_cmb : std_logic := '0';
signal bus2ip_rdreq_opb : std_logic := '0';
signal bus2ip_rdreq_dec_cmb : std_logic := '0';
signal bus2ip_rdreq_dec : std_logic := '0';
signal bus2ip_wrreq_mstr_cmb : std_logic := '0';
signal bus2ip_wrreq_mstr : std_logic := '0';
signal bus2ip_wrreq_opb_cmb : std_logic := '0';
signal bus2ip_wrreq_opb : std_logic := '0';
signal bus2ip_wrreq_dec_cmb : std_logic := '0';
signal bus2ip_wrreq_dec : std_logic := '0';
signal mstr_busy_cmb : std_logic := '0';
signal mstr_busy : std_logic := '0';
signal opb_busy_cmb : std_logic := '0';
signal opb_busy_reg : std_logic := '0';
signal opb_busy : std_logic := '0';
signal sa2ma_rdrdy_cmb : std_logic := '0';
signal sa2ma_rdrdy_i : std_logic := '0';
signal sa2ma_retry_cmb : std_logic := '0';
signal sa2ma_wrack_cmb : std_logic := '0';
signal opb_starting : std_logic := '0';
signal mstr_starting : std_logic := '0';
signal devicesel_inh_opb : std_logic := '0';
signal devicesel_inh_mstr : std_logic := '0';
signal devicesel_set : std_logic := '0';
signal bus2ip_devicesel_i : std_logic := '0';
signal bus2ip_devicesel_opb_cmb : std_logic := '0';
signal bus2ip_devicesel_opb : std_logic := '0';
signal bus2ip_devicesel_mstr_cmb : std_logic := '0';
signal bus2ip_devicesel_mstr : std_logic := '0';
signal bus2ip_burst_mstr : std_logic := '0';
signal ma2sa_xferack_d1 : std_logic := '0';
signal ma2sa_xferack_d2 : std_logic := '0';
signal ma2sa_select_d1 : std_logic := '0';
signal ma2sa_select_d2 : std_logic := '0';
signal ma2sa_rd_d1 : std_logic := '0';
signal ma2sa_select_re : std_logic := '0';
signal ma2sa_rd_re : std_logic := '0';
signal ma2sa_rd_flag : std_logic := '0';
signal ma2sa_rd_flag_rst : std_logic := '0';
signal ma2sa_rd_flag_set : std_logic := '0';
signal valid_decode : std_logic := '0';
signal valid_decode_d1 : std_logic := '0';
signal Bus2IP_Burst_rd_gateoff_needed : std_logic;
signal rd_or_wr_req_p1 : std_logic;
signal rd_or_wr_req : std_logic;
signal Bus2IP_WrReq_i : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component srl_fifo_rbu is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to log2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to log2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end component srl_fifo_rbu;
-- PSELECT is used to decode the upper address bits
component pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end component pselect;
constant RST_VAL : std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1)
:= (others=>'0');
component ld_arith_reg
generic (
C_ADD_SUB_NOT : boolean := false;
C_REG_WIDTH : natural := 8;
C_RESET_VALUE : std_logic_vector;
C_LD_WIDTH : natural := 8;
C_LD_OFFSET : natural := 0;
C_AD_WIDTH : natural := 8;
C_AD_OFFSET : natural := 0
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end component;
-------------------------------------------------------------------------------
-- slave_attachment implementation
-------------------------------------------------------------------------------
begin
---
--------------------------------------------------------------------------------
-- Here are parts of the implementation that are common to the three
-- implementations for master, slave with burst, slave without burst.
--------------------------------------------------------------------------------
OPB_INREGS: process (OPB_Clk) begin
if OPB_Clk'event and OPB_Clk='1' then
if Reset = RESET_ACTIVE then
opb_abus_d1 <= (others => '0');
opb_dbus_d1 <= (others => '0');
opb_rnw_d1 <= '0';
opb_select_d1 <= '0';
opb_be_d1 <= (others => '0');
opb_seqaddr_d1 <= '0';
else
opb_abus_d1 <= OPB_ABus;
opb_dbus_d1 <= OPB_DBus;
opb_rnw_d1 <= OPB_RNW;
opb_select_d1 <= OPB_select;
opb_be_d1 <= OPB_BE;
opb_seqaddr_d1 <= OPB_SeqAddr;
end if;
end if;
end process OPB_INREGS;
ADDR_PROC: process (OPB_Clk) begin
if OPB_Clk'event and OPB_Clk='1' then
Bus2IP_BE_sa <= opb_be_d1;
Bus2IP_Addr_sa <= opb_abus_d1(C_OPB_ABUS_WIDTH-C_IPIF_ABUS_WIDTH to
C_OPB_ABUS_WIDTH-1);
opb_rnw_d2 <= opb_rnw_d1;
end if;
end process ADDR_PROC;
en_seqaddr <= '0' when not C_DEV_BURST_ENABLE and C_DEV_IS_SLAVE_ONLY
-- Note, the implementation at the time of
-- this writing always enables burst when
-- there is a local master.
else
( ( not ip2bus_postedwrinh
and not opb_seqaddr_d1
-- Using the 'not opb_seqaddr_dq' gating
-- causes
)
or OPB_RNW
or eff_seqaddr_d1
);
EFF_SEQADDR_PROC: process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk='1' then
if Reset = RESET_ACTIVE then
eff_seqaddr_d1 <= '0';
else
eff_seqaddr_d1 <= OPB_SeqAddr and en_seqaddr;
end if;
end if;
end process EFF_SEQADDR_PROC;
--------------------------------------------------------------------------------
-- Decode the address
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- This option assumes that the address range of the device comprises the
-- smallest power of two that envelopes all of the individual address ranges.
--------------------------------------------------------------------------------
--VALID_DECODE_WITH_ENVELOPE_BLOCK: if false generate
--begin
-- SLVFULL_ATTCH_PSELECT_I: pselect
-- generic map (C_AB => C_DEV_ADDR_DECODE_WIDTH,
-- C_AW => C_OPB_ABUS_WIDTH,
-- C_BAR => C_DEV_BASEADDR)
-- port map (A => opb_abus_d1,
-- AValid => opb_select_d1,
-- CS => valid_decode);
--end generate;
--------------------------------------------------------------------------------
-- This option assumes that the address range of the device is non-monolithic
-- and comprises the union of the individual address ranges but not the holes
-- between them.
--------------------------------------------------------------------------------
VALID_DECODE_BLOCK: if true generate ---(
constant NUM_ARS : positive := C_ARD_ADDR_RANGE_ARRAY'length/2;
signal or_chain : std_logic_vector(0 to NUM_ARS);
constant LI: natural := C_ARD_ADDR_RANGE_ARRAY(0)'length-C_OPB_ABUS_WIDTH;
constant RI: natural := C_ARD_ADDR_RANGE_ARRAY(0)'length-1;
begin
or_chain(0) <= '0';
AR_HIT_GEN: for i in 0 to NUM_ARS-1 generate
signal psel_out: std_logic;
begin
AR_HIT_PSELECT_I: pselect
generic map (C_AB => num_bits_to_designate_ar(i),
C_AW => C_OPB_ABUS_WIDTH,
C_BAR => C_ARD_ADDR_RANGE_ARRAY(2*i)(LI to RI)
)
port map (A => opb_abus_d1,
AValid => opb_select_d1,
CS => psel_out
);
or_chain(i+1) <= or_chain(i) or psel_out;
end generate;
valid_decode <= or_chain(NUM_ARS);
end generate; ---)
-- register the output from the pselect module
VALID_DECODE_REG: process(OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
if Reset = RESET_ACTIVE then
valid_decode_d1 <= '0';
else
valid_decode_d1 <= valid_decode;
end if;
end if;
end process VALID_DECODE_REG;
OPB_BURST_FLAG: process(OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
if Reset = RESET_ACTIVE or opb_burst_rst = '1' then
opb_burst <= '0';
elsif opb_burst_set = '1' then
opb_burst <= '1';
end if;
end if;
end process OPB_BURST_FLAG;
--------------------------------------------------------------------------------
-- Slave Full OPB Transaction State Machine
-- SLVFULL_OPBSM_CMB: combinational process for determining next state
-- SLVFULL_OPBSM_REG: state machine registers
--
-- This state machine is used in conjunction with the SLVFULL_MSTRSM to handle
-- both OPB and master transactions. If the master state machine is busy, as
-- indicated by mstr_busy, an OPB retry is issued. If an OPB transaction is
-- in progress, as indicated by Valid_Decode, then the master state machine
-- waits.
--------------------------------------------------------------------------------
SLVFULL_OPBSM_CMB:
process (OPB_SeqAddr, en_seqaddr, opb_rnw_d1, IP2Bus_WrAck_mx, IP2Bus_RdAck_mx,
valid_decode, eff_seqaddr_d1, IP2Bus_Retry_mx, sln_retry_i,
slv_opbsm_cs, addr_sel_i, opb_burst, mstr_busy, valid_decode_d1,
OPB_timeout, bus2ip_rdreq_dec)
begin
-- set defaults
opb_busy_cmb <= '1';
bus2ip_devicesel_opb_cmb <= '0';
bus2ip_rdreq_opb_cmb <= '0';
bus2ip_wrreq_opb_cmb <= '0';
sln_retry_cmb <= sln_retry_i;
sln_xferack_cmb <= '0';
sln_rst_cmb <= '0';
devicesel_inh_opb <= '0';
opb_starting <= '0';
opb_burst_set <= '0';
opb_burst_rst <= '0';
slv_opbsm_ns <= slv_opbsm_cs;
case slv_opbsm_cs is
-------------------------- OPB_IDLE --------------------------
when OPB_IDLE =>
-- dead state to give OPB_select and Valid_Decode time
-- to negate. Proceed immediately to SET_DEVICESEL
slv_opbsm_ns <= SET_DEVICESEL;
opb_busy_cmb <= '0';
opb_burst_rst <= '1';
-------------------------- SET_DEVICESEL --------------------------
when SET_DEVICESEL =>
opb_busy_cmb <= '0'; -- negate opb_busy
if valid_decode = '1' then
if mstr_busy = '1' then
-- master is executing a transaction
-- issue a retry
sln_retry_cmb <= '1';
slv_opbsm_ns <= RETRY;
else
-- master is not executing a transaction
opb_starting <= '1';
opb_busy_cmb <= '1';
if opb_rnw_d1 = '1' then
-- set read request and devicesel
bus2ip_devicesel_opb_cmb <= '1';
elsif eff_seqaddr_d1 = '0' then
-- only preset write request and
-- Bus2IP_DeviceSel if not a burst
bus2ip_wrreq_opb_cmb <= '1';
bus2ip_devicesel_opb_cmb <= '1';
end if ;
slv_opbsm_ns <= SET_REQ;
end if;
end if;
-------------------------- SET_REQ --------------------------
when SET_REQ =>
opb_busy_cmb <= '1';
bus2ip_devicesel_opb_cmb <= '1';
opb_burst_set <= eff_seqaddr_d1;
if (opb_rnw_d1 = '1') then
-- read transaction
-- wait for IP2BUS_RDACK
bus2ip_rdreq_opb_cmb <= '1';
slv_opbsm_ns <= WAIT_ACK;
elsif eff_seqaddr_d1 = '1' then
-- write burst transaction,
-- don't wait for IP2BUS_WRACK
sln_xferack_cmb <= '1';
bus2ip_devicesel_opb_cmb <= '0';
slv_opbsm_ns <= ACK;
else
slv_opbsm_ns <= WAIT_ACK;
end if;
-------------------------- WAIT_ACK --------------------------
when WAIT_ACK =>
if valid_decode_d1 = '1' then
bus2ip_devicesel_opb_cmb <= '1';
end if;
bus2ip_rdreq_opb_cmb <= bus2ip_rdreq_dec and eff_seqaddr_d1;
if (opb_rnw_d1 = '1' and IP2Bus_RdAck_mx = '1') then
-- read transaction has completed
sln_xferack_cmb <= '1';
bus2ip_rdreq_opb_cmb <= OPB_seqAddr and en_seqaddr;
devicesel_inh_opb <= not (OPB_seqAddr and en_seqaddr);
if eff_seqaddr_d1 = '1' then
else
-- single opb read that's finished, negate opb_busy
-- and Bus2IP_DeviceSel
opb_busy_cmb <= '0';
bus2ip_devicesel_opb_cmb <= '0';
end if ;
slv_opbsm_ns <= ACK;
elsif (opb_rnw_d1 = '0' and IP2Bus_WrAck_mx = '1') then
-- single write transaction has completed
opb_busy_cmb <= '0';
sln_xferack_cmb <= '1';
slv_opbsm_ns <= ACK;
bus2ip_devicesel_opb_cmb <= '0';
elsif (IP2Bus_Retry_mx = '1') then
-- retry
bus2ip_devicesel_opb_cmb <= '0';
devicesel_inh_opb <= '1';
opb_busy_cmb <= '0';
sln_retry_cmb <= '1';
slv_opbsm_ns <= RETRY;
elsif (OPB_timeout = '1') then
bus2ip_devicesel_opb_cmb <= '0';
devicesel_inh_opb <= '1';
slv_opbsm_ns <= OPB_IDLE;
else
slv_opbsm_ns <= WAIT_ACK;
end if;
-------------------------- ACK --------------------------
when ACK =>
if opb_burst = '0' then
-- single transaction, terminate transfer
-- Read-burst termination, if the rdacks are not
-- immediate, also comes through here.
-- Write-bursts can also terminate through this state.
slv_opbsm_ns <= OPB_IDLE;
sln_rst_cmb <= '1';
opb_busy_cmb <= '0';
devicesel_inh_opb <= opb_rnw_d1;
elsif (opb_rnw_d1 = '1' and (OPB_SeqAddr and en_seqaddr) = '0') then
-- end of read burst
slv_opbsm_ns <= OPB_IDLE;
sln_rst_cmb <= '1';
devicesel_inh_opb <= '1';
opb_busy_cmb <= '0';
elsif (opb_rnw_d1 = '0' and (OPB_SeqAddr and en_seqaddr) = '0') then
-- end of write burst
bus2ip_wrreq_opb_cmb <= '1'; -- Need one more cycle of wrreq
slv_opbsm_ns <= FIN_WR_BURST;
sln_rst_cmb <= '1';
bus2ip_devicesel_opb_cmb <= '1';
else
-- continue burst
bus2ip_devicesel_opb_cmb <= '1';
if opb_rnw_d1 = '1' then
bus2ip_rdreq_opb_cmb <= '1';
else
bus2ip_wrreq_opb_cmb <= '1';
end if ;
if (opb_rnw_d1 = '0' or
(opb_rnw_d1 = '1' and IP2Bus_RdAck_mx = '1')) then
--write burst or read burst with immediate read ack
sln_xferack_cmb <= '1';
slv_opbsm_ns <= ACK;
else
-- read burst without immediate read ack
slv_opbsm_ns <= WAIT_ACK;
sln_rst_cmb <= '1';
end if;
end if;
-------------------------- FIN_WR_BURST --------------------------
when FIN_WR_BURST =>
slv_opbsm_ns <= OPB_IDLE;
opb_busy_cmb <= '0';
-------------------------- RETRY --------------------------
when RETRY =>
opb_busy_cmb <= '0';
slv_opbsm_ns <= OPB_IDLE;
-------------------------- DEFAULT --------------------------
when others =>
slv_opbsm_ns <= OPB_IDLE;
end case;
end process;
SLVFULL_OPBSM_REG: process (OPB_Clk)
begin
if (OPB_Clk'event and OPB_Clk = '1') then
if (Reset = RESET_ACTIVE) then
slv_opbsm_cs <= OPB_IDLE;
bus2ip_wrreq_opb <= '0';
bus2ip_rdreq_opb <= '0';
bus2ip_devicesel_opb <= '0';
else
-- reset state machine when valid_decode is negated
if valid_decode = '0' then
slv_opbsm_cs <= SET_DEVICESEL;
else
slv_opbsm_cs <= slv_opbsm_ns;
end if;
bus2ip_wrreq_opb <= bus2ip_wrreq_opb_cmb;
bus2ip_rdreq_opb <= bus2ip_rdreq_opb_cmb;
-- signal below is used a CE to bus2ip data reg
bus2ip_devicesel_opb <= bus2ip_devicesel_opb_cmb;
end if;
end if;
end process;
OPBBUSY_REG: process (OPB_Clk)
begin
if (OPB_Clk'event and OPB_Clk = '1') then
if (Reset = RESET_ACTIVE) then
opb_busy_reg <= '0';
else
opb_busy_reg <= opb_busy_cmb;
end if;
end if;
end process;
-- set when rising edge of valid decode
-- and master state machine not busy
opb_busy <= '1' when opb_starting = '1'
else opb_busy_reg;
---(
GEN_INCLUDE_MSTR_STUFF: if (not C_DEV_IS_SLAVE_ONLY) generate
signal ipic_timeout_cnt : std_logic_vector(0 to 4); -- Timeout when
-- the MSB becomes '1' after counting up from zero.
signal ipic_timeout : std_logic;
signal ipic_timeout_cntr_rst : std_logic;
signal sa2ma_timeout_cmb : std_logic;
begin
ipic_timeout <= ipic_timeout_cnt(ipic_timeout_cnt'left);
--------------------------------------------------------------------------------
-- Register the Master attachment input signals
--------------------------------------------------------------------------------
SLVFULL_MSTR_INREGS: process(OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
if Reset = RESET_ACTIVE then
ma2sa_xferack_d1 <= '0';
ma2sa_xferack_d2 <= '0';
ma2sa_select_d1 <= '0';
ma2sa_select_d2 <= '0';
ma2sa_rd_d1 <= '0';
ma2sa_rd_re <= '0';
else
ma2sa_xferack_d1 <= MA2SA_XferAck;
ma2sa_xferack_d2 <= ma2sa_xferack_d1;
ma2sa_select_d1 <= MA2SA_Select;
ma2sa_select_d2 <= ma2sa_select_d1;
ma2sa_rd_d1 <= MA2SA_Rd;
ma2sa_rd_re <= MA2SA_Rd and not(ma2sa_rd_d1);
end if;
end if;
end process SLVFULL_MSTR_INREGS;
-- generate rising edge signal for ma2sa_select for use with burst counter
ma2sa_select_re <= MA2SA_Select and not(ma2sa_select_d1);
-- MA2SA_RDFLAG registers a rising edge on MA2SA_Rd when opb is busy
-- so that when the OPB is done, the master state machine can proceed
-- it can be reset when SA2MA_RdRdy is asserted indicating that the
-- read cycle is complete
MA2SA_RDFLAG: process(OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
-- if Reset = RESET_ACTIVE or sa2ma_rdrdy_i = '1' then
if Reset = RESET_ACTIVE or ma2sa_rd_flag_rst = '1' then
ma2sa_rd_flag <= '0';
elsif (ma2sa_rd_re = '1' and opb_busy = '1') or
ma2sa_rd_flag_set = '1' then
ma2sa_rd_flag <= '1';
end if;
end if;
end process MA2SA_RDFLAG;
--------------------------------------------------------------------------------
-- Set the Master transaction flags
-- If the MA2SA_Num > 1, then the master is doing either a read or
-- write burst transaction. When the burst count is 0, negate the burst flag.
--------------------------------------------------------------------------------
MSTR_BURST_FLAG: process(OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk = '1' then
if mstr_burst_rst = '1' then
mstr_burst <= '0';
elsif mstr_burst_set = '1' then
mstr_burst <= '1';
end if;
end if;
end process MSTR_BURST_FLAG;
--------------------------------------------------------------------------------
-- Master burst counter
-- Counter will be loaded from MA2SA_Num and will down count each IP2Bus_RdAck
-- or MA2SA_XferAck.
--------------------------------------------------------------------------------
--ToDo, Synplify pro 7.1beta2 and earlier have a bug that precludes declaring
-- RST_VAL within a block enclosing the instance.
--burst_counter: block
-- constant RST_VAL : std_logic_vector(0 to C_MA2SA_NUM_WIDTH-1)
-- := (others=>'0');
--begin
MSTR_BURST_CNTR_I: entity proc_common_v1_00_b.ld_arith_reg2
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_MA2SA_NUM_WIDTH,
C_RESET_VALUE => RST_VAL,
C_LD_WIDTH => C_MA2SA_NUM_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0,
C_LOAD_OVERRIDES => true
)
port map (
CK => OPB_Clk, -- in std_logic;
RST => Reset, -- in std_logic; --Reset to C_RESET_VALUE.
-- (RST overrides OP,LOAD)
Q => mstr_burst_cnt, -- out std_logic_vector(0 to C_REG_WIDTH-1);
LD => MA2SA_Num, -- in std_logic_vector(0 to C_LD_WIDTH-1);
-- Load data.
AD => "1", -- in std_logic_vector(0 to C_AD_WIDTH-1);
-- Arith data.
LOAD_n => mstr_burstcntr_ld_n, -- in std_logic; --Enable for load
OP => mstr_burstcntr_ce -- in std_logic --Enable for the arith op
--(OP overrrides LOAD.)
);
--end block;
mstr_burstcntr_ld_n <= not ( ma2sa_rd_re or
sa2ma_rdrdy_i or
(ma2sa_select_re and not(MA2SA_Rd) and not(MA2SA_RSRA))
);
-- clock enable the counter during each remote read transfer ack, local read
-- read ack, or remote write transfer ack
mstr_burstcntr_cehlp <= (IP2Bus_RdAck_mx and bus2ip_devicesel_mstr) or
(ma2sa_xferack_d1 and not(MA2SA_Rd)); -- The goal of
-- introducing mstr_burstcntr_cehlp is to guide synthesis to put
-- MA2SA_XferAck in the "late-arriving" logic path in the generation of
-- mstr_burstcntr_ce.
mstr_burstcntr_ce <= (MA2SA_XferAck and MA2SA_Rd) or
mstr_burstcntr_cehlp;
--------------------------------------------------------------------------------
-- IPIC timeout counter.
--------------------------------------------------------------------------------
I_IPIC_TIMEOUT_CNTR: ld_arith_reg --Configured as simple, resettable up cntr.
generic map (
C_ADD_SUB_NOT => true,
C_REG_WIDTH => ipic_timeout_cnt'length,
C_RESET_VALUE => ZEROES(ipic_timeout_cnt'range),
C_LD_WIDTH => 1,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => OPB_Clk,
RST => ipic_timeout_cntr_rst,
Q => ipic_timeout_cnt,
LD => "0",
AD => "1",
LOAD => '0',
OP => '1'
);
--------------------------------------------------------------------------------
-- Slave Full Master Transaction State Machine
-- SLVFULL_MASTRANS_SM_CMB: combinational process for determining next state
-- SLVFULL_MASTRANS_SM_REG: state machine registers
--
-- This state machine is used in conjunction with the SLVFULL_OPBSM to handle
-- both OPB and master transactions. If the master state machine is busy, as
-- indicated by mstr_busy, an OPB retry is issued. If an OPB transaction is
-- in progress, as indicated by valid_decode, then the master state machine
-- waits.
--------------------------------------------------------------------------------
-- Combinational process
SLVFULL_MASTRANS_SM_CMB: process (opb_busy, MA2SA_Rd, ma2sa_rd_re,
addr_sel_i, ma2sa_xferack_d1, MA2SA_XferAck, ma2sa_rd_flag,
mstr_burst, IP2Bus_RdAck_mx, mstr_burst_cnt, MA2SA_Num,
IP2Bus_WrAck_mx, IP2Bus_Retry_mx,slv_mstrsm_cs, ma2sa_rd_d1,
ma2sa_select_d2, ipic_timeout, IP2Bus_ToutSup_mx)
begin
bus2ip_devicesel_mstr_cmb <= '0';
bus2ip_rdreq_mstr_cmb <= '0';
bus2ip_wrreq_mstr_cmb <= '0';
SA2MA_Retry_cmb <= '0';
mstr_busy_cmb <= '1';
SA2MA_RdRdy_cmb <= '0';
SA2MA_WrAck_cmb <= '0';
slv_mstrsm_ns <= slv_mstrsm_cs;
ma2sa_rd_flag_rst <= '0';
ma2sa_rd_flag_set <= '0';
mstr_burst_rst <= '0';
mstr_burst_set <= '0';
devicesel_inh_mstr <= '0';
mstr_starting <= '0';
ipic_timeout_cntr_rst <= '1';
sa2ma_timeout_cmb <= '0';
case slv_mstrsm_cs is
-------------------------- MSTR_IDLE --------------------------
when MSTR_IDLE =>
-- wait in this state until a rising edge of MA2SA_Rd or
-- MA2SA_XferAck during a write
mstr_busy_cmb <= '0';
mstr_burst_rst <= '1';
if ( opb_busy = '0'
and ( ma2sa_rd_re = '1'
or ma2sa_rd_flag = '1'
or (MA2SA_Rd = '0'and MA2SA_XferAck = '1')
)
) then
mstr_starting <= '1';
bus2ip_devicesel_mstr_cmb <= '1';
mstr_busy_cmb <= '1';
slv_mstrsm_ns <= MSTR_DEVICE_SEL;
end if;
-------------------------- MSTR_DEVICE_SEL --------------------------
when MSTR_DEVICE_SEL =>
bus2ip_devicesel_mstr_cmb <= '1';
if MA2SA_Rd = '1' then
bus2ip_rdreq_mstr_cmb <= '1';
else
bus2ip_wrreq_mstr_cmb <= ma2sa_xferack_d1;
end if ;
if MA2SA_Num > conv_std_logic_vector(1, C_MA2SA_NUM_WIDTH) then
mstr_burst_set <= '1';
end if;
ma2sa_rd_flag_rst <= '1';
slv_mstrsm_ns <= MSTR_SET_REQ;
-------------------------- MSTR_SET_REQ --------------------------
when MSTR_SET_REQ =>
ipic_timeout_cntr_rst <= IP2Bus_RdAck_mx or IP2Bus_ToutSup_mx;
bus2ip_devicesel_mstr_cmb <= '1';
--
if (MA2SA_Rd = '0' and ma2sa_select_d2 = '0' and mstr_burst = '1')
-- Abort a local-master burst read.
or
(MA2SA_Rd = '0' and ma2sa_rd_d1 = '1')
-- Abort a local-master write.
then
bus2ip_devicesel_mstr_cmb <= '0';
slv_mstrsm_ns <= MSTR_IDLE;
elsif MA2SA_Rd = '1' then
-- Local read in support of mstr write
if IP2Bus_RdAck_mx = '1' then
if mstr_burst = '0' then
-- single read has completed,
-- negate Bus2IP_DeviceSel
SA2MA_RdRdy_cmb <= '1';
bus2ip_devicesel_mstr_cmb <= '0';
slv_mstrsm_ns <= MSTR_IDLE;
elsif mstr_burst_cnt = conv_std_logic_vector(1, C_MA2SA_NUM_WIDTH) then
-- burst is complete, assert MA2SA_RdRdy and end transaction
bus2ip_devicesel_mstr_cmb <= '0';
SA2MA_RdRdy_cmb <= '1';
devicesel_inh_mstr <= '1';
slv_mstrsm_ns <= MSTR_IDLE;
else
-- burst read, keep req asserted
-- set address mux to counter
bus2ip_rdreq_mstr_cmb <= '1';
end if ;
elsif IP2Bus_Retry_mx = '1' then
-- Retry response on single read.
-- Signal sa2ma_retry and terminate the transaction.
SA2MA_RdRdy_cmb <= '1';
sa2ma_retry_cmb <= '1';
bus2ip_devicesel_mstr_cmb <= '0';
devicesel_inh_mstr <= '1';
mstr_busy_cmb <= '0';
slv_mstrsm_ns <= MSTR_IDLE;
elsif ipic_timeout = '1' then
sa2ma_timeout_cmb <= '1';
bus2ip_devicesel_mstr_cmb <= '0';
devicesel_inh_mstr <= '1';
mstr_busy_cmb <= '0';
slv_mstrsm_ns <= MSTR_IDLE;
else
-- waiting for ack, keep req asserted if burst
-- prepare counter
if mstr_burst = '1' then
bus2ip_rdreq_mstr_cmb <= '1';
end if;
end if;
elsif mstr_burst = '1' and
mstr_burst_cnt=conv_std_logic_vector(1,C_MA2SA_NUM_WIDTH) and
ma2sa_xferack_d1 = '1' then
-- write burst finished
slv_mstrsm_ns <= MSTR_IDLE;
bus2ip_devicesel_mstr_cmb <= '0';
bus2ip_wrreq_mstr_cmb <= '1';
elsif mstr_burst = '1' then
-- write burst not finished,
-- stay in this state and pass ma2sa_xferack_d2
-- on as the wrreq and addrcntr_ce
bus2ip_wrreq_mstr_cmb <= ma2sa_xferack_d1;
elsif (IP2Bus_WrAck_mx = '1') then
-- single write completed
-- assert WrAck, negate Bus2IP_DeviceSel
SA2MA_WrAck_cmb <= '1';
slv_mstrsm_ns <= MSTR_IDLE;
bus2ip_devicesel_mstr_cmb <= '0';
elsif (IP2Bus_Retry_mx = '1') then
-- single write with retry response
SA2MA_Retry_cmb <= '1';
slv_mstrsm_ns <= MSTR_IDLE;
bus2ip_devicesel_mstr_cmb <= '0';
devicesel_inh_mstr <= '1';
end if;
-------------------------- DEFAULT --------------------------
when others =>
slv_mstrsm_ns <= MSTR_IDLE;
end case;
end process SLVFULL_MASTRANS_SM_CMB;
SLVFULL_MASTRANS_SM_REG: process (OPB_Clk)
begin
if (OPB_Clk'event and OPB_Clk = '1') then
if (Reset = RESET_ACTIVE) then
bus2ip_wrreq_mstr <= '0';
bus2ip_rdreq_mstr <= '0';
bus2ip_devicesel_mstr <= '0';
SA2MA_Retry <= '0';
mstr_busy <= '0';
sa2ma_rdrdy_i <= '0';
SA2MA_WrAck <= '0';
SA2MA_TimeOut <= '0';
slv_mstrsm_cs <= MSTR_IDLE;
else
bus2ip_wrreq_mstr <= bus2ip_wrreq_mstr_cmb;
bus2ip_rdreq_mstr <= bus2ip_rdreq_mstr_cmb;
bus2ip_devicesel_mstr <= bus2ip_devicesel_mstr_cmb;
SA2MA_Retry <= sa2ma_retry_cmb;
mstr_busy <= mstr_busy_cmb;
sa2ma_rdrdy_i <= sa2ma_rdrdy_cmb;
SA2MA_WrAck <= sa2ma_wrack_cmb;
SA2MA_TimeOut <= sa2ma_timeout_cmb;
slv_mstrsm_cs <= slv_mstrsm_ns;
end if;
end if;
end process;
SA2MA_RdRdy <= sa2ma_rdrdy_i;
SA2MA_ERROR_PROCESS: process (OPB_Clk)
begin
if (OPB_Clk'event and OPB_Clk = '1') then
if (Reset = RESET_ACTIVE) then
SA2MA_Error <= '0';
elsif mstr_busy = '1' then
SA2MA_Error <= IP2Bus_Error_mx;
end if;
end if;
end process SA2MA_ERROR_PROCESS;
SA2MA_PostedWrInh <= IP2Bus_PostedWrInh;
--------------------------------------------------------------------------------
-- These signals control the output fifo that is used to buffer up outgoing
-- master data.
--------------------------------------------------------------------------------
sln_dbus_fifo_rst <= not MA2SA_Rd;
sln_dbus_fifo_wr <= MA2SA_Rd and bus2ip_devicesel_mstr and IP2Bus_RdAck_mx;
sln_dbus_fifo_rd <= MA2SA_Rd and not sln_dbus_fifo_empty and
(Bus_MnGrant or MA2SA_XferAck);
sln_dbus_fifo_bu(sln_dbus_fifo_bu'length-1) <= MA2SA_Rd and
MA2SA_Retry;
sln_dbus_fifo_bu(0 to sln_dbus_fifo_bu'length-2) <= (others => '0');
SA2MA_FifoWr <= sln_dbus_fifo_wr;
SA2MA_FifoRd <= sln_dbus_fifo_rd;
SA2MA_FifoBu <= sln_dbus_fifo_bu(sln_dbus_fifo_bu'length-1);
-- Instantiate the FIFO
SLN_DBUS_FIFO: srl_fifo_rbu
generic map (
C_DWIDTH => 32,
C_DEPTH => 16
)
port map (
Clk => OPB_Clk,
Reset => sln_dbus_fifo_rst,
FIFO_Write => sln_dbus_fifo_wr,
Data_In => IP2Bus_Data_mx,
FIFO_Read => sln_dbus_fifo_rd,
Data_Out => read_buf_data,
FIFO_Full => open,
FIFO_Empty => sln_dbus_fifo_empty,
Addr => SA2MA_BufOccMinus1(1 to 4),
Num_To_Reread => sln_dbus_fifo_bu,
Underflow => open,
Overflow => open
);
SA2MA_BufOccMinus1(0) <= sln_dbus_fifo_empty;
end generate GEN_INCLUDE_MSTR_STUFF;
---)
GEN_EXCLUDE_MSTR_STUFF : if C_DEV_IS_SLAVE_ONLY generate
read_buf_data <= (others => '0');
ma2sa_rd_d1 <= '0';
ma2sa_xferack_d1 <= '0';
mstr_burst <= '0';
mstr_burst_cnt <= (others => '0');
bus2ip_devicesel_mstr_cmb <= '0';
bus2ip_devicesel_mstr <= '0';
bus2ip_wrreq_mstr_cmb <= '0';
bus2ip_rdreq_mstr_cmb <= '0';
mstr_busy <= '0';
mstr_busy_cmb <= '0';
SA2MA_Retry <= '0';
SA2MA_WrAck <= '0';
SA2MA_RdRdy <= '0';
SA2MA_Error <= '0';
SA2MA_FifoWr <= '0';
SA2MA_FifoRd <= '0';
SA2MA_FifoBu <= '0';
SA2MA_PostedWrInh <= '0';
end generate GEN_EXCLUDE_MSTR_STUFF;
--------------------------------------------------------------------------------
-- Slave attachment outputs
--------------------------------------------------------------------------------
Bus2IP_LocalMstTrans <= mstr_busy;
Sln_toutSup <= IP2Bus_ToutSup_mx and opb_busy;
SLVFULL_OPB_OUTREGS: process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk='1' then
if (Reset = RESET_ACTIVE or OPB_Select='0') then
sln_retry_i <= '0';
sln_xferack_i <= '0';
else
sln_xferack_i <= sln_xferack_cmb;
-- assert retry when asserted from the state machine
sln_retry_i <= sln_retry_cmb;
end if;
if (Reset = RESET_ACTIVE or sln_rst_cmb = '1' or OPB_Select='0') then
sln_errack_i <= '0';
elsif mstr_busy = '0' then
sln_errack_i <= IP2Bus_Error_mx;
end if;
end if;
end process SLVFULL_OPB_OUTREGS;
Sln_Retry <= sln_retry_i when OPB_Select='1' else '0';
Sln_XferAck <= sln_xferack_i;
Sln_ErrAck <= sln_errack_i when OPB_Select='1' else '0';
--------------------------------------------------------------------------------
-- OPB data bus process
-- Data is to be driven on the OPB data bus during a read by a remote master or
-- during a write by the local master. Data to be written on the bus by the
-- local master comes from the read buffer FIFO.
--------------------------------------------------------------------------------
SLN_DBUS_RST_PROCESS: process (valid_decode_d1, MA2SA_XferAck, mstr_burst_cnt,
MA2SA_Rd, sln_rst_cmb, Bus_MnGrant,
MA2SA_Retry,sln_dbus_fifo_empty)
-- this process generates the reset for the opb data bus registers
begin
if valid_decode_d1 = '0' then
--master transaction
if MA2SA_Rd = '0'
or MA2SA_Retry = '1'
or ( MA2SA_XferAck = '1'
and sln_dbus_fifo_empty = '1'
)
then
sln_dbus_rst <= '1';
else
sln_dbus_rst <= '0';
end if;
else
-- OPB transaction
-- don't reset if MA2SA_Rd=1 and BusMnGrant = '1' because master will
-- be driving the data bus in the next clock
if MA2SA_Rd = '1' and Bus_MnGrant = '1' then
sln_dbus_rst <= '0';
else
sln_dbus_rst <= sln_rst_cmb;
end if;
end if;
end process SLN_DBUS_RST_PROCESS;
SLN_DATA_PROCESS: process(IP2Bus_Data_mx, read_buf_data, ma2sa_rd_d1, Bus_MnGrant, MA2SA_Select)
-- this process creates the mux for the opb data bus input
begin
if ma2sa_rd_d1 = '1' and (Bus_MnGrant = '1' or MA2SA_Select = '1') then
sln_dbus_data <= read_buf_data;
else
sln_dbus_data <= IP2Bus_Data_mx;
end if;
end process SLN_DATA_PROCESS;
SLN_CE_PROCESS: process(IP2Bus_RdAck_mx, Bus_MnGrant, MA2SA_XferAck, opb_busy)
-- this process creates the mux for the ce for the opb data bus registers
-- sln_dbus_rst is asserted whenever MA2SA_Rd = '0' and valid_decode = '0'
begin
if (opb_busy = '1' and IP2Bus_RdAck_mx = '1') or
Bus_MnGrant = '1' or
MA2SA_XferAck = '1' then
sln_dbus_ce <= '1';
else
sln_dbus_ce <= '0';
end if;
end process SLN_CE_PROCESS;
SLN_DBUS_REG: process (OPB_Clk)
begin
if (OPB_Clk'event and OPB_Clk = '1') then
if (sln_dbus_rst = '1' or Reset = RESET_ACTIVE) then
sln_dbus_i <= (others => '0');
elsif sln_dbus_ce = '1' then
sln_dbus_i <= sln_dbus_data;
end if;
end if;
end process SLN_DBUS_REG;
Sln_DBus <= sln_dbus_i;
--------------------------------------------------------------------------------
-- Bus2IP Signal Muxes
-- Signals from the IPIF to the IP are either driven from the OPB state machine
-- or the master state machine
--------------------------------------------------------------------------------
DEVICESEL_PROCESS: process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk='1' then
if Reset = RESET_ACTIVE then
bus2ip_devicesel_i <= '0';
else
bus2ip_devicesel_i <= bus2ip_devicesel_opb_cmb or bus2ip_devicesel_mstr_cmb;
end if;
end if;
end process DEVICESEL_PROCESS;
-- reset Bus2IP_DeviceSel when read burst ends
-- Bus2IP_DeviceSel <= '0' when (devicesel_inh_opb or devicesel_inh_mstr) = '1'
-- else bus2ip_devicesel_i;
-- Moved devicesel_inh_opb, devicesel_inh_mstr to address decode
Bus2IP_DeviceSel <= bus2ip_devicesel_i;
WRREQ_PROCESS: process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk='1' then
if Reset = RESET_ACTIVE then
Bus2IP_WrReq_i <= '0';
else
Bus2IP_WrReq_i <= bus2ip_wrreq_opb or bus2ip_wrreq_mstr_cmb;
end if;
end if;
end process WRREQ_PROCESS;
Bus2IP_WrReq <= Bus2IP_WrReq_i;
RDREQ_PROCESS: process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk='1' then
if Reset = RESET_ACTIVE then
bus2ip_rdreq_dec <= '0';
else
bus2ip_rdreq_dec <= bus2ip_rdreq_opb_cmb or bus2ip_rdreq_mstr_cmb;
end if;
end if;
end process RDREQ_PROCESS;
-- quickly reset Bus2IPB_RdReq_sa with OPB_SeqAddr falling edge if doing an OPB transaction
Bus2IP_RdReq <= bus2ip_rdreq_dec;
-- ----------------------------------------------------------------------------
-- -- The RFIFO moves burst data on every cycle and requires negation of
-- -- the RdReq signal to the RFIFO at an exact point relative to the last
-- -- data taken from the FIFO--so that the FIFO can back up properly.
-- -- When the RFIFO read is from a slave OPB transaction,
-- -- Thus, the falling edge of OPB_seqAddr must negate the standard
-- -- Bus2IP_RdReq signal to get the right timing, and
-- -- there is a requirement that OPB_seqAddr is low for the last
-- -- transfer of a locked seqaddr transaction (which is a stronger
-- -- requirement than given by the OPB spec, which merely suggests this).
-- ----------------------------------------------------------------------------
Bus2IP_RdReq_rfifo <= Bus2IP_RdReq_dec and
not (opb_busy and not OPB_seqAddr and opb_seqaddr_d1);
------------------------------------------------
-- Falling edge of seqAddr on an OPB
-- transaction to which this device is responding.
rd_or_wr_req_p1 <= (bus2ip_rdreq_opb and OPB_SeqAddr) or --For early fe; re ok
bus2ip_rdreq_mstr_cmb or
bus2ip_wrreq_opb or
bus2ip_wrreq_mstr_cmb;
RD_OR_WR_REQ_PROCESS: process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk='1' then
if Reset = RESET_ACTIVE then
rd_or_wr_req <= '0';
else
rd_or_wr_req <= rd_or_wr_req_p1;
end if;
end if;
end process RD_OR_WR_REQ_PROCESS;
Bus2ip_Burst <= opb_burst or mstr_burst;
ADDRMUXSIGS_PROCESS: process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk='1' then
if (Reset = RESET_ACTIVE) then addr_sel_i <= "00";
elsif opb_starting = '1' then addr_sel_i <= "00";
elsif mstr_starting = '1' then addr_sel_i <= "01";
elsif addr_cntr_clken_i = '1' then addr_sel_i <= "10";
else
null;
end if;
end if;
end process ADDRMUXSIGS_PROCESS;
Addr_Sel <= addr_sel_i;
addr_cntr_clken_i <= (IP2Bus_RdAck_mx or -- Covers slave or master burst read...
Bus2IP_WrReq_i -- ...covers master burst write.
) and
(mstr_burst or
opb_burst
);
Addr_Cntr_ClkEn <= addr_cntr_clken_i;
BUS2IPDATA_PROCESS: process (OPB_Clk)
begin
if OPB_Clk'event and OPB_Clk='1' then
if Reset = RESET_ACTIVE then
Bus2IP_Data <= (others => '0');
elsif (bus2ip_devicesel_opb = '1' or
(MA2SA_Rd='0' and ma2sa_xferack_d1 = '1')) then
Bus2IP_Data <= opb_dbus_d1;
end if;
end if;
end process BUS2IPDATA_PROCESS;
Bus2IP_RNW <= opb_rnw_d2 when mstr_busy = '0'
else ma2sa_rd_d1;
Devicesel_inh_opb_out <= devicesel_inh_opb;
Devicesel_inh_mstr_out <= devicesel_inh_mstr;
end implementation;
| bsd-3-clause | a8fbf3583dfbdd561fb2482874e547c1 | 0.514588 | 3.790402 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/brst_addr_cntr_reg.vhd | 3 | 12,788 | -------------------------------------------------------------------------------
-- $Id: brst_addr_cntr_reg.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- brst_addr_cntr_reg.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address
-- multiplexer.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: brst_addr_cntr_reg.vhd
--
-- Description: This vhdl design file is for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address Bus Output
-- multiplexer.
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- brst_addr_cntr_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- History:
--
-- ALS 12/24/03
-- ^^^^^^
-- Adapted from burst_addr_be_cntr_reg - removed BE generation
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- need the unsigned functions
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_flex_addr_cntr;
library unisim;
Use unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity brst_addr_cntr_reg is
generic (
C_CNTR_WIDTH : integer := 32;
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32
);
port (
-- Clock and Reset
Bus_reset : in std_logic;
Bus_clk : in std_logic;
-- Inputs
-- Burst : in std_logic;
Xfer_done : in std_logic;
RNW : in std_logic;
Addr_Load : in std_logic;
Addr_Cnt_en : in std_logic;
Addr_Cnt_Rst : in std_logic;
Address_In : in std_logic_vector(0 to C_OPB_AWIDTH-1);
Byte_xfer : in std_logic;
Hw_xfer : in std_logic;
Fw_xfer : in std_logic;
-- IPIF & IP address bus source (AMUX output)
Next_address_out : out std_logic_vector(0 to C_OPB_AWIDTH-1);
Address_Out : out std_logic_vector(0 to C_OPB_AWIDTH-1)
);
end brst_addr_cntr_reg;
architecture implementation of brst_addr_cntr_reg is
--INTERNAL SIGNALS
signal address_cnt : std_logic_vector(0 to C_CNTR_WIDTH-1);
signal next_address_cnt : std_logic_vector(0 to C_CNTR_WIDTH-1);
signal cken0 : std_logic;
signal cntx1 : std_logic;
signal cntx2 : std_logic;
signal cntx4 : std_logic;
signal clr_addr : std_logic;
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start of logic -------------------------------------------------
begin
------------------------------------------------------------------------------
-- For an address counter of width less than C_OPB_AWIDTH, address_out and
-- next_address_out are a concatination of an upper address portion and the
-- address counter's output
------------------------------------------------------------------------------
GEN_LESS_THAN_OPB_AWIDTH : if C_CNTR_WIDTH < C_OPB_AWIDTH generate
signal s_h_upper_addr : std_logic_vector(0 to C_OPB_AWIDTH-C_CNTR_WIDTH-1);
begin
-- Output assignments
Address_out <= s_h_upper_addr(0 to C_OPB_AWIDTH-C_CNTR_WIDTH-1) & address_cnt;
Next_address_out <= s_h_upper_addr(0 to C_OPB_AWIDTH-C_CNTR_WIDTH-1) & next_address_cnt
when cken0 = '1'
else
s_h_upper_addr(0 to C_OPB_AWIDTH-C_CNTR_WIDTH-1) & address_cnt;
clr_addr <= Addr_Cnt_Rst and not(Addr_load);
-- Sample and Hold registers
UPPER_ADDR_REG_GEN: for i in 0 to C_OPB_AWIDTH-C_CNTR_WIDTH-1 generate
UPPER_ADDR_REG: FDRE
port map(
Q => s_h_upper_addr(i),
C => Bus_clk,
CE => Addr_Load,
D => Address_in(i),
R => clr_addr
);
end generate UPPER_ADDR_REG_GEN;
-- Set the "count by' controls
cntx1 <= byte_xfer and not(Addr_Load);
cntx2 <= hw_xfer and not(Addr_Load);
cntx4 <= fw_xfer and not(Addr_Load);
cken0 <= Addr_Load or ((Addr_Cnt_en and not(RNW)) or
(Addr_cnt_en and RNW and not(Xfer_done)));
end generate;
------------------------------------------------------------------------------
-- For an address counter width equal to C_OPB_AWIDTH, address_out and
-- next_address_out are simply the address counter's output
------------------------------------------------------------------------------
GEN_EQUAL_TO_OPB_AWIDTH : if C_CNTR_WIDTH = C_OPB_AWIDTH generate
begin
-- Output assignments
Address_out <= address_cnt;
Next_address_out <= next_address_cnt
when cken0 = '1'
else
address_cnt;
clr_addr <= Addr_Cnt_Rst and not(Addr_load);
-- Set the "count by' controls
cntx1 <= byte_xfer and not(Addr_Load);
cntx2 <= hw_xfer and not(Addr_Load);
cntx4 <= fw_xfer and not(Addr_Load);
cken0 <= Addr_Load or ((Addr_Cnt_en and not(RNW)) or
(Addr_cnt_en and RNW and not(Xfer_done)));
end generate GEN_EQUAL_TO_OPB_AWIDTH;
I_FLEX_ADDR_CNTR : entity opb_v20_v1_10_d.opb_flex_addr_cntr
Generic map(
C_AWIDTH => C_CNTR_WIDTH
)
port map(
Clk => Bus_clk, -- : in std_logic;
Rst => clr_addr,
Load_Enable => Addr_Load, -- : in std_logic;
Load_addr => Address_In(C_OPB_AWIDTH-C_CNTR_WIDTH to C_OPB_AWIDTH-1), -- : in std_logic_vector(C_AWIDTH-1 downto 0);
Cnt_by_1 => cntx1, -- : in std_logic;
Cnt_by_2 => cntx2, -- : in std_logic;
Cnt_by_4 => cntx4, -- : in std_logic;
Cnt_by_8 => '0', -- : in std_logic;
Cnt_by_16 => '0', -- : in std_logic;
Cnt_by_32 => '0', -- : in std_logic;
Cnt_by_64 => '0', -- : in std_logic;
Cnt_by_128 => '0', -- : in std_logic;
Clk_En_0 => cken0, -- : in std_logic;
Clk_En_1 => cken0, -- : in std_logic;
Clk_En_2 => cken0, -- : in std_logic;
Clk_En_3 => cken0, -- : in std_logic;
Clk_En_4 => cken0, -- : in std_logic;
Clk_En_5 => cken0, -- : in std_logic;
Clk_En_6 => cken0, -- : in std_logic;
Clk_En_7 => cken0, -- : in std_logic;
Addr_out => address_cnt, -- : out std_logic_vector(C_AWIDTH-1 downto 0);
Next_addr_out => next_address_cnt,
Carry_Out => open -- : out std_logic;
);
end implementation;
| bsd-3-clause | 0a7b8b95fe84a9469a2b7930152c3814 | 0.429856 | 4.431046 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/park_lock_logic.vhd | 3 | 24,460 | -------------------------------------------------------------------------------
-- $Id: park_lock_logic.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- park_lock_logic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: park_lock_logic.vhd
-- Version: v1.02e
-- Description:
-- This file contains the grant_last_register logic, the park
-- logic, and the grant_logic which determines the final grant
-- signal to the Masters.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/24/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- Modified the code so that the arbitration cycle and/or the internal grant
-- register enables are based off the external grants, i.e., grants output
-- to the bus taking into account buslock and park.
-- This file now generates Any_mgrant which indicates when any external grant
-- is asserted and Bus_park which indicates when the bus is parked. Also,
-- OPB_buslock now gates the internal grant signals and bus parking.
-- ~~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- LCW 02/04/05 - update library statements
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
-- Package file that contains constant definition for RESET_ACTIVE and function
-- pad_4
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_MASTERS -- number of Masters
-- C_NUM_MID_BITS -- number of bits required for master IDs
-- C_PARK -- parking supported
-- C_REG_GRANTS -- register grant outputs
--
-- Definition of Ports:
--
-- input Arb_cycle -- Valid arbitration cycle
-- input OPB_buslock -- Bus is locked
--
-- -- Control register interface
-- input Park_master_notlast -- Park on Master not last
-- input Park_master_id -- Master ID to park on
-- input Park_enable -- Enable parking
--
-- -- Intermediate grant signals from arbitration logic
-- input Grant
--
-- -- Master request signals
-- input M_request
--
-- -- Final Master grant signals
-- output Opb_mgrant -- output grants to masters
-- -- may be registered if C_REG_GRANTS=true
-- output MGrant -- cmb grant outputs to priority reg logic
-- output MGrant_n -- cmb active low grant signals to
-- -- priority reg logic
--
-- -- Clock and reset
-- input Clk;
-- input Rst;
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity park_lock_logic is
generic( C_NUM_MASTERS : integer := 8;
C_NUM_MID_BITS : integer := 3;
C_PARK : boolean := false;
C_REG_GRANTS : boolean := true );
port (
Arb_cycle : in std_logic;
OPB_buslock : in std_logic;
Park_master_notlast : in std_logic;
Park_master_id : in std_logic_vector(0 to C_NUM_MID_BITS-1);
Park_enable : in std_logic;
Grant : in std_logic_vector(0 to C_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1);
Bus_park : out std_logic;
Any_mgrant : out std_logic;
OPB_Mgrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
Mgrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
MGrant_n : out std_logic_vector(0 to C_NUM_MASTERS-1);
Clk : in std_logic;
Rst : in std_logic
);
end park_lock_logic;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of park_lock_logic is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- pad number of masters(requests) and Park_enable to nearest multiple of 4
constant NUM_REQ_PAD : integer := pad_4(C_NUM_MASTERS);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- 1-hot register indicating which master was granted the bus
signal grant_last_reg : std_logic_vector(0 to C_NUM_MASTERS-1);
-- Signal indicating that a grant was asserted
signal any_grant : std_logic;
-- 1-hot bus indicating which master has locked the bus
signal locked : std_logic_vector(0 to C_NUM_MASTERS-1);
-- 1-hot bus indicating which master the bus is parked on
signal park : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal park_d1 : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal park_fe : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- signal indicating if other masters are parked
signal others_park : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- signals indicating if other masters are requesting the bus
signal pend_req_cmb : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal pend_req : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-- indicates if any master is requesting the bus
signal any_request : std_logic_vector(0 to 0) := (others => '0');
-- internal grant signals
signal mgrant_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal mgrant_n_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
signal mgrant_reg_i : std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Xilinx primitives are used to generate the PARK signals
-- OR_BITS is used to OR all of the Grant signals so that the Grant_last_reg
-- can be updated.
-- OR_GATE is used to determine if there are any pending requests for the
-- park logic and to determine if any master is parked
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- GRANT_LAST_REGISTER registers the grant signals for use in determining
-- parking and locking.
-- This register is clock enabled by the OR of all the Master grant signals,
-- i.e. only register the grant signals when a new grant has been issued.
-- Note that the GRANT_LAST_REGISTER uses registered internal grant signals
-- when design is configured for registered grant outputs. It uses combinational
-- grant signals when configured for combinational internal grant outputs
-------------------------------------------------------------------------------
REGGRNTS_LASTGRNT: if C_REG_GRANTS generate
begin
-- use internal registered grant signals
OR_GRANTS_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => mgrant_reg_i,
Sig => '0',
Or_out => any_grant
);
LASTGRNT_REG_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
grant_last_reg <= (others => '0');
elsif any_grant = '1' then
grant_last_reg <= mgrant_reg_i;
else
grant_last_reg <= grant_last_reg;
end if;
end if;
end process LASTGRNT_REG_PROCESS;
end generate REGGRNTS_LASTGRNT;
CMBGRNTS_LASTGRNT: if not(C_REG_GRANTS) generate
begin
-- use internal combinational grant signals
OR_GRANTS_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => mgrant_i,
Sig => '0',
Or_out => any_grant
);
LASTGRNT_REG_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
grant_last_reg <= (others => '0');
elsif any_grant = '1' then
grant_last_reg <= mgrant_i;
else
grant_last_reg <= grant_last_reg;
end if;
end if;
end process LASTGRNT_REG_PROCESS;
end generate CMBGRNTS_LASTGRNT;
-------------------------------------------------------------------------------
-- LOCK signals indicate which Master (if any) has locked the bus. Only a Master
-- which has been granted the bus and is still requesting can lock it.
-------------------------------------------------------------------------------
LOCK_GEN: for i in 0 to C_NUM_MASTERS-1 generate
locked(i) <= '1' when grant_last_reg(i) = '1' and OPB_buslock = '1'
else '0';
end generate LOCK_GEN;
-------------------------------------------------------------------------------
-- PARK signals indicate which Master to park the bus on based on the Park
-- Enable, Park Master Not Last, and Park Master ID bits in the Control
-- Register. This code is only implemented if C_PARK=true indicating that
-- parking is supported. If C_PARK=false, the park bus and all OPB park signals
-- stay at their default values of 0.
-------------------------------------------------------------------------------
PARKLOGIC_GEN: if C_PARK generate
-- For each master, must determine if there are any other requests and if parking is enabled
PENDREQ_GEN: for i in 0 to C_NUM_MASTERS-1 generate
signal or_gate_input : std_logic_vector(0 to C_NUM_MASTERS-2);
begin
OR_ALL_BUT_SELF_PROCESS: process (M_request) is
variable k : integer := 0;
begin
for j in 0 to i-1 loop
or_gate_input(j) <= M_request(j);
end loop;
for j in i+1 to C_NUM_MASTERS-1 loop
or_gate_input(j-1) <= M_request(j);
end loop;
end process OR_ALL_BUT_SELF_PROCESS;
PENDREQ_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS-1,1,TRUE)
port map (or_gate_input,pend_req(i to i));
end generate PENDREQ_GEN;
-- If parking is enabled and there are no pending requests, then determine
-- which master to park on based on the PMNL bit.
-- If park on master not last = 0, then park on last master, i.e, park =
-- grant_last_reg. Otherwise, park on master whose ID is set in control register.
-- Register the master's park signals
PARK_GEN: for i in 0 to C_NUM_MASTERS-1 generate
signal park_or_gate_input : std_logic_vector(0 to C_NUM_MASTERS-2);
begin
PARK_PROCESS: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
park(i) <= '0';
elsif pend_req(i) = '0' and Park_enable = '1' then
if Park_master_notlast = '1' then
if Park_master_id = conv_std_logic_vector(i, C_NUM_MID_BITS) then
park(i) <= '1';
else
park(i) <= '0';
end if;
else
park(i) <= grant_last_reg(i);
end if;
else
park(i) <= '0';
end if;
end if;
end process PARK_PROCESS;
-- When the grant outputs are registered, the parked master's grant won't negate
-- until a clock after parking is disabled. Since the park bus is registered,
-- the grant signal must negate as soon as possible after the park bus negates,
-- therefore, use the falling edge of each masters' park to asynchronously reset
-- that master's OPB_MGrant register.
PARK_D1_PROCESS: process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
park_d1(i) <= '0';
else
park_d1(i) <= park(i);
end if;
end if;
end process PARK_D1_PROCESS;
park_fe(i) <= '1' when park(i) = '0' and park_d1(i) = '1'
else '0';
-- determine if other masters are parked so that the grant from the arbitration
-- logic can be properly gated.
OR_ALLPARK_BUT_SELF_PROCESS: process (park) is
variable k : integer := 0;
begin
for j in 0 to i-1 loop
park_or_gate_input(j) <= park(j);
end loop;
for j in i+1 to C_NUM_MASTERS-1 loop
park_or_gate_input(j-1) <= park(j);
end loop;
end process OR_ALLPARK_BUT_SELF_PROCESS;
OTHERSPARK_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS-1,1,TRUE)
port map (park_or_gate_input,others_park(i to i));
end generate PARK_GEN;
-- determine if parked on any master
OR_PARK_I: entity opb_v20_v1_10_d.or_bits
generic map( C_NUM_BITS => C_NUM_MASTERS,
C_START_BIT => 0,
C_BUS_SIZE => C_NUM_MASTERS)
port map ( In_bus => park,
Sig => '0',
Or_out => Bus_park
);
end generate PARKLOGIC_GEN;
NOPARK_GEN: if not(C_PARK) generate
Bus_park <= '0';
park <= (others => '0');
others_park <= (others => '0');
park_fe <= (others => '0');
end generate NOPARK_GEN;
-------------------------------------------------------------------------------
-- GRANT_LOGIC determines the final Master grant signals based on the park/lock
-- signals and the intermediate grant signals from the arbitration logic.
-- The MGrant signals are always combinatorial and are used by the priority
-- register logic.
-------------------------------------------------------------------------------
GRANT_GEN: for i in 0 to C_NUM_MASTERS-1 generate
mgrant_i(i) <= '1' when arb_cycle = '1' and
((grant(i)='1' and others_park(i)='0' and OPB_buslock = '0')
or (park(i) = '1' and OPB_buslock = '0')
or (locked(i) = '1' and M_request(i)='1'))
else '0';
mgrant_n_i(i) <= '0' when arb_cycle = '1' and
((grant(i)='1' and others_park(i)='0' and OPB_buslock = '0')
or (park(i) = '1' and OPB_buslock = '0')
or (locked(i) = '1' and M_request(i)='1'))
else '1';
-- Register the grant signals if registered grant outputs
-- reset this register with park_fe
REGGRNT_GEN: if (C_REG_GRANTS) generate
REGGRNT_PROCESS: process (Clk, park_fe(i))
begin
-- asynchronously reset when park negates
if park_fe(i) = '1' then
mgrant_reg_i(i) <= '0';
elsif Clk'event and Clk='1' then
if Rst = RESET_ACTIVE then
mgrant_reg_i(i) <= '0';
else
mgrant_reg_i(i) <= mgrant_i(i);
end if;
end if;
end process REGGRNT_PROCESS;
end generate REGGRNT_GEN;
end generate GRANT_GEN;
-------------------------------------------------------------------------------
-- Assign internal signals to outputs
-- Master grant signal outputs are registered or combinatorial based on the
-- C_REG_GRANTS parameter.
-------------------------------------------------------------------------------
MGrant <= mgrant_i;
MGrant_n <= mgrant_n_i;
Any_mgrant <= any_grant;
REGGRANT_GEN: if C_REG_GRANTS generate
OPB_MGrant <= mgrant_reg_i;
end generate REGGRANT_GEN;
CMBGRANT_GEN: if not(C_REG_GRANTS) generate
OPB_MGrant <= mgrant_i;
end generate CMBGRANT_GEN;
end implementation;
| bsd-3-clause | e2e5fb9deb57d41c6c9ba7c07e0bd1c1 | 0.469583 | 4.564284 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_bram_if_cntlr_v1_00_a/hdl/vhdl/opb_bram_if_cntlr.vhd | 2 | 30,427 | -------------------------------------------------------------------------------
-- $Id: opb_bram_if_cntlr.vhd,v 1.10 2003/06/27 14:20:34 anitas Exp $
-------------------------------------------------------------------------------
-- opb_bram_if_cntlr.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2003 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_bram_if_cntlr.vhd
-- Version: v1.00a
-- Description: This is the top-level design file for the OPB External Bus
-- Controller. It supports 1-16 masters and control for BRAM
-- modules.
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_bram_if_cntlr.vhd
-- -- bram_if.vhd
--
--
-------------------------------------------------------------------------------
-- Author: DAB
-- History:
-- DAB 06-12-2002 -- First version
-- ALS 05-14-2003
-- ^^^^^^
-- Upgraded to latest OPB_BAM (replaces OPB_IPIF) and added support for bursting
-- ~~~~~~
-- ALS 05-27-2003
-- ^^^^^^
-- Removed XST "dummy" entries in arrays
-- ~~~~~~
-- ALS 06-24-2003
-- ^^^^^^
-- Use proc_common_v1_00_b library to be consistent with bram_if_cntlr and
-- plb_bram_if_cntlr.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.all;
use proc_common_v1_00_b.all;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.ipif_pkg.all;
use ipif_common_v1_00_c.all;
library opb_ipif_v3_00_a;
use opb_ipif_v3_00_a.all;
library bram_if_cntlr_v1_00_a;
use bram_if_cntlr_v1_00_a.all;
--
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
--
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- BRAM memory base address
-- C_HIGHADDR -- BRAM memory high address
-- C_INCLUDE_BURST_SUPPORT -- include support for PLB burst/cachelines
-- C_OPB_DWIDTH -- OPB data bus width
-- C_OPB_AWIDTH -- OPB address bus width
-- C_OPB_CLK_PERIOD_PS -- OPB clock period in pico-seconds
--
-- Definition of Ports:
-- OPB Bus
-- OPB_ABus -- OPB address bus
-- OPB_DBus -- OPB data bus
-- Sln_DBus -- Slave read bus
-- OPB_select -- OPB Select
-- OPB_RNW -- OPB read not write
-- OPB_seqAddr -- OPB sequential address
-- OPB_BE -- OPB byte enables
-- Sln_xferAck -- Slave transfer acknowledge
-- Sln_errAck -- Slave Error acknowledge
-- Sln_toutSup -- Slave Timeout Suppress
-- Sln_retry -- Slave retry
--
-- BRAM interface signals
-- BRAM_Rst -- BRAM reset
-- BRAM_CLK -- BRAM clock
-- BRAM_EN -- BRAM chip enable
-- BRAM_WEN -- BRAM write enable
-- BRAM_Addr -- BRAM address
-- BRAM_Dout -- BRAM write data
-- BRAM_Din -- BRAM read data
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity opb_bram_if_cntlr is
-- Generics to be set by user
generic (
C_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_HIGHADDR : std_logic_vector := X"0000_0000";
--Generics set for IPIF
C_INCLUDE_BURST_SUPPORT : integer := 0;
C_OPB_DWIDTH : integer := 32;
C_OPB_AWIDTH : integer := 32;
C_OPB_CLK_PERIOD_PS : integer := 40000
);
port
(
-- System Port Declarations ********************************************
OPB_Clk : in std_logic;
OPB_Rst : in std_logic;
-- OPB Port Declarations ***********************************************
OPB_ABus : in std_logic_vector(0 to C_OPB_AWIDTH - 1 );
OPB_DBus : in std_logic_vector(0 to C_OPB_DWIDTH - 1 );
Sln_DBus : out std_logic_vector(0 to C_OPB_DWIDTH - 1 );
OPB_select : in std_logic := '0';
OPB_RNW : in std_logic := '0';
OPB_seqAddr : in std_logic := '0';
OPB_BE : in std_logic_vector(0 to C_OPB_DWIDTH/8 - 1 );
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_toutSup : out std_logic;
Sln_retry : out std_logic;
-- User BRAM Port
BRAM_Rst : out std_logic;
BRAM_Clk : out std_logic;
BRAM_EN : out std_logic;
BRAM_WEN : out std_logic_vector(0 to C_OPB_DWIDTH/8 - 1);
BRAM_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1);
BRAM_Din : in std_logic_vector(0 to C_OPB_DWIDTH-1);
BRAM_Dout : out std_logic_vector(0 to C_OPB_DWIDTH-1)
);
--fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of OPB_Clk : signal is "10000";
attribute MAX_FANOUT of OPB_Rst : signal is "10000";
-- PSFUtil MPD attributes
attribute MIN_SIZE : string;
attribute MIN_SIZE of C_BASEADDR : constant is "0x800";
attribute SIGIS : string;
attribute SIGIS of OPB_Clk : signal is "CLK";
attribute SIGIS of OPB_Rst : signal is "RST";
attribute SPECIAL : string;
attribute SPECIAL of opb_bram_if_cntlr:entity is "BRAM_CNTLR";
attribute ADDR_SLICE : integer;
attribute ADDR_SLICE of opb_bram_if_cntlr:entity is 29;
attribute NUM_WRITE_ENABLES : integer;
attribute NUM_WRITE_ENABLES of opb_bram_if_cntlr:entity is 4;
attribute AWIDTH : integer;
attribute AWIDTH of opb_bram_if_cntlr:entity is 32;
attribute DWIDTH : integer;
attribute DWIDTH of opb_bram_if_cntlr:entity is 32;
end opb_bram_if_cntlr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of opb_bram_if_cntlr is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------- Pipeline Model -------------------------------------------
-- Note: the OPBOUT pipeline registers are always required as the reset to
-- these registers is what guarantees that the Sln_DBus is zero'd at the end
-- of the read transaction
-- for smaller latency and perhaps potentially slower Fmax,
-- include only OPBOUT pipeline registers
-- set the PIPELINE_MODEL constant to 4
constant PIPELINE_MODEL : integer := 4;
-- for 1 clock more latency and perhaps potentially faster Fmax,
-- include OPBIN and OPBOUT pipeline registers
-- set the PIPELINE_MODEL constant to 5
--constant PIPELINE_MODEL : integer := 5;
constant BRAM : integer := 120;
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => BRAM -- Memory
);
constant ZEROES : std_logic_vector := X"00000000";
constant ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
ZEROES & C_BASEADDR, -- BRAM Base Address
ZEROES & C_HIGHADDR -- BRAM High Address
);
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_OPB_DWIDTH -- BRAM data width
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 1 -- BRAM CE number
);
constant IP_INTR_MODE_ARRAY : integer_array_type := (1,1);
constant ZERO_AWIDTH : std_logic_vector(0 to C_OPB_AWIDTH - 1)
:= (others => '0');
constant ZERO_DWIDTH : std_logic_vector(0 to C_OPB_DWIDTH - 1)
:= (others => '0');
constant ZERO_BE : std_logic_vector(0 to C_OPB_DWIDTH/8 - 1)
:= (others => '0');
constant ZERO_INTR : std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1)
:= (others => '0');
constant ZERO_POSTED_WRINH : std_logic_vector(0 to ARD_ID_ARRAY'length-1)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- IPIC Used Signals
signal ip2bus_rdack : std_logic;
signal IP2Bus_wrAck : std_logic;
signal IP2Bus_Ack : std_logic_vector(0 to ARD_ID_ARRAY'length-1);
signal IP2Bus_toutSup : std_logic_vector(0 to ARD_ID_ARRAY'length-1);
signal IP2Bus_retry : std_logic_vector(0 to ARD_ID_ARRAY'length-1);
signal IP2Bus_errAck : std_logic_vector(0 to ARD_ID_ARRAY'length-1);
signal IP2Bus_Data : std_logic_vector(0 to C_OPB_DWIDTH*calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Bus2IP_Addr : std_logic_vector(0 to C_OPB_AWIDTH - 1);
signal Bus2IP_Data : std_logic_vector(0 to C_OPB_DWIDTH - 1);
signal Bus2IP_RNW : std_logic;
signal Bus2IP_RdReq : std_logic;
signal Bus2IP_WrReq : std_logic;
signal Bus2IP_CS : std_logic_vector(0 to ((ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal Bus2IP_CE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Bus2IP_BE : std_logic_vector(0 to (C_OPB_DWIDTH / 8) - 1);
signal Bus2IP_Burst : std_logic;
signal Bus2IP_Clk : std_logic;
signal Bus2IP_Reset : std_logic;
-- registered signals
signal bus2ip_rdce_d1 : std_logic;
-- internal signals
signal bram_if_address : std_logic_vector(0 to C_OPB_AWIDTH-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component opb_ipif
generic
(
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE
:= ( 0 => IPIF_INTR,
1 => IPIF_RST,
2 => USER_00
);
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= ( x"0000_0000_6000_0000", -- IPIF_INTR
x"0000_0000_6000_003F",
--
x"0000_0000_6000_0040", -- IPIF_RST
x"0000_0000_6000_0043",
--
x"0000_0000_6000_0100", -- USER_00
x"0000_0000_6000_01FF"
);
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE
:= ( 32, -- IPIF_INTR
32, -- IPIF_INTR
32 -- USER_00
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
:= ( 16, -- IPIF_INTR
1, -- IPIF_RST
8 -- USER_00
);
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE
:= (
0 => (others => 0)
,1 => (others => 0)
,2 => (others => 0)
);
C_PIPELINE_MODEL : integer := 7;
-- The pipe stages are enumerated and numbered as:
-- -- ----------
-- n Pipe stage
-- -- ----------
-- 0 OPBIN
-- 1 IPIC
-- 2 OPBOUT
-- Each pipe stage is either present or absent (i.e. bypassed).
-- The pipe stage, n, is present iff the (2^n)th
-- bit in C_PIPELINE_MODEL is 1.
--
C_DEV_BLK_ID : INTEGER := 1;
-- Unique block ID, assigned to the device when the system is built.
C_DEV_MIR_ENABLE : INTEGER := 0;
C_AWIDTH : INTEGER := 32;
-- width of Address Bus (in bits)
C_DWIDTH : INTEGER := 32;
-- Width of the Data Bus (in bits)
C_FAMILY : string := "virtexe";
--
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 5, 1 );
--
-- There will be one interrupt signal for each entry in
-- C_IP_INTR_MODE_ARRAY. The leftmost entry will be the
-- mode for input port IP2Bus_Intr(0), the next entry
-- for IP2Bus_Intr(1), etc.
--
-- These modes are supported:
--
-- Mode Description
--
-- 1 Active-high interrupt condition.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port-- that is an interrupt condition
-- that is latched and cleared in the IP core and made available
-- to the system via the Interrupt Source Controller in
-- the Bus Attachment Module.
--
-- 2 Active-low interrupt condition.
-- Like 1, except that the interrupt condition is asserted low.
--
-- 3 Active-high pulse interrupt event.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port--whose single clock period of active-high
-- assertion is an interrupt event that is latched,
-- and cleared as a service of the Interrupt Source
-- Controller in the Bus Attachment Module.
--
-- 4 Active-low pulse interrupt event.
-- Like 3, except the interrupt-event pulse is active low.
--
-- 5 Positive-edge interrupt event.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port--whose low-to-high transition, synchronous
-- with the clock, is an interrupt event that is latched,
-- and cleared as a service of the Interrupt Source
-- Controller in the Bus Attachment Module.
--
-- 6 Negative-edge interrupt event.
-- Like 5, except that the interrupt event is a
-- high-to-low transition.
--
-- Other mode codes are reserved.
--
C_INCLUDE_DEV_ISC : INTEGER := 1;
-- 'true' specifies that the full device interrupt
-- source controller structure will be included;
-- 'false' specifies that only the global interrupt
-- enable register of the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller
C_INCLUDE_DEV_IID : integer := 0;
-- 'true' will include the Device IID register in the device ISC
C_DEV_BURST_ENABLE : INTEGER := 0
-- Burst Enable for IPIF Interface
);
port
(
OPB_select : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_DWIDTH-1);
OPB_ABus : in std_logic_vector(0 to C_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
OPB_xferAck : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_DWIDTH-1);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Bus2IP_CS : out std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Data : out std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_BE : out std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RNW : out std_logic;
Bus2IP_Burst : out std_logic;
IP2Bus_Data : in std_logic_vector(0 to C_DWIDTH*calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
IP2Bus_Ack : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Error : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Retry : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_ToutSup : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_PostedWrInh : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
OPB_Clk : in std_logic;
Bus2IP_Clk : out std_logic;
IP2Bus_Clk : in std_logic;
Reset : in std_logic;
Bus2IP_Reset : out std_logic;
IP2Bus_Intr : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
Device_Intr : out std_logic
);
end component opb_ipif;
component bram_if
generic (
C_IPIF_AWIDTH : Integer := 32;
-- The width if the IPIF address bus
C_IPIF_DWIDTH : Integer := 32
-- The width of the IPIF data bus
);
port (
-- input ports
bus_reset : in std_logic;
bus_clk : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_AWIDTH-1);
Bus2IP_Data : in std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_BRAM_CS : in std_logic;
Bus2IP_RNW : in std_logic;
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
-- Output ports
IP2Bus_Data : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic;
--BRAM Ports
BRAM_Rst : out std_logic;
BRAM_CLK : out std_logic;
BRAM_EN : out std_logic;
BRAM_WEN : out std_logic_vector(0 to C_IPIF_DWIDTH/8 - 1 );
BRAM_Addr : out std_logic_vector(0 to C_IPIF_AWIDTH-1);
BRAM_Dout : out std_logic_vector(0 to C_IPIF_DWIDTH-1);
BRAM_Din : in std_logic_vector(0 to C_IPIF_DWIDTH-1)
);
end component;
component direct_path_cntr
generic (
C_WIDTH : natural := 8
);
port (
Clk : in std_logic;
Din : in std_logic_vector(0 to C_WIDTH-1);
Dout : out std_logic_vector(0 to C_WIDTH-1);
Load_n : in std_logic;
Cnt_en : in std_logic
);
end component direct_path_cntr;
begin -- architecture IMP
-------------------------------------------------------------------------------
-- Signal assignments to make new IPIC more like original
-------------------------------------------------------------------------------
-- if bursts are enabled, instantiate address counter for read bursts
-- note: this assumes that burst reads will be of OPB_DWIDTH size
BURST_GENERATE: if C_INCLUDE_BURST_SUPPORT=1 generate
constant DATA_OFFSET : integer := log2(C_OPB_DWIDTH/8);
constant BRST_CNT_WIDTH : integer := C_OPB_AWIDTH -
addr_bits(C_BASEADDR, C_HIGHADDR);
constant ZERO_LOW_ADDR_BITS : std_logic_vector(0 to DATA_OFFSET-1)
:= (others => '0');
signal burst_cnt : std_logic_vector(0 to BRST_CNT_WIDTH - DATA_OFFSET -1);
signal load_n : std_logic;
signal burst_rdaddr : std_logic_vector(0 to C_OPB_AWIDTH-1);
begin
load_n <= (Bus2IP_Burst and Bus2IP_RNW);
I_BRST_CNT: direct_path_cntr
generic map(
C_WIDTH => BRST_CNT_WIDTH-DATA_OFFSET
)
port map (
Clk => OPB_Clk,
Din => Bus2IP_Addr(C_OPB_AWIDTH-BRST_CNT_WIDTH
to C_OPB_AWIDTH - DATA_OFFSET -1),
Cnt_en => Bus2IP_Burst,
Load_n => load_n,
Dout => burst_cnt
);
burst_rdaddr <= Bus2IP_Addr(0 to C_OPB_AWIDTH-BRST_CNT_WIDTH-1) &
burst_cnt & ZERO_LOW_ADDR_BITS;
bram_if_address <= burst_rdaddr;
end generate BURST_GENERATE;
-- If bursts aren't supported, set bram_if_address to Bus2IP_Addr
NOBURST_GENERATE: if C_INCLUDE_BURST_SUPPORT=0 generate
bram_if_address <= Bus2IP_Addr;
end generate NOBURST_GENERATE;
-- rdack is simply a registered version of RdCE to account for registered
-- output of BRAMs
IP2BUS_RDACK_PROC: process (Bus2IP_Clk)
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_CS(0) = '0' then
ip2bus_rdack <= '0';
else
ip2bus_rdack <= Bus2IP_RdCE(0);
end if;
end if;
end process;
IP2Bus_Ack(0) <= ip2bus_rdack or IP2Bus_WrAck after 1 ns;
Bus2IP_RdReq <= Bus2IP_RdCE(0);
Bus2IP_WrReq <= Bus2IP_WrCE(0);
-------------------------------------------------------------------------------
-- Component Instantiations
-------------------------------------------------------------------------------
I_opb_ipif: opb_ipif
generic map(
-- Generics to be set for ipif
C_ARD_ID_ARRAY => ARD_ID_ARRAY ,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY ,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY ,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY ,
C_PIPELINE_MODEL => PIPELINE_MODEL ,
C_DEV_MIR_ENABLE => 0 ,
C_AWIDTH => C_OPB_AWIDTH ,
C_DWIDTH => C_OPB_DWIDTH ,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY ,
C_INCLUDE_DEV_ISC => 0 ,
C_DEV_BURST_ENABLE => C_INCLUDE_BURST_SUPPORT
)
port map (
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
OPB_xferAck => '0',
Sln_DBus => Sln_DBus,
Sln_xferAck => Sln_xferAck,
Sln_errAck => Sln_errAck,
Sln_retry => Sln_retry,
Sln_toutSup => Sln_toutSup,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_CE => Bus2IP_CE,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_Burst => Bus2IP_Burst,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_Ack => IP2Bus_Ack,
IP2Bus_Error => IP2Bus_errAck,
IP2Bus_Retry => IP2Bus_Retry,
IP2Bus_ToutSup => IP2Bus_toutSup,
IP2Bus_PostedWrInh => ZERO_POSTED_WRINH,
OPB_Clk => OPB_Clk,
Bus2IP_Clk => Bus2IP_Clk,
IP2Bus_Clk => '0',
Reset => OPB_Rst,
Bus2IP_Reset => Bus2IP_Reset,
IP2Bus_Intr => ZERO_INTR,
Device_Intr => open
);
-------------------------------------------------------------------------------
-- Instantiate BRAM controller
-------------------------------------------------------------------------------
I_BRAM_CONTROLLER: bram_if
generic map(
C_IPIF_DWIDTH => C_OPB_DWIDTH,
C_IPIF_AWIDTH => C_OPB_AWIDTH
)
port map (
bus_reset => Bus2IP_Reset,
bus_clk => Bus2IP_Clk,
Bus2IP_Addr => bram_if_address,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_WrReq => Bus2IP_WrReq,
Bus2IP_RdReq => Bus2IP_RdReq,
Bus2IP_BRAM_CS => Bus2IP_CS(0),
IP2Bus_Data => IP2Bus_Data(0 to C_OPB_DWIDTH-1),
IP2Bus_Error => IP2Bus_errAck(0),
IP2Bus_retry => IP2Bus_retry(0),
IP2Bus_toutSup => IP2Bus_toutSup(0),
IP2Bus_RdAck => open, -- use the rdack generated above
IP2Bus_WrAck => IP2Bus_WrAck,
BRAM_Rst => BRAM_Rst,
BRAM_Clk => BRAM_Clk,
BRAM_EN => BRAM_EN,
BRAM_WEN => BRAM_WEN,
BRAM_Addr => BRAM_Addr,
BRAM_Din => BRAM_Din,
BRAM_Dout => BRAM_Dout
);
end implementation;
| bsd-3-clause | 0d4f28511d28d983942d07c5881ec3cf | 0.45292 | 4.176091 | false | false | false | false |
QuickJack/logi-hard | hdl/utils/logi_utils_pack.vhd | 1 | 4,785 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.log2;
use IEEE.MATH_REAL.ceil;
package logi_utils_pack is
function nbit(max : integer) return integer;
function count_ones(slv : std_logic_vector) return natural;
function max(LEFT : integer ; RIGHT: integer) return integer ;
type fifo16_bus is
record
fifo_data_in : std_logic_vector(15 downto 0);
fifo_data_out : std_logic_vector(15 downto 0);
fifo_wr : std_logic ;
fifo_rd : std_logic ;
fifo_full : std_logic ;
fifo_empty : std_logic ;
fifo_nb_free : std_logic_vector(15 downto 0);
fifo_nb_available : std_logic_vector(15 downto 0);
end record;
type slv8_array is array (natural range <>) of std_logic_vector(7 downto 0);
type slv16_array is array (natural range <>) of std_logic_vector(15 downto 0);
type slv32_array is array (natural range <>) of std_logic_vector(31 downto 0);
component simple_counter is
generic(NBIT : positive := 4);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sreset : in STD_LOGIC;
en : in STD_LOGIC;
load : in STD_LOGIC;
E : in STD_LOGIC_VECTOR(NBIT - 1 downto 0);
Q : out STD_LOGIC_VECTOR(NBIT - 1 downto 0)
);
end component;
component up_down_counter is
generic(NBIT : positive := 4);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sraz : in STD_LOGIC;
en, load : in STD_LOGIC;
up_downn : in STD_LOGIC;
E : in STD_LOGIC_VECTOR(NBIT - 1 downto 0);
Q : out STD_LOGIC_VECTOR(NBIT - 1 downto 0)
);
end component;
component generic_latch is
generic(NBIT : positive := 8);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sraz : in STD_LOGIC;
en : in STD_LOGIC;
d : in STD_LOGIC_VECTOR((NBIT - 1) downto 0);
q : out STD_LOGIC_VECTOR((NBIT - 1) downto 0));
end component;
component edge_triggered_latch is
generic(NBIT : positive := 8; POL : std_logic :='1');
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sraz : in STD_LOGIC;
en : in STD_LOGIC;
d : in STD_LOGIC_VECTOR((NBIT - 1) downto 0);
q : out STD_LOGIC_VECTOR((NBIT - 1) downto 0));
end component;
component generic_delay is
generic( WIDTH : positive := 1; DELAY : positive := 1);
port(
clk, resetn : std_logic ;
input : in std_logic_vector((WIDTH - 1) downto 0);
output : out std_logic_vector((WIDTH - 1) downto 0)
);
end component;
component dp_fifo is
generic(N : natural := 128 ;
W : positive := 16;
SYNC_WR : boolean := false;
SYNC_RD : boolean := false);
port(
clk, resetn, sraz : in std_logic;
wr, rd : in std_logic;
empty, full : out std_logic ;
data_out : out std_logic_vector((W - 1) downto 0 );
data_in : in std_logic_vector((W - 1) downto 0 );
nb_available : out unsigned(nbit(N) downto 0 )
);
end component;
component small_stack is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
component generic_rs_latch is
port(clk, resetn : in std_logic ;
s, r : in std_logic ;
q : out std_logic );
end component;
component detect_value is
generic(to_be_detected : integer := 16;
nbit : positive := 32);
port(
value : in std_logic_vector(nbit-1 downto 0);
detected : out std_logic
);
end component;
end logi_utils_pack;
package body logi_utils_pack is
function nbit (max : integer) return integer is
begin
if max = 0 then
return 1 ;
end if;
return (integer(ceil(log2(real(max)))));
end nbit;
function count_ones(slv : std_logic_vector) return natural is
variable n_ones : natural := 0;
begin
for i in slv'range loop
if slv(i) ='1' then
n_ones := n_ones + 1;
end if;
end loop;
return n_ones;
end function count_ones;
function max(LEFT : integer; RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
end logi_utils_pack;
| lgpl-3.0 | 7b7661ca481b735ab4a241e5bcb0cd7d | 0.632184 | 3.168874 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_broadcast_2.vhd | 2 | 22,394 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_broadcast_2.c
-- NUM_THREADS = 3
-- reg1 = i
-- reg2 = * mutex
-- reg3 = * cond
-- reg4 = * start_num
-- reg5 = * havelock_num
-- reg6 = * function
-- reg7 = thread[i]
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of cond
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg3_next <= intrfc2thrd_value;
-- Read the address of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg4_next <= intrfc2thrd_value;
-- Read the address of waken_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 12;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg5_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 16;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- for( i=0; i<NUM_THREADS; i++ )
when STATE_6 =>
reg6_next <= intrfc2thrd_value;
-- set i=0
reg1_next <= Z32;
next_state <= STATE_7;
when STATE_7 =>
case reg1 is
when x"00000000" => next_state <= STATE_8;
when x"00000001" => next_state <= STATE_8;
when x"00000002" => next_state <= STATE_8;
when others => next_state <= STATE_13;
end case;
-- hthread_create( &data->thread[i], NULL, data->function, (void *) data );
when STATE_8 =>
-- push (void *) data
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push &data->thread[i]
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000014" + (reg1(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
reg1_next <= reg1 + x"00000001";
-- while( *(data->start_num) != THREAD_NUM ) hthread_yield();
when STATE_13 =>
-- Read the value of start_num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_14;
when STATE_14 =>
case intrfc2thrd_value is
when x"00000003" => next_state <= STATE_16;
when others => next_state <= STATE_15;
end case;
when STATE_15 =>
-- call hthread_yield
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_13;
next_state <= WAIT_STATE;
-- hthread_mutex_lock( data->mutex );
when STATE_16 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
-- call hthread_mutex_lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_18;
next_state <= WAIT_STATE;
-- hthread_cond_broadcast( data->cond );
when STATE_18 =>
-- push data->cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- call hthread_cond_broadcast
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_BROADCAST;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_20;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( data->mutex );
when STATE_20 =>
-- push data->mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_21;
when STATE_21 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_22;
next_state <= WAIT_STATE;
-- for( i=0; i<NUM_THREADS; i++ )
when STATE_22 =>
reg1_next <= Z32;
next_state <= STATE_23;
when STATE_23 =>
case reg1 is
when x"00000000" => next_state <= STATE_24;
when x"00000001" => next_state <= STATE_24;
when x"00000002" => next_state <= STATE_24;
when others => next_state <= STATE_28;
end case;
-- retVal = hthread_join( data->thread[i], NULL );
when STATE_24 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000014" + (reg1(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= STATE_25;
when STATE_25 =>
reg4_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_26;
when STATE_26 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_27;
when STATE_27 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_23;
next_state <= WAIT_STATE;
reg1_next <= reg1 + 1;
-- retVal = *( data->waken_num )
when STATE_28 =>
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg5;
next_state <= WAIT_STATE;
return_state_next <= STATE_29;
when STATE_29 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 27ea8f5526ea5208c933ccb10dca5fbe | 0.552514 | 3.617771 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/wbb2vme_top.vhd | 1 | 25,201 | --------------------------------------------------------------------------------
-- Title : WBB to VME Bridge
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : wbb2vme_top.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 13/01/12
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- The IP-core WBB2VME is used for interfacing the VME bus as master and as
-- slave. It is able to control external driver chips as 74VMEH22501 or 74ABT125.
-- An external SRAM is used for shared memory applications and can be accessed
-- from CPU and VME side.
-- The main functions of the 16z002-01 are:
-- o Wishbone to VME access: VME master D08(EO):D16:D32:D64:A16:A24:A32; BLT;
-- non-privileged program/data; supervisory
-- o VME to Wishbone access: VME slave D08(EO):D16:D32:D64:A16:A24:A32; BLT
-- o VME slave access routing to SRAM or other bus via Wishbone bus (e.g. PCI)
-- o VME Slot1 function with auto-detection
-- o VME Interrupter D08(O):I(7-1):ROAK
-- o VME Interrupt Handler D08(O):IH(7-1)
-- o VME Bus requester
-- o ROR (release on request);
-- o RWD (release-when done);
-- o SGL (single level 3 fair requester)
-- o VME multi-level 0-3 bus arbiter
-- o BTO VME Bus time out
-- o ADO VME Address only cycles
-- o mailbox functionality
-- o VME location monitor A16:A24:A32
-- o DMA controller with scatter gather capabilities (A24; A32; D32; D64;
-- non-privileged; supervisory)
-- o DMA access capabilities VME, SRAM and other bus via Wishbone bus (e.g. PCI)
-- o VME utility functions
-- o access to 1 MByte local SRAM accessible via Wishbone bus
-- o VME Slot geographical addressing
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_ctrl
-- vme_du
-- vme_au
-- vme_locmon
-- vme_mailbox
-- vme_master
-- vme_slave
-- vme_requester
-- vme_bustimer
-- vme_sys_arbiter
-- vme_arbiter
-- vme_wbm
-- vme_wbs
-- vme_dma
-- vme_dma_mstr
-- vme_dma_slv
-- vme_dma_arbiter
-- vme_dma_du
-- vme_dma_au
-- vme_dma_fifo
-- fifo_256x32bit
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.7 $
--
-- $Log: wbb2vme_top.vhd,v $
-- Revision 1.7 2015/09/16 09:19:48 mwawrik
-- Added generics A16_REG_MAPPING and USE_LONGADD
--
-- Revision 1.6 2014/04/17 07:35:18 MMiehling
-- added generic LONGADD_SIZE
-- added status outputs vme_berr and vme_mstr_busy
-- added signal prevent_sysrst
--
-- Revision 1.5 2013/09/12 08:45:19 mmiehling
-- added bit 8 of tga for address modifier extension
--
-- Revision 1.4 2012/11/15 09:43:50 MMiehling
-- connected each interrupt source to interface in order to support edge triggered msi
--
-- Revision 1.3 2012/09/25 11:21:37 MMiehling
-- added wbm_err signal for error signalling from pcie to vme
--
-- Revision 1.2 2012/08/27 12:57:00 MMiehling
-- changed comments
--
-- Revision 1.1 2012/03/29 10:14:27 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.vme_pkg.all;
ENTITY wbb2vme_top IS
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
postwr : OUT std_logic; -- posted write
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
dma_irq : OUT std_logic; -- interrupt request dma to pci-bus
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
test_vec : OUT test_vec_type;
-- vmectrl slave
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- vmectrl master
wbm_ctrl_stb_o : OUT std_logic;
wbm_ctrl_ack_i : IN std_logic;
wbm_ctrl_err_i : IN std_logic;
wbm_ctrl_we_o : OUT std_logic;
wbm_ctrl_sel_o : OUT std_logic_vector(3 DOWNTO 0);
wbm_ctrl_cyc_sram : OUT std_logic;
wbm_ctrl_cyc_pci : OUT std_logic;
wbm_ctrl_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ctrl_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_ctrl_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbm_dma_stb_o : OUT std_logic;
wbm_dma_ack_i : IN std_logic;
wbm_dma_we_o : OUT std_logic;
wbm_dma_cti : OUT std_logic_vector(2 DOWNTO 0);
wbm_dma_tga_o : OUT std_logic_vector(8 DOWNTO 0);
wbm_dma_err_i : IN std_logic;
wbm_dma_sel_o : OUT std_logic_vector(3 DOWNTO 0);
wbm_dma_cyc_sram : OUT std_logic;
wbm_dma_cyc_vme : OUT std_logic;
wbm_dma_cyc_pci : OUT std_logic;
wbm_dma_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dma_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dma_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- vmebus
va : INOUT std_logic_vector(31 DOWNTO 0); -- address
vd : INOUT std_logic_vector(31 DOWNTO 0); -- data
vam : INOUT std_logic_vector(5 DOWNTO 0); -- address modifier
writen : INOUT std_logic; -- write enable
iackn : INOUT std_logic; -- Handler's output
irq_i_n : IN std_logic_vector(7 DOWNTO 1); -- interrupt request inputs
irq_o_n : OUT std_logic_vector(7 DOWNTO 1); -- interrupt request outputs
as_o_n : OUT std_logic; -- address strobe out
as_oe_n : OUT std_logic; -- address strobe output enable
as_i_n : IN std_logic; -- address strobe in
sysresn : OUT std_logic; -- system reset out
sysresin : IN std_logic; -- system reset in
ds_o_n : OUT std_logic_vector(1 DOWNTO 0); -- data strobe outputs
ds_i_n : IN std_logic_vector(1 DOWNTO 0); -- data strobe inputs
ds_oe_n : OUT std_logic; -- data strobe output enable
berrn : OUT std_logic; -- bus error out
berrin : IN std_logic; -- bus error in
dtackn : OUT std_logic; -- dtack out
dtackin : IN std_logic; -- dtack in
slot01n : OUT std_logic; -- indicates whether controller has detected position in slot 1 (low active)
sysfail_i_n : IN std_logic; -- system failure interrupt input
sysfail_o_n : OUT std_logic; -- system failure interrupt output
bbsyn : OUT std_logic; -- bus busy out
bbsyin : IN std_logic; -- bus busy in
bclr_i_n : IN std_logic; -- bus clear input
bclr_o_n : OUT std_logic; -- bus clear output
retry_i_n : IN std_logic; -- bus retry input
retry_o_n : OUT std_logic; -- bus retry output
retry_oe_n : OUT std_logic; -- bus retry output enable
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus request inputs
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request outputs
iackin : IN std_logic; -- Interrupter's input
iackoutn : OUT std_logic; -- Interrupter's output
acfailn : IN std_logic; -- from Power Supply
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus grant input
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus grant output
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
-- vme status signals
vme_berr : OUT std_logic; -- indicates vme bus error (=MSTR(2)), must be cleared by sw
vme_mstr_busy : OUT std_logic; -- indicates vme bus master is active
--data bus bus control signals for vmebus drivers
d_dir : OUT std_logic; -- external driver control data direction (1: drive to vmebus 0: drive to fpga)
d_oe_n : OUT std_logic; -- external driver control data output enable low active
am_dir : OUT std_logic; -- external driver control address modifier direction (1: drive to vmebus 0: drive to fpga)
am_oe_n : OUT std_logic; -- external driver control address modifier output enable low activ
a_dir : OUT std_logic; -- external driver control address direction (1: drive to vmebus 0: drive to fpga)
a_oe_n : OUT std_logic; -- external driver control address output enable low activ
v2p_rst : OUT std_logic -- Reset between VMEbus and Host CPU
);
END wbb2vme_top;
ARCHITECTURE wbb2vme_top_arch OF wbb2vme_top IS
COMPONENT vme_ctrl
GENERIC (
A16_REG_MAPPING : boolean := TRUE; -- if true, access to vme slave A16 space goes to vme runtime registers and above 0x800 to sram (compatible to old revisions)
-- if false, access to vme slave A16 space goes to sram
LONGADD_SIZE : integer range 3 TO 8:=3;
USE_LONGADD : boolean := TRUE -- If FALSE, bits (7 DOWNTO 5) of SIGNAL longadd will be allocated to vme_adr_out(31 DOWNTO 29)
);
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
startup_rst : IN std_logic; -- powerup reset
postwr : OUT std_logic; -- posted write
vme_irq : OUT std_logic_vector(7 DOWNTO 0); -- interrupt request to pci-bus
berr_irq : OUT std_logic; -- signal berrn interrupt request
locmon_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request location monitor to pci-bus
mailbox_irq : OUT std_logic_vector(1 DOWNTO 0); -- interrupt request mailbox to pci-bus
prevent_sysrst : IN std_logic; -- if "1", sysrst_n_out will not be activated after powerup,
-- if "0", sysrst_n_out will be activated if in slot1 and system reset is active (sysc_bit or rst)
test_vec : OUT test_vec_type;
-- dma
dma_sta : OUT std_logic_vector(9 DOWNTO 0);
clr_dma_en : IN std_logic;
set_dma_err : IN std_logic;
dma_act_bd : IN std_logic_vector(7 DOWNTO 4);
-- vmectrl slave
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
-- vmectrl master
wbm_stb_o : OUT std_logic;
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_we_o : OUT std_logic;
wbm_sel_o : OUT std_logic_vector(3 DOWNTO 0);
vme_cyc_sram : OUT std_logic;
vme_cyc_pci : OUT std_logic;
wbm_adr_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbm_dat_i : IN std_logic_vector(31 DOWNTO 0);
-- the VME signals:
va : INOUT std_logic_vector(31 DOWNTO 0); -- address
vd : INOUT std_logic_vector(31 DOWNTO 0); -- data
vam : INOUT std_logic_vector(5 DOWNTO 0); -- address modifier
writen : INOUT std_logic; -- write enable
iackn : INOUT std_logic; -- Handler's output
irq_i_n : IN std_logic_vector(7 DOWNTO 1); -- interrupt request inputs
irq_o_n : OUT std_logic_vector(7 DOWNTO 1); -- interrupt request outputs
as_o_n : OUT std_logic; -- address strobe out
as_oe_n : OUT std_logic; -- address strobe output enable
as_i_n : IN std_logic; -- address strobe in
sysresn : OUT std_logic; -- system reset out
sysresin : IN std_logic; -- system reset in
ds_o_n : OUT std_logic_vector(1 DOWNTO 0); -- data strobe outputs
ds_i_n : IN std_logic_vector(1 DOWNTO 0); -- data strobe inputs
ds_oe_n : OUT std_logic; -- data strobe output enable
berrn : OUT std_logic; -- bus error out
berrin : IN std_logic; -- bus error in
dtackn : OUT std_logic; -- dtack out
dtackin : IN std_logic; -- dtack in
slot01n : OUT std_logic; -- indicates whether controller has detected position in slot 1 (low active)
sysfail_i_n : IN std_logic; -- system failure interrupt input
sysfail_o_n : OUT std_logic; -- system failure interrupt output
bbsyn : OUT std_logic; -- bus busy out
bbsyin : IN std_logic; -- bus busy in
br_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus request inputs
br_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus request outputs
iackin : IN std_logic; -- Interrupter's input
iackoutn : OUT std_logic; -- Interrupter's output
acfailn : IN std_logic; -- from Power Supply
bg_i_n : IN std_logic_vector(3 DOWNTO 0); -- bus grant input
bg_o_n : OUT std_logic_vector(3 DOWNTO 0); -- bus grant output
ga : IN std_logic_vector(4 DOWNTO 0); -- geographical addresses
gap : IN std_logic; -- geographical addresses parity
-- vme status signals
vme_berr : OUT std_logic; -- indicates vme bus error (=MSTR(2)), must be cleared by sw
vme_mstr_busy : OUT std_logic; -- indicates vme bus master is active
--data bus bus control signals for vmebus drivers
d_dir : OUT std_logic; -- external driver control data direction (1: drive to vmebus 0: drive to fpga)
d_oe_n : OUT std_logic; -- external driver control data output enable low active
am_dir : OUT std_logic; -- external driver control address modifier direction (1: drive to vmebus 0: drive to fpga)
am_oe_n : OUT std_logic; -- external driver control address modifier output enable low activ
a_dir : OUT std_logic; -- external driver control address direction (1: drive to vmebus 0: drive to fpga)
a_oe_n : OUT std_logic; -- external driver control address output enable low activ
v2p_rst : OUT std_logic -- Reset between VMEbus and Host CPU
);
END COMPONENT;
COMPONENT vme_dma
PORT (
rst : IN std_logic;
clk : IN std_logic;
irq_o : OUT std_logic;
-- vme_du
dma_sta : IN std_logic_vector(9 DOWNTO 0);
clr_dma_en : OUT std_logic;
set_dma_err : OUT std_logic;
dma_act_bd : OUT std_logic_vector(7 DOWNTO 4);
-- wb-slave
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic;
cyc_i : IN std_logic;
sel_i : IN std_logic_vector(3 DOWNTO 0);
adr_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_i : IN std_logic_vector(31 DOWNTO 0);
slv_dat_o : OUT std_logic_vector(31 DOWNTO 0);
-- wb-master
stb_o : OUT std_logic;
ack_i : IN std_logic;
we_o : OUT std_logic;
cti : OUT std_logic_vector(2 DOWNTO 0);
tga_o : OUT std_logic_vector(8 DOWNTO 0); -- type of dma
err_i : IN std_logic;
cyc_o_sram : OUT std_logic;
cyc_o_vme : OUT std_logic;
cyc_o_pci : OUT std_logic;
sel_o : OUT std_logic_vector(3 DOWNTO 0);
adr_o : OUT std_logic_vector(31 DOWNTO 0);
mstr_dat_o : OUT std_logic_vector(31 DOWNTO 0);
mstr_dat_i : IN std_logic_vector(31 DOWNTO 0)
);
END COMPONENT;
SIGNAL dma_sta : std_logic_vector(9 DOWNTO 0);
SIGNAL clr_dma_en : std_logic;
SIGNAL set_dma_err : std_logic;
SIGNAL dma_act_bd : std_logic_vector(7 DOWNTO 4);
BEGIN
bclr_o_n <= '1';
retry_o_n <= '1';
retry_oe_n <= '1';
vmectrl: vme_ctrl
GENERIC MAP (
A16_REG_MAPPING => A16_REG_MAPPING,
LONGADD_SIZE => LONGADD_SIZE,
USE_LONGADD => USE_LONGADD
)
PORT MAP(
clk => clk ,
rst => rst ,
startup_rst => startup_rst,
postwr => postwr ,
vme_irq => vme_irq ,
berr_irq => berr_irq,
locmon_irq => locmon_irq ,
mailbox_irq => mailbox_irq,
prevent_sysrst => prevent_sysrst,
test_vec => test_vec ,
dma_sta => dma_sta ,
clr_dma_en => clr_dma_en ,
set_dma_err => set_dma_err ,
dma_act_bd => dma_act_bd ,
wbs_stb_i => wbs_stb_i ,
wbs_ack_o => wbs_ack_o ,
wbs_err_o => wbs_err_o ,
wbs_we_i => wbs_we_i ,
wbs_sel_i => wbs_sel_i ,
wbs_cyc_i => wbs_cyc_i ,
wbs_adr_i => wbs_adr_i ,
wbs_dat_o => wbs_dat_o ,
wbs_dat_i => wbs_dat_i ,
wbs_tga_i => wbs_tga_i ,
wbm_stb_o => wbm_ctrl_stb_o ,
wbm_ack_i => wbm_ctrl_ack_i ,
wbm_err_i => wbm_ctrl_err_i ,
wbm_we_o => wbm_ctrl_we_o ,
wbm_sel_o => wbm_ctrl_sel_o ,
vme_cyc_sram => wbm_ctrl_cyc_sram ,
vme_cyc_pci => wbm_ctrl_cyc_pci ,
wbm_adr_o => wbm_ctrl_adr_o ,
wbm_dat_o => wbm_ctrl_dat_o ,
wbm_dat_i => wbm_ctrl_dat_i ,
va => va ,
vd => vd ,
vam => vam ,
writen => writen ,
iackn => iackn ,
irq_i_n => irq_i_n ,
irq_o_n => irq_o_n ,
as_o_n => as_o_n ,
as_oe_n => as_oe_n ,
as_i_n => as_i_n ,
sysresn => sysresn ,
sysresin => sysresin ,
ds_o_n => ds_o_n ,
ds_i_n => ds_i_n ,
ds_oe_n => ds_oe_n ,
berrn => berrn ,
berrin => berrin ,
dtackn => dtackn ,
dtackin => dtackin ,
slot01n => slot01n ,
sysfail_i_n => sysfail_i_n,
sysfail_o_n => sysfail_o_n,
bbsyn => bbsyn ,
bbsyin => bbsyin ,
br_i_n => br_i_n ,
br_o_n => br_o_n ,
iackin => iackin ,
iackoutn => iackoutn ,
acfailn => acfailn ,
bg_i_n => bg_i_n ,
bg_o_n => bg_o_n ,
ga => ga ,
gap => gap,
vme_berr => vme_berr ,
vme_mstr_busy => vme_mstr_busy,
d_dir => d_dir ,
d_oe_n => d_oe_n ,
am_dir => am_dir ,
am_oe_n => am_oe_n ,
a_dir => a_dir ,
a_oe_n => a_oe_n ,
v2p_rst => v2p_rst
);
vmedma: vme_dma
PORT MAP (
rst => rst ,
clk => clk ,
irq_o => dma_irq ,
dma_sta => dma_sta ,
clr_dma_en => clr_dma_en ,
set_dma_err => set_dma_err,
dma_act_bd => dma_act_bd ,
stb_i => '0' ,
ack_o => open ,
we_i => '0' ,
cyc_i => '0' ,
sel_i => (OTHERS => '0') ,
adr_i => (OTHERS => '0') ,
slv_dat_i => (OTHERS => '0') ,
slv_dat_o => open ,
stb_o => wbm_dma_stb_o ,
ack_i => wbm_dma_ack_i ,
we_o => wbm_dma_we_o ,
cti => wbm_dma_cti,
tga_o => wbm_dma_tga_o ,
err_i => wbm_dma_err_i ,
cyc_o_sram => wbm_dma_cyc_sram ,
cyc_o_vme => wbm_dma_cyc_vme ,
cyc_o_pci => wbm_dma_cyc_pci ,
sel_o => wbm_dma_sel_o ,
adr_o => wbm_dma_adr_o ,
mstr_dat_o => wbm_dma_dat_o ,
mstr_dat_i => wbm_dma_dat_i
);
END wbb2vme_top_arch;
| gpl-3.0 | f7c4f6ad37a604d93190af03e2368be9 | 0.478314 | 3.825288 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/interrupt_control.vhd | 3 | 37,168 | -------------------------------------------------------------------------------
-- $Id: interrupt_control.vhd,v 1.2 2003/05/07 22:45:11 ostlerf Exp $
-------------------------------------------------------------------------------
--interrupt_control.vhd version v1.00b
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- need 'conv_std_logic_vector' conversion function
library proc_common_v1_00_b;
Use proc_common_v1_00_b.proc_common_pkg.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.all;
use ipif_common_v1_00_d.all;
----------------------------------------------------------------------
entity interrupt_control is
Generic(
C_INTERRUPT_REG_NUM : INTEGER := 16;
-- Number of IPIF Interrupt sources (not including IP or the
-- two latched IPIF ISR inputs)
C_NUM_IPIF_IRPT_SRC : INTEGER := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2, -- pass through (inverting)
3, -- registered level (non-inverting)
4, -- registered level (inverting)
5, -- positive edge detect
6 -- negative edge detect
);
C_INCLUDE_DEV_PENCODER : BOOLEAN := true;-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : Boolean := true; -- Specifies device ISC hierarchy
--Exclusion of Device ISC requires exclusion of Priority encoder
C_IRPT_DBUS_WIDTH : INTEGER := 32
);
port(
-- Inputs From the IPIF Bus
Bus2IP_Clk_i : In std_logic; -- Master timing clock from the IPIF
Bus2IP_Data_sa : In std_logic_vector(0 to C_IRPT_DBUS_WIDTH-1);
Bus2IP_RdReq_sa : In std_logic;
Bus2IP_Reset_i : In std_logic; -- Master Reset from the IPIF reset block
Bus2IP_WrReq_sa : In std_logic;
Interrupt_RdCE : In std_logic_vector(0 to C_INTERRUPT_REG_NUM-1);
Interrupt_WrCE : In std_logic_vector(0 to C_INTERRUPT_REG_NUM-1);
IPIF_Reg_Interrupts : In std_logic_vector(0 to 1);
-- Interrupt inputs from the IPIF sources that will get registered in this design
IPIF_Lvl_Interrupts : In std_logic_vector(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Level Interrupt inputs from the IPIF sources
-- Inputs from the IP Interface
IP2Bus_IntrEvent : In std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Interrupt inputs from the IP
-- Final Device Interrupt Output
Intr2Bus_DevIntr : Out std_logic;
-- Device interrupt output to the Master Interrupt Controller
-- Status Reply Outputs to the Bus
Intr2Bus_DBus : Out std_logic_vector(0 to C_IRPT_DBUS_WIDTH-1);
Intr2Bus_WrAck : Out std_logic;
Intr2Bus_RdAck : Out std_logic;
Intr2Bus_Error : Out std_logic;
Intr2Bus_Retry : Out std_logic;
Intr2Bus_ToutSup : Out std_logic
);
end interrupt_control ;
-------------------------------------------------------------------------------
architecture implementation of interrupt_control is
--TYPES
-- no Types
-- CONSTANTS
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer range 0 to 15 := 0;
Constant DEVICE_IPR : integer range 0 to 15 := 1;
Constant DEVICE_IER : integer range 0 to 15 := 2;
Constant DEVICE_IAR : integer range 0 to 15 := 3;
Constant DEVICE_SIE : integer range 0 to 15 := 4;
Constant DEVICE_CIE : integer range 0 to 15 := 5;
Constant DEVICE_IIR : integer range 0 to 15 := 6;
Constant DEVICE_GIE : integer range 0 to 15 := 7;
Constant IP_ISR : integer range 0 to 15 := 8;
Constant IP_IPR : integer range 0 to 15 := 9;
Constant IP_IER : integer range 0 to 15 := 10;
Constant IP_IAR : integer range 0 to 15 := 11;
Constant IP_SIE : integer range 0 to 15 := 12;
Constant IP_CIE : integer range 0 to 15 := 13;
Constant IP_IIR : integer range 0 to 15 := 14;
Constant IP_GIE : integer range 0 to 15 := 15;
-- Generic to constant mapping
Constant IRPT_DBUS_WIDTH : Integer := C_IRPT_DBUS_WIDTH - 1;
Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
--INTERNAL SIGNALS
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector(IRPT_DBUS_WIDTH downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector(PRIORITY_ENC_WIDTH-1 downto 0);
--------------------------------------------------------------------------------------------------------------
-------------------------------------- start architecture logic -------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_RdAck <= irpt_rdack;
Intr2Bus_WrAck <= irpt_wrack;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to IRPT_DBUS_WIDTH loop
Intr2Bus_DBus(IRPT_DBUS_WIDTH-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk_i)
begin
If (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk_i)
begin
If (Bus2IP_Clk_i'EVENT and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1') Then -- toggle selected ISR bits from the DBus inputs
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data_sa(IRPT_DBUS_WIDTH-irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1') Then -- load input data from the DBus inputs
ip_irpt_enable_reg <= Bus2IP_Data_sa(IRPT_DBUS_WIDTH-IP_IRPT_HIGH_INDEX
to IRPT_DBUS_WIDTH);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1') Then -- load input data from the DBus inputs
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= (Bus2IP_Data_sa(IRPT_DBUS_WIDTH-i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1') Then -- load input data from the DBus inputs
ipif_irpt_enable_reg <= Bus2IP_Data_sa(IRPT_DBUS_WIDTH-IPIF_IRPT_HIGH_INDEX to IRPT_DBUS_WIDTH);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk_i)
Begin
if (Bus2IP_Clk_i'event and Bus2IP_Clk_i = '1') Then
If (Bus2IP_Reset_i = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1') Then -- load input data from the DBus inputs
ipif_glbl_irpt_enable_reg <= Bus2IP_Data_sa(0);
-- Enable bit is loaded from the DBus MSB
--Placed at bit-0 MSB by Glenn Baxter
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= conv_std_logic_vector(irpt_position, PRIORITY_ENC_WIDTH);
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= conv_std_logic_vector(NO_INTR_VALUE, PRIORITY_ENC_WIDTH);
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE)
Begin
irpt_wrack <= Interrupt_WrCE(DEVICE_ISR) or
Interrupt_WrCE(DEVICE_IER) or
Interrupt_WrCE(DEVICE_GIE) or
Interrupt_WrCE(IP_ISR) or
Interrupt_WrCE(IP_IER);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE)
Begin
irpt_wrack <= Interrupt_WrCE(DEVICE_GIE) or
Interrupt_WrCE(IP_ISR) or
Interrupt_WrCE(IP_IER);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1') Then
irpt_read_data(PRIORITY_ENC_WIDTH-1 downto 0) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_rdack <= ipif_pri_encode_present; -- set the acknowledge handshake depending on
-- priority encoder presence
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1') Then
irpt_read_data(IRPT_DBUS_WIDTH) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
irpt_read_data(i) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1') Then
irpt_read_data(IRPT_DBUS_WIDTH) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
| bsd-3-clause | 7deec24b71e48ade653ba9eceec94b15 | 0.452082 | 4.798348 | false | false | false | false |
iocoder/graduation | hardware/tlc.vhd | 1 | 9,470 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TLC is
Port (
-- The crystal:
CLK : in STD_LOGIC;
-- LED:
LED : out STD_LOGIC_VECTOR ( 7 downto 0);
-- VGA Connector
R : out STD_LOGIC_VECTOR ( 2 downto 0);
G : out STD_LOGIC_VECTOR ( 2 downto 0);
B : out STD_LOGIC_VECTOR ( 1 downto 0);
HS : out STD_LOGIC;
VS : out STD_LOGIC;
-- Memory Bus:
ADDR : out STD_LOGIC_VECTOR (23 downto 0);
DATA : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC := '1';
WE : out STD_LOGIC := '1';
MT_ADV : out STD_LOGIC := '0';
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1';
MT_LB : out STD_LOGIC := '1';
MT_CE : out STD_LOGIC := '1';
MT_CRE : out STD_LOGIC := '0';
MT_WAIT : in STD_LOGIC := '0';
ST_STS : in STD_LOGIC := '0';
RP : out STD_LOGIC := '1';
ST_CE : out STD_LOGIC := '1';
-- PS/2 port:
PS2CLK : in STD_LOGIC := '0';
PS2DATA : in STD_LOGIC := '0'
);
end TLC;
architecture Structural of TLC is
component cpu is
Port (
CLK : in STD_LOGIC;
IRQ : in STD_LOGIC;
NMI : in STD_LOGIC;
IAK : out STD_LOGIC;
NAK : out STD_LOGIC;
-- system bus
MEME : out STD_LOGIC;
RW : out STD_LOGIC;
ADDR : out STD_LOGIC_VECTOR (31 downto 0);
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : out STD_LOGIC_VECTOR ( 2 downto 0);
RDY : in STD_LOGIC
);
end component;
component memif is
Port (
CLK : in STD_LOGIC;
-- Interface
RAM_CS : in STD_LOGIC; -- RAM chip enable
ROM_CS : in STD_LOGIC; -- ROM chip enable
RW : in STD_LOGIC; -- 0: read, 1: write
A : in STD_LOGIC_VECTOR (23 downto 0);
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC;
-- External Memory Bus:
ADDR : out STD_LOGIC_VECTOR (23 downto 0);
DATA : inout STD_LOGIC_VECTOR (15 downto 0);
OE : out STD_LOGIC := '1'; -- active low
WE : out STD_LOGIC := '1'; -- active low
MT_ADV : out STD_LOGIC := '0'; -- active low
MT_CLK : out STD_LOGIC := '0';
MT_UB : out STD_LOGIC := '1'; -- active low
MT_LB : out STD_LOGIC := '1'; -- active low
MT_CE : out STD_LOGIC := '1'; -- active low
MT_CRE : out STD_LOGIC := '0'; -- active high
MT_WAIT : in STD_LOGIC;
ST_STS : in STD_LOGIC;
RP : out STD_LOGIC := '1'; -- active low
ST_CE : out STD_LOGIC := '1' -- active low
);
end component;
component vga is
Port ( CLK : in STD_LOGIC; -- 50MHz clock input
-- System Bus
CS : in STD_LOGIC;
RW : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (13 downto 0);
Din : in STD_LOGIC_VECTOR (15 downto 0);
Dout : out STD_LOGIC_VECTOR (15 downto 0);
RDY : out STD_LOGIC := '0';
INT : out STD_LOGIC := '0';
IAK : in STD_LOGIC;
-- VGA Port
R : out STD_LOGIC_VECTOR (2 downto 0);
G : out STD_LOGIC_VECTOR (2 downto 0);
B : out STD_LOGIC_VECTOR (1 downto 0);
HS : out STD_LOGIC;
VS : out STD_LOGIC);
end component;
component kbdctl is
Port (
-- Crystal:
CLK : in STD_LOGIC;
-- Inputs from PS/2 keyboard:
PS2CLK : in STD_LOGIC;
PS2DATA : in STD_LOGIC;
-- Output:
LED : out STD_LOGIC_VECTOR (7 downto 0);
-- System bus interface:
EN : in STD_LOGIC;
RW : in STD_LOGIC;
DATA : out STD_LOGIC_VECTOR (7 downto 0);
RDY : out STD_LOGIC;
-- Interrupt Logic:
INT : out STD_LOGIC;
IAK : in STD_LOGIC
);
end component;
component pit is
Port (
CLK : in STD_LOGIC;
IRQ : out STD_LOGIC;
IAK : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC; -- 0: read, 1: write
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC := '1');
end component;
component pic is
Port (
CLK : in STD_LOGIC;
IRQ_in : in STD_LOGIC_VECTOR (7 downto 0);
IAK_out : out STD_LOGIC_VECTOR (7 downto 0);
IRQ_out : out STD_LOGIC := '0';
IAK_in : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC; -- 0: read, 1: write
Din : in STD_LOGIC_VECTOR (31 downto 0);
Dout : out STD_LOGIC_VECTOR (31 downto 0);
DTYPE : in STD_LOGIC_VECTOR ( 2 downto 0);
RDY : out STD_LOGIC := '1'
);
end component;
-- CPU signals
signal IRQ : STD_LOGIC := '0';
signal NMI : STD_LOGIC := '0';
signal IAK : STD_LOGIC := '0';
signal NAK : STD_LOGIC := '0';
-- System bus:
signal MEME : STD_LOGIC := '0';
signal RW : STD_LOGIC := '0';
signal Address : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataCPUToMem : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataMemToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataRAMToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataVGAToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataKBDToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataPITToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DataPICToCPU : STD_LOGIC_VECTOR (31 downto 0) := x"00000000";
signal DTYPE : STD_LOGIC_VECTOR ( 2 downto 0) := "000";
signal RAM_CS : STD_LOGIC := '0';
signal ROM_CS : STD_LOGIC := '0';
signal VGA_CS : STD_LOGIC := '0';
signal KBD_CS : STD_LOGIC := '0';
signal PIT_CS : STD_LOGIC := '0';
signal PIC_CS : STD_LOGIC := '0';
signal MEM_RDY : STD_LOGIC := '0';
signal VGA_RDY : STD_LOGIC := '0';
signal KBD_RDY : STD_LOGIC := '0';
signal PIT_RDY : STD_LOGIC := '0';
signal PIC_RDY : STD_LOGIC := '0';
signal RDY : STD_LOGIC := '0';
signal IRQ_to_PIC : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal IAK_from_PIC : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
begin
------------- memory map -------------
-- 0x00000000 - 0x00FFFFFF : RAM
-- 0x1E000000 - 0x1E003FFF : VGA
-- 0x1E800000 - 0x1E800FFF : KBD
-- 0x1E801000 - 0x1E801FFF : PIT
-- 0x1E802000 - 0x1E802FFF : PIC
-- 0x1EC02000 - 0x1EC02007 : PPU
-- 0x1F000000 - 0x1FFFFFFF : ROM
-- memory decoding
RAM_CS <= MEME when Address(31 downto 24) = x"00" else '0';
ROM_CS <= MEME when Address(31 downto 24) = x"1F" else '0';
VGA_CS <= MEME when Address(31 downto 14) = x"1E00"&"00" or
Address(31 downto 12) = x"1EC02" else '0';
KBD_CS <= MEME when Address(31 downto 12) = x"1E800" else '0';
PIT_CS <= MEME when Address(31 downto 12) = x"1E801" else '0';
PIC_CS <= MEME when Address(31 downto 12) = x"1E802" else '0';
DataMemToCPU <= DataRAMToCPU when ROM_CS = '1' or RAM_CS = '1' else
DataVGAToCPU when VGA_CS = '1' else
DataKBDToCPU when KBD_CS = '1' else
DataPITToCPU when PIT_CS = '1' else
DataPICToCPU when PIC_CS = '1' else
x"00000000";
RDY <= MEM_RDY when ROM_CS = '1' or RAM_CS = '1' else
VGA_RDY when VGA_CS = '1' else
KBD_RDY when KBD_CS = '1' else
PIT_RDY when PIT_CS = '1' else
PIC_RDY when PIC_CS = '1' else
'0';
-- subblocks
U1: cpu port map (CLK, IRQ, NMI, IAK, NAK,
MEME, RW, Address, DataMemToCPU, DataCPUToMem, DTYPE, RDY);
U2: memif port map (CLK,
RAM_CS, ROM_CS, RW, Address(23 downto 0),
DataCPUToMem(31 downto 0), DataRAMToCPU(31 downto 0),
DTYPE, MEM_RDY, ADDR, DATA, OE, WE,
MT_ADV, MT_CLK, MT_UB, MT_LB, MT_CE, MT_CRE, MT_WAIT,
ST_STS, RP, ST_CE);
U3: vga port map (CLK, VGA_CS, RW,
Address(13 downto 0), DataCPUToMem(15 downto 0),
DataVGAToCPU(15 downto 0), VGA_RDY,
IRQ_to_PIC(3), IAK_from_PIC(3),
R, G, B, HS, VS);
U4: kbdctl port map (CLK, PS2CLK, PS2DATA, LED,
KBD_CS, RW, DataKBDToCPU(7 downto 0), KBD_RDY,
IRQ_to_PIC(1), IAK_from_PIC(1));
U5: pit port map (CLK, IRQ_to_PIC(0), IAK_from_PIC(0),
PIT_CS, RW, DataCPUToMem, DataPITToCPU, DTYPE, PIT_RDY);
U6: pic port map (CLK, IRQ_to_PIC, IAK_from_PIC, IRQ, IAK,
PIC_CS, RW, DataCPUToMem, DataPICToCPU, DTYPE, PIC_RDY);
end Structural;
| gpl-3.0 | 3eb95326780ffcd3d3619711777d8b65 | 0.503485 | 3.230979 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/srl_fifo.vhd | 2 | 11,844 | -------------------------------------------------------------------------------
-- $Id: srl_fifo.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2001-05-11 First Version
-- KC 2001-06-20 Added Addr as an output port, for use as an occupancy
-- value
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
buffer_Full <= '1' when (addr_i = "1111") else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
Addr <= addr_i;
end process;
end architecture IMP;
| bsd-3-clause | 8a634b0fb658a8c0b480c36cc511ddc1 | 0.43254 | 4.357616 | false | false | false | false |
QuickJack/logi-hard | hdl/utils/dp_fifo.vhd | 2 | 4,679 | ----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 15:37:36 06/18/2012
-- Design Name:
-- Module Name: dp_fifo - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_primitive_pack.all ;
use work.logi_utils_pack.all ;
--! dual port ram based fifo for fast logic to logic communication
entity dp_fifo is
generic(N : natural := 128 ; --! depth of the fifo
W : positive := 16; --! width of the fifo
SYNC_WR : boolean := false;
SYNC_RD : boolean := false
);
port(
clk, resetn, sraz : in std_logic; --! system clock, asynchronous and synchronous reset
wr, rd : in std_logic; --! fifo write and read signal
empty, full : out std_logic ; --! fifo stat signals
data_out : out std_logic_vector((W - 1) downto 0 ); --! data output of fifo
data_in : in std_logic_vector((W - 1) downto 0 ); --! data input of fifo
nb_available : out unsigned(nbit(N) downto 0 ) --! number of available tokens in fifo
);
end dp_fifo;
architecture Behavioral of dp_fifo is
constant std_fifo_size : std_logic_vector(nbit(N) downto 0 ) := std_logic_vector(to_unsigned(N, nbit(N) + 1));
signal rd_addr, rd_addr_adv, wr_addr: std_logic_vector((nbit(N) - 1) downto 0) ;
signal nb_free_t, nb_available_t : unsigned(nbit(N) downto 0 ) ;
signal slv_nb_available_t : std_logic_vector(nbit(N) downto 0 ) ;
signal fifo_out, fifo_in : std_logic_vector((W - 1 ) downto 0) ;
signal rd_old, wr_old, wr_data, rd_data, one_turn, latch_data : std_logic ;
signal rd_rising_edge, wr_rising_edge : std_logic ;
signal rd_falling_edge, wr_falling_edge : std_logic ;
signal en_available_counter, up_downn_available_counter : std_logic ;
signal en_free_counter, up_downn_free_counter, counter_load : std_logic ;
signal fifo_wr, fifo_rd : std_logic ;
begin
dp_ram0 : dpram_NxN
generic map(SIZE => N , NBIT => W, ADDR_WIDTH => nbit(N))
port map(
clk => clk ,
we => wr_data ,
di => data_in ,
a => wr_addr,
dpra => rd_addr_adv ,
dpo => fifo_out
);
data_out <= fifo_out ;
gen_async_rd : if NOT SYNC_RD generate
process(resetn, clk)
begin
if resetn = '0' then
rd_old <= '0' ;
elsif clk'event and clk = '1' then
rd_old <= rd ;
end if ;
end process ;
rd_falling_edge <= ((NOT rd) AND rd_old);
fifo_rd <= rd_falling_edge ;
rd_addr_adv <= rd_addr ;
end generate ;
gen_sync_rd : if SYNC_RD generate
fifo_rd <= rd;
rd_addr_adv <= (rd_addr + 1) when fifo_rd = '1' else
rd_addr ;
end generate ;
gen_async_wr : if NOT SYNC_WR generate
process(resetn, clk)
begin
if resetn = '0' then
wr_old <= '0' ;
elsif clk'event and clk = '1' then
wr_old <= wr ;
end if ;
end process ;
wr_falling_edge <= ((NOT wr) AND wr_old) ;
fifo_wr <= wr_falling_edge ;
end generate ;
gen_sync_wr : if SYNC_WR generate
fifo_wr <= wr ;
end generate ;
--rd process
process(clk, resetn)
begin
if resetn = '0' then
rd_addr <= (others => '0') ;
elsif clk'event and clk = '1' then
if sraz = '1' then
rd_addr <= (others => '0');
elsif fifo_rd = '1' and nb_available_t /= 0 then
rd_addr <= rd_addr + 1;
end if ;
end if ;
end process ;
-- wr process
process(clk, resetn)
begin
if resetn = '0' then
wr_addr <= (others => '0') ;
elsif clk'event and clk = '1' then
if sraz = '1' then
wr_addr <= (others => '0');
elsif fifo_wr = '1' and nb_available_t /= N then
wr_addr <= wr_addr + 1;
end if ;
end if ;
end process ;
-- nb available process
process(clk, resetn)
begin
if resetn = '0' then
nb_available_t <= (others => '0') ;
elsif clk'event and clk = '1' then
if sraz = '1' then
nb_available_t <= (others => '0') ;
elsif fifo_wr = '1' and fifo_rd = '0' and nb_available_t /= N then
nb_available_t <= nb_available_t + 1 ;
elsif fifo_rd = '1' and fifo_wr = '0' and nb_available_t /= 0 then
nb_available_t <= nb_available_t - 1 ;
end if ;
end if ;
end process ;
nb_available <= nb_available_t ;
empty <= '1' when nb_available_t = 0 else
'1' when nb_available_t = 1 and fifo_rd = '1' else -- must check if its useful ...
'0' ;
full <= '1' when nb_available_t = N else
'1' when nb_available_t = N - 1 and fifo_wr = '1' else -- must check if its useful ...
'0' ;
wr_data <= fifo_wr ;
end Behavioral;
| lgpl-3.0 | a0a9ca62bc1b5ff8ab101800300a2269 | 0.606112 | 2.875845 | false | false | false | false |
EnricoGiordano1992/resim-simulating-partial-reconfiguration | examples/state_migration/edk/pcores/ipif_v1_00_a/hdl/vhdl/plbv46_master_burst_wrapper_128.vhd | 3 | 19,674 | ------------------------------------------------------------------------------
-- plbv46_master_burst_wrapper.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_master_burst_v1_01_a;
use plbv46_master_burst_v1_01_a.plbv46_master_burst;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MPLB_AWIDTH -- PLBv46 master: address bus width
-- C_MPLB_DWIDTH -- PLBv46 master: data bus width
-- C_MPLB_NATIVE_DWIDTH -- PLBv46 master: internal native data width
-- C_MPLB_P2P -- PLBv46 master: point to point interconnect scheme
-- C_MPLB_SMALLEST_SLAVE -- PLBv46 master: width of the smallest slave
-- C_MPLB_CLK_PERIOD_PS -- PLBv46 master: bus clock in picoseconds
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- MPLB_Clk -- PLB main bus Clock
-- MPLB_Rst -- PLB main bus Reset
-- MD_error -- Master detected error status output
-- M_request -- Master request
-- M_priority -- Master request priority
-- M_busLock -- Master buslock
-- M_RNW -- Master read/nor write
-- M_BE -- Master byte enables
-- M_MSize -- Master data bus size
-- M_size -- Master transfer size
-- M_type -- Master transfer type
-- M_TAttribute -- Master transfer attribute
-- M_lockErr -- Master lock error indicator
-- M_abort -- Master abort bus request indicator
-- M_UABus -- Master upper address bus
-- M_ABus -- Master address bus
-- M_wrDBus -- Master write data bus
-- M_wrBurst -- Master burst write transfer indicator
-- M_rdBurst -- Master burst read transfer indicator
-- PLB_MAddrAck -- PLB reply to master for address acknowledge
-- PLB_MSSize -- PLB reply to master for slave data bus size
-- PLB_MRearbitrate -- PLB reply to master for bus re-arbitrate indicator
-- PLB_MTimeout -- PLB reply to master for bus time out indicator
-- PLB_MBusy -- PLB reply to master for slave busy indicator
-- PLB_MRdErr -- PLB reply to master for slave read error indicator
-- PLB_MWrErr -- PLB reply to master for slave write error indicator
-- PLB_MIRQ -- PLB reply to master for slave interrupt indicator
-- PLB_MRdDBus -- PLB reply to master for read data bus
-- PLB_MRdWdAddr -- PLB reply to master for read word address
-- PLB_MRdDAck -- PLB reply to master for read data acknowledge
-- PLB_MRdBTerm -- PLB reply to master for terminate read burst indicator
-- PLB_MWrDAck -- PLB reply to master for write data acknowledge
-- PLB_MWrBTerm -- PLB reply to master for terminate write burst indicator
------------------------------------------------------------------------------
entity plbv46_master_burst_wrapper is
generic
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
C_MPLB_AWIDTH : integer := 32;
C_MPLB_DWIDTH : integer := 128;
C_MPLB_NATIVE_DWIDTH : integer := 128;
C_MPLB_SMALLEST_SLAVE : integer := 32;
C_INHIBIT_CC_BLE_INCLUSION : integer := 0;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- ADD USER GENERICS BELOW THIS LINE ---------------
-- ADD USER GENERICS ABOVE THIS LINE ---------------
);
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
MPLB_Clk : in std_logic ;
MPLB_Rst : in std_logic ;
MD_error : out std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8) - 1);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_abort : out std_logic;
M_lockErr : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_UABus : out std_logic_vector(0 to 31);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1);
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to C_MPLB_DWIDTH-1);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- ADD USER PORTS BELOW THIS LINE ------------------
Bus2IP_Mst_Clk : out std_logic;
Bus2IP_Mst_Reset : out std_logic;
IP2Bus_MstRd_Req : in std_logic;
IP2Bus_MstWr_Req : in std_logic;
IP2Bus_Mst_Addr : in std_logic_vector(0 to C_MPLB_AWIDTH-1);
IP2Bus_Mst_Length : in std_logic_vector(0 to 11);
IP2Bus_Mst_BE : in std_logic_vector(0 to 128/8 -1);
IP2Bus_Mst_Type : in std_logic;
IP2Bus_Mst_Lock : in std_logic;
IP2Bus_Mst_Reset : in std_logic;
Bus2IP_Mst_CmdAck : out std_logic;
Bus2IP_Mst_Cmplt : out std_logic;
Bus2IP_Mst_Error : out std_logic;
Bus2IP_Mst_Rearbitrate : out std_logic;
Bus2IP_Mst_Cmd_Timeout : out std_logic;
Bus2IP_MstRd_d : out std_logic_vector(0 to 128-1);
Bus2IP_MstRd_rem : out std_logic_vector(0 to 128/8-1);
Bus2IP_MstRd_sof_n : out std_logic;
Bus2IP_MstRd_eof_n : out std_logic;
Bus2IP_MstRd_src_rdy_n : out std_logic;
Bus2IP_MstRd_src_dsc_n : out std_logic;
IP2Bus_MstRd_dst_rdy_n : in std_logic;
IP2Bus_MstRd_dst_dsc_n : in std_logic;
IP2Bus_MstWr_d : in std_logic_vector(0 to 128-1);
IP2Bus_MstWr_rem : in std_logic_vector(0 to 128/8-1);
IP2Bus_MstWr_sof_n : in std_logic;
IP2Bus_MstWr_eof_n : in std_logic;
IP2Bus_MstWr_src_rdy_n : in std_logic;
IP2Bus_MstWr_src_dsc_n : in std_logic;
Bus2IP_MstWr_dst_rdy_n : out std_logic;
Bus2IP_MstWr_dst_dsc_n : out std_logic
-- ADD USER PORTS ABOVE THIS LINE ------------------
);
end entity plbv46_master_burst_wrapper;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of plbv46_master_burst_wrapper is
constant PADDING_ZEROS : std_logic_vector(0 to 127) := (others => '0');
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
-- NOT USED: signal ipif_IP2Bus_MstRd_Req : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_Req : std_logic;
-- NOT USED: signal ipif_IP2Bus_Mst_Addr : std_logic_vector(0 to C_MPLB_AWIDTH-1);
-- NOT USED: signal ipif_IP2Bus_Mst_Length : std_logic_vector(0 to 11);
-- NOT USED: signal ipif_IP2Bus_Mst_Type : std_logic;
-- NOT USED: signal ipif_IP2Bus_Mst_Lock : std_logic;
-- NOT USED: signal ipif_IP2Bus_Mst_Reset : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_CmdAck : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Cmplt : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Error : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Rearbitrate : std_logic;
-- NOT USED: signal ipif_Bus2IP_Mst_Cmd_Timeout : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_sof_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_eof_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_src_rdy_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstRd_src_dsc_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstRd_dst_rdy_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstRd_dst_dsc_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_sof_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_eof_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_src_rdy_n : std_logic;
-- NOT USED: signal ipif_IP2Bus_MstWr_src_dsc_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstWr_dst_rdy_n : std_logic;
-- NOT USED: signal ipif_Bus2IP_MstWr_dst_dsc_n : std_logic;
--
-- BITWIDTH ADAPTION:
--
-- Bitwidth of plbv46_master_burst is variable depending on the C_SPLB_DWIDTH/C_SPLB_NATIVE_DWIDTH
-- Bitwidth of plbv46_master_burst_wrapper_128 is tuned for 128bit systemc modules
--
-- The following signals may have different bitwidth between
-- plbv46_master_burst and plbv46_master_burst_wrapper_128. And MSBs of them may not be connected
--
signal ipif_IP2Bus_Mst_BE : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_Bus2IP_MstRd_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_Bus2IP_MstRd_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
signal ipif_IP2Bus_MstWr_d : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
signal ipif_IP2Bus_MstWr_rem : std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH/8-1);
begin
------------------------------------------
-- instantiate plbv46_master_burst
------------------------------------------
PLBV46_MASTER_BURST_I : entity plbv46_master_burst_v1_01_a.plbv46_master_burst
generic map
(
C_MPLB_AWIDTH => C_MPLB_AWIDTH,
C_MPLB_DWIDTH => C_MPLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MPLB_NATIVE_DWIDTH,
C_MPLB_SMALLEST_SLAVE => C_MPLB_SMALLEST_SLAVE,
C_INHIBIT_CC_BLE_INCLUSION => C_INHIBIT_CC_BLE_INCLUSION,
C_FAMILY => C_FAMILY
)
port map
(
MPLB_Clk => MPLB_Clk,
MPLB_Rst => MPLB_Rst,
MD_error => MD_error,
M_request => M_request,
M_priority => M_priority,
M_busLock => M_busLock,
M_RNW => M_RNW,
M_BE => M_BE,
M_MSize => M_MSize,
M_size => M_size,
M_type => M_type,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_abort => M_abort,
M_UABus => M_UABus,
M_ABus => M_ABus,
M_wrDBus => M_wrDBus,
M_wrBurst => M_wrBurst,
M_rdBurst => M_rdBurst,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MSSize => PLB_MSSize,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MIRQ => PLB_MIRQ,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MWrBTerm => PLB_MWrBTerm,
IP2Bus_MstRd_Req => IP2Bus_MstRd_Req,
IP2Bus_MstWr_Req => IP2Bus_MstWr_Req,
IP2Bus_Mst_Addr => IP2Bus_Mst_Addr,
IP2Bus_Mst_Length => IP2Bus_Mst_Length,
IP2Bus_Mst_BE => ipif_IP2Bus_Mst_BE, ---- FOR BITWIDTH ADAPTION
IP2Bus_Mst_Type => IP2Bus_Mst_Type,
IP2Bus_Mst_Lock => IP2Bus_Mst_Lock,
IP2Bus_Mst_Reset => IP2Bus_Mst_Reset,
Bus2IP_Mst_CmdAck => Bus2IP_Mst_CmdAck,
Bus2IP_Mst_Cmplt => Bus2IP_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2IP_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2IP_Mst_Rearbitrate,
Bus2IP_Mst_Cmd_Timeout => Bus2IP_Mst_Cmd_Timeout,
Bus2IP_MstRd_d => ipif_Bus2IP_MstRd_d, ---- FOR BITWIDTH ADAPTION
Bus2IP_MstRd_rem => ipif_Bus2IP_MstRd_rem, ---- FOR BITWIDTH ADAPTION
Bus2IP_MstRd_sof_n => Bus2IP_MstRd_sof_n,
Bus2IP_MstRd_eof_n => Bus2IP_MstRd_eof_n,
Bus2IP_MstRd_src_rdy_n => Bus2IP_MstRd_src_rdy_n,
Bus2IP_MstRd_src_dsc_n => Bus2IP_MstRd_src_dsc_n,
IP2Bus_MstRd_dst_rdy_n => IP2Bus_MstRd_dst_rdy_n,
IP2Bus_MstRd_dst_dsc_n => IP2Bus_MstRd_dst_dsc_n,
IP2Bus_MstWr_d => ipif_IP2Bus_MstWr_d, ---- FOR BITWIDTH ADAPTION
IP2Bus_MstWr_rem => ipif_IP2Bus_MstWr_rem, ---- FOR BITWIDTH ADAPTION
IP2Bus_MstWr_sof_n => IP2Bus_MstWr_sof_n,
IP2Bus_MstWr_eof_n => IP2Bus_MstWr_eof_n,
IP2Bus_MstWr_src_rdy_n => IP2Bus_MstWr_src_rdy_n,
IP2Bus_MstWr_src_dsc_n => IP2Bus_MstWr_src_dsc_n,
Bus2IP_MstWr_dst_rdy_n => Bus2IP_MstWr_dst_rdy_n,
Bus2IP_MstWr_dst_dsc_n => Bus2IP_MstWr_dst_dsc_n
);
ipif_IP2Bus_Mst_BE <= IP2Bus_Mst_BE(128/8-C_MPLB_NATIVE_DWIDTH/8 to 128/8-1);
ipif_IP2Bus_MstWr_d <= IP2Bus_MstWr_d(128-C_MPLB_NATIVE_DWIDTH to 128-1);
ipif_IP2Bus_MstWr_rem <= IP2Bus_MstWr_rem(128/8-C_MPLB_NATIVE_DWIDTH/8 to 128/8-1);
Bus2IP_MstRd_d <= PADDING_ZEROS(C_MPLB_NATIVE_DWIDTH to 128-1) & ipif_Bus2IP_MstRd_d;
Bus2IP_MstRd_rem <= PADDING_ZEROS(C_MPLB_NATIVE_DWIDTH/8 to 16-1) & ipif_Bus2IP_MstRd_rem;
Bus2IP_Mst_Clk <= MPLB_Clk;
Bus2IP_Mst_Reset <= MPLB_Rst;
end IMP;
| bsd-3-clause | e7015d9657969f6c353fa76c44d06d13 | 0.493443 | 3.956163 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_lite_ipif_v1_01_a/hdl/vhdl/slave_attachment.vhd | 2 | 21,665 | -------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.proc_common_pkg.max2;
use proc_common_v3_00_a.ipif_pkg.all;
use proc_common_v3_00_a.family_support.all;
use proc_common_v3_00_a.counter_f;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity axi_lite_ipif_v1_01_a.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
| bsd-3-clause | a729eee70c16f43a38f1f0d2b0a95996 | 0.498454 | 3.936228 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/z091_01_wb_slave.vhd | 1 | 62,923 | --------------------------------------------------------------------------------
-- Title : new Wishbone Slave
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : wbs_new.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2015-03-10
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- Wishbone slave module to receive read and write requests from Wishbone
-- master and to return read data via completion
-- Due to different FIFO data port widths (32bit for WB, 64bit for RX & TX)
-- storing or deleting dummy packets is necessary on the WB side.
-- 1. RX storing 64bit wide -> delete 1 dummy packet on WB side
-- 2. store 1 dummy packet on WB side so that TX can read 64bit (otherwise
-- fifo_empty will not indicate 32bit contents to TX side)
-- CPLD := completion with data
-- CDC := clock domain crossing
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- * wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.src_utils_pkg.all;
entity z091_01_wb_slave is
generic(
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000"; -- 32DW = 128Byte
SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111100"; -- = 1020 DW, one place spare for put_stuffing
RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111" -- = 1015 DW
);
port(
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- Rx Module
rx_fifo_c_empty : in std_logic;
rx_fifo_c_out : in std_logic_vector(31 downto 0);
rx_fifo_c_rd_enable : out std_logic;
-- Tx Module
tx_fifo_wr_head_full : in std_logic;
tx_fifo_w_data_full : in std_logic;
tx_fifo_w_data_usedw : in std_logic_vector(9 downto 0);
tx_fifo_wr_head_usedw : in std_logic_vector(4 downto 0);
tx_fifo_wr_head_clr : out std_logic;
tx_fifo_wr_head_enable : out std_logic;
tx_fifo_wr_head_in : out std_logic_vector(31 downto 0);
tx_fifo_w_data_clr : out std_logic;
tx_fifo_w_data_enable : out std_logic;
tx_fifo_w_data_in : out std_logic_vector(31 downto 0);
max_read : in std_logic_vector(2 downto 0);
-- error
error_ecrc_err : in std_logic;
error_timeout : in std_logic
);
end entity z091_01_wb_slave;
architecture z091_01_wb_slave_arch of z091_01_wb_slave is
-- FSM state encoding ---------------------------------------------------------
type fsm_state is (
WAIT_ON_FIFO, IDLE, HEADER_TO_FIFO, WR_TRANS, RD_TRANS, GET_RD_HEADER,
DROP_DATA
);
signal state : fsm_state;
-- internal signals -----------------------------------------------------------
signal tx_fifo_wr_head_en_int : std_logic; -- internal enable
signal cnt_len : std_logic_vector(9 downto 0); -- packet counter
signal cpl_return_len : std_logic_vector(9 downto 0); -- count amount of CPL data
signal put_header : std_logic; -- valid signal for put_h0_h1
signal put_h0_h1 : std_logic; -- qualify which kind of header to store
-- 0: put h0, 1: put h1
signal get_header : std_logic; -- get header info from CPLD
signal wbs_adr_int : std_logic_vector(31 downto 0); -- store wbs_adr
signal first_DW_int : std_logic_vector(3 downto 0); -- store first_DW byte enable
signal last_DW_int : std_logic_vector(3 downto 0); -- store last_DW byte enable
signal length_int : std_logic_vector(9 downto 0); -- store length returned with CPLD
signal max_read_len : std_logic_vector(9 downto 0); -- max read length for RD_TRANS
signal wr_req : std_logic; -- active while write request
signal rd_req : std_logic; -- active while read request
signal wr_burst : std_logic; -- active if burst write
signal rd_burst : std_logic; -- active if burst read
signal max_wr_len_reached : std_logic; -- break if cnt_len will wrap thus 1024DW were written to FIFO
signal multi_cpl : std_logic; -- asserted if read returned in multiple cycles
signal rd_trans_done : std_logic; -- store if WB transaction is finished
signal len_is_1024DW : std_logic; -- if asserted length is 1024
-- 1024DW is encoded as len=0 thus
-- needed to distinguish from reset value
signal compare_to_4k_len : std_logic; -- enable 4k honoring
signal to_4k_len : std_logic_vector(9 downto 0); -- DW counter which holds amount of DWs until next 4k boundary
signal requested_len : std_logic_vector(9 downto 0); -- save requested length for reads
signal act_read_size : std_logic_vector(9 downto 0); -- actual read size composed in IDLE state
-- registered signals
signal max_read_q : std_logic_vector(2 downto 0); -- used for CDC synchronization
signal max_read_qq : std_logic_vector(2 downto 0); -- used for CDC synchronization
signal put_header_q : std_logic;
signal get_header_q : std_logic; -- define 4 stages of header aquisition
signal get_header_qq : std_logic;
signal get_header_qqq : std_logic;
signal first_rd_cycle : std_logic; -- first cycle in RD_TRANS
signal wbs_tga_q : std_logic; -- registered copy of wbs_tga
-------------------------------------------------------------------------------
begin
-- +----------------------------------------------------------------------------
-- | concurrent section
-- +----------------------------------------------------------------------------
----------------------------------------
-- assign static connections for ports
----------------------------------------
wbs_err <= error_ecrc_err or error_timeout;
tx_fifo_w_data_in <= wbs_dat_i;
wbs_dat_o <= rx_fifo_c_out;
-----------------------
-- decode max_read_qq
-----------------------
with max_read_qq select
max_read_len <= "0001000000" when "001",
"0010000000" when "010",
"0100000000" when "011",
"1000000000" when "100",
"0000000000" when "101",
"0000100000" when others;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
--------------------------------------------
-- register different signals using wb_clk
--------------------------------------------
reg_proc : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
tx_fifo_wr_head_enable <= '0';
max_read_q <= (others => '0');
max_read_qq <= (others => '0');
put_header_q <= '0';
get_header_q <= '0';
get_header_qq <= '0';
get_header_qqq <= '0';
first_rd_cycle <= '0';
wbs_tga_q <= '0';
elsif wb_clk'event and wb_clk = '1' then
tx_fifo_wr_head_enable <= tx_fifo_wr_head_en_int;
max_read_q <= max_read;
max_read_qq <= max_read_q;
put_header_q <= put_header;
get_header_q <= get_header;
get_header_qq <= get_header_q;
get_header_qqq <= get_header_qq;
first_rd_cycle <= get_header_qqq;
if state = HEADER_TO_FIFO then
wbs_tga_q <= wbs_tga;
end if;
end if;
end process reg_proc;
---------------------------
-- manage FSM transitions
---------------------------
fsm_transout : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
-- ports
tx_fifo_wr_head_clr <= '1';
tx_fifo_w_data_clr <= '1';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
-- internal signals
wbs_adr_int <= (others => '0');
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
state <= IDLE;
elsif wb_clk'event and wb_clk = '1' then
case state is
when IDLE =>
-- ports
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
-- internal signals
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
------------------------------
-- wait until active request
------------------------------
if wbs_cyc = '1' and wbs_stb = '1' then
wbs_adr_int <= wbs_adr;
first_DW_int <= wbs_sel;
----------------------------------------------------------------------------------------
-- calculate length to 4k boundary:
-- wbs_adr[12] denotes 4k boundary which is 0x1000
-- maximum transfer length is 1024DW = 1024 *4B = 4096B := 0x1000
-- => if wbs_adr[11:0] = 0b000 then all lenghts are ok
-- otherwise calculate length offset to next 4k boundary, use to_4k_len as DW counter
-- subtracting wbs_adr from the next 4k boundary results in a byte value
-- -> use 1024 instead of 4096 to calculated DW counter instead of byte counter
-- ! manage first_DW_be and last_DW_be accordingly
----------------------------------------------------------------------------------------
if wbs_adr(11 downto 0) = x"000" then
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
else
compare_to_4k_len <= '1';
to_4k_len <= std_logic_vector(to_unsigned((1024 - to_integer(unsigned(wbs_adr(11 downto 2)))), 10));
end if;
if wbs_we = '0' and wbs_cti = "010" then
rd_burst <= '1';
else
rd_burst <= '0';
end if;
-----------------------------------------------------------------------------------
-- if write request and TX data FIFO full or
-- read request and TX header FIFO full then
-- wait until FIFO is empty again
-- for both read and write requests the header FIFO must have at least 2 DW space
-- (here 3 for easier checking)
-----------------------------------------------------------------------------------
if (wbs_we = '1' and (tx_fifo_w_data_full = '1' or tx_fifo_w_data_usedw > RESUME_FIFO_ACCESS or
tx_fifo_wr_head_full = '1' or tx_fifo_wr_head_usedw(4 downto 2) = "111")) or
(wbs_we = '0' and (tx_fifo_wr_head_full = '1' or tx_fifo_wr_head_usedw(4 downto 2) = "111")) then
state <= WAIT_ON_FIFO;
elsif wbs_we = '1' and tx_fifo_w_data_full = '0' then
tx_fifo_w_data_enable <= '1';
wbs_ack <= '1';
wr_req <= '1';
cnt_len <= ONE_10B;
state <= WR_TRANS;
elsif wbs_we = '0' and tx_fifo_wr_head_full = '0' then
tx_fifo_wr_head_en_int <= '1';
rd_req <= '1';
put_header <= '1';
state <= HEADER_TO_FIFO;
end if;
else
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
state <= IDLE;
end if;
when HEADER_TO_FIFO =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '1';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
wr_req <= wr_req;
rd_req <= rd_req;
wr_burst <= '0';
put_header <= '1';
put_h0_h1 <= '1';
multi_cpl <= '0'; -- new read startet thus reset
first_DW_int <= first_DW_int;
last_DW_int <= last_DW_int;
cpl_return_len <= (others => '0'); -- requesting new packet thus clear cpl_return_len
rd_trans_done <= '0';
len_is_1024DW <= '0';
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
-- NOTE: this setting is not always true as this state can now be entered for wr_burst as
-- well but it has no influence on write bursts so it will remain unchanged
if wbs_cti = "010" then
rd_burst <= '1';
else
rd_burst <= '0';
end if;
----------------------------------------------------------
-- update address information for reads because multiple
-- read cycles without transition to IDLE are possible
----------------------------------------------------------
if put_header = '1' and put_header_q = '0' and rd_req = '1' then
wbs_adr_int <= wbs_adr;
else
wbs_adr_int <= wbs_adr_int;
end if;
------------------------------------------------------------------------------------
-- don't clear cnt_len for writes because this info must be stored to header first
------------------------------------------------------------------------------------
if wr_req = '1' then
cnt_len <= cnt_len;
else
-- cnt_len is not used for RD headers so it may be cleared here
cnt_len <= (others => '0');
end if;
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif put_h0_h1 = '1' then
tx_fifo_wr_head_en_int <= '0';
put_header <= '0';
put_h0_h1 <= '0';
----------------------------------------------------------------
-- 1. if max write length was reached split packet by writing
-- header and start new PCIe packet thus return to WR_TRANS
-- 2. for reads write request header first then go to RD_TRANS
-- for multiple returned CPLDs this state should not
-- be entered
-- 3. if neither write nor read request then FIFO was full
-- during start of WB transaction thus return to IDLE
----------------------------------------------------------------
if rd_req = '1' then
max_wr_len_reached <= '0';
state <= GET_RD_HEADER;
elsif wr_req = '1' and max_wr_len_reached = '1' then
max_wr_len_reached <= '0';
tx_fifo_w_data_enable <= '1';
wbs_ack <= '1';
first_DW_int <= x"F"; -- set value for next wr cycle
state <= WR_TRANS;
else
wr_req <= '0';
rd_req <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
rd_trans_done <= '0';
len_is_1024DW <= '0';
cpl_return_len <= (others => '0');
state <= IDLE;
end if;
else
state <= HEADER_TO_FIFO;
end if;
when RD_TRANS =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '1';
wbs_adr_int <= wbs_adr_int;
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= '0';
rd_burst <= rd_burst;
wr_burst <= '0';
max_wr_len_reached <= '0';
first_DW_int <= first_DW_int; -- unused for read requests
last_DW_int <= last_DW_int; -- unused for read requests
cnt_len <= std_logic_vector(unsigned(cnt_len) + to_unsigned(1,10));
cpl_return_len <= cpl_return_len;
len_is_1024DW <= len_is_1024DW;
--------------------------------------------------------------------------------
-- there are several possible transitions:
-- 1. CPLD length is the same as PCIE_REQUEST_LENGTH
-- 1a. aligned address and even length => no action
-- 1b. aligned address and odd length => drop 1 dummy packet from RX FIFO
-- 1c. not aligned address and even length => drop 1 dummy packet from RX FIFO
-- 1d. not aligned address and odd length => no action
-- 2. CPLD length is smaller than PCIE_REQUEST_LENGTH (multiple CPLDs)
-- 2a. return to GET_RD_HEADER and wait for next packet
-- 2b. don't write a new header to TX header FIFO
-- 2c. manage address and length as described in 1.
-- 3. WBM finishes transfer while more data packets are in RX FIFO
-- 3a. drop data until PCIE_REQUEST_LENGTH is reached
-- 3b. remember that every split completion has its own header info included
--------------------------------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif rx_fifo_c_empty = '1' and cnt_len < length_int then
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
state <= WAIT_ON_FIFO;
-------------------------
-- single read requests
-------------------------
elsif wbs_cti = ZERO_03B or (wbs_cti = FULL_03B and rd_burst = '0') then
-------------------------------------------------------------
-- aligned single requests always include a dummy packet
-- not aligned single requests never include a dummy packet
-- I/O completions are always aligned
-------------------------------------------------------------
wbs_ack <= '0';
rd_trans_done <= '1';
if wbs_tga_q = '0' and wbs_adr_int(2) = '1' then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
else
rx_fifo_c_rd_enable <= '1';
state <= DROP_DATA;
end if;
-----------------
-- end of burst
-----------------
elsif wbs_cti = FULL_03B and rd_burst = '1' then
wbs_ack <= '0';
rd_trans_done <= '1';
-------------------------------------------------------------------
-- requested length is reached and data is transferred completely
-- drop dummy packet for aligned & odd or !aligned & even
-------------------------------------------------------------------
if cpl_return_len = requested_len and cnt_len = length_int then
if (wbs_adr_int(2) = '0' and length_int(0) = '0') or
(wbs_adr_int(2) = '1' and length_int(0) = '1') then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
elsif (wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') then
state <= DROP_DATA;
end if;
---------------------------------------------------------------------------
-- drop all outstanding CPLDs but capture header thus go to GET_RD_HEADER
-- from there we'll go to DROP_DATA again
---------------------------------------------------------------------------
elsif cpl_return_len < requested_len and cnt_len = length_int then
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
---------------------------------
-- drop all outstanding packets
---------------------------------
else
state <= DROP_DATA;
end if;
-----------------------
-- burst still active
-----------------------
else
-----------------------------------------------------------------------------
-- when first_rd_cycle is asserted and cnt_len =0 this is a 1024DW transfer
-- -> remain in RD_TRANS
-- in case of PCIE_REQUEST_LENGTH = 1024 and full transfer then
-- cpl_return_len =0 and cpl_return_len = cnt_len would be true right
-- and we would transition to IDLE too early
-----------------------------------------------------------------------------
if first_rd_cycle = '1' and cnt_len = ZERO_10B then
state <= RD_TRANS;
elsif cnt_len = length_int and cpl_return_len = requested_len then
wbs_ack <= '0';
------------------------------------------
-- check if dummy packet must be removed
------------------------------------------
if (wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') then
state <= DROP_DATA;
else
----------------------------------------------------------------------------------------
-- calculate length to 4k boundary:
-- wbs_adr[12] denotes 4k boundary which is 0x1000
-- maximum transfer length is 1024DW = 1024 *4B = 4096B := 0x1000
-- => if wbs_adr[11:0] = 0b000 then all lenghts are ok
-- otherwise calculate length offset to next 4k boundary, use to_4k_len as DW counter
-- subtracting wbs_adr from the next 4k boundary results in a byte value
-- -> use 1024 instead of 4096 to calculated DW counter instead of byte counter
-- ! manage first_DW_be and last_DW_be accordingly
-- wbs_adr is the last transferred address here so to_4k_len must be reduced by 4bytes
----------------------------------------------------------------------------------------
--if wbs_adr(11 downto 0) = x"000" then
if (unsigned(wbs_adr(11 downto 0)) + to_unsigned(4,12)) = x"000" then
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
else
compare_to_4k_len <= '1';
to_4k_len <= std_logic_vector(to_unsigned((1024 - to_integer(unsigned(wbs_adr(11 downto 2))) -1), 10));
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
state <= HEADER_TO_FIFO;
end if;
elsif cnt_len = length_int and cpl_return_len < requested_len then
wbs_ack <= '0';
if (wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') then
state <= DROP_DATA;
else
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
end if;
else
state <= RD_TRANS;
end if;
end if;
when WR_TRANS =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '1';
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= '1';
rd_req <= '0';
multi_cpl <= '0';
cnt_len <= std_logic_vector(unsigned(cnt_len) + to_unsigned(1,10));
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
wbs_adr_int <= wbs_adr_int;
first_DW_int <= first_DW_int;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
if cnt_len = FULL_10B then
max_wr_len_reached <= '1';
else
max_wr_len_reached <= '0';
end if;
-------------------------------------------------------------
-- stop transfer upon error timeout
-- if TX data FIFO is full suspend until space is available
-- cti = "000" and cti = "111" signal end of transfer thus
-- put header to FIFO
-- cti = "010" states ongoing burst thus stay here
-- if max wr length is reached put header to FIFO
-------------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif tx_fifo_w_data_usedw >= SUSPEND_FIFO_ACCESS then
if cnt_len(0) = '1' then
tx_fifo_w_data_enable <= '1';
else
tx_fifo_w_data_enable <= '0';
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
-- full FIFO and last packet of transfer could coincide and would not be covered here so use wbs_sel instead of 0xF
-- if cnt_len = 0x1 then last_DW_int must be 0x0 as single transfers only contain first_DW_int
if cnt_len = ONE_10B then
last_DW_int <= x"0";
else
last_DW_int <= wbs_sel;
end if;
state <= HEADER_TO_FIFO;
elsif wbs_cti = "010" then
wr_burst <= '1';
if max_wr_len_reached = '1' or (compare_to_4k_len = '1' and cnt_len = to_4k_len) then
-- store dummy packet if to_4k_len is not even, max_wr_len_reached should result in even length
if cnt_len(0) = '1' then
tx_fifo_w_data_enable <= '1';
else
tx_fifo_w_data_enable <= '0';
end if;
-- if cnt_len = 0x1 then last_DW_int must be 0x0 as single transfers only contain first_DW_int
if cnt_len = ONE_10B then
last_DW_int <= x"0";
else
last_DW_int <= x"F";
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
state <= HEADER_TO_FIFO;
else
state <= WR_TRANS;
end if;
else
wr_burst <= '0';
---------------------------------------------------------
-- odd lengths need one dummy packet so that 64bit side
-- can take the data from the FIFO
---------------------------------------------------------
if cnt_len(0) = '1' then
tx_fifo_w_data_enable <= '1';
else
tx_fifo_w_data_enable <= '0';
end if;
----------------------------------------
-- for single writes last_DW must be 0
----------------------------------------
--TODO ITEM cti=111 is a valid equivalent for cti=000 for single!
-- idea: use signal which is set if cti=010 and which remains active (e.g. registered) to qualify cti=111 as either
-- single (extra signal=0) or burst (extra signal=1)
if wbs_cti = FULL_03B and wr_burst = '1' then
last_DW_int <= wbs_sel;
else
last_DW_int <= (others => '0');
end if;
tx_fifo_wr_head_en_int <= '1';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
put_header <= '1';
state <= HEADER_TO_FIFO;
end if;
when WAIT_ON_FIFO =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
wbs_adr_int <= wbs_adr_int;
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= wr_req;
rd_req <= rd_req;
wr_burst <= wr_burst;
max_wr_len_reached <= '0';
multi_cpl <= multi_cpl;
first_DW_int <= first_DW_int;
cnt_len <= cnt_len;
cpl_return_len <= cpl_return_len;
rd_trans_done <= rd_trans_done;
len_is_1024DW <= len_is_1024DW;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
---------------------------------------------------------
-- if wr_req and rd_req =0 then previous state was IDLE
-- else return to RD_TRANS or WR_TRANS respectively
---------------------------------------------------------
--------------------------------------------------------
-- for writes several FIFO states occur:
-- 1. from IDLE because TX data FIFO is full
-- wr_req is still 0 as this is set during WR_TRANS
-- 2. from WR_TRANS because data FIFO is full
-- this is managed by SUSPEND_FIFO_ACCESS and
-- RESUME_FIFO_ACCESS and wr_req = 1
--------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif wr_req = '1' and tx_fifo_w_data_full = '0' and tx_fifo_w_data_usedw <= RESUME_FIFO_ACCESS then
tx_fifo_w_data_enable <= '1';
wbs_ack <= '1';
state <= WR_TRANS;
------------------------------------------------------------------
-- for reads several FIFO states occur:
-- 1. from IDLE because TX header FIFO is full
-- rd_req is still 0 as this is set during HEADER_TO_FIFO
-- 2. from RD_TRANS because RX FIFO is empty
-- rd_req = 1
-- 2a. because PCIE_REQUEST_LENGTH is transferred
-- multi_cpl= 0
-- 2b. because root splits PCIE_REQUEST_LENGTH into several CPLD
-- multi_cpl= 1
-- 2c. because WBM requests more than PCIE_REQUEST_LENGTH
-- cnt_len = PCIE_REQUEST_LENGTH and wbs_cti /= 111
------------------------------------------------------------------
elsif rd_req = '1' and multi_cpl = '0' and tx_fifo_wr_head_full = '0' then
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '1';
state <= RD_TRANS;
elsif rd_req = '1' and multi_cpl = '1' and rx_fifo_c_empty = '0' then
state <= GET_RD_HEADER;
elsif wr_req = '0' and rd_req = '0' and tx_fifo_w_data_full = '0' and tx_fifo_w_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_wr_head_full = '0' then
state <= IDLE;
else
state <= WAIT_ON_FIFO;
end if;
when GET_RD_HEADER =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
wbs_ack <= '0';
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= '0';
rd_req <= '1';
wr_burst <= '0';
max_wr_len_reached <= '0';
first_DW_int <= first_DW_int;
cnt_len <= ONE_10B;
rd_trans_done <= rd_trans_done;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
------------------------------------------------------------------------
-- update internal address for multiple CPLDs to manage FIFO correctly
-- shifting length_int left by 2 is the same as *4
-- update wbs_adr_int on last valid cycle of length_int which is
-- before any header updates thus check for all get_headers=0
------------------------------------------------------------------------
if multi_cpl = '1' and rx_fifo_c_empty = '0' and get_header = '0' and get_header_q = '0' and get_header_qq = '0' and get_header_qqq = '0' then
wbs_adr_int <= std_logic_vector(unsigned(wbs_adr_int) + unsigned(length_int(7 downto 0) & "00"));
else
wbs_adr_int <= wbs_adr_int;
end if;
if rx_fifo_c_empty = '0' then
rx_fifo_c_rd_enable <= '1';
else
rx_fifo_c_rd_enable <= '0';
end if;
-----------------------------------------------------------------------------------
-- as multiple completions can occur add actual transfer length to cpl_return_len
-----------------------------------------------------------------------------------
if get_header = '1' then
cpl_return_len <= std_logic_vector(unsigned(cpl_return_len) + unsigned(length_int));
end if;
if get_header = '1' and get_header_q = '0' then
get_header <= '0';
elsif rx_fifo_c_empty = '0' and get_header_q = '0' and get_header_qq = '0' and get_header_qqq = '0' then
get_header <= '1';
end if;
------------------------------------------
-- capture if multiple CPLD will be send
-- relevant for bursts only
------------------------------------------
--if get_header_q = '1' and rd_burst = '1' and cpl_return_len < requested_len then
if get_header_q = '1' and rd_burst = '1' and (
(requested_len /= ZERO_10B and cpl_return_len < requested_len) or
(requested_len = ZERO_10B and cpl_return_len > requested_len)) then
multi_cpl <= '1';
end if;
--------------------------------------
-- 1024DW is encoded as length_int=0
-- decode to enable comparison with
-- cnt_len in RD_TRANS as cnt_len
-- has 0 as reset value
--------------------------------------
if get_header_q = '1' and length_int = ZERO_10B then
len_is_1024DW <= '1';
elsif get_header_q = '1' and length_int > ZERO_10B then
len_is_1024DW <= '0';
else
len_is_1024DW <= len_is_1024DW;
end if;
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
----------------------------------------------
-- WB transaction done but outstanding CPLDs
-- -> burst only
----------------------------------------------
elsif multi_cpl = '1' and rd_trans_done = '1' and ((wbs_adr_int(2) = '0' and get_header_qqq = '1') or (wbs_adr_int(2) = '1' and get_header_qq = '1')) then
state <= DROP_DATA;
------------------------------------------------------------
-- RX FIFO contains 4 header packets if address is aligned
-- else 3 header packets
-- I/O completions always return with lower address =0
-- thus they are always aligned!
------------------------------------------------------------
elsif (wbs_tga_q = '0' and ((wbs_adr_int(2) = '0' and get_header_qqq = '1') or (wbs_adr_int(2) = '1' and get_header_qq = '1'))) or
(wbs_tga_q = '1' and get_header_qqq = '1') then
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '1';
state <= RD_TRANS;
else
state <= GET_RD_HEADER;
end if;
when DROP_DATA =>
tx_fifo_wr_head_clr <= '0';
tx_fifo_w_data_clr <= '0';
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '1';
wbs_ack <= '0';
wbs_adr_int <= wbs_adr_int;
put_header <= '0';
put_h0_h1 <= '0';
wr_req <= wr_req;
rd_req <= rd_req;
wr_burst <= wr_burst;
max_wr_len_reached <= '0';
multi_cpl <= multi_cpl;
first_DW_int <= first_DW_int;
last_DW_int <= last_DW_int;
cpl_return_len <= cpl_return_len;
rd_trans_done <= rd_trans_done;
len_is_1024DW <= len_is_1024DW;
compare_to_4k_len <= compare_to_4k_len;
to_4k_len <= to_4k_len;
-----------------------------------------------------
-- remain in DROP_DATA and don't go to WAIT ON FIFO
-- if FIFO is not ready
-----------------------------------------------------
if rx_fifo_c_empty = '0' then
cnt_len <= std_logic_vector(unsigned(cnt_len) + to_unsigned(1,10));
end if;
-------------------------------------------------------------------------------------
-- for I/O completions just drop one packet then go to IDLE
-- for single transmission return to IDLE when all data packets are taken from FIFO
-- for multiple CPLDs
-- 1. drop dummy data packet at the end of RD_TRANS before GET_RD_HEADER
-- 2. drop data packets because WB transaction is done including possible
-- dummy packet
-- as cnt_len now starts with 1 cnt_len can have the value cnt_len +1 = length_int
-- thus use >= for comparison
-------------------------------------------------------------------------------------
if error_timeout = '1' then
tx_fifo_wr_head_en_int <= '0';
tx_fifo_w_data_enable <= '0';
rx_fifo_c_rd_enable <= '0';
wbs_ack <= '0';
cnt_len <= (others => '0');
put_header <= '0';
put_h0_h1 <= '0';
get_header <= '0';
wr_req <= '0';
rd_req <= '0';
wr_burst <= '0';
rd_burst <= '0';
max_wr_len_reached <= '0';
multi_cpl <= '0';
first_DW_int <= (others => '0');
last_DW_int <= (others => '0');
cpl_return_len <= (others => '0');
rd_trans_done <= '0';
len_is_1024DW <= '0';
state <= IDLE;
elsif wbs_tga_q = '1' then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
------------------------------
-- no dummy packet to remove
------------------------------
elsif cnt_len = length_int and (
(wbs_adr_int(2) = '0' and length_int(0) = '0') or
(wbs_adr_int(2) = '1' and length_int(0) = '1') ) then
if multi_cpl = '0' or (multi_cpl = '1' and cpl_return_len = requested_len) then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
elsif multi_cpl = '1' and cpl_return_len < requested_len then
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
else
state <= DROP_DATA;
end if;
---------------------------
-- dummy packet to remove
---------------------------
elsif cnt_len > length_int and (
(wbs_adr_int(2) = '0' and length_int(0) = '1') or
(wbs_adr_int(2) = '1' and length_int(0) = '0') ) then
if multi_cpl = '0' or (multi_cpl = '1' and cpl_return_len = requested_len) then
rx_fifo_c_rd_enable <= '0';
state <= IDLE;
elsif multi_cpl = '1' and cpl_return_len < requested_len then
rx_fifo_c_rd_enable <= '0';
state <= GET_RD_HEADER;
else
state <= DROP_DATA;
end if;
-------------------------------------
-- length to remove not reached yet
-------------------------------------
else
state <= DROP_DATA;
end if;
-- coverage off
when others =>
-- synthesis translate_off
wbs_ack <= '0';
compare_to_4k_len <= '0';
to_4k_len <= (others => '0');
state <= IDLE;
report "wrong state encoding in process fsm_transout of z091_01_wb_slave.vhd" severity error;
-- synthesis translate_on
-- coverage on
end case;
end if;
end process fsm_transout;
-------------------------------------------------------------------------------
wbs_data : process(wb_rst, wb_clk)
begin
if wb_rst = '1' then
requested_len <= (others => '0');
tx_fifo_wr_head_in <= (others => '0');
length_int <= (others => '0');
act_read_size <= (others => '0');
elsif wb_clk'event and wb_clk = '1' then
-------------------------------------------------------------------------------------
-- compose the actual maximum read size out of PCIE_REQUEST_LENGTH and max_read_len
-- CAUTION: max_read_len may not change during an ongoing burst!
-------------------------------------------------------------------------------------
if max_read_len = "0000000000" then
act_read_size <= PCIE_REQUEST_LENGTH;
elsif PCIE_REQUEST_LENGTH > max_read_len or PCIE_REQUEST_LENGTH = "0000000000" then
act_read_size <= max_read_len;
else
act_read_size <= PCIE_REQUEST_LENGTH;
end if;
-------------------------------------------------
-- assemble write request specific header parts
-------------------------------------------------
if(put_header = '1' and put_h0_h1 = '0' and wr_req = '1') then
requested_len <= (others => '0');
tx_fifo_wr_head_in(31) <= '1';
--------------------------------------------------
-- write request is done when header is composed
-- thus use registered copy of tga
--------------------------------------------------
if(wbs_tga = '0') then -- memory
tx_fifo_wr_head_in(30) <= '1';
tx_fifo_wr_head_in(29) <= '1';
else -- I/O
tx_fifo_wr_head_in(30) <= '0';
tx_fifo_wr_head_in(29) <= '0';
end if;
tx_fifo_wr_head_in(28 downto 18) <= "00000000000";
tx_fifo_wr_head_in(17 downto 14) <= first_DW_int;
tx_fifo_wr_head_in(13 downto 10) <= last_DW_int;
---------------------------------------------------------------------------------
-- cnt_len counts to one more while transitioning to next state thus subtract 1
---------------------------------------------------------------------------------
tx_fifo_wr_head_in(9 downto 0) <= std_logic_vector(unsigned(cnt_len) - to_unsigned(1,10));
------------------------------------------------
-- assemble read request specific header parts
------------------------------------------------
elsif(put_header = '1' and put_h0_h1 = '0' and rd_req = '1') then
tx_fifo_wr_head_in(31) <= '0';
tx_fifo_wr_head_in(30) <= '0';
if(wbs_tga = '0') then -- memory
tx_fifo_wr_head_in(29) <= '1';
else -- I/O
tx_fifo_wr_head_in(29) <= '0';
end if;
tx_fifo_wr_head_in(28 downto 18) <= "00000000000";
---------------------------------------
-- always request all bytes for reads
-- WBM will chose later
---------------------------------------
tx_fifo_wr_head_in(17 downto 14) <= x"F"; -- first_DW
---------------------------------------------------------------------------------------------------------------------------
-- if PCIE_REQUEST_LENGTH is max (=0), max_read_len is either =0 too then maximum size is allowed or max_read_len is /= 0
-- then max_read_len must be used -> using max_read_len for both cases is always correct
-- otherwise PCIE_REQUEST_LENGTH is only allowed if <= max_read_len
-- all values may not exceed to_4k_len if it has to be obeyed which is denoted by compare_to_4k_len
---------------------------------------------------------------------------------------------------------------------------
if wbs_cti = "000" or wbs_cti = "111" then
requested_len <= "0000000001";
tx_fifo_wr_head_in(9 downto 0) <= "0000000001";
--------------------------------
-- for single read last_DW =0!
--------------------------------
tx_fifo_wr_head_in(13 downto 10) <= x"0"; -- last_DW
else
tx_fifo_wr_head_in(13 downto 10) <= x"F"; -- last_DW
if compare_to_4k_len = '1' then
if act_read_size <= to_4k_len then
tx_fifo_wr_head_in(9 downto 0) <= act_read_size;
requested_len <= act_read_size;
else
requested_len <= to_4k_len;
tx_fifo_wr_head_in(9 downto 0) <= to_4k_len;
end if;
else
tx_fifo_wr_head_in(9 downto 0) <= act_read_size;
requested_len <= act_read_size;
end if;
--if compare_to_4k_len = '1' and to_4k_len /= "0000000000" then
-- if PCIE_REQUEST_LENGTH <= max_read_len and PCIE_REQUEST_LENGTH <= to_4k_len then
-- requested_len <= PCIE_REQUEST_LENGTH;
-- tx_fifo_wr_head_in(9 downto 0) <= PCIE_REQUEST_LENGTH;
-- elsif PCIE_REQUEST_LENGTH <= max_read_len and PCIE_REQUEST_LENGTH > to_4k_len then
-- requested_len <= to_4k_len;
-- tx_fifo_wr_head_in(9 downto 0) <= to_4k_len;
-- elsif PCIE_REQUEST_LENGTH > max_read_len and max_read_len > to_4k_len then
-- requested_len <= to_4k_len;
-- tx_fifo_wr_head_in(9 downto 0) <= to_4k_len;
-- else
-- requested_len <= max_read_len;
-- tx_fifo_wr_head_in(9 downto 0) <= max_read_len;
-- end if;
--else
-- if(PCIE_REQUEST_LENGTH = "0000000000") then
-- requested_len <= max_read_len;
-- tx_fifo_wr_head_in(9 downto 0) <= max_read_len;
-- elsif(PCIE_REQUEST_LENGTH <= max_read_len or max_read_len = "0000000000") then
-- requested_len <= PCIE_REQUEST_LENGTH;
-- tx_fifo_wr_head_in(9 downto 0) <= PCIE_REQUEST_LENGTH;
-- else
-- requested_len <= max_read_len;
-- tx_fifo_wr_head_in(9 downto 0) <= max_read_len;
-- end if;
--end if;
end if;
------------------------------------------------------------------------------
-- length is for both read and write requests at the same position in header
------------------------------------------------------------------------------
elsif(put_header = '1' and put_h0_h1 = '1') then
requested_len <= requested_len;
tx_fifo_wr_head_in <= wbs_adr_int(31 downto 2) & "00";
end if;
-------------------------------------------
-- store length of this completion packet
-------------------------------------------
if state = GET_RD_HEADER and rx_fifo_c_empty = '0' and get_header = '0' and get_header_q = '0' and get_header_qq = '0' and get_header_qqq = '0' then
length_int <= rx_fifo_c_out(9 downto 0);
end if;
end if;
end process wbs_data;
end architecture z091_01_wb_slave_arch;
| gpl-3.0 | 0fa3f166870bba0b1e13cdc06a977cd5 | 0.364493 | 4.592249 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutexattr_init_1.vhd | 2 | 15,221 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutexattr_init_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutexattr_t * mutexattr = (hthread_mutexattr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutexattr_init( mutexattr );
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutexattr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEXATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = attr->num
when STATE_4 =>
-- read value of attr->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | fd6c35424acb987b495ad9bbb53b0567 | 0.538467 | 3.856347 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_rwTest.vhd | 2 | 13,931 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
LOOP_1,
LOOP_2,
LOOP_3,
LOOP_4,
MEMCPY_1,
MEMCPY_2,
MEMCPY_3,
MEMCPY_4,
CALL_EXIT,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_CALL_EXIT : std_logic_vector(0 to 15) := x"0004";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal argumentPtr, argumentPtr_next : std_logic_vector(0 to 31);
signal readPtr, readPtr_next : std_logic_vector(0 to 31);
signal writePtr, writePtr_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
signal operation, operation_next : std_logic_vector(0 to 1);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
argumentPtr <= argumentPtr_next;
readPtr <= readPtr_next;
writePtr <= writePtr_next;
count <= count_next;
operation <= operation_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_CALL_EXIT =>
current_state <= CALL_EXIT;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
argumentPtr_next <= argumentPtr;
readPtr_next <= readPtr;
writePtr_next <= writePtr;
count_next <= count;
operation_next <= operation;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
when FUNCTION_START =>
-- Read the argument pointer
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= x"00000000";
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
argumentPtr_next <= toUser_value;
-- Read the address of the readPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
readPtr_next <= toUser_value;
-- Read the address of the writePtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= argumentPtr + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
writePtr_next <= toUser_value;
-- read the value of count (which is in bytes)
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= argumentPtr + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
count_next <= toUser_value;
-- read the value of operation
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= argumentPtr + 12;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
operation_next <= toUser_value(30 to 31);
case toUser_value(30 to 31) is
when "11" => -- memcopy operation
next_state <= MEMCPY_1;
when others =>
next_state <= LOOP_1;
end case;
when LOOP_1 =>
case count is
when x"00000000" =>
next_state <= CALL_EXIT;
when others =>
next_state <= LOOP_2;
end case;
when LOOP_2 =>
case operation is
when "00" => -- continuous write
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= writePtr;
thrd2intrfc_value <= x"0000ABCD";
next_state <= WAIT_STATE;
return_state_next <= LOOP_4;
when "01" => -- continuous read
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= readPtr;
next_state <= WAIT_STATE;
return_state_next <= LOOP_4;
when others => -- continuous read, write
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= readPtr;
next_state <= WAIT_STATE;
return_state_next <= LOOP_3;
end case;
when LOOP_3 =>
-- continuous read, write
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= writePtr;
thrd2intrfc_value <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= LOOP_4;
when LOOP_4 =>
-- decrement count, increment readPtr, writePtr
count_next <= count - 4;
readPtr_next <= readPtr + 4;
writePtr_next <= writePtr + 4;
next_state <= LOOP_1;
when MEMCPY_1 =>
-- call memcpy
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= count;
next_state <= WAIT_STATE;
return_state_next <= MEMCPY_2;
when MEMCPY_2 =>
-- call memcpy
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= writePtr;
next_state <= WAIT_STATE;
return_state_next <= MEMCPY_3;
when MEMCPY_3 =>
-- call memcpy
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= readPtr;
next_state <= WAIT_STATE;
return_state_next <= MEMCPY_4;
when MEMCPY_4 =>
-- call memcpy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_MEMCPY;
thrd2intrfc_value <= Z32(0 to 15) & U_CALL_EXIT;
next_state <= WAIT_STATE;
when CALL_EXIT =>
thrd2intrfc_opcode <= OPCODE_RETURN;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= WAIT_STATE;
when WAIT_STATE =>
case toUser_goWait is
when '1' => --Here becasue HWTUL chose to be here for one clock cycle
next_state <= return_state;
when OTHERS => --ie '0', Here because HWTI is telling us to wait
next_state <= return_state;
end case;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 3cc20cb4b840680bbc3890300d519cb1 | 0.589405 | 3.783542 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_adder.vhd | 3 | 6,405 | -------------------------------------------------------------------------------
-- $Id: pf_adder.vhd,v 1.1 2003/03/15 01:05:26 ostlerf Exp $
-------------------------------------------------------------------------------
-- pf_adder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder.vhd
--
-- Description: Parameterized adder/subtractor for Mauna Loa Packet FIFO
-- vacancy calculation. This design has a combinational
-- output. The carry out is not used by the PFIFO so it has
-- been removed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/03/15 01:05:26 $
--
-- History:
-- DET 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze timer counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_adder_bit component
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder is
generic (
C_REGISTERED_RESULT : Boolean := false;
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
--Carry_Out : out std_logic;
Ain : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Bin : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Add_sub_n : in std_logic;
result_out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_adder;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder is
component pf_adder_bit is
generic (
C_REGISTERED_RESULT : Boolean
);
port (
Clk : in std_logic;
Rst : In std_logic;
Ain : in std_logic;
Bin : in std_logic;
Add_sub_n : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end component pf_adder_bit;
-- component FDRE is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- CE : in std_logic;
-- D : in std_logic;
-- R : in std_logic
-- );
-- end component FDRE;
--
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iresult_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
--signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= not(Add_sub_n); -- initial carry-in to adder LSB
count_clock_en <= '1';
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : pf_adder_bit
Generic map(
C_REGISTERED_RESULT => C_REGISTERED_RESULT
)
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Ain => Ain(i), -- [in]
Bin => Bin(i), -- [in]
Add_sub_n => Add_sub_n, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iresult_out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
-- carry_active_high <= alu_cy(0) xor not(Add_sub_n);
--
--
--
-- I_CARRY_OUT: FDRE
-- port map (
-- Q => Carry_Out, -- [out]
-- C => Clk, -- [in]
-- CE => count_clock_en, -- [in]
-- D => carry_active_high, -- [in]
-- R => Rst -- [in]
-- );
result_out <= iresult_out;
end architecture implementation;
| bsd-3-clause | ade61c8e018a4cbe07d3fdd53bfb6c06 | 0.352381 | 4.607914 | false | false | false | false |
michaelmiehling/A25_VME | 16z000-00_src/Source/examples/fpga_pkg_2_16zxxx.vhd | 1 | 2,791 | ---------------------------------------------------------------
-- Title : fpga_pkg_2 example for IP-Core top file
-- Project :
---------------------------------------------------------------
-- File : fpga_pkg_2_16zxxx.vhd
-- Author : Florian Wombacher
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 2008-04-01
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
-- fpga_pkg_2_16zxxx.vhd
-- - one_device.vhd
--
---------------------------------------------------------------
-- Copyright (C) 2008, MEN Mikro Elektronik Nuremberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.2 $
--
-- $Log: fpga_pkg_2_16zxxx.vhd,v $
-- Revision 1.2 2009/02/17 11:37:40 FWombacher
-- cosmetics due to rule checker
--
-- Revision 1.1 2008/11/21 15:16:56 FWombacher
-- Initial Revision
--
-- Revision 1.1 2008/10/24 16:39:57 FWombacher
-- Initial Revision
--
-- Revision 1.1 2008/10/22 14:19:16 FWombacher
-- Initial Revision
--
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY fpga_pkg_2_16zxxx IS
GENERIC (
FPGA_FAMILY : family_type := CYCLONE
);
PORT(
dummy : OUT std_logic
);
END ENTITY;
ARCHITECTURE fpga_pkg_2_16zxxx_arch OF fpga_pkg_2_16zxxx IS
CONSTANT SUPPORTED_DEVICES : supported_family_type := (CYCLONE);
COMPONENT one_device
GENERIC (
FPGA_FAMILY : family_type := NONE -- use NONE to force definiton in top level file
);
PORT
(
dummy : OUT std_logic
);
END COMPONENT;
BEGIN
-- coverage off
ASSERT NOT NO_VALID_DEVICE(supported_device => SUPPORTED_DEVICES, device => FPGA_FAMILY) REPORT "No valid DEVICE!" SEVERITY failure;
-- coverage on
the_one_device : one_device
GENERIC MAP (
FPGA_FAMILY => FPGA_FAMILY -- use NONE to force definiton in top level file
)
PORT MAP (
dummy => dummy
);
END ARCHITECTURE fpga_pkg_2_16zxxx_arch;
| gpl-3.0 | 24d63968f5b88d9bde92e7aa993ebfe9 | 0.450018 | 4.582923 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v3_00_a/hdl/vhdl/opb_bam.vhd | 2 | 68,187 | -------------------------------------------------------------------------------
-- $Id: opb_bam.vhd,v 1.10 2004/05/17 20:33:20 gburch Exp $
-------------------------------------------------------------------------------
-- opb_bam.vhd
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: opb_bam.vhd
--
-- Description: Bus Attachment Module, OPB to IPIC.
--
--
-------------------------------------------------------------------------------
-- Structure: opb_bam
-- reset_mir
-- interrupt_controller
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
--
-- FLO 10/22/02
-- ^^^^^^
-- Initial version.
-- ~~~~~~
-- FLO 12/09/02
-- ^^^^^^
-- Support now for posted writes and burst of posted writes under
-- OPB_seqAddr=1. (The latter not yet tested.)
-- ~~~~~~
-- FLO 03/21/03
-- ^^^^^^
-- Hooked up neglected connection of OPB_BE to opb_be_s0.
-- ~~~~~~
-- FLO 05/15/2003
-- ^^^^^^
-- Introduced signal OPB_seqAddr_eff to disable bursts when parameter
-- C_DEV_BURST_ENABLE is false.
-- ~~~~~~
--
--
-- FLO 05/27/2003
-- ^^^^^^
-- Use sln_xferack_s1 to enable other than '0' values to the
-- OPBOUT pipestage when this stage is present and there is
-- a single address range. This, in turn, allows the optimization
-- of passing ip2bus_data through to ip2bus_data_mx without
-- qualification by a CE Address-Range decode, saving a LUT per
-- data-bus bit for this case.
--
-- ~~~~~~
--
-- FLO 05/28/2003
-- ^^^^^^
-- Made a correction to the last change that was causing it to
-- drive sln_dbus during a write transaction.
-- Now the sln_dbus_s2 signals are separated from the other _s2 signals
-- for application of the reset when sln_xferack_s1 = '0' and this
-- reset is further qualified by bus2ip_rnw_s1.
--
-- ~~~~~~
-- FLO 09/10/2003
-- ^^^^^^
-- Fixed the mirror instantiation, which erroneously had the address tied low.
-- ~~~~~~
-- GAB 05/05/04
-- ^^^^^^
-- Fixed problem with double clock wrce to interrupt_control.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- ToDo Worklist:
-- [ ] (1) Retain RdCE and WrCE, even though each is generated with LUT2?
-- Discuss with Bert.
-- [021121 These are left in. It might be a good idea to document
-- that in cases where e.g. WrCE goes into a parially filled
-- LUT, using CE and RNW instead of WrCE would save a LUT.]
-- [ ] (2) Optimization of decoding as a function of the specific
-- C_ARD_ADDR_RANGE_ARRAY values is a possibility for consideration
-- (e.g. common high-order address bits, common CE offsets, or
-- in general any selection of common address bits that leads to
-- overall resource reduction).
-- [ ] (3) Implement consistency checks for generics, etc.
-- [ ] Booleans passed as integers are either 0 to 1.
-- [ ] At most one address range may be for a reset_mir.
-- [ ] reset_mir address range has exactly one CE
-- [ ] That other "internal" address ranges have consistent # of CEs.
-- [ ] ...
-- [x] (4) Handle retry.
-- [x] (5) Handle timeout. Should require nothing here.
-- [ ] (6) Optimize INTR by implementing and using the OWN_RESP_SIGS,
-- RESP_SIGS_ID concept, or possibly by reworking the interrupt
-- block to have its own response signals, in which case the
-- option to exclude bits should also be implemented.
-- [ ] (7) Slave burst writes.
-- [ ] (8) Slave burst reads.
-- [ ] (9) Master operation.
-- [ ] (10) We could introduce the concept of an address-range span, ARS.
-- An ARS is a set of address ranges. The size of the address
-- space corresponding the ARS is the smallest power of two
-- in units of bytes that is large enough to include all of the
-- address ranges of the span. The base address of the ARS is the
-- smallest of the base addresses of the address ranges of the
-- ARS. The high address of the ARS is the base address plus
-- the size minus one.
-- The default is that there is one ARS including all address
-- ranges in C_ARD_ADDR_RANGE_ARRAY.
-- The motivation for having address-range spans is that it
-- is then possible to place address ranges at widely separated
-- address without "chewing up" all of the unused space between.
-- The reason for not just letting each address range be its
-- own address range span is that some opportunity for optimization
-- of address decoding is lost.
-- [ ] (11) Put Interrupt and Rst/MIR parameters into dependent props.
-- [ ] (12) Put in error detection for IP2Bus_Ack not asserted on a
-- posted write allowed by postedwrinh=0
-- [ ] (13) Handle the case where the master aborts the transaction
-- by deasserting OPB_select before receiving Sln_xferAck
-- or Sln_retry. (See signal OPB_select, Mn_select in the
-- IBM OPB spec.)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.ipif_pkg.INTEGER_ARRAY_TYPE;
use ipif_common_v1_00_c.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_c.ipif_pkg.calc_num_ce;
use ipif_common_v1_00_c.ipif_pkg.calc_start_ce_index;
use ipif_common_v1_00_c.ipif_pkg.DEPENDENT_PROPS_ARRAY_TYPE;
use ipif_common_v1_00_c.ipif_pkg.get_min_dwidth;
use ipif_common_v1_00_c.ipif_pkg.IPIF_INTR;
use ipif_common_v1_00_c.ipif_pkg.IPIF_RST;
use ipif_common_v1_00_c.ipif_pkg.USER_00;
entity opb_bam is
generic
(
C_ARD_ID_ARRAY : INTEGER_ARRAY_TYPE
:= ( 0 => IPIF_INTR,
1 => IPIF_RST,
2 => USER_00
);
C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
:= ( x"0000_0000_6000_0000", -- IPIF_INTR
x"0000_0000_6000_003F",
--
x"0000_0000_6000_0040", -- IPIF_RST
x"0000_0000_6000_0043",
--
x"0000_0000_6000_0100", -- USER_00
x"0000_0000_6000_01FF"
);
C_ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE
:= ( 32, -- IPIF_INTR
32, -- IPIF_INTR
32 -- USER_00
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
:= ( 16, -- IPIF_INTR
1, -- IPIF_RST
8 -- USER_00
);
C_ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE
:= (
0 => (others => 0)
,1 => (others => 0)
,2 => (others => 0)
);
C_PIPELINE_MODEL : integer := 7;
-- The pipe stages are enumerated and numbered as:
-- -- ----------
-- n Pipe stage
-- -- ----------
-- 0 OPBIN
-- 1 IPIC
-- 2 OPBOUT
-- Each pipe stage is either present or absent (i.e. bypassed).
-- The pipe stage, n, is present iff the (2^n)th
-- bit in C_PIPELINE_MODEL is 1.
--
C_DEV_BLK_ID : INTEGER := 1;
-- Unique block ID, assigned to the device when the system is built.
C_DEV_MIR_ENABLE : INTEGER := 0;
C_AWIDTH : INTEGER := 32;
-- width of Address Bus (in bits)
C_DWIDTH : INTEGER := 32;
-- Width of the Data Bus (in bits)
C_FAMILY : string := "virtexe";
--
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE := ( 5, 1 );
--
-- There will be one interrupt signal for each entry in
-- C_IP_INTR_MODE_ARRAY. The leftmost entry will be the
-- mode for input port IP2Bus_Intr(0), the next entry
-- for IP2Bus_Intr(1), etc.
--
-- These modes are supported:
--
-- Mode Description
--
-- 1 Active-high interrupt condition.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port-- that is an interrupt condition
-- that is latched and cleared in the IP core and made available
-- to the system via the Interrupt Source Controller in
-- the Bus Attachment Module.
--
-- 2 Active-low interrupt condition.
-- Like 1, except that the interrupt condition is asserted low.
--
-- 3 Active-high pulse interrupt event.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port--whose single clock period of active-high
-- assertion is an interrupt event that is latched,
-- and cleared as a service of the Interrupt Source
-- Controller in the Bus Attachment Module.
--
-- 4 Active-low pulse interrupt event.
-- Like 3, except the interrupt-event pulse is active low.
--
-- 5 Positive-edge interrupt event.
-- The IP core drives a signal--via the corresponding
-- IP2Bus_Intr(i) port--whose low-to-high transition, synchronous
-- with the clock, is an interrupt event that is latched,
-- and cleared as a service of the Interrupt Source
-- Controller in the Bus Attachment Module.
--
-- 6 Negative-edge interrupt event.
-- Like 5, except that the interrupt event is a
-- high-to-low transition.
--
-- Other mode codes are reserved.
--
C_INCLUDE_DEV_ISC : INTEGER := 1;
-- 'true' specifies that the full device interrupt
-- source controller structure will be included;
-- 'false' specifies that only the global interrupt
-- enable register of the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller
C_INCLUDE_DEV_IID : integer := 0;
-- 'true' will include the Device IID register in the device ISC
C_DEV_BURST_ENABLE : INTEGER := 0
-- Burst Enable for IPIF Interface
--ToDo, check that C_DEV_BURST_ENABLE is eliminated from places
-- where it is not needed do to using OPB_seqAddr_eff.
);
port
(
OPB_select : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_DWIDTH-1);
OPB_ABus : in std_logic_vector(0 to C_AWIDTH-1);
OPB_BE : in std_logic_vector(0 to C_DWIDTH/8-1);
OPB_RNW : in std_logic;
OPB_seqAddr : in std_logic;
OPB_xferAck : in std_logic; --ToDo, rmv this port
Sln_DBus : out std_logic_vector(0 to C_DWIDTH-1);
Sln_xferAck : out std_logic;
Sln_errAck : out std_logic;
Sln_retry : out std_logic;
Sln_toutSup : out std_logic;
Bus2IP_CS : out std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
Bus2IP_CE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Data : out std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_Addr : out std_logic_vector(0 to C_AWIDTH-1);
Bus2IP_BE : out std_logic_vector(0 to C_DWIDTH/8-1);
Bus2IP_RNW : out std_logic;
Bus2IP_Burst : out std_logic;
IP2Bus_Data : in std_logic_vector(0 to C_DWIDTH*calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
IP2Bus_Ack : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Error : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_Retry : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_ToutSup : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
IP2Bus_PostedWrInh : in std_logic_vector(0 to C_ARD_ID_ARRAY'length-1);
OPB_Clk : in std_logic;
Bus2IP_Clk : out std_logic;
IP2Bus_Clk : in std_logic;
Reset : in std_logic;
Bus2IP_Reset : out std_logic;
IP2Bus_Intr : in std_logic_vector(0 to C_IP_INTR_MODE_ARRAY'length-1);
Device_Intr : out std_logic
);
end entity opb_bam;
--ToDo, unisim needed?
library unisim;
use unisim.all;
library proc_common_v1_00_b;
use proc_common_v1_00_b.proc_common_pkg.log2;
library ieee;
use ieee.numeric_std.TO_UNSIGNED;
library ipif_common_v1_00_c;
use ipif_common_v1_00_c.ipif_pkg.find_ard_id;
use ipif_common_v1_00_c.ipif_pkg.get_id_index;
architecture implementation of opb_bam is
----------------------------------------------------------------------------
-- MIR fields
--
-- 4 7 5 8 8 # bits
--
-- 0-----3 4----------10 11-----15 16-----------23 24------------31
-- +-------+-------------+---------+---------------+----------------+
-- |MAJOR | MINOR |REVISION | BLK_ID | TYPE | MIR
-- |VERSION| VERSION |(letter) | | |
-- +-------+-------------+---------+---------------+----------------+
-- 0 = a
-- 1 = b
-- etc.
--
-- \ | /
-- \ | /
-- \ | /
-- \ | /
-- \ | /
-- \ | /
--
-- v1_03_c (aka V1.3c)
----------------------------------------------------------------------------
constant MIR_MAJOR_VERSION : INTEGER range 0 to 15 := 1;
constant MIR_MINOR_VERSION : INTEGER range 0 to 127:= 0;
constant MIR_REVISION : INTEGER := 0;
constant MIR_TYPE : INTEGER := 1;
-- Always '1' for OPB ipif interface type
-- ToDo, stays same for bus_attach?
constant NUM_ARDS : integer := C_ARD_ID_ARRAY'length;
constant NUM_CES : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant INCLUDE_OPBIN_PSTAGE : boolean := (C_PIPELINE_MODEL/1) mod 2 = 1;
constant INCLUDE_IPIC_PSTAGE : boolean := (C_PIPELINE_MODEL/2) mod 2 = 1;
constant INCLUDE_OPBOUT_PSTAGE : boolean := (C_PIPELINE_MODEL/4) mod 2 = 1;
constant INCLUDE_RESET_MIR : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_RST);
constant INCLUDE_INTR : boolean
:= find_ard_id(C_ARD_ID_ARRAY, IPIF_INTR);
constant SINGLE_CE : boolean := C_ARD_ID_ARRAY'length = 1 and
C_ARD_NUM_CE_ARRAY(0) = 1;
constant ZERO_SLV : std_logic_vector(0 to 199) := (others => '0');
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl_table : bo2sl_type := ('0', '1');
function bo2sl(b: boolean) return std_logic is
begin
return bo2sl_table(b);
end bo2sl;
----------------------------------------------------------------------------
-- This function returns the number of high-order address bits
-- that can be commonly decoded across all address pairs passed in as
-- the argument ara. Note: only the C_AWIDTH rightmost bits of an entry
-- in ara are considered to make up the address.
----------------------------------------------------------------------------
function num_common_high_order_addr_bits(ara: SLV64_ARRAY_TYPE)
return integer is
variable n : integer := C_AWIDTH;
-- Maximum number of common high-order bits for
-- the ranges starting at an index less than i.
variable i, j: integer;
variable old_base: std_logic_vector(0 to C_AWIDTH-1)
:= ara(0)( ara(0)'length-C_AWIDTH
to ara(0)'length-1
);
variable new_base, new_high: std_logic_vector(0 to C_AWIDTH-1);
begin
i := 0;
while i < ara'length loop
new_base := ara(i )(ara(0)'length-C_AWIDTH to ara(0)'length-1);
new_high := ara(i+1)(ara(0)'length-C_AWIDTH to ara(0)'length-1);
j := 0;
while j < n -- Limited by earlier value.
and new_base(j) = old_base(j) -- High-order addr diff found
-- with a previous range.
and (new_base(j) xor new_high(j))='0' -- Addr-range boundary found
-- for current range.
loop
j := j+1;
end loop;
n := j;
i := i+2;
end loop;
return n;
end num_common_high_order_addr_bits;
constant K_DEV_ADDR_DECODE_WIDTH
: integer
:= num_common_high_order_addr_bits(C_ARD_ADDR_RANGE_ARRAY);
function cs_index_or_maxint(C_ARD_ID_ARRAY:INTEGER_ARRAY_TYPE; ID:INTEGER)
return integer is
begin
if find_ard_id(C_ARD_ID_ARRAY, ID) then
return get_id_index(C_ARD_ID_ARRAY, ID);
else
return integer'high;
end if;
end cs_index_or_maxint;
constant RESET_MIR_CS_IDX : natural
:=cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_RST);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_RESET_MIR is false.
constant INTR_CS_IDX : integer
:=cs_index_or_maxint(C_ARD_ID_ARRAY, IPIF_INTR);
-- Must be a value outside the range of valid ARD indices if
-- INCLUDE_INTR is false.
function ce_index_or_maxint(C_ARD_ID_ARRAY: INTEGER_ARRAY_TYPE; IDX: integer)
return integer is
begin
if IDX < NUM_ARDS then
return calc_start_ce_index(C_ARD_NUM_CE_ARRAY, IDX);
else
return integer'high;
end if;
end ce_index_or_maxint;
constant RESET_MIR_CE_IDX : natural
:=ce_index_or_maxint(C_ARD_ID_ARRAY,
RESET_MIR_CS_IDX);
constant INTR_CE_LO : natural
:= ce_index_or_maxint(C_ARD_ID_ARRAY,
INTR_CS_IDX);
function intr_ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY: INTEGER_ARRAY_TYPE;
IDX: integer
) return integer is
begin
if IDX < NUM_ARDS then
return calc_start_ce_index(C_ARD_NUM_CE_ARRAY, IDX)
+ C_ARD_NUM_CE_ARRAY(INTR_CS_IDX) - 1;
else
return integer'high;
end if;
end intr_ce_hi_avoiding_bounds_error;
--
constant INTR_CE_HI : natural
:= intr_ce_hi_avoiding_bounds_error(
C_ARD_ID_ARRAY,
INTR_CS_IDX
);
function number_CEs_for(ard_id: integer) return integer is
variable id_included: boolean;
begin
id_included := find_ard_id(C_ARD_ID_ARRAY, ard_id);
if id_included then
return C_ARD_NUM_CE_ARRAY(get_id_index(C_ARD_ID_ARRAY, ard_id));
else return 0;
end if;
end number_CEs_for;
----------------------------------------------------------------------------
-- Constant zero std_logic_vector large enough for any needed use.
----------------------------------------------------------------------------
constant ZSLV : std_logic_vector(0 to 255) := (others => '0');
----------------------------------------------------------------------------
-- This function returns the number of address bits that need to be
-- decoded to find a "hit" in the address range defined by
-- the idx'th pair of base_address/high_address in c_ard_addr_range_array.
-- Only the rightmost numbits are considered and the result is the
-- number of leftmost bits within this field that need to be decoded.
----------------------------------------------------------------------------
function num_decode_bits(ard_addr_range_array : SLV64_ARRAY_TYPE;
numbits : natural;
idx : natural)
return integer is
constant SZ : natural := ard_addr_range_array(0)'length;
constant ADDR_XOR : std_logic_vector(0 to numbits-1)
:= ard_addr_range_array(2*idx )(SZ-numbits to SZ-1) -- base
xor ard_addr_range_array(2*idx+1)(SZ-numbits to SZ-1); -- high
begin
for i in 0 to numbits-1 loop
if ADDR_XOR(i)='1' then return i;
end if;
end loop;
return(numbits);
end function num_decode_bits;
--------------------------------------------------------------------------
-- Returns whether bit n of the encoded representation of the data size
-- for address range ar is a 1
--
-- DSIZE Encoded value
-- 8 001
-- 16 010
-- 32 011
-- 64 100
-- 128 101
-- Others not supported
--------------------------------------------------------------------------
function encoded_size_is_1(ar, n: natural) return boolean is
begin
case n is
-- high-order bit
when 0 => return C_ARD_DWIDTH_ARRAY(ar) = 64 or
C_ARD_DWIDTH_ARRAY(ar) =128;
-- middle bit
when 1 => return C_ARD_DWIDTH_ARRAY(ar) = 16 or
C_ARD_DWIDTH_ARRAY(ar) = 32;
-- low-order bit
when 2 => return C_ARD_DWIDTH_ARRAY(ar) = 8 or
C_ARD_DWIDTH_ARRAY(ar) = 32 or
C_ARD_DWIDTH_ARRAY(ar) =128;
-- default for unsupported values
when others => return false;
end case;
end encoded_size_is_1;
----------------------------------------------------------------------------
-- Returns the number of CS signals that need to be or'ed to give
-- bit n of the encoded size.
----------------------------------------------------------------------------
function num_cs_for_bit(n: natural) return natural is
variable r: natural;
begin
r := 0;
for k in 0 to NUM_ARDS-1 loop
if encoded_size_is_1(k, n) then r := r+1; end if;
end loop;
return r;
end num_cs_for_bit;
function eff_ip2bus_val(i : integer;
rst : std_logic;
intr : std_logic;
user : std_logic
) return std_logic is
begin
if C_ARD_ID_ARRAY(i) = IPIF_RST then return rst;
elsif C_ARD_ID_ARRAY(i) = IPIF_INTR then return intr;
else return user;
end if;
end eff_ip2bus_val;
component pselect is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end component;
component or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component;
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
component IPIF_Steer is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64
C_SMALLEST : integer := 32; -- 8, 16, 32, 64
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end component IPIF_Steer;
component reset_mir is
Generic (
C_DWIDTH : integer := 32;
C_INCLUDE_SW_RST : integer := 1;
C_INCLUDE_MIR : integer := 0;
C_MIR_MAJOR_VERSION : integer := 0;
C_MIR_MINOR_VERSION : integer := 0;
C_MIR_REVISION : integer := 1;
C_MIR_BLK_ID : integer := 1;
C_MIR_TYPE : integer := 1
);
port (
Reset : in std_logic;
Bus2IP_Clk : in std_logic;
SW_Reset_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_Reset : out std_logic;
Reset2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
Reset2Bus_Ack : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_Retry : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end component reset_mir;
component interrupt_control
Generic(
C_INTERRUPT_REG_NUM : INTEGER := 16;
-- Use 16 to allow for the full set of architectural registers,
-- many of which are not populated.
--
C_NUM_IPIF_IRPT_SRC : INTEGER := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE;
C_INCLUDE_DEV_PENCODER : BOOLEAN := true;
-- Include Interrupt ID register
--
C_INCLUDE_DEV_ISC : Boolean := true;
-- If false, the device ISC not be included, except for
-- the GIE register.
--
C_IRPT_DBUS_WIDTH : INTEGER := 32
);
port(
Bus2IP_Clk_i : In std_logic;
Bus2IP_Data_sa : In std_logic_vector(0 to C_IRPT_DBUS_WIDTH-1);
Bus2IP_RdReq_sa : In std_logic;
Bus2IP_Reset_i : In std_logic;
Bus2IP_WrReq_sa : In std_logic;
Interrupt_RdCE : In std_logic_vector(0 to C_INTERRUPT_REG_NUM-1);
Interrupt_WrCE : In std_logic_vector(0 to C_INTERRUPT_REG_NUM-1);
IPIF_Reg_Interrupts : In std_logic_vector(0 to 1);
-- Interrupt inputs from the IPIF sources that will get
-- registered in this design
--
IPIF_Lvl_Interrupts : In std_logic_vector(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Level Interrupt inputs from the IPIF sources
--
IP2Bus_IntrEvent : In std_logic_vector(
0 to C_IP_INTR_MODE_ARRAY'length-1
);
-- Interrupt inputs from the IP
--
Intr2Bus_DevIntr : Out std_logic;
-- Device interrupt output to the Master Interrupt Controller
--
Intr2Bus_DBus : Out std_logic_vector(0 to C_IRPT_DBUS_WIDTH-1);
Intr2Bus_WrAck : Out std_logic;
Intr2Bus_RdAck : Out std_logic;
Intr2Bus_Error : Out std_logic;
Intr2Bus_Retry : Out std_logic;
Intr2Bus_ToutSup : Out std_logic
);
end component interrupt_control;
signal bus2ip_clk_i : std_logic;
signal bus2ip_reset_i : std_logic;
signal opb_select_s0 : std_logic;
signal opb_select_s0_d1 : std_logic;
signal opb_rnw_s0 : std_logic;
signal opb_seqaddr_s0: std_logic;
signal bus2ip_burst_s1: std_logic;
signal opb_seqaddr_d1: std_logic;
signal opb_abus_s0 : std_logic_vector(0 to C_AWIDTH-1);
signal opb_dbus_s0 : std_logic_vector(0 to C_AWIDTH-1);
signal opb_be_s0 : std_logic_vector(0 to C_DWIDTH/8-1);
signal bus2ip_rnw_s1 : std_logic;
signal bus2ip_be_s0 : std_logic_vector(0 to C_DWIDTH/8-1);
signal bus2ip_be_s1 : std_logic_vector(0 to C_DWIDTH/8-1);
signal bus2ip_cs_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_s1 : std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_hit_s0: std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_hit_s0_d1: std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_cs_enable_s0: std_logic_vector(0 to NUM_ARDS-1);
signal bus2ip_ce_s0 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_ce_s1 : std_logic_vector(0 to NUM_CES-1);
signal bus2ip_rdce_s0: std_logic_vector(0 to NUM_CES-1);
signal bus2ip_rdce_s1: std_logic_vector(0 to NUM_CES-1);
signal bus2ip_wrce_s0: std_logic_vector(0 to NUM_CES-1);
signal bus2ip_wrce_s1: std_logic_vector(0 to NUM_CES-1);
signal bus2ip_addr_s0: std_logic_vector(0 to C_AWIDTH-1);
signal bus2ip_addr_s1: std_logic_vector(0 to C_AWIDTH-1);
signal bus2ip_data_s0: std_logic_vector(0 to C_DWIDTH-1);
signal bus2ip_data_s1: std_logic_vector(0 to C_DWIDTH-1);
signal devicesel_s0 : std_logic;
constant NUM_ENCODED_SIZE_BITS : natural := 3;
type OR_CSES_PER_BIT_TABLE_TYPE is array(0 to NUM_ENCODED_SIZE_BITS-1) of
std_logic_vector(0 to NUM_ARDS-1);
signal cs_to_or_for_dsize_bit : OR_CSES_PER_BIT_TABLE_TYPE;
signal encoded_dsize_s0: std_logic_vector(0 to NUM_ENCODED_SIZE_BITS-1);
signal encoded_dsize_s1: std_logic_vector(0 to NUM_ENCODED_SIZE_BITS-1);
signal ip2bus_data_mx: std_logic_vector(0 to C_DWIDTH-1);
signal sln_dbus_s1 : std_logic_vector(0 to C_DWIDTH-1);
signal sln_dbus_s2 : std_logic_vector(0 to C_DWIDTH-1);
signal sln_xferack_s1: std_logic;
signal sln_xferack_s1_d1: std_logic;
signal sln_xferack_s1_d2: std_logic;
signal sln_xferack_s2: std_logic;
signal sln_retry_s1 : std_logic;
signal sln_retry_s2 : std_logic;
signal sln_errack_s1 : std_logic;
signal sln_errack_s2 : std_logic;
signal sln_toutsup_s1: std_logic;
signal sln_toutsup_s2: std_logic;
signal reset2bus_data : std_logic_vector(0 to C_DWIDTH-1);
signal reset2bus_ack : std_logic;
signal reset2bus_error : std_logic;
signal reset2bus_retry : std_logic;
signal reset2bus_toutsup : std_logic;
signal reset2bus_postedwrinh : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_DWIDTH-1);
signal intr2bus_rdack : std_logic;
signal intr2bus_wrack : std_logic;
signal intr2bus_ack : std_logic;
signal intr2bus_error : std_logic;
signal intr2bus_retry : std_logic;
signal intr2bus_toutsup : std_logic;
signal intr2bus_postedwrinh : std_logic;
signal new_select_s0 : std_logic_vector(0 to NUM_ARDS-1);
signal new_select_s0_d1 : std_logic_vector(0 to NUM_ARDS-1);
signal inh_cs_when_pw : std_logic_vector(0 to NUM_ARDS-1);
signal inh_cs_wnot_pw : std_logic;
signal inh_xferack_when_pw: std_logic;
signal last_xferack : std_logic;
signal last_xferack_d1 : std_logic;
signal last_xferack_d2 : std_logic;
signal last_wr_xferack : std_logic;
signal last_wr_xferack_d1 : std_logic;
signal last_wr_xferack_d2 : std_logic;
signal OPB_seqAddr_eff : std_logic;
signal postedwr_s0 : std_logic; --GB
signal postedwrack_s2 : std_logic; --GB
signal last_pw_xferack : std_logic; --GB
signal last_pw_xferack_d1 : std_logic; --GB
signal last_pw_xferack_d2 : std_logic; --GB
begin
OPB_seqAddr_eff <= OPB_seqAddr and bo2sl(C_DEV_BURST_ENABLE=1);
bus2ip_clk_i <= OPB_Clk;
Bus2IP_Clk <= OPB_Clk;
-- reset2bus_postedwrinh <= '0'; --Gb
reset2bus_postedwrinh <= '1';
intr2bus_postedwrinh <= '1';
GEN_PSTAGE0: if INCLUDE_OPBIN_PSTAGE generate
begin
PROC_PSTAGE0 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
opb_select_s0 <= '0';
else
opb_select_s0 <= OPB_select;
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
opb_rnw_s0 <= OPB_RNW;
opb_seqaddr_s0 <= OPB_seqAddr_eff;
opb_abus_s0 <= OPB_ABus;
opb_dbus_s0 <= OPB_DBus;
opb_be_s0 <= OPB_BE;
end if;
end process;
end generate;
--
GEN_BYPASS0: if not INCLUDE_OPBIN_PSTAGE generate
begin
opb_select_s0 <= OPB_select;
opb_rnw_s0 <= OPB_RNW;
opb_seqaddr_s0 <= OPB_seqAddr_eff;
opb_abus_s0 <= OPB_ABus;
opb_dbus_s0 <= OPB_DBus;
opb_be_s0 <= OPB_BE;
end generate;
GEN_PSTAGE1: if INCLUDE_IPIC_PSTAGE generate
begin
PROC_PSTAGE1 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
bus2ip_cs_s1 <= (others => '0');
bus2ip_ce_s1 <= (others => '0');
bus2ip_rdce_s1 <= (others => '0');
bus2ip_wrce_s1 <= (others => '0');
else
bus2ip_cs_s1 <= bus2ip_cs_s0;
bus2ip_ce_s1 <= bus2ip_ce_s0;
bus2ip_rdce_s1 <= bus2ip_rdce_s0;
bus2ip_wrce_s1 <= bus2ip_wrce_s0;
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
bus2ip_addr_s1 <= opb_abus_s0;
bus2ip_data_s1 <= bus2ip_data_s0;
bus2ip_be_s1 <= bus2ip_be_s0;
bus2ip_rnw_s1 <= opb_rnw_s0;
encoded_dsize_s1 <= encoded_dsize_s0;
bus2ip_burst_s1 <= opb_seqaddr_s0
and bo2sl(C_DEV_BURST_ENABLE = 1);
end if;
end process;
end generate;
--
GEN_BYPASS1: if not INCLUDE_IPIC_PSTAGE generate
begin
bus2ip_cs_s1 <= bus2ip_cs_s0;
bus2ip_ce_s1 <= bus2ip_ce_s0;
bus2ip_rdce_s1 <= bus2ip_rdce_s0;
bus2ip_wrce_s1 <= bus2ip_wrce_s0;
bus2ip_addr_s1 <= opb_abus_s0;
bus2ip_data_s1 <= bus2ip_data_s0;
bus2ip_be_s1 <= bus2ip_be_s0;
bus2ip_rnw_s1 <= opb_rnw_s0;
encoded_dsize_s1 <= encoded_dsize_s0;
bus2ip_burst_s1 <= opb_seqaddr_s0
and bo2sl(C_DEV_BURST_ENABLE = 1);
end generate;
Bus2IP_CS <= bus2ip_cs_s1;
Bus2IP_CE <= bus2ip_ce_s1;
Bus2IP_RdCE <= bus2ip_rdce_s1;
Bus2IP_WrCE <= bus2ip_wrce_s1;
Bus2IP_Addr <= bus2ip_addr_s1;
Bus2IP_Data <= bus2ip_data_s1;
Bus2IP_BE <= bus2ip_be_s1;
Bus2IP_RNW <= bus2ip_rnw_s1;
Bus2IP_Burst <= bus2ip_burst_s1;
GEN_PSTAGE2: if INCLUDE_OPBOUT_PSTAGE generate
begin
PROC_PSTAGE2 : process(bus2ip_clk_i)
begin
--------------------------------------------------------------------
-- Sigs that need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
if Reset = '1' then
sln_xferack_s2 <= '0';
sln_retry_s2 <= '0';
sln_errack_s2 <= '0';
sln_toutsup_s2 <= '0';
else
sln_xferack_s2 <= sln_xferack_s1;
sln_retry_s2 <= sln_retry_s1;
sln_errack_s2 <= sln_errack_s1;
sln_toutsup_s2 <= sln_toutsup_s1;
end if;
if (Reset or not (sln_xferack_s1 and bus2ip_rnw_s1)) = '1' then
sln_dbus_s2 <= (others => '0');
else
sln_dbus_s2 <= sln_dbus_s1;
end if;
end if;
--------------------------------------------------------------------
-- Sigs that do not need reset value
--------------------------------------------------------------------
if bus2ip_clk_i'event and bus2ip_clk_i='1' then
postedwrack_s2 <= postedwr_s0; --GB
end if;
end process;
end generate;
--
GEN_BYPASS2: if not INCLUDE_OPBOUT_PSTAGE generate
begin
sln_dbus_s2 <= sln_dbus_s1;
sln_xferack_s2 <= sln_xferack_s1;
sln_retry_s2 <= sln_retry_s1;
sln_errack_s2 <= sln_errack_s1;
sln_toutsup_s2 <= sln_toutsup_s1;
postedwrack_s2 <= postedwr_s0; --GB
end generate;
Sln_Dbus <= sln_dbus_s2;
-- Sln_xferAck <= sln_xferack_s2; --GB
-- Sln_retry <= sln_retry_s2; --GB
-- Sln_errAck <= sln_errack_s2; --GB
Sln_xferAck <= sln_xferack_s2 and OPB_Select; --GB
Sln_retry <= sln_retry_s2 and OPB_Select; --GB
Sln_errAck <= sln_errack_s2 and OPB_Select; --GB
Sln_toutSup <= sln_toutsup_s2;
------------------------------------------------------------------------------
-- Generation of devicesel_s0
-----------------------------------------------------------------------------
DEVICESEL_S0_I: pselect
generic map (
C_AB => K_DEV_ADDR_DECODE_WIDTH,
C_AW => C_AWIDTH,
C_BAR => C_ARD_ADDR_RANGE_ARRAY(0)
( C_ARD_ADDR_RANGE_ARRAY(0)'length-C_AWIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length-1
)
)
port map (
A => opb_abus_s0,
AValid => opb_select_s0,
CS => devicesel_s0
);
------------------------------------------------------------------------------
-- Determination of clock periods on which IPIC transactions are blocked
-- from starting, either because
-- (1) an acknowledged IPIC transaction is finishing and being cleared
-- from the pipeline, or
-- (2) the posted-write pipeline is filling.
-----------------------------------------------------------------------------
DELAYS_FOR_BLK_PROC : process (OPB_Clk) is
begin
if OPB_Clk'event and OPB_Clk='1' then
sln_xferack_s1_d1 <= sln_xferack_s1;
sln_xferack_s1_d2 <= sln_xferack_s1_d1;
opb_select_s0_d1 <= opb_select_s0;
new_select_s0_d1 <= new_select_s0;
opb_seqaddr_d1 <= OPB_seqAddr_eff;
last_xferack_d1 <= last_xferack;
last_xferack_d2 <= last_xferack_d1;
last_wr_xferack_d1 <= last_wr_xferack;
last_wr_xferack_d2 <= last_wr_xferack_d1;
bus2ip_cs_hit_s0_d1 <= bus2ip_cs_hit_s0;
last_pw_xferack_d1 <= last_pw_xferack; --GB
last_pw_xferack_d2 <= last_pw_xferack_d1; --GB
end if;
end process;
inh_cs_wnot_pw <= not (opb_rnw_s0 and OPB_seqAddr_s0) -- Do not inhibit
and -- when a burst read.
(
(sln_xferack_s1 and bo2sl(INCLUDE_IPIC_PSTAGE))
or
(sln_xferack_s1_d1 and bo2sl(INCLUDE_OPBIN_PSTAGE or
INCLUDE_OPBOUT_PSTAGE))
or (sln_xferack_s1_d2 and bo2sl(INCLUDE_OPBIN_PSTAGE and
INCLUDE_OPBOUT_PSTAGE))
);
INH_CS_WHEN_PW_GEN: for i in 0 to NUM_ARDS-1 generate
begin
new_select_s0(i) <= (bus2ip_cs_hit_s0(i) and not bus2ip_cs_hit_s0_d1(i))
or last_xferack_d1;
inh_cs_when_pw(i) <= (new_select_s0(i) and bo2sl(INCLUDE_OPBIN_PSTAGE or
INCLUDE_OPBOUT_PSTAGE))
or (new_select_s0_d1(i) and bo2sl(INCLUDE_OPBIN_PSTAGE and
INCLUDE_OPBOUT_PSTAGE));
end generate;
-- Modified to fix interrupt double wrce
-- last_xferack <= sln_xferack_s2 and not OPB_seqAddr_eff;
--
-- inh_xferack_when_pw <=
-- (last_xferack and bo2sl(INCLUDE_OPBOUT_PSTAGE))
-- or (last_xferack_d1 and bo2sl(INCLUDE_OPBIN_PSTAGE))
-- or (last_xferack_d2 and bo2sl(INCLUDE_OPBIN_PSTAGE and
-- INCLUDE_OPBOUT_PSTAGE));
last_xferack <= sln_xferack_s2 and not OPB_seqAddr_eff and not last_xferack_d1; --GB
POSTEDWRINH_PROC: process(reset2bus_postedwrinh, intr2bus_postedwrinh,
ip2bus_postedwrinh, bus2ip_cs_hit_s0,
opb_rnw_s0)
variable r : std_logic;
begin
r := '0';
for i in 0 to NUM_ARDS-1 loop
r := r or ( bus2ip_cs_hit_s0(i)
and not eff_ip2bus_val(
i => i,
rst => reset2bus_postedwrinh,
intr => intr2bus_postedwrinh,
user => ip2bus_postedwrinh(i)
)
);
end loop;
postedwr_s0 <= bo2sl(r='1' and not opb_rnw_s0='1');-- and C_DEV_BURST_ENABLE=1);
end process;
last_pw_xferack <= sln_xferack_s2 and not OPB_seqAddr_eff and postedwrack_s2;
inh_xferack_when_pw <=
bo2sl((last_pw_xferack='1' and (INCLUDE_OPBOUT_PSTAGE))
or (last_pw_xferack_d1='1' and (INCLUDE_OPBIN_PSTAGE or
INCLUDE_IPIC_PSTAGE))
or (last_pw_xferack_d2='1' and (INCLUDE_OPBIN_PSTAGE and
INCLUDE_IPIC_PSTAGE)) );
------------------------------------------------------------------------------
-- Generation of per-address-range mechanism.
------------------------------------------------------------------------------
PER_AR_GEN: for i in 0 to NUM_ARDS-1 generate
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,i);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= log2(C_ARD_NUM_CE_ARRAY(i));
constant OFFSET : integer
:= log2(C_ARD_DWIDTH_ARRAY(i)/8);
-- OFFSET gives the number of address bits corresponding to the
-- DWIDTH of the address range, e.g. zero for bytes, 1 for
-- doublets, 2 for quadlets, 3 for octlets, etc.
begin
--------------------------------------------------------------------------
-- CS decoders
--------------------------------------------------------------------------
CS_I: pselect
generic map (
C_AB => - K_DEV_ADDR_DECODE_WIDTH
+ num_decode_bits(C_ARD_ADDR_RANGE_ARRAY,
C_AWIDTH,
i),
C_AW => C_AWIDTH - K_DEV_ADDR_DECODE_WIDTH,
C_BAR => C_ARD_ADDR_RANGE_ARRAY(i*2)
( C_ARD_ADDR_RANGE_ARRAY(0)'length
- C_AWIDTH
+ K_DEV_ADDR_DECODE_WIDTH
to C_ARD_ADDR_RANGE_ARRAY(0)'length-1
)
)
port map (
A => opb_abus_s0(K_DEV_ADDR_DECODE_WIDTH to C_AWIDTH-1),
AValid => devicesel_s0,
CS => bus2ip_cs_hit_s0(i)
);
--
-- ToDo, pselect above and AND gate below can
-- be optimized later with a special pselect that
-- has outputs for both bus2ip_cs_s0 and bus2ip_cs_hit_s0.
--
bus2ip_cs_enable_s0(i) <= not inh_cs_wnot_pw
when C_DEV_BURST_ENABLE=0 or
opb_rnw_s0 = '1' or
eff_ip2bus_val(
i =>i,
rst =>reset2bus_postedwrinh,
intr=>intr2bus_postedwrinh,
user=>ip2bus_postedwrinh(i)
)='1'
else
not inh_cs_when_pw(i);
bus2ip_cs_s0(i) <= bus2ip_cs_hit_s0(i) and bus2ip_cs_enable_s0(i);
-------------------------------------------------------------------------
-- Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(i) - 1 generate
begin
----------------------------------------------------------------------
-- CE decoders
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1)
:= std_logic_vector(TO_UNSIGNED(j, CE_ADDR_SIZE));
begin
CE_I : pselect
generic map (
C_AB => CE_ADDR_SIZE,
C_AW => CE_ADDR_SIZE,
C_BAR => BAR
)
port map (
A => opb_abus_s0(C_AWIDTH - OFFSET - CE_ADDR_SIZE to
C_AWIDTH - OFFSET - 1),
AValid => bus2ip_cs_s0(i),
CS => bus2ip_ce_s0(CE_INDEX_START+j)
);
end generate;
--
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
bus2ip_ce_s0(CE_INDEX_START+j) <= bus2ip_cs_s0(i);
end generate;
--
----------------------------------------------------------------------
-- RdCE decoders
----------------------------------------------------------------------
bus2ip_rdce_s0(CE_INDEX_START+j) <=
bus2ip_ce_s0(CE_INDEX_START+j) and opb_rnw_s0;
----------------------------------------------------------------------
-- WrCE decoders
----------------------------------------------------------------------
bus2ip_wrce_s0(CE_INDEX_START+j) <=
bus2ip_ce_s0(CE_INDEX_START+j) and not opb_rnw_s0;
----------------------------------------------------------------------
end generate PER_CE_GEN;
end generate PER_AR_GEN;
------------------------------------------------------------------------------
-- This process selects the set of CS signals that activate a given bit of the
-- encoded size.
------------------------------------------------------------------------------
ENCODE_SIZE_BIT_SEL_PROC : process (bus2ip_cs_s0)
type NAT_ARRAY_TYPE is array(natural range <>) of natural;
variable next_bit : NAT_ARRAY_TYPE(0 to 2);
begin
next_bit := (others => 0);
for i in 0 to NUM_ARDS-1 loop
for j in 0 to NUM_ENCODED_SIZE_BITS-1 loop
if encoded_size_is_1(i,j) then
cs_to_or_for_dsize_bit(j)(next_bit(j)) <= bus2ip_cs_s0(i);
next_bit(j) := next_bit(j)+1;
end if;
end loop;
end loop;
end process;
------------------------------------------------------------------------------
-- This generates the encoded data size as a function of the address range
-- being addressed.
------------------------------------------------------------------------------
ENCODED_SIZE_CS_OR_GEN : for i in 0 to NUM_ENCODED_SIZE_BITS-1 generate
begin
----------------------------------------------------------------------------
-- If no address range requires the bit high, then fix it low.
----------------------------------------------------------------------------
ALWAYS_LOW_GEN : if num_cs_for_bit(i) = 0 generate
encoded_dsize_s0(i) <= '0';
end generate;
----------------------------------------------------------------------------
-- If all address ranges require the bit high, then fix it high.
----------------------------------------------------------------------------
ALWAYS_HIGH_GEN: if num_cs_for_bit(i) = NUM_ARDS generate
encoded_dsize_s0(i) <= '1';
end generate;
----------------------------------------------------------------------------
-- If some address ranges require the bit high, and other address ranges
-- require it low, then OR together the CS signals for the address ranges
-- that require it high.
----------------------------------------------------------------------------
SOMETIMES_HIGH_GEN: if num_cs_for_bit(i) /= 0 and
num_cs_for_bit(i) /= NUM_ARDS
generate
ENCODED_SIZE_OR : or_muxcy -- instance of carry-chain OR for each bit
generic map (
C_NUM_BITS => num_cs_for_bit(i)
)
port map (
In_bus => cs_to_or_for_dsize_bit(i)(0 to num_cs_for_bit(i)-1),
Or_out => encoded_dsize_s0(i)
);
end generate;
end generate;
------------------------------------------------------------------------------
-- Steer write data from appropriate data lanes if C_ARD_DWIDTH_ARRAY has
-- mixed width values.
------------------------------------------------------------------------------
I_STEER : IPIF_Steer
generic map(
C_DWIDTH => C_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_AWIDTH
)
port map (
Wr_Data_In => opb_dbus_s0,
Addr => opb_abus_s0,
BE_In => opb_be_s0,
Decode_size => encoded_dsize_s0,
Wr_Data_Out => bus2ip_data_s0,
BE_Out => bus2ip_be_s0,
--
-- Rd mirroring tied off, see I_MIRROR
Rd_Data_In => ZSLV(0 to C_DWIDTH-1),
Rd_Data_Out => open
);
------------------------------------------------------------------------------
-- Mirror read data to appropriate data lanes if C_ARD_DWIDTH_ARRAY has
-- mixed width values.
------------------------------------------------------------------------------
I_MIRROR : IPIF_Steer
generic map(
C_DWIDTH => C_DWIDTH,
C_SMALLEST => get_min_dwidth(C_ARD_DWIDTH_ARRAY),
C_AWIDTH => C_AWIDTH
)
port map (
Rd_Data_In => ip2bus_data_mx,
Decode_size => encoded_dsize_s1,
Addr => bus2ip_addr_s1,
Rd_Data_Out => sln_dbus_s1,
--
-- Wr steering tied off, see I_MIRROR
Wr_Data_In => ZSLV(0 to C_DWIDTH-1),
BE_In => ZSLV(0 to C_DWIDTH/8-1),
Wr_Data_Out => open,
BE_Out => open
);
------------------------------------------------------------------------------
-- Generation of sln_xferack.
------------------------------------------------------------------------------
SLN_XFERACK_PROC : process (bus2ip_cs_s1, bus2ip_cs_hit_s0,
opb_rnw_s0, inh_xferack_when_pw,
reset2bus_ack, intr2bus_ack,
reset2bus_postedwrinh, intr2bus_postedwrinh,
IP2Bus_Ack, IP2Bus_PostedWrInh) is
variable r : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
if (eff_ip2bus_val(i =>i,
rst =>reset2bus_postedwrinh,
intr=>intr2bus_postedwrinh,
user=>IP2Bus_PostedWrInh(i)
) or opb_rnw_s0
) = '1'
then -- This is the case where transactions are reads, or writes
-- that are not posted.
r := r or
(bus2ip_cs_s1(i) and
eff_ip2bus_val(i =>i,
rst =>reset2bus_ack,
intr=>intr2bus_ack,
user=>IP2Bus_Ack(i)
)
);
else -- This is the case where writes are posted.
r := r or
-- bus2ip_cs_hit_s0(i);
(bus2ip_cs_hit_s0(i) and bus2ip_cs_enable_s0(i)); --GB
end if;
end loop;
sln_xferack_s1 <= r and not(inh_xferack_when_pw);
end process;
------------------------------------------------------------------------------
-- Generation of sln_retry.
------------------------------------------------------------------------------
SLN_RETRY_PROC : process (bus2ip_cs_s1, IP2Bus_Retry, reset2bus_retry,
intr2bus_retry) is
variable r : std_logic;
variable ip2bus_retry_help : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_retry_help := reset2bus_retry;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_retry_help := intr2bus_retry;
else
ip2bus_retry_help := IP2Bus_Retry(i);
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_retry_help);
end loop;
sln_retry_s1 <= r;
end process;
------------------------------------------------------------------------------
-- Generation of sln_error.
------------------------------------------------------------------------------
SLN_ERRACK_PROC : process (bus2ip_cs_s1, IP2Bus_Error, reset2bus_error,
intr2bus_error) is
variable r : std_logic;
variable ip2bus_error_help : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_error_help := reset2bus_error;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_error_help := intr2bus_error;
else
ip2bus_error_help := IP2Bus_Error(i);
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_error_help);
end loop;
sln_errack_s1 <= r;
end process;
------------------------------------------------------------------------------
-- Generation of sln_toutsup.
------------------------------------------------------------------------------
SLN_TOUTSUP_PROC : process (bus2ip_cs_s1, IP2Bus_ToutSup, reset2bus_toutsup,
intr2bus_toutsup) is
variable r : std_logic;
variable ip2bus_toutsup_help : std_logic;
begin
r := '0';
for i in bus2ip_cs_s1'range loop
if INCLUDE_RESET_MIR and (i = RESET_MIR_CS_IDX) then
ip2bus_toutsup_help := reset2bus_toutsup;
elsif INCLUDE_INTR and (i = INTR_CS_IDX) then
ip2bus_toutsup_help := intr2bus_toutsup;
else
ip2bus_toutsup_help := IP2Bus_ToutSup(i);
end if;
r := r or (bus2ip_cs_s1(i) and ip2bus_toutsup_help);
end loop;
sln_toutsup_s1 <= r;
end process;
------------------------------------------------------------------------------
-- Generation of ip2bus_data_mx, as a function of IP2Bus_Data
-- and bus2ip_rdce, using carry chain logic.
-- Note, internal address ranges such as RESET_MIR or Interrupt Source
-- controller are multiplexed into the appropriate "slot".
------------------------------------------------------------------------------
READMUX_GEN : if not SINGLE_CE or not INCLUDE_OPBOUT_PSTAGE generate
begin
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
signal cry : std_logic_vector(0 to (Bus2IP_RdCE'length + 1)/2);
begin
cry(0) <= '0';
PER_CE_PAIR_GEN : for j in 0 to (Bus2IP_RdCE'length + 1)/2-1 generate
signal ip2bus_data_rmmx0 : std_logic_vector(0 to C_DWIDTH-1);
signal ip2bus_data_rmmx1 : std_logic_vector(0 to C_DWIDTH-1);
signal lut_out : std_logic;
constant nopad : boolean := (j /= (Bus2IP_RdCE'length + 1)/2-1) or
(Bus2IP_RdCE'length mod 2 = 0);
begin
-----------------------------------------------------------------------
-- ToDo, the read-back mux can be optimized to exclude any data bits
-- that are not present in AR with DWIDTH less than C_DWIDTH...
-- possibly also for bits that are known to be not implemented, e.g.
-- a register that doesn't use all bit positions or is write-only.
-----------------------------------------------------------------------
-- LUT (last LUT may multiplex one data bit instead of two)
-----------------------------------------------------------------------
-- WOPAD : if nopad generate
-- signal ip2bus_data_rmmx0 : std_logic_vector(0 to C_DWIDTH-1);
-- signal ip2bus_data_rmmx1 : std_logic_vector(0 to C_DWIDTH-1);
-- begin
-------------------------------------------------------------------
-- Always include the first of two possilble mux channels thru LUT.
-------------------------------------------------------------------
ip2bus_data_rmmx0 <=
----------------------------------------------
-- RESET_MIR
----------------------------------------------
reset2bus_data
when INCLUDE_RESET_MIR and
(2*j = RESET_MIR_CE_IDX)
else
----------------------------------------------
-- INTR -- ToDo, this is inefficient because
-- interrupt_control already multiplexes
-- the data. Optimize later.
----------------------------------------------
intr2bus_data
when INCLUDE_INTR and
(2*j >= INTR_CE_LO) and
(2*j <= INTR_CE_HI)
else
----------------------------------------------
-- IP Core
----------------------------------------------
IP2Bus_Data((2*j )*C_DWIDTH to
(2*j+1)*C_DWIDTH-1);
-------------------------------------------------------------------
-- Don't include second channel when odd number and on last LUT.
-------------------------------------------------------------------
WOPAD : if nopad generate
begin
ip2bus_data_rmmx1 <=
----------------------------------------------
-- RESET_MIR
----------------------------------------------
reset2bus_data
when INCLUDE_RESET_MIR and
(2*j+1 = RESET_MIR_CE_IDX)
else
----------------------------------------------
-- INTR
----------------------------------------------
intr2bus_data
when INCLUDE_INTR and
(2*j+1 >= INTR_CE_LO) and
(2*j+1 <= INTR_CE_HI)
else
----------------------------------------------
-- IP Core
----------------------------------------------
IP2Bus_Data((2*j+1)*C_DWIDTH to
(2*j+2)*C_DWIDTH-1);
lut_out <= not (
(ip2bus_data_rmmx0(i) and bus2ip_rdce_s1(2*j )) or
(ip2bus_data_rmmx1(i) and bus2ip_rdce_s1(2*j+1)));
end generate;
WIPAD : if not nopad generate
lut_out <= not (
(ip2bus_data_rmmx0(i) and bus2ip_rdce_s1(2*j )));
end generate;
-----------------------------------------------------------------------
-- MUXCY
-----------------------------------------------------------------------
I_MUXCY : MUXCY
port map (
O => cry(j+1),
CI => cry(j),
DI => '1',
S => lut_out
);
end generate;
ip2bus_data_mx(i) <= cry((Bus2IP_RdCE'length + 1)/2);
end generate;
end generate;
--
--
READMUX_SINGLE_CE_GEN : if SINGLE_CE and INCLUDE_OPBOUT_PSTAGE generate
begin
ip2bus_data_mx <= ip2bus_data;
end generate;
EXCLUDE_RESET_MIR_GEN : if not INCLUDE_RESET_MIR generate
begin
bus2ip_reset_i <= Reset;
end generate;
--
INCLUDE_RESET_MIR_GEN : if INCLUDE_RESET_MIR generate
begin
RESET_MIR_I0 : reset_mir
Generic map (
C_DWIDTH => C_DWIDTH,
C_INCLUDE_SW_RST => 1,
C_INCLUDE_MIR => C_DEV_MIR_ENABLE,
C_MIR_MAJOR_VERSION => MIR_MAJOR_VERSION,
C_MIR_MINOR_VERSION => MIR_MINOR_VERSION,
C_MIR_REVISION => MIR_REVISION,
C_MIR_BLK_ID => C_DEV_BLK_ID,
C_MIR_TYPE => MIR_TYPE
)
port map (
Reset => Reset,
Bus2IP_Clk => bus2ip_clk_i,
SW_Reset_WrCE => bus2ip_wrce_s1(RESET_MIR_CE_IDX),
Bus2IP_Data => bus2ip_data_s1,
Bus2IP_Reset => bus2ip_reset_i,
Reset2Bus_Data => reset2bus_data,
Reset2Bus_Ack => reset2bus_ack,
Reset2Bus_Error => reset2bus_error,
Reset2Bus_Retry => reset2bus_retry,
Reset2Bus_ToutSup => reset2bus_toutsup
);
end generate;
Bus2IP_Reset <= bus2ip_reset_i;
INTR_CTRLR_GEN : if INCLUDE_INTR generate
constant NUM_IPIF_IRPT_SRC : natural := 4;
signal ERRACK_RESERVED: std_logic_vector(0 to 1);
begin
ERRACK_RESERVED <= Sln_errack_s2 & '0';
INTERRUPT_CONTROL_I : interrupt_control
generic map (
C_INTERRUPT_REG_NUM => number_CEs_for(IPIF_INTR),
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => C_INCLUDE_DEV_IID = 1,
C_INCLUDE_DEV_ISC => C_INCLUDE_DEV_ISC = 1,
C_IRPT_DBUS_WIDTH => C_DWIDTH
)
port map (
Bus2IP_Clk_i => bus2ip_clk_i,
Bus2IP_Data_sa => bus2ip_data_s1,
Bus2IP_RdReq_sa => '0',
Bus2IP_Reset_i => bus2ip_reset_i,
Bus2IP_WrReq_sa => '0',
Interrupt_RdCE => bus2ip_rdce_s1(INTR_CE_LO to INTR_CE_HI),
Interrupt_WrCE => bus2ip_wrce_s1(INTR_CE_LO to INTR_CE_HI),
IPIF_Reg_Interrupts => ERRACK_RESERVED,
IPIF_Lvl_Interrupts => ZERO_SLV(0 to NUM_IPIF_IRPT_SRC-1),
IP2Bus_IntrEvent => IP2Bus_Intr,
Intr2Bus_DevIntr => Device_Intr,
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error, -- These are tied low in block
Intr2Bus_Retry => intr2bus_retry, --
Intr2Bus_ToutSup => intr2bus_toutsup --
);
end generate;
--intr2bus_ack <= '1'; -- interrupt control acknowledges in same cycle as
-- -- the RdCE or WrCE, so ack can be tied high.
intr2bus_ack <= intr2bus_rdack or intr2bus_wrack;
end implementation;
| bsd-3-clause | 837827df7936771fab1f248f8494bbb0 | 0.449822 | 4.02212 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_thread_manager_v1_00_a/hdl/vhdl/user_logic.vhd | 9 | 57,513 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
--
-- Title Thread Manager
--
-- 26 Jul 2004: Mike Finley: Original author
-- 08 Jun 2005: Erik Anderson: Changes for new interface between TM and
-- Scheduler. Also adding function isQueue().
-- 15 Apr 2009: Jim Stevens: Ported to PLB version 4.6.
--
---------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_CS -- Bus to IP chip select
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
C_RESET_TIMEOUT : natural := 4096
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_CS : in std_logic_vector(0 to 0);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
Access_Intr : out std_logic;
Scheduler_Reset : out std_logic;
Scheduler_Reset_Done : in std_logic;
Semaphore_Reset : out std_logic;
Semaphore_Reset_Done : in std_logic;
SpinLock_Reset : out std_logic;
SpinLock_Reset_Done : in std_logic;
User_IP_Reset : out std_logic;
User_IP_Reset_Done : in std_logic;
Soft_Stop : out std_logic;
tm2sch_cpu_thread_id : out std_logic_vector(0 to 7);
tm2sch_opcode : out std_logic_vector(0 to 5);
tm2sch_data : out std_logic_vector(0 to 7);
tm2sch_request : out std_logic;
tm2sch_DOB : out std_logic_vector(0 to 31);
sch2tm_ADDRB : in std_logic_vector(0 to 8);
sch2tm_DIB : in std_logic_vector(0 to 31);
sch2tm_ENB : in std_logic;
sch2tm_WEB : in std_logic;
sch2tm_busy : in std_logic;
sch2tm_data : in std_logic_vector(0 to 7);
sch2tm_next_id : in std_logic_vector(0 to 7);
sch2tm_next_id_valid : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
-- Define the memory map for each register, Address[16 to 21]
--
constant C_CLEAR_THREAD : std_logic_vector(0 to 5) := "000000";
constant C_JOIN_THREAD : std_logic_vector(0 to 5) := "000001";
constant C_READ_THREAD : std_logic_vector(0 to 5) := "000011";
constant C_ADD_THREAD : std_logic_vector(0 to 5) := "000100";
constant C_CREATE_THREAD_J : std_logic_vector(0 to 5) := "000101";
constant C_CREATE_THREAD_D : std_logic_vector(0 to 5) := "000110";
constant C_EXIT_THREAD : std_logic_vector(0 to 5) := "000111";
constant C_NEXT_THREAD : std_logic_vector(0 to 5) := "001000";
constant C_YIELD_THREAD : std_logic_vector(0 to 5) := "001001";
constant C_CURRENT_THREAD : std_logic_vector(0 to 5) := "010000";
constant C_IS_DETACHED : std_logic_vector(0 to 5) := "011000";
constant C_IS_QUEUED : std_logic_vector(0 to 5) := "011001";
constant C_EXCEPTION_ADDR : std_logic_vector(0 to 5) := "010011";
constant C_EXCEPTION_REG : std_logic_vector(0 to 5) := "010100";
constant C_SOFT_START : std_logic_vector(0 to 5) := "010101";
constant C_SOFT_STOP : std_logic_vector(0 to 5) := "010110";
constant C_SOFT_RESET : std_logic_vector(0 to 5) := "010111";
constant C_SCHED_LINES : std_logic_vector(0 to 5) := "011010";
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
constant OPCODE_IS_QUEUED : std_logic_vector(0 to 5) := "000001";
constant OPCODE_ENQUEUE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DEQUEUE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_IS_EMPTY : std_logic_vector(0 to 5) := "000110";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant H32 : std_logic_vector(0 to 31) := (others => '1');
constant MAX_QUEUE_SIZE : std_logic_vector(0 to 7) := (others => '1');
constant TOUT_CYCLES : natural := 3; -- assert timeout suppress
signal cycle_count : std_logic_vector(0 to 15);
signal timeout_expired : std_logic;
-- Extended Thread Error Codes returned in lower 4 bits
constant ERROR_IN_STATUS : std_logic_vector(0 to 3) := "0001";
constant THREAD_ALREADY_TERMINATED : std_logic_vector(0 to 3) := "0011";
constant THREAD_ALREADY_QUEUED : std_logic_vector(0 to 3) := "0101";
constant ERROR_FROM_SCHEDULER : std_logic_vector(0 to 3) := "0111";
constant JOIN_ERROR_CHILD_JOINED : std_logic_vector(0 to 3) := "1001";
constant JOIN_ERROR_NOT_CHILD : std_logic_vector(0 to 3) := "1011";
constant JOIN_ERROR_CHILD_DETACHED : std_logic_vector(0 to 3) := "1101";
constant JOIN_ERROR_CHILD_NOT_USED : std_logic_vector(0 to 3) := "1111";
constant JOIN_ERROR_UNKNOWN : std_logic_vector(0 to 3) := "0001";
constant CLEAR_ERROR_NOT_USED : std_logic_vector(0 to 3) := "1001";
-- Exception "cause" returned in Exception register
constant EXCEPTION_WRITE_TO_READ_ONLY : std_logic_vector(0 to 3) := "0001";
constant EXCEPTION_UNDEFINED_ADDRESS : std_logic_vector(0 to 3) := "0010";
constant EXCEPTION_TO_SOFT_RESET : std_logic_vector(0 to 3) := "0011";
constant EXCEPTION_TO_SCHD_ISQUEUED : std_logic_vector(0 to 3) := "0100";
constant EXCEPTION_TO_SCHD_ENQUEUE : std_logic_vector(0 to 3) := "0101";
constant EXCEPTION_TO_SCHD_DEQUEUE : std_logic_vector(0 to 3) := "0110";
constant EXCEPTION_TO_SCHD_ISEMPTY : std_logic_vector(0 to 3) := "0111";
constant EXCEPTION_TO_SCHD_NEXT_THREAD : std_logic_vector(0 to 3) := "1000";
constant EXCEPTION_SCHD_INVALID_THREAD : std_logic_vector(0 to 3) := "1001";
constant EXCEPTION_ILLEGAL_STATE : std_logic_vector(0 to 3) := "1111";
-- BRAM constants
constant BRAM_ADDRESS_BITS : integer := 9;
constant BRAM_DATA_BITS : integer := 32;
-- Address,Cause for access exceptions
--
signal Exception_Address : std_logic_vector(0 to 31);
signal Exception_Address_next : std_logic_vector(0 to 31);
signal Exception_Cause : std_logic_vector(0 to 3);
signal Exception_Cause_next : std_logic_vector(0 to 3);
signal access_error : std_logic;
-- Debug control signals
--
-- Soft reset signals, LSB = SWTM reset; reset IP(s) if '1'
-- Resets done, handshake from IPs if done resetting(1)
-- core_stop , halt state machines at next appropriate point if '1'
--
signal soft_resets : std_logic_vector(0 to 4);
signal soft_resets_next : std_logic_vector(0 to 4);
signal resets_done : std_logic_vector(0 to 4);
signal reset_status : std_logic_vector(0 to 4);
signal reset_status_next : std_logic_vector(0 to 4);
signal core_stop : std_logic;
signal core_stop_next : std_logic;
-- Declarations for each register
-- Current thread,Idle thread : bits 0..7 = ID, bit 8 = '1' = invalid
signal current_cpu_thread : std_logic_vector(0 to 8);
signal current_cpu_thread_next : std_logic_vector(0 to 8);
-- internal signals
signal next_ID : std_logic_vector(0 to 8);
signal next_ID_next : std_logic_vector(0 to 8);
signal temp_thread_id : std_logic_vector(0 to 7);
signal temp_thread_id_next : std_logic_vector(0 to 7);
signal temp_thread_id2 : std_logic_vector(0 to 7);
signal temp_thread_id2_next : std_logic_vector(0 to 7);
signal reset_ID : std_logic_vector(0 to 8);
type swtm_state_type is
(IDLE_STATE,
SOFT_RESET_WRITE_INIT,
SOFT_RESET_INIT_TABLE,
SOFT_RESET_WAIT,
READ_THREAD_INIT,
READ_THREAD_RD_WAIT,
READ_THREAD_DONE,
CREATE_THREAD_INIT,
CT_NEW_ID_RD_WAIT,
CT_NEW_ID_AVAILABLE,
CT_ENTRY_RD_WAIT,
CT_ENTRY_AVAILABLE,
CT_DONE,
CLEAR_THREAD_INIT,
CLEAR_ENTRY_RD_WAIT,
CLEAR_ENTRY_AVAIABLE,
DEALLOCATE_ID,
DEALLOCATE_NEXT_ENTRY_RD_WAIT,
DEALLOCATE_NEXT_ENTRY_AVAIL,
JOIN_THREAD_INIT,
JOIN_RD_ENTRY_RD_WAIT,
JOIN_RD_ENTRY_AVAILABLE,
IS_QUEUED_INIT,
IS_QUEUED_DONE,
IS_DETACHED_THREAD_INIT,
IS_DETACHED_ENTRY_RD_WAIT,
IS_DETACHED_ENTRY_AVAILABLE,
NEXT_THREAD_INIT,
NEXT_THREAD_WAIT4_SCHEDULER,
NEXT_THREAD_RD_WAIT,
NEXT_THREAD_AVAILABLE,
NEXT_THREAD_CHECK_DEQUEUE,
ADD_THREAD_INIT,
AT_ENTRY_RD_WAIT,
AT_ENTRY_AVAILABLE,
AT_ISQUEUED_WAIT,
AT_CHECK_ISQUEUE,
AT_ENQUEUE_WAIT,
AT_CHECK_ENQUEUE,
ISQUEUED_WAIT_ACK,
ISQUEUED_WAIT_COMPLETE,
ENQUEUE_WAIT_ACK,
ENQUEUE_WAIT_COMPLETE,
DEQUEUE_WAIT_ACK,
DEQUEUE_WAIT_COMPLETE,
IS_QUEUE_EMPTY_WAIT_ACK,
IS_QUEUE_EMPTY_WAIT_COMPLETE,
YIELD_THREAD_INIT,
YIELD_CURRENT_THREAD_RD_WAIT,
YIELD_CURRENT_THREAD_AVAILABLE,
YIELD_CHECK_QUEUE_EMPTY,
YIELD_ENQUEUE,
YIELD_CHECK_ENQUEUE,
-- YIELD_dummy_is_queued,
YIELD_DEQUEUE,
YIELD_CHECK_DEQUEUE,
EXIT_THREAD_INIT,
EXIT_THREAD_RD_WAIT,
EXIT_THREAD_AVAIABLE,
EXIT_DEALLOCATE,
EXIT_NEXT_THREAD_RD_WAIT,
EXIT_NEXT_THREAD_AVAILABLE,
EXIT_READ_PARENT,
EXIT_READ_PARENT_WAIT,
EXIT_READ_PARENT_AVAILABLE,
EXIT_CHECK_ENQUEUE,
RAISE_EXCEPTION,
END_TRANSACTION,
END_TRANSACTION_WAIT);
signal current_state, next_state : swtm_state_type := IDLE_STATE;
signal return_state, return_state_next : swtm_state_type := IDLE_STATE;
signal bus_data_out : std_logic_vector(0 to 31);
signal bus_data_out_next : std_logic_vector(0 to 31);
signal current_status : std_logic_vector(0 to 31);
signal current_status_next : std_logic_vector(0 to 31);
signal Swtm_Reset_Done : std_logic;
signal Swtm_Reset_Done_next : std_logic;
signal new_ID : std_logic_vector(0 to 7);
signal new_ID_next : std_logic_vector(0 to 7);
signal tm2sch_request_next : std_logic;
signal tm2sch_request_reg : std_logic;
signal tm2sch_data_next : std_logic_vector(0 to 7);
signal tm2sch_data_reg : std_logic_vector(0 to 7);
signal tm2sch_opcode_next : std_logic_vector(0 to 5);
signal tm2sch_opcode_reg : std_logic_vector(0 to 5);
-- Signals for thread table BRAM
signal ENA : std_logic;
signal WEA : std_logic;
signal ADDRA : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1);
signal DIA : std_logic_vector(0 to BRAM_DATA_BITS - 1);
signal DOA : std_logic_vector(0 to BRAM_DATA_BITS - 1);
alias addr :std_logic_vector(0 to 5) is Bus2IP_Addr(16 to 21);
---------------------------------------------------------------------------
-- Component Instantiation of inferred dual ported block RAM
---------------------------------------------------------------------------
component infer_bram_dual_port is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1);
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIB : in std_logic_vector(0 to DATA_BITS - 1);
DOB : out std_logic_vector(0 to DATA_BITS - 1)
);
end component infer_bram_dual_port;
-------------------------------------------------------------------
-- ICON core signal declarations
-------------------------------------------------------------------
signal control0 : std_logic_vector(35 downto 0);
signal my_ack, my_tout_sup, my_error, my_sched_req : std_logic; -- TODO: This line might be gone.
signal my_counter : std_logic_vector(0 to 31);
-------------------------------------------------------------------
-- ICON core component declaration
-------------------------------------------------------------------
-- simulation translate_off
--component chipscope_icon_v1_03_a
-- port
-- (
-- control0 : out std_logic_vector(35 downto 0)
-- );
--end component;
-- simulation translate_on
-------------------------------------------------------------------
-- ILA core component declaration
-------------------------------------------------------------------
-- simulation translate_off
--component chipscope_ila_v1_02_a
-- port
-- (
--- control : in std_logic_vector(35 downto 0);
-- clk : in std_logic;
-- trig0 : in std_logic_vector(63 downto 0);
-- trig1 : in std_logic_vector(63 downto 0);
-- trig2 : in std_logic_vector(31 downto 0);
-- trig3 : in std_logic_vector(31 downto 0);
-- trig4 : in std_logic_vector(15 downto 0)
-- );
--end component;
-- simulation translate_on
begin
thread_table_bram : infer_bram_dual_port
generic map (
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map (
CLKA => Bus2IP_Clk,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DIA => DIA,
DOA => DOA,
CLKB => Bus2IP_Clk,
ENB => sch2tm_ENB,
WEB => sch2tm_WEB,
ADDRB => sch2tm_ADDRB,
DIB => sch2tm_DIB,
DOB => tm2sch_DOB
);
tm2sch_opcode <= tm2sch_opcode_reg;
tm2sch_data <= tm2sch_data_reg;
tm2sch_request <= tm2sch_request_reg;
Soft_Stop <= core_stop;
Scheduler_Reset <= soft_resets(3);
Semaphore_Reset <= soft_resets(2);
SpinLock_Reset <= soft_resets(1);
User_IP_Reset <= soft_resets(0);
Access_Intr <= access_error;
CYCLE_PROC : process (Bus2IP_Clk, Bus2IP_CS) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk='1' ) then
if( Bus2IP_CS(0) = '0' ) then
cycle_count <= (others => '0');
else
cycle_count <= cycle_count + 1;
end if;
end if;
end process CYCLE_PROC;
--
-- create a counter for the number of elapsed cycles
-- in each bus transaction.
-- assert TimeOut suppress when count = TOUT_CYCLES
--
CYCLE_CONTROL : process( cycle_count ) is
begin
IP2Bus_Error <= '0'; -- no error
--
-- count the number of elapsed clock cycles in transaction
--
if cycle_count < C_RESET_TIMEOUT then
timeout_expired <= '0';
else
--timeout_expired <= '1';
timeout_expired <= '0'; -- Disable timeouts.
end if;
--
-- activate time out suppress if count exceeds TOUT_CYCLES
-- edk. Why isn't this done inside the clk_event ???
--
-- if cycle_count > TOUT_CYCLES then
-- --IP2Bus_ToutSup <= '1'; -- halt time out counter
-- my_tout_sup <= '1'; -- halt time out counter
-- else
-- --IP2Bus_ToutSup <= '0'; -- release
-- my_tout_sup <= '0'; -- release
-- end if;
end process CYCLE_CONTROL;
-- IP2Bus_ToutSup <= my_tout_sup;
RESET_PROC : process (Bus2IP_Clk, addr, current_state)
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( addr = C_SOFT_RESET and current_state = SOFT_RESET_WRITE_INIT ) then
reset_ID <= (others => '0');
else
reset_ID <= reset_ID + 1;
end if;
end if;
end process;
ACK_PROC : process(my_ack, Bus2IP_RdCE, Bus2IP_WrCE)
begin
if (Bus2IP_RdCE(0) = '1') then
IP2Bus_RdAck <= my_ack;
else
IP2Bus_RdAck <= '0';
end if;
if (Bus2IP_WrCE(0) = '1') then
IP2Bus_WrAck <= my_ack;
else
IP2Bus_WrAck <= '0';
end if;
end process;
SWTM_STATE_PROC : process (Bus2IP_Clk, core_stop_next, new_ID_next, next_ID_next, temp_thread_id_next, temp_thread_id2_next, current_cpu_thread_next, Current_status_next, soft_resets_next, reset_status_next, Swtm_Reset_Done_next, Scheduler_Reset_Done, Semaphore_Reset_Done, SpinLock_Reset_Done, User_IP_Reset_Done, next_state, return_state_next, Bus2IP_Reset,Exception_Cause_next) is
begin
if (Bus2IP_Clk'event and (Bus2IP_Clk = '1')) then
core_stop <= core_stop_next;
new_ID <= new_ID_next;
next_ID <= next_ID_next;
temp_thread_id <= temp_thread_id_next;
temp_thread_id2 <= temp_thread_id2_next;
current_cpu_thread <= current_cpu_thread_next;
tm2sch_cpu_thread_id <= current_cpu_thread_next(0 to 7);
tm2sch_data_reg <= tm2sch_data_next;
tm2sch_opcode_reg <= tm2sch_opcode_next;
tm2sch_request_reg <= tm2sch_request_next;
current_status <= current_status_next;
Exception_Address <= Exception_Address_next;
Exception_Cause <= Exception_Cause_next;
soft_resets <= soft_resets_next;
reset_status <= reset_status_next;
bus_data_out <= bus_data_out_next;
Swtm_Reset_Done <= Swtm_Reset_Done_next;
resets_done(4) <= Swtm_Reset_Done_next;
resets_done(3) <= Scheduler_Reset_Done;
resets_done(2) <= Semaphore_Reset_Done;
resets_done(1) <= SpinLock_Reset_Done;
resets_done(0) <= User_IP_Reset_Done;
return_state <= return_state_next;
if( Bus2IP_Reset = '1' ) then
current_state <= IDLE_STATE;
else
current_state <= next_state;
end if;
end if;
end process SWTM_STATE_PROC;
-- IP2Bus_Ack <= my_ack; -- pulse(010) to end bus transaction
SWTM_LOGIC_PROC : process (current_state, core_stop, new_ID, next_ID, current_cpu_thread, current_status, reset_status, Swtm_Reset_Done, soft_resets, Bus2IP_Addr, Bus2IP_Data, Exception_Address, Bus2IP_WrCE, addr, Bus2IP_RdCE, reset_ID, resets_done, timeout_expired, DOA, sch2tm_next_id_valid, sch2tm_next_id, sch2tm_busy, bus_data_out, Exception_Cause, tm2sch_request_reg, tm2sch_data_reg, tm2sch_opcode_reg, temp_thread_id, temp_thread_id2) is
begin
-- -------------------------------------------------
-- default output signal assignments
-- -------------------------------------------------
my_ack <= '0'; -- pulse(010) to end bus transaction
access_error <= '0'; -- pulse(010) for access error interrupt
IP2Bus_Data <= (others => '0');
ADDRA <= (others => '0');
ENA <= '0';
WEA <= '0';
DIA <= (others => '0');
-- -------------------------------------------------
-- default register assignments
-- -------------------------------------------------
next_state <= current_state;
return_state_next <= return_state;
core_stop_next <= core_stop;
new_ID_next <= new_ID;
next_ID_next <= next_ID;
temp_thread_id_next <= temp_thread_id;
temp_thread_id2_next <= temp_thread_id2;
current_cpu_thread_next <= current_cpu_thread;
current_status_next <= current_status;
Exception_Address_next <= Exception_Address;
reset_status_next <= reset_status;
Swtm_Reset_Done_next <= Swtm_Reset_Done;
Exception_Cause_next <= Exception_Cause;
tm2sch_request_next <= tm2sch_request_reg;
tm2sch_data_next <= tm2sch_data_reg;
tm2sch_opcode_next <= tm2sch_opcode_reg;
bus_data_out_next <= bus_data_out;
soft_resets_next <= soft_resets;
case current_state is
-- Command (addr) decode whenever we are waiting for something new to do.
when IDLE_STATE =>
bus_data_out_next <= (others => '0');
if (Bus2IP_WrCE(0) = '1') then
case addr is
when C_SOFT_START =>
-- Any write to soft_start address clears
-- all soft reset signals and the Soft_Stop signal
soft_resets_next <= (others => '0');
swtm_reset_done_next <= '0'; -- clear SWTM's reset done
core_stop_next <= '0'; -- clear core_stop
next_state <= END_TRANSACTION;
when C_SOFT_STOP =>
-- write any data to Soft_Stop to assert the Soft_Stop signal
core_stop_next <= '1';
next_state <= END_TRANSACTION;
when C_SOFT_RESET =>
next_state <= SOFT_RESET_WRITE_INIT;
when C_READ_THREAD =>
if (core_stop = '1') then
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
WEA <= '1';
ENA <= '1';
DIA <= Bus2IP_Data(0 to 31);
next_state <= END_TRANSACTION;
else
Exception_Cause_next <= EXCEPTION_WRITE_TO_READ_ONLY;
next_state <= RAISE_EXCEPTION;
end if;
when others =>
Exception_Cause_next <= EXCEPTION_UNDEFINED_ADDRESS;
next_state <= RAISE_EXCEPTION;
end case;
elsif (Bus2IP_RdCE(0) = '1') then
case addr is
when C_SOFT_START =>
bus_data_out_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_SOFT_STOP =>
-- returns signal level in LSB on read
bus_data_out_next <= Z32(0 to 30) & core_stop;
next_state <= END_TRANSACTION;
when C_SOFT_RESET =>
-- returns 1's in bit positions that failed
bus_data_out_next <= Z32(0 to 26) & reset_status;
next_state <= END_TRANSACTION;
when C_CURRENT_THREAD =>
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread;
next_state <= END_TRANSACTION;
when C_EXCEPTION_ADDR =>
bus_data_out_next <= Exception_Address;
Exception_Address_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_EXCEPTION_REG =>
bus_data_out_next <= Z32(0 to 27) & Exception_Cause;
Exception_Cause_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_SCHED_LINES =>
bus_data_out_next <= Z32(0 to 6) & sch2tm_busy & sch2tm_data &
Z32(16 to 22) & sch2tm_next_id_valid &
sch2tm_next_id;
next_state <= END_TRANSACTION;
when C_READ_THREAD => next_state <= READ_THREAD_INIT;
when C_CREATE_THREAD_D => next_state <= CREATE_THREAD_INIT;
when C_CREATE_THREAD_J => next_state <= CREATE_THREAD_INIT;
when C_CLEAR_THREAD => next_state <= CLEAR_THREAD_INIT;
when C_JOIN_THREAD => next_state <= JOIN_THREAD_INIT;
when C_IS_DETACHED => next_state <= IS_DETACHED_THREAD_INIT;
when C_IS_QUEUED => next_state <= IS_QUEUED_INIT;
when C_NEXT_THREAD => next_state <= NEXT_THREAD_INIT;
when C_ADD_THREAD => next_state <= ADD_THREAD_INIT;
when C_YIELD_THREAD => next_state <= YIELD_THREAD_INIT;
when C_EXIT_THREAD => next_state <= EXIT_THREAD_INIT;
when others =>
Exception_Cause_next <= EXCEPTION_UNDEFINED_ADDRESS;
next_state <= RAISE_EXCEPTION;
end case;
end if;
--
-- read/write to the soft resets register (1 bit per IP)
-- write '1' to reset, reads '1' if timeout error occured
-- before IP reports finished
--
-- SW Thread Manager = bit#4 (LSB)
-- Scheduler = bit#3
-- Semaphore = bit#2
-- SpinLock = bit#1
-- User_IP = bit#0
--
when SOFT_RESET_WRITE_INIT =>
soft_resets_next <= Bus2IP_Data(27 to 31);
reset_status_next <= (others => '0');
swtm_reset_done_next <= '0'; -- clear SWTM's reset_done
if (Bus2IP_Data(31) = '1') then -- soft_resets(4)
--
-- perform a soft reset on SWTM
--
bus_data_out_next <= (others => '0');
new_ID_next <= (others => '0');
next_ID_next <= (others => '0');
temp_thread_id_next <= (others => '0');
current_cpu_thread_next <= Z32(0 to 7) & '1';
core_stop_next <= '0';
tm2sch_opcode_next <= OPCODE_NOOP;
tm2sch_data_next <= (others => '0');
tm2sch_request_next <= '0';
next_state <= SOFT_RESET_INIT_TABLE;
else
next_state <= SOFT_RESET_WAIT;
end if;
-- initialize the thread ID table to all zeros
-- and the next available stack to 0..255
when SOFT_RESET_INIT_TABLE =>
ADDRA <= reset_ID;
ENA <= '1';
WEA <= '1';
if( reset_ID(0) = '0' ) then
-- init available ID stack & thread ID table
DIA <= reset_ID(1 to 8) & Z32(0 to 23);
else
-- clear 2nd half of table (unused)
DIA <= Z32(0 to 31);
end if;
if( reset_ID = H32(0 to 8) ) then
swtm_reset_done_next<= '1'; -- done
next_state <= soft_reset_wait;
end if;
-- wait for all IPs to finish initialization or
-- the maximum time to be exceeded then
-- ack to finish transaction
when SOFT_RESET_WAIT =>
if (resets_done = soft_resets) then -- done
next_state <= END_TRANSACTION;
elsif (timeout_expired = '1') then
reset_status_next <= (resets_done xor soft_resets);
Exception_Cause_next <= EXCEPTION_TO_SOFT_RESET;
next_state <= RAISE_EXCEPTION; -- timeout
else
next_state <= current_state;
end if;
when READ_THREAD_INIT =>
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
WEA <= '0';
ENA <= '1';
next_state <= READ_THREAD_RD_WAIT;
when READ_THREAD_RD_WAIT =>
next_state <= READ_THREAD_DONE;
when READ_THREAD_DONE =>
bus_data_out_next <= DOA;
next_state <= END_TRANSACTION;
when CREATE_THREAD_INIT =>
if next_ID(0) = '1' then
-- no IDs available, return with error bit set
--
bus_data_out_next <= Z32(0 to 30) & '1';
next_state <= END_TRANSACTION;
else
-- read next ID from stack
--
ADDRA <= next_ID;
ENA <= '1';
next_state <= CT_NEW_ID_RD_WAIT;
end if;
when CT_NEW_ID_RD_WAIT =>
next_state <= CT_NEW_ID_AVAILABLE;
when CT_NEW_ID_AVAILABLE =>
new_ID_next <= DOA(0 to 7); -- save new ID#
ADDRA <= '0' & DOA(0 to 7); -- point to new thread
ENA <= '1';
next_state <= CT_ENTRY_RD_WAIT;
when CT_ENTRY_RD_WAIT =>
next_state <= CT_ENTRY_AVAILABLE;
when CT_ENTRY_AVAILABLE =>
ADDRA <= '0' & new_ID;
ENA <= '1';
WEA <= '1'; -- enable write to bram
-- Determine if the thread to create is DETACHED / JOINABLE
if addr = C_CREATE_THREAD_D then -- set new thread status
-- create detached
DIA <= DOA(0 to 7) & Z32(0 to 7) &
Z32(0 to 7) & "1011" & Z32(0 to 3);
else
-- create joinable
DIA <= DOA(0 to 7) & Z32(0 to 7) &
current_cpu_thread(0 to 7) & "0011" & Z32(0 to 3);
end if;
next_state <= CT_DONE;
when CT_DONE =>
-- return new ID with no error,
bus_data_out_next <= Z32(0 to 22) & new_ID & '0';
-- point to next available ID
next_ID_next <= next_ID + 1;
next_state <= END_TRANSACTION;
when CLEAR_THREAD_INIT =>
-- clear the encoded thread ID if it is used and exited
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= CLEAR_ENTRY_RD_WAIT;
when CLEAR_ENTRY_RD_WAIT =>
next_state <= CLEAR_ENTRY_AVAIABLE ;
when CLEAR_ENTRY_AVAIABLE =>
if (DOA(26 to 27) = "10") then -- used and exited
bus_data_out_next <= Z32; -- success, return zero
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
WEA <= '1'; -- clear old status but
DIA <= DOA(0 to 7) & Z32(0 to 23); -- preserve ID stack
next_state <= DEALLOCATE_ID;
else
-- error occurred, return thread status w/ LSB=1
bus_data_out_next <= DOA(0 to 27) & CLEAR_ERROR_NOT_USED;
next_state <= END_TRANSACTION;
end if;
when DEALLOCATE_ID =>
if (next_ID /= Z32(0 to 8)) then
ADDRA <= next_ID - 1;
ENA <= '1';
next_ID_next <= next_ID - 1;
next_state <= DEALLOCATE_NEXT_ENTRY_RD_WAIT;
else
next_state <= END_TRANSACTION;
end if;
when DEALLOCATE_NEXT_ENTRY_RD_WAIT =>
next_state <= DEALLOCATE_NEXT_ENTRY_AVAIL;
when DEALLOCATE_NEXT_ENTRY_AVAIL =>
-- put ID back on stack, preserve other bits
ADDRA <= next_ID;
ENA <= '1';
WEA <= '1';
DIA <= Bus2IP_Addr(22 to 29) & DOA(8 to 31);
next_state <= END_TRANSACTION;
when JOIN_THREAD_INIT =>
-- join on the encoded thread ID if its PID = current_thread
-- and its status = used,~joined,~detached
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= JOIN_RD_ENTRY_RD_WAIT;
when JOIN_RD_ENTRY_RD_WAIT =>
next_state <= JOIN_RD_ENTRY_AVAILABLE;
when JOIN_RD_ENTRY_AVAILABLE =>
if ((DOA(16 to 23) & '0' = current_cpu_thread) and -- PID = current thread
(DOA(24 to 25) = "00") and -- ~detached,~joined
(DOA(26 to 27) /= "00")) then -- not unused
if DOA(27) = '0' then
-- thread has already exited, return a WARNING code
bus_data_out_next <= Z32(0 to 27) & THREAD_ALREADY_TERMINATED;
next_state <= END_TRANSACTION;
else
-- thread has not exited
bus_data_out_next <= Z32; -- success, return zero
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
WEA <= '1';
-- clear old status but
-- set joined bit; and preserve all other bits
DIA <= DOA(0 to 24) & '1' & DOA(26 to 31);
next_state <= END_TRANSACTION;
end if;
else
-- An error occured. Determine the error and return correct error code.
if( DOA(24) = '1' ) then
-- trying to join on a detached thread
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_DETACHED;
elsif ( DOA(24 to 25) = "01" ) then
-- tyring to join on a thread that is already joined
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_JOINED;
elsif( DOA(26) = '0' ) then
-- trying to join on a thread that is not used
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_NOT_USED;
elsif( DOA(16 to 23) & '0' /= current_cpu_thread ) then
-- trying to join to a thread that is not the current thread's child
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_NOT_CHILD;
else
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_UNKNOWN;
end if;
next_state <= END_TRANSACTION;
end if;
when IS_DETACHED_THREAD_INIT =>
-- Returns a 1 if the encoded thread ID is detached, else returns 0
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= IS_DETACHED_ENTRY_RD_WAIT;
when IS_DETACHED_ENTRY_RD_WAIT =>
next_state <= IS_DETACHED_ENTRY_AVAILABLE;
when IS_DETACHED_ENTRY_AVAILABLE =>
if (DOA(24) = '1' and DOA(26) = '1') then
-- Thread is detached, return 1
bus_data_out_next <= Z32(0 to 29) & "10"; -- The 0 in the last bit indicates no error
else
-- Thread is not detached, or not used, return 0
bus_data_out_next <= Z32;
end if;
next_state <= END_TRANSACTION;
when IS_QUEUED_INIT =>
tm2sch_opcode_next <= OPCODE_IS_QUEUED;
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29); -- thread ID
next_state <= ISQUEUED_WAIT_ACK;
return_state_next <= IS_QUEUED_DONE;
when IS_QUEUED_DONE =>
bus_data_out_next <= Z32(0 to 22) & sch2tm_data & '0';
next_state <= END_TRANSACTION;
when NEXT_THREAD_INIT =>
-- Return to the caller the value of the next thread to run
if sch2tm_next_id_valid = '1' then
-- the next thread has been identified,
-- read from Scheduler and check thread status
-- as stored by SWTM for consistency
ADDRA <= '0' & sch2tm_next_id;
ENA <= '1';
next_state <= NEXT_THREAD_RD_WAIT;
else
next_state <= NEXT_THREAD_WAIT4_SCHEDULER;
end if;
when NEXT_THREAD_WAIT4_SCHEDULER =>
if (sch2tm_next_id_valid = '1') then
-- Scheduler has made a scheduling decision
ADDRA <= '0' & sch2tm_next_id;
ENA <= '1';
next_state <= NEXT_THREAD_RD_WAIT;
elsif (timeout_expired = '1') then
-- Timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_NEXT_THREAD;
next_state <= RAISE_EXCEPTION; -- timeout
else
-- Continue waiting for scheduler
next_state <= current_state;
end if;
when NEXT_THREAD_RD_WAIT =>
next_state <= NEXT_THREAD_AVAILABLE;
when NEXT_THREAD_AVAILABLE =>
if DOA(26 to 27) = "11" then
-- thread status is used and not exited
-- dequeue the next_thread_id from the scheduler's queue
current_cpu_thread_next <= sch2tm_next_id & '0';
-- Send dequeue opperation to scheduler
tm2sch_opcode_next <= OPCODE_DEQUEUE;
tm2sch_request_next <= '1';
tm2sch_data_next <= Z32(0 to 7);
next_state <= DEQUEUE_WAIT_ACK;
return_state_next <= NEXT_THREAD_CHECK_DEQUEUE;
else
-- TM and SCHEDULER disagree if thread was used and not exited
-- return thread ID, set error bit and raise exception
bus_data_out_next <= Z32(0 to 22) & sch2tm_next_id & '1';
Exception_Cause_next <= EXCEPTION_SCHD_INVALID_THREAD;
next_state <= RAISE_EXCEPTION; -- timeout
end if;
when NEXT_THREAD_CHECK_DEQUEUE =>
-- Perform a check to make sure scheduler completed successfully
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
-- return the value of the next thread id (which by now is in the current_cpu_thread register)
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread(0 to 7) & '0';
next_state <= END_TRANSACTION;
end if;
when ADD_THREAD_INIT =>
-- if the thread is !used or exited return error
-- call scheduler to check queued status
-- if queued return error
-- call scheduler to enqueue thread ID
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- encoded thread ID
ENA <= '1';
next_state <= AT_ENTRY_RD_WAIT;
when AT_ENTRY_RD_WAIT =>
next_state <= AT_ENTRY_AVAILABLE;
when AT_ENTRY_AVAILABLE =>
-- check to see if the thread is used and !exited
if (DOA(26 to 27) = "11") then
-- thread is used and not exited
-- call scheduler isQueued
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29);
tm2sch_opcode_next <= OPCODE_IS_QUEUED;
next_state <= ISQUEUED_WAIT_ACK;
return_state_next <= AT_CHECK_ISQUEUE;
else
-- thread is unused or exited (or both)
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when AT_CHECK_ISQUEUE =>
-- Check to see if the thread is queued
if sch2tm_data(7) = '0' then
-- Thread is not queued, call scheduler's enqueue
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29);
tm2sch_opcode_next <= OPCODE_ENQUEUE;
next_state <= ENQUEUE_WAIT_ACK;
return_state_next <= AT_CHECK_ENQUEUE;
else
-- Thread is queued, return error
bus_data_out_next <= DOA(0 to 7) & sch2tm_data & DOA(16 to 27) & THREAD_ALREADY_QUEUED;
next_state <= END_TRANSACTION;
end if;
when AT_CHECK_ENQUEUE =>
-- Check to make sure the scheduler added the thread correctly
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 7) & sch2tm_data & Z32(16 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
bus_data_out_next <= Z32(0 to 7) & sch2tm_data & Z32(16 to 31);
next_state <= END_TRANSACTION;
end if;
when ISQUEUED_WAIT_ACK =>
-- wait for the scheduler to acknowledge the isqueued request
if sch2tm_busy = '0' then
-- scheduler has not yet responded to request
next_state <= current_state;
elsif (timeout_expired = '1') then
-- timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISQUEUED;
next_state <= RAISE_EXCEPTION;
else
-- scheduler acknowledged request, lower request line
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= ISQUEUED_WAIT_COMPLETE;
end if;
when ISQUEUED_WAIT_COMPLETE =>
-- wait for the scheduler to complete the isqueued request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
next_state <= current_state;
elsif (timeout_expired = '1') then
-- timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISQUEUED;
next_state <= RAISE_EXCEPTION;
else
-- scheduler finished request, and (should) have data on data_return line
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when ENQUEUE_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the enqueue request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ENQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= ENQUEUE_WAIT_COMPLETE;
end if;
when ENQUEUE_WAIT_COMPLETE =>
-- wait for the scheduler to complete the enqueue request
if sch2tm_busy = '1' then
-- scheduler has notyet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ENQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when DEQUEUE_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the dequeue request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_DEQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= DEQUEUE_WAIT_COMPLETE;
end if;
when DEQUEUE_WAIT_COMPLETE =>
-- wait for the scheduler to complete the dequeue request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_DEQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when IS_QUEUE_EMPTY_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the is queue empty request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISEMPTY;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= IS_QUEUE_EMPTY_WAIT_COMPLETE;
end if;
when IS_QUEUE_EMPTY_WAIT_COMPLETE =>
-- wait for the scheduler to complete the is queue empty request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISEMPTY;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when YIELD_THREAD_INIT =>
-- Retrieve the status of the current cpu thread
ADDRA <= '0' & current_cpu_thread(0 to 7);
ENA <= '1';
next_state <= YIELD_CURRENT_THREAD_RD_WAIT;
when YIELD_CURRENT_THREAD_RD_WAIT =>
next_state <= YIELD_CURRENT_THREAD_AVAILABLE;
when YIELD_CURRENT_THREAD_AVAILABLE =>
-- check to see if thread's status is used,~exited,~queued
if (DOA(26 to 27) = "11") then
-- check to see if the scheduler's queue is empty
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_IS_EMPTY;
tm2sch_data_next <= Z32(0 to 7);
next_state <= IS_QUEUE_EMPTY_WAIT_ACK;
return_state_next <= YIELD_CHECK_QUEUE_EMPTY;
else
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when YIELD_CHECK_QUEUE_EMPTY =>
if (sch2tm_data(7) = '1') then
-- Queue is empty, return the current thread id
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread;
next_state <= END_TRANSACTION;
else
-- Queue is not empty, add currently running thread to Q and then follow with a DEQ
next_state <= YIELD_ENQUEUE;
end if;
when YIELD_ENQUEUE =>
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_ENQUEUE;
tm2sch_data_next <= current_cpu_thread(0 to 7);
next_state <= ENQUEUE_WAIT_ACK;
return_state_next <= YIELD_CHECK_ENQUEUE;
when YIELD_CHECK_ENQUEUE =>
if (sch2tm_data(7) = '0') then
-- ENQ was successful, now DEQ to get next scheduling decision
current_cpu_thread_next <= sch2tm_next_id & '0'; -- update the currently running thread to the one that is scheduled to run next (AKA to be DEQ'd)
-- next_state <= YIELD_dummy_is_queued;
next_state <= YIELD_DEQUEUE;
else
-- ENQ failed, return error to caller
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
end if;
-- when YIELD_dummy_is_queued =>
-- tm2sch_request_next <= '1'; -- request the dummy is_queued operation
-- tm2sch_opcode_next <= OPCODE_IS_QUEUED;
-- tm2sch_data_next <= "11111111";
-- next_state <= ISQUEUED_WAIT_ACK;
-- return_state_next <= YIELD_DEQUEUE;
when YIELD_DEQUEUE =>
tm2sch_request_next <= '1'; -- request the DEQ operation to remove the thread to run from Q
tm2sch_opcode_next <= OPCODE_DEQUEUE;
tm2sch_data_next <= Z32(0 to 7);
next_state <= DEQUEUE_WAIT_ACK;
return_state_next <= YIELD_CHECK_DEQUEUE;
when YIELD_CHECK_DEQUEUE =>
if (sch2tm_data(7) = '1') then
-- error during DEQ...
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- DEQ completed successfully, end operation
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread(0 to 7) & '0'; -- setup the return value of the next thread to run (now in the currently running thread)
next_state <= END_TRANSACTION;
end if;
when EXIT_THREAD_INIT =>
bus_data_out_next <= Z32; -- change if failure occurs
ADDRA <= '0' & Bus2IP_Addr(22 to 29);
ENA <= '1';
next_state <= EXIT_THREAD_RD_WAIT;
when EXIT_THREAD_RD_WAIT =>
next_state <= EXIT_THREAD_AVAIABLE;
when EXIT_THREAD_AVAIABLE =>
-- full entry for the current_thread is required in later states
current_status_next <= DOA(0 to 31);
ADDRA <= '0' & Bus2IP_Addr(22 to 29);
ENA <= '1';
WEA <= '1';
if (DOA(24) = '1') then
-- Thread is detached
-- Make the thread status used and exited.
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= END_TRANSACTION;
elsif (DOA(25) = '1') then
-- Thread is joined
-- Make the thread status used and exited, and wake the parent
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= EXIT_READ_PARENT;
else
-- Thread is not detached and still joinable
-- Set the thread status to used and exited
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= END_TRANSACTION;
end if;
when EXIT_READ_PARENT =>
-- The thread that is exiting was joined, wake the parent up
ADDRA <= '0' & current_status(16 to 23);
ENA <= '1';
next_state <= EXIT_READ_PARENT_WAIT;
when EXIT_READ_PARENT_WAIT =>
next_state <= EXIT_READ_PARENT_AVAILABLE;
when EXIT_READ_PARENT_AVAILABLE =>
-- Make sure the parent thread is used and not exited
if (DOA(26 to 27) = "11") then
-- Parent thread is used and not exited.
-- Add the parent thread tothe scheduler's queue
tm2sch_opcode_next <= OPCODE_ENQUEUE;
tm2sch_request_next <= '1';
tm2sch_data_next <= current_status(16 to 23);
return_state_next <= EXIT_CHECK_ENQUEUE;
next_state <= ENQUEUE_WAIT_ACK;
else
-- Parent thread is either unused or exited, neither of which it should be
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when EXIT_CHECK_ENQUEUE =>
-- Check to make sure the scheduler added the thread correctly
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
bus_data_out_next <= Z32(0 to 31);
next_state <= END_TRANSACTION;
end if;
when RAISE_EXCEPTION =>
-- NOTE !!! You must assign Exception_Cause
-- where-ever you assign next_state <= RAISE_EXCEPTION;
Exception_Address_next <= Bus2IP_Addr(0 to 31); -- save address
access_error <= '1'; -- assert interrupt
my_ack <= '1'; -- done, "ack" the bus
next_state <= END_TRANSACTION_WAIT;
when END_TRANSACTION =>
IP2Bus_Data <= bus_data_out;
my_ack <= '1'; -- done, "ack" the bus
next_state <= END_TRANSACTION_WAIT;
when END_TRANSACTION_WAIT =>
if( Bus2IP_RdCE(0)='0' and Bus2IP_WrCE(0)='0' ) then
next_state <= IDLE_STATE;
else
next_state <= current_state;
end if;
when others =>
Exception_Cause_next <= EXCEPTION_ILLEGAL_STATE;
next_state <= RAISE_EXCEPTION;
end case; -- case current_state
end process SWTM_LOGIC_PROC;
-------------------------------------------------------------------
-- ICON core instance
-------------------------------------------------------------------
-- -- simulation translate_off
-- i_icon : chipscope_icon_v1_03_a
-- port map
-- (
-- control0 => control0
-- );
-- -- simulation translate_on
--
-- COUNTER_PROC : process (Bus2IP_Clk) is
-- begin
-- if( Bus2IP_Clk'event and Bus2IP_Clk='1' ) then
-- if (Bus2IP_Reset = '1') then
-- my_counter <= (others => '0');
-- else
-- my_counter <= my_counter + 1;
-- end if;
-- end if;
-- end process COUNTER_PROC;
--
-- --
--
-- -------------------------------------------------------------------
-- -- ILA core instance
-- -------------------------------------------------------------------
--
-- -- simulation translate_off
-- i_ila : chipscope_ila_v1_02_a
-- port map
-- (
-- control => control0,
-- clk => Bus2IP_Clk,
-- trig0(63 downto 32) => Bus2IP_Data,
-- trig0(31 downto 0) => my_counter, -- 64 bits -- Add in chipscope signals and run on board!!!!
-- trig1(63 downto 32) => Bus2IP_Addr,
-- trig1(31 downto 0) => bus_data_out, -- 64 bits
-- trig2 => current_status, -- 32 bits
-- trig3 => Bus2IP_Addr, -- 32 bits
-- trig4(0) => Bus2IP_RdCE, -- 16 bits
-- trig4(1) => Bus2IP_WrCE,
-- trig4(2) => my_ack,
-- trig4(3) => my_tout_sup,
-- trig4(4) => Bus2IP_Reset,
-- trig4(5) => '0',
-- trig4(6) => tm2sch_request_reg,
-- trig4(7) => next_ID(0),
-- trig4(8) => next_ID(1),
-- trig4(9) => next_ID(2),
-- trig4(10) => next_ID(3),
-- trig4(11) => next_ID(4),
-- trig4(12) => next_ID(5),
-- trig4(13) => next_ID(6),
-- trig4(14) => next_ID(7),
-- trig4(15) => next_ID(8)
-- );
-- -- simulation translate_on
--
end IMP;
| bsd-3-clause | 3487ea08cc1b4ee7b54a41939c38b528 | 0.535548 | 3.697396 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_acc_idea_v1_00_a/hdl/vhdl/_hw_acc_idea.vhd | 2 | 9,027 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_idea is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
Clk : in std_logic;
RST : in std_logic;
BRAM_A_Clk : out std_logic;
BRAM_A_RST : out std_logic;
BRAM_B_Clk : out std_logic;
BRAM_B_RST : out std_logic;
BRAM_C_Clk : out std_logic;
BRAM_C_RST : out std_logic;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : in std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : out std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_idea;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_idea is
component idea_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
component chipscope_ila
PORT (
CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
CLK : IN STD_LOGIC;
TRIG0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
TRIG5 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
TRIG6 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
TRIG7 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
TRIG8 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
TRIG9 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG10 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG11 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG12 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG13 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG14 : IN STD_LOGIC_VECTOR(0 TO 0);
TRIG15 : IN STD_LOGIC_VECTOR(0 TO 0));
end component;
component chipscope_icon
PORT (
CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
end component;
signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0);
signal sBRAM_A_addr : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_A_dIN : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_A_dOUT : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_A_en : std_logic_vector(0 to 0) ;
signal sBRAM_A_wEN : std_logic_vector(0 to (32/8) -1);
signal sBRAM_B_addr : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_B_dIN : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_B_dOUT : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_B_en : std_logic_vector(0 to 0) ;
signal sBRAM_B_wEN : std_logic_vector(0 to (32/8) -1);
signal sBRAM_C_addr : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_C_dIN : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_C_dOUT : std_logic_vector(0 to (32 - 1)) ;
signal sBRAM_C_en : std_logic_vector(0 to 0) ;
signal sBRAM_C_wEN : std_logic_vector(0 to (32/8) -1);
signal sFSL0_S_Read : std_logic_vector(0 to 0);
signal sFSL0_S_Data : std_logic_vector(0 to 31);
signal sFSL0_S_Exists : std_logic_vector(0 to 0);
------------------------------------------------------
signal sFSL0_M_Write : std_logic_vector(0 to 0);
signal sFSL0_M_Data : std_logic_vector(0 to 31);
signal sFSL0_M_Full : std_logic_vector(0 to 0);
signal reset_sig : std_logic;
-- Architecture Section
begin
BRAM_A_clk <= clk;
BRAM_A_rst <= rst;
BRAM_B_clk <= clk;
BRAM_B_rst <= rst;
BRAM_C_clk <= clk;
BRAM_C_rst <= rst;
sBRAM_A_dIN <= BRAM_A_din;
BRAM_A_addr <= sBRAM_A_addr;
BRAM_A_dOUT <= sBRAM_A_dout;
BRAM_A_en <= sBRAM_A_en(0);
BRAM_A_wEN <= sBRAM_A_wen;
sBRAM_B_dIN <= BRAM_B_din ;
BRAM_B_addr <= sBRAM_B_addr ;
BRAM_B_dOUT <= sBRAM_B_dout ;
BRAM_B_en <= sBRAM_B_en(0) ;
BRAM_B_wEN <= sBRAM_B_wen ;
sBRAM_C_dIN <= BRAM_C_din ;
BRAM_C_addr <= sBRAM_C_addr ;
BRAM_C_dOUT <= sBRAM_C_dout ;
BRAM_C_en <= sBRAM_C_en(0) ;
BRAM_C_wEN <= sBRAM_C_wen ;
FSL0_S_Read<= sFSL0_S_Read(0);
sFSL0_S_Data<= FSL0_S_data;
sFSL0_S_Exists(0) <= FSL0_S_exists;
------------------------------------------------------
FSL0_M_Write <= sFSL0_M_Write(0);
FSL0_M_Data <= sFSL0_M_data;
sFSL0_M_Full(0) <= FSL0_M_full;
--icon_uut : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL0);
-- ila_uut : chipscope_ila
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk,
-- TRIG0 => sBRAM_addr,
-- TRIG1 => sBRAM_dout,
-- TRIG2 => sBRAM_din,
-- TRIG3 => sFSL0_M_Data,
-- TRIG4 => sFSL0_S_Data,
-- TRIG5 => X"0000" ,
-- TRIG6 => X"00" ,
-- TRIG7 => X"0",
-- TRIG8 => sBRAM_wen,
-- TRIG9 => sBRAM_en(0 to 0),
-- TRIG10 => sFSL0_S_Exists(0 to 0),
-- TRIG11 => sFSL0_S_Read(0 to 0),
-- TRIG12 => sFSL0_M_Write(0 to 0),
-- TRIG13 => sFSL0_M_Write(0 to 0),
-- TRIG14 => sFSL0_M_Write(0 to 0),
-- TRIG15 => sFSL0_M_Write(0 to 0));
uut : idea_chan
port map (
Vector_A_addr0 => sBRAM_A_addr,
Vector_A_dIN0 => sBRAM_A_dout,
Vector_A_dOUT0 => sBRAM_A_din,
Vector_A_rENA0 => sBRAM_A_en(0),
Vector_A_wENA0 => sBRAM_A_wen,
Vector_B_addr0 => sBRAM_B_addr,
Vector_B_dIN0 => sBRAM_B_dout,
Vector_B_dOUT0 => sBRAM_B_din,
Vector_B_rENA0 => sBRAM_B_en(0),
Vector_B_wENA0 => sBRAM_B_wen,
Vector_C_addr0 => sBRAM_C_addr,
Vector_C_dIN0 => sBRAM_C_dout,
Vector_C_dOUT0 => sBRAM_C_din,
Vector_C_rENA0 => sBRAM_C_en(0),
Vector_C_wENA0 => sBRAM_C_wen,
chan1_channelDataIn => sFSL0_M_Data,
chan1_channelDataOut => sFSL0_S_Data,
chan1_exists => sFSL0_S_Exists(0),
chan1_full => sFSL0_M_Full(0),
chan1_channelRead => sFSL0_S_Read(0),
chan1_channelWrite => sFSL0_M_Write(0),
clock_sig => clk,
reset_sig => rst
);
end architecture implementation;
| bsd-3-clause | bbcb1cf0343c269494eb262944fbebe7 | 0.568074 | 2.688207 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/or_muxcy.vhd | 3 | 11,464 | -------------------------------------------------------------------------------
-- $Id: or_muxcy.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- or_muxcy
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy.vhd
-- Version: v1.02e
-- Description: This file is used to implement an OR function using
-- carry chain muxes.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of or_muxcy is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- If the number of bits to OR is 4 or less, a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 5 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= In_bus(0);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more, then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 5 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(0 to C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => '0' , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
| bsd-3-clause | 33bfd529a8477bd9f8f827787194b8d7 | 0.402477 | 5.043555 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/tx_ctrl.vhd | 1 | 38,507 | --------------------------------------------------------------------------------
-- Title : tx_ctrl
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : tx_ctrl.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 09.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- this module controls all actions within the TxModule, including power
-- messages and information given by the init module
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- * tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.src_utils_pkg.all;
entity tx_ctrl is
port(
clk : in std_logic;
rst : in std_logic;
-- IP core
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
pme_to_cr : out std_logic;
-- FIFO
tx_c_head_empty : in std_logic;
tx_wr_head_empty : in std_logic;
tx_c_data_empty : in std_logic;
tx_wr_data_empty : in std_logic;
tx_c_head_enable : out std_logic;
tx_wr_head_enable : out std_logic;
tx_c_data_enable : out std_logic;
tx_wr_data_enable : out std_logic;
-- tx_put_data
aligned : in std_logic;
data_len : in std_logic_vector(9 downto 0);
wr_rd : in std_logic; -- 0: write, 1: read
posted : in std_logic; -- 0: non-posted, 1: posted
byte_count : in std_logic_vector(11 downto 0);
io_write : in std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : in std_logic_vector(31 downto 0);
tx_tag_nbr : out std_logic_vector(7 downto 0);
get_header : out std_logic;
get_next_header : out std_logic;
make_header : out std_logic;
data_enable : out std_logic;
c_wrrd : out std_logic; -- =0: completion, =1: write or read
completer_id : out std_logic_vector(15 downto 0);
own_id : out std_logic_vector(15 downto 0);
abort_compl : out std_logic;
send_len : out std_logic_vector(9 downto 0); -- length of actual packet, stored to header
send_addr : out std_logic_vector(31 downto 0); -- address of actual packet, stored to header
payload_loop : out std_logic; -- =0: no loop, =1: loop
first_last_full : out std_logic_vector(1 downto 0); -- 00: unused, 01: first packet of payload_loop, 01: last
-- packet of payload_loop, 11: all enabled
-- tx_compl_timeout
start : out std_logic;
start_tag_nbr : out std_logic_vector(4 downto 0);
-- error
compl_abort : out std_logic;
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
max_payload : in std_logic_vector(2 downto 0)
);
end entity tx_ctrl;
-- ****************************************************************************
architecture tx_ctrl_arch of tx_ctrl is
-- FSM state encoding ---------------------------------------------------------
type fsm_state is (
PREP_HEADER, IDLE, PREP_TRANS, START_TRANS, TRANSMIT, PME_OFF, TAG_START, ABORT, IO_WR
);
signal state : fsm_state;
-------------------------------------------------------------------------------
-- constants ------------------------------------------------------------------
constant ADDR_INCR : std_logic_vector(31 downto 0) := x"00000008";
-------------------------------------------------------------------------------
-- internal signals -----------------------------------------------------------
signal data_from_fifo : std_logic_vector(10 downto 0);
signal desired_len : std_logic_vector(10 downto 0);
signal data_to_ava : std_logic_vector(11 downto 0);
signal ready_q : std_logic;
signal wait_clk : integer range 3 downto 0 := 0;
signal pme_off_int : std_logic;
signal c_wr_int : std_logic;
signal tag_nbr_cntr : std_logic_vector(4 downto 0);
signal data_enable_int : std_logic;
signal fifo_enable_int : std_logic;
signal own_id_int : std_logic_vector(15 downto 0);
signal abort_compl_int : std_logic;
signal max_payload_len : std_logic_vector(9 downto 0);
signal payload_loop_en : std_logic;
signal addr_int : std_logic_vector(31 downto 0);
signal addr_offset : std_logic_vector(31 downto 0);
signal eop_int : std_logic;
signal get_last_packet : std_logic;
signal tx_st_valid0_int : std_logic;
signal send_len_int : std_logic_vector(9 downto 0);
signal arbit_access : std_logic_vector(1 downto 0); -- 00: invalid, 01: cpl, 10: wr/rd
-------------------------------------------------------------------------------
begin
-- unused signal, set to zero
tx_st_err0 <= '0';
-- decode max_payload
with max_payload select
max_payload_len <= "0001000000" when "001",
"0010000000" when "010",
"0100000000" when "011",
"1000000000" when "100",
"0000000000" when "101",
"0000100000" when others;
data_enable <= data_enable_int;
c_wrrd <= c_wr_int;
abort_compl <= abort_compl_int;
tx_st_valid0 <= tx_st_valid0_int;
send_len <= send_len_int;
-------------------------------------------------------------------------------
fsm_trans : process(rst, clk)
begin
if(rst = '1') then
state <= IDLE;
elsif(clk'event and clk = '1') then
case state is
when IDLE =>
if(arbit_access /= "00") then
state <= PREP_TRANS;
elsif(pme_off_int = '1') then
state <= PME_OFF;
else
state <= IDLE;
end if;
when PREP_HEADER =>
if(wait_clk = 3) then
state <= START_TRANS;
else
state <= PREP_HEADER;
end if;
when PREP_TRANS =>
if(wait_clk = 1 and c_wr_int = '1') then
state <= PREP_HEADER;
elsif(wait_clk = 2 and c_wr_int = '0') then
state <= PREP_HEADER;
else
state <= PREP_TRANS;
end if;
when START_TRANS =>
if(ready_q = '1') then
state <= TRANSMIT;
else
state <= START_TRANS;
end if;
when TRANSMIT =>
if(io_write = '1') then
state <= IO_WR;
elsif(data_to_ava <= TWO_12B and c_wr_int = '1' and wr_rd = '1') then
state <= TAG_START;
elsif(data_to_ava <= TWO_12B and c_wr_int = '0' and abort_compl_int = '1') then
state <= ABORT;
-- no loop on completion as read requests with length > max_payload_len are rejected
-- if looped write is finished (payload_loop_en = 0) go to IDLE as well
elsif(ready_q = '1' and (c_wr_int = '0' or (c_wr_int = '1' and wr_rd = '0' and payload_loop_en = '0')) and
((data_to_ava <= TWO_12B and ((aligned = '1' and send_len_int(0) = '0') or (aligned = '0' and send_len_int(0) = '1'))) or
(data_to_ava <= ONE_12B and ((aligned = '1' and send_len_int(0) = '1') or (aligned = '0' and send_len_int(0) = '0')))) ) then
state <= IDLE;
elsif(data_to_ava <= TWO_12B and c_wr_int = '1' and wr_rd = '0' and payload_loop_en = '1' and tx_st_valid0_int = '1') then
state <= PREP_HEADER;
else
state <= TRANSMIT;
end if;
when PME_OFF =>
state <= IDLE;
when TAG_START =>
-- transmission is done so process received power off request now
if(pme_off_int = '1' or pme_to_sr = '1') then
state <= PME_OFF;
elsif(payload_loop_en = '1') then
state <= PREP_HEADER;
else
state <= IDLE;
end if;
when ABORT =>
-- transmission is done so process received power off request now
if(pme_off_int = '1' or pme_to_sr = '1') then
state <= PME_OFF;
elsif(data_from_fifo <= TWO_11B) then
state <= IDLE;
else
state <= ABORT;
end if;
when IO_WR =>
-- transmission is done so process received power off request now
if(pme_off_int = '1' or pme_to_sr = '1') then
state <= PME_OFF;
else
state <= IDLE;
end if;
-- coverage off
when others =>
-- synthesis translate_off
report "undecoded state in ctrl_fsm" severity error;
-- synthesis translate_on
-- coverage on
end case;
end if;
end process fsm_trans;
-------------------------------------------------------------------------------
fsm_out : process(rst, clk)
begin
if(rst = '1') then
tx_st_valid0_int <= '0';
tx_st_sop0 <= '0';
tx_st_eop0 <= '0';
pme_to_cr <= '0';
tx_c_head_enable <= '0';
tx_wr_head_enable <= '0';
tx_c_data_enable <= '0';
tx_wr_data_enable <= '0';
tx_tag_nbr <= (others => '0');
get_header <= '0';
get_next_header <= '0';
make_header <= '0';
data_enable_int <= '0';
c_wr_int <= '0';
completer_id <= (others => '0');
own_id <= (others => '0');
abort_compl_int <= '0';
send_len_int <= (others => '0');
send_addr <= (others => '0');
payload_loop <= '0';
first_last_full <= (others => '0');
start <= '0';
start_tag_nbr <= (others => '0');
compl_abort <= '0';
data_from_fifo <= (others => '0');
desired_len <= (others => '0');
data_to_ava <= (others => '0');
ready_q <= '0';
wait_clk <= 0;
pme_off_int <= '0';
tag_nbr_cntr <= (others => '0');
fifo_enable_int <= '0';
own_id_int <= (others => '0');
payload_loop_en <= '0';
addr_int <= (others => '0');
addr_offset <= (others => '0');
eop_int <= '0';
get_last_packet <= '0';
arbit_access <= (others => '0');
elsif(clk'event and clk = '1') then
if(state = IDLE and tx_c_head_empty = '0') then
arbit_access <= "01";
elsif(state = IDLE and tx_wr_head_empty = '0') then
arbit_access <= "10";
elsif(state /= IDLE) then
arbit_access <= (others => '0');
end if;
if(state = TRANSMIT and tx_st_ready0 = '0' and data_from_fifo <= FOUR_12B and data_from_fifo > ZERO_12B and get_last_packet = '0') then
get_last_packet <= '1';
elsif(state = IDLE or (state = TRANSMIT and tx_st_ready0 = '1' and get_last_packet = '1')) then
get_last_packet <= '0';
end if;
if(state = TRANSMIT and data_to_ava >= THREE_12B and ready_q = '0') then
eop_int <= '1';
elsif(state = IDLE or state = PREP_HEADER or state = ABORT or state = TAG_START or state = IO_WR
or (state = TRANSMIT and tx_st_ready0 = '1' and ready_q = '1')
) then
eop_int <= '0';
end if;
-- release transfer when there is no more data to send
if(state = IDLE or state = PREP_HEADER or state = ABORT or state = IO_WR or state = TAG_START or
(state = TRANSMIT and ((data_to_ava <= TWO_12B and eop_int = '0') or ready_q = '0')) or
(state = START_TRANS and ready_q = '0')) then
tx_st_valid0_int <= '0';
-- assert tx_st_valid0 after correct ReadyLatency, in this case ReadyLatency = 2
elsif((state = START_TRANS and ready_q = '1') or (state = TRANSMIT and ready_q = '1')
) then
tx_st_valid0_int <= '1';
end if;
-- assert tx_st_sop0 after correct ReadyLatency, in this case ReadyLatency = 2
if(state = START_TRANS and ready_q = '1') then
tx_st_sop0 <= '1';
elsif((state = START_TRANS and ready_q = '0') or state = TRANSMIT) then
tx_st_sop0 <= '0';
end if;
if(state = IDLE or state = PREP_HEADER or state = TAG_START or state = ABORT or state = IO_WR or (state = TRANSMIT and
(data_to_ava > FOUR_12B or (data_to_ava <= TWO_12B and eop_int = '0')) and io_write = '0')) then
tx_st_eop0 <= '0';
-- set end of packet according to actual transfer length
elsif(state = TRANSMIT and ready_q = '1' and ((wr_rd = '1' and data_to_ava = THREE_12B) or
(data_to_ava = FOUR_12B and eop_int = '0' and ((aligned = '1' and send_len_int(0) = '0') or (aligned = '0' and send_len_int(0) = '1'))) or
(data_to_ava = THREE_12B and eop_int = '0' and ((aligned = '1' and send_len_int(0) = '1') or (aligned = '0' and send_len_int(0) = '0'))) or
io_write = '1' or (eop_int = '1' and data_to_ava <= TWO_12B) or (abort_compl_int = '1' and data_to_ava <= FOUR_12B))) then
tx_st_eop0 <= '1';
end if;
-- enable FIFO for corresponding type of transaction chosen before
if((state = IDLE and tx_c_head_empty = '0' and arbit_access = "01") or (state = PREP_TRANS and wait_clk = 1 and tx_c_head_empty = '0' and c_wr_int = '0')) then
tx_c_head_enable <= '1';
elsif(state = PREP_TRANS and (wait_clk /= 1 or tx_c_head_empty = '1' or c_wr_int = '1')) then
tx_c_head_enable <= '0';
end if;
-- enable FIFO for corresponding type of transaction chosen before
if(state = IDLE and tx_wr_head_empty = '0' and arbit_access = "10") then
tx_wr_head_enable <= '1';
-- enable correct header FIFO
elsif(state = PREP_TRANS and (wait_clk /= 1 or tx_c_head_empty = '1' or c_wr_int = '1')) then
tx_wr_head_enable <= '0';
end if;
-- enable appropriate FIFO
if((state = PREP_HEADER and wait_clk = 0 and c_wr_int = '0' and abort_compl_int = '0') or
(state = START_TRANS and tx_st_ready0 = '1' and c_wr_int = '0' and data_from_fifo > ZERO_11B and abort_compl_int = '0') or
(state = ABORT and data_from_fifo > TWO_11B) or
(state = TRANSMIT and tx_st_ready0 = '1' and c_wr_int = '0' and ((data_from_fifo > TWO_11B and data_to_ava > THREE_12B) or (get_last_packet = '1' and data_from_fifo > ZERO_12B)))
) then
tx_c_data_enable <= '1';
elsif((state = PREP_HEADER and wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0') or
(state = START_TRANS and c_wr_int = '0' and ((tx_st_ready0 = '0' and data_from_fifo = ONE_11B) or
(ready_q = '1' and data_from_fifo <= ONE_11B))) or
(state = TRANSMIT and ((data_from_fifo <= TWO_11B and c_wr_int = '0') or (tx_st_ready0 = '0'))) or -- reset FIFO enable when hard IP
-- core isn't able to receive data
(state = ABORT and data_from_fifo <= TWO_11B) -- disble data retrieval from FIFO due to end of transmission
) then
tx_c_data_enable <= '0';
end if;
if((state = PREP_HEADER and wait_clk = 1 and c_wr_int = '1' and wr_rd = '0') or
(state = START_TRANS and tx_st_ready0 = '1' and c_wr_int = '1' and wr_rd = '0' and data_from_fifo > ZERO_11B and fifo_enable_int = '0') or
(state = TRANSMIT and tx_st_ready0 = '1' and c_wr_int = '1' and wr_rd = '0' and ((data_from_fifo > TWO_11B and data_to_ava > THREE_12B) or (get_last_packet = '1' and data_from_fifo > ZERO_12B)))
) then
tx_wr_data_enable <= '1';
elsif((state = PREP_HEADER and wait_clk = 2 and c_wr_int = '1' and wr_rd = '0') or
(state = START_TRANS and c_wr_int = '1' and ((fifo_enable_int = '1' and ((send_len_int(0) = '1' and data_from_fifo = ONE_11B) or
(send_len_int(0) = '0' and data_from_fifo = TWO_11B))) or (tx_st_ready0 = '0' and data_from_fifo = ONE_11B))) or
(state = TRANSMIT and ((data_from_fifo <= TWO_11B and c_wr_int = '1') or (tx_st_ready0 = '0'))) -- reset FIFO enable when hard IP
-- core isn't able to receive data
) then
tx_wr_data_enable <= '0';
end if;
-- calculate tag ID
if(state = PREP_HEADER and c_wr_int = '1' and (wr_rd = '1' or (wr_rd = '0' and posted = '0'))) then
tx_tag_nbr <= "000" & tag_nbr_cntr;
elsif(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and posted = '1') then
tx_tag_nbr <= "00100000";
end if;
-- tell tx_put_data module to process header information
if(state = PREP_TRANS and wait_clk = 0) then
get_header <= '1';
elsif(state = PREP_HEADER or (state = PREP_TRANS and wait_clk = 1)) then
get_header <= '0';
end if;
-- completion information is stored to the FIFO using more than one header packet, thus get next header too
if(state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0') then
get_next_header <= '1';
elsif(state = PREP_HEADER) then
get_next_header <= '0';
end if;
-- advise tx_put_data module to process header information and to route that onto Avalon ST data bus
if(state = PREP_HEADER and ((c_wr_int = '0' and wait_clk = 0) or (c_wr_int = '1' and wait_clk = 1))) then
make_header <= '1';
elsif(state = PREP_HEADER and ((c_wr_int = '0' and wait_clk = 1) or (c_wr_int = '1' and wait_clk = 2))) then
make_header <= '0';
end if;
if((state = IDLE or state = ABORT or (state = START_TRANS and ready_q = '0')) or
(state = TRANSMIT and (ready_q = '0' or data_to_ava <= ZERO_12B)) or
(state = PREP_HEADER and (wait_clk = 0 or (wait_clk = 2 and c_wr_int = '0') or (wait_clk = 3 and c_wr_int = '1')))
) then
data_enable_int <= '0';
elsif((state = PREP_HEADER and ((wait_clk = 1 and c_wr_int = '0') or (wait_clk = 2 and c_wr_int = '1'))) or
(state = START_TRANS and ready_q = '1') or -- enable data processing when hard IP is ready to process data
(state = TRANSMIT and ready_q = '1' and data_to_ava > ZERO_12B) -- enable data processing as long as the data length counter isn't 0
) then
data_enable_int <= '1';
end if;
-- start transaction with priority on completions, don't change in any other state except IDLE
if(state = IDLE and arbit_access = "01") then
c_wr_int <= '0';
elsif(state = IDLE and arbit_access = "10") then
c_wr_int <= '1';
end if;
-- give actual own bus/dev/func number (=own_id_int) to tx_put_data module either for completion transmission
if(state = PREP_TRANS and c_wr_int = '0') then
completer_id <= own_id_int;
end if;
-- give actual own bus/dev/func number (=own_id_int) to tx_put_data module either for write/read transmission
if(state = PREP_TRANS and c_wr_int = '1') then
own_id <= own_id_int;
end if;
if(state = IDLE or state = ABORT) then
abort_compl_int <= '0';
-- if byte_count is greater than allowed (greater than max_payload) reject transmission, send completion without data
-- with completer abort status and signal error to error module which will signal error to hard IP by asserting cpl_err(2)
-- for 1 clock cycle
elsif(state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and tx_c_head_empty = '0' and ((data_len = ZERO_10B and
max_payload_len /= ZERO_10B) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
abort_compl_int <= '1';
end if;
if(state = IDLE) then
send_len_int <= (others => '0');
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0') or (state = PREP_HEADER and wait_clk = 1 and c_wr_int = '1' and
wr_rd = '1')) then
send_len_int <= data_len;
-- store transmission length
elsif(state = PREP_HEADER and wait_clk = 1 and c_wr_int = '1' and wr_rd = '0') then
send_len_int <= data_from_fifo(9 downto 0);
end if;
if(state = IDLE) then
send_addr <= (others => '0');
-- show right address to tx_put_data module
elsif(state = PREP_HEADER and wait_clk = 1) then
send_addr <= addr_int;
end if;
if(state = IDLE) then
payload_loop <= '0';
-- if packet length is greater than allowed payload size, set payload_loop_en = 1 and do internal loop until desired
-- packet length is sent using multiple TLPs; don't forget to adapt packet address after each loop
elsif(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and
((data_len = ZERO_10B and data_len /= max_payload_len) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
payload_loop <= '1';
end if;
if(state = IDLE) then
first_last_full <= (others => '0');
-- advise tx_put_data module how to process first/last byte enables
elsif(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and
((data_len = ZERO_10B and data_len /= max_payload_len) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
first_last_full <= "01";
elsif(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and wait_clk = 1 and desired_len <= data_from_fifo) then
first_last_full <= "10";
elsif(state = START_TRANS) then
first_last_full <= "11";
end if;
if(state = IDLE or state = ABORT) then
compl_abort <= '0';
-- assert completion abort indicator
elsif(state = TRANSMIT and data_to_ava <= TWO_12B and c_wr_int = '0' and abort_compl_int = '1') then
compl_abort <= '1';
end if;
-- calculate length counter for data that has to be taken from appropriate FIFO
if((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and data_len = ZERO_10B) or
(state = PREP_HEADER and wait_clk = 0 and data_len = ZERO_10B and ((desired_len /= ZERO_11B and c_wr_int = '0') or (desired_len = ZERO_11B and
(c_wr_int = '0' or (c_wr_int = '1' and data_len = max_payload_len)))))
) then
data_from_fifo <= '1' & data_len;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and data_len > ZERO_10B) or
(state = PREP_HEADER and wait_clk = 0 and data_len /= ZERO_10B and ((desired_len /= ZERO_11B and c_wr_int = '0') or (desired_len = ZERO_11B
and (c_wr_int = '0' or (c_wr_int = '1' and (max_payload_len = ZERO_10B or data_len <= max_payload_len))))))
) then
data_from_fifo <= '0' & data_len;
elsif(state = PREP_HEADER and wait_clk = 0 and c_wr_int = '1' and ((desired_len = ZERO_11B and ((data_len = ZERO_10B and data_len /= max_payload_len) or
(data_len /= ZERO_10B and data_len > max_payload_len))) or (desired_len /= ZERO_11B and ((desired_len = X_400_11B and
desired_len(9 downto 0) /= max_payload_len) or (desired_len < X_400_11B and desired_len(9 downto 0) > max_payload_len))))
)then
data_from_fifo <= '0' & max_payload_len;
elsif(state = PREP_HEADER and desired_len /= ZERO_11B and wait_clk = 0 and c_wr_int = '1' and desired_len = X_400_11B and desired_len(9 downto 0) = max_payload_len) then
data_from_fifo <= desired_len;
elsif(state = PREP_HEADER and desired_len /= ZERO_11B and wait_clk = 0 and c_wr_int = '1' and ((desired_len < X_400_11B and max_payload_len = ZERO_10B) or (desired_len < X_400_11B
and desired_len(9 downto 0) <= max_payload_len)))then
data_from_fifo <= '0' & desired_len(9 downto 0);
elsif((state = PREP_HEADER and ((wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0' and data_from_fifo > ONE_11B) or
(wait_clk = 2 and c_wr_int = '1' and wr_rd = '0' and data_from_fifo > ONE_11B))) or
(fifo_enable_int = '1' and ((state = TRANSMIT and data_from_fifo > ONE_11B and abort_compl_int = '0') or (state = ABORT and abort_compl_int = '0') or (state = START_TRANS and data_from_fifo > ONE_11B)))
)then
data_from_fifo <= data_from_fifo - TWO_11B;
elsif((state = PREP_HEADER and data_from_fifo <= ONE_11B and ((wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0') or
(wait_clk = 2 and c_wr_int = '1' and wr_rd = '0'))) or
(state = START_TRANS and fifo_enable_int = '1' and data_from_fifo = ONE_11B) or
(fifo_enable_int = '1' and state = TRANSMIT and data_from_fifo <= ONE_11B)
)then
data_from_fifo <= (others => '0');
end if;
-- as this is a loop, change desired_len only when entering this state for the very first time
-- on other entry times only subtract data_from_fifo value
-- new value for data_from_fifo is valid when wait_clk = 1
if(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and data_len = ZERO_10B) then
desired_len <= '1' & data_len;
elsif(state = PREP_HEADER and desired_len = ZERO_11B and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and data_len /= ZERO_10B) then
desired_len <= '0' & data_len;
elsif(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and wait_clk = 1 and desired_len >= data_from_fifo) then
desired_len <= desired_len - data_from_fifo;
elsif(state = PREP_HEADER and c_wr_int = '1' and (wr_rd = '1' or (wr_rd = '0' and wait_clk = 1 and desired_len < data_from_fifo))) then
desired_len <= (others => '0');
end if;
-- in actual design, completion data is returned using one completion only
-- reads that request more data than max_payload_size (max_read ignored by PCIe requester) are rejected thus use original data length here
-- check bit 2 for address alignment (=0: aligned, =1: not aligned) thus wait until addr_int is set (wait_clk = 1)
-- decrement length counters for amount of data taken from FIFO and amount of data sent to hard IP core
if((state = PREP_TRANS and wait_clk = 2 and ((c_wr_int = '0' and abort_compl_int = '1') or (c_wr_int = '1' and wr_rd = '1'))) or
(state = PREP_HEADER and ((c_wr_int = '1' and wait_clk = 1 and wr_rd = '1') or (abort_compl_int = '1' and wait_clk < 2)))) then
data_to_ava <= THREE_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '1' and data_len = ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '1' and data_len = ZERO_10B)) then
data_to_ava <= ("01" & data_len) + FOUR_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '0' and data_len = ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '0' and data_len = ZERO_10B)) then
data_to_ava <= ("01" & data_len) + THREE_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '1' and data_len /= ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '1' and data_len /= ZERO_10B)) then
data_to_ava <= ("00" & data_len) + FOUR_12B;
elsif((state = PREP_TRANS and wait_clk = 2 and c_wr_int = '0' and abort_compl_int = '0' and aligned = '0' and data_len /= ZERO_10B) or
(state = PREP_HEADER and c_wr_int = '0' and wait_clk = 0 and aligned = '0' and data_len /= ZERO_10B)) then
data_to_ava <= ("00" & data_len) + THREE_12B;
elsif(state = PREP_HEADER and c_wr_int = '1' and wait_clk = 1 and addr_int(2) = '0') then
data_to_ava <= ('0' & data_from_fifo) + FOUR_12B;
elsif(state = PREP_HEADER and c_wr_int = '1' and wait_clk = 1 and addr_int(2) = '1') then
data_to_ava <= ('0' & data_from_fifo) + THREE_12B;
elsif(state = TRANSMIT and data_to_ava > ONE_12B and tx_st_valid0_int = '1') then
data_to_ava <= data_to_ava - "10";
elsif((state = START_TRANS and data_enable_int = '1' and data_to_ava = 1) or (state = TRANSMIT and data_enable_int = '1' and data_to_ava <= ONE_12B)) then
data_to_ava <= (others => '0');
end if;
if(state = IDLE or state = PREP_HEADER or (tx_st_ready0 = '0' and (state = TRANSMIT or state = START_TRANS))) then
ready_q <= '0';
elsif(tx_st_ready0 = '1' and (state = TRANSMIT or state = START_TRANS)) then
ready_q <= '1';
end if;
-- use wait_clk to enable processing at the right point of time
if(state = IDLE or (state = PREP_TRANS and ((wait_clk = 2 and c_wr_int = '0') or (wait_clk = 1 and c_wr_int = '1'))) or
(state = PREP_HEADER and wait_clk = 3)) then
wait_clk <= 0;
elsif((state = PREP_TRANS and (c_wr_int = '1' or (c_wr_int = '0' and tx_c_head_empty = '0'))) or
(state = PREP_HEADER and wait_clk /= 3)) then
wait_clk <= wait_clk + 1;
end if;
-- if power off request occured, save it for later processing
if(pme_to_sr = '1' and (state = IDLE or state = PREP_TRANS or state = PREP_HEADER or state = START_TRANS or state = TRANSMIT
or state = TAG_START or state = ABORT)) then
pme_off_int <= '1';
elsif(state = PME_OFF or (state = IDLE and pme_to_sr = '0')) then
pme_off_int <= '0';
end if;
-- disable or enable data retrieval from FIFO
if(state = IDLE or
(state = ABORT and data_from_fifo <= 2) or
(state = PREP_HEADER and ((wait_clk = 1 and c_wr_int = '0' and abort_compl_int = '0') or (wait_clk = 2 and c_wr_int = '1' and
wr_rd = '0'))) or
(state = START_TRANS and ((tx_st_ready0 = '0' and data_from_fifo = ONE_11B) or
(ready_q = '1' and c_wr_int = '0' and data_from_fifo <= 1) or
(c_wr_int = '1' and fifo_enable_int = '1' and ((data_len(0) = '1' and data_from_fifo = ONE_11B) or (data_len(0) = '0' and
data_from_fifo = TWO_11B))))) or
(state = TRANSMIT and (tx_st_ready0 = '0' or (data_from_fifo <= TWO_11B and get_last_packet = '0')))) then
fifo_enable_int <= '0';
elsif((state = START_TRANS and tx_st_ready0 = '1' and data_from_fifo > ZERO_11B and (c_wr_int = '1' or (c_wr_int = '0' and
abort_compl_int = '0'))) or (state = ABORT and data_from_fifo > TWO_11B) or
(state = PREP_HEADER and ((wait_clk = 0 and c_wr_int = '0' and abort_compl_int = '0') or (wait_clk = 1 and c_wr_int = '1' and
wr_rd = '0'))) or
(state = TRANSMIT and tx_st_ready0 = '1') ) then
fifo_enable_int <= '1';
end if;
-- if packet length is greater than allowed payload size, set payload_loop_en = 1 and do internal loop until desired
-- packet length is sent using multiple TLPs
-- don't forget to adapt packet address after each loop
if(state = IDLE or
(state = PREP_HEADER and c_wr_int = '1' and wr_rd = '0' and desired_len > 0 and wait_clk = 1 and desired_len <= data_from_fifo)) then
payload_loop_en <= '0';
elsif(state = PREP_HEADER and desired_len = 0 and c_wr_int = '1' and wr_rd = '0' and wait_clk = 0 and
((data_len = ZERO_10B and data_len /= max_payload_len) or (data_len /= ZERO_10B and data_len > max_payload_len))) then
payload_loop_en <= '1';
end if;
if(state = IDLE) then
addr_int <= (others => '0');
-- calculate internal address used if transaction must be split into more parts
elsif(state = PREP_HEADER and wait_clk = 0) then
addr_int <= orig_addr + addr_offset;
end if;
-- calculate address offset for internal address calculation
if(state = IDLE) then
addr_offset <= (others => '0');
elsif((state = PREP_HEADER and wait_clk = 2 and c_wr_int = '1' and wr_rd = '0') or
(state = START_TRANS and fifo_enable_int = '1' and c_wr_int = '1') or
(state = TRANSMIT and fifo_enable_int = '1' and c_wr_int = '1' and data_from_fifo > ZERO_12B)) then
addr_offset <= addr_offset + ADDR_INCR;
end if;
case state is
when IDLE =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
own_id_int <= bus_dev_func;
when PREP_HEADER =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when PREP_TRANS =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when START_TRANS =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when TRANSMIT =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when PME_OFF =>
pme_to_cr <= '1';
start <= '0';
start_tag_nbr <= (others => '0');
when TAG_START =>
pme_to_cr <= '0';
start <= '1';
start_tag_nbr <= tag_nbr_cntr;
tag_nbr_cntr <= tag_nbr_cntr + '1';
when ABORT =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
when others =>
pme_to_cr <= '0';
start <= '0';
start_tag_nbr <= (others => '0');
end case;
end if;
end process fsm_out;
-------------------------------------------------------------------------------
end architecture tx_ctrl_arch;
| gpl-3.0 | e23bd1b35e26a83f7db8d64561a31740 | 0.49417 | 3.603163 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/common/asyncwrite.vhd | 1 | 1,653 | library ieee;
use ieee.std_logic_1164.all;
--use work.config.all;
-- ASYNCWRITE: data from asynchronous clock write to register with synchronous clock
-- reset : global reset
-- async_clk : clock of source data
-- async_wren : source data valid
-- sync_clk : clock of destination register
-- trigger : condition when destination register can be written
-- sync_wren : destination register writing enabled
-- over : destination register writing finished
-- flag : source data in but destination register not written
entity ASYNCWRITE is
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end ASYNCWRITE;
architecture ASYNCWRITE of ASYNCWRITE is
signal flag1: std_logic;
signal flag2: std_logic;
signal flag3: std_logic;
begin
async: process( async_clk, reset )
begin
if reset = '1' then
flag1 <= '0';
elsif rising_edge(async_clk) then
if async_wren = '1' then
flag1 <= not flag1;
end if;
end if;
end process async;
sync: process( sync_clk, reset )
begin
if reset = '1' then
flag2 <= '0';
flag3 <= '0';
over <= '0';
elsif rising_edge(sync_clk) then
flag2 <= flag1;
if flag2 /= flag3 and trigger = '1' then
flag3 <= not flag3;
over <= '1';
else
over <= '0';
end if;
end if;
end process sync;
sync_wren <= '1' when flag2 /= flag3 and trigger='1' else '0';
flag <= '1' when flag1/=flag2 or flag2/=flag3 else '0';
end ASYNCWRITE;
| gpl-2.0 | 2dc299c09b192878ae760892bb404859 | 0.635814 | 3.112994 | false | false | false | false |
michaelmiehling/A25_VME | 16z126-01_src/Source/z126_01_ru_ctrl_cyc5.vhd | 1 | 30,439 | ---------------------------------------------------------------
-- Title : Remote Update Control
-- Project : General IP-core
---------------------------------------------------------------
-- Author : Andreas Geissler
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 14.0.2
---------------------------------------------------------------
-- Description : The module is used to control the
-- serial loading of the FPGA image using the
-- altera remote update block.
---------------------------------------------------------------
-- Hierarchy:
-- z126_01_ru_ctrl_cyc5.vhd
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: z126_01_ru_ctrl_cyc5.vhd,v $
-- Revision 1.3 2015/02/18 16:58:36 AGeissler
-- R1: The remote update controller for CYCLONE V from altera
-- needs a startup time to initialize the internal registers
-- M1: Added state START_UP_WAIT to wait 128 clock cycles
-- R2: Missing data out for state WRITE_CURR_STATE
-- M2: Write 1 to configuration mode (AnF)
-- R3: Wrong bit ordering for reconfig_cond register because of change
-- internal register bits meaning for CYCLONE V
-- M3: Changed assignment to connect the register that the bit meaning
-- is equal to CYCLONE IV
-- R4: Wrong transition from CHECK_STATE to WRITE_CURR_STATE
-- M4: Changed transition to WRITE_BOOT_ADDR and adjust ru_ctrl_param
-- R5: The boot address is read wrong, it could be connected directly
-- M5: Changed boot address assignment
--
-- Revision 1.2 2014/12/02 10:32:27 AGeissler
-- R1: The watchdog value is not correctly set, so that the user image could not
-- be loaded
-- M1: Changed param value from enable to value
--
-- Revision 1.1 2014/11/24 16:44:18 AGeissler
-- Initial Revision
--
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
USE work.z126_01_pkg.all;
ENTITY z126_01_ru_ctrl_cyc5 IS
GENERIC
(
FPGA_FAMILY : family_type := CYCLONE5; -- see SUPPORTED_FPGA_FAMILIES for supported FPGA family types
LOAD_FPGA_IMAGE : boolean := TRUE; -- true => after configuration of the FPGA Fallback Image the FPGA Image is loaded immediately (can only be set when USE_REMOTE_UPDATE = TRUE)
-- false => after configuration the FPGA stays in the FPGA Fallback Image, FPGA Image must be loaded by software
LOAD_FPGA_IMAGE_ADR : std_logic_vector(23 DOWNTO 0) := (OTHERS=>'0') -- if LOAD_FPGA_IMAGE = TRUE this address is the offset to the FPGA Image in the serial flash
);
PORT
(
clk : IN std_logic; -- system clock
rst : IN std_logic; -- unit ru_ctrl_reset
-- register interface
wbs_reg_cyc : IN std_logic;
wbs_reg_ack : OUT std_logic;
wbs_reg_we : IN std_logic;
wbs_reg_sel : IN std_logic_vector(3 DOWNTO 0);
wbs_reg_dat_o : OUT std_logic_vector(31 DOWNTO 0);
wbs_reg_dat_i : IN std_logic_vector(31 DOWNTO 0);
reg_reconfig : IN std_logic; -- reconfiguration trigger from register interface
reg_reconfig_cond : OUT std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
reg_board_status : OUT std_logic_vector(1 DOWNTO 0); -- gives information whether the loading process was successful or not
-- ALTREMOTE_UPDATE interface
ru_ctrl_busy : IN std_logic;
ru_ctrl_data_out : IN std_logic_vector(23 DOWNTO 0); -- data from altera remote update module
ru_ctrl_data_in : OUT std_logic_vector(23 DOWNTO 0); -- data to altera remote update module
ru_ctrl_param : OUT std_logic_vector(2 DOWNTO 0);
ru_ctrl_read_param : OUT std_logic;
ru_ctrl_reconfig : OUT std_logic;
ru_ctrl_reset_timer : OUT std_logic;
ru_ctrl_reset : OUT std_logic;
ru_ctrl_write_param : OUT std_logic
);
END z126_01_ru_ctrl_cyc5;
ARCHITECTURE z126_01_ru_ctrl_cyc5_arch OF z126_01_ru_ctrl_cyc5 IS
TYPE ru_ctrl_states IS (IDLE,
START_UP_WAIT,
READ_CURR_STATE,
READ_RECONFIG_COND,
CHECK_STATE,
WRITE_CURR_STATE,
WRITE_BOOT_ADDR,
WRITE_WATCHDOG_VALUE,
WRITE_WATCHDOG_ENABLE,
RECONFIGURE,
FPGA_IMAGE,
FALLBACK_IMAGE,
WRITE_BOOT_ADDR_WB_FALLBACK,
READ_BOOT_ADDR_WB_FALLBACK,
READ_BOOT_ADDR_WB_FGPA_IMAGE
);
CONSTANT SUPPORTED_DEVICES : supported_family_types := (CYCLONE3, CYCLONE4);
SIGNAL ru_ctrl_state : ru_ctrl_states := IDLE; -- remote update control block state signal
-- registers
SIGNAL reconfig_cond : std_logic_vector(4 DOWNTO 0); -- reconfiguration trigger condition of last reconfiguration
SIGNAL curr_state : std_logic; -- current state of fpga
-- '1' => A FPGA image is loaded
-- '0' => Fallback FPGA image is loaded
SIGNAL boot_addr : std_logic_vector(23 DOWNTO 0); -- fpga boot addr (only write able in Factory Mode)
SIGNAL board_status : std_logic_vector(1 DOWNTO 0); -- current state of fpga
-- delayed busy signal
SIGNAL ru_ctrl_busy_q : std_logic := '0'; -- used for edge detection
SIGNAL ru_ctrl_busy_qq : std_logic := '0'; -- used for delayed edge detection (for generate wb ack)
-- wishbone ack
SIGNAL wbs_reg_ack_int : std_logic := '0'; -- wishbone acknowledge internal
-- reset
SIGNAL reset_timer_int : std_logic := '0'; -- reset watchdog timer (triggers on falling edge)
SIGNAL reset_timer_cnt : std_logic_vector(15 DOWNTO 0); -- counter for reset watchdog timer (the watchdog reset must
-- be active for at least 250 ns!!)
-- startup counter
SIGNAL startup_cnt : unsigned(7 DOWNTO 0); -- startup count for FPGA initialization
BEGIN
-- wishbone data out
wbs_reg_dat_o <= x"00" & boot_addr;
wbs_reg_ack <= wbs_reg_ack_int;
-- data to remote update controller
ru_ctrl_dat_in_proc : PROCESS (ru_ctrl_state, boot_addr) IS
BEGIN
CASE ru_ctrl_state IS
WHEN WRITE_BOOT_ADDR_WB_FALLBACK =>
ru_ctrl_data_in <= boot_addr(23 DOWNTO 0);
WHEN WRITE_BOOT_ADDR =>
ru_ctrl_data_in <= LOAD_FPGA_IMAGE_ADR(23 DOWNTO 0);
WHEN WRITE_WATCHDOG_ENABLE =>
-- enable watchdog
ru_ctrl_data_in <= x"000001";
WHEN WRITE_WATCHDOG_VALUE =>
-- the first 12 bit are the highest 12 bit (of 29 bit) in the watchdog timer value
ru_ctrl_data_in <= x"000" & x"100"; -- => 33554432 clock cycle (2^25) => ~1 sec
WHEN WRITE_CURR_STATE =>
ru_ctrl_data_in <= x"000001"; -- write '1' to Configuration Mode (AnF)
WHEN OTHERS =>
ru_ctrl_data_in <= x"000000";
END CASE;
END PROCESS;
-- reset remote update controller when reconfiguration from FPGA Image
ru_ctrl_reset <= rst; -- reset remote update controller
ru_ctrl_reconfig <= '1' WHEN ru_ctrl_state = RECONFIGURE ELSE '0'; -- start reconfiguration
ru_ctrl_reset_timer <= reset_timer_int; -- reset watchdog timer
-- register out
reg_reconfig_cond <= reconfig_cond; -- reconfiguration trigger condition of last reconfiguration
reg_board_status <= board_status; -- gives information whether the loading process was successful or not
-- wishbone acknowledge and watchdog counter
ru_ctrl_wb_ack_and_wdog_cnt_proc : PROCESS (clk, rst) IS
BEGIN
IF rst = '1' THEN
wbs_reg_ack_int <= '0';
reset_timer_cnt <= (OTHERS=>'0');
ELSIF rising_edge(clk) THEN
-- wishbone acknowledge
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' AND wbs_reg_ack_int = '0' THEN
wbs_reg_ack_int <= '1';
ELSIF wbs_reg_cyc = '1' AND wbs_reg_we = '0' AND ru_ctrl_busy_qq = '1' AND ru_ctrl_busy_q = '0' THEN
-- read acknowledge when busy falling edge delayed by 1 cycle (1 cycle needed to write the register)
wbs_reg_ack_int <= '1';
ELSE
wbs_reg_ack_int <= '0';
END IF;
-- watchdog counter
IF ru_ctrl_state = FPGA_IMAGE THEN
reset_timer_cnt <= std_logic_vector(unsigned(reset_timer_cnt) + 1);
ELSE
reset_timer_cnt <= (OTHERS=>'0');
END IF;
END IF;
END PROCESS;
ru_ctrl_cyc5_proc : PROCESS (clk, rst) IS
BEGIN
IF rst = '1' THEN
ru_ctrl_state <= IDLE;
ru_ctrl_param <= (OTHERS=>'0');
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ru_ctrl_busy_q <= '0';
ru_ctrl_busy_qq <= '0';
reconfig_cond <= (OTHERS=>'0');
curr_state <= '0';
board_status <= (OTHERS=>'0');
boot_addr <= (OTHERS=>'0');
startup_cnt <= (OTHERS=>'0');
reset_timer_int <= '0';
ELSIF falling_edge(clk) THEN
ru_ctrl_busy_q <= ru_ctrl_busy;
ru_ctrl_busy_qq <= ru_ctrl_busy_q;
-- board status register
IF (ru_ctrl_state = CHECK_STATE
AND ( reconfig_cond(3) = '1' -- CRC-Error
OR reconfig_cond(2) = '1' -- nStatus triggered
OR reconfig_cond(1) = '1' -- watchdog timeout
) ) THEN
board_status <= "10"; -- error while loading image (FPGA Fallback Image is loaded!)
ELSIF curr_state = '1' THEN
board_status <= "01"; -- FPGA Image loaded
END IF;
-- last reconfiguration condition register
IF ru_ctrl_state = READ_RECONFIG_COND AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- The register reconfig_cond shall have the same bit meaning as for Cyclone IV devices
reconfig_cond(0) <= ru_ctrl_data_out(2); -- runconfig_source - Configuration reset triggered from logic array.
reconfig_cond(1) <= ru_ctrl_data_out(4); -- wdtimer_source - User Watchdog Timer timeout.
reconfig_cond(2) <= ru_ctrl_data_out(1); -- nstatus_source - nSTATUS asserted by an external device as the result of an error
reconfig_cond(3) <= ru_ctrl_data_out(0); -- crcerror_source - CRC error during application configuration
reconfig_cond(4) <= ru_ctrl_data_out(3); -- nconfig_source - External configuration reset (nCONFIG) assertion.
END IF;
-- current state register
IF ru_ctrl_state = READ_CURR_STATE AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
curr_state <= ru_ctrl_data_out(0); -- get data from remote update block
END IF;
-- boot address register
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' THEN
IF wbs_reg_sel(0) = '1' THEN
boot_addr(7 DOWNTO 2) <= wbs_reg_dat_i(7 DOWNTO 2);
END IF;
IF wbs_reg_sel(1) = '1' THEN
boot_addr(15 DOWNTO 8) <= wbs_reg_dat_i(15 DOWNTO 8);
END IF;
IF wbs_reg_sel(2) = '1' THEN
boot_addr(23 DOWNTO 16) <= wbs_reg_dat_i(23 DOWNTO 16);
END IF;
ELSIF ru_ctrl_state = READ_BOOT_ADDR_WB_FALLBACK AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- read boot address from remote update controller at falling edge of busy signal
-- on FPGA Fallback Image the boot address width is 22 bit
boot_addr <= ru_ctrl_data_out(23 DOWNTO 0);
ELSIF ru_ctrl_state = READ_BOOT_ADDR_WB_FGPA_IMAGE AND ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- read boot address from remote update controller at falling edge of busy signal
-- on FPGA Image the boot address width is 22 bit
boot_addr <= ru_ctrl_data_out(23 DOWNTO 0);
END IF;
CASE ru_ctrl_state IS
WHEN IDLE =>
-- read current state of remote update controller
ru_ctrl_state <= START_UP_WAIT;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- master StateMachineCurrent StateMode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
WHEN START_UP_WAIT =>
-- wait for falling edge of delayed busy signal (wait until curr_state is written)
IF startup_cnt(startup_cnt'HIGH) = '1' THEN
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- master StateMachineCurrent StateMode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
startup_cnt <= (OTHERS=>'0');
ELSE
ru_ctrl_state <= START_UP_WAIT;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- master StateMachineCurrent StateMode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
startup_cnt <= startup_cnt + 1;
END IF;
WHEN READ_CURR_STATE =>
-- wait for falling edge of delayed busy signal (wait until curr_state is written)
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' AND curr_state = '0' THEN
-- read reconfiguration trigger condition source when in Factory Mode
ru_ctrl_state <= READ_RECONFIG_COND;
ru_ctrl_param <= Z126_01_RU_RECONF_CON_PAR_CYC5; -- reconfiguration trigger condition source
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- the FPGA Image is successfully loaded
-- the reconfiguration condition can only be read in Factory Mode!
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle longer to store data in curr_state register
-- disable remote update controller access
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read current state of remote update controller
ru_ctrl_state <= READ_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- read current state
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_RECONFIG_COND =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- check in which state is the FPGA
ru_ctrl_state <= CHECK_STATE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read reconfiguration trigger condition source
ru_ctrl_state <= READ_RECONFIG_COND;
ru_ctrl_param <= Z126_01_RU_RECONF_CON_PAR_CYC5; -- reconfiguration trigger condition source
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
END IF;
WHEN CHECK_STATE =>
IF LOAD_FPGA_IMAGE = TRUE AND reconfig_cond(3) = '0' AND reconfig_cond(2) = '0' AND reconfig_cond(1) = '0' THEN
-- we are still in the FPGA Fallback Image and no error
-- start loading the FPGA Image (enable watchdog, write boot address and write current state)
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- the FPGA Fallback Image is loaded
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
END IF;
WHEN WRITE_WATCHDOG_VALUE =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- enable watchdog
ru_ctrl_state <= WRITE_WATCHDOG_ENABLE;
ru_ctrl_param <= Z126_01_RU_WDOG_EN_PAR_CYC5; -- watchdog enable
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- write watchdog time out value
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC5; -- watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN WRITE_WATCHDOG_ENABLE =>
-- wait for falling edge of busy signal
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- write current mode to '1' => FPGA Image
ru_ctrl_state <= WRITE_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- write current mode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- enable watchdog
ru_ctrl_state <= WRITE_WATCHDOG_ENABLE;
ru_ctrl_param <= Z126_01_RU_WDOG_EN_PAR_CYC5; -- watchdog enable
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN WRITE_CURR_STATE =>
-- wait for falling edge of delayed busy signal (wait until curr_state is written)
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- reconfiguration
ru_ctrl_state <= RECONFIGURE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- write current mode to '1' => FPGA Image
ru_ctrl_state <= WRITE_CURR_STATE;
ru_ctrl_param <= Z126_01_RU_CONF_MODE_PAR_CYC5; -- write current mode
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN WRITE_BOOT_ADDR =>
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- write watchdog time out value and start reconfiguration
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC5; -- watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
WHEN RECONFIGURE =>
-- start reconfiguration
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
-- fpga should be reconfigurated so the fsm should stay in this state
-- until the reconfiguration is finished
ru_ctrl_state <= RECONFIGURE;
WHEN FPGA_IMAGE =>
-- reset the watchdog timer if the FPGA Image is successfully loaded
-- (the watchdog timer is reset on falling edge of reset_timer_int)
-- if the watchdog expires the FPGA Fallback Image will be loaded again
reset_timer_int <= reset_timer_cnt(reset_timer_cnt'high);
IF wbs_reg_cyc = '1' AND wbs_reg_we = '0' THEN
-- indirecte interface register access read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
ELSIF reg_reconfig = '1' THEN
-- start reconfiguration
ru_ctrl_state <= RECONFIGURE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- stay in FPGA Image
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
END IF;
WHEN FALLBACK_IMAGE =>
IF wbs_reg_cyc = '1' AND wbs_reg_we = '1' THEN
-- indirecte interface register access write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSIF wbs_reg_cyc = '1' AND wbs_reg_we = '0' THEN
-- indirecte interface register access read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- read access
ru_ctrl_write_param <= '0';
ELSIF reg_reconfig = '1' THEN
-- enable watchdog and start reconfiguration
ru_ctrl_state <= WRITE_WATCHDOG_VALUE;
ru_ctrl_param <= Z126_01_RU_WDOG_VAL_PAR_CYC5; -- set watchdog value
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
ELSE
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_BOOT_ADDR_WB_FALLBACK =>
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- write access
ru_ctrl_write_param <= '0';
END IF;
WHEN READ_BOOT_ADDR_WB_FGPA_IMAGE =>
IF ru_ctrl_busy_q = '0' AND ru_ctrl_busy_qq = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- stay in FPGA Image
ru_ctrl_state <= FPGA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSIF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- wait one cycle longer to acknowledge the wishbone bus with the correct data
-- disable remote update controller access
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- read boot address
ru_ctrl_state <= READ_BOOT_ADDR_WB_FGPA_IMAGE;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '1'; -- write access
ru_ctrl_write_param <= '0';
END IF;
WHEN WRITE_BOOT_ADDR_WB_FALLBACK =>
IF ru_ctrl_busy = '0' AND ru_ctrl_busy_q = '1' THEN
-- stay in FPGA Fallback Image
ru_ctrl_state <= FALLBACK_IMAGE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
ELSE
-- write boot address
ru_ctrl_state <= WRITE_BOOT_ADDR_WB_FALLBACK;
ru_ctrl_param <= Z126_01_RU_PAGE_SEL_PAR_CYC5; -- boot address
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '1'; -- write access
END IF;
-- coverage off
WHEN OTHERS =>
ru_ctrl_state <= IDLE;
ru_ctrl_param <= "000";
ru_ctrl_read_param <= '0';
ru_ctrl_write_param <= '0';
-- coverage on
END CASE;
END IF;
END PROCESS;
END z126_01_ru_ctrl_cyc5_arch;
| gpl-3.0 | adbf124e55f93f10d3e3d6b3834c40dd | 0.471599 | 4.379082 | false | true | false | false |
a4a881d4/zcpsm | src/zcpsm/core/shiftR.vhd | 1 | 807 | library ieee;
use ieee.std_logic_1164.all;
ENTITY shiftR IS
generic (
width : integer := 8
);
port (
A: IN std_logic_VECTOR(width-1 downto 0);
Ci: In std_logic;
OP: IN std_logic_vector( 2 downto 0);
S: OUT std_logic_VECTOR(width-1 downto 0);
Co: out std_logic
);
END shiftR;
ARCHITECTURE behavior OF shiftR IS
begin
process( A, OP, Ci )
begin
S(width-2 downto 0) <= A(width-1 downto 1);
Co <= A(0);
case OP is
when "110" => --SR0
S(width-1) <= '0';
when "111" => --SR1
S(width-1) <= '1';
when "010" => --SRX
S(width-1) <= A(width-1);
when "000" => --SRA
S(width-1) <= Ci;
when "100" => --RR
S(width-1) <= A(0);
when others =>
S(width-1) <= '0';
end case;
end process;
end behavior;
| gpl-2.0 | 2cc60ebc42d0af7a7a9f6199f231351a | 0.52912 | 2.483077 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_two_v1_00_a/hdl/vhdl/hw_acc_two.vhd | 2 | 7,966 | ------------------------------------------------------------------------------
-- add_sub_core - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: add_sub_core
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Thu Aug 9 10:06:10 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_two is
port
(
Tintrfc2thrd_value : out std_logic_vector(0 to 31);
Tintrfc2thrd_function : out std_logic_vector(0 to 15);
Tintrfc2thrd_goWait : out std_logic;
Tthrd2intrfc_address : out std_logic_vector(0 to 31);
Tthrd2intrfc_value : out std_logic_vector(0 to 31);
Tthrd2intrfc_function : out std_logic_vector(0 to 15);
Tthrd2intrfc_opcode : out std_logic_vector(0 to 5);
Ttimer : out std_logic_vector( 0 to 31);
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
FSL1_M_Write : out std_logic;
FSL1_M_Data : out std_logic_vector(0 to 31);
FSL1_M_Full : in std_logic;
FSL2_M_Write : out std_logic;
FSL2_M_Data : out std_logic_vector(0 to 31);
FSL2_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
end hw_acc_two;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_two is
component user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic ;
full : in std_logic ;
Ttimer : out std_logic_vector( 0 to 31)
);
end component user_logic_hwtul;
signal intrfc2thrd : std_logic_vector(0 to 63);
signal thrd2intrfc : std_logic_vector( 0 to 95);
signal rd : std_logic;
signal wr : std_logic;
signal exist : std_logic;
signal full : std_logic;
signal timer : std_logic_vector( 0 to 31) ;
-- Architecture Section
begin
Tintrfc2thrd_value <= intrfc2thrd(0 to 31) ;
Tintrfc2thrd_function <= intrfc2thrd (32 to 47);
Tintrfc2thrd_goWait <= exist ;
Tthrd2intrfc_address <= thrd2intrfc (32 to 63);
Tthrd2intrfc_value <= thrd2intrfc (0 to 31) ;
Tthrd2intrfc_function <= thrd2intrfc (64 to 79);
Tthrd2intrfc_opcode <= thrd2intrfc (80 to 85);
Ttimer <= timer;
intrfc2thrd <= FSL0_S_Data & FSL1_S_Data;
FSL0_M_Data <= thrd2intrfc(0 to 31);
FSL1_M_Data <= thrd2intrfc(32 to 63);
FSL2_M_Data <= thrd2intrfc(64 to 95);
--=======================================================
full <= FSL0_M_Full or FSL1_M_Full or FSL2_M_Full;
exist <= FSL0_S_Exists and FSL1_S_Exists ;
--=======================================================
FSL0_S_Read <= rd;
FSL1_S_Read <= rd;
FSL0_M_Write <= wr;
FSL1_M_Write <= wr;
FSL2_M_Write <= wr;
USER_LOGIC_HWTUL_I : user_logic_hwtul
port map
(
clock => FSL_Clk,
intrfc2thrd => intrfc2thrd,
thrd2intrfc => thrd2intrfc,
rd => rd,
wr => wr,
exist => exist,
full => full,
Ttimer => timer
);
end architecture implementation;
| bsd-3-clause | 25253431ab22e070274584f236e19092 | 0.472634 | 4.179433 | false | false | false | false |
QuickJack/logi-hard | hdl/wishbone/peripherals/wishbone_register.vhd | 1 | 3,721 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:29:34 07/31/2013
-- Design Name:
-- Module Name: wishbone_register - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_wishbone_peripherals_pack.all ;
entity wishbone_register is
generic(
wb_size : natural := 16; -- Data port size for wishbone
nb_regs : natural := 1
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
reg_out : out slv16_array(0 to nb_regs-1);
reg_in : in slv16_array(0 to nb_regs-1)
);
end wishbone_register;
architecture Behavioral of wishbone_register is
signal reg_in_d, reg_out_d : slv16_array(0 to nb_regs-1) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others =>(others => '0'));
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d(conv_integer(wbs_address)) <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
reg_out <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
reg_in_d <= reg_in ; -- latching inputs
wbs_readdata <= reg_in_d(conv_integer(wbs_address)) ; -- this is not clear if this should only happen in the read part
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
| lgpl-3.0 | 6b0a03786ab580ff2fb7fb7ae884d9fa | 0.594464 | 3.70987 | false | false | false | false |
jevinskie/aes-over-pcie | source/aes_rcu.vhd | 1 | 12,834 | -- File name: aes_rcu.vhd
-- Created: 2009-03-30
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.1 Initial Design Entry
-- Description: Rijndael RCU
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity aes_rcu is
port (
clk : in std_logic;
nrst : in std_logic;
key_done : in std_logic;
got_key : in std_logic;
got_pt : in std_logic;
send_ct : in std_logic;
p : out g_index;
subblock : out subblock_type;
current_round : out round_type;
start_key : out std_logic;
key_load : out std_logic;
aes_done : out std_logic
);
end entity aes_rcu;
architecture behavioral of aes_rcu is
type state_type is (
idle, e_idle, load_pt, load_key, sub_bytes,
mix_columns, shift_rows, add_round_key,
key_scheduler_start, key_scheduler_wait,
round_start, round_end, block_done, store_ct
);
signal state, next_state : state_type;
signal round_count, next_round_count : round_type;
signal round_count_up, round_count_clr : std_logic;
signal i, next_i : g_index;
signal i_up, i_clr : std_logic;
begin
fsm_reg : process(clk, nrst)
begin
if (nrst = '0') then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process fsm_reg;
fsm_nsl : process(state, round_count, i, key_done, got_pt, got_key, send_ct)
begin
next_state <= state;
case state is
when idle =>
if (got_key = '1') then
next_state <= load_key;
elsif (got_pt = '1') then
next_state <= load_pt;
elsif (send_ct = '1') then
next_state <= store_ct;
else
next_state <= idle;
end if;
when e_idle =>
next_state <= e_idle;
when load_key =>
if (i /= 15) then
next_state <= load_key;
else
next_state <= idle;
end if;
when load_pt =>
if (i /= 15) then
next_state <= load_pt;
else
next_state <= round_start;
end if;
when store_ct =>
if (i /= 15) then
next_state <= store_ct;
else
next_state <= idle;
end if;
when round_start =>
next_state <= key_scheduler_start;
when key_scheduler_start =>
next_state <= key_scheduler_wait;
when key_scheduler_wait =>
if (key_done = '0') then
next_state <= key_scheduler_wait;
elsif (round_count = 0) then
next_state <= add_round_key;
else
next_state <= sub_bytes;
end if;
when sub_bytes =>
if (i /= 15) then
next_state <= sub_bytes;
else
next_state <= shift_rows;
end if;
when shift_rows =>
if (i /= 3) then
next_state <= shift_rows;
elsif (round_count /= 10) then
next_state <= mix_columns;
else
next_state <= add_round_key;
end if;
when mix_columns =>
if (i /= 3) then
next_state <= mix_columns;
else
next_state <= add_round_key;
end if;
when add_round_key =>
if (i /= 15) then
next_state <= add_round_key;
else
next_state <= round_end;
end if;
when round_end =>
if (round_count /= 10) then
next_state <= round_start;
else
next_state <= block_done;
end if;
when block_done =>
next_state <= idle;
when others =>
-- nothing
end case;
end process fsm_nsl;
fsm_output : process(state, i)
begin
i_clr <= '0';
i_up <= '0';
round_count_clr <= '0';
round_count_up <= '0';
start_key <= '0';
aes_done <= '0';
key_load <= '0';
subblock <= identity;
case state is
when idle =>
subblock <= identity;
i_clr <= '1';
round_count_clr <= '1';
when e_idle =>
subblock <= identity;
i_clr <= '1';
round_count_clr <= '1';
when load_key =>
subblock <= identity;
key_load <= '1';
i_up <= '1';
when load_pt =>
subblock <= load_pt;
i_up <= '1';
when store_ct =>
subblock <= store_ct;
i_up <= '1';
when sub_bytes =>
subblock <= sub_bytes;
i_up <= '1';
when shift_rows =>
subblock <= shift_rows;
i_up <= '1';
if (i = 3) then
i_clr <= '1';
end if;
when mix_columns =>
subblock <= mix_columns;
i_up <= '1';
if (i = 3) then
i_clr <= '1';
end if;
when add_round_key =>
subblock <= add_round_key;
i_up <= '1';
when key_scheduler_start =>
subblock <= identity;
start_key <= '1';
when key_scheduler_wait =>
subblock <= identity;
when round_start =>
subblock <= identity;
when round_end =>
subblock <= identity;
round_count_up <= '1';
when block_done =>
aes_done <= '1';
when others =>
-- nothing
end case;
end process fsm_output;
-- leda C_1406 off
round_count_reg : process(clk)
begin
if rising_edge(clk) then
round_count <= next_round_count;
end if;
end process round_count_reg;
-- leda C_1406 on
round_count_nsl : process(round_count, round_count_up, round_count_clr)
variable nrc : round_type;
begin
if (round_count_clr = '1') then
next_round_count <= 0;
elsif (round_count_up = '1') then
if (round_count = 11) then
nrc := 0;
else
nrc := round_count + 1;
end if;
next_round_count <= nrc;
else
next_round_count <= round_count;
end if;
end process round_count_nsl;
-- leda C_1406 off
i_reg : process(clk)
begin
if rising_edge(clk) then
i <= next_i;
end if;
end process i_reg;
-- leda C_1406 on
i_nsl : process(i, i_up, i_clr)
begin
if (i_clr = '1') then
next_i <= 0;
elsif (i_up = '1') then
next_i <= to_integer(to_unsigned(i, 4) + 1);
else
next_i <= i;
end if;
end process i_nsl;
current_round <= round_count;
p <= i;
end architecture behavioral;
architecture behavioral_p of aes_rcu is
type state_type is (
idle, e_idle, load_pt, load_key, sub_bytes,
mix_columns, shift_rows, add_round_key,
key_scheduler_start, key_scheduler_wait,
round_start, round_end, block_done, store_ct
);
signal state, next_state : state_type;
signal round_count, next_round_count : round_type;
signal round_count_up, round_count_clr : std_logic;
signal i, next_i : g_index;
signal i_up, i_clr : std_logic;
begin
fsm_reg : process(clk, nrst)
begin
if (nrst = '0') then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process fsm_reg;
fsm_nsl : process(state, round_count, i, key_done, got_pt, got_key, send_ct)
begin
next_state <= state;
case state is
when idle =>
if (got_key = '1') then
next_state <= load_key;
elsif (got_pt = '1') then
next_state <= load_pt;
elsif (send_ct = '1') then
next_state <= store_ct;
else
next_state <= idle;
end if;
when e_idle =>
next_state <= e_idle;
when load_key =>
if (i /= 15) then
next_state <= load_key;
else
next_state <= idle;
end if;
when load_pt =>
if (i /= 15) then
next_state <= load_pt;
else
next_state <= round_start;
end if;
when store_ct =>
if (i /= 15) then
next_state <= store_ct;
else
next_state <= idle;
end if;
when round_start =>
next_state <= key_scheduler_start;
when key_scheduler_start =>
next_state <= key_scheduler_wait;
when key_scheduler_wait =>
if (key_done = '0') then
next_state <= key_scheduler_wait;
elsif (round_count = 0) then
next_state <= add_round_key;
else
next_state <= sub_bytes;
end if;
when sub_bytes =>
next_state <= shift_rows;
when shift_rows =>
if (round_count /= 10) then
next_state <= mix_columns;
else
next_state <= add_round_key;
end if;
when mix_columns =>
next_state <= add_round_key;
when add_round_key =>
next_state <= round_end;
when round_end =>
if (round_count /= 10) then
next_state <= round_start;
else
next_state <= block_done;
end if;
when block_done =>
next_state <= idle;
when others =>
-- nothing
end case;
end process fsm_nsl;
fsm_output : process(state, i)
begin
i_clr <= '0';
i_up <= '0';
round_count_clr <= '0';
round_count_up <= '0';
start_key <= '0';
aes_done <= '0';
key_load <= '0';
subblock <= identity;
case state is
when idle =>
subblock <= identity;
i_clr <= '1';
round_count_clr <= '1';
when e_idle =>
subblock <= identity;
i_clr <= '1';
round_count_clr <= '1';
when load_key =>
subblock <= identity;
key_load <= '1';
i_up <= '1';
when load_pt =>
subblock <= load_pt;
i_up <= '1';
when store_ct =>
subblock <= store_ct;
i_up <= '1';
when sub_bytes =>
subblock <= sub_bytes;
i_up <= '1';
when shift_rows =>
subblock <= shift_rows;
when mix_columns =>
subblock <= mix_columns;
when add_round_key =>
subblock <= add_round_key;
when key_scheduler_start =>
subblock <= identity;
start_key <= '1';
when key_scheduler_wait =>
subblock <= identity;
when round_start =>
subblock <= identity;
when round_end =>
subblock <= identity;
round_count_up <= '1';
when block_done =>
aes_done <= '1';
when others =>
-- nothing
end case;
end process fsm_output;
-- leda C_1406 off
round_count_reg : process(clk)
begin
if rising_edge(clk) then
round_count <= next_round_count;
end if;
end process round_count_reg;
-- leda C_1406 on
round_count_nsl : process(round_count, round_count_up, round_count_clr)
variable nrc : round_type;
begin
if (round_count_clr = '1') then
next_round_count <= 0;
elsif (round_count_up = '1') then
if (round_count = 11) then
nrc := 0;
else
nrc := round_count + 1;
end if;
next_round_count <= nrc;
else
next_round_count <= round_count;
end if;
end process round_count_nsl;
-- leda C_1406 off
i_reg : process(clk)
begin
if rising_edge(clk) then
i <= next_i;
end if;
end process i_reg;
-- leda C_1406 on
i_nsl : process(i, i_up, i_clr)
begin
if (i_clr = '1') then
next_i <= 0;
elsif (i_up = '1') then
next_i <= to_integer(to_unsigned(i, 4) + 1);
else
next_i <= i;
end if;
end process i_nsl;
current_round <= round_count;
p <= i;
end architecture behavioral_p;
| bsd-3-clause | dc23e850f1b2e12cd6aa5790d2a0246f | 0.45621 | 3.902098 | false | false | false | false |
iocoder/graduation | hardware/vga/decoder.vhd | 1 | 738 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (EN : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (2 downto 0);
O : out STD_LOGIC_VECTOR (7 downto 0));
end decoder;
architecture Dataflow of decoder is
begin
O <= "00000001" when I = "000" AND EN = '1' else
"00000010" when I = "001" AND EN = '1' else
"00000100" when I = "010" AND EN = '1' else
"00001000" when I = "011" AND EN = '1' else
"00010000" when I = "100" AND EN = '1' else
"00100000" when I = "101" AND EN = '1' else
"01000000" when I = "110" AND EN = '1' else
"10000000" when I = "111" AND EN = '1' else
"00000000";
end Dataflow;
| gpl-3.0 | e9e371d023b44ffa8d00b4999079ccd0 | 0.593496 | 2.963855 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDEV2/tb_IDE_control_unit.vhd | 1 | 3,947 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:23:07 12/16/2015
-- Design Name:
-- Module Name: C:/Users/Bailey/Documents/IDE V2/IDEV2/tb_IDE_control_unit.vhd
-- Project Name: IDEV2
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: IDE_control_unit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_IDE_control_unit IS
END tb_IDE_control_unit;
ARCHITECTURE behavior OF tb_IDE_control_unit IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT IDE_control_unit
PORT(
R : IN std_logic;
W : IN std_logic;
Re : OUT std_logic;
CS : IN std_logic;
enables : OUT std_logic_vector(2 downto 0);
data_select : OUT std_logic;
clk : IN std_logic;
reset : IN std_logic;
w_select : OUT std_logic;
wr_prev : OUT std_logic_vector(1 downto 0);
data_enable : OUT std_logic
);
END COMPONENT;
--Inputs
signal R : std_logic := '0';
signal W : std_logic := '0';
signal CS : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal Re : std_logic;
signal enables : std_logic_vector(2 downto 0);
signal data_select : std_logic;
signal w_select : std_logic;
signal wr_prev : std_logic_vector(1 downto 0);
signal data_enable : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: IDE_control_unit PORT MAP (
R => R,
W => W,
Re => Re,
CS => CS,
enables => enables,
data_select => data_select,
clk => clk,
reset => reset,
w_select => w_select,
wr_prev => wr_prev,
data_enable => data_enable
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '1';
wait for clk_period*10;
reset <= '0';
--Format of a read
--State 0
W <= '1';
wait for clk_period*6;
W <= '0';
wait for clk_period*6;
--State 1
W <= '1';
wait for clk_period*6;
W <= '0';
wait for clk_period*6;
--State 2
W <= '1';
wait for clk_period*6;
W <= '0';
wait for clk_period*6;
--State 3
R <= '1';
wait for clk_period*6;
R <= '0';
wait for clk_period*6;
--State 4
R <= '1';
wait for clk_period*6;
R <= '0';
wait for clk_period*6;
--Format of a Write
--State 0
W <= '1';
wait for clk_period*6;
W <= '0';
wait for clk_period*6;
--State 1
W <= '1';
wait for clk_period*6;
W <= '0';
wait for clk_period*6;
--State 2
W <= '1';
wait for clk_period*6;
W <= '0';
wait for clk_period*6;
--State 3
W <= '1';
wait for clk_period*6;
W <= '0';
wait for clk_period*6;
--State 4
W <= '1';
wait for clk_period*6;
W <= '0';
wait for clk_period*6;
wait;
end process;
END;
| unlicense | be959b99103902016de05bf8317ecf20 | 0.554598 | 3.261983 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/proc_common_pkg.vhd | 3 | 18,158 | -------------------------------------------------------------------------------
-- $Id: proc_common_pkg.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end proc_common_pkg;
package body proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
-- ASCII value - 42 TBD
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body proc_common_pkg;
| bsd-3-clause | cbb5273288c338ede7c64e26c548434e | 0.465084 | 4.651127 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_thvadd_v1_00_a/hdl/vhdl/hw_thvadd.vhd | 2 | 7,963 | ------------------------------------------------------------------------------
-- add_sub_core - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: add_sub_core
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Thu Aug 9 10:06:10 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_thvadd is
port
(
Tintrfc2thrd_value : out std_logic_vector(0 to 31);
Tintrfc2thrd_function : out std_logic_vector(0 to 15);
Tintrfc2thrd_goWait : out std_logic;
Tthrd2intrfc_address : out std_logic_vector(0 to 31);
Tthrd2intrfc_value : out std_logic_vector(0 to 31);
Tthrd2intrfc_function : out std_logic_vector(0 to 15);
Tthrd2intrfc_opcode : out std_logic_vector(0 to 5);
Ttimer : out std_logic_vector( 0 to 31);
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
FSL1_M_Write : out std_logic;
FSL1_M_Data : out std_logic_vector(0 to 31);
FSL1_M_Full : in std_logic;
FSL2_M_Write : out std_logic;
FSL2_M_Data : out std_logic_vector(0 to 31);
FSL2_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
end hw_thvadd;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_thvadd is
component user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic ;
full : in std_logic ;
Ttimer : out std_logic_vector( 0 to 31)
);
end component user_logic_hwtul;
signal intrfc2thrd : std_logic_vector(0 to 63);
signal thrd2intrfc : std_logic_vector( 0 to 95);
signal rd : std_logic;
signal wr : std_logic;
signal exist : std_logic;
signal full : std_logic;
signal timer : std_logic_vector( 0 to 31) ;
-- Architecture Section
begin
Tintrfc2thrd_value <= intrfc2thrd(0 to 31) ;
Tintrfc2thrd_function <= intrfc2thrd (32 to 47);
Tintrfc2thrd_goWait <= exist ;
Tthrd2intrfc_address <= thrd2intrfc (32 to 63);
Tthrd2intrfc_value <= thrd2intrfc (0 to 31) ;
Tthrd2intrfc_function <= thrd2intrfc (64 to 79);
Tthrd2intrfc_opcode <= thrd2intrfc (80 to 85);
Ttimer <= timer;
intrfc2thrd <= FSL0_S_Data & FSL1_S_Data;
FSL0_M_Data <= thrd2intrfc(0 to 31);
FSL1_M_Data <= thrd2intrfc(32 to 63);
FSL2_M_Data <= thrd2intrfc(64 to 95);
--=======================================================
full <= FSL0_M_Full or FSL1_M_Full or FSL2_M_Full;
exist <= FSL0_S_Exists and FSL1_S_Exists ;
--=======================================================
FSL0_S_Read <= rd;
FSL1_S_Read <= rd;
FSL0_M_Write <= wr;
FSL1_M_Write <= wr;
FSL2_M_Write <= wr;
USER_LOGIC_HWTUL_I : user_logic_hwtul
port map
(
clock => FSL_Clk,
intrfc2thrd => intrfc2thrd,
thrd2intrfc => thrd2intrfc,
rd => rd,
wr => wr,
exist => exist,
full => full,
Ttimer => timer
);
end architecture implementation;
| bsd-3-clause | cd0b02d4c298fcf35a5b25e9b892832e | 0.472812 | 4.184446 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/xor_f.vhd | 2 | 17,708 | -------------------------------------------------------------------------------
-- $Id: xor_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- xor_f
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: xor_f.vhd
--
-- Description: Xor_out <= xor_reduce(In_bus)
--
-- In other words the C_NUM_BITS bits of vector In_bus are
-- XOR'ed together to form Xor_out.
--
-- The implementation will depend on C_FAMILY. If the FPGA
-- architecture corresponding to C_FAMILY supports the
-- XORCY and MUXCY primitives and the traditional carry chain,
-- then the implementation will be structural and
-- a local XOR gate in the hierarchy will consist, in
-- general, of two LUTs programmed for XOR functionality
-- feeding their unique commonly reachable XORCY (through
-- a MUXCY in the case of the upstream LUT).
--
-- Here are some properties of the overall structural XOR gate:
-- - The maximum number of levels of the local XOR gates will
-- be minimal.
-- - The number of inputs that have the maximum number of
-- levels will also be minimal.
-- - At most one LUT will have partially populated inputs.
--
-- The structural implementation also takes into account
-- the differences between pre-virtex5, LUT4-based FPGAs
-- and post-virtex5-style LUT6-based FPGAs.
--
-- If the structural XOR gate cannot be built, either because
-- C_FAMILY does not support the requisite primitives and
-- carry-chain structure or because C_FAMILY is set (or left
-- defaulted) to "nofamily", then the implementation is
-- inferred by synthesis.
--
-------------------------------------------------------------------------------
-- Structure: Common use module with two locally declared helper units.
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 07/24/06 -- First version
-- ~~~~~~
-- FLO 12/20/07
-- ^^^^^^
-- Eliminated making the min function directly visible from a package because
-- in ncsim this results in two min identifiers being made directly visible.
-- These two are the function and the min (minutes) identifier from the
-- 'pseudo' package, STANDARD.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- The xor_f entity is declared further down.
-- First, a helper entity, recursive_xor, is declared.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity recursive_xor is
generic (
L : positive; -- Length of the input vector
N : positive -- Width of xor gate used in the hierarchy
);
port (
In_bus : in std_logic_vector(0 to L-1);
Xor_out : out std_logic
);
end recursive_xor;
library proc_common_v3_00_a;
library unisim;
use unisim.vcomponents.all;
---(
architecture implementation of recursive_xor is
--
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
--
function greatest_power_of_N_lt_L (N, L: positive) return positive is
variable x : positive := 1;
begin
while x*N < L loop
x := x*N;
end loop;
return x;
end;
--
constant G : positive := greatest_power_of_N_lt_L(N, L);
constant LDG: natural := L/G; -- L divided by G
constant EXTRA_G_NEEDED: boolean := L-(LDG*G) > (N-LDG)*(G/N); -- Another
-- sub XOR with more than G/N inputs, but less than G inputs, is
-- needed if the rest of the inputs beyond (LDG)*G won't fit into
-- the (N-LDG) inputs that are left over and are allocated to
-- each process a sub XOR of size G/N.
constant NG : natural := LDG + bo2na(EXTRA_G_NEEDED); -- Number of sub
-- XOR's of size G.
-- Note: One of these groupings of "size G" in general is adjusted
-- to a smaller size and represents the only sub XOR that may be
-- of size not a power of N.
constant P : positive := L - (NG-1)*G - (N-NG)*(G/N); -- Each of the N
-- sub XORs will have either G or G/N inputs, except one, which
-- will have P inputs, where G/N < P <= G.
constant NIB : positive
:= bo2na(L< N)*L +
bo2na(L>=N)*N; -- Number of ib bits used at this level.
constant DLS : positive := bo2na(N=8)*4 + bo2na(N=11)*6; -- Downstream
-- LUT Size. In general, the XOR at the current level is made up of two
-- carry-chain-adjacent LUTs whose outputs are XOR'ed by the
-- XORCY associated with the downstream LUT. DLS is the size of
-- the downstream LUT. The size of the upstream LUT is N-DLS.
--
function min (a, b: natural) return natural is
begin
if (a>b) then return b; else return a; end if;
end;
--
function xor_reduce (v : std_logic_vector) return std_logic is
variable r : std_logic := '0';
begin
for i in v'range loop
r := r xor v(i);
end loop;
return r;
end;
--
signal ib : std_logic_vector(0 to N-1); -- The Input Bits to the
-- xor at this level.
attribute keep : string;
attribute keep of ib : signal is "true"; -- To inhibit unpredictable
-- (and possibly non-productive) synthesis optimizations.
--
signal lutout0 : std_logic;
--
begin
---(--------------------------------------------------------------------------
-- Sub-divide the XOR problem across the N inputs at the current level.
-- Use recursive instantiation as needed.
------------------------------------------------------------------------------
--
PARTIAL_N_GEN : if NIB < N generate -- Some inputs at current level are unfilled.
ib(0 to L-1) <= In_bus;
end generate;
--
FULL_N_GEN : if NIB = N generate -- All N inputs at current level are filled.
SUBSTRUCTURE_GEN : for i in 0 to N-1 generate
constant START : natural
:= bo2na(i<=NG-1)*i*G
+ bo2na(i> NG-1)*((NG-1)*G + P + (i-NG)*(G/N));
constant LEN : natural
:= bo2na(i<NG-1)*G
+ bo2na(i=NG-1)*P
+ bo2na(i>NG-1)*(G/N);
begin
--
RECUR_GEN : if LEN /= 1 generate -- Recursive instantiation
--
RECURSIVE_XOR_I : entity recursive_xor
generic map (L => LEN, N => N)
port map (
In_bus => In_bus(START to START + LEN - 1),
Xor_out => ib(i)
);
--
end generate;
--
BASE_GEN : if LEN = 1 generate
ib(i) <= In_bus(START);
end generate;
--
end generate;
end generate;
---)
---(------------------------------------------------------------------------
-- Build the XOR gate at the current level.
----------------------------------------------------------------------------
--
NO_LUT_NEEDED_GEN : if NIB = 1 generate
Xor_out <= In_bus(0);
end generate;
--
DOWNSTREAM_LUT_NEEDED_GEN : if NIB /= 1 generate
--
lutout0 <= xor_reduce(ib(0 to min(NIB, DLS)-1));
--
OUTPUT_FROM_GEN : if NIB <= DLS generate
Xor_out <= lutout0;
end generate;
--
end generate;
--
UPSTREAM_LUT_NEEDED_GEN : if NIB > DLS generate
signal lutout1, di, ci, cy : std_logic;
begin
--------------------------------------------------------------------------
-- - When N=8, the pre-virtex5 LUT-MUXCY-XORCY structure is used. The
-- CI and DI inputs are set to '1' and '0', respectively, to
-- allow the xor function realized in the upstream LUT to be
-- sent downstream through the MUXCY.
--
-- - When N=11, a virtex5-type LUT-MUXCY-XORCY structure is assumed.
-- The facts that (1) carry chains can only be initialized on 4-LUT
-- slice boundaries and (2) the DI and S inputs of the MUXCY can be
-- driven by separate LUT5's are taken into consideration.
-- Driving the upstream XOR function through DI means
-- that only a five-bit XOR is implemented in the upstream LUT.
-- On the other hand, since the CI input is not needed,
-- the 11-bit upstream/downstream LUT pair can be packed at
-- any LUT position except the very last (most downstream) in a
-- whole column. If the CI input were used, only one in four LUTs
-- could serve as the upstream LUT. The better packing flexibility
-- is preferred over utilization of all 12, rather than 11, of
-- the available LUT inputs.
--------------------------------------------------------------------------
--
lutout1 <= xor_reduce(ib(DLS to NIB-1)) when N=8 else '0';
di <= xor_reduce(ib(DLS to NIB-1)) when N=11 else '0';
ci <= '1' when N=8 else '-';
--
MUXCY_I : component MUXCY port map (
O => cy,
CI => ci,
DI => di,
S => lutout1
);
--
XORCY_I : component XORCY port map (
O => Xor_out,
CI => cy,
LI => lutout0
);
--
end generate;
---)
end architecture implementation;
---)
library ieee;
use ieee.std_logic_1164.all;
--
entity xor_f is
generic (
C_NUM_BITS : natural;
C_FAMILY : string := "nofamily"
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Xor_out : out std_logic
);
end xor_f;
library proc_common_v3_00_a;
use proc_common_v3_00_a.family_support.all;
-- Makes visible the function 'supported' and related types,
-- including enumeration literals for the unisim primitives (e.g.
-- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.).
library work;
use work.recursive_xor;
--
architecture implementation of xor_f is
--
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
----------------------------------------------------------------------------
-- Here is determined which structural or inferred implementation to use.
----------------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean := (In_bus'length > 0) and
supported(C_FAMILY,
(u_MUXCY, u_XORCY)
);
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
--
function xor_reduce (v : std_logic_vector) return std_logic is
variable r : std_logic := '0';
begin
for i in v'range loop
r := r xor v(i);
end loop;
return r;
end;
--
begin
---(------------------------------------------------------------------------
-- Inferred implementation.
----------------------------------------------------------------------------
INFERRED_GEN : if USE_INFERRED generate
begin
Xor_out <= xor_reduce(In_bus);
end generate;
---)
---(------------------------------------------------------------------------
-- Structural implementation A.
----------------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
constant N : positive := bo2na(NLS=4)*8 + bo2na(NLS=6)*11;
begin
I_RECURSIVE_XOR_A: entity recursive_xor
generic map (
L => C_NUM_BITS,
N => N
)
port map (
In_bus => In_bus,
Xor_out => Xor_out
);
end generate;
---)
end implementation;
| bsd-3-clause | fb4b4e42719db61e209e148f5709a025 | 0.467246 | 4.737293 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/cond_init_2.vhd | 2 | 15,313 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- cond_init_2.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_cond_t * cond = (hthread_cond_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_cond_init( cond, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push cond
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_cond_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = cond->num
when STATE_4 =>
-- Load the value of cond->num
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | b50d28aefc07c8c4bd7212e48dc97150 | 0.538235 | 3.838807 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_quicksort.vhd | 2 | 34,764 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Quicksort
-- Thread implements the quicksort algorithm
-- Passed in argument is a pointer to following struct
-- struct sortData {
-- int * startData; //pointer to start of array
-- int * endData; //pointer to end of array
-- int cacheOption // 1 operate on data where it is, 0 copy into HWTI first
-- There is not return argument, the HWT just sorts the data.
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
READ_SORTDATA_1,
READ_SORTDATA_2,
READ_SORTDATA_3,
READ_SORTDATA_4,
READ_SORTDATA_5,
READ_SORTDATA_6,
READ_SORTDATA_7,
READ_SORTDATA_8,
COPY_DATA_1,
COPY_DATA_2,
COPY_DATA_3,
COPY_DATA_4,
COPY_DATA_5,
COPY_DATA_6,
COPY_DATA_7,
RECOPY_DATA_1,
RECOPY_DATA_2,
RECOPY_DATA_3,
RECOPY_DATA_4,
FREE_1,
FREE_2,
CALL_QSORT_1,
CALL_QSORT_2,
CALL_QSORT_3,
READ_ARRAY_1,
READ_ARRAY_2,
READ_ARRAY_3,
READ_ARRAY_4,
READ_ARRAY_5,
READ_ARRAY_6,
EXIT_THREAD_1,
EXIT_THREAD_2,
QUICKSORT_1,
QUICKSORT_2,
QUICKSORT_3,
QUICKSORT_4,
QUICKSORT_5,
QUICKSORT_6,
QUICKSORT_7,
QUICKSORT_8,
QUICKSORT_9,
QUICKSORT_A,
QUICKSORT_B,
QUICKSORT_DO,
QUICKSORT_WHILE_LEFT_0,
QUICKSORT_WHILE_LEFT_1,
QUICKSORT_WHILE_LEFT_2,
QUICKSORT_WHILE_LEFT_3,
QUICKSORT_BREAK,
QUICKSORT_WHILE_RIGHT_1,
QUICKSORT_WHILE_RIGHT_2,
QUICKSORT_WHILE_RIGHT_3,
QUICKSORT_SWAP_1,
QUICKSORT_SWAP_2,
QUICKSORT_SWAP_3,
QUICKSORT_SWAP_4,
QUICKSORT_SWAP_5,
QUICKSORT_WHILE,
QUICKSORT_CALL_QS_0,
QUICKSORT_CALL_QS_1,
QUICKSORT_CALL_QS_2,
QUICKSORT_CALL_QS_3,
QUICKSORT_CALL_QS_4,
QUICKSORT_CALL_QS_5,
QUICKSORT_CALL_QS_6,
QUICKSORT_CALL_QS_7,
QUICKSORT_CALL_QS_8,
QUICKSORT_CALL_QS_9,
QUICKSORT_CALL_QS_A,
QUICKSORT_RETURN,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_READ_SORTDATA_5 : std_logic_vector(0 to 15) := x"0007";
constant U_COPY_DATA_3 : std_logic_vector(0 to 15) := x"0053";
constant U_READ_ARRAY_1 : std_logic_vector(0 to 15) := x"0031";
constant U_EXIT_THREAD_1 : std_logic_vector(0 to 15) := x"0021";
constant U_FREE_1 : std_logic_vector(0 to 15) := x"0041";
constant U_QUICKSORT_1 : std_logic_vector(0 to 15) := x"0101";
constant U_QUICKSORT_CALL_QS_6 : std_logic_vector(0 to 15) := x"0171";
constant U_QUICKSORT_RETURN : std_logic_vector(0 to 15) := x"0181";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
-- constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
-- constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
-- constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
-- constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
-- constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
-- constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next : state_machine := FUNCTION_RESET;
signal startPtr, startPtr_next : std_logic_vector(0 to 31);
signal endPtr, endPtr_next : std_logic_vector(0 to 31);
signal leftPtr, leftPtr_next : std_logic_vector(0 to 31);
signal rightPtr, rightPtr_next : std_logic_vector(0 to 31);
signal left, left_next : std_logic_vector(0 to 31);
signal right, right_next : std_logic_vector(0 to 31);
signal pivot, pivot_next : std_logic_vector(0 to 31);
signal cache, cache_next : std_logic;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
startPtr <= startPtr_next;
endPtr <= endPtr_next;
leftPtr <= leftPtr_next;
rightPtr <= rightPtr_next;
left <= left_next;
right <= right_next;
pivot <= pivot_next;
cache <= cache_next;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_READ_SORTDATA_5 =>
current_state <= READ_SORTDATA_5;
when U_COPY_DATA_3 =>
current_state <= COPY_DATA_3;
when U_READ_ARRAY_1 =>
current_state <= READ_ARRAY_1;
when U_FREE_1 =>
current_state <= FREE_1;
when U_EXIT_THREAD_1 =>
current_state <= EXIT_THREAD_1;
when U_QUICKSORT_1 =>
current_state <= QUICKSORT_1;
when U_QUICKSORT_CALL_QS_6 =>
current_state <= QUICKSORT_CALL_QS_6;
when U_QUICKSORT_RETURN =>
current_state <= QUICKSORT_RETURN;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (current_state) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
next_state <= current_state;
return_state_next <= return_state;
startPtr_next <= startPtr;
endPtr_next <= endPtr;
leftPtr_next <= leftPtr;
rightPtr_next <= rightPtr;
left_next <= left;
right_next <= right;
pivot_next <= pivot;
cache_next <= cache;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
startPtr_next <= Z32;
endPtr_next <= Z32;
leftPtr_next <= Z32;
rightPtr_next <= Z32;
left_next <= Z32;
right_next <= Z32;
pivot_next <= Z32;
cache_next <= '1';
when FUNCTION_START => -- 0002
-- read the passed in argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_address <= Z32;
return_state_next <= READ_SORTDATA_1;
next_state <= WAIT_STATE;
when READ_SORTDATA_1 => -- 0003
-- The passed in argument is address of struct sortdata
-- For the time being, store value in startPtr
startPtr_next <= toUser_value;
-- Read the endPtr address
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value + 4;
return_state_next <= READ_SORTDATA_2;
next_state <= WAIT_STATE;
when READ_SORTDATA_2 => -- 0004
endPtr_next <= toUser_value;
-- Read the cache option
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= startPtr + 8;
return_state_next <= READ_SORTDATA_3;
next_state <= WAIT_STATE;
when READ_SORTDATA_3 => -- 0005
cache_next <= toUser_value(31);
-- Now read the address of startPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= startPtr;
return_state_next <= READ_SORTDATA_4;
next_state <= WAIT_STATE;
when READ_SORTDATA_4 => -- 0006
startPtr_next <= toUser_value;
leftPtr_next <= toUser_value;
rightPtr_next <= endPtr;
-- Declare four local variables to hold start, end, left, right pointers
thrd2intrfc_opcode <= OPCODE_DECLARE;
thrd2intrfc_value <= x"00000004";
if ( cache = '1' ) then
-- copy the global data locally
return_state_next <= COPY_DATA_1;
next_state <= WAIT_STATE;
else
-- work on data where it is
return_state_next <= READ_SORTDATA_5;
next_state <= WAIT_STATE;
end if;
when READ_SORTDATA_5 => -- 0007
-- Save the start pointer
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= startPtr;
return_state_next <= READ_SORTDATA_6;
next_state <= WAIT_STATE;
when READ_SORTDATA_6 => -- 0008
-- Save the end pointer
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= x"00000001";
thrd2intrfc_value <= endPtr;
return_state_next <= READ_SORTDATA_7;
next_state <= WAIT_STATE;
when READ_SORTDATA_7 => -- 0009
-- Save the left pointer
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= x"00000002";
thrd2intrfc_value <= leftPtr;
return_state_next <= READ_SORTDATA_8;
next_state <= WAIT_STATE;
when READ_SORTDATA_8 => -- 000A
-- Save the right pointer
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= x"00000003";
thrd2intrfc_value <= rightPtr;
-- Sort the data!
return_state_next <= CALL_QSORT_1;
next_state <= WAIT_STATE;
when CALL_QSORT_1 => -- 0011
-- Push the second argument, endPtr;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= rightPtr;
return_state_next <= CALL_QSORT_2;
next_state <= WAIT_STATE;
when CALL_QSORT_2 => -- 0012
-- Push the first argument, startPtr;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= leftPtr;
return_state_next <= CALL_QSORT_3;
next_state <= WAIT_STATE;
when CALL_QSORT_3 => -- 0013
-- Call quicksort
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= U_QUICKSORT_1;
thrd2intrfc_value <= Z32(0 to 15) & U_READ_ARRAY_1;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when READ_ARRAY_1 => -- 0031
-- Read the startPtr from memory
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= Z32;
return_state_next <= READ_ARRAY_2;
next_state <= WAIT_STATE;
when READ_ARRAY_2 => -- 0032
startPtr_next <= toUser_value;
-- Read the endPtr from memory
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= x"00000001";
return_state_next <= READ_ARRAY_3;
next_state <= WAIT_STATE;
when READ_ARRAY_3 => -- 0033
endPtr_next <= toUser_value;
-- Read the leftPtr from memory
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= x"00000002";
return_state_next <= READ_ARRAY_4;
next_state <= WAIT_STATE;
when READ_ARRAY_4 => -- 0034
leftPtr_next <= toUser_value;
-- Read the rightPtr from memory
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= x"00000003";
return_state_next <= READ_ARRAY_5;
next_state <= WAIT_STATE;
when READ_ARRAY_5 => -- 0035
rightPtr_next <= toUser_value;
next_state <= READ_ARRAY_6;
when READ_ARRAY_6 => -- 0037
if ( cache = '1' ) then
-- Recopy data
next_state <= RECOPY_DATA_1;
else
next_state <= EXIT_THREAD_1;
end if;
when RECOPY_DATA_1 => -- 0061
-- Push the number of bytes to allocate to stack
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= (rightPtr - leftPtr + 4);
return_state_next <= RECOPY_DATA_2;
next_state <= WAIT_STATE;
when RECOPY_DATA_2 => -- 0062
-- Push the address to start cpying from
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= leftPtr;
return_state_next <= RECOPY_DATA_3;
next_state <= WAIT_STATE;
when RECOPY_DATA_3 => -- 0063
-- Push the address to copy to
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= startPtr;
return_state_next <= RECOPY_DATA_4;
next_state <= WAIT_STATE;
when RECOPY_DATA_4 => -- 0064
-- Call mempy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_MEMCPY;
thrd2intrfc_value <= Z32(0 to 15) & U_FREE_1;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when FREE_1 =>
-- Push the address to free
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= leftPtr;
return_state_next <= FREE_2;
next_state <= WAIT_STATE;
when FREE_2 =>
-- Call free
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_FREE;
thrd2intrfc_value <= Z32(0 to 15) & U_EXIT_THREAD_1;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when COPY_DATA_1 => -- 0051
-- Push the number of bytes to allocate to stack
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= (endPtr - startPtr + 4);
return_state_next <= COPY_DATA_2;
next_state <= WAIT_STATE;
when COPY_DATA_2 => -- 0052
-- Call the malloc function
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_MALLOC;
thrd2intrfc_value <= Z32(0 to 15) & U_COPY_DATA_3;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when COPY_DATA_3 => -- 0053
-- Record the starting address of allocated data
leftPtr_next <= toUser_value;
-- Calculate the ending address of allocated dta
rightPtr_next <= toUser_value + (endPtr - startPtr);
-- Copy the data
next_state <= COPY_DATA_4;
when COPY_DATA_4 => -- 0054
-- Push the number of bytes to copy
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= (endPtr - startPtr + 4);
return_state_next <= COPY_DATA_5;
next_state <= WAIT_STATE;
when COPY_DATA_5 => -- 0055
-- Push the address to start copying from
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= startPtr;
return_state_next <= COPY_DATA_6;
next_state <= WAIT_STATE;
when COPY_DATA_6 => -- 0056
-- Push the address to copy data to
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= leftPtr;
return_state_next <= COPY_DATA_7;
next_state <= WAIT_STATE;
when COPY_DATA_7 => -- 0057
-- Call memcopy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_MEMCPY;
thrd2intrfc_value <= Z32(0 to 15) & U_READ_SORTDATA_5;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when EXIT_THREAD_1 => -- 0021
-- Push a null argument onto stack, as required by hthread_exit;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
return_state_next <= EXIT_THREAD_2;
next_state <= WAIT_STATE;
when EXIT_THREAD_2 => -- 0022
-- Call exit thread
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when ERROR_STATE => -- 7999
next_state <= ERROR_STATE;
-----------------------------------------------------------------------
-- Quicksort function
-- argument 1 - start pointer
-- argument 2 - end pointer
-----------------------------------------------------------------------
when QUICKSORT_1 => -- 0101
-- Read the first argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
return_state_next <= QUICKSORT_2;
next_state <= WAIT_STATE;
when QUICKSORT_2 => -- 0102
startPtr_next <= toUser_value;
-- Read the second argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= x"00000001";
return_state_next <= QUICKSORT_3;
next_state <= WAIT_STATE;
when QUICKSORT_3 => -- 0103
endPtr_next <= toUser_value;
next_state <= QUICKSORT_4;
when QUICKSORT_4 => -- 0104
-- Declare 5 variables
thrd2intrfc_opcode <= OPCODE_DECLARE;
thrd2intrfc_value <= x"00000002";
return_state_next <= QUICKSORT_5;
next_state <= WAIT_STATE;
when QUICKSORT_5 => -- 0105
-- Copy the start and end pointers
leftPtr_next <= startPtr;
rightPtr_next <= endPtr;
next_state <= QUICKSORT_6;
when QUICKSORT_6 => -- 0106
-- check to see if left and right pointers are equal
if ( leftPtr >= rightPtr ) then
-- Nothing to sort, return
next_state <= QUICKSORT_RETURN;
else
next_state <= QUICKSORT_7;
end if;
when QUICKSORT_7 => -- 0107
-- Read the value of the leftPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= leftPtr;
return_state_next <= QUICKSORT_8;
next_state <= WAIT_STATE;
when QUICKSORT_8 => -- 0108
left_next <= toUser_value;
-- Read the value of the rightPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= rightPtr;
return_state_next <= QUICKSORT_9;
next_state <= WAIT_STATE;
when QUICKSORT_9 => -- 0109
right_next <= toUser_value;
next_state <= QUICKSORT_A;
when QUICKSORT_A => -- 010A
-- determine the pivot value by first taking sum of left and right
pivot_next <= left + right;
next_state <= QUICKSORT_B;
when QUICKSORT_B => -- 010B
-- next divide the sum of left and right by two (or shift)
pivot_next <= '0' & pivot(0 to 30);
next_state <= QUICKSORT_DO;
when QUICKSORT_DO => -- 0111
-- This is a placeholder for my own sanity
next_state <= QUICKSORT_WHILE_LEFT_0;
when QUICKSORT_WHILE_LEFT_0 => -- 0121
-- check to see if leftPtr moved past rightPtr
if ( leftPtr < rightPtr ) then
next_state <= QUICKSORT_WHILE_LEFT_1;
else
leftPtr_next <= rightPtr;
next_state <= QUICKSORT_BREAK;
end if;
when QUICKSORT_WHILE_LEFT_1 => -- 0121
-- check to see if left < pivot
if ( left <= pivot ) then
-- left does not have to be swapped, increment leftPtr
leftPtr_next <= leftPtr + 4;
next_state <= QUICKSORT_WHILE_LEFT_2;
else
-- left needs to be swapped, end the while loop
next_state <= QUICKSORT_BREAK;
end if;
when QUICKSORT_WHILE_LEFT_2 => -- 0122
-- read value of leftPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= leftPtr;
return_state_next <= QUICKSORT_WHILE_LEFT_3;
next_state <= WAIT_STATE;
when QUICKSORT_WHILE_LEFT_3 => -- 0123
left_next <= toUser_value;
next_state <= QUICKSORT_WHILE_LEFT_0;
when QUICKSORT_BREAK => -- 0131
-- Check that we did not move past right ptr
if ( leftPtr >= rightPtr ) then
-- we are done swapping
next_state <= QUICKSORT_CALL_QS_0;
else
next_state <= QUICKSORT_WHILE_RIGHT_1;
end if;
when QUICKSORT_WHILE_RIGHT_1 => -- 0141
-- check to see if right < pivot
if ( right > pivot ) then
-- right does not have to be swapped, decrement rightPtr
rightPtr_next <= rightPtr - 4;
next_state <= QUICKSORT_WHILE_RIGHT_2;
else
-- right needs to be swapped, end the while loop
next_state <= QUICKSORT_SWAP_1;
end if;
when QUICKSORT_WHILE_RIGHT_2 => -- 0142
-- read value of rightPtr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= rightPtr;
return_state_next <= QUICKSORT_WHILE_RIGHT_3;
next_state <= WAIT_STATE;
when QUICKSORT_WHILE_RIGHT_3 => -- 0143
right_next <= toUser_value;
next_state <= QUICKSORT_BREAK;
when QUICKSORT_SWAP_1 => -- 0151
-- write the value of rightPtr with left
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= rightPtr;
thrd2intrfc_value <= left;
return_state_next <= QUICKSORT_SWAP_2;
next_state <= WAIT_STATE;
when QUICKSORT_SWAP_2 => -- 0152
-- write the value of leftPtr with right
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= leftPtr;
thrd2intrfc_value <= right;
return_state_next <= QUICKSORT_SWAP_3;
next_state <= WAIT_STATE;
when QUICKSORT_SWAP_3 => -- 0153
-- increment/decrement pointers
leftPtr_next <= leftPtr + 4;
rightPtr_next <= rightPtr - 4;
next_state <= QUICKSORT_SWAP_4;
when QUICKSORT_SWAP_4 => -- 0154
-- read new value of left
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= leftPtr;
return_state_next <= QUICKSORT_SWAP_5;
next_state <= WAIT_STATE;
when QUICKSORT_SWAP_5 => -- 0155
left_next <= toUser_value;
-- read new value of right
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= rightPtr;
return_state_next <= QUICKSORT_WHILE;
next_state <= WAIT_STATE;
when QUICKSORT_WHILE => -- 0161
right_next <= toUser_value;
-- check to make sure leftPtr < rightPtr
if ( leftPtr < rightPtr ) then
next_state <= QUICKSORT_DO;
else
next_state <= QUICKSORT_CALL_QS_0;
end if;
when QUICKSORT_CALL_QS_0 => -- 0170
-- Check to see if leftPtr == rightPtr
if ( leftPtr = rightPtr ) then
-- Check to see if right > pivot
if ( right >= pivot ) then
leftPtr_next <= rightPtr - 4;
else
rightPtr_next <= rightPtr + 4;
end if;
else
if ( right > pivot ) then
leftPtr_next <= rightPtr - 4;
else
leftPtr_next <= rightPtr;
rightPtr_next <= leftPtr;
end if;
end if;
next_state <= QUICKSORT_CALL_QS_1;
when QUICKSORT_CALL_QS_1 => -- 0171
-- Before calling quicksort need to save rightPtr and endPtr
-- Save the rightPtr
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= x"00000000";
thrd2intrfc_value <= rightPtr;
return_state_next <= QUICKSORT_CALL_QS_2;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_2 => -- 0172
-- Save the endPtr
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= x"00000001";
thrd2intrfc_value <= endPtr;
return_state_next <= QUICKSORT_CALL_QS_3;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_3 => -- 0173
-- Push the leftPtr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= leftPtr;
return_state_next <= QUICKSORT_CALL_QS_4;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_4 => -- 0174
-- Push the startPtr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= startPtr;
return_state_next <= QUICKSORT_CALL_QS_5;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_5 => -- 0175
-- Call quicksort
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= U_QUICKSORT_1;
thrd2intrfc_value <= Z32(0 to 15) & U_QUICKSORT_CALL_QS_6;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_6 => -- 0176
-- read the value of endPtr
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= x"00000001";
return_state_next <= QUICKSORT_CALL_QS_7;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_7 => -- 0177
endPtr_next <= toUser_value;
-- read the value of rightPtr
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= x"00000000";
return_state_next <= QUICKSORT_CALL_QS_8;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_8 => -- 0178
rightPtr_next <= toUser_value;
-- Push the rightPtr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= endPtr;
return_state_next <= QUICKSORT_CALL_QS_9;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_9 => -- 0179
-- push the endPtr
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= rightPtr;
return_state_next <= QUICKSORT_CALL_QS_A;
next_state <= WAIT_STATE;
when QUICKSORT_CALL_QS_A => -- 017A
-- Call quicksort
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= U_QUICKSORT_1;
thrd2intrfc_value <= Z32(0 to 15) & U_QUICKSORT_RETURN;
return_state_next <= WAIT_STATE;
next_state <= WAIT_STATE;
when QUICKSORT_RETURN => -- 0181
-- Return
thrd2intrfc_opcode <= OPCODE_RETURN;
thrd2intrfc_value <= Z32;
return_state_next <= ERROR_STATE;
next_state <= WAIT_STATE;
when WAIT_STATE =>
case toUser_goWait is
when '1' => --Here because HWTUL chose to be here for one clock cycle
next_state <= return_state;
when OTHERS => --ie '0', Here because HWTI is telling us to wait
next_state <= return_state;
end case;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | d60e960287f4d144843cbe0c8902b4b8 | 0.535928 | 4.171847 | false | false | false | false |
michaelmiehling/A25_VME | 16z126-01_src/Source/z126_01_wb2pasmi.vhd | 1 | 25,536 | ---------------------------------------------------------------
-- Title : Wishbone to PASMI
-- Project : 16z126-01
---------------------------------------------------------------
-- File : z126_01_wb2pasmi.vhd
-- Author : Andreas Geissler
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
-- wb2pasmi is a Wishbone to Parallel Active Serial Flash IF
---------------------------------------------------------------
-- Hierarchy:
-- z126_01_top
-- z126_01_wb2pasmi_i0
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.4 $
--
-- $Log: z126_01_wb2pasmi.vhd,v $
-- Revision 1.4 2014/11/24 16:44:22 AGeissler
-- R1: Clearness
-- M1.1: Changed spacing
-- M1.2: Changed comment
--
-- Revision 1.3 2014/04/02 09:28:04 AGeissler
-- R: Wrong data when reading with byte or word access
-- M: Changed conditions for read fsm b2lw_state
--
-- Revision 1.2 2014/03/05 11:19:43 AGeissler
-- R: Missing reset for signal
-- M: Added reset
--
-- Revision 1.1 2014/03/03 17:49:55 AGeissler
-- Initial Revision
--
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.z126_01_pkg.ALL;
ENTITY z126_01_wb2pasmi IS
GENERIC (
FLASH_TYPE : flash_type := NONE
);
PORT (
clk : IN std_logic; -- flash clk 40 MHz
rst : IN std_logic; -- global async high active reset
-- PASMI interface
pasmi_addr : OUT std_logic_vector(23 DOWNTO 0);
pasmi_bulk_erase : OUT std_logic;
pasmi_busy : IN std_logic;
pasmi_data_valid : IN std_logic;
pasmi_datain : IN std_logic_vector(7 DOWNTO 0); -- data from altera pasmi interface
pasmi_dataout : OUT std_logic_vector(7 DOWNTO 0); -- data to altera pasmi
pasmi_epcs_id : IN std_logic_vector(7 DOWNTO 0);
pasmi_rdid : IN std_logic_vector(7 DOWNTO 0);
pasmi_fast_read : OUT std_logic;
pasmi_illegal_erase : IN std_logic;
pasmi_illegal_write : IN std_logic;
pasmi_rden : OUT std_logic;
pasmi_read_sid : OUT std_logic;
pasmi_read_rdid : OUT std_logic;
pasmi_read_status : OUT std_logic;
pasmi_sector_erase : OUT std_logic;
pasmi_sector_protect : OUT std_logic;
pasmi_shift_bytes : OUT std_logic;
pasmi_status_out : IN std_logic_vector(7 DOWNTO 0);
pasmi_wren : OUT std_logic;
pasmi_write : OUT std_logic;
-- wishbone signals slave interface 0 (direct addressing)
wbs_stb : IN std_logic; -- request
wbs_ack : OUT std_logic; -- acknoledge
wbs_we : IN std_logic; -- write=1 read=0
wbs_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
wbs_cyc : IN std_logic; -- chip select
wbs_dat_o : OUT std_logic_vector(31 DOWNTO 0); -- data out
wbs_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
wbs_adr : IN std_logic_vector(31 DOWNTO 0); -- address
wbs_tga : IN std_logic_vector(5 DOWNTO 0); -- address extension for address generation 0=dir/1=indir
wbs_err : OUT std_logic; -- error
-- control interface
ctrl_read_sid : IN std_logic;
ctrl_sector_protect : IN std_logic;
ctrl_write : IN std_logic;
ctrl_read_status : IN std_logic;
ctrl_sector_erase : IN std_logic;
ctrl_bulk_erase : IN std_logic;
ctrl_busy : OUT std_logic
);
END z126_01_wb2pasmi;
ARCHITECTURE z126_01_wb2pasmi_arch OF z126_01_wb2pasmi IS
TYPE sel_states IS (IDLE,SEL_0,SEL_1,SEL_2,SEL_3, END_ACCESS);
SIGNAL b2lw_state : sel_states;
SIGNAL lw2b_state : sel_states;
SIGNAL pasmi_busy_q : std_logic;
SIGNAL pasmi_busy_qq : std_logic;
SIGNAL pasmi_data_write_fin : std_logic;
SIGNAL pasmi_data_read_fin : std_logic;
-- internal pasmi signals
SIGNAL pasmi_rden_fsm_int : std_logic;
SIGNAL pasmi_wren_fsm_int : std_logic;
SIGNAL pasmi_shift_bytes_fsm_int : std_logic;
SIGNAL pasmi_fast_read_fsm_int : std_logic;
SIGNAL pasmi_rden_int : std_logic;
SIGNAL pasmi_wren_int : std_logic;
SIGNAL pasmi_shift_bytes_int : std_logic;
SIGNAL pasmi_bulk_erase_int : std_logic;
SIGNAL pasmi_fast_read_int : std_logic;
SIGNAL pasmi_read_rdid_int : std_logic;
SIGNAL pasmi_read_status_int : std_logic;
SIGNAL pasmi_sector_erase_int : std_logic;
SIGNAL pasmi_write_int : std_logic;
SIGNAL pasmi_sector_protect_int : std_logic;
SIGNAL id_oe : std_logic; -- select wishbone data out to serial flash id from altera component
SIGNAL status_oe : std_logic; -- select wishbone data out to status from altera component
SIGNAL wbs_ack_int : std_logic;
SIGNAL dat_32_reg : std_logic_vector(31 DOWNTO 0); -- internal register for shifting read data from pasmi interface
SIGNAL dat_8_reg : std_logic_vector(7 DOWNTO 0); -- internal register for writing data to pasmi interface
SIGNAL pasmi_datain_swapped_int : std_logic_vector(7 DOWNTO 0); -- swapped pasmi data in (MSB <-> LSB)
SIGNAL pasmi_dataout_swapped_int : std_logic_vector(7 DOWNTO 0); -- swapped pasmi data out (MSB <-> LSB)
BEGIN
ctrl_busy <= pasmi_busy_q;
-- wishbone signals
wbs_ack <= wbs_ack_int;
wbs_err <= '0';
-- if flash type M25P32 or M25P64 is used the driver expect the sid instead of the rdid
-- this means to be backwards compatible the rdid is subtracted by 1
-- M25P32 : sid = 15; rdid = 16
-- M25P64 : sid = 16; rdid = 17
-- M25P128: rdid = 18 (there is no sid for the M25P128)
z126_01_wb2pasmi_m25p32_gen: IF FLASH_TYPE = M25P32 GENERATE
wbs_dat_o <= x"0000_00" & std_logic_vector((unsigned (pasmi_rdid)) - 1) WHEN id_oe = '1' ELSE
x"0000_00" & pasmi_status_out WHEN status_oe = '1' ELSE
dat_32_reg;
END GENERATE;
z126_01_wb2pasmi_m25p64_gen: IF FLASH_TYPE = M25P64 GENERATE
wbs_dat_o <= x"0000_00" & std_logic_vector((unsigned (pasmi_rdid)) - 1) WHEN id_oe = '1' ELSE
x"0000_00" & pasmi_status_out WHEN status_oe = '1' ELSE
dat_32_reg;
END GENERATE;
z126_01_wb2pasmi_m25p128_gen: IF FLASH_TYPE = M25P128 GENERATE
wbs_dat_o <= x"0000_00" & pasmi_rdid WHEN id_oe = '1' ELSE
x"0000_00" & pasmi_status_out WHEN status_oe = '1' ELSE
dat_32_reg;
END GENERATE;
-- pasmi signals
pasmi_read_sid <= '0'; -- read sid is not used any longer (rdid is used instead)
pasmi_read_rdid <= pasmi_read_rdid_int;
pasmi_fast_read <= pasmi_fast_read_fsm_int;
pasmi_write <= pasmi_write_int;
pasmi_read_status <= pasmi_read_status_int;
pasmi_sector_erase <= pasmi_sector_erase_int;
pasmi_bulk_erase <= pasmi_bulk_erase_int;
pasmi_rden <= pasmi_rden_fsm_int;
pasmi_dataout <= pasmi_dataout_swapped_int;
pasmi_wren <= '1' WHEN pasmi_wren_fsm_int = '1' OR
pasmi_write_int = '1' OR
pasmi_sector_erase_int = '1' OR
pasmi_bulk_erase_int = '1' ELSE
'0';
pasmi_shift_bytes <= pasmi_shift_bytes_fsm_int;
pasmi_sector_protect <= pasmi_sector_protect_int WHEN pasmi_wren_fsm_int = '1' ELSE '0';
pasmi_addr <= wbs_adr(23 DOWNTO 0) WHEN wbs_we = '1' ELSE --write access depends on adr_register
wbs_adr(23 DOWNTO 2) & "00" WHEN wbs_sel(0) = '1' ELSE --read access depends on byte-sel
wbs_adr(23 DOWNTO 2) & "01" WHEN wbs_sel(1) = '1' ELSE
wbs_adr(23 DOWNTO 2) & "10" WHEN wbs_sel(2) = '1' ELSE
wbs_adr(23 DOWNTO 2) & "11" ;
-- bit-swapping of data lines
bit_swapping: FOR i IN 0 TO 7 GENERATE
pasmi_dataout_swapped_int(i) <= dat_8_reg(7-i) WHEN pasmi_sector_protect_int = '0' ELSE
dat_8_reg(i);
pasmi_datain_swapped_int(i) <= pasmi_datain(7-i);
END GENERATE;
------------------------------
-- Byte to long word (READ) --
------------------------------
z126_01_pasmi_read_access_fsm : PROCESS (b2lw_state, rst, clk)
BEGIN
IF b2lw_state = END_ACCESS THEN
pasmi_data_read_fin <= '1';
ELSE
pasmi_data_read_fin <= '0';
END IF;
IF rst = '1' THEN
b2lw_state <= IDLE;
pasmi_rden_fsm_int <= '0';
pasmi_fast_read_fsm_int <= '0';
dat_32_reg <= (OTHERS=>'0');
ELSIF falling_edge(clk) THEN
CASE b2lw_state IS
WHEN IDLE =>
dat_32_reg <= dat_32_reg;
IF pasmi_fast_read_int = '1' THEN
pasmi_rden_fsm_int <= '1';
pasmi_fast_read_fsm_int <= '1';
IF (wbs_sel(0) = '1') THEN
b2lw_state <= SEL_0;
ELSIF(wbs_sel(1) = '1') THEN
b2lw_state <= SEL_1;
ELSIF(wbs_sel(2) = '1') THEN
b2lw_state <= SEL_2;
ELSE
b2lw_state <= SEL_3;
END IF;
ELSE
pasmi_rden_fsm_int <= '0';
b2lw_state <= IDLE;
END IF;
WHEN SEL_0 =>
dat_32_reg(7 DOWNTO 0) <= pasmi_datain_swapped_int;
pasmi_fast_read_fsm_int <= '0';
IF wbs_sel(1) = '0' AND pasmi_data_valid = '1' THEN
b2lw_state <= END_ACCESS;
pasmi_rden_fsm_int <= '0';
ELSIF pasmi_data_valid = '1' THEN
b2lw_state <= SEL_1;
pasmi_rden_fsm_int <= '1';
ELSE
pasmi_rden_fsm_int <= '1';
END IF;
WHEN SEL_1 =>
dat_32_reg(15 DOWNTO 8) <= pasmi_datain_swapped_int;
pasmi_fast_read_fsm_int <= '0';
IF wbs_sel(2) = '0' AND pasmi_data_valid = '1' THEN
b2lw_state <= END_ACCESS;
pasmi_rden_fsm_int <= '0';
ELSIF pasmi_data_valid = '1' THEN
b2lw_state <= SEL_2;
pasmi_rden_fsm_int <= '1';
ELSE
pasmi_rden_fsm_int <= '1';
END IF;
WHEN SEL_2 =>
dat_32_reg(23 DOWNTO 16) <= pasmi_datain_swapped_int;
pasmi_fast_read_fsm_int <= '0';
IF wbs_sel(3) = '0' AND pasmi_data_valid = '1' THEN
b2lw_state <= END_ACCESS;
pasmi_rden_fsm_int <= '0';
ELSIF pasmi_data_valid = '1' THEN
b2lw_state <= SEL_3;
pasmi_rden_fsm_int <= '1';
ELSE
pasmi_rden_fsm_int <= '1';
END IF;
WHEN SEL_3 =>
dat_32_reg(31 DOWNTO 24) <= pasmi_datain_swapped_int;
pasmi_fast_read_fsm_int <= '0';
pasmi_rden_fsm_int <= '0';
IF pasmi_data_valid = '1' THEN
b2lw_state <= END_ACCESS;
END IF;
WHEN END_ACCESS =>
dat_32_reg <= dat_32_reg;
pasmi_rden_fsm_int <= '0';
pasmi_fast_read_fsm_int <= '0';
b2lw_state <= IDLE;
-- coverage off
WHEN OTHERS =>
b2lw_state <= IDLE;
dat_32_reg <= dat_32_reg;
pasmi_rden_fsm_int <= '0';
pasmi_fast_read_fsm_int <= '0';
ASSERT FALSE REPORT "Undeocded State" SEVERITY WARNING;
-- coverage on
END CASE;
END IF;
END PROCESS z126_01_pasmi_read_access_fsm;
-------------------------------
-- Long word to Byte (WRITE) --
-------------------------------
z126_01_pasmi_write_access_fsm : PROCESS (lw2b_state, clk, rst)
BEGIN
IF lw2b_state = END_ACCESS THEN
pasmi_data_write_fin <= '1';
ELSE
pasmi_data_write_fin <= '0';
END IF;
IF rst = '1' THEN
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
lw2b_state <= IDLE;
dat_8_reg <= (OTHERS=>'0');
ELSIF falling_edge(clk) THEN
CASE lw2b_state IS
WHEN IDLE =>
IF pasmi_wren_int = '1' AND pasmi_shift_bytes_int = '1' THEN
pasmi_wren_fsm_int <= '1';
pasmi_shift_bytes_fsm_int <= pasmi_shift_bytes_int;
IF(wbs_sel(0) = '1') THEN
lw2b_state <= SEL_0;
dat_8_reg <= wbs_dat_i(7 DOWNTO 0);
ELSIF(wbs_sel(1) = '1') THEN
lw2b_state <= SEL_1;
dat_8_reg <= wbs_dat_i(15 DOWNTO 8);
ELSIF(wbs_sel(2) = '1') THEN
lw2b_state <= SEL_2;
dat_8_reg <= wbs_dat_i(23 DOWNTO 16);
ELSE
lw2b_state <= SEL_3;
dat_8_reg <= wbs_dat_i(31 DOWNTO 24);
END IF;
ELSIF pasmi_wren_int = '1' AND pasmi_sector_protect_int = '1' THEN
lw2b_state <= IDLE;
dat_8_reg <= wbs_dat_i(7 DOWNTO 0);
pasmi_wren_fsm_int <= '1';
pasmi_shift_bytes_fsm_int <= '0';
ELSE
lw2b_state <= IDLE;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
END IF;
WHEN SEL_0 =>
IF(wbs_sel(1) = '1') THEN
lw2b_state <= SEL_1;
dat_8_reg <= wbs_dat_i(15 DOWNTO 8);
pasmi_wren_fsm_int <= '1';
pasmi_shift_bytes_fsm_int <= pasmi_shift_bytes_int;
ELSE
lw2b_state <= END_ACCESS;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
END IF;
WHEN SEL_1 =>
IF(wbs_sel(2) = '1') THEN
lw2b_state <= SEL_2;
dat_8_reg <= wbs_dat_i(23 DOWNTO 16);
pasmi_wren_fsm_int <= '1';
pasmi_shift_bytes_fsm_int <= pasmi_shift_bytes_int;
ELSE
lw2b_state <= END_ACCESS;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
END IF;
WHEN SEL_2 =>
IF(wbs_sel(3) = '1') THEN
lw2b_state <= SEL_3;
dat_8_reg <= wbs_dat_i(31 DOWNTO 24);
pasmi_wren_fsm_int <= '1';
pasmi_shift_bytes_fsm_int <= pasmi_shift_bytes_int;
ELSE
lw2b_state <= END_ACCESS;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
END IF;
WHEN SEL_3 =>
lw2b_state <= END_ACCESS;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
WHEN END_ACCESS =>
lw2b_state <= IDLE;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
-- coverage off
WHEN OTHERS =>
lw2b_state <= IDLE;
dat_8_reg <= dat_8_reg;
pasmi_wren_fsm_int <= '0';
pasmi_shift_bytes_fsm_int <= '0';
ASSERT FALSE REPORT "Undeocded State" SEVERITY WARNING;
-- coverage on
END CASE;
END IF;
END PROCESS z126_01_pasmi_write_access_fsm;
----------------------
-- WBS to PASMI FSM --
----------------------
z126_01_pasmi_fsm_proc : PROCESS (rst, clk)
BEGIN
IF rst = '1' THEN
wbs_ack_int <= '0';
pasmi_busy_q <= '0';
pasmi_busy_qq <= '0';
pasmi_wren_int <= '0';
pasmi_rden_int <= '0';
pasmi_shift_bytes_int <= '0';
pasmi_read_rdid_int <= '0';
pasmi_sector_protect_int <= '0';
pasmi_fast_read_int <= '0';
pasmi_write_int <= '0';
pasmi_read_status_int <= '0';
pasmi_sector_erase_int <= '0';
pasmi_bulk_erase_int <= '0';
id_oe <= '0';
status_oe <= '0';
ELSIF rising_edge(clk) THEN
pasmi_busy_q <= pasmi_busy;
pasmi_busy_qq <= pasmi_busy_q;
IF ( ctrl_sector_protect = '1' OR ctrl_sector_erase = '1'
OR ctrl_bulk_erase = '1' OR ctrl_write = '1')
AND wbs_cyc = '1' AND wbs_stb = '1' THEN
-- control actions shall be acknowledged after start
IF pasmi_busy_q = '0' AND pasmi_busy = '1' THEN -- if action is started
wbs_ack_int <= '1';
ELSE
wbs_ack_int <= '0';
END IF;
ELSIF wbs_cyc = '1' AND wbs_stb = '1'
AND pasmi_busy_q = '1' AND pasmi_busy = '0' THEN
-- read and write access shall be acknowledged when finnished
wbs_ack_int <= '1';
ELSIF wbs_cyc = '1' AND wbs_stb = '1'
AND pasmi_wren_int = '1' AND pasmi_shift_bytes_int = '1' AND pasmi_data_write_fin = '1' THEN
-- write access shall be acknowledged when byte shifting has finished (no busy signal from pasmi)
wbs_ack_int <= '1';
ELSE
wbs_ack_int <= '0';
END IF;
ELSIF falling_edge(clk) THEN
IF ctrl_write = '1' AND pasmi_busy = '0' THEN
-- for the page write command no wishbone access for ctrl_write is needed
pasmi_wren_int <= '1';
pasmi_write_int <= '1';
ELSIF pasmi_busy_q = '1' AND pasmi_busy = '0' THEN
-- reset pasmi control signals at the same moment when wishbone access acknowledged
pasmi_wren_int <= '0';
pasmi_write_int <= '0';
pasmi_shift_bytes_int <= '0';
pasmi_rden_int <= '0';
pasmi_read_rdid_int <= '0';
pasmi_sector_protect_int <= '0';
pasmi_fast_read_int <= '0';
pasmi_read_status_int <= '0';
pasmi_sector_erase_int <= '0';
pasmi_bulk_erase_int <= '0';
ELSIF wbs_cyc = '1' AND wbs_stb = '1' AND wbs_ack_int = '0' THEN
-- wishbone acces
IF pasmi_busy_qq = '0' AND pasmi_busy_q = '0' AND pasmi_busy = '0' THEN
-- set control signals until they are recognized
id_oe <= '0';
status_oe <= '0';
IF ctrl_read_sid = '1' THEN
pasmi_read_rdid_int <= '1';
id_oe <= '1';
ELSIF ctrl_sector_protect = '1' THEN
pasmi_wren_int <= '1';
pasmi_sector_protect_int <= '1';
ELSIF ctrl_read_status = '1' THEN
pasmi_read_status_int <= '1';
status_oe <= '1';
ELSIF ctrl_sector_erase = '1' THEN
pasmi_wren_int <= '1';
pasmi_sector_erase_int <= '1';
ELSIF ctrl_bulk_erase = '1' THEN
pasmi_wren_int <= '1';
pasmi_bulk_erase_int <= '1';
ELSIF wbs_we = '1' THEN
-- programm page (fill buffer)
pasmi_wren_int <= '1';
pasmi_shift_bytes_int <= '1';
ELSE
-- we = '0' (read)
pasmi_fast_read_int <= '1';
pasmi_rden_int <= '1';
END IF;
ELSE
-- the pasmi access is recognized, so the control signals can be cleared
pasmi_wren_int <= '0';
pasmi_shift_bytes_int <= '0';
pasmi_read_rdid_int <= '0';
pasmi_sector_protect_int <= '0';
pasmi_fast_read_int <= '0';
pasmi_write_int <= '0';
pasmi_read_status_int <= '0';
pasmi_sector_erase_int <= '0';
pasmi_bulk_erase_int <= '0';
-- continue read until wishbone access is finished
IF pasmi_data_read_fin = '0' THEN
pasmi_rden_int <= pasmi_rden_int;
ELSE
pasmi_rden_int <= '0';
END IF;
id_oe <= id_oe;
status_oe <= status_oe;
END IF;
ELSE
-- reset pasmi control signals after wishbone acknowledged
pasmi_wren_int <= '0';
pasmi_write_int <= '0';
pasmi_shift_bytes_int <= '0';
pasmi_rden_int <= '0';
pasmi_read_rdid_int <= '0';
pasmi_sector_protect_int <= '0';
pasmi_fast_read_int <= '0';
pasmi_read_status_int <= '0';
pasmi_sector_erase_int <= '0';
pasmi_bulk_erase_int <= '0';
END IF; -- wishbone acces
END IF; -- clk
END PROCESS z126_01_pasmi_fsm_proc;
END z126_01_wb2pasmi_arch;
| gpl-3.0 | 2fa1f32935111de3cdae8c7cd8747675 | 0.43096 | 3.992495 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/dma/rx_dma_ctrl.vhd | 1 | 7,003 | ---------------------------------------------------------------------------------------------------
--
-- Title : rx_dma_ctrl
-- Design : eth_new
-- Author : dove
-- Company : google
--
---------------------------------------------------------------------------------------------------
--
-- File : rx_dma_ctrl.vhd
-- Generated : Sun Sep 10 22:46:39 2006
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description :
--
---------------------------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {rx_dma_ctrl} architecture {arch_rx_dma_ctrl}}
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rx_dma_ctrl is
generic(
DWIDTH : natural; -- 8
RD_CYCLE : natural; -- 1
RD_DELAY : natural; -- 1
RAM_AWIDTH : natural
);
port(
clk : in std_logic;
reset : in std_logic;
ena : in std_logic;
start : in std_logic;
length : in std_logic_vector(15 downto 0);
start_waddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- start_raddr : in std_logic_vector(23 downto 0);
start_raddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : in std_logic_vector(7 downto 0);
rstep : in std_logic_vector(7 downto 0);
busy : out std_logic;
-- raddr : out std_logic_vector(23 downto 0);
raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
rdata : in std_logic_vector(DWIDTH - 1 downto 0);
wren : out std_logic;
waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wdata : out std_logic_vector(2*DWIDTH - 1 downto 0)
);
end rx_dma_ctrl;
--}} End of automatically maintained section
architecture arch_rx_dma_ctrl of rx_dma_ctrl is
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
signal length_reg : std_logic_vector(15 downto 0);
signal start_waddr_reg : std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- signal start_raddr_reg : std_logic_vector(23 downto 0);
signal start_raddr_reg : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal wstep_reg : std_logic_vector(7 downto 0);
signal rstep_reg : std_logic_vector(7 downto 0);
signal busy_buf : std_logic;
signal cycle_cnt : std_logic_vector(7 downto 0);
signal cnt : std_logic_vector(15 downto 0);
signal rden_buf : std_logic;
-- signal raddr_buf : std_logic_vector(23 downto 0);
signal raddr_buf : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal wren_buf : std_logic;
signal waddr_buf : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal rd_start : std_logic;
signal wr_start : std_logic;
signal rd_ctrl : std_logic_vector(1 downto 0);
signal wr_ctrl : std_logic_vector(1 downto 0);
signal flag : std_logic;
begin
-- DMA Status
process(clk, reset)
begin
if reset = '1' then
length_reg <= (others => '0');
start_waddr_reg <= (others => '0');
start_raddr_reg <= (others => '0');
wstep_reg <= (others => '0');
rstep_reg <= (others => '0');
elsif rising_edge(clk) then
if start = '1' then
length_reg <= length;
start_waddr_reg <= start_waddr;
start_raddr_reg <= start_raddr;
wstep_reg <= wstep;
rstep_reg <= rstep;
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '1' then
busy_buf <= '0';
elsif rising_edge(clk) then
if start = '1' then
busy_buf <= '1';
-- elsif cnt = length_reg and cycle_cnt = RD_CYCLE - 1 then
elsif cnt = length_reg then
busy_buf <= '0';
end if;
end if;
end process;
busy <= busy_buf;
process(clk, reset)
begin
if reset = '1' then
cycle_cnt <= (others => '0');
elsif rising_edge(clk) then
if busy_buf = '1' and ena = '1' then
if cycle_cnt = RD_CYCLE - 1 then
cycle_cnt <= (others => '0');
else
cycle_cnt <= cycle_cnt + 1;
end if;
else
cycle_cnt <= (others => '0');
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '1' then
cnt <= X"0000";
elsif rising_edge(clk) then
if start = '1' then
cnt <= X"0000";
elsif busy_buf = '1' and ena = '1' and (cycle_cnt = 0 or cycle_cnt = 1) then
cnt <= cnt + 1;
end if;
end if;
end process;
-- Read Ctrl
process(clk, reset)
begin
if reset = '1' then
rden_buf <= '0';
elsif rising_edge(clk) then
-- if busy_buf = '1' and ena = '1' and cycle_cnt = RD_CYCLE - 1 and cnt < length_reg then
if busy_buf = '1' and ena = '1' and (cycle_cnt = 0 or cycle_cnt = 1) and cnt < length_reg then
rden_buf <= '1';
else
rden_buf <= '0';
end if;
end if;
end process;
process(clk, reset)
begin
if reset = '1' then
raddr_buf <= (others => '0');
elsif rising_edge(clk) then
if rd_start = '1' then
raddr_buf <= start_raddr_reg;
elsif rden_buf = '1' then
raddr_buf <= raddr_buf + rstep_reg;
end if;
end if;
end process;
raddr <= raddr_buf;
-- Write Ctrl
u_wr_ctrl : shiftreg
generic map(
width => 2,
depth => RD_DELAY
)
port map(
clk => clk,
ce => '1',
D => rd_ctrl,
Q => wr_ctrl,
S => open
);
rd_ctrl(0) <= rden_buf;
rd_ctrl(1) <= rd_start;
wren_buf <= wr_ctrl(0);
wr_start <= wr_ctrl(1);
process(clk, reset)
begin
if reset = '1' then
waddr_buf <= (others => '0');
elsif rising_edge(clk) then
if wr_start = '1' then
waddr_buf <= start_waddr_reg;
elsif wren_buf = '1' and flag = '1' then
waddr_buf <= waddr_buf + wstep_reg;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
rd_start <= start;
-- wren <= wr_start or wren_buf;
end if;
end process;
process(reset, clk)
begin
if reset = '1' then
flag <= '0';
elsif rising_edge(clk) then
if wren_buf = '1' and flag = '0' then
flag <= '1';
elsif flag <= '1' then
flag <= '0';
end if;
end if;
end process;
process(reset, clk)
begin
if reset = '1' then
wren <= '0';
elsif rising_edge(clk) then
wren <= flag;
waddr <= waddr_buf;
if wren_buf = '1' and flag = '0'then
wdata(7 downto 0) <= rdata;
elsif flag = '1' then
wdata(15 downto 8) <= rdata;
end if;
end if;
end process;
-- wren <= flag;
-- waddr <= waddr_buf;
-- wdata <= rdata;
end arch_rx_dma_ctrl;
| gpl-2.0 | af14e6cea8cfb15a8e1491d74d84e2a6 | 0.53577 | 2.863042 | false | false | false | false |
QuickJack/logi-hard | hdl/virtual_instrument/virtual_top_level.vhd | 2 | 4,649 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:42:23 12/19/2013
-- Design Name:
-- Module Name: virtual_top_level - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity virtual_top_level is
port(
clk, reset : in std_logic ;
pb, sw : in std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0);
sseg_anode : out std_logic_vector(7 downto 0);
sseg_common_cathode : out std_logic_vector(7 downto 0)
);
end virtual_top_level;
architecture Behavioral of virtual_top_level is
constant DIVIDER1HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(100_000_000, 32));
constant DIVIDER5HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(20_000_000, 32));
constant DIVIDER10HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(10_000_000, 32));
constant DIVIDER100HZ : std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(1_000_000, 32));
signal divider_output1hz,divider_output5hz ,divider_output10hz ,divider_output100hz : std_logic_vector(31 downto 0);
signal onehz_signal, fivehz_signal, tenhz_signal, onehundredhz_signal : std_logic ;
signal update_count_output: std_logic;
signal counter_output : std_logic_vector(7 downto 0);
signal counter_enable, counter_reset : std_logic ;
signal sel: std_logic_vector(1 downto 0);
begin
process(clk, reset)
begin
if reset='1' then
divider_output1hz <= DIVIDER1HZ ;
divider_output5hz <= DIVIDER5HZ ;
divider_output10hz <= DIVIDER10HZ;
divider_output100hz <= DIVIDER100HZ;
elsif clk'event and clk = '1' then
if divider_output1hz = 0 then
divider_output1hz <= DIVIDER1HZ ;
else
divider_output1hz <= divider_output1hz - 1 ;
end if ;
if divider_output5hz = 0 then
divider_output5hz <= DIVIDER5HZ ;
else
divider_output5hz <= divider_output5hz - 1 ;
end if ;
if divider_output10hz = 0 then
divider_output10hz <= DIVIDER10HZ ;
else
divider_output10hz <= divider_output10hz - 1 ;
end if ;
if divider_output100hz = 0 then
divider_output100hz <= DIVIDER100HZ ;
else
divider_output100hz <= divider_output100hz - 1 ;
end if ;
end if ;
end process ;
onehz_signal <= '1' when divider_output1hz = 0 else
'0' ;
fivehz_signal <= '1' when divider_output5hz = 0 else
'0' ;
tenhz_signal <= '1' when divider_output10hz = 0 else
'0' ;
onehundredhz_signal <= '1' when divider_output100hz = 0 else
'0' ;
--mux the count out enable input different frequncy values
with sw(7 downto 6) select
update_count_output <= onehz_signal when "00",
fivehz_signal when "01",
tenhz_signal when "10",
onehundredhz_signal when "11";
counter_enable <= sw(0);
counter_reset <= pb(1);
process(clk, reset)
begin
if reset = '1' then
counter_output <= (others => '0');
elsif clk'event and clk = '1' then
if counter_reset = '1' then
counter_output <= (others => '0');
elsif counter_enable = '1' and update_count_output = '1' then --100 hz updateupdate_count_output
counter_output <= counter_output + 1;
end if ;
end if ;
end process ;
led(7 downto 0) <= counter_output;
sseg_common_cathode <= (others => '0');
sseg_anode(7) <= '0' ; -- dot point
with counter_output(3 downto 0) select
--"gfedcba" segments
sseg_anode(6 downto 0)<= "0111111" when "0000",--0
"0000110" when "0001",--1
"1011011" when "0010",--2
"1001111" when "0011",--3
"1100110" when "0100",--4
"1101101" when "0101",--5
"1111101" when "0110",--6
"0000111" when "0111",--7
"1111111" when "1000",--8
"1101111" when "1001",--9
"1110111" when "1010", --a
"1111100" when "1011", --b
"0111001" when "1100", --c
"1011110" when "1101", --d
"1111001" when "1110", --e
"1110001" when others; --f
end Behavioral;
| lgpl-3.0 | bce77cf7c7532ae978ab094670ceffde | 0.62336 | 3.239721 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/user_logic/user_logic_dwt.vhd | 2 | 15,862 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Quicksort
-- Thread implements the quicksort algorithm
-- Passed in argument is a pointer to following struct
-- struct sortData {
-- int * startData; //pointer to start of array
-- int * endData; //pointer to end of array
-- int cacheOption // 1 operate on data where it is, 0 copy into HWTI first
-- There is not return argument, the HWT just sorts the data.
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
READ_ARGS_1,
READ_ARGS_2,
READ_ARGS_3,
WHILE_1,
WHILE_2,
WHILE_3,
WHILE_4,
WHILE_5,
WHILE_6,
WHILE_7,
WHILE_8,
FOO,
LOOP_1,
LOOP_2,
LOOP_3,
LOOP_4,
LOOP_5,
LOOP_6,
EXIT_THREAD,
EXIT_THREAD_1,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next : state_machine := FUNCTION_RESET;
signal arg, arg_next : std_logic_vector(0 to 31);
signal sig, sig_next : std_logic_vector(0 to 31);
signal len, len_next : std_logic_vector(0 to 31);
signal i, i_next : std_logic_vector(0 to 31);
signal r1, r1_next : std_logic_vector(0 to 31);
signal r2, r2_next : std_logic_vector(0 to 31);
signal r3, r3_next : std_logic_vector(0 to 31);
signal r4, r4_next : std_logic_vector(0 to 31);
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
arg <= arg_next;
sig <= sig_next;
len <= len_next;
i <= i_next;
r1 <= r1_next;
r2 <= r2_next;
r3 <= r3_next;
r4 <= r4_next;
return_state <= return_state_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (current_state) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
next_state <= current_state;
return_state_next <= return_state;
arg_next <= arg;
sig_next <= sig;
len_next <= len;
i_next <= i;
r1_next <= r1;
r2_next <= r2;
r3_next <= r3;
r4_next <= r4;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
arg_next <= Z32;
sig_next <= Z32;
len_next <= Z32;
i_next <= Z32;
r1_next <= Z32;
r2_next <= Z32;
r3_next <= Z32;
r4_next <= Z32;
when FUNCTION_START =>
-- read the passed in argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_address <= Z32;
return_state_next <= READ_ARGS_1;
next_state <= WAIT_STATE;
-- struct Array * arrayPtr;
-- arrayPtr = (struct Array *) arg;
-- Huint * sig = arrayPtr->data;
when READ_ARGS_1 =>
arg_next <= toUser_value;
-- Read the address of the data array
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
return_state_next <= READ_ARGS_2;
next_state <= WAIT_STATE;
-- Huint len = arrayPtr->length
when READ_ARGS_2 =>
sig_next <= toUser_value;
-- Read value of length
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
return_state_next <= READ_ARGS_3;
next_state <= WAIT_STATE;
-- int i=0
-- Huint tmp[LENGTH];
when READ_ARGS_3 =>
len_next <= toUser_value;
-- initialize i
i_next <= Z32;
-- Declare len number of variables on the stack
thrd2intrfc_opcode <= OPCODE_DECLARE;
thrd2intrfc_value <= toUser_value;
return_state_next <= WHILE_1;
next_state <= WAIT_STATE;
-- while ( i < (len >> 1 ) ) {
when WHILE_1 =>
-- set r1 to len >> 1
r1_next <= '0' & len(0 to 30);
-- set r2 to i << 1
r2_next <= i(1 to 31) & '0';
next_state <= WHILE_2;
when WHILE_2 =>
if ( i < r1 ) then
next_state <= WHILE_3;
else
next_state <= FOO;
end if;
-- tmp[(i<<1)+1] = (sig[(i<<1)] + sig[(i<<1)+1]) >> 1;
when WHILE_3 =>
-- Read the value of sig[(i<<1)]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= sig + (r2(2 to 31) & "00");
return_state_next <= WHILE_4;
next_state <= WAIT_STATE;
when WHILE_4 =>
r3_next <= toUser_value;
-- Read the value of sig[(i<<1) + 1]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= sig + (r2(2 to 31) & "00") + x"00000004";
return_state_next <= WHILE_5;
next_state <= WAIT_STATE;
when WHILE_5 =>
-- Calculate the averaged value
r4_next <= ('0' & r3(0 to 30)) + ('0' & toUser_value(0 to 30));
next_state <= WHILE_6;
when WHILE_6 =>
-- write the average value to tmp array
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= r2 + x"00000001";
thrd2intrfc_value <= r4;
return_state_next <= WHILE_7;
next_state <= WAIT_STATE;
-- tmp[(i<<1)] = (sig[(i<<1)] - tmp[(i<<1) + 1];
when WHILE_7 =>
-- write the difference to tmp array
thrd2intrfc_opcode <= OPCODE_WRITE;
thrd2intrfc_address <= r2;
thrd2intrfc_value <= r3 - r4;
return_state_next <= WHILE_8;
next_state <= WAIT_STATE;
-- i++;
when WHILE_8 =>
-- increment i
i_next <= i + x"00000001";
next_state <= WHILE_1;
-- i=0;
when FOO =>
i_next <= Z32;
next_state <= LOOP_1;
-- while ( i < (len >> 1 ) ) {
when LOOP_1 =>
-- set r2 to i << 1
r2_next <= i(1 to 31) & '0';
-- Check the while condition
if ( i < r1 ) then
next_state <= LOOP_2;
else
next_state <= EXIT_THREAD;
end if;
-- sig[i] = tmp[(i<<1)+1];
when LOOP_2 =>
-- read the value of the tmp array
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= r2 + x"00000001";
return_state_next <= LOOP_3;
next_state <= WAIT_STATE;
when LOOP_3 =>
-- write the temp value back to data array
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= sig + (i(2 to 31) & "00");
thrd2intrfc_value <= toUser_value;
return_state_next <= LOOP_4;
next_state <= WAIT_STATE;
-- sig[(len>>1)+i] = tmp[(i<<1)];
when LOOP_4 =>
-- read the value of the tmp array
thrd2intrfc_opcode <= OPCODE_READ;
thrd2intrfc_address <= r2;
return_state_next <= LOOP_5;
next_state <= WAIT_STATE;
when LOOP_5 =>
-- write the temp value back to data array
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= sig + (r1(2 to 31) & "00") + (i(2 to 31) & "00");
thrd2intrfc_value <= toUser_value;
return_state_next <= LOOP_6;
next_state <= WAIT_STATE;
when LOOP_6 =>
-- increment i
i_next <= i + x"00000001";
next_state <= LOOP_1;
when EXIT_THREAD =>
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
return_state_next <= EXIT_THREAD_1;
next_state <= WAIT_STATE;
when EXIT_THREAD_1 =>
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
next_state <= WAIT_STATE;
when WAIT_STATE =>
case toUser_goWait is
when '1' => --Here because HWTUL chose to be here for one clock cycle
next_state <= return_state;
when OTHERS => --ie '0', Here because HWTI is telling us to wait
next_state <= return_state;
end case;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | fbe5ed7818f8376fcd15ac51ba7fe947 | 0.555163 | 3.614859 | false | false | false | false |
myriadrf/A2300 | hdl/wca/hal/FiFo512Core32W32R/simulation/FiFo512Core32W32R_rng.vhd | 1 | 4,014 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY FiFo512Core32W32R_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF FiFo512Core32W32R_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | a59974ebf3e584110bb8a9dc16c18904 | 0.624564 | 4.142415 | false | false | false | false |
QuickJack/logi-hard | test_bench/max7219_tb.vhd | 2 | 4,814 |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:21:19 08/19/2013
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/max7219_tb.vhd
-- Project Name: logipi_face
-- Target Device:
-- Tool versions: ISE 14.1
-- Description:
--
-- VHDL Test Bench Created by ISE for module: max7219
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY max7219_tb IS
END max7219_tb;
ARCHITECTURE behavior OF max7219_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT wishbone_max7219
PORT(
gls_reset : IN std_logic;
gls_clk : IN std_logic;
wbs_address : IN std_logic_vector(15 downto 0);
wbs_writedata : IN std_logic_vector(15 downto 0);
wbs_readdata : OUT std_logic_vector(15 downto 0);
wbs_strobe : IN std_logic;
wbs_cycle : IN std_logic;
wbs_write : IN std_logic;
wbs_ack : OUT std_logic;
DOUT : OUT std_logic;
SCLK : OUT std_logic;
LOAD : OUT std_logic
);
END COMPONENT;
--Inputs
signal gls_reset : std_logic := '0';
signal gls_clk : std_logic := '0';
signal wbs_address : std_logic_vector(15 downto 0) := (others => '0');
signal wbs_writedata : std_logic_vector(15 downto 0) := (others => '0');
signal wbs_strobe : std_logic := '0';
signal wbs_cycle : std_logic := '0';
signal wbs_write : std_logic := '0';
--Outputs
signal wbs_readdata : std_logic_vector(15 downto 0);
signal wbs_ack : std_logic;
signal DOUT : std_logic;
signal SCLK : std_logic;
signal LOAD : std_logic;
-- Clock period definitions
constant gls_clk_period : time := 10 ns;
constant SCLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: wishbone_max7219
PORT MAP (
gls_reset => gls_reset,
gls_clk => gls_clk,
wbs_address => wbs_address,
wbs_writedata => wbs_writedata,
wbs_readdata => wbs_readdata,
wbs_strobe => wbs_strobe,
wbs_cycle => wbs_cycle,
wbs_write => wbs_write,
wbs_ack => wbs_ack,
DOUT => DOUT,
SCLK => SCLK,
LOAD => LOAD
);
-- Clock process definitions
gls_clk_process :process
begin
gls_clk <= '0';
wait for gls_clk_period/2;
gls_clk <= '1';
wait for gls_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
gls_reset <= '1' ;
wbs_strobe <= '0';
wbs_cycle <= '0' ;
wbs_write <= '0' ;
wait for 100 ns;
gls_reset <= '0' ;
wait for gls_clk_period*10;
wbs_address <= X"0000";
wbs_writedata <= X"AA55" ;
wbs_strobe <= '1';
wbs_cycle <= '1' ;
wbs_write <= '1' ;
wait for gls_clk_period*10;
wbs_strobe <= '0';
wbs_cycle <= '0' ;
wbs_write <= '0' ;
wait for gls_clk_period*10;
wbs_address <= X"0001";
wbs_writedata <= X"55AA" ;
wbs_strobe <= '1';
wbs_cycle <= '1' ;
wbs_write <= '1' ;
wait for gls_clk_period*10;
wbs_strobe <= '0';
wbs_cycle <= '0' ;
wbs_write <= '0' ;
-- insert stimulus here
wait;
end process;
END;
| lgpl-3.0 | 68540e65b8141d16c2bd702669bed3f6 | 0.58413 | 3.655277 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/stress/mutex_lock_1.vhd | 2 | 17,362 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
--signal reg5, reg5_next : std_logic_vector(0 to 31);
--signal reg6, reg6_next : std_logic_vector(0 to 31);
--signal reg7, reg7_next : std_logic_vector(0 to 31);
--signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
--retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
--reg5 <= reg5_next;
--reg6 <= reg6_next;
--reg7 <= reg7_next;
--reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
--retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
--reg5_next <= reg5;
--reg6_next <= reg6;
--reg7_next <= reg7;
--reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: mutex_lock_stress_1
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mutex = (hthread_mutex_t*) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
next_state <= STATE_2;
-- hthread_mutex_lock( mutex );
when STATE_2 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- hthread_yield();
when STATE_4 =>
-- call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_YIELD;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_5;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( mutex );
when STATE_5 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- call mutex lock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
when STATE_7 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 9ba4b6297332ab119f2fbb21919f2f75 | 0.531045 | 3.809963 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/write_buffer.vhd | 3 | 27,635 | -------------------------------------------------------------------------------
-- $Id: write_buffer.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- write_buffer.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address
-- multiplexer.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2004,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: write_buffer.vhd
--
-- Description: This vhdl design file is for the entity and architecture
-- of the write buffer design.
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- write_buffer.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
--
--
-- GAB 04/14/04
-- ^^^^^^
-- Updated to proc_common_v2_00_a
-- Fixed issues with master aborts, delayed IP acknowledges, and single
-- beat reads (i.e. rdce was 2 clocks wide)
-- ~~~~~~~
-- GAB 07/07/04
-- ^^^^^^
-- Fixed issues with xferack due to changes in opb_bam signal timing
-- Fixed wrbuf_burst signal to negate 1 cycle before cs negates
-- Fixed wrbuf_addrvalid signal to only drive during valid addresses
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.or_reduce;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.srl_fifo3;
use opb_v20_v1_10_d.proc_common_pkg.log2;
use opb_v20_v1_10_d.counter;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity write_buffer is
generic (
C_INCLUDE_OPBIN_PSTAGE : boolean := TRUE;
C_INCLUDE_IPIC_PSTAGE : boolean := TRUE;
C_INCLUDE_OPBOUT_PSTAGE : boolean := TRUE;
C_OPB_DWIDTH : integer := 32;
C_WRBUF_DEPTH : integer := 16; -- max is 16
C_NUM_CES : integer := 4;
C_NUM_ARDS : integer := 4
);
port (
-- Clock and Reset
Bus_reset : in std_logic;
Bus_clk : in std_logic;
-- Inputs
Data_in : in std_logic_vector(0 to C_OPB_DWIDTH-1);
CE : in std_logic_vector(0 to C_NUM_CES-1);
Wr_CE : in std_logic_vector(0 to C_NUM_CES-1);
Rd_CE : in std_logic_vector(0 to C_NUM_CES-1);
RNW : in std_logic;
CS_hit : in std_logic_vector(0 to C_NUM_ARDS-1);
CS : in std_logic_vector(0 to C_NUM_ARDS-1);
CS_enable : in std_logic_vector(0 to C_NUM_ARDS-1);
Burst : in std_logic;
Xfer_start : in std_logic;
Xfer_done : in std_logic;
Addr_ack : in std_logic;
Wrdata_ack : in std_logic;
WrBuf_data : out std_logic_vector(0 to C_OPB_DWIDTH-1);
WrBuf_burst : out std_logic;
WrBuf_xferack : out std_logic;
WrBuf_errack : out std_logic;
WrBuf_retry : out std_logic;
WrBuf_CS : out std_logic_vector(0 to C_NUM_ARDS-1);
WrBuf_RNW : out std_logic;
WrBuf_CE : out std_logic_vector(0 to C_NUM_CES-1);
WrBuf_WrCE : out std_logic_vector(0 to C_NUM_CES-1);
WrBuf_RdCE : out std_logic_vector(0 to C_NUM_CES-1);
WrBuf_Empty : out std_logic;
WrBuf_AddrCnt_en : out std_logic;
WrBuf_AddrCntr_rst : out std_logic;
WrBuf_AddrValid : out std_logic;
IPIC_Pstage_CE : out std_logic
);
end write_buffer;
architecture implementation of write_buffer is
-----------------------------------------------------------------------------
-- Functions
-----------------------------------------------------------------------------
function "and" ( l : std_logic_vector; r : std_logic )
return std_logic_vector is
variable rex : std_logic_vector(l'range);
begin
rex := (others=>r);
return( l and rex );
end function "and";
-------------------------------------------------------------------------------
-- Constant Declaration
-------------------------------------------------------------------------------
constant ZERO_LOAD : std_logic_vector(0 to 4) := (others => '0');
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
signal wrbuf_write : std_logic;
signal wrbuf_write_d1 : std_logic;
signal wrbuf_write_re : std_logic;
signal wrbuf_read : std_logic;
signal wrbuf_data_i : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal wrbuf_full : std_logic;
signal wrbuf_empty_i : std_logic;
signal wrbuf_empty_d1 : std_logic;
signal wrbuf_empty_fe : std_logic;
signal wrdata_ack_d1 : std_logic;
signal wrbuf_addr : std_logic_vector(0 to 3);
signal wrbuf_going_full : std_logic;
signal wrbuf_going_empty : std_logic;
signal wrbuf_wrce_i : std_logic_vector(0 to C_NUM_CES-1);
signal wrbuf_rdce_i : std_logic_vector(0 to C_NUM_CES-1);
signal wrbuf_ce_i : std_logic_vector(0 to C_NUM_CES-1);
signal wrbuf_rnw_i : std_logic;
signal wrbuf_burst_i : std_logic;
signal wrbuf_cs_i : std_logic_vector(0 to C_NUM_ARDS-1);
signal wrbuf_addrcnt_en_i : std_logic;
signal wrbuf_addrcntr_rst_i: std_logic;
signal wrbuf_xferack_i : std_logic;
signal wrbuf_retry_i : std_logic;
signal wrbuf_retry_d1 : std_logic;
signal wrbuf_retry_d2 : std_logic;
signal valid_addr_cntr_ce : std_logic;
signal valid_addr_cnt : std_logic_vector(0 to 4);
signal sample_hold_ce : std_logic;
signal xfer_start_reg : std_logic;
signal cs_rnw_rst : std_logic;
signal wrbuf_write_i : std_logic;
signal burst_d1 : std_logic;
signal wrbuf_full_retry : std_logic;
signal wrbuf_xferack_cmb : std_logic;
signal wrbuf_xferack_d1 : std_logic;
signal wr_ce_i : std_logic;
signal wrbuf2ip_burst : std_logic;
signal wrbuf_addrvalid_i : std_logic;
-------------------------------------------------------------------------------
-- Begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Output assignments
-------------------------------------------------------------------------------
WrBuf_data <= wrbuf_data_i;
WrBuf_RNW <= wrbuf_rnw_i;
WrBuf_Burst <= wrbuf2ip_burst;
WrBuf_WrCE <= wrbuf_wrce_i;
WrBuf_RdCE <= wrbuf_rdce_i;
WrBuf_CE <= wrbuf_ce_i;
WrBuf_CS <= wrbuf_cs_i;
WrBuf_AddrCnt_en <= wrbuf_addrcnt_en_i;
WrBuf_AddrCntr_Rst <= wrbuf_addrcntr_rst_i;
WrBuf_Empty <= wrbuf_empty_i;
-------------------------------------------------------------------------------
-- Transaction acknowledges
-------------------------------------------------------------------------------
-- XferAck--
-- Assert XferAck when at the start of a xfer if wrbuffer is empty, keep
-- asserted until wrbuffer is full or cs_hit = 0
-- Don't need to qualify with CS_Hit because the XferAck logic in OPB_BAM
-- takes care of this
--ToDo: see if wrbuf_going_empty can be used
XFERACK_REG: process(Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
if or_reduce(CS_hit) ='0'
or (wrbuf_xferack_i = '1' and Burst = '0')
or (wrbuf_rnw_i='0' and wrbuf_going_empty='1' and wrdata_ack='1')then
wrbuf_xferack_i <= '0';
elsif xfer_start = '1' and wrbuf_empty_i = '1' and RNW = '0' then
wrbuf_xferack_i <= '1';
end if;
end if;
end process XFERACK_REG;
wrbuf_xferack_cmb <= (((wrbuf_xferack_i and or_reduce(CS_hit))
or (or_reduce(CS_hit) and wrbuf_empty_i
and not(RNW) and xfer_start and Burst))
and not wrbuf_going_full);
-- Generate for pipeline models 5 and 7
GEN_PIPE_5_7 : if C_INCLUDE_OPBIN_PSTAGE = true
and C_INCLUDE_OPBOUT_PSTAGE = true generate
WrBuf_xferack <= wrbuf_xferack_d1 and not wrbuf_going_full
and not wrbuf_retry_i and or_reduce(CS_hit);
end generate;
-- Generate for pipeline models 1,2,3,4,and 6
GEN_PIPE_THE_REST : if (C_INCLUDE_OPBIN_PSTAGE = false
or C_INCLUDE_OPBOUT_PSTAGE = false)generate
WrBuf_xferack <= wrbuf_xferack_d1 and not wrbuf_retry_i
and or_reduce(CS_hit);
end generate;
-------------------------------------------------------------------------------
-- Transaction Retry
-------------------------------------------------------------------------------
-- If the write buffer is almost full set the full retry flag
-- keep this flag set until the write buffer empties. This
-- will prevent further cycles from occuring once the write
-- buffer becomes full.
RETRY_FULL_PROCESS : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
-- When buffer returns to empty state then reset retry flag
if(Bus_reset = '1' or wrbuf_empty_i = '1')then
wrbuf_full_retry <= '0';
-- When buffer is almost full set retry flag
elsif(wrbuf_going_full = '1')then
wrbuf_full_retry <= '1';
end if;
end if;
end process RETRY_FULL_PROCESS;
wrbuf_retry_i <= (xfer_start and not wrbuf_empty_i)
or (RNW and not wrbuf_empty_i)
or (wrbuf_full_retry);
WrBuf_retry <= wrbuf_retry_i;
-------------------------------------------------------------------------------
-- Transaction Error
-------------------------------------------------------------------------------
-- This signal is never asserted
WrBuf_errack <= '0';
-------------------------------------------------------------------------------
-- Actual write buffer implemented using SRL_FIFO
-------------------------------------------------------------------------------
WRBUF_DATA_FIFO: entity opb_v20_v1_10_d.srl_fifo3
generic map ( C_DWIDTH => C_OPB_DWIDTH,
C_DEPTH => C_WRBUF_DEPTH)
port map (
Clk => Bus_clk,
Reset => Bus_reset,
FIFO_Write => wrbuf_write,
Data_In => Data_in,
FIFO_Read => wrbuf_read,
Data_Out => wrbuf_data_i,
FIFO_Full => wrbuf_full,
FIFO_Empty => wrbuf_empty_i,
FIFO_AlmostEmpty => wrbuf_going_empty,
Data_Exists => open,
Addr => wrbuf_addr
);
-------------------------------------------------------------------------------
-- Generation of write buffer control signals
-------------------------------------------------------------------------------
FIFO_WRITE_2_GEN : if not(C_INCLUDE_OPBIN_PSTAGE)
and (C_INCLUDE_IPIC_PSTAGE)
and not(C_INCLUDE_OPBOUT_PSTAGE) generate
wrbuf_write_i <= (xfer_start and not RNW and not Burst and not(wrbuf_retry_i))
or (wr_ce_i and not(wrbuf_retry_d1) and not(wrbuf_retry_i));
end generate;
FIFO_WRITE_REST_GEN : if C_INCLUDE_OPBIN_PSTAGE
or not(C_INCLUDE_IPIC_PSTAGE)
or C_INCLUDE_OPBOUT_PSTAGE generate
wrbuf_write_i <= (xfer_start and not RNW and not Burst and not(wrbuf_retry_i))
or (wr_ce_i and not(wrbuf_retry_d1));
end generate;
wrbuf_write <= wrbuf_write_i;
wrbuf_read <= Wrdata_ack;
-- Write Buffer is almost full
wrbuf_going_full <= '1' when wrbuf_addr >= C_WRBUF_DEPTH-3
else '0';
REG_FOR_FMAX_PROCESS : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wrbuf_xferack_d1 <= wrbuf_xferack_cmb;
wrbuf_retry_d1 <= wrbuf_retry_i;
end if;
end process REG_FOR_FMAX_PROCESS;
-- Generate register for pipeline models 5 and 7
REGWRCE_GEN_5_7 : if C_INCLUDE_OPBIN_PSTAGE and C_INCLUDE_OPBOUT_PSTAGE generate
REG_WRCE : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wr_ce_i <= or_reduce(Wr_CE)
and Burst
and not(wrbuf_retry_d2);
wrbuf_retry_d2 <= wrbuf_retry_d1;
end if;
end process REG_WRCE;
end generate;
-- Generate register for pipeline models 1,3,4, and 6
REGWRCE_GEN_1_3_4_6 : if (C_INCLUDE_OPBIN_PSTAGE and not(C_INCLUDE_OPBOUT_PSTAGE))
or (not(C_INCLUDE_OPBIN_PSTAGE) and C_INCLUDE_OPBOUT_PSTAGE) generate
REG_WRCE : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wr_ce_i <= or_reduce(Wr_CE)
and Burst
and not(wrbuf_retry_d1);
end if;
end process REG_WRCE;
end generate;
-- Generate register for pipeline models 0 and 2
REGWRCE_GEN_0_2 : if not(C_INCLUDE_OPBIN_PSTAGE) and not(C_INCLUDE_OPBOUT_PSTAGE) generate
REG_WRCE : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wr_ce_i <= or_reduce(Wr_CE)
and Burst;
end if;
end process REG_WRCE;
end generate;
-------------------------------------------------------------------------------
-- Need to count number of valid addresses to be generated (matches the number
-- of data words written into the write buffer) and allow the
-- address counter to only produce that number of addresses
-- counter only needs to count to the max buffer size (16)
-- count up with each wrbuf_write and count down with each Addr_ack - don't
-- count when wrbuf_write and Addr_ack are both asserted
--------------------------------------------------------------------------------
valid_addr_cntr_ce <= wrbuf_write xor Addr_ack;
VALID_ADDR_CNTR: entity opb_v20_v1_10_d.counter
generic map ( C_NUM_BITS => 5)
port map (
Clk => Bus_clk,
Rst => cs_rnw_rst,
Load_In => ZERO_LOAD,
Count_Enable => valid_addr_cntr_ce,
Count_Load => '0',
Count_Down => Addr_ack,
Count_Out => valid_addr_cnt,
Carry_Out => open
);
wrbuf_addrcnt_en_i <= '0' when (valid_addr_cnt = "00000" and wrbuf_rnw_i = '0')
else '1';
wrbuf_addrcntr_rst_i <= '1'
when ( (valid_addr_cnt = "00001" and Addr_Ack = '1'
and valid_addr_cntr_ce ='1')
or Bus_reset = '1' )
else '0';
WRBUF_ADDRVALID_REG: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
if (wrbuf_addrcntr_rst_i = '1' and wrbuf_rnw_i = '0')
or (wrbuf_rnw_i = '1' and Addr_ack = '1' and wrbuf_burst_i ='0') then
wrbuf_addrvalid_i <= '0';
elsif xfer_start = '1' then
wrbuf_addrvalid_i <= '1';
end if;
end if;
end process WRBUF_ADDRVALID_REG;
WrBuf_AddrValid <= wrbuf_addrvalid_i when or_reduce(wrbuf_cs_i) = '1'
else '0';
-------------------------------------------------------------------------------
-- Sample and hold Bus2IP_CS, Bus2IP_Burst and Bus2IP_RNW until write buffer is
-- empty and Ack is received from the IP since the OPB Address, SeqAddr, and RNW
-- signals will be modified for the next transaction
--
-- Delay CEs by 1 clock to account for buffer delay
-------------------------------------------------------------------------------
XFER_START_REG_PROCESS: process(Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
if or_reduce(CS_enable) = '1' then
xfer_start_reg <= '0';
elsif xfer_start = '1' then
xfer_start_reg <= '1';
end if;
end if;
end process XFER_START_REG_PROCESS;
sample_hold_ce <= ((xfer_start or xfer_start_reg) and wrbuf_empty_i);
DELAY_REG: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
wrbuf_empty_d1 <= wrbuf_empty_i;
wrdata_ack_d1 <= Wrdata_ack;
wrbuf_write_d1 <= wrbuf_write;
burst_d1 <= Burst; --GB
end if;
end process DELAY_REG;
cs_rnw_rst <= Bus_reset or
(not(wrbuf_rnw_i) and wrbuf_going_empty and wrdata_ack ) or
(wrbuf_rnw_i and Xfer_done);
wrbuf_empty_fe <= not(wrbuf_empty_i) and wrbuf_empty_d1;
wrbuf_write_re <= wrbuf_write and not(wrbuf_write_d1);
BURST_RNW_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
wrbuf_rnw_i <= '0';
wrbuf_burst_i <= '0';
elsif sample_hold_ce = '1' then
wrbuf_rnw_i <= RNW;
wrbuf_burst_i <= Burst;
end if;
end if;
end process BURST_RNW_SAMPLE_HOLD;
-- Logic for negating burst signal 1 clock before end of cycle.
wrbuf2ip_burst <= wrbuf_burst_i when cs_rnw_rst='0' and or_reduce(wrbuf_cs_i) = '1'
else '0';
----------------------------------------------------------------------
-- Bus2IP Control Signals
----------------------------------------------------------------------
-- Generate for no output pipeline stage
GEN_WITHOUT_OUTPIPE : if C_INCLUDE_OPBOUT_PSTAGE = false generate
CS_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
wrbuf_cs_i <= (others => '0');
wrbuf_wrce_i <= (others => '0');
wrbuf_rdce_i <= (others => '0');
wrbuf_ce_i <= (others => '0');
elsif wrbuf_write_re = '1' or
(sample_hold_ce = '1' and RNW = '1') then
wrbuf_cs_i <= CS;
wrbuf_wrce_i <= Wr_CE;
wrbuf_rdce_i <= Rd_CE;
wrbuf_ce_i <= CE;
end if;
end if;
end process CS_SAMPLE_HOLD;
end generate GEN_WITHOUT_OUTPIPE;
-- Generate for output pipeline stage
GEN_WITH_OUTPIPE : if C_INCLUDE_OPBOUT_PSTAGE = true generate
signal read_rdce_i : std_logic_vector(0 to C_NUM_CES-1);
signal read_cs_i : std_logic_vector(0 to C_NUM_ARDS-1);
signal read_ce_i : std_logic_vector(0 to C_NUM_CES-1);
signal write_cs_i : std_logic_vector(0 to C_NUM_ARDS-1);
signal write_ce_i : std_logic_vector(0 to C_NUM_CES-1);
begin
WRCS_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
write_cs_i <= (others => '0');
wrbuf_wrce_i <= (others => '0');
write_ce_i <= (others => '0');
elsif wrbuf_write_re = '1' then
write_cs_i <= CS;
wrbuf_wrce_i <= Wr_CE;
write_ce_i <= CE;
end if;
end if;
end process WRCS_SAMPLE_HOLD;
RDCS_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
read_cs_i <= (others => '0');
read_rdce_i <= (others => '0');
read_ce_i <= (others => '0');
elsif sample_hold_ce = '1' and RNW = '1' then
read_cs_i <= CS;
read_rdce_i <= Rd_CE;
read_ce_i <= CE;
end if;
end if;
end process RDCS_SAMPLE_HOLD;
-- Gate off rdce signal to make it a single clock cycle during single beat reads
GEN_RDCE_BUS : process(read_rdce_i, Xfer_done, wrbuf_burst_i)
begin
for i in 0 to C_NUM_CES-1 loop
wrbuf_rdce_i(i) <= (read_rdce_i(i) and wrbuf_burst_i)
or (read_rdce_i(i) and not(wrbuf_burst_i) and not Xfer_done);
end loop;
end process GEN_RDCE_BUS;
-- Gate off ce signal to make it a single clock cycle during single beat reads
GEN_CE_BUS : process(write_ce_i,read_ce_i, Xfer_done, wrbuf_burst_i)
begin
for i in 0 to C_NUM_CES-1 loop
wrbuf_ce_i(i) <= (read_ce_i(i) and wrbuf_burst_i)
or (read_ce_i(i) and not(wrbuf_burst_i) and not Xfer_done)
or write_ce_i(i);
end loop;
end process GEN_CE_BUS;
-- Gate off cs signal to make it a single clock cycle during single beat reads
GEN_CS_BUS : process(write_cs_i,read_cs_i, Xfer_done, wrbuf_burst_i)
begin
for i in 0 to C_NUM_ARDS-1 loop
wrbuf_cs_i(i) <= (read_cs_i(i) and wrbuf_burst_i)
or (read_cs_i(i) and not(wrbuf_burst_i) and not Xfer_done)
or write_cs_i(i);
end loop;
end process GEN_CS_BUS;
end generate GEN_WITH_OUTPIPE;
-------------------------------------------------------------------------------
-- Logic when IPIC_PSTAGE is included
-------------------------------------------------------------------------------
IPIC_PSTAGE_GEN: if C_INCLUDE_IPIC_PSTAGE generate
IPIC_Pstage_CE <= not(wrbuf_empty_i);
end generate IPIC_PSTAGE_GEN;
NO_IPIC_PSTAGE_GEN: if not(C_INCLUDE_IPIC_PSTAGE) generate
IPIC_Pstage_CE <= '1';
end generate NO_IPIC_PSTAGE_GEN;
end implementation;
| bsd-3-clause | 5de09bf718c49a16173da4126ae90aeb | 0.469369 | 4.088018 | false | false | false | false |
a4a881d4/zcpsm | src/zcpsm/core/zheap.vhd | 1 | 966 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library synplify;
--use synplify.attributes.all;
entity zHeap is
port (
reset : in std_logic;
addra: in std_logic_vector(4 downto 0);
dia: in std_logic_vector(7 downto 0);
wea: in std_logic;
clk: in std_logic;
clk_en: in std_logic; --
addrb: in std_logic_vector(4 downto 0);
doa: out std_logic_vector(7 downto 0);
dob: out std_logic_vector(7 downto 0)
);
end zHeap;
architecture behavior of zHeap is
type mem is array(0 to 31) of std_logic_vector(7 downto 0);
signal heap: mem:=(others=>(others=>'0'));
begin
doa <= heap(conv_integer(addra));
dob <= heap(conv_integer(addrb));
wr:
process(clk)
begin
if rising_edge(clk) then
if clk_en='0' then
if wea='1' then
heap(conv_integer(addra)) <= dia;
end if;
end if;
end if;
end process wr;
end behavior;
| gpl-2.0 | 3ecb1c9ecac006f39648a2fcf62b3347 | 0.632505 | 2.668508 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/eval_timer.vhd | 2 | 11,245 | -------------------------------------------------------------------------------
-- $Id: eval_timer.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- eval_timer.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: eval_timer.vhd
-- Version: v1.00a
-- Description: 40-bit counter that enables IP to be used in an evaluation
-- mode. Once the counter expires, the eval_timeout signal
-- asserts and can be used to reset the IP.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- eval_timer.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from PCI eval timer
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No generics
--
-- Definition of Ports:
-- Clk -- clock
-- Rst -- active high reset
-- Eval_timeout -- timer has expired
-------------------------------------------------------------------------------
entity eval_timer is
port (
Clk : in std_logic;
Rst : in std_logic;
Eval_timeout : out std_logic
);
end entity eval_timer;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of eval_timer is
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_BITS : integer := 8;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
signal co : std_logic_vector(0 to 4); -- carry out
signal ceo : std_logic_vector(0 to 4); -- count enable out
signal ceo_d1 : std_logic_vector(0 to 4); -- registered count enable out
signal zeros : std_logic_vector(NUM_BITS-1 downto 0);
-----------------------------------------------------------------------------
-- Component Declarations
-----------------------------------------------------------------------------
component Counter is
generic(
C_NUM_BITS : Integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end component Counter;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin -- VHDL_RTL
-- set the load value to zero
zeros <= (others => '0');
-- Generate a 40-bit counter from 5 8-bit counters. Register the carry-out between counters
-- to avoid timing problems.
COUNTER_GEN: for i in 0 to 4 generate
-- first 8-bit counter
FIRST: if i = 0 generate
COUNT_0_I: Counter
generic map (C_NUM_BITS => NUM_BITS)
port map ( Clk => Clk,
Rst => Rst,
Load_in => zeros,
Count_Enable => '1',
Count_Load => '0',
Count_Down => '0',
Count_out => open,
Carry_Out => co(0)
);
-- register the carry out to create the count enable out
ceo(i) <= co(i);
FDR_0_I: FDR
port map (
Q => ceo_d1(i),
C => Clk,
D => ceo(i),
R => Rst
);
end generate FIRST;
-- all other eight bit counters and the carry out register
ALL_OTHERS: if i /= 0 generate
COUNT_I: Counter
generic map (C_NUM_BITS => NUM_BITS)
port map ( Clk => Clk,
Rst => Rst,
Load_in => zeros,
Count_Enable => ceo_d1(i-1),
Count_Load => '0',
Count_Down => '0',
Count_out => open,
Carry_Out => co(i)
);
-- register the carry out AND the count enable to create the count enable out
ceo(i) <= co(i) and ceo_d1(i-1);
FDR_0_I: FDR
port map (
Q => ceo_d1(i),
C => Clk,
D => ceo(i),
R => Rst
);
end generate ALL_OTHERS;
end generate COUNTER_GEN;
-- Using the final carry out as a CE, clock a '1' to assert and hold the eval_timeout signal.
FDRE_I: FDRE
port map (
Q => eval_timeout, --[out]
C => Clk, --[in]
CE => ceo_d1(4), --[in]
D => '1', --[in]
R => Rst --[in]
);
end imp;
| bsd-3-clause | 34a08cce52082d1fda5770cb381b9735 | 0.397065 | 5.206019 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/smp_synch_core_v1_00_a/hdl/vhdl/smp_synch_core.vhd | 2 | 23,947 | ------------------------------------------------------------------------------
-- smp_synch_core.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: smp_synch_core.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Aug 4 00:06:12 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
use proc_common_v2_00_a.ipif_pkg.all;
use proc_common_v2_00_a.soft_reset;
library plbv46_slave_single_v1_00_a;
use plbv46_slave_single_v1_00_a.plbv46_slave_single;
library smp_synch_core_v1_00_a;
use smp_synch_core_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
------------------------------------------------------------------------------
entity smp_synch_core is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex5"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
end entity smp_synch_core;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of smp_synch_core is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant RST_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant RST_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & RST_BASEADDR, -- soft reset space base address
ZERO_ADDR_PAD & RST_HIGHADDR -- soft reset space high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 16;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant RST_NUM_CE : integer := 1;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => RST_NUM_CE -- number of ce for soft reset space
);
------------------------------------------
-- Ratio of bus clock to core clock (for use in dual clock systems)
-- 1 = ratio is 1:1
-- 2 = ratio is 2:1
------------------------------------------
constant IPIF_BUS2CORE_CLK_RATIO : integer := 1;
------------------------------------------
-- Width of the slave data bus (32 only)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Width of triggered reset in bus clocks
------------------------------------------
constant RESET_WIDTH : integer := 4;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant RST_CS_INDEX : integer := 1;
constant RST_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, RST_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal rst_Bus2IP_Reset : std_logic;
signal rst_IP2Bus_WrAck : std_logic;
signal rst_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_single
------------------------------------------
PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_00_a.plbv46_slave_single
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate soft_reset
------------------------------------------
SOFT_RESET_I : entity proc_common_v2_00_a.soft_reset
generic map
(
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_RESET_WIDTH => RESET_WIDTH
)
port map
(
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_WrCE => ipif_Bus2IP_WrCE(RST_CE_INDEX),
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Reset2IP_Reset => rst_Bus2IP_Reset,
Reset2Bus_WrAck => rst_IP2Bus_WrAck,
Reset2Bus_Error => rst_IP2Bus_Error,
Reset2Bus_ToutSup => open
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity smp_synch_core_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => rst_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "10" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "01" => ipif_IP2Bus_Data <= (others => '0');
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or rst_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or rst_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
end IMP;
| bsd-3-clause | d7b4b5ae58dd3cd1af4fbcba792da0c2 | 0.451414 | 4.419081 | false | false | false | false |
iocoder/graduation | hardware/vga/sequencer.vhd | 1 | 7,834 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sequencer is
Port (CLK56 : in STD_LOGIC;
CLK28 : in STD_LOGIC;
SE : in STD_LOGIC;
MODE : in STD_LOGIC;
ROW_BASE : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_ROW : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_COL : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_CTRL : in STD_LOGIC_VECTOR (15 downto 0);
PPU_HSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_VSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
X : in STD_LOGIC_VECTOR (15 downto 0);
Y : in STD_LOGIC_VECTOR (15 downto 0);
B9 : in STD_LOGIC := '0';
VRAM0Read : out STD_LOGIC := '0';
VRAM0Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1Read : out STD_LOGIC := '0';
VRAM1Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM1Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2Read : out STD_LOGIC := '0';
VRAM2Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM2Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3Read : out STD_LOGIC := '0';
VRAM3Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM3Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM4Read : out STD_LOGIC := '0';
VRAM4Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM4Data : in STD_LOGIC_VECTOR ( 8 downto 0);
SprRD : in STD_LOGIC;
SprWR : in STD_LOGIC;
SprAddr : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
PalRD : in STD_LOGIC;
PalWR : in STD_LOGIC;
PalAddr : in STD_LOGIC_VECTOR ( 4 downto 0);
PalDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
PalDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
Color : out STD_LOGIC_VECTOR ( 5 downto 0) := "000000");
end sequencer;
architecture Structural of sequencer is
component vgaseq is
Port (CLK : in STD_LOGIC;
SE : in STD_LOGIC;
ROW_BASE : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_ROW : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_COL : in STD_LOGIC_VECTOR ( 7 downto 0);
X : in STD_LOGIC_VECTOR (15 downto 0);
Y : in STD_LOGIC_VECTOR (15 downto 0);
B9 : in STD_LOGIC := '0';
VRAM0Read : out STD_LOGIC := '0';
VRAM0Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1Read : out STD_LOGIC := '0';
VRAM1Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM1Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2Read : out STD_LOGIC := '0';
VRAM2Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM2Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3Read : out STD_LOGIC := '0';
VRAM3Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM3Data : in STD_LOGIC_VECTOR ( 8 downto 0);
Color : out STD_LOGIC_VECTOR ( 3 downto 0) := "0000");
end component;
component ppuseq is
Port (CLK : in STD_LOGIC;
SE : in STD_LOGIC;
ROW_BASE : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_ROW : in STD_LOGIC_VECTOR ( 7 downto 0);
CURSOR_COL : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_CTRL : in STD_LOGIC_VECTOR (15 downto 0);
PPU_HSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
PPU_VSCR : in STD_LOGIC_VECTOR ( 7 downto 0);
X : in STD_LOGIC_VECTOR (15 downto 0);
Y : in STD_LOGIC_VECTOR (15 downto 0);
B9 : in STD_LOGIC := '0';
VRAM0Read : out STD_LOGIC := '0';
VRAM0Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1Read : out STD_LOGIC := '0';
VRAM1Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM1Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2Read : out STD_LOGIC := '0';
VRAM2Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM2Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3Read : out STD_LOGIC := '0';
VRAM3Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM3Data : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM4Read : out STD_LOGIC := '0';
VRAM4Addr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM4Data : in STD_LOGIC_VECTOR ( 8 downto 0);
SprRD : in STD_LOGIC;
SprWR : in STD_LOGIC;
SprAddr : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
PalRD : in STD_LOGIC;
PalWR : in STD_LOGIC;
PalAddr : in STD_LOGIC_VECTOR ( 4 downto 0);
PalDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
PalDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
Color : out STD_LOGIC_VECTOR ( 5 downto 0) := "000000");
end component;
signal VGA_VRAM0Read : STD_LOGIC;
signal VGA_VRAM0Addr : STD_LOGIC_VECTOR (10 downto 0);
signal VGA_VRAM1Read : STD_LOGIC;
signal VGA_VRAM1Addr : STD_LOGIC_VECTOR (10 downto 0);
signal VGA_VRAM2Read : STD_LOGIC;
signal VGA_VRAM2Addr : STD_LOGIC_VECTOR (10 downto 0);
signal VGA_VRAM3Read : STD_LOGIC;
signal VGA_VRAM3Addr : STD_LOGIC_VECTOR (10 downto 0);
signal VGA_Color : STD_LOGIC_VECTOR ( 3 downto 0);
signal PPU_VRAM0Read : STD_LOGIC;
signal PPU_VRAM0Addr : STD_LOGIC_VECTOR (10 downto 0);
signal PPU_VRAM1Read : STD_LOGIC;
signal PPU_VRAM1Addr : STD_LOGIC_VECTOR (10 downto 0);
signal PPU_VRAM2Read : STD_LOGIC;
signal PPU_VRAM2Addr : STD_LOGIC_VECTOR (10 downto 0);
signal PPU_VRAM3Read : STD_LOGIC;
signal PPU_VRAM3Addr : STD_LOGIC_VECTOR (10 downto 0);
signal PPU_Color : STD_LOGIC_VECTOR ( 5 downto 0);
begin
U1: vgaseq port map (CLK28, SE, ROW_BASE, CURSOR_ROW, CURSOR_COL, X, Y, B9,
VGA_VRAM0Read, VGA_VRAM0Addr, VRAM0Data,
VGA_VRAM1Read, VGA_VRAM1Addr, VRAM1Data,
VGA_VRAM2Read, VGA_VRAM2Addr, VRAM2Data,
VGA_VRAM3Read, VGA_VRAM3Addr, VRAM3Data,
VGA_Color);
U2: ppuseq port map (CLK28, SE, ROW_BASE, CURSOR_ROW, CURSOR_COL,
PPU_CTRL, PPU_HSCR, PPU_VSCR,
X, Y, B9,
PPU_VRAM0Read, PPU_VRAM0Addr, VRAM0Data,
PPU_VRAM1Read, PPU_VRAM1Addr, VRAM1Data,
PPU_VRAM2Read, PPU_VRAM2Addr, VRAM2Data,
PPU_VRAM3Read, PPU_VRAM3Addr, VRAM3Data,
VRAM4Read, VRAM4Addr, VRAM4Data,
SprRD, SprWR, SprAddr, SprDataIn, SprDataOut,
PalRD, PalWR, PalAddr, PalDataIn, PalDataOut,
PPU_Color);
VRAM0Read <= VGA_VRAM0Read when MODE = '0' else PPU_VRAM0Read;
VRAM0Addr <= VGA_VRAM0Addr when MODE = '0' else PPU_VRAM0Addr;
VRAM1Read <= VGA_VRAM1Read when MODE = '0' else PPU_VRAM1Read;
VRAM1Addr <= VGA_VRAM1Addr when MODE = '0' else PPU_VRAM1Addr;
VRAM2Read <= VGA_VRAM2Read when MODE = '0' else PPU_VRAM2Read;
VRAM2Addr <= VGA_VRAM2Addr when MODE = '0' else PPU_VRAM2Addr;
VRAM3Read <= VGA_VRAM3Read when MODE = '0' else PPU_VRAM3Read;
VRAM3Addr <= VGA_VRAM3Addr when MODE = '0' else PPU_VRAM3Addr;
Color <= ("00" & VGA_Color) when MODE = '0' else PPU_Color;
end Structural;
| gpl-3.0 | a60955e9fd418e7ffe05a2dcd4b65e92 | 0.561144 | 3.359348 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_sync_manager_v1_00_a/hdl/vhdl/common.vhd | 11 | 19,809 | -------------------------------------------------------------------------------------
-- Copyright (c) 2006, University of Kansas - Hybridthreads Group
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the University of Kansas nor the name of the
-- Hybridthreads Group nor the names of its contributors may be used to
-- endorse or promote products derived from this software without specific
-- prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-- ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package common is
-- Synch Manager Operations
constant SYNCH_LOCK : std_logic_vector(0 to 2) := "000";
constant SYNCH_UNLOCK : std_logic_vector(0 to 2) := "001";
constant SYNCH_TRY : std_logic_vector(0 to 2) := "010";
constant SYNCH_OWNER : std_logic_vector(0 to 2) := "011";
constant SYNCH_KIND : std_logic_vector(0 to 2) := "100";
constant SYNCH_COUNT : std_logic_vector(0 to 2) := "101";
constant SYNCH_RESULT : std_logic_vector(0 to 2) := "110";
-- Synch Manager Lock Types
constant SYNCH_FAST : std_logic_vector(0 to 1) := "00";
constant SYNCH_RECURS : std_logic_vector(0 to 1) := "01";
constant SYNCH_ERROR : std_logic_vector(0 to 1) := "10";
-- Constants for the status codes which are returned
constant SYNCH_LOCKSTA_CONTINUE : std_logic_vector(0 to 0) := "0";
constant SYNCH_LOCKSTA_BLOCK : std_logic_vector(0 to 0) := "1";
constant SYNCH_UNLOCKSTA_SUCCESS : std_logic_vector(0 to 0) := "0";
constant SYNCH_UNLOCKSTA_ERROR : std_logic_vector(0 to 0) := "1";
constant SYNCH_TRYLOCKSTA_SUCCESS : std_logic_vector(0 to 0) := "0";
constant SYNCH_TRYLOCKSTA_ERROR : std_logic_vector(0 to 0) := "1";
-- Constants used by this package
constant CMBITS : natural := 3;
constant KNBITS : natural := 2;
-- Calculate the number one for any given bit width
function one( n : in natural ) return std_logic_vector;
-- Calculate the number zero for any given bit width
function zero( n : in natural ) return std_logic_vector;
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive;
-- Calculate the 2 to the power n. This function can be used to determine
-- the maximum natural number which is representable by a given number
-- of bits.
function pow2( n : in natural ) return positive;
-- Determine if a number is exactly a power of two. This can be used
-- to check that generics are input as power of two (if that is what
-- is wanted).
function is_pow2( n : in natural ) return boolean;
-- Calculate the address used to add a thread to the thread scheduler.
function add_thread( base : in std_logic_vector;
tid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address used to store the result value from an add thread.
function add_result( base : in std_logic_vector ) return std_logic_vector;
-- Calculate a synchronization manager command
function synch_cmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector;
cmd : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_lockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_unlockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_trylockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_kindcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_countcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_ownercmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_locksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_unlocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_trylocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_kindsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_countsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
-- Calculate the address for a lock command
function synch_ownersta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector;
end package common;
package body common is
-- Calculate a synchronization manager command
function synch_cmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector;
cmd : in std_logic_vector ) return std_logic_vector is
variable addr : std_logic_vector(0 to DWID-1);
begin
addr := BASE;
addr(DWID-MBITS-2 to DWID-3) := mid;
addr(DWID-MBITS-TBITS-2 to DWID-MBITS-3) := tid;
addr(DWID-MBITS-TBITS-CMBITS-2 to DWID-MBITS-TBITS-3) := cmd;
return addr;
end function synch_cmd;
-- Calculate the address for a lock command
function synch_lockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_LOCK);
end function synch_lockcmd;
-- Extract status information for the lock operation
function synch_locksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
variable tmp : std_logic_vector(0 to 0);
begin
tmp(0) := sta(0) or sta(1);
return tmp;
end function synch_locksta;
-- Calculate the address for a lock command
function synch_unlockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_UNLOCK);
end function synch_unlockcmd;
-- Extract status information for the unlock operation
function synch_unlocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(0 to 0);
end function synch_unlocksta;
-- Calculate the address for a lock command
function synch_trylockcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_TRY);
end function synch_trylockcmd;
-- Extract status information for the unlock operation
function synch_trylocksta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(1 to 1);
end function synch_trylocksta;
-- Calculate the address for a lock command
function synch_kindcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_KIND);
end function synch_kindcmd;
-- Extract status information for the unlock operation
function synch_kindsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(DWID-2 to DWID-1);
end function synch_kindsta;
-- Calculate the address for a lock command
function synch_ownercmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_OWNER);
end function synch_ownercmd;
-- Extract status information for the unlock operation
function synch_ownersta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(DWID-TBITS to DWID-1);
end function synch_ownersta;
-- Calculate the address for a lock command
function synch_countcmd( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
tid : in std_logic_vector;
mid : in std_logic_vector ) return std_logic_vector is
begin
return synch_cmd(BASE,DWID,MBITS,TBITS,CBITS,tid,mid,SYNCH_COUNT);
end function synch_countcmd;
-- Extract status information for the unlock operation
function synch_countsta( BASE : in std_logic_vector;
DWID : in natural;
MBITS : in natural;
TBITS : in natural;
CBITS : in natural;
sta : in std_logic_vector ) return std_logic_vector is
begin
return sta(DWID-CBITS to DWID-1);
end function synch_countsta;
-- Calculate the number one for any given bit width
function one( n : in natural ) return std_logic_vector is
variable o : std_logic_vector(0 to n-1);
begin
o(0 to n-2) := (others => '0');
o(n-1) := '1';
return o;
end function one;
-- Calculate the number zero for any given bit width
function zero( n : in natural ) return std_logic_vector is
variable z : std_logic_vector(0 to n-1);
begin
z(0 to n-1) := (others => '0');
return z;
end function zero;
-- Calculate the log base 2 of some natural number. This function can be
-- used to determine the minimum number of bits needed to represent the
-- given natural number.
function log2( n : in natural ) return positive is
begin
if n <= 2 then
return 1;
else
return 1 + log2(n/2);
end if;
end function log2;
-- Calculate the 2 to the power n. This function can be used to determine
-- the maximum natural number which is representable by a given number
-- of bits.
function pow2( n : in natural ) return positive is
begin
if n = 0 then
return 1;
else
return 2 * pow2( n - 1 );
end if;
end function pow2;
-- Determine if a number is exactly a power of two. This can be used
-- to check that generics are input as power of two (if that is what
-- is wanted).
function is_pow2( n : in natural ) return boolean is
variable l : positive;
variable p : positive;
begin
if( n = 1 ) then
return true;
end if;
if( (n mod 2) = 1 or n = 0) then
return false;
end if;
return is_pow2( n / 2 );
end function is_pow2;
-- Calculate the address used to add a thread to the thread scheduler.
function add_thread( base : in std_logic_vector; tid : in std_logic_vector ) return std_logic_vector is
begin
return base(0 to base'high - tid'length - 7) &
"00100" &
tid &
base(base'high-1 to base'high);
end function add_thread;
-- Calculate the address used to store the result value from an add thread.
function add_result( base : in std_logic_vector ) return std_logic_vector is
begin
return base(0 to base'high-2) & "11";
end function add_result;
end package body common;
| bsd-3-clause | 8598805559abec165e1b8d168c9eb41b | 0.522843 | 4.773253 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/ipif_control_wr.vhd | 3 | 38,141 | -------------------------------------------------------------------------------
-- $Id: ipif_control_wr.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
--ipif_control_wr.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
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-- ** Xilinx expressly disclaims any warranty whatsoever with **
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-- ** but not limited to any warranties or representations that this **
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-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_control_wr.vhd
--
-- Description: This VHDL design file is for the Point Design of the Mauna
-- Loa Write Packet FIFO IPIF Local Bus Interface control
-- block.
--
-------------------------------------------------------------------------------
-- Structure:
--
--
--
-- ipif_control_wr.vhd
--
--
--
--
--
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe April 5, 2001 -- V1.00a
--
-- DET June 25, 2001 V1.00b
-- - eliminated redundant logic warnings during synthesis
--
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
--
-- DET Sept. 4, 2001
-- - Optimization changes and clean up
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
entity ipif_control_wr is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for disable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_INTFC_TYPE : integer range 0 to 31 := 1;
-- IPIF block protocol Type
C_VERSION_MAJOR : integer range 0 to 9 := 9;
-- Major versioning of top level design
C_VERSION_MINOR : integer range 0 to 99 := 99;
-- Minor Version of top level design
C_VERSION_REV : integer range 0 to 25 := 0;
-- Revision letter of top level design
C_FIFO_WIDTH : Integer := 32;
-- Width of FIFO data in bits
C_DP_ADDRESS_WIDTH : Integer := 9;
-- Indicates address width of RdFIFO memory
-- (= log2(fifo_depth)
C_SUPPORT_BURST : Boolean := true;
-- Indicates write burst support for the IPIF bus
C_IPIF_DBUS_WIDTH : Integer := 32
-- Width of the IPIF data bus in bits
);
port (
-- Inputs From the IPIF Bus
Bus_rst : In std_logic; -- Master Reset from the IPIF
Bus_clk : In std_logic; -- Master timing clock from the IPIF
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-- Inputs from the FIFO Interface Logic
Fifo_WrAck : In std_logic;
Vacancy : In std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
AlmostFull : In std_logic;
Full : In std_logic;
Deadlock : In std_logic;
-- Outputs to the FIFO
Fifo_wr_data : Out std_logic_vector(0 to C_FIFO_WIDTH-1);
Fifo_Reset : Out std_logic;
Fifo_WrReq : Out std_logic;
Fifo_burst_wr_xfer : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock : Out std_logic;
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end ipif_control_wr ;
-------------------------------------------------------------------------------
architecture implementation of ipif_control_wr is
--FUNCTIONS
-----------------------------------------------------------------------------
-- Function set_fwidth
--
-- This function is used to set the value of FIFO width status
-- field based on the setting of the width parameter.
-----------------------------------------------------------------------------
function set_fwidth (fifo_width : integer) return integer is
constant byte_lane_num : Integer := (fifo_width+7)/8;
Variable enc_size : Integer := 0;
begin
case byte_lane_num is
when 0|1 =>
enc_size := 1;
when 2 =>
enc_size := 2;
when 3 | 4 =>
enc_size := 3;
when 5|6|7|8 =>
enc_size := 4;
When 9|10|11|12|13|14|15|16 =>
enc_size := 5;
when others =>
enc_size := 6;
end case;
return(enc_size);
end function set_fwidth;
--TYPES
-- no types
-- CONSTANTS
-- Module Software Reset key value for write data
Constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- This requires a Hex 'A' to be written
-- to activate the S/W reset port
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- Bus Width Matching constant
Constant ENC_FIFO_WIDTH : integer := set_fwidth(C_FIFO_WIDTH);
--INTERNAL SIGNALS
signal bus_data_out : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
--signal mir_value : std_logic_vector(0 to 31);
Signal sw_reset_error : std_logic;
signal reg_vacancy : std_logic_vector(0 to C_DP_ADDRESS_WIDTH);
Signal reg_almostfull : std_logic;
Signal reg_full : std_logic;
Signal reg_deadlock : std_logic;
Signal reg_rdce1 : std_logic;
Signal reg_rdce2 : std_logic;
Signal reg_rdce3 : std_logic;
Signal reg_wrce1 : std_logic;
Signal reg_wrce2 : std_logic;
Signal reg_wrce3 : std_logic;
Signal reg_wrreq : std_logic;
Signal reg_rdreq : std_logic;
Signal read_ack : std_logic;
Signal reg_read_ack : std_logic;
Signal write_ack : std_logic;
Signal rd_access_error : std_logic;
Signal wr_access_error : std_logic;
Signal burst_wr_xfer : std_logic;
Signal read_req : std_logic;
Signal reg_read_req : std_logic;
Signal write_req : std_logic;
Signal reg_write_req : std_logic;
Signal fifo_errack_inhibit : std_logic;
Signal rd_vect : std_logic_vector(0 to 3);
Signal sig_rst_match : std_logic;
Signal sig_rst_vect : std_logic_vector(0 to 1);
Signal sig_fifo_wr_data : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-------------------------------------------------------------------------------
--------------------- start architecture logic --------------------------------
begin
-- General access detection (used to terminate reply signal to the Bus)
read_req <= (Bus2FIFO_RdCE1 or Bus2FIFO_RdCE2 or Bus2FIFO_RdCE3);
write_req <= (Bus2FIFO_WrCE1 or Bus2FIFO_WrCE2 or Bus2FIFO_WrCE3);
-- I/O assignments
FIFO2Bus_DBus <= bus_data_out;
FIFO2Bus_ToutSup <= LOGIC_LOW;
-- This output signal not currently used so
-- drive it low.
FIFO2Bus_Retry <= LOGIC_LOW;
-- This output signal not currently used so
-- drive it low.
FIFO2Bus_WrAck <= write_ack and write_req;
-- Connect the write acknowledge (drive only if a
-- request is present)
FIFO2Bus_RdAck <= read_ack and read_req;
-- Connect the read acknowledge (drive only if
-- a request is present)
FIFO2Bus_Error <= (sw_reset_error or
rd_access_error or
wr_access_error) and
(read_req or write_req);
FIFO2IRPT_DeadLock <= Deadlock;
Fifo_WrReq <= Bus2FIFO_WrCE3 and Bus_WrReq;
-- Write Request to FIFO read controller
Fifo_burst_wr_xfer <= burst_wr_xfer;
-- Burst detect signal to FIFO read controller
sig_fifo_wr_data <= Bus_DBus;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- The FIFO data bus width is smaller than the IPIF data bus width so connect
-- the smaller FIFO data to LSB position of data bus to IPIF interface and
-- set the remaining data bus bits to zeroes.
-------------------------------------------------------------------------------
BUS_BIGGER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH > C_FIFO_WIDTH) generate
CONNECT_DBUS : process (sig_fifo_wr_data)
Begin
for j in 0 to C_FIFO_WIDTH-1 loop
fifo_wr_data(j) <= sig_fifo_wr_data(C_IPIF_DBUS_WIDTH-
C_FIFO_WIDTH+j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_BIGGER_THAN_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is equal to the IPIF data bus width so connect
-- the FIFO data to IPIF data interface.
-------------------------------------------------------------------------------
BUS_EQUAL_TO_FIFO : if (C_IPIF_DBUS_WIDTH = C_FIFO_WIDTH) generate
fifo_wr_data <= sig_fifo_wr_data;
end generate BUS_EQUAL_TO_FIFO;
-------------------------------------------------------------------------------
-- The FIFO data bus width is bigger than the IPIF data bus width !!BAD!!!
-- Connect the LSBits of the FIFO data to the IPIF data bus interface,
-- Don't use (truncate) the MSBits of the FIFO data spilling over the IPIF
-- data bus width.
-------------------------------------------------------------------------------
BUS_SMALLER_THAN_FIFO : if (C_IPIF_DBUS_WIDTH < C_FIFO_WIDTH) generate
CONNECT_DBUS : process (sig_fifo_wr_data)
Begin
fifo_wr_data <= (others => '0'); --default bus state
for j in C_IPIF_DBUS_WIDTH-1 downto 0 loop
fifo_wr_data(C_FIFO_WIDTH-C_IPIF_DBUS_WIDTH+j)
<= sig_fifo_wr_data(j);
End loop;
End process; -- CONNECT_DBUS
end generate BUS_SMALLER_THAN_FIFO;
------------------------------------------------------------------------------
-- Register the input chip enables
------------------------------------------------------------------------------
REGISTER_CHIP_ENABLES : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
reg_rdce1 <= '0';
reg_rdce2 <= '0';
reg_rdce3 <= '0';
reg_wrce1 <= '0';
reg_wrce2 <= '0';
reg_wrce3 <= '0';
reg_rdreq <= '0';
reg_wrreq <= '0';
reg_read_req <= '0';
reg_write_req <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
reg_rdce1 <= Bus2FIFO_RdCE1;
reg_rdce2 <= Bus2FIFO_RdCE2;
reg_rdce3 <= Bus2FIFO_RdCE3;
reg_wrce1 <= Bus2FIFO_WrCE1;
reg_wrce2 <= Bus2FIFO_WrCE2;
reg_wrce3 <= Bus2FIFO_WrCE3;
reg_rdreq <= Bus_RdReq;
reg_read_req <= read_req;
reg_wrreq <= Bus_WrReq;
reg_write_req <= write_req;
Else
null;
End if;
End process; -- REGISTER_CHIP_ENABLES
-------------------------------------------------------------------------------
-- Detect a Burst Write Condition (used for reading the FIFO Data)
-------------------------------------------------------------------------------
BURST_DETECT : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
burst_wr_xfer <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (reg_wrreq = '1' and Bus_WrReq = '1') Then
burst_wr_xfer <= '1';
Elsif (burst_wr_xfer = '1' and Bus_WrReq = '0') Then
burst_wr_xfer <= '0';
else
burst_wr_xfer <= '0';
End if;
else
null;
End if;
End process; -- BURST_DETECT
-------------------------------------------------------------------------------
-- Assemble and latch the FIFO status register fields
-------------------------------------------------------------------------------
GET_STATUS : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
reg_vacancy <= (others => '0');
reg_deadlock <= '0';
reg_almostfull <= '0';
reg_full <= '1';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (reg_rdce2 = '1') Then -- hold last value registered during read
-- operation.
null;
else -- register new status every clock
reg_vacancy <= Vacancy ;
reg_deadlock <= Deadlock ;
reg_almostfull <= AlmostFull ;
reg_full <= Full ;
End if;
else
null; -- do nothing
End if;
End process; -- GET_STATUS
sig_rst_match <= Bus_DBus(C_IPIF_DBUS_WIDTH-4)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-3))
and Bus_DBus(C_IPIF_DBUS_WIDTH-2)
and not(Bus_DBus(C_IPIF_DBUS_WIDTH-1));
sig_rst_vect <= sig_rst_match & Bus2FIFO_WrCE1;
------------------------------------------------------------------------------
-- Generate the S/W reset as a result of an IPIF Bus write to register
-- port 1 and data on the DBus inputs matching the Reset match value.
------------------------------------------------------------------------------
GENERATE_SOFTWARE_RESET : process (Bus_rst, Bus_Clk)
Begin
If (Bus_rst = '1') Then
FIFO_Reset <= '1';
sw_reset_error <= '0';
Elsif (Bus_Clk'EVENT and Bus_Clk = '1') Then
Case sig_rst_vect Is
When "11" =>
FIFO_Reset <= '1';
sw_reset_error <= '0';
When "01" =>
FIFO_Reset <= '0';
sw_reset_error <= '1';
When others =>
FIFO_Reset <= '0';
sw_reset_error <= '0';
End case;
Else
null;
End if;
End process; -- GENERATE_SOFTWARE_RESET
-- Synthesis for MIR inclusion ------------------------------------------------
Include_MIR :if (C_MIR_ENABLE = True) generate
signal mir_value : std_logic_vector(0 to 31);
Signal mir_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
-------------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics and Constants
-- conversion to std_logic_vector required
-------------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MAJOR, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_VERSION_MINOR, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_VERSION_REV, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_BLOCK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_INTFC_TYPE, 8);
-------------------------------------------------------------------------
-- If the IPIF read data bus width is less than or equal to the MIR value
-- size (32bits), then populate the LS MIR bits that will fit. Truncate
-- those that will not fit.
-------------------------------------------------------------------------
BUS_LEQ_32 : if (C_IPIF_DBUS_WIDTH <= 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
for j in 0 to (C_IPIF_DBUS_WIDTH-1) loop
mir_bus(j) <= mir_value((32-C_IPIF_DBUS_WIDTH)+j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_LEQ_32;
-------------------------------------------------------------------------
-- If the IPIF read data bus width is greater than the MIR value size
-- (32bits), then populate the MIR bits into the LSBits of the bus
-- and zero the remaining MSBits
-------------------------------------------------------------------------
BUS_GT_32 : if (C_IPIF_DBUS_WIDTH > 32) generate
begin
BUILD_MIR_BUS : process (mir_value)
Begin
mir_bus <= (others => '0'); -- default bus values
for j in 0 to 31 loop
mir_bus((C_IPIF_DBUS_WIDTH-32)+j) <= mir_value(j);
End loop;
End process; -- BUILD_MIR_BUS
end generate BUS_GT_32;
----------------------------------------------------------------------------
-- The IPIF DBUS is larger than 32 bits in width. Place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(C_IPIF_DBUS_WIDTH-28 to C_IPIF_DBUS_WIDTH-26)
-- <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- occupancy is not scaled
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostfull;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- The IPIF DBUS is of sufficient width to contain the complete status
-- information so do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(4 to 6) <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- Set Vacancy is not scaled in this case.
status_bus(3) <= '0';
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull ;
status_bus(0) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the vacancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
-- set Encoded FIFO data width
--status_bus(4 to 6) <= CONV_STD_LOGIC_VECTOR(ENC_FIFO_WIDTH,3);
-- Set Vacancy is scaled in this case.
status_bus(3) <= '1';
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull;
status_bus(0) <= reg_full ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the three read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, mir_bus, status_bus,
rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1001" => -- Read MIR port
bus_data_out <= mir_bus;
When "1010" => -- Read Status port
bus_data_out <= status_bus;
When others => -- default to zeroes
bus_data_out <= (others => '0');
End case;
End process; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (Bus2FIFO_RdCE3 = '1') Then -- attempting a read of the FIFO
-- data through the data write
rd_access_error <= '1'; -- port. This is always an error.
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Include_MIR;
-- Synthesis for MIR occlusion ------------------------------------------------
Occlude_MIR : if (C_MIR_ENABLE = False) generate
Signal status_bus : std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
begin
----------------------------------------------------------------------------
-- If the IPIF DBUS is larger than 32 bits in width, place the 32 bit status
-- word on the 32 LSBits of the data bus.
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_BIG : if (C_IPIF_DBUS_WIDTH >= 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(C_IPIF_DBUS_WIDTH-29) <= '0' ;
-- occupancy is not scaled
status_bus(C_IPIF_DBUS_WIDTH-30) <= reg_deadlock ;
status_bus(C_IPIF_DBUS_WIDTH-31) <= reg_almostfull ;
status_bus(C_IPIF_DBUS_WIDTH-32) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_BIG;
----------------------------------------------------------------------------
-- If the IPIF DBUS is less than or equal to 32 bits wide and is of sufficient
-- width to contain the complete status informatio, then.....
-- Do not scale the vacancy value down.
-- Note status_bus bit 3 is not set, signaling a complete vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_FIT : if (C_IPIF_DBUS_WIDTH >= C_DP_ADDRESS_WIDTH+4
and C_IPIF_DBUS_WIDTH < 32) generate
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '0' ; -- occupancy is not scaled
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull ;
status_bus(0) <= reg_full ;
for j in C_DP_ADDRESS_WIDTH downto 0 loop
status_bus((C_IPIF_DBUS_WIDTH-1)-(C_DP_ADDRESS_WIDTH-j))
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_FIT;
----------------------------------------------------------------------------
-- The IPIF DBUS is too narrow to contain the complete status information so
-- scale the vacancy value down until it fits in the available space.
-- Note status_bus bit 3 is now set, signaling a scaled vacancy value.
----------------------------------------------------------------------------
BUILD_STATUS_NO_FIT : if (C_IPIF_DBUS_WIDTH < C_DP_ADDRESS_WIDTH+4) generate
constant OCC_INDEX_END : Integer := (C_IPIF_DBUS_WIDTH-4)-1;
begin
BUILD_STATUS_BUS : process (reg_deadlock, reg_almostfull, reg_full,
reg_vacancy)
Begin
status_bus <= (others => '0'); -- set default bus values
status_bus(3) <= '1' ;
-- occupancy is scaled to fit
status_bus(2) <= reg_deadlock ;
status_bus(1) <= reg_almostfull;
status_bus(0) <= reg_full ;
for j in 0 to OCC_INDEX_END loop
status_bus((C_IPIF_DBUS_WIDTH-1)-OCC_INDEX_END+j)
<= reg_vacancy(j);
End loop;
End process; -- BUILD_STATUS_BUS
end generate BUILD_STATUS_NO_FIT;
----------------------------------------------------------------------------
-- Mux the two read data sources to the IPIF Local Bus output port during
-- reads.
----------------------------------------------------------------------------
MUX_THE_OUTPUT_DATA : process (Bus2FIFO_RdCE3, Bus2FIFO_RdCE2,
Bus2FIFO_RdCE1, status_bus,
rd_vect, reg_read_req)
Begin
rd_vect <= reg_read_req & Bus2FIFO_RdCE3 &
Bus2FIFO_RdCE2 & Bus2FIFO_RdCE1;
Case rd_vect Is
When "1010" =>
bus_data_out <= status_bus;
When others =>
bus_data_out <= (others => '0');
End case;
End process; -- MUX_THE_OUTPUT_DATA
----------------------------------------------------------------------------
-- Generate the Read Error Acknowledge Reply to the Bus when
-- an attempted read access by the IPIF Local Bus is invalid
----------------------------------------------------------------------------
GEN_RD_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
rd_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_RdCE1 = '1') Then -- attempting to read the MIR but it
-- is not included
rd_access_error <= '1';
Elsif (Bus2FIFO_RdCE3 = '1') Then -- attempting a read of the FIFO
rd_access_error <= '1'; -- data through the data write
-- port. This is always an error.
Else
rd_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_RD_ERROR
end generate Occlude_MIR;
-------------------------------------------------------------------------------
-- Generate the Read Acknowledge to the Bus
-------------------------------------------------------------------------------
GEN_READ_ACK : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
reg_read_ack <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
If (Bus2FIFO_RdCE1 = '1' ) Then
reg_read_ack <= '1';
Elsif (Bus2FIFO_RdCE2 = '1' ) Then
reg_read_ack <= '1';
else
reg_read_ack <= '0';
End if;
Else
null;
End if;
End process; -- GEN_READ_ACK
read_ack <= reg_read_ack or rd_access_error;
write_ack <= reg_wrce1 or -- used for reset port write
wr_access_error or -- used for error ack on invalid
-- write ops
Fifo_WrAck ; -- The FIFO accepted the write data
-------------------------------------------------------------------------------
-- This process detects the completion of at least one valid FIFO data write
-- cycle during a burst write. An error ack is generated only if a data
-- write is initiated at the same time as the FIFO is FUll.
-------------------------------------------------------------------------------
GEN_ERRACK_INHIB : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
fifo_errack_inhibit <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1' ) Then
If (Bus2FIFO_WrCE3 = '1' and Fifo_WrAck = '1') Then
fifo_errack_inhibit <= '1';
Elsif (Bus2FIFO_WrCE3 = '0') Then
fifo_errack_inhibit <= '0';
else
null;
End if;
else
null;
End if;
End process; -- GEN_ERRACK_INHIB
-------------------------------------------------------------------------------
-- Generate the Error Acknowledge Reply to the Bus when
-- an attempted access by the IPIF Local Bus is invalid
-------------------------------------------------------------------------------
GEN_WR_ERROR : process (Bus_rst, Bus_clk)
Begin
If (Bus_rst = '1') Then
wr_access_error <= '0';
Elsif (Bus_clk'EVENT and Bus_clk = '1') Then
if (Bus2FIFO_WrCE3 = '1' and
Full = '1' and
fifo_errack_inhibit = '0') Then -- Initiating a fifo write during a
wr_access_error <= '1'; -- full condition, this is an error.
Elsif (Bus2FIFO_WrCE2 = '1') Then -- Attempting to write to the staus
-- register
wr_access_error <= '1';
Else
wr_access_error <= '0';
End if;
Else
null;
End if;
End process; -- GEN_WR_ERROR
end implementation;
| bsd-3-clause | a0356ae6dc9a665d7b1ae1b07e90960c | 0.442254 | 4.563412 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_d/hdl/vhdl/dma_sg_cmp.vhd | 3 | 22,459 | -------------------------------------------------------------------------------
-- $Id: dma_sg_cmp.vhd,v 1.6 2003/09/03 18:07:53 ostlerf Exp $
-------------------------------------------------------------------------------
-- Package with component declarations to support the DMA Scatter/Gather entity
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: dma_sg_cmp.vhd
--
-- Description: Components instantiated within dma_sg are declared here.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- dma_sg_cmp.vhds
-- dma_sg_pkg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
--
-- FLO 01/30/03
-- ^^^^^^
-- Changed the dma_sg component to correspond to a changes made to the entity
-- when fixed DMASG as a 32-bit device.
-- ~~~~~~
--
-- FLO 03/02/03
-- ^^^^^^
-- Added signal DMA2Bus_MstLoc2Loc.
-- ~~~~~~
--
-- FLO 05/15/2003
-- ^^^^^^
-- Added generics C_DMA_SHORT_BURST_REMAINDER and C_DMA_BURST_SIZE
-- to the dma_sg component.
-- ~~~~~~
-- FLO 09/03/2003
-- ^^^^^^
-- Added the ld_arith_reg2 component.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library ipif_common_v1_00_d;
use ipif_common_v1_00_d.ipif_pkg.SLV64_ARRAY_TYPE;
use ipif_common_v1_00_d.ipif_pkg.INTEGER_ARRAY_TYPE;
package dma_sg_cmp is
component dma_sg is
-- Four channel, 0123, simple sg tx rx coalesc.
generic (
C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
C_IPIF_ABUS_WIDTH : natural :=15;
C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
-- The time unit, in nanoseconds, that applies to
-- the Packet Wait Bound register. The specified value of this
-- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- simulations.
C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
: INTEGER_ARRAY_TYPE
:= ( 0, 1, 2, 3 );
-- The leftmost defined bit of the LENGTH field, assuming
-- big endian bit numbering and a LSB at bit 31.
-- If the channel is a packet channel, it is assumed that
-- the number bits defined in the LENGTH register is also
-- enough bits to hold the length of a maximum sized packet.
-- ToDo, current impl requires all channels to be the same length.
C_DMA_LENGTH_WIDTH
: INTEGER_ARRAY_TYPE
:= ( 11, 11, 11, 11 );
C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 3)
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3800",
X"0000_0000_0000_4800" );
C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 3)
: SLV64_ARRAY_TYPE
:= ( X"0000_0000_0000_0000",
X"0000_0000_0000_0000",
X"0000_0000_0000_3804",
X"0000_0000_0000_4804" );
C_INTR_COALESCE
: INTEGER_ARRAY_TYPE
:= ( 0, 0, 1, 1 );
C_DEV_BLK_ID : integer := 0;
C_DMA_BASEADDR : std_logic_vector
:= X"0000_0000_0000_0000";
C_DMA_BURST_SIZE : positive := 16; -- Must be a power of 2
C_DMA_SHORT_BURST_REMAINDER : integer := 0;
C_MA2SA_NUM_WIDTH : INTEGER := 8;
C_WFIFO_VACANCY_WIDTH : integer := 10
);
-- Two channel, 23, tx rx coalesc.
-- generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 10000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 2, 3 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1800",
-- X"0000_0000_0000_2800" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1804",
-- X"0000_0000_0000_2804" );
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 1, 1 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_BURST_SIZE : positive := 16; -- Must be a power of 2
--
-- C_USE_SHORT_BURST_FOR_REMAINDER: boolean := false;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
-- Two channel, 00, simple DMA only
--generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_BURST_SIZE : positive := 16; -- Must be a power of 2
--
-- C_USE_SHORT_BURST_FOR_REMAINDER: boolean := false;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
-- Three channel, 000, simple DMA only
--generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0, 0 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000",
-- X"0000_0000_0000_0000" );
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 0, 0, 0 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_BURST_SIZE : positive := 16; -- Must be a power of 2
--
-- C_USE_SHORT_BURST_FOR_REMAINDER: boolean := false;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
-- One channel version. (under construction)
--generic (
-- C_OPB_DWIDTH : natural := 32; -- Width of data bus (32, 64).
-- C_OPB_AWIDTH : natural := 32; -- width of Bus addr.
-- C_IPIF_ABUS_WIDTH : natural :=15;
--
-- C_CLK_PERIOD_PS : integer := 16000; --ps Period of Bus2IP_Clk.
--
-- -- The time unit, in nanoseconds, that applies to
-- -- the Packet Wait Bound register. The specified value of this
-- -- generic is 1,000,000 (1 ms), but a smaller value can be used for
-- -- simulations.
-- C_PACKET_WAIT_UNIT_NS : integer := 1000; --ns
--
-- C_DMA_CHAN_TYPE -- 0=simple, 1=sg, 2=tx, 3=rx
-- : INTEGER_ARRAY_TYPE
-- := ( 2, 3 );
--
-- -- The leftmost defined bit of the LENGTH field, assuming
-- -- big endian bit numbering and a LSB at bit 31.
-- -- If the channel is a packet channel, it is assumed that
-- -- the number bits defined in the LENGTH register is also
-- -- enough bits to hold the length of a maximum sized packet.
-- -- ToDo, current impl requires all channels to be the same length.
-- C_DMA_LENGTH_WIDTH
-- : INTEGER_ARRAY_TYPE
-- := ( 11, 11 );
--
-- C_LEN_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1800", X"0000_0000_0000_2800" );
--
-- C_STAT_FIFO_ADDR
-- : SLV64_ARRAY_TYPE (0 to 1)
-- := ( X"0000_0000_0000_1804", X"0000_0000_0000_2804" );
--
--
-- C_INTR_COALESCE
-- : INTEGER_ARRAY_TYPE
-- := ( 1, 1 );
--
-- C_DEV_BLK_ID : integer := 0;
--
-- C_DMA_BASEADDR : std_logic_vector
-- := X"0000_0000_0000_0000";
--
-- C_DMA_BURST_SIZE : positive := 16; -- Must be a power of 2
--
-- C_USE_SHORT_BURST_FOR_REMAINDER: boolean := false;
--
-- C_MA2SA_NUM_WIDTH : INTEGER := 4;
--
-- C_WFIFO_VACANCY_WIDTH : integer := 10
--);
port (
DMA2Bus_Data : out std_logic_vector(0 to 31);
DMA2Bus_Addr : out std_logic_vector(0 to C_OPB_AWIDTH-1 );
DMA2Bus_MstBE : out std_logic_vector(0 to C_OPB_DWIDTH/8 - 1);
DMA2Bus_MstWrReq : out std_logic;
DMA2Bus_MstRdReq : out std_logic;
DMA2Bus_MstNum : out std_logic_vector(
0 to C_MA2SA_NUM_WIDTH-1);
DMA2Bus_MstBurst : out std_logic;
DMA2Bus_MstBusLock : out std_logic;
DMA2Bus_MstLoc2Loc : out std_logic;
DMA2IP_Addr : out std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
DMA2Bus_WrAck : out std_logic;
DMA2Bus_RdAck : out std_logic;
DMA2Bus_Retry : out std_logic;
DMA2Bus_Error : out std_logic;
DMA2Bus_ToutSup : out std_logic;
Bus2IP_MstWrAck : in std_logic;
Bus2IP_MstRdAck : in std_logic;
Mstr_sel_ma : in std_logic;
Bus2IP_MstRetry : in std_logic;
Bus2IP_MstError : in std_logic;
Bus2IP_MstTimeOut : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to 3);
Bus2IP_WrReq : in std_logic;
Bus2IP_RdReq : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Freeze : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_IPIF_ABUS_WIDTH-3);
Bus2IP_Data : in std_logic_vector(0 to 31);
Bus2IP_Burst : in std_logic;
WFIFO2DMA_Vacancy : in std_logic_vector(0 to C_WFIFO_VACANCY_WIDTH-1);
Bus2IP_MstLastAck : in std_logic;
DMA_RdCE : in std_logic;
DMA_WrCE : in std_logic;
IP2DMA_RxStatus_Empty : in std_logic;
IP2DMA_RxLength_Empty : in std_logic;
IP2DMA_TxStatus_Empty : in std_logic;
IP2DMA_TxLength_Full : in std_logic;
IP2Bus_DMA_Req : in std_logic;
Bus2IP_DMA_Ack : out std_logic;
DMA2Intr_Intr : out std_logic_vector(0 to 1)
);
end component;
component ctrl_reg_0_to_6
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector(0 to 6);
q : out std_logic_vector(0 to 6)
);
end component;
component ctrl_reg_0_to_0
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
-- XGR_E33 d : in std_logic_vector(0 to 0);
-- XGR_E33 q : out std_logic_vector(0 to 0)
d : in std_logic;
q : out std_logic
);
end component;
component SRL_FIFO
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end component;
component ld_arith_reg
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset to left (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset to left of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end component;
component ld_arith_reg2
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end component;
component burst_size_calc is
generic (
C_LENGTH_WIDTH : positive := 11;
C_MSTNUM_WIDTH : positive := 5;
C_DMA_BURST_SIZE : positive := 16;
C_BYTES_PER_SINGLE_TRANSFER : positive := 4;
C_DMA_SHORT_BURST_REMAINDER : integer := 0
);
port (
Bus2IP_Clk : in std_logic;
LENGTH_cco : in std_logic_vector(0 to C_LENGTH_WIDTH-1);
PLENGTH_cco : in std_logic_vector(0 to C_LENGTH_WIDTH-1);
Rx_cco : in std_logic;
MstNum : out std_logic_vector(0 to C_MSTNUM_WIDTH-1)
);
end component burst_size_calc;
end package;
| bsd-3-clause | a227d86bf365ed048a351c59120e4e25 | 0.453048 | 3.730731 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_wbs.vhd | 1 | 16,034 | --------------------------------------------------------------------------------
-- Title : Wishbone Slave Interface
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_wbs.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 13/01/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- The receives wishbone read/write requests either to internal registers or to
-- VME space. Depending on the signal wbs_tga, the corresponding space will be
-- accessed by forwarding the access to vme_master/wbs_du/wbs_au. The module
-- vme_master is connected via handshake signals and performs the access to the
-- vme space depending on the tga settings.
--
-- +-Module Name-----------------+----------vme_acc_type-------------+-----size-+
-- +-----------------------------+----tga-dma------+---tga-pci-------+----------+
-- +-----------------------------+ M D R S B D A | M D R S B D A +----------+
-- |16z002-01 VME | | x 0 1 x x xx xx | 800000 |
-- |16z002-01 VME IACK | | x 0 1 x x xx 11 | 10 |
-- |16z002-01 VME A16D16 | m 1 0 0 0 00 10 | x 0 0 0 0 00 10 | 10000 |
-- |16z002-01 VME A16D32 | m 1 0 0 0 01 10 | x 0 0 0 0 01 10 | 10000 |
-- |16z002-01 VME A24D16 | m 1 0 0 x 00 00 | x 0 0 0 0 00 00 | 1000000 |
-- |16z002-01 VME A24D32 | m 1 0 0 x 01 00 | x 0 0 0 0 01 00 | 1000000 |
-- |16z002-01 VME A24D64 | m 1 0 0 x 11 00 | | 1000000 |
-- |16z002-01 VME A32D32 | m 1 0 0 x 01 01 | x 0 0 0 0 01 01 | 20000000 |
-- |16z002-01 VME CR/CSR | | x 0 0 0 0 10 00 | 1000000 |
-- |16z002-01 VME A32D64 | m 1 0 0 x 11 01 | | |
-- |16z002-01 VME A16D16 swapped | | x 0 0 1 0 00 10 | 10000 |
-- |16z002-01 VME A16D32 swapped | | x 0 0 1 0 01 10 | 10000 |
-- |16z002-01 VME A24D16 swapped | m 1 0 1 x 00 00 | x 0 0 1 0 00 00 | 1000000 |
-- |16z002-01 VME A24D32 swapped | m 1 0 1 x 01 00 | x 0 0 1 0 01 00 | 1000000 |
-- |16z002-01 VME A32D32 swapped | m 1 0 1 x 01 01 | x 0 0 1 0 01 01 | 20000000 |
-- |16z002-01 VME A32D64 swapped | m 1 0 1 x 11 01 | | |
-- +-----------------------------+-----------------+-----------------+----------+
-- D - DMA Access
-- R - Register Access
-- S - Swapped Access
-- B - Burst Access
-- D - Data Width (00=D16, 01=D32, 11=D64, 10=CR/CSR)
-- A - Address Width (10=A16, 00=A24, 01=A32, 11=IACK)
-- M - Address Space (0=non-privileged 1=supervisory data)
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- wbb2vme
-- vme_ctrl
-- vme_wbs
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- Revision 1.5 2017 07:00:00 mmiehling
-- changed vme_acc_type/tga setting for CR/CSR and D32 to be compliant to DMA configuration bits
--
-- Revision 1.4 2013/09/12 08:45:21 mmiehling
-- added bit 8 of tga for address modifier extension (supervisory, non-privileged data/program)
--
-- Revision 1.2 2012/08/27 12:57:02 MMiehling
-- wbb compliant: activate wbs_ack in case of vme buserror additional to wbs_err signal in order not to block the pci bus
--
-- Revision 1.1 2012/03/29 10:14:28 MMiehling
-- Initial Revision
--
-- Revision 1.8 2006/05/18 14:28:54 MMiehling
-- read and write accesses after a bus-error are wrong => bugfix
--
-- Revision 1.7 2004/11/02 11:29:42 mmiehling
-- changed dma-type signaling to tga
--
-- Revision 1.6 2004/07/27 17:15:28 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.5 2003/12/01 10:03:29 MMiehling
-- changed all
--
-- Revision 1.4 2003/06/24 13:46:49 MMiehling
-- removed burst; changed comments
--
-- Revision 1.3 2003/06/13 10:06:18 MMiehling
-- improved timing
--
-- Revision 1.2 2003/04/02 16:11:27 MMiehling
-- verbessertes max. Frequenz
--
-- Revision 1.1 2003/04/01 13:04:28 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_wbs IS
PORT (
clk : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
-- wbs
wbs_stb_i : IN std_logic;
wbs_ack_o : OUT std_logic;
wbs_err_o : OUT std_logic;
wbs_we_i : IN std_logic;
wbs_cyc_i : IN std_logic;
wbs_adr_i : IN std_logic_vector(31 DOWNTO 0);
wbs_sel_i : IN std_logic_vector(3 DOWNTO 0);
wbs_sel_int : OUT std_logic_vector(3 DOWNTO 0);
wbs_tga_i : IN std_logic_vector(8 DOWNTO 0);
loc_write_flag : OUT std_logic; -- write flag for register
ma_en_vme_data_out_reg : OUT std_logic; -- for normal d32 or d64 low
ma_en_vme_data_out_reg_high: OUT std_logic; -- for d64 high
set_berr : IN std_logic;
wb_dma_acc : OUT std_logic; -- indicates dma_access
mensb_req : OUT std_logic; -- request line for reg access
mensb_active : IN std_logic; -- acknoledge line
vme_acc_type : OUT std_logic_vector(8 DOWNTO 0); -- signal indicates the type of VME access
run_mstr : OUT std_logic; -- starts vme master
mstr_ack : IN std_logic; -- this pulse indicates the end of Master transaction
mstr_busy : IN std_logic; -- if master is busy => 1
burst : OUT std_logic; -- indicates a burst transfer from dma to vme
sel_loc_data_out : OUT std_logic_vector(1 DOWNTO 0) -- mux select signal for 0=reg, 1=vme data_out
);
END vme_wbs;
ARCHITECTURE vme_wbs_arch OF vme_wbs IS
TYPE mensb_states IS (mensb_idle, mensb_write_regs, mensb_read_regs, mensb_read_regs2, mensb_read_regs_perf, mensb_vme_req, mensb_vme, mensb_vme_d64, mensb_vme_end);
SIGNAL mensb_state : mensb_states;
SIGNAL vme_acc_type_l : std_logic_vector(8 DOWNTO 0);
SIGNAL vme_acc_type_q : std_logic_vector(8 DOWNTO 0);
SIGNAL wbs_ack_o_int : std_logic;
BEGIN
vme_acc_type <= vme_acc_type_q;
wbs_ack_o <= wbs_ack_o_int;
wbs_sel_int <= wbs_sel_i;
wb_dma_acc <= wbs_tga_i(7) AND wbs_cyc_i;
vme_acc_type_l <= wbs_tga_i WHEN wbs_cyc_i = '1' ELSE (OTHERS => '0');
-- vme_acc_type_l <= wbs_tga_i(7 DOWNTO 6) & '1' & wbs_tga_i(4 DOWNTO 0) WHEN wbs_cyc_i = '1' ELSE (OTHERS => '0');
regs : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
vme_acc_type_q <= (OTHERS => '0');
sel_loc_data_out(0) <= '1';
burst <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
vme_acc_type_q <= vme_acc_type_l;
sel_loc_data_out(0) <= NOT vme_acc_type_l(6);
IF wbs_cyc_i = '1' AND wbs_tga_i(4) = '1' THEN
burst <= '1'; -- set if burst on vme is requested
ELSE
burst <= '0';
END IF;
END IF;
END PROCESS regs;
mensb_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
mensb_state <= mensb_idle;
loc_write_flag <= '0';
run_mstr <= '0';
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
sel_loc_data_out(1) <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE mensb_state IS
WHEN mensb_idle =>
sel_loc_data_out(1) <= '0';
IF wbs_stb_i = '1' AND vme_acc_type_l(6) = '1' AND wbs_we_i = '1' AND mensb_active = '1' THEN
wbs_ack_o_int <= '1';
wbs_err_o <= '0';
run_mstr <= '0';
loc_write_flag <= '1';
mensb_state <= mensb_vme_end;
ELSIF wbs_stb_i = '1' AND vme_acc_type_l(6) = '1' AND wbs_we_i = '0' AND mensb_active = '1' THEN
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
run_mstr <= '0';
loc_write_flag <= '0';
mensb_state <= mensb_read_regs;
ELSIF wbs_stb_i = '1' AND vme_acc_type_q(6) = '0' AND mstr_busy = '0' THEN -- general vme access
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
run_mstr <= '1';
loc_write_flag <= '0';
mensb_state <= mensb_vme_req;
ELSIF wbs_stb_i = '1' AND vme_acc_type_q(6) = '0' AND mstr_busy = '1' THEN -- rmw or burst vme access
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
run_mstr <= '1';
loc_write_flag <= '0';
mensb_state <= mensb_vme;
ELSE
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
run_mstr <= '0';
loc_write_flag <= '0';
mensb_state <= mensb_idle;
END IF;
WHEN mensb_read_regs =>
sel_loc_data_out(1) <= '0';
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
run_mstr <= '0';
loc_write_flag <= '0';
mensb_state <= mensb_read_regs2;
WHEN mensb_read_regs2 =>
sel_loc_data_out(1) <= '0';
wbs_ack_o_int <= '1';
wbs_err_o <= '0';
run_mstr <= '0';
loc_write_flag <= '0';
mensb_state <= mensb_vme_end;
WHEN mensb_vme_req => -- wait until master has got internal register control, then latch data
sel_loc_data_out(1) <= '0';
run_mstr <= '0';
loc_write_flag <= '0';
IF mstr_busy = '1' AND vme_acc_type_l(3 DOWNTO 2) = "11" AND wbs_we_i = '1' THEN
mensb_state <= mensb_vme;
wbs_ack_o_int <= '1'; -- acknoledge low d64 write
wbs_err_o <= '0';
ELSIF mstr_busy = '1' THEN
mensb_state <= mensb_vme;
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
ELSE
mensb_state <= mensb_vme_req;
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
END IF;
WHEN mensb_vme => -- vme-mstr is working, wait for mstr_ack
sel_loc_data_out(1) <= '0';
run_mstr <= '0';
loc_write_flag <= '0';
IF set_berr = '1' THEN
mensb_state <= mensb_vme_end;
wbs_ack_o_int <= '1'; -- also ack for termination of wbb access
wbs_err_o <= '1'; -- error
ELSIF mstr_ack = '1' AND vme_acc_type_l(3 DOWNTO 2) = "11" AND wbs_we_i = '0' THEN
mensb_state <= mensb_vme_d64;
wbs_ack_o_int <= '1';
wbs_err_o <= '0';
ELSIF mstr_ack = '1' THEN
mensb_state <= mensb_vme_end;
wbs_ack_o_int <= '1';
wbs_err_o <= '0';
ELSE
mensb_state <= mensb_vme;
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
END IF;
WHEN mensb_vme_d64 =>
sel_loc_data_out(1) <= '1';
run_mstr <= '0';
loc_write_flag <= '0';
IF wbs_stb_i = '1' AND wbs_ack_o_int = '0' THEN
wbs_ack_o_int <= '1';
wbs_err_o <= '0';
mensb_state <= mensb_vme_end;
ELSE
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
mensb_state <= mensb_vme_d64;
END IF;
WHEN mensb_vme_end => -- wait on end of this wb-cycle
sel_loc_data_out(1) <= '0';
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
run_mstr <= '0';
loc_write_flag <= '0';
mensb_state <= mensb_idle;
WHEN OTHERS =>
sel_loc_data_out(1) <= '0';
wbs_ack_o_int <= '0';
wbs_err_o <= '0';
run_mstr <= '0';
loc_write_flag <= '0';
mensb_state <= mensb_idle;
END CASE;
END IF;
END PROCESS mensb_fsm;
mensb_out : PROCESS (mensb_state, mensb_active, wbs_stb_i, vme_acc_type_q, mstr_busy, set_berr)
BEGIN
CASE mensb_state IS
WHEN mensb_idle =>
ma_en_vme_data_out_reg_high <= '0';
IF wbs_stb_i = '1' AND vme_acc_type_q(6) = '1' AND mensb_active = '0' THEN -- register access
mensb_req <= '1';
ma_en_vme_data_out_reg <= '0';
ELSIF wbs_stb_i = '1' AND vme_acc_type_q(6) = '0' AND mstr_busy = '1' THEN -- rmw vme access
mensb_req <= '0';
ma_en_vme_data_out_reg <= '1';
ELSE
mensb_req <= '0';
ma_en_vme_data_out_reg <= '0';
END IF;
WHEN mensb_read_regs =>
mensb_req <= '1';
ma_en_vme_data_out_reg <= '0';
ma_en_vme_data_out_reg_high <= '0';
WHEN mensb_read_regs2 =>
mensb_req <= '1';
ma_en_vme_data_out_reg <= '0';
ma_en_vme_data_out_reg_high <= '0';
WHEN mensb_vme_req =>
mensb_req <= '0';
ma_en_vme_data_out_reg_high <= '0';
IF mstr_busy = '1' OR set_berr = '1' THEN
ma_en_vme_data_out_reg <= '1';
ELSE
ma_en_vme_data_out_reg <= '0';
END IF;
WHEN mensb_vme =>
mensb_req <= '0';
ma_en_vme_data_out_reg <= '0';
ma_en_vme_data_out_reg_high <= '1';
WHEN mensb_vme_d64 =>
mensb_req <= '0';
ma_en_vme_data_out_reg <= '0';
ma_en_vme_data_out_reg_high <= '1';
WHEN mensb_vme_end =>
mensb_req <= '0';
ma_en_vme_data_out_reg <= '0';
ma_en_vme_data_out_reg_high <= '0';
WHEN OTHERS =>
mensb_req <= '0';
ma_en_vme_data_out_reg <= '0';
ma_en_vme_data_out_reg_high <= '0';
END CASE;
END PROCESS mensb_out;
END vme_wbs_arch;
| gpl-3.0 | 9af24264f49fe9e85e4d5fd62b1b51b7 | 0.450355 | 3.559156 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hwti_common_v1_00_a/hdl/vhdl/command.vhd | 2 | 14,869 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library hwti_common_v1_00_a;
use hwti_common_v1_00_a.common.all;
entity command is
generic
(
MTX_BITS : natural := 6;
TID_BITS : natural := 8;
CMD_BITS : natural := 3;
MTX_BASE : std_logic_vector := x"75000000";
CDV_BASE : std_logic_vector := x"74000000";
SCH_BASE : std_logic_vector := x"61000000";
MNG_BASE : std_logic_vector := x"60000000";
C_AWIDTH : integer := 32;
C_DWIDTH : integer := 64
);
port
(
clk : in std_logic;
rst : in std_logic;
tid : in std_logic_vector(0 to TID_BITS-1);
arg : in std_logic_vector(0 to 31);
opcode_read : out std_logic;
opcode_data : in std_logic_vector(0 to 63);
opcode_control : in std_logic;
opcode_exists : in std_logic;
result_write : out std_logic;
result_data : out std_logic_vector(0 to 63);
result_control : out std_logic;
result_full : in std_logic;
memrd : in std_logic;
memwr : in std_logic;
memrdack : out std_logic;
memwrack : out std_logic;
command : in std_logic_vector(0 to 3);
status : in std_logic_vector(0 to 7);
setsta : out std_logic;
outsta : out std_logic_vector(0 to 31);
setres : out std_logic;
outres : out std_logic_vector(0 to 31);
rd : out std_logic;
wr : out std_logic;
addr : out std_logic_vector(0 to C_AWIDTH-1);
data : out std_logic_vector(0 to C_DWIDTH-1);
bytes : out std_logic_vector(0 to 23);
ack : in std_logic;
last : in std_logic;
err : in std_logic;
results : in std_logic_vector(0 to C_DWIDTH-1)
);
end entity;
architecture behavioral of command is
type command_state is
(
START,
WAKEUP,
IDLE,
READ,
SEND,
WRITE,
RECV,
HOLD,
BLOCKED
);
alias opdev : std_logic_vector(0 to 3) is opcode_data(0 to 3);
alias opcmd : std_logic_vector(0 to 3) is opcode_data(4 to 7);
alias oparg : std_logic_vector(0 to 23) is opcode_data(8 to 31);
alias operr : std_logic is result_control;
alias opres : std_logic_vector(0 to 31) is result_data(32 to 63);
alias memsize : std_logic_vector(0 to 23) is opcode_data(8 to 31);
alias memaddr : std_logic_vector(0 to 31) is opcode_data(32 to 63);
alias osta : std_logic_vector(0 to 7) is outsta(24 to 31);
alias ores : std_logic_vector(0 to 31) is outres(0 to 31);
alias waketid : std_logic_vector(0 to 7) is result_data(24 to 31);
alias wakearg : std_logic_vector(0 to 31) is result_data(32 to 63);
signal cmd_cs : command_state;
signal cmd_ns : command_state;
--signal addr_cv : std_logic_vector(0 to C_AWIDTH-1);
--signal addr_nv : std_logic_vector(0 to C_AWIDTH-1);
--signal data_cv : std_logic_vector(0 to C_DWIDTH-1);
--signal data_nv : std_logic_vector(0 to C_DWIDTH-1);
--signal send_cv : std_logic_vector(0 to C_DWIDTH-1);
--signal send_nv : std_logic_vector(0 to C_DWIDTH-1);
--signal recv_cv : std_logic_vector(0 to C_DWIDTH-1);
--signal recv_nv : std_logic_vector(0 to C_DWIDTH-1);
--signal byte_cv : std_logic_vector(0 to 23);
--signal byte_nv : std_logic_vector(0 to 23);
--signal rd_cv : std_logic;
--signal rd_nv : std_logic;
--signal wr_cv : std_logic;
--signal wr_nv : std_logic;
signal last_nv : std_logic;
signal last_cv : std_logic;
--alias send_cv : std_logic_vector(0 to 63) is data_cv;
--alias send_nv : std_logic_vector(0 to 63) is data_nv;
--alias recv_cv : std_logic_vector(0 to 63) is data_cv;
--alias recv_nv : std_logic_vector(0 to 63) is data_nv;
alias opknd : std_logic_vector(0 to 1) is opcode_data(32-MTX_BITS-2 to 32-MTX_BITS-1);
--alias data_knd : std_logic_vector(0 to 1) is data_nv(C_DWIDTH-2 to C_DWIDTH-1);
begin
--rd <= rd_cv;
--wr <= wr_cv;
--addr <= addr_cv;
--data <= data_cv;
--bytes <= byte_cv;
--outsta(0 to 55) <= (others => '0');
--outres(0 to 31) <= (others => '0');
outsta(0 to 23) <= (others => '0');
update : process(clk,rst,cmd_ns) is
begin
if( rising_edge(clk) ) then
if( rst = '1' ) then
cmd_cs <= START;
--addr_cv <= (others => '0');
--data_cv <= (others => '0');
--byte_cv <= (others => '0');
last_cv <= '0';
--send_cv <= (others => '0');
--recv_cv <= (others => '0');
--rd_cv <= '0';
--wr_cv <= '0';
else
cmd_cs <= cmd_ns;
--addr_cv <= addr_nv;
--data_cv <= data_nv;
--byte_cv <= byte_nv;
last_cv <= last_nv;
--send_cv <= send_nv;
--recv_cv <= recv_nv;
--rd_cv <= rd_nv;
--wr_cv <= wr_nv;
end if;
end if;
end process;
controller : process(results,cmd_cs,opdev,opcmd,
ack,command,opcode_exists, opcode_data, tid,
oparg, result_full, arg,
last,memwr,last_cv,memrd) is
function mutex_cmd( tid : in std_logic_vector;
arg : in std_logic_vector;
cmd : in std_logic_vector )
return std_logic_vector is
constant AW : integer := C_AWIDTH;
constant MB : integer := MTX_BITS;
constant TB : integer := TID_BITS;
constant CB : integer := CMD_BITS;
variable addr : std_logic_vector(0 to AW-1);
begin
addr := MTX_BASE;
addr(AW-MB-2 to AW-3) := arg(24-MB to 23);
addr(AW-MB-TB-2 to AW-MB-3) := tid;
addr(AW-MB-TB-CB-3 to AW-MB-TB-3) := cmd;
return addr;
end function;
function condv_cmd( tid : in std_logic_vector;
arg : in std_logic_vector;
cmd : in std_logic_vector )
return std_logic_vector is
constant AW : integer := C_AWIDTH;
constant MB : integer := MTX_BITS;
constant TB : integer := TID_BITS;
constant CB : integer := CMD_BITS;
variable addr : std_logic_vector(0 to AW-1);
begin
addr := CDV_BASE;
addr(AW-MB-2 to AW-3) := arg(24-MB to 23);
addr(AW-MB-TB-2 to AW-MB-3) := tid;
addr(AW-MB-TB-CB-4 to AW-MB-TB-4) := cmd;
return addr;
end function;
function manag_cmd( tid : in std_logic_vector;
arg : in std_logic_vector;
cmd : in std_logic_vector )
return std_logic_vector is
constant AW : integer := C_AWIDTH;
constant MB : integer := MTX_BITS;
constant TB : integer := TID_BITS;
constant CB : integer := CMD_BITS;
variable addr : std_logic_vector(0 to AW-1);
begin
addr := MNG_BASE;
addr(AW-TB-2 to AW-3) := tid;
addr(AW-TB-CB-3 to AW-TB-3) := cmd;
return addr;
end function;
begin
result_data <= (others => '0');
result_control <= '0';
result_write <= '0';
opcode_read <= '0';
data <= (others => '0');
last_nv <= '0';
--addr_nv <= (others => '0');
--data_nv <= (others => '0');
--send_nv <= (others => '0');
--recv_nv <= (others => '0');
--byte_nv <= (others => '0');
cmd_ns <= cmd_cs;
memrdack <= '0';
memwrack <= '0';
--rd_nv <= '0';
--wr_nv <= '0';
setsta <= '0';
setres <= '0';
osta <= (others => '0');
ores <= (others => '0');
rd <= '0';
wr <= '0';
addr <= (others => '0');
bytes <= (others => '0');
case cmd_cs is
when START =>
if( command = COMMAND_RUN ) then
setsta <= '1';
osta <= STATUS_RUNNING;
cmd_ns <= WAKEUP;
end if;
when WAKEUP =>
if( result_full = '0' ) then
result_write <= '1';
result_control <= '1';
cmd_ns <= IDLE;
waketid <= tid;
wakearg <= arg;
end if;
when IDLE =>
if( opcode_exists = '1' and result_full = '0' ) then
case opdev is
when x"0" =>
if( opcmd = x"6" ) then
wr <= '1';
bytes <= x"000004";
addr <= mutex_cmd(tid,oparg,x"4");
data <= x"0000000" & "00" & opknd;
cmd_ns <= HOLD;
else
rd <= '1';
bytes <= x"000004";
addr <= mutex_cmd(tid,oparg,opcmd);
cmd_ns <= HOLD;
end if;
when x"1" =>
rd <= '1';
bytes <= x"000004";
addr <= condv_cmd(tid,oparg,opcmd);
cmd_ns <= HOLD;
when x"2" =>
rd <= '1';
bytes <= x"000004";
cmd_ns <= HOLD;
if( opcmd = x"7" or opcmd = x"2") then
addr <= manag_cmd(tid,oparg,opcmd);
else
addr <= manag_cmd(oparg(16 to 23),oparg,opcmd);
end if;
when x"3" =>
addr <= memaddr;
bytes <= memsize;
cmd_ns <= HOLD;
if( opcmd = x"0" ) then
rd <= '1';
cmd_ns <= READ;
else
wr <= '1';
cmd_ns <= RECV;
end if;
when others =>
result_control <= '1';
result_write <= '1';
end case;
end if;
when READ =>
result_data <= results;
if( last = '1' ) then
opcode_read <= '1';
cmd_ns <= IDLE;
elsif( memwr = '1' ) then
if( result_full = '0' ) then
memwrack <= '1';
result_write <= '1';
else
cmd_ns <= SEND;
end if;
end if;
when SEND =>
last_nv <= last_cv;
if( result_full = '0' ) then
memwrack <= '1';
result_write <= '1';
result_data <= results;
if( last_cv = '1' ) then
cmd_ns <= IDLE;
else
cmd_ns <= READ;
end if;
end if;
when WRITE =>
if( last = '1' ) then
cmd_ns <= IDLE;
elsif( memrd = '1' ) then
if( opcode_exists = '1' ) then
opcode_read <= '1';
memrdack <= '1';
else
cmd_ns <= RECV;
end if;
end if;
when RECV =>
if( opcode_exists = '1' ) then
opcode_read <= '1';
memrdack <= '1';
cmd_ns <= WRITE;
end if;
when HOLD =>
memwrack <= memrd;
memrdack <= memwr;
data <= x"000000000000000" & "00" & opknd;
if( ack = '1' ) then
opcode_read <= '1';
case opdev is
when x"0" =>
if( results(1) = '1' and opcmd /= x"2" ) then
setsta <= '1';
osta <= STATUS_BLOCKED;
cmd_ns <= BLOCKED;
else
result_write <= '1';
cmd_ns <= IDLE;
end if;
when x"1" =>
if( results(C_DWIDTH-4 to C_DWIDTH-1) /= x"E" ) then
if( opcmd = x"2" ) then
setsta <= '1';
osta <= STATUS_BLOCKED;
cmd_ns <= BLOCKED;
else
result_write <= '1';
cmd_ns <= IDLE;
end if;
end if;
when x"2" =>
if( results(C_DWIDTH-4 to C_DWIDTH-1) = "0011" ) then
setsta <= '1';
osta <= STATUS_BLOCKED;
cmd_ns <= BLOCKED;
elsif( opcmd = x"7" ) then
setsta <= '1';
osta <= STATUS_EXITED;
setres <= '1';
ores <= opcode_data(32 to 63);
cmd_ns <= START;
else
result_write <= '1';
cmd_ns <= IDLE;
end if;
when others =>
result_write <= '1';
cmd_ns <= IDLE;
end case;
end if;
when BLOCKED =>
if( command = COMMAND_RUN ) then
result_write <= '1';
setsta <= '1';
osta <= STATUS_RUNNING;
cmd_ns <= IDLE;
end if;
end case;
end process controller;
end architecture;
| bsd-3-clause | e1ae47a97b6f264b9f55154ec3b1e2cf | 0.395454 | 3.951369 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/interrupt_wb.vhd | 1 | 5,427 | --------------------------------------------------------------------------------
-- Title : Module for interrupt generation, synchonized to wb_clk
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : interrupt_wb.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 15.03.2011
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- This module will generate both INTA and MSI messages. It will start in INTA
-- mode and then determine if it is allowed to send MSI interrupts by reading
-- the config space. If MSI are allowed, the corresponding number of allocated
-- requests will be shown.
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- interrupt_core
-- * interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity interrupt_wb is
port(
wb_clk : in std_logic;
wb_rst : in std_logic;
-- interrupt_core
inter_ack : in std_logic;
num_allowed : in std_logic_vector(5 downto 0);
wb_pwr_en : out std_logic;
wb_num_int : out std_logic_vector(4 downto 0);
wb_inter : out std_logic;
ack_ok : out std_logic;
-- Wishbone
wb_int : in std_logic;
wb_pwr_enable : in std_logic; -- =1 if wb_int_num should be for power management, else
-- for normal interrupt
wb_int_num : in std_logic_vector(4 downto 0);
wb_int_ack : out std_logic;
wb_int_num_allowed : out std_logic_vector(5 downto 0) -- =0 if MSI not allowed, else: nbr. of allocated signals
);
end entity interrupt_wb;
-- ****************************************************************************
architecture interrupt_wb_arch of interrupt_wb is
-- internal signals -----------------------------------------------------------
signal inter_ack_qqq : std_logic;
-- registers for synchronization:
signal inter_ack_q : std_logic;
signal inter_ack_qq : std_logic;
signal num_allowed_q : std_logic_vector(5 downto 0);
signal num_allowed_qq : std_logic_vector(5 downto 0);
-------------------------------------------------------------------------------
begin
set_val : process(wb_rst,wb_clk)
begin
if(wb_rst = '1') then
inter_ack_q <= '0';
inter_ack_qq <= '0';
num_allowed_q <= (others => '0');
num_allowed_qq <= (others => '0');
wb_pwr_en <= '0';
wb_num_int <= (others => '0');
wb_inter <= '0';
wb_int_ack <= '0';
wb_int_num_allowed <= (others => '0');
ack_ok <= '0';
inter_ack_qqq <= '0';
elsif(wb_clk'event and wb_clk = '1') then
-- register all inputs that need to be registered on rising edge of wb_clk
inter_ack_q <= inter_ack;
inter_ack_qq <= inter_ack_q;
inter_ack_qqq <= inter_ack_qq;
num_allowed_q <= num_allowed;
num_allowed_qq <= num_allowed_q;
wb_pwr_en <= wb_pwr_enable;
wb_num_int <= wb_int_num;
wb_inter <= wb_int;
wb_int_num_allowed <= num_allowed_qq;
ack_ok <= inter_ack_qq;
-- assert interrupt acknowledge when rising_edge(inter_ack_qq) occured
if(inter_ack_qq = '1' and inter_ack_qqq = '0') then
wb_int_ack <= '1';
else
wb_int_ack <= '0';
end if;
end if;
end process set_val;
-------------------------------------------------------------------------------
end architecture interrupt_wb_arch;
| gpl-3.0 | 458276e1ef244b12cccd932ad15a767e | 0.457159 | 4.327751 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plb_scheduler_v1_00_a/hdl/vhdl/user_logic.vhd | 10 | 89,379 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 6 14:20:46 2009 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.srl_fifo_f;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_MST_AWIDTH -- Master interface address bus width
-- C_MST_DWIDTH -- Master interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_MstRd_Req -- IP to Bus master read request
-- IP2Bus_MstWr_Req -- IP to Bus master write request
-- IP2Bus_Mst_Addr -- IP to Bus master address bus
-- IP2Bus_Mst_BE -- IP to Bus master byte enables
-- IP2Bus_Mst_Lock -- IP to Bus master lock
-- IP2Bus_Mst_Reset -- IP to Bus master reset
-- Bus2IP_Mst_CmdAck -- Bus to IP master command acknowledgement
-- Bus2IP_Mst_Cmplt -- Bus to IP master transfer completion
-- Bus2IP_Mst_Error -- Bus to IP master error response
-- Bus2IP_Mst_Rearbitrate -- Bus to IP master re-arbitrate
-- Bus2IP_Mst_Cmd_Timeout -- Bus to IP master command timeout
-- Bus2IP_MstRd_d -- Bus to IP master read data bus
-- Bus2IP_MstRd_src_rdy_n -- Bus to IP master read source ready
-- IP2Bus_MstWr_d -- IP to Bus master write data bus
-- Bus2IP_MstWr_dst_rdy_n -- Bus to IP master write destination ready
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_MST_AWIDTH : integer := 32;
C_MST_DWIDTH : integer := 32;
C_NUM_REG : integer := 5
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
Soft_Reset : in std_logic;
Reset_Done : out std_logic;
Soft_Stop : in std_logic;
SWTM_DOB : in std_logic_vector(0 to 31);
SWTM_ADDRB : out std_logic_vector(0 to 8);
SWTM_DIB : out std_logic_vector(0 to 31);
SWTM_ENB : out std_logic;
SWTM_WEB : out std_logic;
TM2SCH_current_cpu_tid : in std_logic_vector(0 to 7);
TM2SCH_opcode : in std_logic_vector(0 to 5);
TM2SCH_data : in std_logic_vector(0 to 7);
TM2SCH_request : in std_logic;
SCH2TM_busy : out std_logic;
SCH2TM_data : out std_logic_vector(0 to 7);
SCH2TM_next_cpu_tid : out std_logic_vector(0 to 7);
SCH2TM_next_tid_valid : out std_logic;
Preemption_Interrupt : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_MstRd_Req : out std_logic;
IP2Bus_MstWr_Req : out std_logic;
IP2Bus_Mst_Addr : out std_logic_vector(0 to C_MST_AWIDTH-1);
IP2Bus_Mst_BE : out std_logic_vector(0 to C_MST_DWIDTH/8-1);
IP2Bus_Mst_Lock : out std_logic;
IP2Bus_Mst_Reset : out std_logic;
Bus2IP_Mst_CmdAck : in std_logic;
Bus2IP_Mst_Cmplt : in std_logic;
Bus2IP_Mst_Error : in std_logic;
Bus2IP_Mst_Rearbitrate : in std_logic;
Bus2IP_Mst_Cmd_Timeout : in std_logic;
Bus2IP_MstRd_d : in std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstRd_src_rdy_n : in std_logic;
IP2Bus_MstWr_d : out std_logic_vector(0 to C_MST_DWIDTH-1);
Bus2IP_MstWr_dst_rdy_n : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
attribute SIGIS of IP2Bus_Mst_Reset: signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
-- Define the memory map for each command register, Address[24 to 31]
-- This value is the offset from the base address assigned to this module
constant C_TOGGLE_PREEMPTION : std_logic_vector(0 to 7) := "01001000"; -- 0x48
constant C_SET_DEFAULT_PRIORITY : std_logic_vector(0 to 7) := "01001100"; -- 0x4C
constant C_GET_IDLE_THREAD : std_logic_vector(0 to 7) := "01010000"; -- 0x50
constant C_SET_IDLE_THREAD : std_logic_vector(0 to 7) := "01010100"; -- 0x54
constant C_GET_ENCODER_OUTPUT : std_logic_vector(0 to 7) := "01011000"; -- 0x58
constant C_SET_SCHEDPARAM : std_logic_vector(0 to 7) := "01011100"; -- 0x5C
constant C_GET_ENTRY : std_logic_vector(0 to 7) := "01100000"; -- 0x60
constant C_GET_SCHEDPARAM : std_logic_vector(0 to 7) := "01100100"; -- 0x64
constant C_CHECK_SCHEDPARAM : std_logic_vector(0 to 7) := "01101000"; -- 0x68
constant C_MALLOC_LOCK : std_logic_vector(0 to 7) := "01000100"; -- 0x44
-- TM Command Opcodes
constant ENQUEUE_OPCODE : std_logic_vector(0 to 5) := "000010";
constant DEQUEUE_OPCODE : std_logic_vector(0 to 5) := "000011";
constant IS_QUEUED_OPCODE : std_logic_vector(0 to 5) := "000001";
constant IS_EMPTY_OPCODE : std_logic_vector(0 to 5) := "000110";
-- HW Thread Opcodes
constant HW_THREAD_START : std_logic_vector(0 to 3) := "0001";
-- Initialization Strings & Constants
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant BRAM_init_string : std_logic_vector(0 to 31) := Z32(0 to 31);
-- Busy Signals
signal Next_Thread_Valid_reg : std_logic;
signal Next_Thread_Valid_next : std_logic;
signal sched_busy : std_logic;
signal sched_busy_next : std_logic;
-- ACK signal
signal IP2Bus_Ack : std_logic;
-- Reset Signals
signal reset_addr : std_logic_vector(0 to 8);
-- CE concatenation signals
signal Bus2IP_RdCE_concat : std_logic;
signal Bus2IP_WrCE_concat : std_logic;
-- TM Output Controller signals
signal TM_data_ready : std_logic;
signal TM_data_out : std_logic_vector (0 to 7);
-- Bus Output Controller signals
signal bus_data_ready : std_logic;
signal bus_ack_ready : std_logic;
signal bus_data_out : std_logic_vector (0 to 31);
-- Interrupt Signals
signal Preemption_Interrupt_Line : std_logic;
signal Preemption_Interrupt_Enable : std_logic;
signal Preemption_Interrupt_Enable_next : std_logic;
-- Thread ID registers
signal TM2SCH_current_cpu_tid_reg : std_logic_vector(0 to 7);
signal next_thread_id_reg : std_logic_vector(0 to 7);
signal next_thread_id_next : std_logic_vector(0 to 7);
-- TM <--> SCH Debug Register
signal debug_reg : std_logic_vector(0 to 31);
signal debug_reg_next : std_logic_vector(0 to 31);
-- Reset Signals
-- FIXME: It would be nice to eliminate the default values here
signal inside_reset : std_logic := '0';
signal inside_reset_next : std_logic := '0';
-- Signals for each event type
signal Enqueue_Request : std_logic;
signal Dequeue_Request : std_logic;
signal Is_Queued_Request : std_logic;
signal Is_Empty_Request : std_logic;
signal Get_EncoderOutput_Request : std_logic;
signal Set_SchedParam_Request : std_logic;
signal Get_SchedParam_Request : std_logic;
signal Check_SchedParam_Request : std_logic;
signal Toggle_Preemption_Request : std_logic;
signal Get_IdleThread_Request : std_logic;
signal Set_IdleThread_Request : std_logic;
signal Get_Entry_Request : std_logic;
signal Default_Priority_Request : std_logic;
signal Error_Request : std_logic;
signal MALLOC_Lock_Request : std_logic;
-- State Machine data signals
signal lookup_entry : std_logic_vector(0 to 31);
signal lookup_entry_next : std_logic_vector(0 to 31);
signal dequeue_entry : std_logic_vector(0 to 31);
signal dequeue_entry_next : std_logic_vector(0 to 31);
signal enqueue_entry : std_logic_vector(0 to 31);
signal enqueue_entry_next : std_logic_vector(0 to 31);
signal enqueue_pri_entry : std_logic_vector(0 to 31);
signal enqueue_pri_entry_next : std_logic_vector(0 to 31);
signal deq_pri_entry : std_logic_vector(0 to 31);
signal deq_pri_entry_next : std_logic_vector(0 to 31);
signal sched_param : std_logic_vector(0 to 31);
signal sched_param_next : std_logic_vector(0 to 31);
signal old_tail_ptr : std_logic_vector(0 to 7);
signal old_tail_ptr_next : std_logic_vector(0 to 7);
signal current_entry_pri_value : std_logic_vector(0 to 6);
signal current_entry_pri_value_next : std_logic_vector(0 to 6);
signal old_priority : std_logic_vector(0 to 6);
signal old_priority_next : std_logic_vector(0 to 6);
signal new_priority : std_logic_vector(0 to 6);
signal new_priority_next : std_logic_vector(0 to 6);
signal lookup_id : std_logic_vector(0 to 7);
signal lookup_id_next : std_logic_vector(0 to 7);
signal idle_thread_id : std_logic_vector(0 to 7);
signal idle_thread_id_next : std_logic_vector(0 to 7);
signal idle_thread_valid : std_logic;
signal idle_thread_valid_next : std_logic;
signal temp_valid : std_logic;
signal temp_valid_next : std_logic;
-- BRAM Constants
constant BRAM_ADDRESS_BITS : integer := 9;
constant BRAM_DATA_BITS : integer := 32;
-- BRAM signals (THREAD_DATA)
signal DOA : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ADDRA : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1) := (others => '0');
signal DIA : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ENA : std_logic := '0';
signal WEA : std_logic := '0';
-- BRAM signals (PRIORITY_DATA)
signal DOB : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ADDRB : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1) := (others => '0');
signal DIB : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ENB : std_logic := '0';
signal WEB : std_logic := '0';
-- BRAM signals (PARAM_DATA)
signal DOU : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ADDRU : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1) := (others => '0');
signal DIU : std_logic_vector(0 to BRAM_DATA_BITS - 1) := (others => '0');
signal ENU : std_logic := '0';
signal WEU : std_logic := '0';
-- Priority Encoder Constants & Signals
constant INPUT_BITS : integer := 128;
constant OUTPUT_BITS : integer := 7;
constant CHUNK_BITS : integer := 32;
signal encoder_reset : std_logic;
signal encoder_input : std_logic_vector(0 to INPUT_BITS - 1);
signal encoder_input_next : std_logic_vector(0 to INPUT_BITS - 1);
signal encoder_output : std_logic_vector(0 to OUTPUT_BITS - 1);
signal encoder_enable_next : std_logic;
signal encoder_enable : std_logic;
-- Lock/Mutex signals
signal lock_op : std_logic;
signal lock_op_next : std_logic;
signal lock_count : std_logic_vector(0 to 3);
signal lock_count_next : std_logic_vector(0 to 3);
signal malloc_mutex : std_logic;
signal malloc_mutex_next : std_logic;
signal malloc_mutex_holder : std_logic_vector(0 to 7);
signal malloc_mutex_holder_next : std_logic_vector(0 to 7);
-- signal and type for MASTER FSM
type master_state_type is
(
idle, -- idle states
wait_trans_done, -- wait for bus transaction to complete
reset, -- reset states
reset_BRAM,
reset_wait_4_ack,
GET_encoder_output, -- get_encoder_output state
SET_SCHED_PARAM_begin, -- set_sched_param states
SET_SCHED_PARAM_lookup_setpri_entries_begin,
SET_SCHED_PARAM_lookup_setpri_entries_idle,
SET_SCHED_PARAM_lookup_setpri_entries_finished,
SET_SCHED_PARAM_lookup_old_pri_entry_idle,
SET_SCHED_PARAM_lookup_old_pri_entry_finished,
SET_SCHED_PARAM_priority_field_check,
SET_SCHED_PARAM_lookup_old_head_ptr_idle,
SET_SCHED_PARAM_lookup_old_head_ptr_finished,
SET_SCHED_PARAM_lookup_old_tail_ptr_idle,
SET_SCHED_PARAM_lookup_old_tail_ptr_finished,
SET_SCHED_PARAM_lookup_prev_ptr_idle,
SET_SCHED_PARAM_lookup_prev_ptr_finished,
SET_SCHED_PARAM_write_back_deq_pri_entry,
SET_SCHED_PARAM_begin_add_to_new_pri_queue,
SET_SCHED_PARAM_init_tail_ptr,
SET_SCHED_PARAM_lookup_enq_old_tail_ptr_idle,
SET_SCHED_PARAM_update_enqueue_info,
SET_SCHED_PARAM_write_back_entries,
SET_SCHED_PARAM_wait_for_encoder_0,
SET_SCHED_PARAM_wait_for_encoder_1,
SET_SCHED_PARAM_last_wait_0,
SET_SCHED_PARAM_last_wait_1,
SET_SCHED_PARAM_check_encoder,
SET_SCHED_PARAM_lookup_highest_pri_entry_idle,
SET_SCHED_PARAM_lookup_highest_pri_entry_finished,
SET_SCHED_PARAM_preemption_check,
SET_SCHED_PARAM_return_with_error,
SET_SCHED_PARAM_return_with_no_error,
GET_SCHED_PARAM_begin, -- get_sched_param states
GET_SCHED_PARAM_lookup_entry,
GET_SCHED_PARAM_lookup_entry_idle,
GET_SCHED_PARAM_lookup_entry_finished,
CHECK_SCHED_PARAM_begin, -- check_sched_param states
CHECK_SCHED_PARAM_lookup_entries,
CHECK_SCHED_PARAM_lookup_entries_idle,
CHECK_SCHED_PARAM_lookup_entries_finished,
ENQ_begin, -- enqueue states
ENQ_lookup_enqueue_entry_idle,
ENQ_lookup_enqueue_entry_finished,
ENQ_start_hw_thread_begin,
ENQ_start_hw_thread_finished,
ENQ_lookup_enqueue_pri_entry_idle,
ENQ_lookup_enqueue_pri_entry_finished,
ENQ_init_head_pointer,
ENQ_init_tail_pointer,
ENQ_wait_for_encoder_0,
ENQ_lookup_old_tail_ptr,
ENQ_lookup_old_tail_ptr_idle,
ENQ_lookup_old_tail_ptr_finished,
ENQ_write_back_entries,
ENQ_lookup_highest_pri_entry,
ENQ_lookup_highest_pri_entry_idle,
ENQ_lookup_highest_pri_entry_finished,
ENQ_preemption_check,
DEQ_begin, -- dequeue states
DEQ_lookup_dequeue_entry_idle,
DEQ_lookup_dequeue_entry_finished,
DEQ_lookup_deq_pri_entry_idle,
DEQ_lookup_deq_pri_entry_finished,
DEQ_lookup_old_head_ptr_idle,
DEQ_lookup_old_head_ptr_finished,
DEQ_write_back_entries,
DEQ_wait_for_encoder_0,
DEQ_wait_for_encoder_1,
DEQ_wait_for_encoder_2,
DEQ_check_encoder_output,
DEQ_lookup_highest_pri_entry_idle,
DEQ_lookup_highest_pri_entry_finished,
MALLOC_LOCK, -- MALLOC lock states
MALLOC_LOCK_idle,
MALLOC_LOCK_idle_finished,
MALLOC_LOCK_ACQUIRE,
MALLOC_LOCK_ACQUIRE_RETURN,
MALLOC_LOCK_RELEASE,
MALLOC_LOCK_RELEASE_next,
MALLOC_LOCK_RELEASE_RETURN,
GET_ENTRY_begin, -- get entry states
GET_ENTRY_lookup_entry,
GET_ENTRY_lookup_entry_idle,
GET_ENTRY_lookup_entry_finished,
IS_QUEUED_begin, -- is_queued states
IS_QUEUED_lookup_entry,
IS_QUEUED_lookup_entry_idle,
IS_QUEUED_lookup_entry_finished,
IS_EMPTY_check, -- is_empty states
IS_EMPTY_finished,
SET_IDLE_THREAD_begin, -- set_idle_thread states
SET_IDLE_THREAD_lookup_entries_idle,
SET_IDLE_THREAD_lookup_entries_finished,
SET_IDLE_THREAD_return_with_error,
SET_IDLE_THREAD_return_with_no_error
);
signal current_state_master, next_state_master : master_state_type := idle;
---------------------------------------------------
-- is_encoder_bit_zero()
--********************
-- Function used to check an encoder bit
-- Returns booleans:
-- * '0' --> True
-- * '1' --> False
---------------------------------------------------
function is_encoder_bit_zero(pri_index: integer; e_entry: std_logic_vector(0 to INPUT_BITS-1)) return boolean is
begin
if (e_entry(pri_index) = '0') then
return true;
else
return false;
end if;
end function is_encoder_bit_zero;
---------------------------------------------------
---------------------------------------------------
-- set_encoder_bit()
-- *******************
-- Function used to set an encoder bit
--
---------------------------------------------------
function set_encoder_bit(e_bit: std_logic; pri: integer; e_entry: std_logic_vector(0 to INPUT_BITS - 1)) return std_logic_vector is
variable temp_entry : std_logic_vector(0 to INPUT_BITS-1);
begin
temp_entry := e_entry; -- make a copy of the entry
temp_entry(pri) := e_bit; -- update bit in entry
return temp_entry; -- return new entry
end function set_encoder_bit;
---------------------------------------------------
---------------------------------------------------
-- bit_set()
-- *******************
-- Determine if any bit in the array is set.
-- If any of the bits are set then '1' is returned,
-- otherwise '0' is returned.
---------------------------------------------------
function bit_set( data : in std_logic_vector ) return std_logic is
begin
for i in data'range loop
if( data(i) = '1' ) then
return '1';
end if;
end loop;
return '0';
end function;
---------------------------------------------------
---------------------------------------------------
-- get_head_pointer()
-- *******************
-- function to extract the head_pointer field from a
-- priority attribute entry
--
---------------------------------------------------
function get_head_pointer(entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 7);
end function get_head_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_head_pointer()
-- *******************
-- function to set the head_pointer field for a
-- priority attribute entry
--
---------------------------------------------------
function set_head_pointer(head_ptr: std_logic_vector(0 to 7); entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return head_ptr & entry(8 to 31);
end function set_head_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_tail_pointer()
-- *******************
-- function to extract the tail_pointer field from a
-- priority attribute entry
--
---------------------------------------------------
function get_tail_pointer(entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(8 to 15);
end function get_tail_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_tail_pointer()
-- *******************
-- function to set the tail_pointer field for a
-- priority attribute entry
--
---------------------------------------------------
function set_tail_pointer(tail_ptr: std_logic_vector(0 to 7); entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 7) & tail_ptr & entry(16 to 31);
end function set_tail_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_priority()
-- *******************
-- function to extract the priority field from a
-- scheduler attribute entry
--
---------------------------------------------------
function get_priority(entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(9 to 15);
end function get_priority;
---------------------------------------------------
---------------------------------------------------
-- set_priority()
-- *******************
-- function to set the priority field for a
-- scheduler attribute entry
--
---------------------------------------------------
function set_priority(priority: std_logic_vector(0 to 6); entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 8) & priority & entry(16 to 31);
end function set_priority;
---------------------------------------------------
---------------------------------------------------
-- get_next_pointer()
-- *******************
-- function to extract the next_pointer field from a
-- scheduler attribute entry
--
---------------------------------------------------
function get_next_pointer(entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(1 to 8);
end function get_next_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_next_pointer()
-- *******************
-- function to set the next_pointer field for a
-- scheduler attribute entry
--
---------------------------------------------------
function set_next_pointer(next_ptr: std_logic_vector(0 to 7); entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0) & next_ptr & entry(9 to 31);
end function set_next_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_prev_pointer()
-- *******************
-- function to extract the prev_pointer field from a
-- scheduler attribute entry
--
---------------------------------------------------
function get_prev_pointer(entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(16 to 23);
end function get_prev_pointer;
---------------------------------------------------
---------------------------------------------------
-- set_prev_pointer()
-- *******************
-- function to set the prev_pointer field for a
-- scheduler attribute entry
--
---------------------------------------------------
function set_prev_pointer(prev_ptr: std_logic_vector(0 to 7); entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return entry(0 to 15) & prev_ptr & entry(24 to 31);
end function set_prev_pointer;
---------------------------------------------------
---------------------------------------------------
-- get_queue_bit()
-- *******************
-- function to extract the queue bit field from a
-- scheduler attribute entry
--
---------------------------------------------------
function get_queue_bit(entry: std_logic_vector(0 to 31)) return std_logic is
begin
return entry(0);
end function get_queue_bit;
---------------------------------------------------
---------------------------------------------------
-- set_queue_bit()
-- *******************
-- function to set the queue bit field for a
-- scheduler attribute entry
--
---------------------------------------------------
function set_queue_bit(q_bit: std_logic; entry: std_logic_vector(0 to 31)) return std_logic_vector is
begin
return q_bit & entry(1 to 31);
end function set_queue_bit;
---------------------------------------------------
---------------------------------------------------
-- Component Instantiation of the Priority Encoder
---------------------------------------------------
component parallel
generic
(
INPUT_BITS : integer := 128;
OUTPUT_BITS : integer := 7;
CHUNK_BITS : integer := 32
);
port
(
clk : in std_logic;
rst : in std_logic;
input : in std_logic_vector(0 to 127);
enable : in std_logic;
output : out std_logic_vector(0 to 6)
);
end component parallel;
---------------------------------------------------
-- Component Instantiation of the Inferred BRAM entity
---------------------------------------------------
component infer_bram
generic
(
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1)
);
end component infer_BRAM;
---------------------------------------------------
--*************************************************
-- Beginning of user_logic ARCHITECTURE
--*************************************************
------------------------------------------
-- Signals for user logic master model example
------------------------------------------
-- signals for master model control/status registers write/read
signal mst_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
-- signals for master model control/status registers
type BYTE_REG_TYPE is array(0 to 15) of std_logic_vector(0 to 7);
signal mst_go, IP2Bus_MstWrReq : std_logic;
-- signals for master model command interface state machine
type CMD_CNTL_SM_TYPE is (CMD_IDLE, CMD_RUN, CMD_WAIT_FOR_DATA, CMD_DONE);
signal mst_cmd_sm_state : CMD_CNTL_SM_TYPE;
signal mst_cmd_sm_set_done : std_logic;
signal mst_cmd_sm_set_error : std_logic;
signal mst_cmd_sm_set_timeout : std_logic;
signal mst_cmd_sm_busy : std_logic;
signal mst_cmd_sm_clr_go : std_logic;
signal mst_cmd_sm_rd_req : std_logic;
signal mst_cmd_sm_wr_req : std_logic;
signal mst_cmd_sm_reset : std_logic;
signal mst_cmd_sm_bus_lock : std_logic;
signal IP2Bus_Addr, mst_cmd_sm_ip2bus_addr : std_logic_vector(0 to C_MST_AWIDTH-1);
signal mst_cmd_sm_ip2bus_be : std_logic_vector(0 to C_MST_DWIDTH/8-1);
signal mst_fifo_valid_write_xfer : std_logic;
signal mst_fifo_valid_read_xfer : std_logic;
begin
--USER logic implementation added here
-- user logic master command interface assignments
IP2Bus_MstRd_Req <= mst_cmd_sm_rd_req;
IP2Bus_MstWr_Req <= mst_cmd_sm_wr_req;
IP2Bus_Mst_Addr <= mst_cmd_sm_ip2bus_addr;
IP2Bus_Mst_BE <= mst_cmd_sm_ip2bus_be;
IP2Bus_Mst_Lock <= mst_cmd_sm_bus_lock;
IP2Bus_Mst_Reset <= mst_cmd_sm_reset;
--implement master command interface state machine
mst_go <= IP2Bus_MstWrReq;
MASTER_CMD_SM_PROC : process( Bus2IP_Clk ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if ( Bus2IP_Reset = '1' ) then
-- reset condition
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '0';
else
-- default condition
mst_cmd_sm_clr_go <= '0';
mst_cmd_sm_rd_req <= '0';
mst_cmd_sm_wr_req <= '0';
mst_cmd_sm_bus_lock <= '0';
mst_cmd_sm_reset <= '0';
mst_cmd_sm_ip2bus_addr <= (others => '0');
mst_cmd_sm_ip2bus_be <= (others => '0');
mst_cmd_sm_set_done <= '0';
mst_cmd_sm_set_error <= '0';
mst_cmd_sm_set_timeout <= '0';
mst_cmd_sm_busy <= '1';
-- state transition
case mst_cmd_sm_state is
when CMD_IDLE =>
if ( mst_go = '1' ) then
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_clr_go <= '1';
else
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end if;
when CMD_RUN =>
if ( Bus2IP_Mst_CmdAck = '1' and Bus2IP_Mst_Cmplt = '0' ) then
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
elsif ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
if ( Bus2IP_Mst_Cmd_Timeout = '1' ) then
-- PLB address phase timeout
mst_cmd_sm_set_error <= '1';
mst_cmd_sm_set_timeout <= '1';
elsif ( Bus2IP_Mst_Error = '1' ) then
-- PLB data transfer error
mst_cmd_sm_set_error <= '1';
end if;
else
mst_cmd_sm_state <= CMD_RUN;
mst_cmd_sm_rd_req <= '0'; -- Perform a write (rd = '0', wr = '1')
mst_cmd_sm_wr_req <= '1';
mst_cmd_sm_ip2bus_addr <= IP2Bus_Addr; -- Setup address
mst_cmd_sm_ip2bus_be <= (others => '1'); -- Use all byte lanes
mst_cmd_sm_bus_lock <= '0'; -- De-assert bus lock
end if;
when CMD_WAIT_FOR_DATA =>
if ( Bus2IP_Mst_Cmplt = '1' ) then
mst_cmd_sm_state <= CMD_DONE;
else
mst_cmd_sm_state <= CMD_WAIT_FOR_DATA;
end if;
when CMD_DONE =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_set_done <= '1';
mst_cmd_sm_busy <= '0';
when others =>
mst_cmd_sm_state <= CMD_IDLE;
mst_cmd_sm_busy <= '0';
end case;
end if;
end if;
end process MASTER_CMD_SM_PROC;
---------------------------------------------------
-- Entity Instantiation of the Priority Encoder
---------------------------------------------------
priority_encoder : parallel
generic map
(
INPUT_BITS => INPUT_BITS,
OUTPUT_BITS => OUTPUT_BITS,
CHUNK_BITS => CHUNK_BITS
)
port map
(
clk => Bus2IP_Clk,
rst => encoder_reset,
input => encoder_input,
enable => encoder_enable,
output => encoder_output
);
---------------------------------------------------
-- Entity Instantiation of the THREAD_DATA BRAM
---------------------------------------------------
thread_data_bram : infer_bram
generic map
(
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map
(
CLKA => Bus2IP_Clk,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DIA => DIA,
DOA => DOA
);
---------------------------------------------------
-- Entity Instantiation of the PRIORITY_DATA BRAM
---------------------------------------------------
priority_data_bram : infer_bram
generic map
(
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map
(
CLKA => Bus2IP_Clk,
ENA => ENB,
WEA => WEB,
ADDRA => ADDRB,
DIA => DIB,
DOA => DOB
);
---------------------------------------------------
-- Entity Instantiation of the PARAM_DATA BRAM
---------------------------------------------------
param_data_bram : infer_bram
generic map
(
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map
(
CLKA => Bus2IP_Clk,
ENA => ENU,
WEA => WEU,
ADDRA => ADDRU,
DIA => DIU,
DOA => DOU
);
-- Create concatenation signals
Bus2IP_RdCE_concat <= bit_set(Bus2IP_RdCE);
Bus2IP_WrCE_concat <= bit_set(Bus2IP_WrCE);
-- Connect registers to external port signals...
SCH2TM_busy <= sched_busy;
SCH2TM_next_cpu_tid <= next_thread_id_reg;
SCH2TM_next_tid_valid <= Next_Thread_Valid_reg;
-- Connect port signals to registers...
TM2SCH_current_cpu_tid_reg <= TM2SCH_current_cpu_tid;
-- Toggle on/off timeout suppression with read/write requests
--IP2Bus_ToutSup <= (Bus2IP_RdCE_concat) or (Bus2IP_WrCE_concat);
-- AND the Preemption Interrupt Enable w/ the Interrupt line
Preemption_Interrupt <= (Preemption_Interrupt_Line) and (Preemption_Interrupt_Enable);
-- *************************************************************************
-- Process: TM_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to TM
-- * Can be controlled using TM_data_ready and TM_data_out signals.
-- *************************************************************************
TM_OUTPUT_CONTROLLER : process( Bus2IP_Clk, tm_data_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( TM_data_ready = '1' ) then
SCH2TM_data <= TM_data_out; -- put data out to TM and leave until next transaction
end if;
end if;
end process TM_OUTPUT_CONTROLLER;
-- *************************************************************************
-- Process: BUS_OUTPUT_CONTROLLER
-- Purpose: Control output from IP to Bus
-- * Can be controlled using bus_data_ready, bus_ack_ready, and bus_data_out signals.
-- *************************************************************************
BUS_OUTPUT_CONTROLLER : process( Bus2IP_Clk, bus_data_ready, bus_ack_ready ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( bus_data_ready = '1' and bus_ack_ready = '1' ) then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '1'; -- ACK bus
elsif (bus_data_ready = '1' and bus_ack_ready = '0') then
IP2Bus_Data <= bus_data_out; -- put data on bus
IP2Bus_Ack <= '0'; -- turn off ACK
else
IP2Bus_Data <= (others => '0'); -- output 0's on bus
IP2Bus_Ack <= '0'; -- turn off ACK
end if;
end if;
end process BUS_OUTPUT_CONTROLLER;
ACK_ROUTER : process (IP2Bus_Ack, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat) is
begin
-- Turn an "ACK" into a specific ACK (read or write ACK)
if (Bus2IP_RdCE_concat = '1') then
IP2Bus_RdAck <= IP2Bus_Ack;
IP2Bus_WrAck <= '0';
else
IP2Bus_RdAck <= '0';
IP2Bus_WrAck <= IP2Bus_Ack;
end if;
end process;
-- FIXME: This process should be incorporated into the FSM
-- *************************************************************************
-- Process: RESET_ADDR_INC
-- Purpose: Process to increment the "reset" address so that each element of
-- the BRAMs can be indexed and initialized
-- *************************************************************************
RESET_ADDR_INC : process( Bus2IP_Clk, Soft_Reset, inside_reset, ENA ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
reset_addr <= (others => '0');
elsif( ENA = '1' ) then
reset_addr <= reset_addr + 1;
end if;
end if;
end process RESET_ADDR_INC;
-- *************************************************************************
-- Process: TM_CMD_PROC
-- Purpose: Controller and decoder for incoming TM operations (requests)
-- *************************************************************************
TM_CMD_PROC : process (Bus2IP_Clk, TM2SCH_opcode, TM2SCH_data, TM2SCH_request ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Enqueue_Request <= '0';
Dequeue_Request <= '0';
Is_Queued_Request <= '0';
Is_Empty_Request <= '0';
if (TM2SCH_request = '1') then
case (TM2SCH_opcode) is
when ENQUEUE_OPCODE => Enqueue_Request <= '1';
when DEQUEUE_OPCODE => Dequeue_Request <= '1';
when IS_QUEUED_OPCODE => Is_Queued_Request <= '1';
when IS_EMPTY_OPCODE => Is_Empty_Request <= '1';
when others => null;
end case;
end if;
end if;
end process TM_CMD_PROC;
-- *************************************************************************
-- Process: BUS_CMD_PROC
-- Purpose: Controller and decoder for incoming bus operations (reads and writes)
-- *************************************************************************
BUS_CMD_PROC : process (Bus2IP_Clk, Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Bus2IP_Addr ) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
Get_EncoderOutput_Request <= '0';
Set_SchedParam_Request <= '0';
Get_SchedParam_Request <= '0';
Check_SchedParam_Request <= '0';
Toggle_Preemption_Request <= '0';
Get_IdleThread_Request <= '0';
Set_IdleThread_Request <= '0';
Get_Entry_Request <= '0';
Default_Priority_Request <= '0';
Error_Request <= '0';
MALLOC_Lock_Request <= '0';
if( Bus2IP_WrCE_concat = '1' ) then
case Bus2IP_Addr(24 to 31) is
when C_SET_SCHEDPARAM => Set_SchedParam_Request <= '1';
when C_TOGGLE_PREEMPTION => Toggle_Preemption_Request <= '1';
when others => Error_Request <= '1';
end case;
elsif( Bus2IP_RdCE_concat = '1' ) then
case Bus2IP_Addr(24 to 31) is
when C_GET_IDLE_THREAD => Get_IdleThread_Request <= '1';
when C_SET_IDLE_THREAD => Set_IdleThread_Request <= '1';
when C_GET_ENTRY => Get_Entry_Request <= '1';
when C_GET_ENCODER_OUTPUT => Get_EncoderOutput_Request <= '1';
when C_SET_DEFAULT_PRIORITY => Default_Priority_Request <= '1';
when C_GET_SCHEDPARAM => Get_SchedParam_Request <= '1';
when C_CHECK_SCHEDPARAM => Check_SchedParam_Request <= '1';
when C_MALLOC_LOCK => MALLOC_Lock_Request <= '1';
when others => Error_Request <= '1';
end case;
end if;
end if;
end process BUS_CMD_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_STATE_PROC
-- Purpose: Synchronous FSM controller for the master state machine
-- *************************************************************************
MASTER_FSM_STATE_PROC: process(
Bus2IP_Clk, Soft_Reset, inside_reset, next_state_master, encoder_enable_next,
enqueue_pri_entry_next, deq_pri_entry_next, old_tail_ptr_next,
encoder_input_next, next_thread_id_next, lookup_entry_next, sched_param_next,
dequeue_entry_next, enqueue_entry_next, current_entry_pri_value_next,
old_priority_next, new_priority_next, lookup_id_next, idle_thread_id_next,
idle_thread_valid_next, inside_reset_next, Preemption_Interrupt_Enable_next,
sched_busy_next, Next_Thread_Valid_next, debug_reg_next, temp_valid_next,
lock_op_next, lock_count_next, malloc_mutex_next, malloc_mutex_holder_next ) is
begin
if ( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( Soft_Reset = '1' and inside_reset = '0' ) then
-- Initialize all signals...
current_state_master <= reset;
encoder_enable <= '0';
enqueue_pri_entry <= (others => '0');
deq_pri_entry <= (others => '0');
old_tail_ptr <= (others => '0');
encoder_input <= (others => '0');
next_thread_id_reg <= (others => '0');
lookup_entry <= (others => '0');
sched_param <= (others => '0');
dequeue_entry <= (others => '0');
enqueue_entry <= (others => '0');
current_entry_pri_value <= (others => '0');
old_priority <= (others => '0');
new_priority <= (others => '0');
lookup_id <= (others => '0');
idle_thread_id <= (others => '0');
debug_reg <= (others => '0');
idle_thread_valid <= '0';
temp_valid <= '0';
inside_reset <= '1';
Preemption_Interrupt_Enable <= '0';
sched_busy <= '0';
Next_Thread_Valid_reg <= '0';
lock_count <= (others => '0');
lock_op <= '0';
malloc_mutex <= '0';
malloc_mutex_holder <= x"FF";
else
-- Assign all signals to their next state...
current_state_master <= next_state_master;
encoder_enable <= encoder_enable_next;
enqueue_pri_entry <= enqueue_pri_entry_next;
deq_pri_entry <= deq_pri_entry_next;
old_tail_ptr <= old_tail_ptr_next;
encoder_input <= encoder_input_next;
next_thread_id_reg <= next_thread_id_next;
lookup_entry <= lookup_entry_next;
sched_param <= sched_param_next;
dequeue_entry <= dequeue_entry_next;
enqueue_entry <= enqueue_entry_next;
current_entry_pri_value <= current_entry_pri_value_next;
old_priority <= old_priority_next;
new_priority <= new_priority_next;
lookup_id <= lookup_id_next;
idle_thread_id <= idle_thread_id_next;
debug_reg <= debug_reg_next;
idle_thread_valid <= idle_thread_valid_next;
temp_valid <= temp_valid_next;
inside_reset <= inside_reset_next;
Preemption_Interrupt_Enable <= Preemption_Interrupt_Enable_next;
sched_busy <= sched_busy_next;
Next_Thread_Valid_reg <= Next_Thread_Valid_next;
lock_count <= lock_count_next;
lock_op <= lock_op_next;
malloc_mutex <= malloc_mutex_next;
malloc_mutex_holder <= malloc_mutex_holder_next;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
-- *************************************************************************
-- Process: MASTER_FSM_LOGIC_PROC
-- Purpose: Combinational process that contains all state machine logic and
-- state transitions for the master state machine
-- *************************************************************************
MASTER_FSM_LOGIC_PROC: process (
reset_addr, next_thread_id_reg, lookup_entry, sched_param, dequeue_entry,
enqueue_entry, current_entry_pri_value, old_priority, new_priority, lookup_id,
idle_thread_id, idle_thread_valid, temp_valid, current_state_master, inside_reset,
Preemption_Interrupt_Enable, Enqueue_Request, Dequeue_Request,
Is_Queued_Request, Is_Empty_Request, Get_EncoderOutput_Request, Error_Request,
Set_SchedParam_Request, Get_SchedParam_Request, Check_SchedParam_Request,
Toggle_Preemption_Request, Bus2IP_Data, Get_IdleThread_Request,
Set_IdleThread_Request, Get_Entry_Request, Default_Priority_Request,
Bus2IP_RdCE_concat, Bus2IP_WrCE_concat, Soft_Reset, DOA, debug_reg,
TM2SCH_current_cpu_tid_reg, TM2SCH_current_cpu_tid, Bus2IP_Addr, sched_busy,
Next_Thread_Valid_reg, SWTM_DOB, encoder_input, encoder_output, encoder_enable,
enqueue_pri_entry, deq_pri_entry, old_tail_ptr, DOB, DOU, TM2SCH_data,
lock_op, lock_count, malloc_mutex, malloc_mutex_holder, MALLOC_Lock_Request ) is
-- Idle Variable, concatenation of all request signals
variable idle_concat : std_logic_vector(0 to 14);
begin
IP2Bus_Error <= '0'; -- no error
IP2Bus_Addr <= (others => '0');
IP2Bus_MstWrReq <= '0';
IP2Bus_MstWr_d <= (others => '0');
Reset_Done <= '0'; -- reset is done unless we override it later
encoder_reset <= '0';
ADDRA <= (others => '0');
DIA <= (others => '0');
ENA <= '0';
WEA <= '0';
ADDRB <= (others => '0');
DIB <= (others => '0');
ENB <= '0';
WEB <= '0';
ADDRU <= (others => '0');
DIU <= (others => '0');
ENU <= '0';
WEU <= '0';
SWTM_ADDRB <= (others => '0');
SWTM_DIB <= (others => '0');
SWTM_ENB <= '0';
SWTM_WEB <= '0';
encoder_enable_next <= '0';
enqueue_pri_entry_next <= enqueue_pri_entry;
deq_pri_entry_next <= deq_pri_entry;
old_tail_ptr_next <= old_tail_ptr;
encoder_input_next <= encoder_input;
next_state_master <= current_state_master;
next_thread_id_next <= next_thread_id_reg;
lookup_entry_next <= lookup_entry;
sched_param_next <= sched_param;
dequeue_entry_next <= dequeue_entry;
enqueue_entry_next <= enqueue_entry;
current_entry_pri_value_next <= current_entry_pri_value;
old_priority_next <= old_priority;
new_priority_next <= new_priority;
lookup_id_next <= lookup_id;
idle_thread_id_next <= idle_thread_id;
debug_reg_next <= debug_reg;
idle_thread_valid_next <= idle_thread_valid;
temp_valid_next <= temp_valid;
inside_reset_next <= inside_reset;
bus_data_out <= (others => '0');
bus_data_ready <= '0';
bus_ack_ready <= '0';
TM_data_out <= (others => '0');
TM_data_ready <= '0';
Preemption_Interrupt_Line <= '0';
Preemption_Interrupt_Enable_next<= Preemption_Interrupt_Enable;
sched_busy_next <= sched_busy;
Next_Thread_Valid_next <= Next_Thread_Valid_reg;
lock_count_next <= lock_count;
lock_op_next <= lock_op;
malloc_mutex_next <= malloc_mutex;
malloc_mutex_holder_next <= malloc_mutex_holder;
case current_state_master is
when idle =>
-- Assign to variable for case statement
idle_concat := (Enqueue_Request & Dequeue_Request & Is_Queued_Request & Is_Empty_Request & Get_EncoderOutput_Request &
Set_SchedParam_Request & Toggle_Preemption_Request & Get_IdleThread_Request &
Set_IdleThread_Request & Get_Entry_Request & Default_Priority_Request &
Get_SchedParam_Request & Check_SchedParam_Request & MALLOC_Lock_Request & Error_Request);
-- Decode request
case (idle_concat) is
when "100000000000000" => next_state_master <= ENQ_begin; -- Enqueue
when "010000000000000" => next_state_master <= DEQ_begin; -- Dequeue
when "001000000000000" => next_state_master <= IS_QUEUED_begin; -- Is_Queued
when "000100000000000" => next_state_master <= IS_EMPTY_check; -- Is_Empty
when "000010000000000" => next_state_master <= GET_encoder_output; -- Get_EncoderOutput
when "000001000000000" => next_state_master <= SET_SCHED_PARAM_begin; -- Set_SchedParam
when "000000100000000" => Preemption_Interrupt_Enable_next <= Bus2IP_Data(0); -- Toggle_Preemption (single clock cycle op.)
bus_data_out <= (others => '0');
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when "000000010000000" => bus_data_out <= Z32(0 to 22) & idle_thread_id & idle_thread_valid; -- Get_IdleThread
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when "000000001000000" => next_state_master <= SET_IDLE_THREAD_begin; -- Set_IdleThread
when "000000000100000" => next_state_master <= GET_ENTRY_begin; -- Get_Entry
when "000000000010000" => bus_data_out <= (others => '1'); -- ERROR (Set_Default_Priority)
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when "000000000001000" => next_state_master <= GET_SCHED_PARAM_begin; -- Get_SchedParam
when "000000000000100" => next_state_master <= CHECK_SCHED_PARAM_begin; -- Check_SchedParam
when "000000000000010" => next_state_master <= MALLOC_LOCK; -- MALLOC Lock
when "000000000000001" => bus_data_out <= (others => '1'); -- Error!!!
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when others => next_state_master <= idle; -- Others, stay in idle state
end case;
when wait_trans_done =>
-- Goal of this state is to return to the idle state ONLY (iff) the bus transaction has COMPLETELY ended!
bus_data_ready <= '0'; -- de-assert bus transaction signals
bus_ack_ready <= '0';
if( Bus2IP_RdCE_concat = '0' and Bus2IP_WrCE_concat = '0' ) then
next_state_master <= idle;
end if;
----------------------------
-- RESET: begin
----------------------------
when reset =>
WEA <= '0'; -- Turn off any BRAM access that was active
ENA <= '0';
WEB <= '0';
ENB <= '0';
WEU <= '0';
ENU <= '0';
SWTM_WEB<= '0';
SWTM_ENB<= '0';
encoder_reset <= '1'; -- Reset priority encoder
TM_data_out <= (others => '0'); -- Reset TM data out
TM_data_ready <= '1';
Reset_Done <= '0'; -- De-assert Reset_Done
next_state_master <= reset_BRAM;
when reset_BRAM =>
ADDRA <= reset_addr; -- setup BRAM write to init. THREAD_DATA entry
DIA <= set_priority("1000000", BRAM_init_string(0 to 22) & reset_addr);
ENA <= '1';
WEA <= '1';
ADDRB <= reset_addr; -- setup BRAM write to init. PRIORITY_DATA entry
DIB <= BRAM_init_string;
ENB <= '1';
WEB <= '1';
ADDRU <= reset_addr; -- setup BRAM write to init. PARAM_DATA entry
DIU <= BRAM_init_string;
ENU <= '1';
WEU <= '1';
if( reset_addr = "011111111" ) then
next_state_master <= reset_wait_4_ack;
end if;
when reset_wait_4_ack =>
ENA <= '0'; -- turn off BRAM access
WEA <= '0';
ENB <= '0'; -- turn off BRAM access
WEB <= '0';
ENU <= '0'; -- turn off BRAM access
WEU <= '0';
Reset_Done <= '1'; -- Assert that reset has completed
if( Soft_Reset = '0' ) then -- if reset is complete
Reset_Done <= '0'; -- de-assert that reset is complete
inside_reset_next <= '0'; -- de-assert to signal that process is no longer in reset
next_state_master <= idle; -- return to idle stage
end if;
----------------------------
-- RESET: end
----------------------------
----------------------------
-- MALLOC_LOCK: begin
----------------------------
-- Communication - BusCom
-- Submit a request to acquire or release the malloc lock
-- returns zero if the request was denied, one if the request was granted
when MALLOC_LOCK =>
-- Bus2IP_Addr(13) = 0 : RELEASE lock
-- Bus2IP_Addr(13) = 1 : ACQUIRE lock
lock_op_next <= Bus2IP_Addr(13);
-- Store tid requesting the lock
lookup_id_next <= Bus2IP_Addr(16 to 23);
next_state_master <= MALLOC_LOCK_IDLE;
when MALLOC_LOCK_idle =>
-- idle state
next_state_master <= MALLOC_LOCK_idle_finished;
when MALLOC_LOCK_idle_finished =>
-- default next state
next_state_master <= MALLOC_LOCK_ACQUIRE;
if(lock_op = '0') then
-- Override default next state
next_state_master <= MALLOC_LOCK_RELEASE;
end if;
when MALLOC_LOCK_ACQUIRE =>
if(malloc_mutex = '0') then
malloc_mutex_holder_next <= lookup_id;
lock_count_next <= lock_count + 1;
malloc_mutex_next <= '1';
elsif(malloc_mutex = '1' AND malloc_mutex_holder = lookup_id) then
lock_count_next <= lock_count + 1;
end if;
next_state_master <= MALLOC_LOCK_ACQUIRE_RETURN;
when MALLOC_LOCK_ACQUIRE_RETURN =>
if(malloc_mutex_holder = lookup_id) then
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 30) & '1';
else
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 31);
end if;
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when MALLOC_LOCK_RELEASE =>
if(malloc_mutex_holder = lookup_id) then
lock_count_next <= lock_count - 1;
end if;
next_state_master <= MALLOC_LOCK_RELEASE_next;
when MALLOC_LOCK_RELEASE_next =>
if(lock_count = x"0") then
-- Release the lock
malloc_mutex_next <= '0';
malloc_mutex_holder_next <= x"FF";
end if;
next_state_master <= MALLOC_LOCK_RELEASE_RETURN;
when MALLOC_LOCK_RELEASE_RETURN =>
if(malloc_mutex_holder = lookup_id) then
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 30) & '1';
else
bus_data_out <= Z32(0 to 3) & lock_count & malloc_mutex_holder & Z32(16 to 31);
end if;
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- MALLOC_LOCK: end
----------------------------
----------------------------
-- ENQ: begin
----------------------------
when ENQ_begin =>
debug_reg_next <= "00" & ENQUEUE_OPCODE & TM2SCH_data & Z32(16 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that scheduler is busy
lookup_id_next <= TM2SCH_data; -- store threadID to ENQ
ADDRA <= '0' & TM2SCH_data; -- setup BRAM read for tid to enqueue from THREAD_DATA
ENA <= '1';
WEA <= '0';
ADDRU <= '0' & TM2SCH_data; -- setup BRAM read for tid to enqueue from PARAM_DATA
ENU <= '1';
WEU <= '0';
next_state_master <= ENQ_lookup_enqueue_entry_idle;
when ENQ_lookup_enqueue_entry_idle =>
-- idle stage
next_state_master <= ENQ_lookup_enqueue_entry_finished;
when ENQ_lookup_enqueue_entry_finished =>
-- DOA has THREAD_DATA entry for tid to ENQ
-- DOU has PARAM_DATA entry for tid to ENQ
-- Check scheduling paramter:
-- If HW range: start HW thread
-- If SW range: add thread to ready-to-run queue
case ( DOU(0 to 24) ) is
when "0000000000000000000000000" =>
-- SW-valid range, proceed with ENQ operation...
debug_reg_next <= debug_reg(0 to 27) & "1000";
Next_Thread_Valid_next <= '0'; -- invalidate the current next_thread
enqueue_entry_next <= set_queue_bit('1',DOA); -- store entry and set as queued
new_priority_next <= get_priority(DOA); -- Assigned priority to this signal b/c used to address encoder_input (used in state below)
ADDRB <= "00" & get_priority(DOA); -- setup BRAM read to get PRIORITY_DATA entry for the enq'd thread
ENB <= '1';
WEB <= '0';
next_state_master <=ENQ_lookup_enqueue_pri_entry_idle;
when others =>
-- HW-valid range, proceed with start HW thread operation...
debug_reg_next <= debug_reg(0 to 27) & "1110";
sched_param_next <= DOU; -- store scheduling param. (base addr. of HW thread)
TM_data_out <= Z32(0 to 7); -- return status to the TM, so the TM will continue processing
TM_data_ready <= '1'; -- and unlock the bus (freeing it so that we can make a master transaction)
sched_busy_next <= '0';
-- No longer use these lines for the new PLB interface
--bus_data_out <= Z32(0 to 27) & HW_THREAD_START; -- put data on bus w/o ACK (for the upcoming write operation)
--bus_data_ready <= '1';
--bus_ack_ready <= '0';
next_state_master <= ENQ_start_hw_thread_begin;
end case;
when ENQ_start_hw_thread_begin =>
-- Start a bus write transaction to start HW thread
IP2Bus_Addr <= sched_param; -- write to base addr. of HW thread (data was put on bus in previous state)
IP2Bus_MstWrReq <= '1';
IP2Bus_MstWr_d <= Z32(0 to 27) & HW_THREAD_START; -- put data to write on bus w/o ACK
next_state_master <= ENQ_start_hw_thread_finished;
when ENQ_start_hw_thread_finished =>
if (mst_cmd_sm_busy = '0') then
-- Master FSM has finished our request, de-assert request lines, and continue on
-- HW thread has been started
-- TM has already been ACK'ed
-- now just return to idle
IP2Bus_Addr <= (others => '0'); -- write to base addr. of HW thread (data was put on bus in previous state)
IP2Bus_MstWrReq <= '0';
IP2Bus_MstWr_d <= (others => '0'); -- put data to write on bus w/o ACK
next_state_master <= idle;
else
-- Master FSM has not yet detected the request, persist
IP2Bus_Addr <= sched_param; -- write to base addr. of HW thread (data was put on bus in previous state)
IP2Bus_MstWrReq <= '1';
IP2Bus_MstWr_d <= Z32(0 to 27) & HW_THREAD_START; -- put data to write on bus w/o ACK
next_state_master <= ENQ_start_hw_thread_finished;
end if;
when ENQ_lookup_enqueue_pri_entry_idle =>
-- idle stage
next_state_master <= ENQ_lookup_enqueue_pri_entry_finished;
when ENQ_lookup_enqueue_pri_entry_finished =>
enqueue_pri_entry_next <= DOB; -- store pri_entry
if ( is_encoder_bit_zero(conv_integer(new_priority), encoder_input)) then
-- Queue is empty for this priority level
-- set encoder_input bit for given priority
encoder_input_next <= set_encoder_bit('1', conv_integer(get_priority(enqueue_entry)), encoder_input);
encoder_enable_next <= '1'; -- allow the priority encoder to process, 1
next_state_master <= ENQ_init_head_pointer;
else
-- Queue is not empty for this priority level
old_tail_ptr_next <= get_tail_pointer(DOB); -- store old tail_ptr
next_state_master <= ENQ_lookup_old_tail_ptr;
end if;
when ENQ_init_head_pointer =>
-- Set head_ptr to the lookup_id
enqueue_pri_entry_next <= set_head_pointer(lookup_id, enqueue_pri_entry);
next_state_master <= ENQ_init_tail_pointer;
when ENQ_init_tail_pointer =>
-- Set tail_ptr to the lookup_id
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
next_state_master <= ENQ_wait_for_encoder_0;
when ENQ_wait_for_encoder_0 =>
-- idle stage
next_state_master <= ENQ_write_back_entries;
when ENQ_lookup_old_tail_ptr =>
ADDRA <= '0' & old_tail_ptr; -- setup read of old tail_ptr
ENA <= '1';
WEA <= '0';
next_state_master <= ENQ_lookup_old_tail_ptr_idle;
when ENQ_lookup_old_tail_ptr_idle =>
-- idle stage
next_state_master <= ENQ_lookup_old_tail_ptr_finished;
when ENQ_lookup_old_tail_ptr_finished =>
-- setup write to make old_tail_ptr's next_ptr point to newly enq'd thread
ADDRA <= '0' & old_tail_ptr;
ENA <= '1';
WEA <= '1';
DIA <= set_next_pointer(lookup_id, DOA);
-- Update enqueue_entry's prev. ptr to point to old_tail_ptr
enqueue_entry_next <= set_prev_pointer(old_tail_ptr, enqueue_entry);
-- Update priority entry's tail_ptr to be newly enq'd thread
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
next_state_master <= ENQ_write_back_entries;
when ENQ_write_back_entries =>
ADDRA <= '0' & lookup_id; -- Write back enqueue_entry
ENA <= '1';
WEA <= '1';
DIA <= enqueue_entry;
ADDRB <= "00" & get_priority(enqueue_entry); -- Write back enqueue_pri_entry
ENB <= '1';
WEB <= '1';
DIB <= enqueue_pri_entry;
next_state_master <= ENQ_lookup_highest_pri_entry;
when ENQ_lookup_highest_pri_entry =>
ADDRB <= "00" & encoder_output; -- setup read of highest PRIORITY_DATA entry in system
ENB <= '1';
WEA <= '0';
ADDRA <= '0' & TM2SCH_current_cpu_tid_reg; -- setup read of currently running thread
ENA <= '1';
WEA <= '0';
next_state_master <= ENQ_lookup_highest_pri_entry_idle;
when ENQ_lookup_highest_pri_entry_idle =>
-- idle stage
next_state_master <= ENQ_lookup_highest_pri_entry_finished;
when ENQ_lookup_highest_pri_entry_finished =>
-- DOA has current thread entry
-- DOB has highest priority entry
current_entry_pri_value_next <= get_priority(DOA); -- store current_entry's priority
next_thread_id_next <= get_head_pointer(DOB); -- store next_thread_id
next_state_master <= ENQ_preemption_check;
when ENQ_preemption_check =>
-- Check if next_thread_id has "better" priority than the current_entry_pri_value
if( encoder_output < current_entry_pri_value ) then
Preemption_Interrupt_Line <= '1';
end if;
TM_data_out <= get_queue_bit(enqueue_entry) & Z32(1 to 7); -- return 0x80 to TM
TM_data_ready <= '1';
Next_Thread_Valid_next <= '1'; -- Assert that the next_thread is valid
sched_busy_next <= '0'; -- de-assert busy signal
next_state_master <= idle; -- return to idle stage
----------------------------
-- ENQ: end
----------------------------
----------------------------
-- DEQ: begin
----------------------------
when DEQ_begin =>
debug_reg_next <= "00" & DEQUEUE_OPCODE & TM2SCH_data & Z32(16 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that scheduler is busy
Next_Thread_Valid_next <= '0'; -- invalidate the next_thread
ADDRA <= '0' & TM2SCH_current_cpu_tid; -- setup BRAM read of thread to dequeue
ENA <= '1';
WEA <= '0';
next_state_master <= DEQ_lookup_dequeue_entry_idle;
when DEQ_lookup_dequeue_entry_idle =>
-- idle stage
next_state_master <= DEQ_lookup_dequeue_entry_finished;
when DEQ_lookup_dequeue_entry_finished =>
dequeue_entry_next <= set_queue_bit('0',DOA); -- store entry in variable and clear queue-bit
ADDRB <= "00" & get_priority(DOA); -- setup read of deq_pri_entry
ENB <= '1';
WEB <= '0';
next_state_master <= DEQ_lookup_deq_pri_entry_idle;
when DEQ_lookup_deq_pri_entry_idle =>
-- idle stage
next_state_master <= DEQ_lookup_deq_pri_entry_finished;
when DEQ_lookup_deq_pri_entry_finished =>
deq_pri_entry_next <= DOB; -- store deq entry from PRIORITY_DATA
if ( get_head_pointer(DOB) = get_tail_pointer(DOB) ) then
-- If list priority Q has 1 element (head = tail) then list will now be empty
-- Clear encoder bit for given priority
encoder_input_next <= set_encoder_bit('0', conv_integer(get_priority(dequeue_entry)), encoder_input);
encoder_enable_next <= '1'; -- allow the priority encoder to process, 1
next_state_master <= DEQ_wait_for_encoder_0;
else
-- Otherwise...
ADDRA <= '0' & get_head_pointer(DOB); -- setup read of head_ptr
ENA <= '1';
WEA <= '0';
next_state_master <= DEQ_lookup_old_head_ptr_idle;
end if;
when DEQ_wait_for_encoder_0 =>
-- idle stage
next_state_master <= DEQ_wait_for_encoder_1;
when DEQ_wait_for_encoder_1 =>
-- idle stage
next_state_master <= DEQ_wait_for_encoder_2;
when DEQ_wait_for_encoder_2 =>
-- idle stage
next_state_master <= DEQ_write_back_entries;
when DEQ_lookup_old_head_ptr_idle =>
-- idle stage
next_state_master <= DEQ_lookup_old_head_ptr_finished;
when DEQ_lookup_old_head_ptr_finished =>
-- DOA has old_head_ptr entry
-- update head_ptr to be next_ptr of old head_ptr
deq_pri_entry_next <= set_head_pointer( get_next_pointer(DOA), deq_pri_entry);
next_state_master <= DEQ_write_back_entries;
when DEQ_write_back_entries =>
ADDRA <= '0' & TM2SCH_current_cpu_tid; -- setup write to update dequeue_entry
ENA <= '1';
WEA <= '1';
DIA <= dequeue_entry;
ADDRB <= "00" & get_priority(dequeue_entry); -- setup write to update deq_pri_entry
ENB <= '1';
WEB <= '1';
DIB <= deq_pri_entry;
next_state_master <= DEQ_check_encoder_output;
when DEQ_check_encoder_output =>
if (encoder_input = 0 ) then
-- No queued threads in the system: finish with invalid next thread or with idle thread if one exists
if (idle_thread_valid = '1') then
Next_Thread_Valid_next <= '1';
next_thread_id_next <= idle_thread_id;
else
Next_Thread_Valid_next <= '0';
end if;
TM_data_out <= Z32(0 to 7); -- return all 0's (success) to TM
TM_data_ready <= '1';
sched_busy_next <= '0'; -- de-assert busy signal
next_state_master <= idle;
else
-- Queued threads exist...
ADDRB <= "00" & encoder_output; -- setup read of highest priority (PRIORITY_DATA) entry
ENB <= '1';
WEB <= '0';
next_state_master <= DEQ_lookup_highest_pri_entry_idle;
end if;
when DEQ_lookup_highest_pri_entry_idle =>
-- idle stage
next_state_master <= DEQ_lookup_highest_pri_entry_finished;
when DEQ_lookup_highest_pri_entry_finished =>
next_thread_id_next <= get_head_pointer(DOB); -- store next_thread_id
TM_data_out <= Z32(0 to 7); -- return all 0's (success) to TM
TM_data_ready <= '1';
sched_busy_next <= '0'; -- de-assert busy signal
Next_Thread_Valid_next <= '1'; -- Assert that the next_thread is valid
next_state_master <= idle; -- return to idle stage
----------------------------
-- DEQ: end
----------------------------
----------------------------
-- GET_ENTRY: begin
----------------------------
when GET_ENTRY_begin =>
lookup_id_next <= Bus2IP_Addr(16 to 23); -- latch thread_id to lookup
next_state_master <= GET_ENTRY_lookup_entry;
when GET_ENTRY_lookup_entry =>
ADDRA <= '0' & lookup_id; -- setup BRAM read of lookup thread_id
ENA <= '1';
WEA <= '0';
next_state_master <= GET_ENTRY_lookup_entry_idle;
when GET_ENTRY_lookup_entry_idle =>
-- idle stage
next_state_master <= GET_ENTRY_lookup_entry_finished;
when GET_ENTRY_lookup_entry_finished =>
ENA <= '0'; -- turn off BRAM access
WEA <= '0';
bus_data_out <= DOA; -- return entry on bus
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- GET_ENTRY: end
----------------------------
----------------------------
-- IS_QUEUED: begin
----------------------------
when IS_QUEUED_begin =>
debug_reg_next <= "00" & IS_QUEUED_OPCODE & TM2SCH_data & Z32(16 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that operation is busy
lookup_id_next <= TM2SCH_data; -- latch thread_id to lookup
next_state_master <= IS_QUEUED_lookup_entry;
when IS_QUEUED_lookup_entry =>
ADDRA <= '0' & lookup_id; -- setup BRAM read of lookup thread_id
ENA <= '1';
WEA <= '0';
next_state_master <= IS_QUEUED_lookup_entry_idle;
when IS_QUEUED_lookup_entry_idle =>
-- idle stage
next_state_master <= IS_QUEUED_lookup_entry_finished;
when IS_QUEUED_lookup_entry_finished =>
ENA <= '0'; -- turn off BRAM access
WEA <= '0';
TM_data_out <= Z32(0 to 6) & get_queue_bit(DOA); -- return data to TM
TM_data_ready <= '1';
sched_busy_next <= '0'; -- de-assert busy signal
next_state_master <= idle;
----------------------------
-- IS_QUEUED: end
----------------------------
----------------------------
-- IS_EMPTY: begin
----------------------------
when IS_EMPTY_check =>
debug_reg_next <= "00" & IS_EMPTY_OPCODE & TM2SCH_data & Z32(16 to 31); -- store debug info
sched_busy_next <= '1'; -- assert that scheduler is busy
next_state_master <= IS_EMPTY_finished;
when IS_EMPTY_finished =>
-- Check to see if all queues are empty
if (encoder_input = 0) then
TM_data_out <= Z32(0 to 6) & '1'; -- set data_out to true, (LSB = 1)
else
TM_data_out <= Z32(0 to 6) & '0'; -- set data_out to false, (LSB = 0)
end if;
sched_busy_next <= '0'; --de-assert busy signal
TM_data_ready <= '1'; -- return results to TM
next_state_master <= idle;
----------------------------
-- IS_EMPTY: end
----------------------------
----------------------------
-- GET_encoder_output: begin
----------------------------
when GET_encoder_output =>
-- bus_data_out <= Z32(0 to 24)& encoder_output; -- return highest priority entry on bus
bus_data_out <= debug_reg; -- return debug reg on bus FIXME (last TM request)
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- GET_encoder_output: end
----------------------------
----------------------------
-- SET_sched_param: begin
----------------------------
when SET_SCHED_PARAM_begin =>
debug_reg_next <= (others => '1');
temp_valid_next <= Next_Thread_Valid_reg; -- Store the current Next_Thread_Valid bit (used for restore later)
Next_Thread_Valid_next <= '0'; -- invalidate the next thread
lookup_id_next <= Bus2IP_Addr(16 to 23); -- store tid
sched_param_next <= Bus2IP_Data(0 to 31); -- store sched_param
new_priority_next <= Bus2IP_Data(25 to 31); -- store priority (low 7 bits of sched_param)
ADDRU <= '0' & Bus2IP_Addr(16 to 23); -- setup BRAM write to update sched param value in PARAM_DATA
DIU <= Bus2IP_Data(0 to 31);
ENU <= '1';
WEU <= '1';
-- Check to see if sched param is in SW-valid range
case ( Bus2IP_Data(0 to 24) ) is
when "0000000000000000000000000" => -- SW-valid range, proceed with a set_priority operation
next_state_master <= SET_SCHED_PARAM_lookup_setpri_entries_begin;
when others => -- HW-valid range, simply end, no error checks
next_state_master <= SET_SCHED_PARAM_return_with_no_error;
end case;
when SET_SCHED_PARAM_lookup_setpri_entries_begin =>
ADDRA <= '0' & lookup_id; -- setup BRAM read of thread_id to
ENA <= '1';
WEA <= '0';
ADDRB <= "00" & new_priority; -- setup BRAM read of new_priority_entry
ENB <= '1';
WEB <= '0';
SWTM_ADDRB <= '0' & lookup_id; -- setup SWTM_BRAM read of thread_id
SWTM_ENB <= '1';
SWTM_WEB <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_setpri_entries_idle;
when SET_SCHED_PARAM_lookup_setpri_entries_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_setpri_entries_finished;
when SET_SCHED_PARAM_lookup_setpri_entries_finished =>
old_priority_next <= get_priority(DOA); -- store old_priority value
lookup_entry_next <= DOA; -- store setpri_entry
enqueue_pri_entry_next <= DOB; -- store new_priority_entry
-- Check Validity of Set_Priority operation
if ( (SWTM_DOB(26) = '1') and
( (lookup_id = TM2SCH_current_cpu_tid_reg) or
(SWTM_DOB(16 to 23) = TM2SCH_current_cpu_tid_reg)
)
) then
if(get_queue_bit(DOA) = '1') then
-- If QUEUED...
ADDRB <= "00" & get_priority(DOA); -- setup read of old_pri_entry
ENB <= '1';
WEB <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_old_pri_entry_idle;
else
-- IF ~QUEUED...
ADDRA <= '0' & lookup_id; -- setup BRAM write to update priority value in THREAD_DATA
DIA <= set_priority(new_priority, DOA);
ENA <= '1';
WEA <= '1';
next_state_master <= SET_SCHED_PARAM_check_encoder;
end if;
else
-- Otherwise, return with an error b/c operation cannot be completed...
next_state_master <= SET_SCHED_PARAM_return_with_error;
end if;
when SET_SCHED_PARAM_lookup_old_pri_entry_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_old_pri_entry_finished;
when SET_SCHED_PARAM_lookup_old_pri_entry_finished =>
deq_pri_entry_next <= DOB; -- store old_priority_entry
next_state_master <= SET_SCHED_PARAM_priority_field_check;
when SET_SCHED_PARAM_priority_field_check =>
-- update priority value to new_priority
lookup_entry_next <= set_priority(new_priority, lookup_entry);
-- FIXME: The following bunch of IF's could be replaced by a sig_case stmt where
-- the sigs are head==tail,lookup_id=head,lookup_id=tail
-- If (head_ptr = tail_ptr) then Q will now be empty
if ( get_tail_pointer(deq_pri_entry) = get_head_pointer(deq_pri_entry) ) then
-- Clear encoder bit for given priority
encoder_input_next <= set_encoder_bit('0', conv_integer(old_priority), encoder_input);
next_state_master <= SET_SCHED_PARAM_begin_add_to_new_pri_queue;
else -- If the Q will not be empty
-- If the head is being deq'd
if ( lookup_id = get_head_pointer(deq_pri_entry) ) then
-- Setup BRAM read of old head_ptr's entry
ADDRA <= '0' & get_head_pointer(deq_pri_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_old_head_ptr_idle;
-- If the tail is being deq'd
elsif ( lookup_id = get_tail_pointer(deq_pri_entry) ) then
-- Setup BRAM read of old tail_ptr's entry
ADDRA <= '0' & get_tail_pointer(deq_pri_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_old_tail_ptr_idle;
-- If an item in the "middle" of the list is being deq'd
else
-- Setup BRAM read of prev_ptr's entry
ADDRA <= '0' & get_prev_pointer(lookup_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_prev_ptr_idle;
end if;
end if;
when SET_SCHED_PARAM_lookup_old_head_ptr_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_old_head_ptr_finished;
when SET_SCHED_PARAM_lookup_old_head_ptr_finished =>
-- DOA has old head_ptr entry on it
deq_pri_entry_next <= set_head_pointer(get_next_pointer(DOA), deq_pri_entry);
next_state_master <= SET_SCHED_PARAM_write_back_deq_pri_entry;
when SET_SCHED_PARAM_lookup_old_tail_ptr_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_old_tail_ptr_finished;
when SET_SCHED_PARAM_lookup_old_tail_ptr_finished =>
-- DOA has old tail_ptr entry on it
deq_pri_entry_next <= set_tail_pointer(get_prev_pointer(DOA), deq_pri_entry);
next_state_master <= SET_SCHED_PARAM_write_back_deq_pri_entry;
when SET_SCHED_PARAM_lookup_prev_ptr_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_prev_ptr_finished;
when SET_SCHED_PARAM_lookup_prev_ptr_finished =>
-- DOA has prev_ptr entry on it
-- set next_ptr of prev_ptr to that of next_ptr of setpri_entry (AKA lookup_entry)
ADDRA <= '0' & get_prev_pointer(lookup_entry);
ENA <= '1';
WEA <= '1';
DIA <= set_next_pointer(get_next_pointer(lookup_entry),DOA);
next_state_master <= SET_SCHED_PARAM_begin_add_to_new_pri_queue;
when SET_SCHED_PARAM_write_back_deq_pri_entry =>
-- Write back old_priority entry (AKA deq_pri_entry)
ADDRB <= "00" & old_priority;
ENB <= '1';
WEB <= '1';
DIB <= deq_pri_entry;
next_state_master <= SET_SCHED_PARAM_begin_add_to_new_pri_queue;
when SET_SCHED_PARAM_begin_add_to_new_pri_queue =>
-- If the new priority Q is empty...
if ( is_encoder_bit_zero(conv_integer(new_priority), encoder_input)) then
-- update head_ptr to that of lookup_id (AKA setpri_ID)
enqueue_pri_entry_next <= set_head_pointer(lookup_id, enqueue_pri_entry);
-- set encoder input bit for new_priority to '1'
encoder_input_next <= set_encoder_bit('1', conv_integer(new_priority), encoder_input);
-- now update the tail_ptr to that of lookup_id (AKA setpri_ID)
next_state_master <= SET_SCHED_PARAM_init_tail_ptr;
else -- new priority Q is not empty
-- Setup read of old tail_ptr in new Q
ADDRA <= '0' & get_tail_pointer(enqueue_pri_entry);
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_enq_old_tail_ptr_idle;
end if;
when SET_SCHED_PARAM_init_tail_ptr =>
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
encoder_enable_next <= '1'; -- allow priority encoder to process, 1a
next_state_master <= SET_SCHED_PARAM_write_back_entries;
when SET_SCHED_PARAM_lookup_enq_old_tail_ptr_idle =>
-- idle stage
-- Change the prev_ptr of lookup_id (AKA setpri_ID) to that of old_tail_ptr
lookup_entry_next <= set_prev_pointer(get_tail_pointer(enqueue_pri_entry), lookup_entry);
next_state_master <= SET_SCHED_PARAM_update_enqueue_info;
when SET_SCHED_PARAM_update_enqueue_info =>
-- DOA has old tail_ptr info for new Q
-- Change & Write-back the old tail_ptr's next_ptr to that of lookup_id (AKA setpri_ID)
ADDRA <= '0' & get_tail_pointer(enqueue_pri_entry);
ENA <= '1';
WEA <= '1';
DIA <= set_next_pointer(lookup_id, DOA);
-- Update the tail_ptr of new priority Q to be that of lookup_id (AKA setpri_ID)
enqueue_pri_entry_next <= set_tail_pointer(lookup_id, enqueue_pri_entry);
encoder_enable_next <= '1'; -- allow priority encoder to process, 1b
next_state_master <= SET_SCHED_PARAM_write_back_entries;
when SET_SCHED_PARAM_write_back_entries =>
-- Write back lookup_entry (AKA setpri_entry)
ADDRA <= '0' & lookup_id;
ENA <= '1';
WEA <= '1';
DIA <= lookup_entry;
-- Write back enqueue_pri_entry (AKA new_priority_entry)
ADDRB <= "00" & new_priority;
ENB <= '1';
WEB <= '1';
DIB <= enqueue_pri_entry;
next_state_master <= SET_SCHED_PARAM_wait_for_encoder_0;
when SET_SCHED_PARAM_wait_for_encoder_0 =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_wait_for_encoder_1;
when SET_SCHED_PARAM_wait_for_encoder_1 =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_last_wait_0;
when SET_SCHED_PARAM_last_wait_0=>
-- idle stage
next_state_master <= SET_SCHED_PARAM_last_wait_1;
when SET_SCHED_PARAM_last_wait_1=>
-- idle stage
next_state_master <= SET_SCHED_PARAM_check_encoder;
when SET_SCHED_PARAM_check_encoder =>
-- Continue to find highest priority thread in the system...
ADDRB <= "00" & encoder_output; -- setup read of highest PRIORITY_DATA entry in system
ENB <= '1';
WEA <= '0';
ADDRA <= '0' & TM2SCH_current_cpu_tid_reg; -- setup read of currently running thread
ENA <= '1';
WEA <= '0';
next_state_master <= SET_SCHED_PARAM_lookup_highest_pri_entry_idle;
when SET_SCHED_PARAM_lookup_highest_pri_entry_idle =>
-- idle stage
next_state_master <= SET_SCHED_PARAM_lookup_highest_pri_entry_finished;
when SET_SCHED_PARAM_lookup_highest_pri_entry_finished =>
-- DOA has current thread entry
-- DOB has highest priority entry
current_entry_pri_value_next <= get_priority(DOA); -- store current_entry's priority
next_thread_id_next <= get_head_pointer(DOB); -- store next_thread_id
next_state_master <= SET_SCHED_PARAM_preemption_check;
when SET_SCHED_PARAM_preemption_check =>
-- Check if next_thread_id has "better" priority than the current_entry_pri_value
if( encoder_output < current_entry_pri_value ) then
Preemption_Interrupt_Line <= '1';
end if;
-- Late check for scheduling idle thread when encoder shows there are no
-- threads to schedule
if (encoder_input = 0) then
if (idle_thread_valid = '1') then
Next_Thread_Valid_next <= '1';
next_thread_id_next <= idle_thread_id;
else
Next_Thread_Valid_next <= '0';
end if;
else
-- There was data to process, so set thread valid
Next_Thread_Valid_next <= '1'; -- Assert that the next_thread is valid
end if;
Next_Thread_Valid_next <= '1'; -- Assert that the next_thread is valid
next_state_master <= SET_SCHED_PARAM_return_with_no_error; -- return to idle stage
when SET_SCHED_PARAM_return_with_error =>
ENA <= '0';
WEA <= '0';
debug_reg_next <= debug_reg(0 to 30) & '1';
bus_data_out <= Z32(0 to 27) & "0000"; -- return with error status (not possible with write op's, so just return all 0's)
bus_data_ready <= '1';
bus_ack_ready <= '1';
Next_Thread_Valid_next <= temp_valid; -- restore Next_Thread_Valid
next_state_master <= wait_trans_done;
when SET_SCHED_PARAM_return_with_no_error =>
ENA <= '0';
WEA <= '0';
debug_reg_next <= debug_reg(0 to 30) & '0';
bus_data_out <= Z32(0 to 27) & "0000"; -- return with successful status
bus_data_ready <= '1';
bus_ack_ready <= '1';
Next_Thread_Valid_next <= temp_valid; -- restore Next_Thread_Valid
next_state_master <= wait_trans_done;
----------------------------
-- SET_sched_param: end
----------------------------
----------------------------
-- GET_sched_param: begin
----------------------------
when GET_SCHED_PARAM_begin =>
lookup_id_next <= Bus2IP_Addr(16 to 23);
next_state_master <= GET_SCHED_PARAM_lookup_entry;
when GET_SCHED_PARAM_lookup_entry =>
ADDRU <= '0' & lookup_id; -- setup read from PARAM_DATA[tid]
ENU <= '1';
WEU <= '0';
next_state_master <= GET_SCHED_PARAM_lookup_entry_idle;
when GET_SCHED_PARAM_lookup_entry_idle =>
-- idle stage
next_state_master <= GET_SCHED_PARAM_lookup_entry_finished;
when GET_SCHED_PARAM_lookup_entry_finished =>
-- DOU has sched_param on it
bus_data_out <= DOU(0 to 31); -- return sched_param on bus and ACK
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- GET_sched_param: end
----------------------------
----------------------------
-- CHECK_sched_param: begin
----------------------------
when CHECK_SCHED_PARAM_begin =>
lookup_id_next <= Bus2IP_Addr(16 to 23);
next_state_master <= CHECK_SCHED_PARAM_lookup_entries;
when CHECK_SCHED_PARAM_lookup_entries =>
ADDRA <= '0' & lookup_id; -- Setup read from THREAD_DATA[tid]
ENA <= '1';
WEA <= '0';
ADDRU <= '0' & lookup_id; -- Setup read from PARAM_DATA[tid]
ENU <= '1';
WEU <= '0';
SWTM_ADDRB <= '0' & lookup_id; -- Setup read from SWTM_DATA[tid]
SWTM_ENB <= '1';
SWTM_WEB <= '0';
next_state_master <= CHECK_SCHED_PARAM_lookup_entries_idle;
when CHECK_SCHED_PARAM_lookup_entries_idle =>
-- idle stage
next_state_master <= CHECK_SCHED_PARAM_lookup_entries_finished;
when CHECK_SCHED_PARAM_lookup_entries_finished =>
-- DOA, DOU, and SWTM DOB have entries on them
-- Error check for properness of sched_param:
-- * If queued : sched_param must in the SW-valid range (less than 128)
-- * If not-queued : sched param can be in any range
if(get_queue_bit(DOA) = '1') then
-- thread is QUEUED
-- then check to see if Most Significant 25 bits of sched_param are 0's => in SW-valid range
case ( DOU(0 to 24) ) is
when "0000000000000000000000000" => -- SW-valid range, return all 0's
bus_data_out <= Z32(0 to 31);
when others => -- Not in SW-valid range, return LSB=1, error bit
bus_data_out <= Z32(0 to 30) & '1';
end case;
else
-- thread is ~QUEUED, return all 0's
bus_data_out <= Z32(0 to 31);
end if;
bus_data_ready <= '1'; -- ACK Bus, with data put on it
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- CHECK_sched_param: end
----------------------------
----------------------------
-- SET_IDLE_THREAD: begin
----------------------------
when SET_IDLE_THREAD_begin =>
lookup_id_next <= Bus2IP_Addr(16 to 23); -- store thread_id
ADDRA <= '0' & Bus2IP_Addr(16 to 23); -- setup BRAM read of THREAD_DATA[tid]
ENA <= '1';
WEA <= '0';
ADDRU <= '0' & Bus2IP_Addr(16 to 23); -- setup BRAM read of PARAM_DATA[tid]
ENU <= '1';
WEU <= '0';
SWTM_ADDRB <= '0' & Bus2IP_Addr(16 to 23); -- setup SWTM_BRAM read of thread_id to set_pri
SWTM_ENB <= '1';
SWTM_WEB <= '0';
next_state_master <= SET_IDLE_THREAD_lookup_entries_idle;
when SET_IDLE_THREAD_lookup_entries_idle =>
-- idle stage
next_state_master <= SET_IDLE_THREAD_lookup_entries_finished;
when SET_IDLE_THREAD_lookup_entries_finished =>
-- Check to see if this thread can become the idle thread
-- * TID must be ~queued
-- * TID must be created and used.
-- * TID must not have a HW sched param.
if ( get_queue_bit(DOA) = '0' and
SWTM_DOB(26) = '1' and
DOU(0 to 24) = "0000000000000000000000000"
) then
idle_thread_id_next <= lookup_id;
idle_thread_valid_next <= '1';
next_state_master <= SET_IDLE_THREAD_return_with_no_error;
else
-- This thread cannot become the idle thread
next_state_master <= SET_IDLE_THREAD_return_with_error;
end if;
when SET_IDLE_THREAD_return_with_error =>
bus_data_out <= Z32(0 to 30) & '1'; -- return LSB=1, error bit, on bus and ACK
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
when SET_IDLE_THREAD_return_with_no_error =>
-- FIXME: this if statement and body may not be needed (idle thread should be set up at all times)
-- If there is not a next thread ready to run, then make the newly set idle thread ready to run.
if (Next_Thread_Valid_reg = '0') then
Next_Thread_Valid_next <= '1';
next_thread_id_next <= idle_thread_id;
end if;
bus_data_out <= Z32(0 to 31); -- return all 0's on bus and ACK
bus_data_ready <= '1';
bus_ack_ready <= '1';
next_state_master <= wait_trans_done;
----------------------------
-- SET_IDLE_THREAD: end
----------------------------
when others =>
ENA <= '0'; -- turn off any BRAM access
WEA <= '0';
ENB <= '0';
WEB <= '0';
ENU <= '0';
WEU <= '0';
next_state_master <= idle;
end case; -- END CASE (current_state_master)
end process MASTER_FSM_LOGIC_PROC;
end architecture IMP;
| bsd-3-clause | 73fa38c1a147ae2a22daf0586fbef205 | 0.560501 | 3.343646 | false | false | false | false |
pdaxrom/p601zero | cpu68.vhd | 1 | 132,518 | --===========================================================================--
--
-- S Y N T H E Z I A B L E CPU68 C O R E
--
-- www.OpenCores.Org - December 2002
-- This core adheres to the GNU public license
--
-- File name : cpu68.vhd
--
-- Purpose : Implements a 6800 compatible CPU core with some
-- additional instructions found in the 6801
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
--===========================================================================----
--
-- Revision History:
--
-- Date: Revision Author
-- 22 Sep 2002 0.1 John Kent
--
-- 30 Oct 2002 0.2 John Kent
-- made NMI edge triggered
--
-- 30 Oct 2002 0.3 John Kent
-- more corrections to NMI
-- added wai_wait_state to prevent stack overflow on wai.
--
-- 1 Nov 2002 0.4 John Kent
-- removed WAI states and integrated WAI with the interrupt service routine
-- replace Data out (do) and Data in (di) register with a single Memory Data (md) reg.
-- Added Multiply instruction states.
-- run ALU and CC out of CPU module for timing measurements.
--
-- 3 Nov 2002 0.5 John Kent
-- Memory Data Register was not loaded on Store instructions
-- SEV and CLV were not defined in the ALU
-- Overflow Flag on NEG was incorrect
--
-- 16th Feb 2003 0.6 John Kent
-- Rearranged the execution cycle for dual operand instructions
-- so that occurs during the following fetch cycle.
-- This allows the reduction of one clock cycle from dual operand
-- instruction. Note that this also necessitated re-arranging the
-- program counter so that it is no longer incremented in the ALU.
-- The effective address has also been re-arranged to include a
-- separate added. The STD (store accd) now sets the condition codes.
--
-- 28th Jun 2003 0.7 John Kent
-- Added Hold and Halt signals. Hold is used to steal cycles from the
-- CPU or add wait states. Halt puts the CPU in the inactive state
-- and is only honoured in the fetch cycle. Both signals are active high.
--
-- 9th Jan 2004 0.8 John Kent
-- Clear instruction did an alu_ld8 rather than an alu_clr, so
-- the carry bit was not cleared correctly.
-- This error was picked up by Michael Hassenfratz.
--
-- 13th May 2017 0.8 Alexander Chukov
-- Added XGDX instruction from HD6301
--
--
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cpu68 is
port (
clk: in std_logic;
rst: in std_logic;
rw: out std_logic;
vma: out std_logic;
address: out std_logic_vector(15 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
hold: in std_logic;
halt: in std_logic;
irq: in std_logic;
nmi: in std_logic
-- test_alu: out std_logic_vector(15 downto 0);
-- test_cc: out std_logic_vector(7 downto 0)
);
end;
architecture CPU_ARCH of cpu68 is
constant SBIT : integer := 7;
constant XBIT : integer := 6;
constant HBIT : integer := 5;
constant IBIT : integer := 4;
constant NBIT : integer := 3;
constant ZBIT : integer := 2;
constant VBIT : integer := 1;
constant CBIT : integer := 0;
type state_type is (reset_state, fetch_state, decode_state,
extended_state, indexed_state, read8_state, read16_state, immediate16_state,
write8_state, write16_state,
execute_state, halt_state, error_state,
mul_state, mulea_state, muld_state,
mul0_state, mul1_state, mul2_state, mul3_state,
mul4_state, mul5_state, mul6_state, mul7_state,
jmp_state, jsr_state, jsr1_state,
branch_state, bsr_state, bsr1_state,
rts_hi_state, rts_lo_state,
int_pcl_state, int_pch_state,
int_ixl_state, int_ixh_state,
int_cc_state, int_acca_state, int_accb_state,
int_wai_state, int_mask_state,
rti_state, rti_cc_state, rti_acca_state, rti_accb_state,
rti_ixl_state, rti_ixh_state,
rti_pcl_state, rti_pch_state,
pula_state, psha_state, pulb_state, pshb_state,
pulx_lo_state, pulx_hi_state, pshx_lo_state, pshx_hi_state,
vect_lo_state, vect_hi_state );
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, push_ad, pull_ad, int_hi_ad, int_lo_ad );
type dout_type is (md_lo_dout, md_hi_dout, acca_dout, accb_dout, ix_lo_dout, ix_hi_dout, cc_dout, pc_lo_dout, pc_hi_dout );
type op_type is (reset_op, fetch_op, latch_op );
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca, load_right_hi_acca );
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb, load_right_lo_accb );
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
type sp_type is (reset_sp, latch_sp, load_sp );
type pc_type is (reset_pc, latch_pc, load_ea_pc, add_ea_pc, pull_lo_pc, pull_hi_pc, inc_pc );
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
type ea_type is (reset_ea, latch_ea, add_ix_ea, load_accb_ea, inc_ea, fetch_first_ea, fetch_next_ea );
type iv_type is (reset_iv, latch_iv, swi_iv, nmi_iv, irq_iv );
type nmi_type is (reset_nmi, set_nmi, latch_nmi );
type left_type is (acca_left, accb_left, accd_left, md_left, ix_left, sp_left );
type right_type is (md_right, zero_right, plus_one_right, accb_right, ix_right );
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
alu_inx, alu_dex, alu_cpx,
alu_lsr16, alu_lsl16,
alu_ror8, alu_rol8,
alu_asr8, alu_asl8, alu_lsr8,
alu_sei, alu_cli, alu_sec, alu_clc, alu_sev, alu_clv, alu_tpa, alu_tap,
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_nop, alu_daa);
signal op_code: std_logic_vector(7 downto 0);
signal acca: std_logic_vector(7 downto 0);
signal accb: std_logic_vector(7 downto 0);
signal cc: std_logic_vector(7 downto 0);
signal cc_out: std_logic_vector(7 downto 0);
signal xreg: std_logic_vector(15 downto 0);
signal sp: std_logic_vector(15 downto 0);
signal ea: std_logic_vector(15 downto 0);
signal pc: std_logic_vector(15 downto 0);
signal md: std_logic_vector(15 downto 0);
signal left: std_logic_vector(15 downto 0);
signal right: std_logic_vector(15 downto 0);
signal out_alu: std_logic_vector(15 downto 0);
signal iv: std_logic_vector(1 downto 0);
signal nmi_req: std_logic;
signal nmi_ack: std_logic;
signal state: state_type;
signal next_state: state_type;
signal pc_ctrl: pc_type;
signal ea_ctrl: ea_type;
signal op_ctrl: op_type;
signal md_ctrl: md_type;
signal acca_ctrl: acca_type;
signal accb_ctrl: accb_type;
signal ix_ctrl: ix_type;
signal cc_ctrl: cc_type;
signal sp_ctrl: sp_type;
signal iv_ctrl: iv_type;
signal left_ctrl: left_type;
signal right_ctrl: right_type;
signal alu_ctrl: alu_type;
signal addr_ctrl: addr_type;
signal dout_ctrl: dout_type;
signal nmi_ctrl: nmi_type;
begin
----------------------------------
--
-- Address bus multiplexer
--
----------------------------------
addr_mux: process( clk, addr_ctrl, pc, ea, sp, iv )
begin
case addr_ctrl is
when idle_ad =>
address <= "1111111111111111";
vma <= '0';
rw <= '1';
when fetch_ad =>
address <= pc;
vma <= '1';
rw <= '1';
when read_ad =>
address <= ea;
vma <= '1';
rw <= '1';
when write_ad =>
address <= ea;
vma <= '1';
rw <= '0';
when push_ad =>
address <= sp;
vma <= '1';
rw <= '0';
when pull_ad =>
address <= sp;
vma <= '1';
rw <= '1';
when int_hi_ad =>
address <= "1111111111111" & iv & "0";
vma <= '1';
rw <= '1';
when int_lo_ad =>
address <= "1111111111111" & iv & "1";
vma <= '1';
rw <= '1';
when others =>
address <= "1111111111111111";
vma <= '0';
rw <= '1';
end case;
end process;
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process( clk, dout_ctrl, md, acca, accb, xreg, pc, cc )
begin
case dout_ctrl is
when md_hi_dout => -- alu output
data_out <= md(15 downto 8);
when md_lo_dout =>
data_out <= md(7 downto 0);
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when ix_lo_dout => -- index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- index reg
data_out <= xreg(15 downto 8);
when cc_dout => -- condition codes
data_out <= cc;
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
when others =>
data_out <= "00000000";
end case;
end process;
----------------------------------
--
-- Program Counter Control
--
----------------------------------
pc_mux: process( clk, pc_ctrl, pc, out_alu, data_in, ea, hold )
variable tempof : std_logic_vector(15 downto 0);
variable temppc : std_logic_vector(15 downto 0);
begin
case pc_ctrl is
when add_ea_pc =>
if ea(7) = '0' then
tempof := "00000000" & ea(7 downto 0);
else
tempof := "11111111" & ea(7 downto 0);
end if;
when inc_pc =>
tempof := "0000000000000001";
when others =>
tempof := "0000000000000000";
end case;
case pc_ctrl is
when reset_pc =>
temppc := "1111111111111110";
when load_ea_pc =>
temppc := ea;
when pull_lo_pc =>
temppc(7 downto 0) := data_in;
temppc(15 downto 8) := pc(15 downto 8);
when pull_hi_pc =>
temppc(7 downto 0) := pc(7 downto 0);
temppc(15 downto 8) := data_in;
when others =>
temppc := pc;
end case;
if clk'event and clk = '0' then
if hold = '1' then
pc <= pc;
else
pc <= temppc + tempof;
end if;
end if;
end process;
----------------------------------
--
-- Effective Address Control
--
----------------------------------
ea_mux: process( clk, ea_ctrl, ea, out_alu, data_in, accb, xreg, hold )
variable tempind : std_logic_vector(15 downto 0);
variable tempea : std_logic_vector(15 downto 0);
begin
case ea_ctrl is
when add_ix_ea =>
tempind := "00000000" & ea(7 downto 0);
when inc_ea =>
tempind := "0000000000000001";
when others =>
tempind := "0000000000000000";
end case;
case ea_ctrl is
when reset_ea =>
tempea := "0000000000000000";
when load_accb_ea =>
tempea := "00000000" & accb(7 downto 0);
when add_ix_ea =>
tempea := xreg;
when fetch_first_ea =>
tempea(7 downto 0) := data_in;
tempea(15 downto 8) := "00000000";
when fetch_next_ea =>
tempea(7 downto 0) := data_in;
tempea(15 downto 8) := ea(7 downto 0);
when others =>
tempea := ea;
end case;
if clk'event and clk = '0' then
if hold = '1' then
ea <= ea;
else
ea <= tempea + tempind;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator A
--
--------------------------------
acca_mux : process( clk, acca_ctrl, out_alu, acca, data_in, hold, right )
begin
if clk'event and clk = '0' then
if hold = '1' then
acca <= acca;
else
case acca_ctrl is
when reset_acca =>
acca <= "00000000";
when load_acca =>
acca <= out_alu(7 downto 0);
when load_hi_acca =>
acca <= out_alu(15 downto 8);
when pull_acca =>
acca <= data_in;
when load_right_hi_acca =>
acca <= right(15 downto 8);
when others =>
-- when latch_acca =>
acca <= acca;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator B
--
--------------------------------
accb_mux : process( clk, accb_ctrl, out_alu, accb, data_in, hold, right )
begin
if clk'event and clk = '0' then
if hold = '1' then
accb <= accb;
else
case accb_ctrl is
when reset_accb =>
accb <= "00000000";
when load_accb =>
accb <= out_alu(7 downto 0);
when pull_accb =>
accb <= data_in;
when load_right_lo_accb =>
accb <= right(7 downto 0);
when others =>
-- when latch_accb =>
accb <= accb;
end case;
end if;
end if;
end process;
--------------------------------
--
-- X Index register
--
--------------------------------
ix_mux : process( clk, ix_ctrl, out_alu, xreg, data_in, hold )
begin
if clk'event and clk = '0' then
if hold = '1' then
xreg <= xreg;
else
case ix_ctrl is
when reset_ix =>
xreg <= "0000000000000000";
when load_ix =>
xreg <= out_alu(15 downto 0);
when pull_hi_ix =>
xreg(15 downto 8) <= data_in;
when pull_lo_ix =>
xreg(7 downto 0) <= data_in;
when others =>
-- when latch_ix =>
xreg <= xreg;
end case;
end if;
end if;
end process;
--------------------------------
--
-- stack pointer
--
--------------------------------
sp_mux : process( clk, sp_ctrl, out_alu, hold )
begin
if clk'event and clk = '0' then
if hold = '1' then
sp <= sp;
else
case sp_ctrl is
when reset_sp =>
sp <= "0000000000000000";
when load_sp =>
sp <= out_alu(15 downto 0);
when others =>
-- when latch_sp =>
sp <= sp;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Memory Data
--
--------------------------------
md_mux : process( clk, md_ctrl, out_alu, data_in, md, hold )
begin
if clk'event and clk = '0' then
if hold = '1' then
md <= md;
else
case md_ctrl is
when reset_md =>
md <= "0000000000000000";
when load_md =>
md <= out_alu(15 downto 0);
when fetch_first_md =>
md(15 downto 8) <= "00000000";
md(7 downto 0) <= data_in;
when fetch_next_md =>
md(15 downto 8) <= md(7 downto 0);
md(7 downto 0) <= data_in;
when shiftl_md =>
md(15 downto 1) <= md(14 downto 0);
md(0) <= '0';
when others =>
-- when latch_md =>
md <= md;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Condition Codes
--
----------------------------------
cc_mux: process( clk, cc_ctrl, cc_out, cc, data_in, hold )
begin
if clk'event and clk = '0' then
if hold = '1' then
cc <= cc;
else
case cc_ctrl is
when reset_cc =>
cc <= "11000000";
when load_cc =>
cc <= cc_out;
when pull_cc =>
cc <= data_in;
when others =>
-- when latch_cc =>
cc <= cc;
end case;
end if;
end if;
end process;
----------------------------------
--
-- interrupt vector
--
----------------------------------
iv_mux: process( clk, iv_ctrl, hold )
begin
if clk'event and clk = '0' then
if hold = '1' then
iv <= iv;
else
case iv_ctrl is
when reset_iv =>
iv <= "11";
when nmi_iv =>
iv <= "10";
when swi_iv =>
iv <= "01";
when irq_iv =>
iv <= "00";
when others =>
iv <= iv;
end case;
end if;
end if;
end process;
----------------------------------
--
-- op code fetch
--
----------------------------------
op_fetch: process( clk, data_in, op_ctrl, op_code, hold )
begin
if clk'event and clk = '0' then
if hold = '1' then
op_code <= op_code;
else
case op_ctrl is
when reset_op =>
op_code <= "00000001"; -- nop
when fetch_op =>
op_code <= data_in;
when others =>
-- when latch_op =>
op_code <= op_code;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Left Mux
--
----------------------------------
left_mux: process( left_ctrl, acca, accb, xreg, sp, pc, ea, md )
begin
case left_ctrl is
when acca_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= acca;
when accb_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= accb;
when accd_left =>
left(15 downto 8) <= acca;
left(7 downto 0) <= accb;
when ix_left =>
left <= xreg;
when sp_left =>
left <= sp;
when others =>
-- when md_left =>
left <= md;
end case;
end process;
----------------------------------
--
-- Right Mux
--
----------------------------------
right_mux: process( right_ctrl, data_in, md, accb, ea, xreg )
begin
case right_ctrl is
when zero_right =>
right <= "0000000000000000";
when plus_one_right =>
right <= "0000000000000001";
when accb_right =>
right <= "00000000" & accb;
when ix_right =>
right <= xreg;
when others =>
-- when md_right =>
right <= md;
end case;
end process;
----------------------------------
--
-- Arithmetic Logic Unit
--
----------------------------------
mux_alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
variable valid_lo, valid_hi : boolean;
variable carry_in : std_logic;
variable daa_reg : std_logic_vector(7 downto 0);
begin
case alu_ctrl is
when alu_adc | alu_sbc |
alu_rol8 | alu_ror8 =>
carry_in := cc(CBIT);
when others =>
carry_in := '0';
end case;
valid_lo := left(3 downto 0) <= 9;
valid_hi := left(7 downto 4) <= 9;
if (cc(CBIT) = '0') then
if( cc(HBIT) = '1' ) then
if valid_hi then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
else
if valid_lo then
if valid_hi then
daa_reg := "00000000";
else
daa_reg := "01100000";
end if;
else
if( left(7 downto 4) <= 8 ) then
daa_reg := "00000110";
else
daa_reg := "01100110";
end if;
end if;
end if;
else
if ( cc(HBIT) = '1' )then
daa_reg := "01100110";
else
if valid_lo then
daa_reg := "01100000";
else
daa_reg := "01100110";
end if;
end if;
end if;
case alu_ctrl is
when alu_add8 | alu_inc |
alu_add16 | alu_inx |
alu_adc =>
out_alu <= left + right + ("000000000000000" & carry_in);
when alu_sub8 | alu_dec |
alu_sub16 | alu_dex |
alu_sbc | alu_cpx =>
out_alu <= left - right - ("000000000000000" & carry_in);
when alu_and =>
out_alu <= left and right; -- and/bit
when alu_ora =>
out_alu <= left or right; -- or
when alu_eor =>
out_alu <= left xor right; -- eor/xor
when alu_lsl16 | alu_asl8 | alu_rol8 =>
out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16
when alu_lsr16 | alu_lsr8 =>
out_alu <= carry_in & left(15 downto 1); -- lsr
when alu_ror8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror
when alu_asr8 =>
out_alu <= "00000000" & left(7) & left(7 downto 1); -- asr
when alu_neg =>
out_alu <= right - left; -- neg (right=0)
when alu_com =>
out_alu <= not left;
when alu_clr | alu_ld8 | alu_ld16 =>
out_alu <= right; -- clr, ld
when alu_st8 | alu_st16 =>
out_alu <= left;
when alu_daa =>
out_alu <= left + ("00000000" & daa_reg);
when alu_tpa =>
out_alu <= "00000000" & cc;
when others =>
out_alu <= left; -- nop
end case;
--
-- carry bit
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(CBIT) <= (left(7) and right(7)) or
(left(7) and not out_alu(7)) or
(right(7) and not out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(CBIT) <= ((not left(7)) and right(7)) or
((not left(7)) and out_alu(7)) or
(right(7) and out_alu(7));
when alu_add16 =>
cc_out(CBIT) <= (left(15) and right(15)) or
(left(15) and not out_alu(15)) or
(right(15) and not out_alu(15));
when alu_sub16 =>
cc_out(CBIT) <= ((not left(15)) and right(15)) or
((not left(15)) and out_alu(15)) or
(right(15) and out_alu(15));
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
cc_out(CBIT) <= left(0);
when alu_rol8 | alu_asl8 =>
cc_out(CBIT) <= left(7);
when alu_lsl16 =>
cc_out(CBIT) <= left(15);
when alu_com =>
cc_out(CBIT) <= '1';
when alu_neg | alu_clr =>
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
when alu_daa =>
if ( daa_reg(7 downto 4) = "0110" ) then
cc_out(CBIT) <= '1';
else
cc_out(CBIT) <= '0';
end if;
when alu_sec =>
cc_out(CBIT) <= '1';
when alu_clc =>
cc_out(CBIT) <= '0';
when alu_tap =>
cc_out(CBIT) <= left(CBIT);
when others => -- carry is not affected by cpx
cc_out(CBIT) <= cc(CBIT);
end case;
--
-- Zero flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_inc | alu_dec |
alu_neg | alu_com | alu_clr |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_ld8 | alu_st8 =>
cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_inx | alu_dex |
alu_ld16 | alu_st16 | alu_cpx =>
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_tap =>
cc_out(ZBIT) <= left(ZBIT);
when others =>
cc_out(ZBIT) <= cc(ZBIT);
end case;
--
-- negative flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
alu_ld8 | alu_st8 =>
cc_out(NBIT) <= out_alu(7);
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 | alu_cpx =>
cc_out(NBIT) <= out_alu(15);
when alu_tap =>
cc_out(NBIT) <= left(NBIT);
when others =>
cc_out(NBIT) <= cc(NBIT);
end case;
--
-- Interrupt mask flag
--
case alu_ctrl is
when alu_sei =>
cc_out(IBIT) <= '1'; -- set interrupt mask
when alu_cli =>
cc_out(IBIT) <= '0'; -- clear interrupt mask
when alu_tap =>
cc_out(IBIT) <= left(IBIT);
when others =>
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
end case;
--
-- Half Carry flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(HBIT) <= (left(3) and right(3)) or
(right(3) and not out_alu(3)) or
(left(3) and not out_alu(3));
when alu_tap =>
cc_out(HBIT) <= left(HBIT);
when others =>
cc_out(HBIT) <= cc(HBIT);
end case;
--
-- Overflow flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
((not left(7)) and (not right(7)) and out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
((not left(7)) and right(7) and out_alu(7));
when alu_add16 =>
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
((not left(15)) and (not right(15)) and out_alu(15));
when alu_sub16 | alu_cpx =>
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
((not left(15)) and right(15) and out_alu(15));
when alu_inc =>
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
left(3) and left(2) and left(1) and left(0));
when alu_dec | alu_neg =>
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
when alu_asr8 =>
cc_out(VBIT) <= left(0) xor left(7);
when alu_lsr8 | alu_lsr16 =>
cc_out(VBIT) <= left(0);
when alu_ror8 =>
cc_out(VBIT) <= left(0) xor cc(CBIT);
when alu_lsl16 =>
cc_out(VBIT) <= left(15) xor left(14);
when alu_rol8 | alu_asl8 =>
cc_out(VBIT) <= left(7) xor left(6);
when alu_tap =>
cc_out(VBIT) <= left(VBIT);
when alu_and | alu_ora | alu_eor | alu_com |
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 |
alu_clv =>
cc_out(VBIT) <= '0';
when alu_sev =>
cc_out(VBIT) <= '1';
when others =>
cc_out(VBIT) <= cc(VBIT);
end case;
case alu_ctrl is
when alu_tap =>
cc_out(XBIT) <= cc(XBIT) and left(XBIT);
cc_out(SBIT) <= left(SBIT);
when others =>
cc_out(XBIT) <= cc(XBIT) and left(XBIT);
cc_out(SBIT) <= cc(SBIT);
end case;
-- test_alu <= out_alu;
-- test_cc <= cc_out;
end process;
------------------------------------
--
-- Detect Edge of NMI interrupt
--
------------------------------------
nmi_handler : process( clk, rst, nmi, nmi_ack )
begin
if clk'event and clk='0' then
if hold = '1' then
nmi_req <= nmi_req;
else
if rst='1' then
nmi_req <= '0';
else
if (nmi='1') and (nmi_ack='0') then
nmi_req <= '1';
else
if (nmi='0') and (nmi_ack='1') then
nmi_req <= '0';
else
nmi_req <= nmi_req;
end if;
end if;
end if;
end if;
end if;
end process;
------------------------------------
--
-- Nmi mux
--
------------------------------------
nmi_mux: process( clk, nmi_ctrl, nmi_ack, hold )
begin
if clk'event and clk='0' then
if hold = '1' then
nmi_ack <= nmi_ack;
else
case nmi_ctrl is
when set_nmi =>
nmi_ack <= '1';
when reset_nmi =>
nmi_ack <= '0';
when others =>
-- when latch_nmi =>
nmi_ack <= nmi_ack;
end case;
end if;
end if;
end process;
------------------------------------
--
-- state sequencer
--
------------------------------------
process( state, op_code, cc, ea, irq, nmi_req, nmi_ack, hold, halt )
begin
case state is
when reset_state => -- released from reset
-- reset the registers
op_ctrl <= reset_op;
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
ix_ctrl <= reset_ix;
sp_ctrl <= reset_sp;
pc_ctrl <= reset_pc;
ea_ctrl <= reset_ea;
md_ctrl <= reset_md;
iv_ctrl <= reset_iv;
nmi_ctrl <= reset_nmi;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= reset_cc;
-- idle the bus
dout_ctrl <= md_lo_dout;
addr_ctrl <= idle_ad;
next_state <= vect_hi_state;
--
-- Jump via interrupt vector
-- iv holds interrupt type
-- fetch PC hi from vector location
--
when vect_hi_state =>
-- default the registers
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- fetch pc low interrupt vector
pc_ctrl <= pull_hi_pc;
addr_ctrl <= int_hi_ad;
dout_ctrl <= pc_hi_dout;
next_state <= vect_lo_state;
--
-- jump via interrupt vector
-- iv holds vector type
-- fetch PC lo from vector location
--
when vect_lo_state =>
-- default the registers
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
iv_ctrl <= latch_iv;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- fetch the vector low byte
pc_ctrl <= pull_lo_pc;
addr_ctrl <= int_lo_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
--
-- Here to fetch an instruction
-- PC points to opcode
-- Should service interrupt requests at this point
-- either from the timer
-- or from the external input.
--
when fetch_state =>
case op_code(7 downto 4) is
when "0000" |
"0001" |
"0010" | -- branch conditional
"0011" |
"0100" | -- acca single op
"0101" | -- accb single op
"0110" | -- indexed single op
"0111" => -- extended single op
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1000" | -- acca immediate
"1001" | -- acca direct
"1010" | -- acca indexed
"1011" => -- acca extended
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0011" => -- subd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1100" => -- cpx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_cpx;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1101" => -- bsr / jsr
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1110" => -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when others =>
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
end case;
when "1100" | -- accb immediate
"1101" | -- accb direct
"1110" | -- accb indexed
"1111" => -- accb extended
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when "1110" => -- ldx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= load_ix;
sp_ctrl <= latch_sp;
when "1111" => -- stx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
when others =>
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
end case;
when others =>
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
end case;
md_ctrl <= latch_md;
-- fetch the op code
op_ctrl <= fetch_op;
ea_ctrl <= reset_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
iv_ctrl <= latch_iv;
if halt = '1' then
pc_ctrl <= latch_pc;
nmi_ctrl <= latch_nmi;
next_state <= halt_state;
-- service non maskable interrupts
elsif (nmi_req = '1') and (nmi_ack = '0') then
pc_ctrl <= latch_pc;
nmi_ctrl <= set_nmi;
next_state <= int_pcl_state;
-- service maskable interrupts
else
--
-- nmi request is not cleared until nmi input goes low
--
if(nmi_req = '0') and (nmi_ack='1') then
nmi_ctrl <= reset_nmi;
else
nmi_ctrl <= latch_nmi;
end if;
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
pc_ctrl <= latch_pc;
next_state <= int_pcl_state;
else
-- Advance the PC to fetch next instruction byte
pc_ctrl <= inc_pc;
next_state <= decode_state;
end if;
end if;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode_state =>
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
iv_ctrl <= latch_iv;
case op_code(7 downto 4) is
when "0000" =>
md_ctrl <= fetch_first_md;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
when "0001" => -- nop
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "0100" => -- lsrd
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
when "0101" => -- lsld
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsl16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
ix_ctrl <= latch_ix;
when "0110" => -- tap
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tap;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "0111" => -- tpa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tpa;
cc_ctrl <= latch_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1000" => -- inx
left_ctrl <= ix_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_inx;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= load_ix;
when "1001" => -- dex
left_ctrl <= ix_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_dex;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= load_ix;
when "1010" => -- clv
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clv;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1011" => -- sev
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sev;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1100" => -- clc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clc;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1101" => -- sec
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sec;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1110" => -- cli
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_cli;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when "1111" => -- sei
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
end case;
next_state <= fetch_state;
-- acca / accb inherent instructions
when "0001" =>
md_ctrl <= fetch_first_md;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
left_ctrl <= acca_left;
right_ctrl <= accb_right;
case op_code(3 downto 0) is
when "0000" => -- sba
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
when "0001" => -- cba
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
when "0110" => -- tab
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= load_accb;
when "0111" => -- tba
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
when "1000" => -- xgdx
left_ctrl <= accd_left;
right_ctrl <= ix_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
ix_ctrl <= load_ix;
acca_ctrl <= load_right_hi_acca;
accb_ctrl <= load_right_lo_accb;
when "1001" => -- daa
alu_ctrl <= alu_daa;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
when "1011" => -- aba
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
accb_ctrl <= latch_accb;
when others =>
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end case;
next_state <= fetch_state;
when "0010" => -- branch conditional
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- increment the pc
pc_ctrl <= inc_pc;
case op_code(3 downto 0) is
when "0000" => -- bra
next_state <= branch_state;
when "0001" => -- brn
next_state <= fetch_state;
when "0010" => -- bhi
if (cc(CBIT) or cc(ZBIT)) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0011" => -- bls
if (cc(CBIT) or cc(ZBIT)) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0100" => -- bcc/bhs
if cc(CBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0101" => -- bcs/blo
if cc(CBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0110" => -- bne
if cc(ZBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "0111" => -- beq
if cc(ZBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1000" => -- bvc
if cc(VBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1001" => -- bvs
if cc(VBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1010" => -- bpl
if cc(NBIT) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1011" => -- bmi
if cc(NBIT) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1100" => -- bge
if (cc(NBIT) xor cc(VBIT)) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1101" => -- blt
if (cc(NBIT) xor cc(VBIT)) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1110" => -- bgt
if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when "1111" => -- ble
if (cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1' then
next_state <= branch_state;
else
next_state <= fetch_state;
end if;
when others =>
next_state <= fetch_state;
end case;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
case op_code(3 downto 0) is
when "0000" => -- tsx
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= load_ix;
sp_ctrl <= latch_sp;
next_state <= fetch_state;
when "0001" => -- ins
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0010" => -- pula
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= pula_state;
when "0011" => -- pulb
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= pulb_state;
when "0100" => -- des
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0101" => -- txs
left_ctrl <= ix_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= fetch_state;
when "0110" => -- psha
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= psha_state;
when "0111" => -- pshb
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= pshb_state;
when "1000" => -- pulx
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= pulx_hi_state;
when "1001" => -- rts
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= rts_hi_state;
when "1010" => -- abx
left_ctrl <= ix_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= load_ix;
sp_ctrl <= latch_sp;
next_state <= fetch_state;
when "1011" => -- rti
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= load_sp;
next_state <= rti_cc_state;
when "1100" => -- pshx
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= pshx_lo_state;
when "1101" => -- mul
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= mul_state;
when "1110" => -- wai
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= int_pcl_state;
when "1111" => -- swi
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= int_pcl_state;
when others =>
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
next_state <= fetch_state;
end case;
--
-- Accumulator A Single operand
-- source = Acc A dest = Acc A
-- Do not advance PC
--
when "0100" => -- acca single op
md_ctrl <= fetch_first_md;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
left_ctrl <= acca_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= plus_one_right;
alu_ctrl <= alu_dec;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= plus_one_right;
alu_ctrl <= alu_inc;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
acca_ctrl <= latch_acca;
cc_ctrl <= load_cc;
when "1110" => -- jmp
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
end case;
next_state <= fetch_state;
--
-- single operand acc b
-- Do not advance PC
--
when "0101" =>
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
pc_ctrl <= latch_pc;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
left_ctrl <= accb_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= plus_one_right;
alu_ctrl <= alu_dec;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= plus_one_right;
alu_ctrl <= alu_inc;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
when "1110" => -- jmp
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
end case;
next_state <= fetch_state;
--
-- Single operand indexed
-- Two byte instruction so advance PC
-- EA should hold index offset
--
when "0110" => -- indexed single op
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= inc_pc;
next_state <= indexed_state;
--
-- Single operand extended addressing
-- three byte instruction so advance the PC
-- Low order EA holds high order address
--
when "0111" => -- extended single op
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= inc_pc;
next_state <= extended_state;
when "1000" => -- acca immediate
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= inc_pc;
case op_code(3 downto 0) is
when "0011" | -- subdd #
"1100" | -- cpx #
"1110" => -- lds #
next_state <= immediate16_state;
when "1101" => -- bsr
next_state <= bsr_state;
when others =>
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
pc_ctrl <= inc_pc;
case op_code(3 downto 0) is
when "0111" => -- staa direct
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1111" => -- sts direct
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1101" => -- jsr direct
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= jsr_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= read8_state;
end case;
when "1010" => -- acca indexed
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= inc_pc;
next_state <= indexed_state;
when "1011" => -- acca extended
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= inc_pc;
next_state <= extended_state;
when "1100" => -- accb immediate
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= inc_pc;
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
"1110" => -- ldx #
next_state <= immediate16_state;
when others =>
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
pc_ctrl <= inc_pc;
case op_code(3 downto 0) is
when "0111" => -- stab direct
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std direct
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx direct
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
next_state <= read8_state;
end case;
when "1110" => -- accb indexed
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= inc_pc;
next_state <= indexed_state;
when "1111" => -- accb extended
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- increment the pc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= inc_pc;
next_state <= extended_state;
when others =>
md_ctrl <= fetch_first_md;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
-- idle the pc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= latch_pc;
next_state <= fetch_state;
end case;
when immediate16_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
op_ctrl <= latch_op;
iv_ctrl <= latch_iv;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment pc
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= inc_pc;
-- fetch next immediate byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
--
-- ea holds 8 bit index offet
-- calculate the effective memory address
-- using the alu
--
when indexed_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- calculate effective address from index reg
-- index offest is not sign extended
ea_ctrl <= add_ix_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
-- work out next state
case op_code(7 downto 4) is
when "0110" => -- single op indexed
md_ctrl <= latch_md;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
case op_code(3 downto 0) is
when "1011" => -- undefined
next_state <= fetch_state;
when "1110" => -- jmp
next_state <= jmp_state;
when others =>
next_state <= read8_state;
end case;
when "1010" => -- acca indexed
case op_code(3 downto 0) is
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- jsr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jsr_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1110" => -- accb indexed
case op_code(3 downto 0) is
when "0111" => -- stab direct
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std direct
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx direct
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when others =>
md_ctrl <= latch_md;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
next_state <= fetch_state;
end case;
--
-- ea holds the low byte of the absolute address
-- Move ea low byte into ea high byte
-- load new ea low byte to for absolute 16 bit address
-- advance the program counter
--
when extended_state => -- fetch ea low byte
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- increment pc
pc_ctrl <= inc_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
-- work out the next state
case op_code(7 downto 4) is
when "0111" => -- single op extended
md_ctrl <= latch_md;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
case op_code(3 downto 0) is
when "1011" => -- undefined
next_state <= fetch_state;
when "1110" => -- jmp
next_state <= jmp_state;
when others =>
next_state <= read8_state;
end case;
when "1011" => -- acca extended
case op_code(3 downto 0) is
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- jsr
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= jsr_state;
when "1111" => -- sts
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when "1111" => -- accb extended
case op_code(3 downto 0) is
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when "1111" => -- stx
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= read8_state;
end case;
when others =>
md_ctrl <= latch_md;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte (direct page)
-- can enter here from extended addressing
-- read memory location
-- note that reads may be 8 or 16 bits
--
when read8_state => -- read data
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
--
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
when "0110" | "0111" => -- single operand
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
ea_ctrl <= latch_ea;
next_state <= execute_state;
when "1001" | "1010" | "1011" => -- acca
case op_code(3 downto 0) is
when "0011" | -- subd
"1110" | -- lds
"1100" => -- cpx
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
-- increment the effective address in case of 16 bit load
ea_ctrl <= inc_ea;
next_state <= read16_state;
-- when "0111" => -- staa
-- left_ctrl <= acca_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_st8;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= load_md;
-- ea_ctrl <= latch_ea;
-- next_state <= write8_state;
-- when "1101" => -- jsr
-- left_ctrl <= acca_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_nop;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= latch_md;
-- ea_ctrl <= latch_ea;
-- next_state <= jsr_state;
-- when "1111" => -- sts
-- left_ctrl <= sp_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_st16;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= load_md;
-- ea_ctrl <= latch_ea;
-- next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
ea_ctrl <= latch_ea;
next_state <= fetch_state;
end case;
when "1101" | "1110" | "1111" => -- accb
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldx
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
-- increment the effective address in case of 16 bit load
ea_ctrl <= inc_ea;
next_state <= read16_state;
-- when "0111" => -- stab
-- left_ctrl <= accb_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_st8;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= load_md;
-- ea_ctrl <= latch_ea;
-- next_state <= write8_state;
-- when "1101" => -- std
-- left_ctrl <= accd_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_st16;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= load_md;
-- ea_ctrl <= latch_ea;
-- next_state <= write16_state;
-- when "1111" => -- stx
-- left_ctrl <= ix_left;
-- right_ctrl <= zero_right;
-- alu_ctrl <= alu_st16;
-- cc_ctrl <= latch_cc;
-- md_ctrl <= load_md;
-- ea_ctrl <= latch_ea;
-- next_state <= write16_state;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
ea_ctrl <= latch_ea;
next_state <= execute_state;
end case;
when others =>
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= fetch_first_md;
ea_ctrl <= latch_ea;
next_state <= fetch_state;
end case;
when read16_state => -- read second data byte from ea
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle the effective address
ea_ctrl <= latch_ea;
-- read the low byte of the 16 bit data
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
--
-- 16 bit Write state
-- write high byte of ALU output.
-- EA hold address of memory to write to
-- Advance the effective address in ALU
--
when write16_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
-- increment the effective address
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
ea_ctrl <= inc_ea;
-- write the ALU hi byte to ea
addr_ctrl <= write_ad;
dout_ctrl <= md_hi_dout;
next_state <= write8_state;
--
-- 8 bit write
-- Write low 8 bits of ALU output
--
when write8_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
when jmp_state =>
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- load PC with effective address
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= load_ea_pc;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
when jsr_state => -- JSR
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= jsr1_state;
when jsr1_state => -- JSR
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= jmp_state;
when branch_state => -- Bcc
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- calculate signed branch
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
pc_ctrl <= add_ea_pc;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
when bsr_state => -- BSR
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= bsr1_state;
when bsr1_state => -- BSR
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= branch_state;
when rts_hi_state => -- RTS
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment the sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_hi_dout;
next_state <= rts_lo_state;
when rts_lo_state => -- RTS1
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle the ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
when mul_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- move acca to md
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
cc_ctrl <= latch_cc;
md_ctrl <= load_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mulea_state;
when mulea_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
md_ctrl <= latch_md;
-- idle ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- move accb to ea
ea_ctrl <= load_accb_ea;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= muld_state;
when muld_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
md_ctrl <= latch_md;
-- clear accd
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= latch_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul0_state;
when mul0_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 0 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(0) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul1_state;
when mul1_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 1 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(1) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul2_state;
when mul2_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 2 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(2) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul3_state;
when mul3_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 3 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(3) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul4_state;
when mul4_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 4 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(4) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul5_state;
when mul5_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 5 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(5) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul6_state;
when mul6_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 6 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(6) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= mul7_state;
when mul7_state =>
-- default
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- if bit 7 of ea set, add accd to md
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
if ea(7) = '1' then
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
else
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
end if;
md_ctrl <= shiftl_md;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
when execute_state => -- execute single operand instruction
-- default
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
case op_code(7 downto 4) is
when "0110" | -- indexed single op
"0111" => -- extended single op
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
left_ctrl <= md_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1010" => -- dec
right_ctrl <= plus_one_right;
alu_ctrl <= alu_dec;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1100" => -- inc
right_ctrl <= plus_one_right;
alu_ctrl <= alu_inc;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1110" => -- jmp
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= write8_state;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
md_ctrl <= latch_md;
next_state <= fetch_state;
end case;
when others =>
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
ea_ctrl <= latch_ea;
-- idle the bus
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= fetch_state;
end case;
when psha_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= push_ad;
dout_ctrl <= acca_dout;
next_state <= fetch_state;
when pula_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pull_ad;
dout_ctrl <= acca_dout;
next_state <= fetch_state;
when pshb_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= push_ad;
dout_ctrl <= accb_dout;
next_state <= fetch_state;
when pulb_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pull_ad;
dout_ctrl <= accb_dout;
next_state <= fetch_state;
when pshx_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= push_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshx_hi_state;
when pshx_hi_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= push_ad;
dout_ctrl <= ix_hi_dout;
next_state <= fetch_state;
when pulx_hi_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- pull ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_hi_dout;
next_state <= pulx_lo_state;
when pulx_lo_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_lo_dout;
next_state <= fetch_state;
--
-- return from interrupt
-- enter here from bogus interrupts
--
when rti_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- idle address bus
cc_ctrl <= latch_cc;
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
next_state <= rti_cc_state;
when rti_cc_state =>
-- default registers
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pull_ad;
dout_ctrl <= cc_dout;
next_state <= rti_accb_state;
when rti_accb_state =>
-- default registers
acca_ctrl <= latch_acca;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pull_ad;
dout_ctrl <= accb_dout;
next_state <= rti_acca_state;
when rti_acca_state =>
-- default registers
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pull_ad;
dout_ctrl <= acca_dout;
next_state <= rti_ixh_state;
when rti_ixh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_hi_dout;
next_state <= rti_ixl_state;
when rti_ixl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pull_ad;
dout_ctrl <= ix_lo_dout;
next_state <= rti_pch_state;
when rti_pch_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_add16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_hi_dout;
next_state <= rti_pcl_state;
when rti_pcl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- idle sp
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
-- pull pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pull_ad;
dout_ctrl <= pc_lo_dout;
next_state <= fetch_state;
--
-- here on interrupt
-- iv register hold interrupt type
--
when int_pcl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= push_ad;
dout_ctrl <= pc_lo_dout;
next_state <= int_pch_state;
when int_pch_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= push_ad;
dout_ctrl <= pc_hi_dout;
next_state <= int_ixl_state;
when int_ixl_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= push_ad;
dout_ctrl <= ix_lo_dout;
next_state <= int_ixh_state;
when int_ixh_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= push_ad;
dout_ctrl <= ix_hi_dout;
next_state <= int_acca_state;
when int_acca_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= push_ad;
dout_ctrl <= acca_dout;
next_state <= int_accb_state;
when int_accb_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= push_ad;
dout_ctrl <= accb_dout;
next_state <= int_cc_state;
when int_cc_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= latch_cc;
sp_ctrl <= load_sp;
-- write cc
addr_ctrl <= push_ad;
dout_ctrl <= cc_dout;
nmi_ctrl <= latch_nmi;
--
-- nmi is edge triggered
-- nmi_req is cleared when nmi goes low.
--
if nmi_req = '1' then
iv_ctrl <= nmi_iv;
next_state <= vect_hi_state;
else
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_mask_state;
else
case op_code is
when "00111110" => -- WAI (wait for interrupt)
iv_ctrl <= latch_iv;
next_state <= int_wai_state;
when "00111111" => -- SWI (Software interrupt)
iv_ctrl <= swi_iv;
next_state <= vect_hi_state;
when others => -- bogus interrupt (return)
iv_ctrl <= latch_iv;
next_state <= rti_state;
end case;
end if;
end if;
when int_wai_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
op_ctrl <= latch_op;
ea_ctrl <= latch_ea;
-- enable interrupts
left_ctrl <= sp_left;
right_ctrl <= plus_one_right;
alu_ctrl <= alu_cli;
cc_ctrl <= load_cc;
sp_ctrl <= latch_sp;
-- idle bus
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
if (nmi_req = '1') and (nmi_ack='0') then
iv_ctrl <= nmi_iv;
nmi_ctrl <= set_nmi;
next_state <= vect_hi_state;
else
--
-- nmi request is not cleared until nmi input goes low
--
if (nmi_req = '0') and (nmi_ack='1') then
nmi_ctrl <= reset_nmi;
else
nmi_ctrl <= latch_nmi;
end if;
--
-- IRQ is level sensitive
--
if (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_mask_state;
else
iv_ctrl <= latch_iv;
next_state <= int_wai_state;
end if;
end if;
when int_mask_state =>
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- Mask IRQ
left_ctrl <= sp_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
sp_ctrl <= latch_sp;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= vect_hi_state;
when halt_state => -- halt CPU.
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- do nothing in ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
if halt = '1' then
next_state <= halt_state;
else
next_state <= fetch_state;
end if;
when others => -- error state halt on undefine states
-- default
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
ix_ctrl <= latch_ix;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
iv_ctrl <= latch_iv;
op_ctrl <= latch_op;
nmi_ctrl <= latch_nmi;
ea_ctrl <= latch_ea;
-- do nothing in ALU
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
-- idle bus cycle
addr_ctrl <= idle_ad;
dout_ctrl <= md_lo_dout;
next_state <= error_state;
end case;
end process;
--------------------------------
--
-- state machine
--
--------------------------------
change_state: process( clk, rst, state, hold )
begin
if clk'event and clk = '0' then
if rst = '1' then
state <= reset_state;
elsif hold = '1' then
state <= state;
else
state <= next_state;
end if;
end if;
end process;
-- output
end CPU_ARCH;
| gpl-3.0 | 9ba1492b5a0b003a113d00443f9eb822 | 0.425135 | 3.670655 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_thvadd_v1_00_a/hdl/vhdl/user_logic_hwtul.vhd | 2 | 14,825 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic;
full : in std_logic;
Ttimer : out std_logic_vector( 0 to 31)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
alias intrfc2thrd_value : std_logic_vector(0 to 31) is intrfc2thrd(0 to 31);
alias intrfc2thrd_function : std_logic_vector(0 to 15) is intrfc2thrd(32 to 47);
alias intrfc2thrd_goWait : std_logic is intrfc2thrd(48);
alias thrd2intrfc_address : std_logic_vector(0 to 31) is thrd2intrfc( 32 to 63);
alias thrd2intrfc_value : std_logic_vector(0 to 31) is thrd2intrfc( 0 to 31);
alias thrd2intrfc_function : std_logic_vector(0 to 15) is thrd2intrfc( 64 to 79);
alias thrd2intrfc_opcode : std_logic_vector(0 to 5) is thrd2intrfc( 80 to 85) ;
signal new_request : std_logic; --when there is a new request to HWTI
signal timer : std_logic_vector(0 to 31);
type timer_state_machine is ( idle,counting);
signal timer_cs : timer_state_machine :=idle;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
SETUP_1,
SETUP_2,
SETUP_3,
SETUP_4,
SETUP_5,
SETUP_6,
WHILE_LOOP_1,
WHILE_LOOP_2,
WHILE_LOOP_3,
WHILE_LOOP_4,
WHILE_LOOP_4a,
WHILE_LOOP_5,
WHILE_LOOP_6,
WHILE_LOOP_7,
WHILE_LOOP_8,
WHILE_LOOP_9,
FUNCTION_EXIT_1,
FUNCTION_EXIT_2,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_WHILE_LOOP_3 : std_logic_vector(0 to 15) := x"0103";
constant U_WHILE_LOOP_6 : std_logic_vector(0 to 15) := x"0106";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESSOF : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal structAddr, structAddr_next : std_logic_vector(0 to 31);
signal size, size_next : std_logic_vector(0 to 31);
signal xAddr, xAddr_next : std_logic_vector(0 to 31);
signal yAddr, yAddr_next : std_logic_vector(0 to 31);
signal zAddr, zAddr_next : std_logic_vector(0 to 31);
signal xVal, xVal_next : std_logic_vector(0 to 31);
signal yVal, yVal_next : std_logic_vector(0 to 31);
signal count, count_next : std_logic_vector(0 to 31);
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
Ttimer <= timer;
timer_process: process(clock)
begin
if (clock'event and (clock = '1')) then
case timer_cs is
when idle=>
timer <= (others =>'0');
if current_state= FUNCTION_START then
timer_cs <= counting;
end if;
when counting =>
timer <= timer + x"00000001";
if (current_state= FUNCTION_RESET or current_state=FUNCTION_EXIT_1) then
timer_cs <= idle;
end if;
when others =>
timer <= (others =>'0');
timer_cs <= idle;
end case;
end if;
end process timer_process;
wr <= '0' when ( current_state= WAIT_STATE ) else new_request ;
rd <= exist;
HWTUL_STATE_PROCESS : process (clock, exist) is
begin
if (clock'event and (clock = '1')) then
return_state <= return_state_next;
structAddr <= structAddr_next;
size <= size_next;
xAddr <= xAddr_next;
yAddr <= yAddr_next;
zAddr <= zAddr_next;
xVal <= xVal_next;
yVal <= yVal_next;
count <= count_next;
-- Find out if the HWTI is tell us what to do
if (exist = '1') then
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_WHILE_LOOP_3 =>
current_state <= WHILE_LOOP_3;
when U_WHILE_LOOP_6 =>
current_state <= WHILE_LOOP_6;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
elsif ( new_request = '0') then
current_state <= next_state;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
new_request <= '1';
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
structAddr_next <= structAddr;
size_next <= size;
xAddr_next <= xAddr;
yAddr_next <= yAddr;
zAddr_next <= zAddr;
xVal_next <= xVal;
yVal_next <= yVal;
count_next <= count;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
new_request <= '0';
when FUNCTION_START =>
-- POP the argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
count_next <= Z32;
next_state <= WAIT_STATE;
return_state_next <= SETUP_1;
when SETUP_1 =>
-- Read the argument, which is an address of a struct
structAddr_next <= toUser_value;
-- Initiate the reading of the first variable in the struct, size
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= SETUP_2;
when SETUP_2 =>
-- Read the value of size
size_next <= toUser_value;
-- Initiate the reading of the third variable in the struct, xAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= SETUP_3;
when SETUP_3 =>
-- Read the value of xAddr
xAddr_next <= toUser_value;
-- Initiate the reading of the fourth variable in the struct, yAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000008";
next_state <= WAIT_STATE;
return_state_next <= SETUP_4;
when SETUP_4 =>
-- Read the value of yAddr
yAddr_next <= toUser_value;
-- Initiate the reading of the fifth variable in the struct, zAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"0000000c";
next_state <= WAIT_STATE;
return_state_next <= SETUP_6;
when SETUP_6 =>
-- Read the value of zAddr
zAddr_next <= toUser_value;
next_state <=WHILE_LOOP_6;
new_request <= '0';
when WHILE_LOOP_6 =>
-- Check to see if the index is over the size
if ( count < size ) then
-- More work to be done
-- Initiate the read of the X matrix
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= xAddr + (count(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_7;
else
-- we may exit
next_state <= FUNCTION_EXIT_1;
new_request <= '0';
end if;
when WHILE_LOOP_7 =>
xVal_next <= ToUser_value;
-- Initiate the read of the Y matrix
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= yAddr + (count(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_8;
when WHILE_LOOP_8 =>
yVal_next <= ToUser_value;
next_state <= WHILE_LOOP_9;
new_request <= '0';
when WHILE_LOOP_9 =>
-- Initiate the writing of the Z matrix
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= zAddr + (count(2 to 31) & "00");
thrd2intrfc_value <= xVal + yVal;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_6;
-- Increment count
count_next <= count + x"00000001";
when FUNCTION_EXIT_1 =>
thrd2intrfc_value <= timer;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT_2;
when FUNCTION_EXIT_2 =>
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
new_request <= '0';
when others =>
next_state <= ERROR_STATE;
new_request <= '0';
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 88aabdb302bd5adf2ed6a8bd8a8b14bf | 0.568162 | 3.847651 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/hw_acc.vhd | 2 | 7,954 | ------------------------------------------------------------------------------
-- add_sub_core - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: add_sub_core
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Thu Aug 9 10:06:10 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc is
port
(
Tintrfc2thrd_value : out std_logic_vector(0 to 31);
Tintrfc2thrd_function : out std_logic_vector(0 to 15);
Tintrfc2thrd_goWait : out std_logic;
Tthrd2intrfc_address : out std_logic_vector(0 to 31);
Tthrd2intrfc_value : out std_logic_vector(0 to 31);
Tthrd2intrfc_function : out std_logic_vector(0 to 15);
Tthrd2intrfc_opcode : out std_logic_vector(0 to 5);
Ttimer : out std_logic_vector( 0 to 31);
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
FSL1_M_Write : out std_logic;
FSL1_M_Data : out std_logic_vector(0 to 31);
FSL1_M_Full : in std_logic;
FSL2_M_Write : out std_logic;
FSL2_M_Data : out std_logic_vector(0 to 31);
FSL2_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
end hw_acc;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc is
component user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic ;
full : in std_logic ;
Ttimer : out std_logic_vector( 0 to 31)
);
end component user_logic_hwtul;
signal intrfc2thrd : std_logic_vector(0 to 63);
signal thrd2intrfc : std_logic_vector( 0 to 95);
signal rd : std_logic;
signal wr : std_logic;
signal exist : std_logic;
signal full : std_logic;
signal timer : std_logic_vector( 0 to 31) ;
-- Architecture Section
begin
Tintrfc2thrd_value <= intrfc2thrd(0 to 31) ;
Tintrfc2thrd_function <= intrfc2thrd (32 to 47);
Tintrfc2thrd_goWait <= exist ;
Tthrd2intrfc_address <= thrd2intrfc (32 to 63);
Tthrd2intrfc_value <= thrd2intrfc (0 to 31) ;
Tthrd2intrfc_function <= thrd2intrfc (64 to 79);
Tthrd2intrfc_opcode <= thrd2intrfc (80 to 85);
Ttimer <= timer;
intrfc2thrd <= FSL0_S_Data & FSL1_S_Data;
FSL0_M_Data <= thrd2intrfc(0 to 31);
FSL1_M_Data <= thrd2intrfc(32 to 63);
FSL2_M_Data <= thrd2intrfc(64 to 95);
--=======================================================
full <= FSL0_M_Full or FSL1_M_Full or FSL2_M_Full;
exist <= FSL0_S_Exists and FSL1_S_Exists ;
--=======================================================
FSL0_S_Read <= rd;
FSL1_S_Read <= rd;
FSL0_M_Write <= wr;
FSL1_M_Write <= wr;
FSL2_M_Write <= wr;
USER_LOGIC_HWTUL_I : user_logic_hwtul
port map
(
clock => FSL_Clk,
intrfc2thrd => intrfc2thrd,
thrd2intrfc => thrd2intrfc,
rd => rd,
wr => wr,
exist => exist,
full => full,
Ttimer => timer
);
end architecture implementation;
| bsd-3-clause | 0f4fe03ebaa84b0e4401c2defb4de5d2 | 0.472215 | 4.186316 | false | false | false | false |
jevinskie/aes-over-pcie | source/tb_top_top.vhd | 1 | 15,220 | -- File name: tb_top_top.vhd
-- Created: 2009-04-24
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: The one test bench to rule them all
use work.pcie.all;
use work.aes.all;
use work.numeric_std_textio.all;
use work.aes_textio.all;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_top_top is
generic (
clk_per : time := 10 ns
);
end tb_top_top;
architecture test of tb_top_top is
-- dut signals
signal clk : std_logic := '0';
signal nrst : std_logic := '1';
signal rx_data : byte := x"7C"; -- IDL
signal rx_data_k : std_logic := '1'; -- control byte
signal rx_status : std_logic_vector(2 downto 0) := "000";
signal rx_elec_idle : std_logic := '0';
signal phy_status : std_logic := '0';
signal rx_valid : std_logic := '1';
signal tx_detect_rx : std_logic;
signal tx_elec_idle : std_logic;
signal tx_comp : std_logic;
signal rx_pol : std_logic;
signal power_down : std_logic_vector(1 downto 0);
signal tx_data : byte;
signal tx_data_k : std_logic;
-- clock only runs when stop isnt asserted
signal stop : std_logic := '1';
signal test_num : natural := 0;
-- test signals
signal test_w : word;
signal test_dw : dword;
constant null_payload : state_type := (others => (others => x"00"));
-- reset the device
procedure reset (
signal nrst : out std_logic
) is
begin
nrst <= '0';
wait for clk_per;
nrst <= '1';
end procedure reset;
procedure tx_dllp_packet (
constant dllp_type : byte;
constant seq : seq_number_type;
signal rx_data : inout byte;
signal rx_data_k : inout std_logic
) is
variable last_rx_data : byte;
variable last_rx_data_k : std_logic;
variable crc : word := x"FFFF";
begin
last_rx_data := rx_data;
last_rx_data_k := rx_data_k;
rx_data <= x"5C"; -- SDP
rx_data_k <= '1';
wait for clk_per;
rx_data <= dllp_type;
crc := crc_gen(rx_data, crc);
rx_data_k <= '0';
wait for clk_per;
rx_data <= x"00";
crc := crc_gen(rx_data, crc);
wait for clk_per;
rx_data <= x"0" & seq(11 downto 8);
crc := crc_gen(rx_data, crc);
wait for clk_per;
rx_data <= seq(7 downto 0);
crc := crc_gen(rx_data, crc);
wait for clk_per;
rx_data <= crc(15 downto 8);
wait for clk_per;
rx_data <= crc(7 downto 0);
wait for clk_per;
rx_data <= x"FD"; -- END
rx_data_k <= '1';
wait for clk_per;
rx_data <= last_rx_data;
rx_data_k <= last_rx_data_k;
end procedure tx_dllp_packet;
procedure tx_tlp_packet (
constant dllp_type : byte;
constant dllp_seq : seq_number_type;
constant tlp_seq : seq_number_type;
constant tlp_type : byte;
constant length : word;
constant requester_id : word;
constant tag : byte;
constant byte_en : byte;
constant addr : dword;
constant payload : state_type;
constant send_payload : boolean;
signal rx_data : inout byte;
signal rx_data_k : inout std_logic
) is
variable last_rx_data : byte;
variable last_rx_data_k : std_logic;
variable crc : word := x"FFFF";
variable lcrc : dword := x"FFFFFFFF";
begin
last_rx_data := rx_data;
last_rx_data_k := rx_data_k;
rx_data <= x"FB"; -- STP
rx_data_k <= '1';
wait for clk_per;
rx_data <= dllp_type;
crc := crc_gen(rx_data, crc);
rx_data_k <= '0';
wait for clk_per;
rx_data <= x"00";
crc := crc_gen(rx_data, crc);
wait for clk_per;
rx_data <= x"0" & dllp_seq(11 downto 8);
crc := crc_gen(rx_data, crc);
wait for clk_per;
rx_data <= dllp_seq(7 downto 0);
crc := crc_gen(rx_data, crc);
wait for clk_per;
rx_data <= crc(15 downto 8);
wait for clk_per;
rx_data <= crc(7 downto 0);
wait for clk_per;
-- start of tlp
rx_data <= x"0" & tlp_seq(11 downto 8);
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= tlp_seq(7 downto 0);
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= tlp_type;
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= x"00";
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= length(15 downto 8);
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= length(7 downto 0);
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= requester_id(15 downto 8);
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= requester_id(7 downto 0);
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= tag;
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= byte_en;
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= addr(31 downto 24);
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= addr(23 downto 16);
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= addr(15 downto 8);
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
rx_data <= addr(7 downto 0);
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
if send_payload then
for i in index loop
for j in index loop
rx_data <= payload(j, i);
lcrc := lcrc_gen(rx_data, lcrc);
wait for clk_per;
end loop;
end loop;
end if;
rx_data <= lcrc(31 downto 24);
wait for clk_per;
rx_data <= lcrc(23 downto 16);
wait for clk_per;
rx_data <= lcrc(15 downto 8);
wait for clk_per;
rx_data <= lcrc(7 downto 0);
wait for clk_per;
rx_data <= x"FD"; -- END
rx_data_k <= '1';
wait for clk_per;
rx_data <= last_rx_data;
rx_data_k <= last_rx_data_k;
end procedure tx_tlp_packet;
procedure rx_dllp_packet (
constant dllp_type : byte;
constant dllp_seq : seq_number_type;
signal tx_data : in byte;
signal tx_data_k : in std_logic
) is
variable crc : word := x"FFFF";
begin
wait until (tx_data_k /= '1' or tx_data /= x"7C");
wait for clk_per/2;
assert (tx_data_k = '1' and tx_data = x"FB");
wait for clk_per;
assert (tx_data_k = '0' and tx_data = dllp_type); -- ACK
crc := crc_gen(tx_data, crc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = x"00"); -- dummy
crc := crc_gen(tx_data, crc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = x"0" & dllp_seq(11 downto 8)); -- seq hi
crc := crc_gen(tx_data, crc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = dllp_seq(7 downto 0)); -- seq lo
crc := crc_gen(tx_data, crc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = crc(15 downto 8)); -- crc hi
wait for clk_per;
assert (tx_data_k = '0' and tx_data = crc(7 downto 0)); -- crc lo
wait for clk_per;
assert (tx_data_k = '1' and tx_data = x"FD"); -- END
wait for clk_per;
assert (tx_data_k = '1' and tx_data = x"7C"); -- IDL
end procedure rx_dllp_packet;
procedure rx_tlp_packet (
constant dllp_type : byte;
constant dllp_seq : seq_number_type;
constant tlp_seq : seq_number_type;
constant tlp_type : byte;
constant length : word;
constant requester_id : word;
constant completer_id : word;
constant tag : byte;
constant byte_cnt : word;
constant addr : dword;
variable payload : out state_type;
signal tx_data : in byte;
signal tx_data_k : in std_logic;
signal lcrc : inout dword
) is
variable crc : word := x"FFFF";
--variable lcrc : dword := x"FFFFFFFF";
begin
lcrc <= x"FFFFFFFF";
wait until (tx_data_k /= '1' or tx_data /= x"7C");
wait for clk_per/2;
assert (tx_data_k = '1' and tx_data = x"FB");
wait for clk_per;
assert (tx_data_k = '0' and tx_data = dllp_type); -- ACK
crc := crc_gen(tx_data, crc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = x"00"); -- dummy
crc := crc_gen(tx_data, crc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = x"0" & dllp_seq(11 downto 8)); -- seq hi
crc := crc_gen(tx_data, crc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = dllp_seq(7 downto 0)); -- seq lo
crc := crc_gen(tx_data, crc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = crc(15 downto 8)); -- crc hi
wait for clk_per;
assert (tx_data_k = '0' and tx_data = crc(7 downto 0)); -- crc lo
wait for clk_per;
assert (tx_data_k = '0' and tx_data = x"0" & tlp_seq(11 downto 8)); -- tlp seq hi
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = tlp_seq(7 downto 0)); -- tlp seq lo
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = tlp_type);
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = x"00"); -- dummy
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = length(15 downto 8)); -- length hi
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = length(7 downto 0)); -- length lo
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = completer_id(15 downto 8)); -- completer id hi
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = completer_id(7 downto 0)); -- completer id lo
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = byte_cnt(15 downto 8)); -- byte count hi
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = byte_cnt(7 downto 0)); -- byte count lo
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = requester_id(15 downto 8)); -- requester id hi
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = requester_id(7 downto 0)); -- requester id lo
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = tag);
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (tx_data_k = '0' and tx_data = '0' & addr(6 downto 0)); -- weird address thing
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
assert (length = 4); -- only read payloads of length 4 DWs now
for i in g_index loop
assert (tx_data_k = '0');
payload(i mod 4, i / 4) := tx_data;
lcrc <= lcrc_gen(tx_data, lcrc);
wait for clk_per;
end loop;
assert (tx_data_k = '0' and tx_data = lcrc(31 downto 24));
wait for clk_per;
assert (tx_data_k = '0' and tx_data = lcrc(23 downto 16));
wait for clk_per;
assert (tx_data_k = '0' and tx_data = lcrc(15 downto 8));
wait for clk_per;
assert (tx_data_k = '0' and tx_data = lcrc(7 downto 0));
wait for clk_per;
assert (tx_data_k = '1' and tx_data = x"FD"); -- END
wait for clk_per;
assert (tx_data_k = '1' and tx_data = x"7C"); -- IDL
end procedure rx_tlp_packet;
begin
dut : entity work.top_top(structural) port map (
clk => clk, nrst => nrst,
rx_data => rx_data, rx_data_k => rx_data_k,
rx_status => rx_status, rx_elec_idle => rx_elec_idle,
phy_status => phy_status, rx_valid => rx_valid,
tx_detect_rx => tx_detect_rx, tx_elec_idle => tx_elec_idle,
tx_comp => tx_comp, rx_pol => rx_pol,
power_down => power_down, tx_data => tx_data,
tx_data_k => tx_data_k
);
-- main test bench code
-- clock when stop isnt asserted
clk <= not clk and not stop after clk_per/2;
process
file data : text open read_mode is "test_vectors/tb_aes_top.dat";
variable sample : line;
variable gold_enc_key : key_type;
variable gold_pt : state_type;
variable gold_ct : state_type;
variable dllp_seq_num : seq_number_type := (others => '0');
variable tlp_seq_num : seq_number_type := x"010";
variable ct : state_type;
begin
wait for clk_per*5;
-- start the clock
stop <= '0';
-- reset the device
reset(nrst);
wait for clk_per*10;
--################################################################
-- leda DCVHDL_165 off
while not endfile(data) loop
readline(data, sample);
hread(sample, gold_enc_key);
hread(sample, gold_pt);
hread(sample, gold_ct);
-- send key memory write
tx_tlp_packet(x"00", dllp_seq_num, tlp_seq_num, x"40", x"0004",
x"0000", x"00", x"FF", x"00001000", gold_enc_key,
true, rx_data, rx_data_k);
-- read key ack
rx_dllp_packet(x"00", dllp_seq_num, tx_data, tx_data_k);
dllp_seq_num := dllp_seq_num + 1;
tlp_seq_num := tlp_seq_num + 1;
wait for clk_per*10;
-- send pt memory write
tx_tlp_packet(x"00", dllp_seq_num, tlp_seq_num, x"40", x"0004",
x"0000", x"00", x"FF", x"00002000", gold_pt,
true, rx_data, rx_data_k);
-- read pt ack
rx_dllp_packet(x"00", dllp_seq_num, tx_data, tx_data_k);
dllp_seq_num := dllp_seq_num + 1;
tlp_seq_num := tlp_seq_num + 1;
wait for clk_per*10;
-- send ct memory read
tx_tlp_packet(x"00", dllp_seq_num, tlp_seq_num, x"00", x"0004",
x"0001", x"00", x"FF", x"00003000", null_payload,
false, rx_data, rx_data_k);
-- read ct ack
rx_dllp_packet(x"00", dllp_seq_num, tx_data, tx_data_k);
wait for clk_per*10;
-- read ct completion
rx_tlp_packet(x"00", dllp_seq_num, tlp_seq_num, "00001010",
x"0004", x"0001", x"0011", x"00", x"0010", x"00003000", ct,
tx_data, tx_data_k, test_dw);
assert ct = gold_ct;
dllp_seq_num := dllp_seq_num + 1;
tlp_seq_num := tlp_seq_num + 1;
wait for clk_per*10;
end loop;
-- leda DCVHDL_165 on
--################################################################
report "done with tests";
wait for clk_per*10;
-- stop the clock
stop <= '1';
wait for clk_per*5;
wait;
end process;
end test;
| bsd-3-clause | 943b578c337d94cf09390b0c179b5fcf | 0.531472 | 3.178117 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/ipif_regonly_slave.vhd | 3 | 19,787 | -------------------------------------------------------------------------------
-- $Id: ipif_regonly_slave.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- ipif_regonly_slave.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_regonly_slave.vhd
-- Version: v1.02e
-- Description: This file provides the OPB Slave interface to the arbiter
-- registers. Note that if the parameter, C_PROC_INTRFCE is
-- false, this logic is not instantiated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- opb_arbiter.vhd
-- --opb_arbiter_core.vhd
-- -- ipif_regonly_slave.vhd
-- -- priority_register_logic.vhd
-- -- priority_reg.vhd
-- -- onehot2encoded.vhd
-- -- or_bits.vhd
-- -- control_register.vhd
-- -- arb2bus_data_mux.vhd
-- -- mux_onehot.vhd
-- -- or_bits.vhd
-- -- watchdog_timer.vhd
-- -- arbitration_logic.vhd
-- -- or_bits.vhd
-- -- park_lock_logic.vhd
-- -- or_bits.vhd
-- -- or_gate.vhd
-- -- or_muxcy.vhd
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 08/28/01 -- Version 1.01a creation to include IPIF v1.22a
--
-- ALS 08/30/01
-- ^^^^^^
-- Updated IPIF component instantiation to change VERTEXII to VIRTEXII.
-- ~~~~~~
--
-- ALS 10/04/01 -- Version 1.02a creation to include IPIF v1.23a
--
-- ALS 10/08/01
-- ^^^^^^
-- Updated IPIF library to opb_ipif_v1_23_a
-- ~~~~~~
--
-- ALS 10/12/01
-- ^^^^^^
-- The width of the IPIF address bus is now set to 9 by the constant
-- IPIF_ABUS_WIDTH which is defined in opb_arb_pkg.
-- ~~~~~~
--
-- ALS 10/16/01
-- ^^^^^^
-- Updated component instantiation of IPIF.
-- ~~~~~~
-- ALS 11/27/01
-- ^^^^^^
-- Version 1.02b created to fix registered grant problem.
-- ~~~~~~
-- ALS 01/26/02
-- ^^^^^^
-- Created version 1.02c to fix problem with registered grants, and buslock when
-- the buslock master is holding request high and performing conversion cycles.
-- ~~~~~~
-- ALS 01/09/03
-- ^^^^^^
-- Created version 1.02d to register OPB_timeout to improve timing
-- ~~~~~~
-- bsbrao 09/27/04
-- ^^^^^^
-- Created version 1.02e to upgrade IPIF from opb_ipif_v1_23_a to
-- opb_ipif_v3_01_a
-- ~~~~~~
-- GAB 07/05/05
-- ^^^^^^
-- Fixed XST issue with adding an integer to a std_logic_vector. This
-- fixes CR211277.
-- Removed library ieee.std_logic_unsigned and ieee.std_logic_arith
-- Added library ieee.numeric_std
-- ~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- opb_arb_pkg defines RESET_ACTIVE and IPIF_ABUS_WIDTH
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.opb_arb_pkg.all;
use opb_v20_v1_10_d.ipif_pkg.all;
use opb_v20_v1_10_d.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OPB_ABUS_WIDTH -- width of OPB address bus
-- C_OPB_DBUS_WIDTH -- width of OPB data bus
-- C_BASEADDR -- OPB Arbiter base address
-- C_NUM_MASTERS -- number of OPB masters
-- C_NUM_MID_BITS -- number of bits to encode master id
-- C_DEV_BLK_ID -- device block id
-- C_DEV_MIR_ENABLE -- IPIF mirror capability enable
-- C_DEV_ADDR_DECODE_WIDTH -- width of device address
--
-- Definition of Ports:
--
-- Bus2IP_Data -- OPB data to processor bus
-- Bus2IP_Reg_RdCE -- read register clock enables
-- Bus2IP_Reg_WrCE -- write register clock enables
-- Bus2IP_Clk -- clock
-- Bus2IP_Reset -- reset
-- IP2Bus_Data -- IP data to processor bus
-- IP2Bus_RdAck -- IP read acknowledge
-- IP2Bus_WrAck -- IP write acknowledge
-- OPB_ABus -- OPB address bus
-- OPB_BE -- OPB byte enables
-- OPB_Clk -- OPB clock
-- OPB_DBus -- OPB data bus
-- OPB_RNW -- Read not Write
-- OPB_Select -- Master has control of bus
-- OPB_seqAddr -- Sequential Address
-- Rst -- Reset
-- Sln_DBus -- Slave data bus
-- Sln_ErrAck -- Slave error acknowledge
-- Sln_Retry -- Slave retry
-- Sln_ToutSup -- Slave timeout suppress
-- Sln_XferAck -- Slave transfer acknowledge
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity ipif_regonly_slave is
generic (
C_OPB_ABUS_WIDTH : integer := 32;
C_OPB_DBUS_WIDTH : integer := 32;
C_BASEADDR : std_logic_vector;
C_NUM_MASTERS : integer := 4;
C_NUM_MID_BITS : integer := 2;
C_DEV_BLK_ID : integer :=0;
C_DEV_MIR_ENABLE : integer := 0;
C_DEV_ADDR_DECODE_WIDTH : integer := 4
);
port (
Bus2IP_Data : out std_logic_vector(0 to C_OPB_DBUS_WIDTH - 1 );
Bus2IP_Reg_RdCE : out std_logic_vector(0 to C_NUM_MASTERS );
Bus2IP_Reg_WrCE : out std_logic_vector(0 to C_NUM_MASTERS );
Bus2IP_Clk : out std_logic;
Bus2IP_Reset : out std_logic;
IP2Bus_Data : in std_logic_vector(0 to C_OPB_DBUS_WIDTH - 1 );
IP2Bus_RdAck : in std_logic;
IP2Bus_WrAck : in std_logic;
OPB_ABus : in std_logic_vector(0 to C_OPB_ABUS_WIDTH - 1 );
OPB_BE : in std_logic_vector(0 to C_OPB_DBUS_WIDTH / 8 - 1 );
OPB_Clk : in std_logic;
OPB_DBus : in std_logic_vector(0 to C_OPB_DBUS_WIDTH - 1 );
OPB_RNW : in std_logic;
OPB_Select : in std_logic;
OPB_seqAddr : in std_logic;
Rst : in std_logic;
Sln_DBus : out std_logic_vector(0 to C_OPB_DBUS_WIDTH - 1 );
Sln_ErrAck : out std_logic;
Sln_Retry : out std_logic;
Sln_ToutSup : out std_logic;
Sln_XferAck : out std_logic
);
end ipif_regonly_slave;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of ipif_regonly_slave is
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
constant ZEROES : std_logic_vector := X"00000000";
constant ARD_ID_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_00 -- OPB_V20 priority registers
);
constant REG_BASEADDR : std_logic_vector := C_BASEADDR or x"00000100";
-- Fixed XST issue with adding an integer to a std_logic_vetor (GAB)
--constant REG_HIGHADDR : std_logic_vector := C_BASEADDR + x"00000100" + C_NUM_MASTERS*4;
constant REG_HIGHADDR : std_logic_vector := REG_BASEADDR or
(std_logic_vector(to_unsigned(
C_NUM_MASTERS*4,32)));
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZEROES & REG_BASEADDR, -- registers Base Address
ZEROES & REG_HIGHADDR -- registers High Address
);
constant ARD_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_OPB_DBUS_WIDTH -- User Logic data width
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => C_NUM_MASTERS + 1 -- register CEs
);
constant ARD_DEPENDENT_PROPS_ARRAY : DEPENDENT_PROPS_ARRAY_TYPE :=
(
0 => (others => 0)
);
-- Set the pipeline model
-- 1 = include OPB-In pipeline registers
-- 2 = include IP pipeline registers
-- 3 = include OPB-In and IP pipeline registers
-- 4 = include OPB-Out pipeline registers
-- 5 = include OPB-In and OPB-Out pipeline registers
-- 6 = include IP and OPB-Out pipeline registers
-- 7 = include OPB-In, IP, and OPB-Out pipeline registers
constant PIPELINE_MODEL : integer := 6;
-- Include IP interrupts, don't need Device ISC or IID
constant IP_INTR_MODE_ARRAY : integer_array_type :=
populate_intr_mode_array(1, 0);
-- No bursting
constant DEV_BURST_ENABLE : integer := 0;
-- Index for user logic
constant USER00_CS_INDEX : integer :=
get_id_index(ARD_ID_ARRAY, USER_00);
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- IPIC Used Signals
signal iP2Bus_IntrEvent :std_logic_vector(0 to IP_INTR_MODE_ARRAY'length-1) := (others => '0');
signal iP2Bus_Ack : std_logic;
signal iP2Bus_PostedWrInh_vec :std_logic_vector(0 to ARD_ID_ARRAY'length-1)
:= (others => '1');
signal bus2IP_CS_vec :std_logic_vector(0 to ARD_ID_ARRAY'length-1);
signal bus2IP_RdCE_vec :std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2IP_WrCE_vec :std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
--------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- assign IP inputs/output to correct vector value
iP2Bus_Ack <= IP2Bus_RdAck or IP2Bus_WrAck ;
iP2Bus_PostedWrInh_vec(USER00_CS_INDEX) <= '1';
Bus2IP_Reg_RdCE <= bus2IP_RdCE_vec;
Bus2IP_Reg_WrCE <= bus2IP_WrCE_vec;
-- instantiate the OPB IPIF
OPB_IPIF_I : entity opb_v20_v1_10_d.opb_ipif
generic map
(
C_ARD_ID_ARRAY => ARD_ID_ARRAY,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_DWIDTH_ARRAY => ARD_DWIDTH_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_ARD_DEPENDENT_PROPS_ARRAY => ARD_DEPENDENT_PROPS_ARRAY,
C_PIPELINE_MODEL => PIPELINE_MODEL,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE,
C_OPB_AWIDTH => C_OPB_ABUS_WIDTH,
C_OPB_DWIDTH => C_OPB_DBUS_WIDTH,
C_FAMILY => "virtex2",
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_DEV_BURST_ENABLE => DEV_BURST_ENABLE,
C_INCLUDE_ADDR_CNTR => 0,
C_INCLUDE_WR_BUF => 0
)
port map
(
-- OPB signals
OPB_select => OPB_select,
OPB_DBus => OPB_DBus,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_RNW => OPB_RNW,
OPB_seqAddr => OPB_seqAddr,
Sln_DBus => Sln_DBus,
Sln_xferAck => Sln_XferAck,
Sln_errAck => Sln_ErrAck,
Sln_retry => Sln_Retry,
Sln_toutSup => Sln_ToutSup,
-- IPIC signals (address, data, acknowledge)
Bus2IP_CS => bus2IP_CS_vec,
Bus2IP_CE => open,
Bus2IP_RdCE => bus2IP_RdCE_vec,
Bus2IP_WrCE => bus2IP_WrCE_vec,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_Addr => open,
Bus2IP_AddrValid => open,
Bus2IP_BE => open,
Bus2IP_RNW => open,
Bus2IP_Burst => open,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_Ack => iP2Bus_Ack,
IP2Bus_AddrAck => '0', -- new signal
IP2Bus_Error => '0',
IP2Bus_Retry => '0',
IP2Bus_ToutSup => '0',
IP2Bus_PostedWrInh => iP2Bus_PostedWrInh_vec,
-- IPIC signals (Read Packet FIFO)
IP2RFIFO_Data => open,
IP2RFIFO_WrMark => open,
IP2RFIFO_WrRelease => open,
IP2RFIFO_WrReq => open,
IP2RFIFO_WrRestore => open,
RFIFO2IP_AlmostFull => open,
RFIFO2IP_Full => open,
RFIFO2IP_Vacancy => open,
RFIFO2IP_WrAck => open,
-- IPIC signals (Write Packet FIFO)
IP2WFIFO_RdMark => '0',
IP2WFIFO_RdRelease => '0',
IP2WFIFO_RdReq => '0',
IP2WFIFO_RdRestore => '0',
WFIFO2IP_AlmostEmpty=> open,
WFIFO2IP_Data => open,
WFIFO2IP_Empty => open,
WFIFO2IP_Occupancy => open,
WFIFO2IP_RdAck => open,
-- interrupts
IP2Bus_IntrEvent => iP2Bus_IntrEvent,
IP2INTC_Irpt => open,
-- Software test breakpoint signal
Freeze => '0',
Bus2IP_Freeze => open,
-- clocks and reset
OPB_Clk => OPB_Clk,
Bus2IP_Clk => Bus2IP_Clk,
IP2Bus_Clk => '0',
Reset => Rst,
Bus2IP_Reset => Bus2IP_Reset
);
end implementation;
| bsd-3-clause | 888faa8f3f366433b42f0e3cc5378fc4 | 0.443018 | 4.424642 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/ipif_common_v1_00_c/hdl/vhdl/ctrl_reg.vhd | 2 | 4,906 | -------------------------------------------------------------------------------
-- $Id: ctrl_reg.vhd,v 1.1 2003/02/18 19:16:00 ostlerf Exp $
-------------------------------------------------------------------------------
-- A generic control register for use with the dma_sg block.
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: ctrl_reg.vhd
--
-- Description: Control register with parameterizable width and two
-- write enables.
--
-------------------------------------------------------------------------------
-- Structure:
-- ctrl_reg.vhds
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
-- History:
-- FLO 12/19/01 -- Header added
--
-- -- Two point solution registers are declared
-- -- for this version as XST E.33 does not handle
-- -- the parameterized width.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector;
q : out std_logic_vector
);
end ctrl_reg;
architecture sim of ctrl_reg is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
q <= C_RESET_VAL;
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg_0_to_6 is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
d : in std_logic_vector(0 to 6);
q : out std_logic_vector(0 to 6)
);
end ctrl_reg_0_to_6;
architecture sim of ctrl_reg_0_to_6 is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
q <= C_RESET_VAL;
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
entity ctrl_reg_0_to_0 is
generic(
C_RESET_VAL: std_logic_vector
);
port(
clk : in std_logic;
rst : in std_logic;
chan_sel : in std_logic;
reg_sel : in std_logic;
wr_ce : in std_logic;
-- XGR_E33 d : in std_logic_vector(0 to 0);
-- XGR_E33 q : out std_logic_vector(0 to 0)
d : in std_logic;
q : out std_logic
);
end ctrl_reg_0_to_0;
architecture sim of ctrl_reg_0_to_0 is
begin
CTRL_REG_PROCESS: process (clk)
begin
if clk'event and clk='1' then
if (rst = '1') then
-- XGR_E33 q <= C_RESET_VAL;
q <= C_RESET_VAL(0);
elsif (chan_sel and reg_sel and wr_ce) = '1' then
q <= d;
end if;
end if;
end process;
end;
| bsd-3-clause | 8378b12a2464c2621d456af17fef49e0 | 0.387281 | 4.171769 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/g_eth/g_ethrx.vhd | 1 | 11,259 | library ieee;
use ieee.std_logic_1164.all;
entity g_ethrx is
generic(
HEAD_AWIDTH : natural := 5;
BUFF_AWIDTH : natural := 12;
FIFO_AWIDTH : natural := 2;
WR_CYCLE : natural := 3;
RAM_AWIDTH : natural := 32
);
port(
clk : in std_logic;
zcpsm_clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(7 downto 0);
rxdv : in std_logic;
db_ce : in std_logic;
db_port_id : in std_logic_vector(3 downto 0);
db_write_strobe : in std_logic;
db_out_port : in std_logic_vector(7 downto 0);
db_read_strobe : in std_logic;
db_in_port : out std_logic_vector(7 downto 0);
eth_ce : in std_logic;
eth_port_id : in std_logic_vector(3 downto 0);
eth_write_strobe : in std_logic;
eth_out_port : in std_logic_vector(7 downto 0);
eth_read_strobe : in std_logic;
eth_in_port : out std_logic_vector(7 downto 0);
eth_dma_ce : in std_logic;
ethrx_busy : out std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
lastframe_flag : out std_logic;
ram_wren : out std_logic;
ram_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
-- test : out std_logic_vector(3 downto 0);
ram_wdata : out std_logic_vector(31 downto 0)
);
end entity;
architecture arch_ethrx of g_ethrx is
component g_ethrx_input
generic(
HEAD_AWIDTH : NATURAL;
BUFF_AWIDTH : NATURAL);
port(
-- test_crc : out std_logic_vector(3 downto 0);
clk : in std_logic;
reset : in std_logic;
rxclk : in std_logic;
rxd : in std_logic_vector(7 downto 0);
rxdv : in std_logic;
recvtime : out std_logic_vector(31 downto 0);
recvtime_valid : out std_logic;
localtime_locked : out std_logic;
head_wren : out std_logic;
head_waddr : out std_logic_vector((HEAD_AWIDTH-1) downto 0);
head_wdata : out std_logic_vector(7 downto 0);
head_wr_block : out std_logic;
buff_wren : out std_logic;
buff_waddr : out std_logic_vector((BUFF_AWIDTH-1) downto 0);
buff_wdata : out std_logic_vector(31 downto 0));
end component;
component Rx_queue
generic(
HEAD_AWIDTH : NATURAL;
FIFO_AWIDTH : NATURAL;
RAM_TYPE : STRING);
port(
clk : in std_logic;
reset : in std_logic;
head_wren : in std_logic;
head_waddr : in std_logic_vector((HEAD_AWIDTH-1) downto 0);
head_wdata : in std_logic_vector(7 downto 0);
head_wr_block : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0));
end component;
component blockdram
generic(
depth : INTEGER;
Dwidth : INTEGER;
Awidth : INTEGER);
port(
addra : in std_logic_vector((Awidth-1) downto 0);
clka : in std_logic;
addrb : in std_logic_vector((Awidth-1) downto 0);
clkb : in std_logic;
dia : in std_logic_vector((Dwidth-1) downto 0);
wea : in std_logic;
dob : out std_logic_vector((Dwidth-1) downto 0));
end component;
component zcpsm2dma
generic(
RAM_AWIDTH : NATURAL
);
port(
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0);
lastframe_flag : out std_logic;
start : out std_logic;
length : out std_logic_vector(15 downto 0);
start_waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
start_raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : out std_logic_vector(7 downto 0);
rstep : out std_logic_vector(7 downto 0);
busy : in std_logic);
end component;
component dma_ctrl
generic(
DWIDTH : NATURAL;
RD_CYCLE : NATURAL;
RD_DELAY : NATURAL;
RAM_AWIDTH : NATURAL
);
port(
clk : in std_logic;
reset : in std_logic;
ena : in std_logic;
start : in std_logic;
length : in std_logic_vector(15 downto 0);
start_waddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
start_raddr : in std_logic_vector(RAM_AWIDTH - 1 downto 0);
wstep : in std_logic_vector(7 downto 0);
rstep : in std_logic_vector(7 downto 0);
busy : out std_logic;
raddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
rdata : in std_logic_vector((DWIDTH-1) downto 0);
wren : out std_logic;
waddr : out std_logic_vector(RAM_AWIDTH - 1 downto 0);
wdata : out std_logic_vector((DWIDTH-1) downto 0));
end component;
component shiftreg
generic(
width : INTEGER;
depth : INTEGER);
port(
clk : in std_logic;
ce : in std_logic;
D : in std_logic_vector((width-1) downto 0);
Q : out std_logic_vector((width-1) downto 0);
S : out std_logic_vector((width-1) downto 0));
end component;
signal head_wren : std_logic;
signal head_waddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal head_wdata : std_logic_vector(7 downto 0);
signal head_wr_block : std_logic;
signal buff_wren : std_logic;
signal buff_waddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_wdata : std_logic_vector(31 downto 0);
signal buff_raddr : std_logic_vector(BUFF_AWIDTH - 1 downto 0);
signal buff_rdata : std_logic_vector(31 downto 0);
signal dma_length_byte : std_logic_vector(15 downto 0);
signal dma_length_dword : std_logic_vector(15 downto 0);
signal dma_start_waddr_word : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_start_waddr_dword : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_start_raddr_byte : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_start_raddr_dword : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_wstep : std_logic_vector(7 downto 0);
signal dma_rstep : std_logic_vector(7 downto 0);
signal dma_start : std_logic;
signal dma_busy : std_logic;
signal dma_raddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_rdata : std_logic_vector(31 downto 0);
signal dma_wren : std_logic;
signal dma_waddr : std_logic_vector(RAM_AWIDTH - 1 downto 0);
signal dma_wdata : std_logic_vector(31 downto 0);
signal ram_wren_d1 : std_logic;
signal ram_wren_d2 : std_logic;
signal v0 : std_logic_vector(0 downto 0);
signal v1 : std_logic_vector(0 downto 0);
signal dma_wren_dly : std_logic;
begin
-- test <= head_wr_block;
ethrx_busy <= dma_busy;
u_input : g_ethrx_input
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
BUFF_AWIDTH => BUFF_AWIDTH
)
port map(
-- test_crc => test,
clk => clk,
reset => reset,
rxclk => rxclk,
rxd => rxd,
rxdv => rxdv,
recvtime => recvtime,
recvtime_valid => recvtime_valid,
localtime_locked => localtime_locked,
head_wren => head_wren,
head_waddr => head_waddr,
head_wdata => head_wdata,
head_wr_block => head_wr_block,
buff_wren => buff_wren,
buff_waddr => buff_waddr,
buff_wdata => buff_wdata
);
u_db_queue : Rx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => 1,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
head_wren => head_wren,
head_waddr => head_waddr,
head_wdata => head_wdata,
head_wr_block => head_wr_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => db_ce,
zcpsm_port_id => db_port_id,
zcpsm_write_strobe => db_write_strobe,
zcpsm_out_port => db_out_port,
zcpsm_read_strobe => db_read_strobe,
zcpsm_in_port => db_in_port
);
u_rx_queue : Rx_queue
generic map(
HEAD_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => FIFO_AWIDTH,
RAM_TYPE => "DIS_RAM"
)
port map(
clk => clk,
reset => reset,
head_wren => head_wren,
head_waddr => head_waddr,
head_wdata => head_wdata,
head_wr_block => head_wr_block,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => eth_ce,
zcpsm_port_id => eth_port_id,
zcpsm_write_strobe => eth_write_strobe,
zcpsm_out_port => eth_out_port,
zcpsm_read_strobe => eth_read_strobe,
zcpsm_in_port => eth_in_port
);
u_rx_buffer : blockdram
generic map(
DEPTH => 2 ** BUFF_AWIDTH,
AWIDTH => BUFF_AWIDTH,
DWIDTH => 32
)
port map(
addra => buff_waddr,
clka => clk,
addrb => buff_raddr,
clkb => clk,
dia => buff_wdata,
wea => buff_wren,
dob => buff_rdata
);
u_dma : dma_ctrl
generic map(
DWIDTH => 32,
RD_CYCLE => WR_CYCLE,
RD_DELAY => 0,
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
ena => '1',
start => dma_start,
length => dma_length_dword,
start_waddr => dma_start_waddr_dword,
start_raddr => dma_start_raddr_dword, -- 32룬½ØÈ¡ºó12λ×÷Ϊrx_bufferµÄµØÖ·
wstep => dma_wstep,
rstep => dma_rstep,
busy => dma_busy,
raddr => dma_raddr,
rdata => dma_rdata,
wren => dma_wren,
waddr => dma_waddr,
wdata => dma_wdata
);
dma_length_dword <= "00" & dma_length_byte(15 downto 2);
dma_start_raddr_dword <= "00" & dma_start_raddr_byte(RAM_AWIDTH-1 downto 2);
dma_start_waddr_dword <= '0' & dma_start_waddr_word(RAM_AWIDTH-1 downto 1);
u_zcpsm2dma : zcpsm2dma
generic map (
RAM_AWIDTH => RAM_AWIDTH
)
port map(
clk => clk,
reset => reset,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => eth_dma_ce,
zcpsm_port_id => eth_port_id,
zcpsm_write_strobe => eth_write_strobe,
zcpsm_out_port => eth_out_port,
zcpsm_read_strobe => eth_read_strobe,
zcpsm_in_port => eth_in_port,
lastframe_flag => lastframe_flag,
start => dma_start,
length => dma_length_byte,
start_waddr => dma_start_waddr_word,
start_raddr => dma_start_raddr_byte,
wstep => dma_wstep,
rstep => dma_rstep,
busy => dma_busy
);
buff_raddr <= dma_raddr(BUFF_AWIDTH - 1 downto 0);
dma_rdata <= buff_rdata;
-- p_wr: process(clk, reset)
-- begin
-- if reset = '1' then
--- ram_wren_d1 <= '0';
-- ram_wren_d2 <= '0';
-- ram_waddr <= (others => '0');
-- ram_wdata <= (others => '0');
-- elsif rising_edge(clk) then
-- ram_wren_d1 <= dma_wren;
-- ram_wren_d2 <= ram_wren_d1;
-- if dma_wren = '1' then
-- ram_waddr <= dma_waddr;
-- ram_wdata <= dma_wdata;
-- end if;
-- end if;
-- end process;
-- ram_wren <= ram_wren_d1 or ram_wren_d2;
u_wren_dly : ShiftReg
generic map(width => 1, depth => WR_CYCLE)
port map(clk => clk, ce => '1', d => v0, q => v1, s => open);
v0(0) <= dma_wren;
dma_wren_dly <= v1(0);
p_wr : process(clk, reset)
begin
if reset = '1' then
ram_wren <= '0';
ram_waddr <= (others => '0');
ram_wdata <= (others => '0');
elsif rising_edge(clk) then
if dma_wren = '1' then
ram_waddr <= dma_waddr;
ram_wdata <= dma_wdata;
end if;
if dma_wren = '1' then
ram_wren <= '1';
elsif dma_wren_dly = '1' then
ram_wren <= '0';
end if;
end if;
end process;
end arch_ethrx;
| gpl-2.0 | 89a903116cf6955ed6734317cf77727f | 0.611156 | 2.666746 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/stress/cond_wait_1.vhd | 2 | 20,910 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
--signal reg5, reg5_next : std_logic_vector(0 to 31);
--signal reg6, reg6_next : std_logic_vector(0 to 31);
--signal reg7, reg7_next : std_logic_vector(0 to 31);
--signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
--retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
--reg5 <= reg5_next;
--reg6 <= reg6_next;
--reg7 <= reg7_next;
--reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
--retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
--reg5_next <= reg5;
--reg6_next <= reg6;
--reg7_next <= reg7;
--reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: cond_init_stress_1
-- reg1 = numberOfTestsToComplete
-- reg2 = * numberOfTestsCompleted
-- reg3 = * mutex
-- reg4 = * condvar
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Read the value of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg1_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of mutex
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
reg3_next <= intrfc2thrd_value;
-- Read the address of condvar
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C";
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
reg4_next <= intrfc2thrd_value;
next_state <= STATE_21;
-- hthread_mutex_lock( data->completedMutex );
when STATE_21 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_LOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_7;
next_state <= WAIT_STATE;
-- while( *(data->numberOfTestsCompleted) < *(data->numberOfTestsToComplete) )
when STATE_7 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_8;
when STATE_8 =>
-- Do the comparision between completed and toBeCompleted
if ( intrfc2thrd_value < reg1 ) then
next_state <= STATE_9;
else
next_state <= STATE_16;
end if;
-- hthread_cond_signal( condvar );
when STATE_9 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- call COND_SIGNAL
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_SIGNAL;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_11;
next_state <= WAIT_STATE;
-- hthread_cond_wait( condvar, mutex );
when STATE_11 =>
-- push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_13;
when STATE_13 =>
-- call hthread_cond_wait
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_WAIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_14;
next_state <= WAIT_STATE;
-- *( data->numberOfTestsCompleted) += 1;
when STATE_14 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_15;
when STATE_15 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg2;
thrd2intrfc_value <= intrfc2thrd_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- END OF WHILE LOOP
-- hthread_cond_broadcast( condvar );
when STATE_16 =>
-- push condvar
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_17;
when STATE_17 =>
-- call COND_BROADCAST
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_COND_BROADCAST;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_18;
next_state <= WAIT_STATE;
-- hthread_mutex_unlock( data->completedMutex );
when STATE_18 =>
-- push data->completedMutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_19;
when STATE_19 =>
-- call hthread_mutex_unlock
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_UNLOCK;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_20;
next_state <= WAIT_STATE;
when STATE_20 =>
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 50797b6002ccf82233c1d801b2eb4d10 | 0.553993 | 3.722628 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/stress/create_1.vhd | 2 | 21,409 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
STATE_21,
STATE_22,
STATE_23,
STATE_24,
STATE_25,
STATE_26,
STATE_27,
STATE_28,
STATE_29,
STATE_30,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
constant U_STATE_21 : std_logic_vector(0 to 15) := x"0121";
constant U_STATE_22 : std_logic_vector(0 to 15) := x"0122";
constant U_STATE_23 : std_logic_vector(0 to 15) := x"0123";
constant U_STATE_24 : std_logic_vector(0 to 15) := x"0124";
constant U_STATE_25 : std_logic_vector(0 to 15) := x"0125";
constant U_STATE_26 : std_logic_vector(0 to 15) := x"0126";
constant U_STATE_27 : std_logic_vector(0 to 15) := x"0127";
constant U_STATE_28 : std_logic_vector(0 to 15) := x"0128";
constant U_STATE_29 : std_logic_vector(0 to 15) := x"0129";
constant U_STATE_30 : std_logic_vector(0 to 15) := x"0130";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
--signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
--signal reg7, reg7_next : std_logic_vector(0 to 31);
--signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
--retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
--reg7 <= reg7_next;
--reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
when U_STATE_21 =>
current_state <= STATE_21;
when U_STATE_22 =>
current_state <= STATE_22;
when U_STATE_23 =>
current_state <= STATE_23;
when U_STATE_24 =>
current_state <= STATE_24;
when U_STATE_25 =>
current_state <= STATE_25;
when U_STATE_26 =>
current_state <= STATE_26;
when U_STATE_27 =>
current_state <= STATE_27;
when U_STATE_28 =>
current_state <= STATE_28;
when U_STATE_29 =>
current_state <= STATE_29;
when U_STATE_30 =>
current_state <= STATE_30;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
--retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
--reg7_next <= reg7;
--reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: create_stress_1
-- reg1 = numberOfTestsToComplete
-- reg2 = * numberOfTestsCompleted
-- reg3 = * function
-- reg4 = thread
-- reg5 = i
-- reg6 = createReturn/numberOfTestsComplted
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Read the value of numberOfTestsToComplete
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
reg1_next <= intrfc2thrd_value;
-- Read the address of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 4;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
reg2_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + 8;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
--createReturn = SUCCESS
-- i = 0
when STATE_5 =>
reg3_next <= intrfc2thrd_value;
reg5_next <= Z32;
reg6_next <= Z32;
next_state <= STATE_6;
-- while( createReturn == SUCCESS
-- && *(data->numberOfTestsCompleted) < *(data->numberOfTestsToComplete) )
when STATE_6 =>
case reg6 is
when x"00000000" =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when others =>
next_state <= STATE_17;
end case;
when STATE_7 =>
-- Do the comparision between completed and toBeCompleted
if ( intrfc2thrd_value < reg1 ) then
next_state <= STATE_8;
else
next_state <= STATE_17;
end if;
-- createReturn == hthread_create( &(data->threads[i]), NULL, data->function, NULL );
when STATE_8 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg3;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- push &( data->threads[i] )
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"0000000C" + ( reg5(2 to 31) & "00" );
next_state <= WAIT_STATE;
return_state_next <= STATE_12;
when STATE_12 =>
-- call create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_13;
next_state <= WAIT_STATE;
when STATE_13 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_14;
-- if ( createReturn == SUCCESS )
-- *(data->numberOfTestsCompleted) += 1;
-- i++;
when STATE_14 =>
case reg6 is
when x"00000000" =>
next_state <= STATE_15;
when others =>
next_state <= STATE_6;
end case;
when STATE_15 =>
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_16;
-- increment i
reg5_next <= reg5 + x"00000001";
when STATE_16 =>
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= reg2;
thrd2intrfc_value <= intrfc2thrd_value + x"00000001";
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
-- END OF WHILE LOOP
-- for( i=0; i< *(data->numberOfTestsCompleted); i++ );
when STATE_17 =>
-- set i to 0
reg5_next <= Z32;
-- Read the value of numberOfTestsCompleted
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= reg2;
next_state <= WAIT_STATE;
return_state_next <= STATE_18;
when STATE_18 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_19;
when STATE_19 =>
-- compare i and numberOfTestsComplted
if ( reg5 < reg6 ) then
next_state <= STATE_20;
else
next_state <=FUNCTION_EXIT;
end if;
-- hthread_join( data->thread[i], NULL );
when STATE_20 =>
-- read the value of data->thread[i]
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"0000000C" + ( reg5(2 to 31) & "00" );
next_state <= WAIT_STATE;
return_state_next <= STATE_21;
when STATE_21 =>
reg4_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_22;
when STATE_22 =>
-- push thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg4;
next_state <= WAIT_STATE;
return_state_next <= STATE_23;
when STATE_23 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_24;
next_state <= WAIT_STATE;
when STATE_24 =>
reg5_next <= reg5 + x"00000001";
next_state <= STATE_19;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | 471fb8f33c5d8ae55b5d1238a9a326c3 | 0.549208 | 3.705903 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/attr_init_1.vhd | 2 | 15,193 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: attr_init_1.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_attr_t * attr = (hthread_attr_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_attr_init( attr );
when STATE_1 =>
-- Push the argument to hthread_attr_init
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Call hthread_attr_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_ATTR_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_3;
next_state <= WAIT_STATE;
-- retVal = attr->detached
when STATE_3 =>
-- Read the value of attr->detached
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | a5f9d1c549a81cd9b9b640e586404786 | 0.538932 | 3.850228 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDE/IDE_READ/read_tb.vhd | 1 | 3,009 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:03:22 11/13/2015
-- Design Name:
-- Module Name: C:/Users/Gham/Desktop/Actual files/IDE/IDE3_final/IDE_READ/read_tb.vhd
-- Project Name: IDE_READ
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: read_circuit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY read_tb IS
END read_tb;
ARCHITECTURE behavior OF read_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT read_circuit
PORT(
clk : IN std_logic;
reset : IN std_logic;
pa : IN std_logic;
sc : IN std_logic;
rd_cpu : IN std_logic;
rdy : OUT std_logic;
IOR : OUT std_logic;
data_bus : IN std_logic_vector(15 downto 0);
data_out_cpu : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal pa : std_logic := '0';
signal sc : std_logic := '0';
signal rd_cpu : std_logic := '0';
signal data_bus : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal rdy : std_logic;
signal IOR : std_logic;
signal data_out_cpu : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: read_circuit PORT MAP (
clk => clk,
reset => reset,
pa => pa,
sc => sc,
rd_cpu => rd_cpu,
rdy => rdy,
IOR => IOR,
data_bus => data_bus,
data_out_cpu => data_out_cpu
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
wait for 10 ns;
pa <= '1';
sc <= '1';
wait for 10 ns;
rd_cpu<= '1';
wait for 10 ns;
data_bus<= "0001001000110100";
wait for 10 ns;
rd_cpu<= '0';
-- wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| unlicense | e24b84e56077dacc3ac62b21c3f71a5e | 0.566966 | 3.607914 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/axi_master_lite_v1_00_a/hdl/vhdl/axi_master_lite.vhd | 2 | 16,641 | -------------------------------------------------------------------------------
-- axi_master_lite.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_master_lite.vhd
--
-- Description:
--
-- This VHDL file is the top level design file for the (Lite) AXI Master
-- design that only supports single data beat transfers. This succeeds
-- the plbv46_master_single design.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_lite.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.1.2.3 $
-- Date: $12/01/2010$
--
-- History:
-- DET 12/01/2010 Initial Version
--
-- DET 12/14/2010 Initial
-- ~~~~~~
-- -- Per CR587090
-- - Removed the input port m_axi_rlast. It is not part of the AXI4-Lite
-- signal set.
-- ^^^^^^
--
-- DET 12/17/2010 Initial
-- ~~~~~~
-- -- Per CR587285
-- - Add _lite to AXI4 port names per DDS.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_master_lite_v1_00_a;
Use axi_master_lite_v1_00_a.axi_master_lite_reset;
Use axi_master_lite_v1_00_a.axi_master_lite_cntlr;
-------------------------------------------------------------------------------
entity axi_master_lite is
generic (
-- AXI4-Lite Parameters
C_M_AXI_LITE_ADDR_WIDTH : INTEGER range 32 to 32 := 32;
-- width of AXI4 Address Bus (in bits)
C_M_AXI_LITE_DATA_WIDTH : INTEGER range 32 to 32 := 32;
-- Width of the AXI4 Data Bus (in bits)
-- FPGA Family Parameter
C_FAMILY : String := "virtex6"
-- Select the target architecture type
-- see the family.vhd package in the proc_common
-- library
);
port (
-----------------------------------------------------------------------
-- Clock Input
-----------------------------------------------------------------------
m_axi_lite_aclk : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- Reset Input (active low)
-----------------------------------------------------------------------
m_axi_lite_aresetn : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- Master Detected Error output
-----------------------------------------------------------------------
md_error : out std_logic ;-- Discrete Out
----------------------------------------------------------------------------
-- AXI4 Read Channels
----------------------------------------------------------------------------
-- AXI4 Read Address Channel -- AXI4
m_axi_lite_arready : in std_logic ; -- AXI4
m_axi_lite_arvalid : out std_logic ; -- AXI4
m_axi_lite_araddr : out std_logic_vector -- AXI4
(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- AXI4
m_axi_lite_arprot : out std_logic_vector(2 downto 0) ; -- AXI4
-- AXI4
-- AXI4 Read Data Channel -- AXI4
m_axi_lite_rready : out std_logic ; -- AXI4
m_axi_lite_rvalid : in std_logic ; -- AXI4
m_axi_lite_rdata : in std_logic_vector -- AXI4
(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) ; -- AXI4
m_axi_lite_rresp : in std_logic_vector(1 downto 0) ; -- AXI4
-----------------------------------------------------------------------------
-- AXI4 Write Channels
-----------------------------------------------------------------------------
-- AXI4 Write Address Channel
m_axi_lite_awready : in std_logic ; -- AXI4
m_axi_lite_awvalid : out std_logic ; -- AXI4
m_axi_lite_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- AXI4
m_axi_lite_awprot : out std_logic_vector(2 downto 0) ; -- AXI4
-- AXI4
-- AXI4 Write Data Channel -- AXI4
m_axi_lite_wready : in std_logic ; -- AXI4
m_axi_lite_wvalid : out std_logic ; -- AXI4
m_axi_lite_wdata : out std_logic_vector -- AXI4
(C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- AXI4
m_axi_lite_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);-- AXI4
-- AXI4
-- AXI4 Write Response Channel -- AXI4
m_axi_lite_bready : out std_logic ; -- AXI4
m_axi_lite_bvalid : in std_logic ; -- AXI4
m_axi_lite_bresp : in std_logic_vector(1 downto 0) ; -- AXI4
-----------------------------------------------------------------------------
-- IP Master Request/Qualifers
-----------------------------------------------------------------------------
ip2bus_mstrd_req : In std_logic; -- IPIC
ip2bus_mstwr_req : In std_logic; -- IPIC
ip2bus_mst_addr : in std_logic_vector(0 to C_M_AXI_LITE_ADDR_WIDTH-1); -- IPIC
ip2bus_mst_be : in std_logic_vector(0 to (C_M_AXI_LITE_DATA_WIDTH/8)-1);-- IPIC
ip2bus_mst_lock : In std_logic; -- IPIC
ip2bus_mst_reset : In std_logic; -- IPIC
-- IPIC
-----------------------------------------------------------------------------
-- IP Request Status Reply
-----------------------------------------------------------------------------
bus2ip_mst_cmdack : Out std_logic; -- IPIC
bus2ip_mst_cmplt : Out std_logic; -- IPIC
bus2ip_mst_error : Out std_logic; -- IPIC
bus2ip_mst_rearbitrate : Out std_logic; -- IPIC
bus2ip_mst_cmd_timeout : out std_logic; -- IPIC
-- IPIC
-- IPIC
-----------------------------------------------------------------------------
-- IPIC Read data
-----------------------------------------------------------------------------
bus2ip_mstrd_d : out std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1); -- IPIC
bus2ip_mstrd_src_rdy_n : Out std_logic; -- IPIC
-- IPIC
-----------------------------------------------------------------------------
-- IPIC Write data
-----------------------------------------------------------------------------
ip2bus_mstwr_d : In std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1); -- IPIC
bus2ip_mstwr_dst_rdy_n : Out std_logic -- IPIC
);
end entity axi_master_lite;
architecture implementation of axi_master_lite is
-- Signals
signal sig_master_reset : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- Instance: I_RESET_MODULE
--
-- Description:
-- Instance for the Reset Module
--
------------------------------------------------------------
I_RESET_MODULE : entity axi_master_lite_v1_00_a.axi_master_lite_reset
port map (
-- Clock Input
axi_aclk => m_axi_lite_aclk ,
-- Reset Input (active low)
axi_aresetn => m_axi_lite_aresetn ,
-- IPIC Reset Input
ip2bus_mst_reset => ip2bus_mst_reset ,
-- Combined Reset Output
rst2ip_reset_out => sig_master_reset
);
------------------------------------------------------------
-- Instance: I_RD_WR_CNTLR
--
-- Description:
-- Instance for the Read/Write Controller Module
--
------------------------------------------------------------
I_RD_WR_CNTLR : entity axi_master_lite_v1_00_a.axi_master_lite_cntlr
generic map (
C_M_AXI_LITE_ADDR_WIDTH => C_M_AXI_LITE_ADDR_WIDTH,
C_M_AXI_LITE_DATA_WIDTH => C_M_AXI_LITE_DATA_WIDTH,
C_FAMILY => C_FAMILY
)
port map (
-----------------------------------
-- Clock Input
-----------------------------------
axi_aclk => m_axi_lite_aclk ,
-----------------------------------
-- Reset Input (active high)
-----------------------------------
axi_reset => sig_master_reset,
-----------------------------------
-- Master Detected Error output
-----------------------------------
md_error => md_error ,
-----------------------------------
-- AXI4 Read Channels
-----------------------------------
-- AXI4 Read Address Channel
m_axi_arready => m_axi_lite_arready ,
m_axi_arvalid => m_axi_lite_arvalid ,
m_axi_araddr => m_axi_lite_araddr ,
m_axi_arprot => m_axi_lite_arprot ,
-- AXI4 Read Data Channel
m_axi_rready => m_axi_lite_rready ,
m_axi_rvalid => m_axi_lite_rvalid ,
m_axi_rdata => m_axi_lite_rdata ,
m_axi_rresp => m_axi_lite_rresp ,
-----------------------------------
-- AXI4 Write Channels
-----------------------------------
-- AXI4 Write Address Channel
m_axi_awready => m_axi_lite_awready ,
m_axi_awvalid => m_axi_lite_awvalid ,
m_axi_awaddr => m_axi_lite_awaddr ,
m_axi_awprot => m_axi_lite_awprot ,
-- AXI4 Write Data Channel
m_axi_wready => m_axi_lite_wready ,
m_axi_wvalid => m_axi_lite_wvalid ,
m_axi_wdata => m_axi_lite_wdata ,
m_axi_wstrb => m_axi_lite_wstrb ,
-- AXI4 Write Response Channel
m_axi_bready => m_axi_lite_bready ,
m_axi_bvalid => m_axi_lite_bvalid ,
m_axi_bresp => m_axi_lite_bresp ,
-----------------------------------
-- IP Master Request/Qualifers
-----------------------------------
ip2bus_mstrd_req => ip2bus_mstrd_req ,
ip2bus_mstwr_req => ip2bus_mstwr_req ,
ip2bus_mst_addr => ip2bus_mst_addr ,
ip2bus_mst_be => ip2bus_mst_be ,
ip2bus_mst_lock => ip2bus_mst_lock ,
-----------------------------------
-- IP Request Status Reply
-----------------------------------
bus2ip_mst_cmdack => bus2ip_mst_cmdack ,
bus2ip_mst_cmplt => bus2ip_mst_cmplt ,
bus2ip_mst_error => bus2ip_mst_error ,
bus2ip_mst_rearbitrate => bus2ip_mst_rearbitrate ,
bus2ip_mst_cmd_timeout => bus2ip_mst_cmd_timeout ,
-----------------------------------
-- IPIC Read data
-----------------------------------
bus2ip_mstrd_d => bus2ip_mstrd_d ,
bus2ip_mstrd_src_rdy_n => bus2ip_mstrd_src_rdy_n ,
----------------------------------
-- IPIC Write data
----------------------------------
ip2bus_mstwr_d => ip2bus_mstwr_d ,
bus2ip_mstwr_dst_rdy_n => bus2ip_mstwr_dst_rdy_n
);
end implementation;
| bsd-3-clause | 67f8e27df05e2e841af17c47f775aa1e | 0.36993 | 5.14246 | false | false | false | false |
a4a881d4/zcpsm | src/example/eth_hub/vhd/ethtx_zcpsm/ethtx_zcpsm.vhd | 1 | 2,347 | ---------------------------------------------------------------------------------------------------
--
-- Title : ethtx_zcpsm
-- Design : eth_new
-- Author : a4a881d4
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : ethtx_zcpsm.vhd
-- Generated : Tue Aug 29 22:34:33 2006
-- From : interface description file
-- By : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description :
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ethtx_zcpsm is
port(
reset : in std_logic;
clk : in std_logic;
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0)
);
end ethtx_zcpsm;
--}} End of automatically maintained section
architecture behavior of ethtx_zcpsm is
component zcpsm
Port (
address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
component ethtxrom_romonly
port(
addrb : in std_logic_vector(11 downto 0);
clkb : in std_logic;
dob : out std_logic_vector(17 downto 0));
end component;
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
begin
u_tx_zcpsm : zcpsm
port map(
address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => '0',
reset => reset,
clk => clk
);
u_tx_rom : ethtxrom_romonly
port map(
addrb => address,
clkb => clk,
dob => instruction
);
end behavior;
| gpl-2.0 | 75505ddaf9564009de707fcca7a92e4a | 0.496804 | 3.357654 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/plb_hwt_exit_v1_00_a/hdl/vhdl/plb_hwt_exit.vhd | 2 | 10,401 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library plb_hwti_v1_00_a;
library plb_hwt_exit_v1_00_a;
use plb_hwti_v1_00_a.all;
entity plb_hwt_exit is
generic
(
C_MANAG_BASE : std_logic_vector := x"60000000";
C_SCHED_BASE : std_logic_vector := x"61000000";
C_MUTEX_BASE : std_logic_vector := x"75000000";
C_CONDV_BASE : std_logic_vector := x"74000000";
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
C_PLB_NUM_MASTERS : integer := 8;
C_PLB_MID_WIDTH : integer := 3;
C_FAMILY : string := "virtex2p"
);
port
(
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
Sl_addrAck : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_MErr : out std_logic_vector(0 to C_PLB_NUM_MASTERS-1);
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic;
PLB_abort : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_PLB_AWIDTH-1);
PLB_BE : in std_logic_vector(0 to C_PLB_DWIDTH/8-1);
PLB_busLock : in std_logic;
PLB_compress : in std_logic;
PLB_guarded : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_PLB_MID_WIDTH-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_ordered : in std_logic;
PLB_PAValid : in std_logic;
PLB_pendPri : in std_logic_vector(0 to 1);
PLB_pendReq : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_wrPrim : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_compress : out std_logic;
M_guarded : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_ordered : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MErr : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1)
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity plb_hwt_exit;
architecture imp of plb_hwt_exit is
signal HWTI2USER_READ : std_logic;
signal HWTI2USER_DATA : std_logic_vector(0 to 63);
signal HWTI2USER_CONTROL : std_logic;
signal HWTI2USER_EXISTS : std_logic;
signal USER2HWTI_WRITE : std_logic;
signal USER2HWTI_DATA : std_logic_vector(0 to 63);
signal USER2HWTI_CONTROL : std_logic;
signal USER2HWTI_FULL : std_logic;
signal U2HLOW_M_WRITE : std_logic;
signal U2HLOW_M_DATA : std_logic_vector(0 to 31);
signal U2HLOW_M_CONTROL : std_logic;
signal U2HLOW_M_FULL : std_logic;
signal U2HHIGH_M_WRITE : std_logic;
signal U2HHIGH_M_DATA : std_logic_vector(0 to 31);
signal U2HHIGH_M_CONTROL : std_logic;
signal U2HHIGH_M_FULL : std_logic;
signal H2ULOW_S_READ : std_logic;
signal H2ULOW_S_DATA : std_logic_vector(0 to 31);
signal H2ULOW_S_CONTROL : std_logic;
signal H2ULOW_S_EXISTS : std_logic;
signal H2UHIGH_S_READ : std_logic;
signal H2UHIGH_S_DATA : std_logic_vector(0 to 31);
signal H2UHIGH_S_CONTROL : std_logic;
signal H2UHIGH_S_EXISTS : std_logic;
begin
ihwti : entity plb_hwti_v1_00_a.plb_hwti
generic map
(
C_MANAG_BASE => C_MANAG_BASE,
C_SCHED_BASE => C_SCHED_BASE,
C_MUTEX_BASE => C_MUTEX_BASE,
C_CONDV_BASE => C_CONDV_BASE,
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_PLB_AWIDTH => C_PLB_AWIDTH,
C_PLB_DWIDTH => C_PLB_DWIDTH,
C_PLB_NUM_MASTERS => C_PLB_NUM_MASTERS,
C_PLB_MID_WIDTH => C_PLB_MID_WIDTH,
C_FAMILY => C_FAMILY
)
port map
(
U2HLOW_M_WRITE => U2HLOW_M_WRITE,
U2HLOW_M_DATA => U2HLOW_M_DATA,
U2HLOW_M_CONTROL => U2HLOW_M_CONTROL,
U2HLOW_M_FULL => U2HLOW_M_FULL,
U2HHIGH_M_WRITE => U2HHIGH_M_WRITE,
U2HHIGH_M_DATA => U2HHIGH_M_DATA,
U2HHIGH_M_CONTROL => U2HHIGH_M_CONTROL,
U2HHIGH_M_FULL => U2HHIGH_M_FULL,
H2ULOW_S_READ => H2ULOW_S_READ,
H2ULOW_S_DATA => H2ULOW_S_DATA,
H2ULOW_S_CONTROL => H2ULOW_S_CONTROL,
H2ULOW_S_EXISTS => H2ULOW_S_EXISTS,
H2UHIGH_S_READ => H2UHIGH_S_READ,
H2UHIGH_S_DATA => H2UHIGH_S_DATA,
H2UHIGH_S_CONTROL => H2UHIGH_S_CONTROL,
H2UHIGH_S_EXISTS => H2UHIGH_S_EXISTS,
PLB_Clk => PLB_Clk,
PLB_Rst => PLB_Rst,
Sl_addrAck => Sl_addrAck,
Sl_MBusy => Sl_MBusy,
Sl_MErr => Sl_MErr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
PLB_abort => PLB_abort,
PLB_ABus => PLB_ABus,
PLB_BE => PLB_BE,
PLB_busLock => PLB_busLock,
PLB_compress => PLB_compress,
PLB_guarded => PLB_guarded,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_ordered => PLB_ordered,
PLB_PAValid => PLB_PAValid,
PLB_pendPri => PLB_pendPri,
PLB_pendReq => PLB_pendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
M_abort => M_abort,
M_ABus => M_ABus,
M_BE => M_BE,
M_busLock => M_busLock,
M_compress => M_compress,
M_guarded => M_guarded,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_ordered => M_ordered,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_RNW => M_RNW,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
PLB_MBusy => PLB_MBusy,
PLB_MErr => PLB_MErr,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MSSize => PLB_MSSize
);
ihwt : entity plb_hwt_exit_v1_00_a.hwtexit
port map
(
clk => PLB_Clk,
rst => PLB_Rst,
HWTI2USER_READ => HWTI2USER_READ,
HWTI2USER_DATA => HWTI2USER_DATA,
HWTI2USER_CONTROL => HWTI2USER_CONTROL,
HWTI2USER_EXISTS => HWTI2USER_EXISTS,
USER2HWTI_WRITE => USER2HWTI_WRITE,
USER2HWTI_DATA => USER2HWTI_DATA,
USER2HWTI_CONTROL => USER2HWTI_CONTROL,
USER2HWTI_FULL => USER2HWTI_FULL
);
H2ULOW_S_READ <= HWTI2USER_READ;
H2UHIGH_S_READ <= HWTI2USER_READ;
HWTI2USER_DATA <= H2UHIGH_S_DATA & H2ULOW_S_DATA;
HWTI2USER_CONTROL <= H2UHIGH_S_CONTROL or H2ULOW_S_CONTROL;
HWTI2USER_EXISTS <= H2UHIGH_S_EXISTS and H2ULOW_S_EXISTS;
U2HLOW_M_WRITE <= USER2HWTI_WRITE;
U2HHIGH_M_WRITE <= USER2HWTI_WRITE;
U2HLOW_M_DATA <= USER2HWTI_DATA(32 to 63);
U2HHIGH_M_DATA <= USER2HWTI_DATA(0 to 31);
U2HLOW_M_CONTROL <= USER2HWTI_CONTROL;
U2HHIGH_M_CONTROL <= USER2HWTI_CONTROL;
USER2HWTI_FULL <= U2HLOW_M_FULL or U2HHIGH_M_FULL;
end imp;
| bsd-3-clause | 9f80adb1fee0af7c0cece8337aafa4bd | 0.521681 | 3.115004 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/srl16_fifo.vhd | 2 | 13,095 | -------------------------------------------------------------------------------
-- $Id: srl16_fifo.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl16_fifo.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl16_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl16_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: D.Thorpe
--
-- History:
-- DET 2001-10-11 First Version adapted from Goran B. srl_fifo.vhd
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Bus_clk", "Bus_clk_div#", "Bus_clk_#x"
-- Bus_rst signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.pf_adder;
use proc_common_v3_00_a.pf_counter_top;
use proc_common_v3_00_a.pf_occ_counter_top;
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
entity srl16_fifo is
generic (
C_FIFO_WIDTH : integer range 1 to 128 := 8;
-- Width of FIFO Data Bus
C_FIFO_DEPTH_LOG2X : integer range 2 to 4 := 4;
-- Depth of FIFO in address bit width
-- ie 4 = 16 locations deep
-- 3 = 8 locations deep
-- 2 = 4 ocations deep
C_INCLUDE_VACANCY : Boolean := true
-- Command to include vacancy calculation
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
Wr_Req : in std_logic;
Wr_Data : in std_logic_vector(0 to C_FIFO_WIDTH-1);
Rd_Req : in std_logic;
Rd_Data : out std_logic_vector(0 to C_FIFO_WIDTH-1);
Full : out std_logic;
Almostfull : Out std_logic;
Empty : Out std_logic;
Almostempty : Out std_logic;
Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X)
);
end entity srl16_fifo;
-------------------------------------------------------------------------------
architecture implementation of srl16_fifo is
Signal sig_occupancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_occ_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_addr_load_value : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
Signal sig_logic_low : std_logic;
signal sig_almost_full : std_logic;
signal sig_full : std_logic;
signal sig_almost_empty : std_logic;
signal sig_empty : std_logic;
signal sig_valid_write : std_logic;
signal sig_inc_addr : std_logic;
signal sig_dec_addr : std_logic;
signal sig_valid_read : std_logic;
signal sig_addr : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X-1);
signal sig_srl_addr : std_logic_vector(0 to 3);
signal sig_addr_is_nonzero : std_logic;
signal sig_addr_is_zero : std_logic;
begin -- architecture implementation
-- Misc I/O
Full <= sig_full;
Almostfull <= sig_almost_full;
Empty <= sig_empty;
Almostempty <= sig_almost_empty;
Occupancy <= sig_occupancy;
----------------------------------------------------------------------------
-- Occupancy Counter Function
----------------------------------------------------------------------------
sig_occ_load_value <= (others => '0');
sig_logic_low <= '0';
I_OCCUPANCY_CNTR : entity proc_common_v3_00_a.pf_occ_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X+1
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_occ_load_value,
Count_Down => sig_valid_read,
Count_Up => sig_valid_write,
By_2 => sig_logic_low,
Count_Out => sig_occupancy,
almost_full => sig_almost_full,
full => sig_full,
almost_empty => sig_almost_empty,
empty => sig_empty
);
----------------------------------------------------------------------------
-- Address Counter Function
----------------------------------------------------------------------------
sig_addr_load_value <= (others => '0');
sig_addr_is_nonzero <= (sig_srl_addr(0)
or sig_srl_addr(1)
or sig_srl_addr(2)
or sig_srl_addr(3));
sig_addr_is_zero <= not(sig_addr_is_nonzero);
sig_valid_write <= Wr_Req and not(sig_full);
sig_valid_read <= Rd_Req and not(sig_empty);
sig_inc_addr <= (sig_valid_write and not(sig_empty))
and not(sig_valid_read and sig_addr_is_zero);
sig_dec_addr <= sig_valid_read and sig_addr_is_nonzero;
I_ADDR_CNTR : entity proc_common_v3_00_a.pf_counter_top
generic map(
C_COUNT_WIDTH => C_FIFO_DEPTH_LOG2X
)
port map(
Clk => Bus_clk,
Rst => Bus_rst,
Load_Enable => sig_logic_low,
Load_value => sig_addr_load_value,
Count_Down => sig_dec_addr,
Count_Up => sig_inc_addr,
Count_Out => sig_addr
);
ASSIGN_ADDRESS : process(sig_addr)
Begin
sig_srl_addr <= (others => '0'); -- assign default values
for i in 0 to C_FIFO_DEPTH_LOG2X-1 loop
sig_srl_addr((4-C_FIFO_DEPTH_LOG2X)+i) <= sig_addr(i);
end loop;
end process ASSIGN_ADDRESS;
----------------------------------------------------------------------------
-- SRL memory function
----------------------------------------------------------------------------
FIFO_RAM : for i in 0 to C_FIFO_WIDTH-1 generate
I_SRL16E : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => sig_valid_write,
D => Wr_Data(i),
Clk => Bus_clk,
A0 => sig_srl_addr(3),
A1 => sig_srl_addr(2),
A2 => sig_srl_addr(1),
A3 => sig_srl_addr(0),
Q => Rd_Data(i)
);
end generate FIFO_RAM;
INCLUDE_VACANCY : if (C_INCLUDE_VACANCY = true) generate
Constant REGISTER_VACANCY : boolean := false;
Constant OCC_CNTR_WIDTH : integer := C_FIFO_DEPTH_LOG2X+1;
Constant MAX_OCCUPANCY : integer := 2**C_FIFO_DEPTH_LOG2X;
Signal slv_max_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
Signal int_vacancy : std_logic_vector(0 to OCC_CNTR_WIDTH-1);
begin
Vacancy <= int_vacancy; -- set to zeroes for now.
slv_max_vacancy <= CONV_STD_LOGIC_VECTOR(MAX_OCCUPANCY, OCC_CNTR_WIDTH);
I_VAC_CALC : entity proc_common_v3_00_a.pf_adder
generic map(
C_REGISTERED_RESULT => REGISTER_VACANCY,
C_COUNT_WIDTH => OCC_CNTR_WIDTH
)
port map (
Clk => Bus_Clk,
Rst => Bus_rst,
Ain => slv_max_vacancy,
Bin => sig_occupancy,
Add_sub_n => '0', -- always subtract
result_out => int_vacancy
);
end generate; -- INCLUDE_VACANCY
OMIT_VACANCY : if (C_INCLUDE_VACANCY = false) generate
Signal int_vacancy : std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
begin
int_vacancy <= (others => '0');
Vacancy <= int_vacancy; -- set to zeroes for now.
end generate; -- INCLUDE_VACANCY
end architecture implementation;
| bsd-3-clause | 3bb5a938e5ffcf7f0bad6af1d6658b7a | 0.453761 | 4.381064 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_v1_00_a/hdl/vhdl/user_logics/functional/mutex_destroy_3.vhd | 2 | 15,583 | ---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- mutex_destroy_3.c
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- hthread_mutex_t * mtuex= (hthread_mutex_t *) arg
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
-- hthread_mutex_init( mutex, NULL );
when STATE_1 =>
-- Push NULL
arg_next <= intrfc2thrd_value;
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
-- Push mutex
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_3;
when STATE_3 =>
-- Call hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_INIT;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_4;
next_state <= WAIT_STATE;
-- retVal = hthread_mutex_destroy( mutex );
when STATE_4 =>
-- Push the argument to hthread_mutex_init
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- Call hthread_mutex_destroy
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_MUTEX_DESTROY;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_6;
next_state <= WAIT_STATE;
when STATE_6 =>
retVal_next <= intrfc2thrd_value;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | cdb39f6b1787df944b7ebb734090cd50 | 0.541359 | 3.826866 | false | false | false | false |
jevinskie/aes-over-pcie | source/tb_fifo.vhd | 1 | 3,174 | -- File name: tb_fifo.vhd
-- Created: 2009-04-20 (^-^)y-~~'`
-- Author: Jevin Sweval
-- Lab Section: 337-02
-- Version: 1.0 Initial Design Entry
-- Description: FIFO test bench
use work.aes.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_fifo is
generic (
clk_per : time := 4 ns;
size : positive := 32
);
end tb_fifo;
architecture test of tb_fifo is
-- dut and gold model signals
signal clk : std_logic := '0';
signal nrst : std_logic := '1';
signal re : std_logic := '0';
signal we : std_logic := '0';
signal w_data : byte;
signal r_data : byte;
signal empty : std_logic;
signal full : std_logic;
-- clock only runs when stop isnt asserted
signal stop : std_logic := '1';
procedure store (
constant d : in byte;
signal w_enable : out std_logic;
signal w_data : out byte
) is
begin
w_data <= d;
w_enable <= '1';
wait for clk_per;
w_enable <= '0';
end procedure store;
procedure get (
variable d : out byte;
signal r_enable : out std_logic;
signal r_data : in byte
) is
begin
d := r_data;
r_enable <= '1';
wait for clk_per;
r_enable <= '0';
end procedure get;
begin
dut : entity work.fifo(behavioral)
--generic map (
--size => size
--)
port map (
clk => clk,
nrst => nrst,
re => re,
we => we,
w_data => w_data,
r_data => r_data,
empty => empty,
full => full
);
-- main test bench code
-- clock when stop isnt asserted
clk <= not clk and not stop after clk_per/2;
process
variable d : byte;
begin
wait for clk_per*5;
-- start the clock
stop <= '0';
-- reset the device
nrst <= '0';
wait for clk_per;
nrst <= '1';
assert empty = '1';
assert full = '0';
-- fill the buffer up
for i in 0 to size-2 loop
store(to_unsigned(i, 8), we, w_data);
wait for clk_per*5;
assert empty = '0';
end loop;
-- we better be full now
assert full = '1';
-- get all that shiz out
for i in 0 to size-2 loop
get(d, re, r_data);
wait for clk_per*5;
assert full = '0';
-- make sure we get back what we put in
assert d = to_unsigned(i, 8);
end loop;
-- we better be empty now
assert empty = '1';
-- overflow the fifo for fun...
for i in 0 to size*2-2 loop
store(to_unsigned(i, 8), we, w_data);
wait for clk_per*5;
assert empty = '0';
if i > size-2 then
assert full = '1';
end if;
end loop;
-- ... and see what comes out
for i in 0 to size*2-2 loop
get(d, re, r_data);
wait for clk_per*5;
assert full = '0';
if i > size*2-2 then
assert empty = '1';
end if;
end loop;
wait for clk_per*5;
-- stop the clock
stop <= '1';
wait for clk_per*5;
wait;
end process;
end test;
| bsd-3-clause | 50cd8e677a5503a0217b619cc85125ce | 0.508507 | 3.416577 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/hw_acc_vector_v1_00_a/hdl/vhdl/hw_acc_vector.vhd | 2 | 4,996 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_vector is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : out std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : in std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_vector;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_vector is
component vector_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal ap_rst : STD_LOGIC;
-- Architecture Section
begin
ap_rst <= not ap_rst_n;
uut : vector_chan
port map (
Vector_A_addr0 => BRAM_A_addr,
Vector_A_dIN0 => BRAM_A_din,
Vector_A_dOUT0 => BRAM_A_dout,
Vector_A_rENA0 => BRAM_A_en,
Vector_A_wENA0 => BRAM_A_wen,
Vector_B_addr0 => BRAM_B_addr,
Vector_B_dIN0 => BRAM_B_din,
Vector_B_dOUT0 => BRAM_B_dout,
Vector_B_rENA0 => BRAM_B_en,
Vector_B_wENA0 => BRAM_B_wen,
Vector_C_addr0 => BRAM_C_addr,
Vector_C_dIN0 => BRAM_C_din,
Vector_C_dOUT0 => BRAM_C_dout,
Vector_C_rENA0 => BRAM_C_en,
Vector_C_wENA0 => BRAM_C_wen,
chan1_channelDataIn => M_AXIS_TDATA,
chan1_channelDataOut => S_AXIS_TDATA,
chan1_exists => S_AXIS_Tvalid,
chan1_full => not M_AXIS_Tready,
chan1_channelRead => S_AXIS_Tready,
chan1_channelWrite => M_AXIS_tvalid,
clock_sig => ap_clk,
reset_sig => ap_rst
);
end architecture implementation;
| bsd-3-clause | 57107973b5d7c14bb380e02f9c7ba5b4 | 0.578663 | 2.966746 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/hdl_crc_v1_00_a/hdl/hdl_crc.vhd | 2 | 3,923 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hdl_crc is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : out std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : in std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hdl_crc;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hdl_crc is
component crc is
port
(
array_addr0 : out std_logic_vector(0 to (32 - 1));
array_dIN0 : out std_logic_vector(0 to (32- 1));
array_dOUT0 : in std_logic_vector(0 to (32 - 1));
array_rENA0 : out std_logic;
array_wENA0 : out std_logic_vector(0 to (32/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal ap_rst : STD_LOGIC;
-- Architecture Section
begin
ap_rst <= not ap_rst_n;
uut : crc
port map (
array_addr0 => BRAM_A_addr,
array_dIN0 => BRAM_A_din,
array_dOUT0 => BRAM_A_dout,
array_rENA0 => BRAM_A_en,
array_wENA0 => BRAM_A_wen,
chan1_channelDataIn => M_AXIS_TDATA,
chan1_channelDataOut => S_AXIS_TDATA,
chan1_exists => S_AXIS_Tvalid,
chan1_full => not M_AXIS_Tready,
chan1_channelRead => S_AXIS_Tready,
chan1_channelWrite => M_AXIS_tvalid,
clock_sig => ap_clk,
reset_sig => ap_rst
);
end architecture implementation;
| bsd-3-clause | bc5c5c16f829f33d4083d098d45752f3 | 0.554932 | 3.228807 | false | false | false | false |
Nibble-Knowledge/peripheral-ide | IDE/IDE3_write/shift_reg.vhd | 1 | 1,615 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:43:15 11/10/2015
-- Design Name:
-- Module Name: shift_reg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SHIFT_REGISTER is
--Generic( CAPACITY : integer := 16);
Port ( CLK : in STD_LOGIC;
DATA : in STD_LOGIC_vector(3 downto 0);
RESET,enable : in STD_LOGIC;
OUTPUT : out STD_LOGIC_vector(15 downto 0)
);
end SHIFT_REGISTER;
architecture Behavioral of SHIFT_REGISTER is
signal reg: Std_Logic_Vector(15 downto 0):=(others=>'0');
begin
process(CLK,RESET)
begin
if RESET = '1' then
reg<=(others=>'0');
elsif (rising_edge(CLK)) and (enable = '1') then
reg<= reg(11 downto 0) & DATA ; --&= concatenation
end if;
end process;
OUTPUT<=reg(15 downto 0 );
end Behavioral;
| unlicense | f8fa051a1187fc09978aec2731e99f1f | 0.520743 | 4.21671 | false | false | false | false |
a4a881d4/zcpsm | src/example/Q7Led/vhd/ARM.vhd | 1 | 57,119 | --Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:24:04 MST 2014
--Date : Sun Mar 01 22:41:07 2015
--Host : dodo-PC running 64-bit Service Pack 1 (build 7601)
--Command : generate_target ARM.bd
--Design : ARM
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_K5P28A is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_K5P28A;
architecture STRUCTURE of s00_couplers_imp_K5P28A is
component ARM_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component ARM_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(12 downto 0) <= auto_pc_to_s00_couplers_ARADDR(12 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(12 downto 0) <= auto_pc_to_s00_couplers_AWADDR(12 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component ARM_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ARM_axi_mem_intercon_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 12 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end ARM_axi_mem_intercon_0;
architecture STRUCTURE of ARM_axi_mem_intercon_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_ACLK_net : STD_LOGIC;
signal axi_mem_intercon_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_mem_intercon_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_mem_intercon_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal s00_couplers_to_axi_mem_intercon_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_mem_intercon_ARREADY : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_ARVALID : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal s00_couplers_to_axi_mem_intercon_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_mem_intercon_AWREADY : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_AWVALID : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_BREADY : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_mem_intercon_BVALID : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_mem_intercon_RREADY : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_mem_intercon_RVALID : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_mem_intercon_WREADY : STD_LOGIC;
signal s00_couplers_to_axi_mem_intercon_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_mem_intercon_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(12 downto 0) <= s00_couplers_to_axi_mem_intercon_ARADDR(12 downto 0);
M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0);
M00_AXI_arvalid <= s00_couplers_to_axi_mem_intercon_ARVALID;
M00_AXI_awaddr(12 downto 0) <= s00_couplers_to_axi_mem_intercon_AWADDR(12 downto 0);
M00_AXI_awprot(2 downto 0) <= s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0);
M00_AXI_awvalid <= s00_couplers_to_axi_mem_intercon_AWVALID;
M00_AXI_bready <= s00_couplers_to_axi_mem_intercon_BREADY;
M00_AXI_rready <= s00_couplers_to_axi_mem_intercon_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_axi_mem_intercon_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0);
M00_AXI_wvalid <= s00_couplers_to_axi_mem_intercon_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_mem_intercon_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_mem_intercon_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= axi_mem_intercon_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_mem_intercon_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= axi_mem_intercon_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= axi_mem_intercon_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_mem_intercon_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_mem_intercon_to_s00_couplers_WREADY;
axi_mem_intercon_ACLK_net <= M00_ACLK;
axi_mem_intercon_ARESETN_net(0) <= M00_ARESETN(0);
axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_mem_intercon_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_mem_intercon_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_mem_intercon_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_mem_intercon_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
axi_mem_intercon_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_mem_intercon_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_axi_mem_intercon_ARREADY <= M00_AXI_arready;
s00_couplers_to_axi_mem_intercon_AWREADY <= M00_AXI_awready;
s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_axi_mem_intercon_BVALID <= M00_AXI_bvalid;
s00_couplers_to_axi_mem_intercon_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_axi_mem_intercon_RVALID <= M00_AXI_rvalid;
s00_couplers_to_axi_mem_intercon_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_K5P28A
port map (
M_ACLK => axi_mem_intercon_ACLK_net,
M_ARESETN(0) => axi_mem_intercon_ARESETN_net(0),
M_AXI_araddr(12 downto 0) => s00_couplers_to_axi_mem_intercon_ARADDR(12 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_axi_mem_intercon_ARREADY,
M_AXI_arvalid => s00_couplers_to_axi_mem_intercon_ARVALID,
M_AXI_awaddr(12 downto 0) => s00_couplers_to_axi_mem_intercon_AWADDR(12 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_axi_mem_intercon_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_axi_mem_intercon_AWREADY,
M_AXI_awvalid => s00_couplers_to_axi_mem_intercon_AWVALID,
M_AXI_bready => s00_couplers_to_axi_mem_intercon_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_axi_mem_intercon_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_axi_mem_intercon_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_axi_mem_intercon_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_mem_intercon_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_axi_mem_intercon_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_axi_mem_intercon_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_axi_mem_intercon_WREADY,
M_AXI_wstrb(3 downto 0) => s00_couplers_to_axi_mem_intercon_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_axi_mem_intercon_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => axi_mem_intercon_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => axi_mem_intercon_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_mem_intercon_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_mem_intercon_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_mem_intercon_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => axi_mem_intercon_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => axi_mem_intercon_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_mem_intercon_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_mem_intercon_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_mem_intercon_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_mem_intercon_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => axi_mem_intercon_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => axi_mem_intercon_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_mem_intercon_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => axi_mem_intercon_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => axi_mem_intercon_to_s00_couplers_RLAST,
S_AXI_rready => axi_mem_intercon_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_mem_intercon_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_mem_intercon_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_mem_intercon_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => axi_mem_intercon_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => axi_mem_intercon_to_s00_couplers_WLAST,
S_AXI_wready => axi_mem_intercon_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_mem_intercon_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_mem_intercon_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ARM is
port (
BRAM_PORTA_addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
BRAM_PORTA_clk : out STD_LOGIC;
BRAM_PORTA_din : out STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_dout : in STD_LOGIC_VECTOR ( 31 downto 0 );
BRAM_PORTA_en : out STD_LOGIC;
BRAM_PORTA_rst : out STD_LOGIC;
BRAM_PORTA_we : out STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end ARM;
architecture STRUCTURE of ARM is
component ARM_arm_0 is
port (
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component ARM_arm_0;
component ARM_armbus_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 12 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 12 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component ARM_armbus_0;
component ARM_rst_arm_40M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component ARM_rst_arm_40M_0;
signal GND_1 : STD_LOGIC;
signal VCC_1 : STD_LOGIC;
signal arm_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal arm_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal arm_DDR_CAS_N : STD_LOGIC;
signal arm_DDR_CKE : STD_LOGIC;
signal arm_DDR_CK_N : STD_LOGIC;
signal arm_DDR_CK_P : STD_LOGIC;
signal arm_DDR_CS_N : STD_LOGIC;
signal arm_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal arm_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal arm_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal arm_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal arm_DDR_ODT : STD_LOGIC;
signal arm_DDR_RAS_N : STD_LOGIC;
signal arm_DDR_RESET_N : STD_LOGIC;
signal arm_DDR_WE_N : STD_LOGIC;
signal arm_FCLK_CLK0 : STD_LOGIC;
signal arm_FCLK_RESET0_N : STD_LOGIC;
signal arm_FIXED_IO_DDR_VRN : STD_LOGIC;
signal arm_FIXED_IO_DDR_VRP : STD_LOGIC;
signal arm_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal arm_FIXED_IO_PS_CLK : STD_LOGIC;
signal arm_FIXED_IO_PS_PORB : STD_LOGIC;
signal arm_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal arm_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal arm_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal arm_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal arm_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal arm_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal arm_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal arm_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal arm_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal arm_M_AXI_GP0_ARREADY : STD_LOGIC;
signal arm_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal arm_M_AXI_GP0_ARVALID : STD_LOGIC;
signal arm_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal arm_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal arm_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal arm_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal arm_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal arm_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal arm_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal arm_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal arm_M_AXI_GP0_AWREADY : STD_LOGIC;
signal arm_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal arm_M_AXI_GP0_AWVALID : STD_LOGIC;
signal arm_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal arm_M_AXI_GP0_BREADY : STD_LOGIC;
signal arm_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal arm_M_AXI_GP0_BVALID : STD_LOGIC;
signal arm_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal arm_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal arm_M_AXI_GP0_RLAST : STD_LOGIC;
signal arm_M_AXI_GP0_RREADY : STD_LOGIC;
signal arm_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal arm_M_AXI_GP0_RVALID : STD_LOGIC;
signal arm_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal arm_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal arm_M_AXI_GP0_WLAST : STD_LOGIC;
signal arm_M_AXI_GP0_WREADY : STD_LOGIC;
signal arm_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal arm_M_AXI_GP0_WVALID : STD_LOGIC;
signal armbus_BRAM_PORTA_ADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal armbus_BRAM_PORTA_CLK : STD_LOGIC;
signal armbus_BRAM_PORTA_DIN : STD_LOGIC_VECTOR ( 31 downto 0 );
signal armbus_BRAM_PORTA_DOUT : STD_LOGIC_VECTOR ( 31 downto 0 );
signal armbus_BRAM_PORTA_EN : STD_LOGIC;
signal armbus_BRAM_PORTA_RST : STD_LOGIC;
signal armbus_BRAM_PORTA_WE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal axi_mem_intercon_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_ARREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_ARVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 12 downto 0 );
signal axi_mem_intercon_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_mem_intercon_M00_AXI_AWREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_AWVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_BVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_RREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_mem_intercon_M00_AXI_RVALID : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_mem_intercon_M00_AXI_WREADY : STD_LOGIC;
signal axi_mem_intercon_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_mem_intercon_M00_AXI_WVALID : STD_LOGIC;
signal rst_arm_40M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_arm_40M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_arm_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_arm_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_arm_40M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_arm_40M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_arm_40M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
begin
BRAM_PORTA_addr(12 downto 0) <= armbus_BRAM_PORTA_ADDR(12 downto 0);
BRAM_PORTA_clk <= armbus_BRAM_PORTA_CLK;
BRAM_PORTA_din(31 downto 0) <= armbus_BRAM_PORTA_DIN(31 downto 0);
BRAM_PORTA_en <= armbus_BRAM_PORTA_EN;
BRAM_PORTA_rst <= armbus_BRAM_PORTA_RST;
BRAM_PORTA_we(3 downto 0) <= armbus_BRAM_PORTA_WE(3 downto 0);
armbus_BRAM_PORTA_DOUT(31 downto 0) <= BRAM_PORTA_dout(31 downto 0);
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
arm: component ARM_arm_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => arm_FCLK_CLK0,
FCLK_RESET0_N => arm_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => arm_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => arm_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => arm_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => arm_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => arm_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => arm_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => arm_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => arm_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => arm_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => arm_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => arm_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => arm_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => arm_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => arm_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => arm_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => arm_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => arm_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => arm_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => arm_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => arm_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => arm_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => arm_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => arm_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => arm_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => arm_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => arm_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => arm_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => arm_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => arm_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => arm_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => arm_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => arm_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => arm_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => arm_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => arm_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => arm_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => arm_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => arm_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => arm_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
USB0_PORT_INDCTL(1 downto 0) => NLW_arm_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => GND_1,
USB0_VBUS_PWRSELECT => NLW_arm_USB0_VBUS_PWRSELECT_UNCONNECTED
);
armbus: component ARM_armbus_0
port map (
bram_addr_a(12 downto 0) => armbus_BRAM_PORTA_ADDR(12 downto 0),
bram_clk_a => armbus_BRAM_PORTA_CLK,
bram_en_a => armbus_BRAM_PORTA_EN,
bram_rddata_a(31 downto 0) => armbus_BRAM_PORTA_DOUT(31 downto 0),
bram_rst_a => armbus_BRAM_PORTA_RST,
bram_we_a(3 downto 0) => armbus_BRAM_PORTA_WE(3 downto 0),
bram_wrdata_a(31 downto 0) => armbus_BRAM_PORTA_DIN(31 downto 0),
s_axi_aclk => arm_FCLK_CLK0,
s_axi_araddr(12 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(12 downto 0),
s_axi_aresetn => rst_arm_40M_peripheral_aresetn(0),
s_axi_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
s_axi_arready => axi_mem_intercon_M00_AXI_ARREADY,
s_axi_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
s_axi_awaddr(12 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(12 downto 0),
s_axi_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
s_axi_awready => axi_mem_intercon_M00_AXI_AWREADY,
s_axi_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
s_axi_bready => axi_mem_intercon_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_mem_intercon_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
s_axi_rready => axi_mem_intercon_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_mem_intercon_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
s_axi_wready => axi_mem_intercon_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_mem_intercon_M00_AXI_WVALID
);
axi_mem_intercon: entity work.ARM_axi_mem_intercon_0
port map (
ACLK => arm_FCLK_CLK0,
ARESETN(0) => rst_arm_40M_interconnect_aresetn(0),
M00_ACLK => arm_FCLK_CLK0,
M00_ARESETN(0) => rst_arm_40M_peripheral_aresetn(0),
M00_AXI_araddr(12 downto 0) => axi_mem_intercon_M00_AXI_ARADDR(12 downto 0),
M00_AXI_arprot(2 downto 0) => axi_mem_intercon_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready => axi_mem_intercon_M00_AXI_ARREADY,
M00_AXI_arvalid => axi_mem_intercon_M00_AXI_ARVALID,
M00_AXI_awaddr(12 downto 0) => axi_mem_intercon_M00_AXI_AWADDR(12 downto 0),
M00_AXI_awprot(2 downto 0) => axi_mem_intercon_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready => axi_mem_intercon_M00_AXI_AWREADY,
M00_AXI_awvalid => axi_mem_intercon_M00_AXI_AWVALID,
M00_AXI_bready => axi_mem_intercon_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_mem_intercon_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_mem_intercon_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_mem_intercon_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => axi_mem_intercon_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_mem_intercon_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_mem_intercon_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_mem_intercon_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => axi_mem_intercon_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_mem_intercon_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_mem_intercon_M00_AXI_WVALID,
S00_ACLK => arm_FCLK_CLK0,
S00_ARESETN(0) => rst_arm_40M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => arm_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => arm_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => arm_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => arm_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => arm_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => arm_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => arm_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => arm_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => arm_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => arm_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => arm_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => arm_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => arm_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => arm_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => arm_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => arm_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => arm_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => arm_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => arm_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => arm_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => arm_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => arm_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => arm_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => arm_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => arm_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => arm_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => arm_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => arm_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => arm_M_AXI_GP0_RLAST,
S00_AXI_rready => arm_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => arm_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => arm_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => arm_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => arm_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => arm_M_AXI_GP0_WLAST,
S00_AXI_wready => arm_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => arm_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => arm_M_AXI_GP0_WVALID
);
rst_arm_40M: component ARM_rst_arm_40M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_arm_40M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => VCC_1,
ext_reset_in => arm_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_arm_40M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_arm_40M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_arm_40M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_arm_40M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => arm_FCLK_CLK0
);
end STRUCTURE;
| gpl-2.0 | d8b040dd824572cdc3878b5533189be9 | 0.663667 | 2.800637 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/ipif_steer.vhd | 3 | 22,542 | --SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_steer.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
-------------------------------------------------------------------------------
-- IPIF_Steer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic steers data from the correct byte
-- lane to IPIF devices which may be smaller than the bus
-- width. The BE signals are also steered if the BE_Steer
-- signal is asserted, which indicates that the address space
-- being accessed has a smaller maximum data transfer size
-- than the bus size.
--
-- For writes, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer.vhd
--
-------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2-5-2002 -- First version
-- ^^^^^^
-- First version of IPIF steering logic.
-- ~~~~~~
-- BLT 2-12-2002 -- Removed BE_Steer, now generated internally
--
-- DET 2-24-2002 -- Added 'When others' to size case statement
-- in BE_STEER_PROC process.
--
-- BLT 10-10-2002 -- Rewrote to get around some XST synthesis
-- issues.
--
-- BLT 11-18-2002 -- Added addr_bits to sensitivity lists to
-- fix simulation bug
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of host databus attached to the IPIF
-- C_SMALLEST : integer := width of smallest device (not access size)
-- attached to the IPIF
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of MAXIMUM data access allowed to
-- a particular address map decode.
--
-- Size indication (Decode_size)
-- 001 - byte
-- 010 - halfword
-- 011 - word
-- 100 - doubleword
-- 101 - 128-b
-- 110 - 256-b
-- 111 - 512-b
-- num_bytes = 2^(n-1)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity IPIF_Steer is
generic (
C_DWIDTH : integer := 32; -- 8, 16, 32, 64
C_SMALLEST : integer := 32; -- 8, 16, 32, 64
C_AWIDTH : integer := 32
);
port (
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Addr : in std_logic_vector(0 to C_AWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Decode_size : in std_logic_vector(0 to 2);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity IPIF_Steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of IPIF_Steer is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-----------------------------------------------------------------------------
-- OPB Data Muxing and Steering
-----------------------------------------------------------------------------
-- GEN_DWIDTH_SMALLEST
GEN_SAME: if C_DWIDTH = C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
GEN_16_8: if C_DWIDTH = 16 and C_SMALLEST = 8 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-1);
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1) <= '0';
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_16_8;
GEN_32_8: if C_DWIDTH = 32 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2 to C_AWIDTH-1); --a30 to a31
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when "010" => --HW
Rd_Data_Out(8 to 15) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 3) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(1) <= BE_In(3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_8;
GEN_32_16: if C_DWIDTH = 32 and C_SMALLEST = 16 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-2); --a30
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 3) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_32_16;
GEN_64_8: if C_DWIDTH = 64 and C_SMALLEST = 8 generate
signal addr_bits : std_logic_vector(0 to 2);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-1); --a29 to a31
case addr_bits is
when "001" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(8 to 15);
case Decode_size is
when "001" => --B
BE_Out(0) <= BE_In(1);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(8 to 15) <= Rd_Data_In(0 to 7);
when others => null;
end case;
when "010" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(2);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(16 to 23) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "011" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(24 to 31);
Wr_Data_Out(8 to 15) <= Wr_Data_In(24 to 31);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(3);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(24 to 31) <= Rd_Data_In(8 to 15);
when others => null;
end case;
when "100" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(4);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(32 to 39) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "101" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(40 to 47);
Wr_Data_Out(8 to 15) <= Wr_Data_In(40 to 47);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(5);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(40 to 47) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "110" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(6);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(48 to 55) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "111" =>
Wr_Data_Out(0 to 7) <= Wr_Data_In(56 to 63);
Wr_Data_Out(8 to 15) <= Wr_Data_In(56 to 63);
Wr_Data_Out(24 to 31) <= Wr_Data_In(56 to 63);
case Decode_size is
when "001" => -- B
BE_Out(0) <= BE_In(7);
BE_Out(1 to 7) <= (others => '0');
Rd_Data_Out(56 to 63) <= Rd_Data_In(0 to 7);
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_8;
GEN_64_16: if C_DWIDTH = 64 and C_SMALLEST = 16 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3 to C_AWIDTH-2); --a29 to a30
case addr_bits is
when "01" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(16 to 31);
case Decode_size is
when "010" => --HW
BE_Out(0 to 1) <= BE_In(2 to 3);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(16 to 31) <= Rd_Data_In(0 to 15);
when others => null;
end case;
when "10" =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(4 to 5);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(32 to 47) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when "11" =>
Wr_Data_Out(0 to 15) <= Wr_Data_In(48 to 63);
Wr_Data_Out(16 to 31) <= Wr_Data_In(48 to 63);
case Decode_size is
when "010" => -- HW
BE_Out(0 to 1) <= BE_In(6 to 7);
BE_Out(2 to 7) <= (others => '0');
Rd_Data_Out(48 to 63) <= Rd_Data_In(0 to 15);
when "011" => -- FW
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_16;
GEN_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Addr,Wr_Data_In,BE_In,Rd_Data_In,Decode_size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
Wr_Data_Out(0 to 31) <= Wr_Data_In(32 to 63);
case Decode_size is
when "011" =>
BE_Out(0 to 3) <= BE_In(4 to 7);
BE_Out(4 to 7) <= (others => '0');
Rd_Data_Out(32 to 63) <= Rd_Data_In(0 to 31);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_64_32;
-- Size indication (Decode_size)
-- n = 001 byte 2^0
-- n = 010 halfword 2^1
-- n = 011 word 2^2
-- n = 100 doubleword 2^3
-- n = 101 128-b
-- n = 110 256-b
-- n = 111 512-b
-- num_bytes = 2^(n-1)
end architecture IMP;
| bsd-3-clause | 6797ccaf745e6a43695c9bd4735bc47c | 0.424408 | 3.867879 | false | false | false | false |
michaelmiehling/A25_VME | 16z091-01_src/Source/interrupt_core.vhd | 1 | 9,767 | --------------------------------------------------------------------------------
-- Title : Module for interrupt generation, synchronized to clk
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : interrupt_core.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 15.03.2011
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- This module will generate both INTA and MSI messages. It will start in INTA
-- mode and then determine if it is allowed to send MSI interrupts by reading
-- the config space. If MSI are allowed, the corresponding number of allocated
-- requests will be shown.
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- error
-- err_fifo
-- init
-- * interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity interrupt_core is
port(
clk : in std_logic;
rst : in std_logic;
-- IP Core
app_int_ack : in std_logic;
app_msi_ack : in std_logic;
app_int_sts : out std_logic;
app_msi_req : out std_logic;
app_msi_tc : out std_logic_vector(2 downto 0);
app_msi_num : out std_logic_vector(4 downto 0);
pex_msi_num : out std_logic_vector(4 downto 0);
-- interrupt_wb
wb_pwr_en : in std_logic;
wb_num_int : in std_logic_vector(4 downto 0);
wb_inter : in std_logic;
ack_ok : in std_logic;
inter_ack : out std_logic;
num_allowed : out std_logic_vector(5 downto 0);
-- init
cfg_msicsr : in std_logic_vector(15 downto 0);
-- error
wb_num_err : out std_logic
);
end entity interrupt_core;
-- ****************************************************************************
architecture interrupt_core_arch of interrupt_core is
-- internal signals -----------------------------------------------------------
signal msi_allowed_int : std_logic;
signal msi_allowed_num : std_logic_vector(5 downto 0);
signal ack_int : std_logic;
-- registers for synchronization:
signal cfg_msicsr_q : std_logic_vector(15 downto 0);
signal cfg_msicsr_qq : std_logic_vector(15 downto 0);
signal wb_pwr_en_q : std_logic;
signal wb_pwr_en_qq : std_logic;
signal wb_num_int_q : std_logic_vector(4 downto 0);
signal wb_num_int_qq : std_logic_vector(4 downto 0);
signal wb_inter_q : std_logic;
signal wb_inter_qq : std_logic;
signal wb_inter_qqq : std_logic;
signal ack_ok_q : std_logic;
signal ack_ok_qq : std_logic;
-------------------------------------------------------------------------------
begin
num_allowed <= msi_allowed_num;
-- register all input signals
reg_val : process(rst, clk)
begin
if(rst = '1') then
cfg_msicsr_q <= (others => '0');
cfg_msicsr_qq <= (others => '0');
wb_pwr_en_q <= '0';
wb_pwr_en_qq <= '0';
wb_num_int_q <= (others => '0');
wb_num_int_qq <= (others => '0');
wb_inter_q <= '0';
wb_inter_qq <= '0';
wb_inter_qqq <= '0';
ack_ok_q <= '0';
ack_ok_qq <= '0';
elsif(clk'event and clk = '1') then
cfg_msicsr_q <= cfg_msicsr;
cfg_msicsr_qq <= cfg_msicsr_q;
wb_pwr_en_q <= wb_pwr_en;
wb_pwr_en_qq <= wb_pwr_en_q;
wb_num_int_q <= wb_num_int;
wb_num_int_qq <= wb_num_int_q;
wb_inter_q <= wb_inter;
wb_inter_qq <= wb_inter_q;
wb_inter_qqq <= wb_inter_qq;
ack_ok_q <= ack_ok;
ack_ok_qq <= ack_ok_q;
end if;
end process reg_val;
-- fixed value for traffic class
app_msi_tc <= (others => '0');
-------------------------------------------------------------------------------
config : process(rst, cfg_msicsr_qq)
begin
if(rst = '1') then
msi_allowed_num <= "000000";
msi_allowed_int <= '0';
else
-- set number of allowed vectors according to cfg register settings
if(cfg_msicsr_qq(0) = '0') then -- MSI not allowed
msi_allowed_num <= "000000";
msi_allowed_int <= '0';
else
case cfg_msicsr_qq(6 downto 4) is
when "000" =>
msi_allowed_num <= "000001";
msi_allowed_int <= '1';
when "001" =>
msi_allowed_num <= "000010";
msi_allowed_int <= '1';
when "010" =>
msi_allowed_num <= "000100";
msi_allowed_int <= '1';
when "011" =>
msi_allowed_num <= "001000";
msi_allowed_int <= '1';
when "100" =>
msi_allowed_num <= "010000";
msi_allowed_int <= '1';
when "101" =>
msi_allowed_num <= "100000";
msi_allowed_int <= '1';
-- the following two encodings are specified as reserved by the PCIe base specification and should not be used. Thus they
-- should not be covered because these statements will never occur.
-- coverage off
when "110" =>
msi_allowed_num <= "000000";
msi_allowed_int <= '0';
when "111" =>
msi_allowed_num <= "000000";
msi_allowed_int <= '0';
when others =>
msi_allowed_num <= "000000";
msi_allowed_int <= '0';
-- coverage on
end case;
end if;
end if;
end process config;
-------------------------------------------------------------------------------
calc : process(rst, clk)
begin
if(rst = '1') then
app_int_sts <= '0';
app_msi_req <= '0';
app_msi_num <= (others => '0');
pex_msi_num <= (others => '0');
inter_ack <= '0';
wb_num_err <= '0';
ack_int <= '0';
elsif(clk'event and clk = '1') then
-- pass acknowledge to interrupt_wb module
-- if app_int_ack is asserted on the next clock
-- cycle after Deassert_INTA is set then this
-- fails because ack_int is released too late
if(app_int_ack = '1' or app_msi_ack = '1') then
inter_ack <= '1';
elsif(ack_ok_qq = '1') then
inter_ack <= '0';
end if;
if(app_int_ack = '1' or app_msi_ack = '1') then
ack_int <= '1';
elsif(wb_inter_qqq = '0') then
ack_int <= '0';
end if;
-- is MSI is acknowledged, reset requesting signals
if(app_msi_ack = '1') then
app_msi_num <= (others => '0');
pex_msi_num <= (others => '0');
end if;
if(wb_inter_qqq = '1' and msi_allowed_int = '0') then
app_int_sts <= '1';
elsif(wb_inter_qqq = '0' and msi_allowed_int = '0') then
app_int_sts <= '0';
elsif(wb_inter_qqq = '1' and msi_allowed_int = '1' and app_msi_ack = '0' and ack_int = '0') then
app_msi_req <= '1';
elsif(wb_inter_qqq = '1' and msi_allowed_int = '1' and app_msi_ack = '1') then
app_msi_req <= '0';
end if;
-- set vector number according to wb_pwr_en_qq
if(wb_pwr_en_qq = '1' and msi_allowed_int = '1') then
pex_msi_num <= wb_num_int_qq;
elsif(wb_pwr_en_qq = '0' and msi_allowed_int = '1') then
app_msi_num <= wb_num_int_qq;
end if;
-- set num_error if input vector number exceeds maximum allowed, if msi_allowed_num(5) = '1' then the maximum is allocated
-- thus a check is not necessary
if(wb_inter_qqq = '1' and msi_allowed_int = '1' and msi_allowed_num(5) = '0' and wb_num_int_qq >= msi_allowed_num(4 downto 0)) then
wb_num_err <= '1';
else
wb_num_err <= '0';
end if;
end if;
end process calc;
-------------------------------------------------------------------------------
end architecture interrupt_core_arch;
| gpl-3.0 | 74f8308ce98ed515dafa6ae13a19ffa1 | 0.466059 | 3.880413 | false | false | false | false |
michaelmiehling/A25_VME | 16z000-00_src/Source/fpga_pkg_2.vhd | 1 | 7,970 | ---------------------------------------------------------------
-- Title : Package for FPGA family type
-- Project :
---------------------------------------------------------------
-- File : fpga_pkg_2.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 24/10/06
---------------------------------------------------------------
-- Simulator :
-- Synthesis :
---------------------------------------------------------------
-- Description :
--! \desid
--! \archid
--! \desbody
---------------------------------------------------------------
--!\hierarchy
--!\endofhierarchy
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.8 $
--
-- $Log: fpga_pkg_2.vhd,v $
-- Revision 1.8 2014/11/19 10:10:34 FLenhardt
-- R: No support for device family "Cyclone V"
-- M: Added device family CYCLONE5 to family_type
--
-- Revision 1.7 2014/06/03 11:34:30 CSchwark
-- R: no support for device family SmartFusion2
-- M: added device family SF2 to family_type
--
-- Revision 1.6 2013/02/11 14:33:42 FLenhardt
-- * added CYCLONE4E
-- * added FUNCTION altera_device_family
--
-- Revision 1.5 2012/10/24 09:04:32 MMiehling
-- added ARRIA2_GX, ARRIA2_GZ
--
-- Revision 1.4 2010/12/22 14:22:27 TWickleder
-- added CYCLONE4
--
-- Revision 1.3 2010/05/05 10:27:55 TWickleder
-- added FUNCTION get_fsrev and conv_chr_to_int
--
-- Revision 1.2 2009/02/17 11:37:35 FWombacher
-- cosmetics due to rule checker
--
-- Revision 1.1 2008/11/21 15:16:54 FWombacher
-- Initial Revision
--
-- Revision 1.2 2008/10/24 16:39:53 FWombacher
-- added comments
--
-- Revision 1.1 2008/10/22 14:19:15 FWombacher
-- Initial Revision
--
-- Revision 1.2 2007/12/12 14:04:48 mernst
-- Added Cyclone III device to FPGA_PKG
--
-- Revision 1.1 2006/11/27 14:15:26 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
PACKAGE fpga_pkg_2 IS
TYPE family_type IS (NONE, CYCLONE, CYCLONE2, CYCLONE3, CYCLONE4, CYCLONE4E, CYCLONE5, FLEX, ACEX, A3P, ARRIA_GX, ARRIA2_GX, ARRIA2_GZ, SF2);
TYPE supported_family_types IS array (natural range <>) OF family_type; -- for more than one supported devices
SUBTYPE supported_family_type IS family_type; -- for exactly one supported device
FUNCTION altera_device_family(FPGA_FAMILY : IN family_type) RETURN string;
-- CONSTANT fpga_family : family_type := CYCLONE3;
FUNCTION no_valid_device(
supported_devices : IN supported_family_types;
device : IN family_type )
RETURN boolean;
FUNCTION no_valid_device(
supported_device : IN supported_family_type;
device : IN family_type )
RETURN boolean;
FUNCTION get_fsrev(fsrev_str : IN string) RETURN std_logic_vector;
FUNCTION conv_chr_to_int(char : IN character) RETURN integer;
END fpga_pkg_2;
PACKAGE BODY fpga_pkg_2 IS
FUNCTION altera_device_family(FPGA_FAMILY : IN family_type) RETURN string IS
BEGIN
IF FPGA_FAMILY = CYCLONE THEN
RETURN "Cyclone";
ELSIF FPGA_FAMILY = CYCLONE2 THEN
RETURN "Cyclone II";
ELSIF FPGA_FAMILY = CYCLONE3 THEN
RETURN "Cyclone III";
ELSIF FPGA_FAMILY = CYCLONE4E THEN
RETURN "Cyclone IV E";
ELSIF FPGA_FAMILY = CYCLONE4 THEN
RETURN "Cyclone IV GX";
ELSIF FPGA_FAMILY = CYCLONE5 THEN
RETURN "Cyclone V";
ELSIF FPGA_FAMILY = ARRIA_GX THEN
RETURN "Arria GX";
ELSIF FPGA_FAMILY = ARRIA2_GX THEN
RETURN "Arria II GX";
ELSIF FPGA_FAMILY = ARRIA2_GZ THEN
RETURN "Arria II GZ";
--ELSIF FPGA_FAMILY = THEN
-- RETURN "";
ELSE
ASSERT FALSE REPORT "UNSUPPORTED ALTERA DEVICE" SEVERITY FAILURE;
RETURN "";
END IF;
END altera_device_family;
FUNCTION no_valid_device(
supported_devices : IN supported_family_types;
device : IN family_type )
RETURN boolean IS
VARIABLE no_valid : boolean := TRUE;
BEGIN
FOR i IN supported_devices'range LOOP
IF(device = supported_devices(i)) THEN
no_valid := FALSE;
ELSE
no_valid := no_valid;
END IF;
END LOOP;
RETURN no_valid;
END no_valid_device;
FUNCTION no_valid_device(
supported_device : IN supported_family_type;
device : IN family_type )
RETURN boolean IS
VARIABLE no_valid : boolean := TRUE;
BEGIN
IF(device = supported_device) THEN
no_valid := FALSE;
ELSE
no_valid := TRUE;
END IF;
RETURN no_valid;
END no_valid_device;
FUNCTION get_fsrev(fsrev_str : IN string) RETURN std_logic_vector IS
VARIABLE minor_no : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
VARIABLE major_no : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
VARIABLE scan_str : string(7 DOWNTO 1) := " ";
VARIABLE maj_str : string(3 DOWNTO 1) := " ";
VARIABLE min_str : string(3 DOWNTO 1) := " ";
VARIABLE fsrev_found : boolean := FALSE;
VARIABLE next_is_rev : boolean := FALSE;
VARIABLE major_found : boolean := FALSE;
VARIABLE minor_found : boolean := FALSE;
BEGIN
FOR i IN fsrev_str'range LOOP
scan_str := scan_str(6 DOWNTO 1) & fsrev_str(i); --shift string in
IF(scan_str = "%FSREV ") THEN fsrev_found := TRUE;
ELSIF(fsrev_found AND NOT next_is_rev) THEN
IF(scan_str(1) = ' ') THEN next_is_rev := TRUE; END IF;
ELSIF(next_is_rev AND NOT major_found) THEN
IF(scan_str(1) = '.') THEN major_found := TRUE; ELSE maj_str := maj_str(2 DOWNTO 1) & scan_str(1); END IF;
ELSIF(major_found AND NOT minor_found) THEN
IF(scan_str(1) = ' ') THEN minor_found := TRUE; ELSE min_str := min_str(2 DOWNTO 1) & scan_str(1); END IF;
ELSIF(minor_found) THEN exit;
END IF;
END LOOP;
minor_no := conv_std_logic_vector(100*conv_chr_to_int(min_str(3))+10*conv_chr_to_int(min_str(2))+conv_chr_to_int(min_str(1)),8);
major_no := conv_std_logic_vector(100*conv_chr_to_int(maj_str(3))+10*conv_chr_to_int(maj_str(2))+conv_chr_to_int(maj_str(1)),8);
RETURN (major_no&minor_no);
END get_fsrev;
FUNCTION conv_chr_to_int(char : IN character) RETURN integer IS
VARIABLE num : integer := 0;
BEGIN
CASE char IS
WHEN '0' => num := 0;
WHEN '1' => num := 1;
WHEN '2' => num := 2;
WHEN '3' => num := 3;
WHEN '4' => num := 4;
WHEN '5' => num := 5;
WHEN '6' => num := 6;
WHEN '7' => num := 7;
WHEN '8' => num := 8;
WHEN '9' => num := 9;
WHEN OTHERS => num := 0;
END CASE;
RETURN num;
END conv_chr_to_int;
END;
| gpl-3.0 | a1c6aa46064c768d89d42fc35377a2eb | 0.564115 | 3.691524 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_acc_three_v1_00_a/hdl/vhdl/hw_acc_three.vhd | 2 | 7,972 | ------------------------------------------------------------------------------
-- add_sub_core - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: add_sub_core
-- Version: 1.00.a
-- Description: Example FSL core (VHDL).
-- Date: Thu Aug 9 10:06:10 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_three is
port
(
Tintrfc2thrd_value : out std_logic_vector(0 to 31);
Tintrfc2thrd_function : out std_logic_vector(0 to 15);
Tintrfc2thrd_goWait : out std_logic;
Tthrd2intrfc_address : out std_logic_vector(0 to 31);
Tthrd2intrfc_value : out std_logic_vector(0 to 31);
Tthrd2intrfc_function : out std_logic_vector(0 to 15);
Tthrd2intrfc_opcode : out std_logic_vector(0 to 5);
Ttimer : out std_logic_vector( 0 to 31);
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
FSL1_M_Write : out std_logic;
FSL1_M_Data : out std_logic_vector(0 to 31);
FSL1_M_Full : in std_logic;
FSL2_M_Write : out std_logic;
FSL2_M_Data : out std_logic_vector(0 to 31);
FSL2_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
end hw_acc_three;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_three is
component user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic ;
full : in std_logic ;
Ttimer : out std_logic_vector( 0 to 31)
);
end component user_logic_hwtul;
signal intrfc2thrd : std_logic_vector(0 to 63);
signal thrd2intrfc : std_logic_vector( 0 to 95);
signal rd : std_logic;
signal wr : std_logic;
signal exist : std_logic;
signal full : std_logic;
signal timer : std_logic_vector( 0 to 31) ;
-- Architecture Section
begin
Tintrfc2thrd_value <= intrfc2thrd(0 to 31) ;
Tintrfc2thrd_function <= intrfc2thrd (32 to 47);
Tintrfc2thrd_goWait <= exist ;
Tthrd2intrfc_address <= thrd2intrfc (32 to 63);
Tthrd2intrfc_value <= thrd2intrfc (0 to 31) ;
Tthrd2intrfc_function <= thrd2intrfc (64 to 79);
Tthrd2intrfc_opcode <= thrd2intrfc (80 to 85);
Ttimer <= timer;
intrfc2thrd <= FSL0_S_Data & FSL1_S_Data;
FSL0_M_Data <= thrd2intrfc(0 to 31);
FSL1_M_Data <= thrd2intrfc(32 to 63);
FSL2_M_Data <= thrd2intrfc(64 to 95);
--=======================================================
full <= FSL0_M_Full or FSL1_M_Full or FSL2_M_Full;
exist <= FSL0_S_Exists and FSL1_S_Exists ;
--=======================================================
FSL0_S_Read <= rd;
FSL1_S_Read <= rd;
FSL0_M_Write <= wr;
FSL1_M_Write <= wr;
FSL2_M_Write <= wr;
USER_LOGIC_HWTUL_I : user_logic_hwtul
port map
(
clock => FSL_Clk,
intrfc2thrd => intrfc2thrd,
thrd2intrfc => thrd2intrfc,
rd => rd,
wr => wr,
exist => exist,
full => full,
Ttimer => timer
);
end architecture implementation;
| bsd-3-clause | 347ceb23dd04dbc813d68b8c7d51485d | 0.473031 | 4.182581 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/hw_threads/hw_thcrc_v1_00_a/hdl/vhdl/user_logic_hwtul.vhd | 2 | 14,354 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
entity user_logic_hwtul is
generic(
G_INPUT_WIDTH : integer := 32;
G_DIVISOR_WIDTH : integer := 4;
divisor : std_logic_vector(0 to 3) := "1011"
);
port (
clock : in std_logic;
intrfc2thrd : in std_logic_vector(0 to 63);
thrd2intrfc : out std_logic_vector( 0 to 95);
rd : out std_logic;
wr : out std_logic;
exist : in std_logic;
full : in std_logic;
Ttimer : out std_logic_vector( 0 to 31)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
alias intrfc2thrd_value : std_logic_vector(0 to 31) is intrfc2thrd(0 to 31);
alias intrfc2thrd_function : std_logic_vector(0 to 15) is intrfc2thrd(32 to 47);
alias intrfc2thrd_goWait : std_logic is intrfc2thrd(48);
alias thrd2intrfc_address : std_logic_vector(0 to 31) is thrd2intrfc( 32 to 63);
alias thrd2intrfc_value : std_logic_vector(0 to 31) is thrd2intrfc( 0 to 31);
alias thrd2intrfc_function : std_logic_vector(0 to 15) is thrd2intrfc( 64 to 79);
alias thrd2intrfc_opcode : std_logic_vector(0 to 5) is thrd2intrfc( 80 to 85) ;
signal new_request : std_logic; --when there is a new request to HWTI
signal timer : std_logic_vector(0 to 31);
type timer_state_machine is ( idle,counting);
signal timer_cs : timer_state_machine :=idle;
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
SETUP_1,
SETUP_2,
SETUP_3,
SETUP_4,
SETUP_5,
SETUP_6,
WHILE_LOOP_1,
WHILE_LOOP_2,
WHILE_LOOP_3,
WHILE_LOOP_4,
WHILE_LOOP_4a,
WHILE_LOOP_5,
WHILE_LOOP_6,
WHILE_LOOP_7,
WHILE_LOOP_8,
WHILE_LOOP_9,
FUNCTION_EXIT_1,
FUNCTION_EXIT_2,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_WHILE_LOOP_3 : std_logic_vector(0 to 15) := x"0103";
constant U_WHILE_LOOP_6 : std_logic_vector(0 to 15) := x"0106";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
-- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
-- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
-- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
-- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
-- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
-- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
-- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
-- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
-- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
-- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
-- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
-- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
-- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
-- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
-- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
-- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESSOF : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal structAddr, structAddr_next : std_logic_vector(0 to 31);
signal size, size_next : std_logic_vector(0 to 31);
signal xAddr, xAddr_next : std_logic_vector(0 to 31);
signal xVal, xVal_next : std_logic_vector(0 to 31);
signal i, i_next : std_logic_vector(0 to 7);
signal count, count_next : std_logic_vector(0 to 31);
-- misc constants
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
Ttimer <= timer;
timer_process: process(clock)
begin
if (clock'event and (clock = '1')) then
case timer_cs is
when idle=>
timer <= (others =>'0');
if current_state= FUNCTION_START then
timer_cs <= counting;
end if;
when counting =>
timer <= timer + x"00000001";
if (current_state= FUNCTION_RESET or current_state=FUNCTION_EXIT_1) then
timer_cs <= idle;
end if;
when others =>
timer <= (others =>'0');
timer_cs <= idle;
end case;
end if;
end process timer_process;
wr <= '0' when ( current_state= WAIT_STATE ) else new_request ;
rd <= exist;
HWTUL_STATE_PROCESS : process (clock, exist) is
begin
if (clock'event and (clock = '1')) then
return_state <= return_state_next;
structAddr <= structAddr_next;
size <= size_next;
xAddr <= xAddr_next;
xVal <= xVal_next;
count <= count_next;
i <= i_next;
-- Find out if the HWTI is tell us what to do
if (exist = '1') then
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_WHILE_LOOP_3 =>
current_state <= WHILE_LOOP_3;
when U_WHILE_LOOP_6 =>
current_state <= WHILE_LOOP_6;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
elsif ( new_request = '0') then
current_state <= next_state;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
new_request <= '1';
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
structAddr_next <= structAddr;
size_next <= size;
xAddr_next <= xAddr;
xVal_next <= xVal;
count_next <= count;
i_next <= i;
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
new_request <= '0';
when FUNCTION_START =>
-- POP the argument
thrd2intrfc_opcode <= OPCODE_POP;
thrd2intrfc_value <= Z32;
count_next <= Z32;
i_next <= (others =>'0');
next_state <= WAIT_STATE;
return_state_next <= SETUP_1;
when SETUP_1 =>
-- Read the argument, which is an address of a struct
structAddr_next <= toUser_value;
-- Initiate the reading of the first variable in the struct, size
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= toUser_value;
next_state <= WAIT_STATE;
return_state_next <= SETUP_2;
when SETUP_2 =>
-- Read the value of size
size_next <= toUser_value;
-- Initiate the reading of the third variable in the struct, xAddr
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= structAddr + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= SETUP_6;
when SETUP_6 =>
--
xAddr_next <= toUser_value;
next_state <=WHILE_LOOP_6;
new_request <= '0';
when WHILE_LOOP_6 =>
-- Check to see if the index is over the size
if ( count < size ) then
-- More work to be done
-- Initiate the read of the X matrix
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= xAddr + (count(2 to 31) & "00");
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_7;
i_next <= conv_std_logic_vector(0,8);
else
-- we may exit
next_state <= FUNCTION_EXIT_1;
new_request <= '0';
end if;
when WHILE_LOOP_7 =>
xVal_next <= ToUser_value;
--
next_state <=WHILE_LOOP_8 ;
new_request <= '0';
when WHILE_LOOP_8 =>
if ( i < G_INPUT_WIDTH - G_DIVISOR_WIDTH + 1 ) and ( xVal(conv_integer(i)) = '0' ) then
i_next <= i + 1;
next_state <= WHILE_LOOP_8;
new_request <= '0';
elsif ( i < G_INPUT_WIDTH - G_DIVISOR_WIDTH + 1 ) then
xval_next(conv_integer(i) to conv_integer(i) + ( G_DIVISOR_WIDTH - 1 )) <= xval(conv_integer(i) to conv_integer(i) + ( G_DIVISOR_WIDTH - 1 )) xor divisor;
i_next <= i + 1;
next_state <= WHILE_LOOP_8;
new_request <= '0';
else
-- Initiate the writing of the result
thrd2intrfc_opcode <= OPCODE_STORE;
thrd2intrfc_address <= xaddr + (count(2 to 31) & "00");
thrd2intrfc_value <= xval;
next_state <= WAIT_STATE;
return_state_next <= WHILE_LOOP_6;
-- Increment count
count_next <= count + x"00000001";
end if;
when FUNCTION_EXIT_1 =>
thrd2intrfc_value <= timer;
thrd2intrfc_opcode <= OPCODE_PUSH;
next_state <= WAIT_STATE;
return_state_next <= FUNCTION_EXIT_2;
when FUNCTION_EXIT_2 =>
--Immediatly exit
thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT;
thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET;
thrd2intrfc_opcode <= OPCODE_CALL;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
new_request <= '0';
when others =>
next_state <= ERROR_STATE;
new_request <= '0';
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
| bsd-3-clause | ef6ddfd8cb6e660e4d613560d7006591 | 0.561377 | 3.783342 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_ipif_v2_00_h/hdl/vhdl/pf_dly1_mux.vhd | 3 | 6,781 | -------------------------------------------------------------------------------
-- $Id: pf_dly1_mux.vhd,v 1.1 2003/03/15 01:05:27 ostlerf Exp $
-------------------------------------------------------------------------------
-- pf_dly1_mux.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************
-- ** Copyright Xilinx, Inc. **
-- ** All rights reserved. **
-- ****************************
--
-------------------------------------------------------------------------------
-- Filename: pf_dly1_mux.vhd
--
-- Description: Implements a multiplexer and register combo that allows
-- selection of a registered or non-registered version of
-- the input signal for output.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_dly1_mux.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1 $
-- Date: $Date: 2003/03/15 01:05:27 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v1_00_b;
Use proc_common_v1_00_b.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_dly1_mux is
Generic (C_MUX_WIDTH : Integer := 12
);
port (
Clk : in std_logic;
Rst : In std_logic;
dly_sel1 : in std_logic;
dly_sel2 : in std_logic;
Inputs : in std_logic_vector(0 to C_MUX_WIDTH-1);
Y_out : out std_logic_vector(0 to C_MUX_WIDTH-1)
);
end pf_dly1_mux;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_dly1_mux is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
component inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component inferred_lut4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal lut_out : std_logic_vector(0 to C_MUX_WIDTH-1);
signal reg_out : std_logic_vector(0 to C_MUX_WIDTH-1);
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
MAKE_DLY_MUX : for i in 0 to C_MUX_WIDTH-1 generate
--- xst wrk around I_SEL_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"FE10"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => lut_out(i),
--- xst wrk around I0 => dly_sel1,
--- xst wrk around I1 => dly_sel2,
--- xst wrk around I2 => Inputs(i),
--- xst wrk around I3 => reg_out(i)
--- xst wrk around );
I_SEL_LUT : inferred_lut4
generic map(
INIT => X"FE10"
)
port map (
O => lut_out(i),
I0 => dly_sel1,
I1 => dly_sel2,
I2 => Inputs(i),
I3 => reg_out(i)
);
FDRE_I: FDRE
port map (
Q => reg_out(i),
C => Clk,
CE => '1',
D => Inputs(i),
R => Rst
);
End generate MAKE_DLY_MUX;
Y_out <= lut_out;
end implementation;
| bsd-3-clause | 594f7bd38bfcd2ffe760291e092b8c30 | 0.383572 | 4.437827 | false | false | false | false |
iocoder/graduation | hardware/vga/graphics.vhd | 1 | 11,851 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity graphics is
Port ( CLK50 : in STD_LOGIC;
CLK12 : in STD_LOGIC;
CS : in STD_LOGIC;
RW : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (13 downto 0);
Din : in STD_LOGIC_VECTOR (15 downto 0);
Dout : out STD_LOGIC_VECTOR (15 downto 0) := x"0000";
INT : out STD_LOGIC := '0';
IAK : in STD_LOGIC;
VBLANK : in STD_LOGIC;
VRAM0Read : out STD_LOGIC;
VRAM1Read : out STD_LOGIC;
VRAM2Read : out STD_LOGIC;
VRAM3Read : out STD_LOGIC;
VRAM4Read : out STD_LOGIC;
VRAM0Write : out STD_LOGIC;
VRAM1Write : out STD_LOGIC;
VRAM2Write : out STD_LOGIC;
VRAM3Write : out STD_LOGIC;
VRAM4Write : out STD_LOGIC;
VRAMAddr : out STD_LOGIC_VECTOR (10 downto 0);
VRAM0DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM1DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM2DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM3DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAM4DataIn : in STD_LOGIC_VECTOR ( 8 downto 0);
VRAMDataOut : out STD_LOGIC_VECTOR ( 8 downto 0);
SprRD : out STD_LOGIC;
SprWR : out STD_LOGIC;
SprAddr : out STD_LOGIC_VECTOR ( 7 downto 0);
SprDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
SprDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
PalRD : out STD_LOGIC;
PalWR : out STD_LOGIC;
PalAddr : out STD_LOGIC_VECTOR ( 4 downto 0);
PalDataIn : in STD_LOGIC_VECTOR ( 7 downto 0);
PalDataOut : out STD_LOGIC_VECTOR ( 7 downto 0);
ROW_BASE : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
CURSOR_ROW : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
CURSOR_COL : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
PPU_CTRL : out STD_LOGIC_VECTOR (15 downto 0) := x"0000";
PPU_HSCR : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
PPU_VSCR : out STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
MODE : out STD_LOGIC);
end graphics;
architecture Behavioral of graphics is
signal LASTCS : STD_LOGIC := '0';
signal LASTVBLANK : STD_LOGIC := '0';
signal LASTVBLANK2 : STD_LOGIC := '0';
-- general registers
signal ROW_BASE_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal CURSOR_ROW_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal CURSOR_COL_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal MODE_REG : STD_LOGIC := '0';
-- PPU registers
signal PPU_CTRL_REG : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
signal PPU_HSCR_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal PPU_VSCR_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal PPU_ADDR_REG : STD_LOGIC_VECTOR (15 downto 0) := x"0000";
signal PPU_SMA_REG : STD_LOGIC_VECTOR ( 7 downto 0) := x"00";
signal PPU_HIT_REG : STD_LOGIC := '0';
signal PPU_VBLANK_REG : STD_LOGIC := '0';
signal PPU_FF : STD_LOGIC := '0';
begin
process (CLK12)
procedure ppu_mem_access(write : in STD_LOGIC;
data : in STD_LOGIC_VECTOR(7 downto 0)) is
begin
case PPU_ADDR_REG(13 downto 12) is
when "00" =>
-- ram0 and ram1
if (PPU_ADDR_REG(3) = '0') then
VRAM0Read <= NOT write;
VRAM0Write <= write;
else
VRAM1Read <= NOT write;
VRAM1Write <= write;
end if;
VRAMAddr <= PPU_ADDR_REG(11 downto 4) &
PPU_ADDR_REG( 2 downto 0);
VRAMDataOut <= "0" & data;
when "01" =>
-- ram2 and ram3
if (PPU_ADDR_REG(3) = '0') then
VRAM2Read <= NOT write;
VRAM2Write <= write;
else
VRAM3Read <= NOT write;
VRAM3Write <= write;
end if;
VRAMAddr <= PPU_ADDR_REG(11 downto 4) &
PPU_ADDR_REG( 2 downto 0);
VRAMDataOut <= "0" & data;
when "10" =>
-- ram4 (namtabs)
VRAM4Read <= NOT write;
VRAM4Write <= write;
VRAMAddr <= PPU_ADDR_REG(10 downto 0);
VRAMDataOut <= "0" & data;
when "11" =>
-- palette
if (PPU_ADDR_REG(13 downto 8) = "111111") then
if (PPU_ADDR_REG(3 downto 0) = "0000") then
PalAddr <= "00000";
else
PalAddr <= PPU_ADDR_REG(4 downto 0);
end if;
if (write = '0') then
PalRD <= '1';
else
PalWR <= '1';
PalDataOut <= data;
end if;
end if;
when others =>
end case;
if (PPU_CTRL_REG(2) = '1') then
-- vertical write
PPU_ADDR_REG <=
conv_std_logic_vector(conv_integer(PPU_ADDR_REG) + 32, 16);
else
PPU_ADDR_REG <=
conv_std_logic_vector(conv_integer(PPU_ADDR_REG) + 1, 16);
end if;
end ppu_mem_access;
begin
if (CLK12 = '0' and CLK12'event ) then
if (CS = '1') then
if (MODE_REG = '1' and RW='1' and LASTCS='0') then
-- write
case A(2 downto 0) is
when "000" =>
-- control 1
PPU_CTRL_REG( 7 downto 0) <= Din(7 downto 0);
when "001" =>
-- control 2
PPU_CTRL_REG(15 downto 8) <= Din(7 downto 0);
when "010" =>
-- status
when "011" =>
-- Sprite Memory Address
PPU_SMA_REG <= Din(7 downto 0);
when "100" =>
-- Sprite Memory Data
SprWR <= '1';
SprAddr <= PPU_SMA_REG;
SprDataOut <= Din(7 downto 0);
PPU_SMA_REG <= conv_std_logic_vector(
conv_integer(
unsigned(PPU_SMA_REG))+1,8);
when "101" =>
-- scroll data
if (PPU_FF = '0') then
-- horizontal scroll
PPU_HSCR_REG <= Din(7 downto 0);
else
-- vertical scroll
PPU_VSCR_REG <= Din(7 downto 0);
end if;
PPU_FF <= NOT PPU_FF;
when "110" =>
-- address
if (PPU_FF = '0') then
PPU_ADDR_REG(13 downto 8) <= Din(5 downto 0);
else
PPU_ADDR_REG( 7 downto 0) <= Din(7 downto 0);
end if;
PPU_FF <= NOT PPU_FF;
when "111" =>
-- data
ppu_mem_access('1', Din(7 downto 0));
when others =>
end case;
elsif (MODE_REG = '1' and RW='0' and LASTCS = '0') then
-- read
case A(2 downto 0) is
when "000" =>
-- control 1 - illegal read
when "001" =>
-- control 2 - illegal read
when "010" =>
-- status
Dout(6) <= PPU_HIT_REG;
Dout(7) <= PPU_VBLANK_REG;
PPU_VBLANK_REG <= '0';
PPU_FF <= '0';
when "011" =>
-- Sprite Memory Address - illegal read
when "100" =>
-- TODO: Sprite Memory Data
when "101" =>
-- scroll offset - illegal read
when "110" =>
-- address - illegal
when "111" =>
-- data
ppu_mem_access('0', x"00");
when others =>
end case;
elsif (A = "0" & x"FFC" & "0") then
MODE_REG <= Din(0);
elsif (A = "0" & x"FFD" & "0") then
ROW_BASE_REG <= Din(7 downto 0);
elsif (A = "0" & x"FFE" & "0") then
CURSOR_ROW_REG <= Din(7 downto 0);
elsif (A = "0" & x"FFF" & "0") then
CURSOR_COL_REG <= Din(7 downto 0);
else
-- access to any other address
if (MODE_REG = '0' and LASTCS = '0') then
VRAM0Read <= (NOT RW) and (NOT A(1)) and (NOT A(13));
VRAM1Read <= (NOT RW) and ( A(1)) and (NOT A(13));
VRAM2Read <= (NOT RW) and (NOT A(1)) and ( A(13));
VRAM3Read <= (NOT RW) and ( A(1)) and ( A(13));
VRAM0Write <= ( RW) and (NOT A(1)) and (NOT A(13));
VRAM1Write <= ( RW) and ( A(1)) and (NOT A(13));
VRAM2Write <= ( RW) and (NOT A(1)) and ( A(13));
VRAM3Write <= ( RW) and ( A(1)) and ( A(13));
VRAMAddr(10 downto 0) <= A(12 downto 2);
VRAMDataOut <= Din(8 downto 0);
end if;
if (MODE_REG = '0' or (RW='0' and A(2 downto 0)="111")) then
Dout(8 downto 0) <= VRAM0DataIn or VRAM1DataIn or
VRAM2DataIn or VRAM3DataIn or
VRAM4DataIn;
end if;
end if;
else
VRAM0Read <= '0';
VRAM1Read <= '0';
VRAM2Read <= '0';
VRAM3Read <= '0';
VRAM4Read <= '0';
VRAM0Write <= '0';
VRAM1Write <= '0';
VRAM2Write <= '0';
VRAM3Write <= '0';
VRAM4Write <= '0';
SprRD <= '0';
SprWR <= '0';
PalRD <= '0';
PalWR <= '0';
Dout <= x"0000";
SprAddr <= x"00";
SprDataOut <= x"00";
PalAddr <= "00000";
PalDataOut <= x"00";
if (VBLANK /= LASTVBLANK) then
PPU_VBLANK_REG <= VBLANK;
end if;
LASTVBLANK <= VBLANK;
end if;
LASTCS <= CS;
end if;
end process;
process (CLK50)
begin
if (CLK50 = '0' and CLK50'event ) then
LASTVBLANK2 <= VBLANK;
if (IAK = '1') then
INT <= '0';
elsif (VBLANK /= LASTVBLANK2) then
if (VBLANK = '1' and PPU_CTRL_REG(7) = '1') then
-- generate interrupt
INT <= '1';
end if;
end if;
end if;
end process;
ROW_BASE <= ROW_BASE_REG;
CURSOR_ROW <= CURSOR_ROW_REG;
CURSOR_COL <= CURSOR_COL_REG;
MODE <= MODE_REG;
PPU_CTRL <= PPU_CTRL_REG;
PPU_HSCR <= PPU_HSCR_REG;
PPU_VSCR <= PPU_VSCR_REG;
end Behavioral;
| gpl-3.0 | bdb366facddf76d08ab9e8eafef71ab5 | 0.408151 | 4.065523 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/pf_counter_top.vhd | 3 | 8,419 | -------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.2.1 $
-- Date: $Date: 2009/10/06 21:15:01 $
--
-- History:
-- DET 2001-08-30 First Version
--
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity opb_v20_v1_10_d.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
| bsd-3-clause | 4ec504d18f893d18794363983373f82a | 0.423566 | 4.877752 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/rdpfifo_top.vhd | 3 | 23,494 | -------------------------------------------------------------------------------
-- $Id: rdpfifo_top.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
--rdpfifo_top.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: rdpfifo_top.vhd
--
-- Description: This file is the top level vhdl design for the Read Packet
-- FIFO module.
--
-------------------------------------------------------------------------------
-- Structure: This is the hierarchical structure of the RPFIFO design.
--
-- rdpfifo_top.vhd
-- |
-- |---> ipif_control_rd.vhd
-- |
-- |---> rdpfifo_dp_cntl.vhd
-- | |
-- | |
-- | |-- pf_counter_top.vhd
-- | | |
-- | | |-- pf_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |
-- | |-- pf_occ_counter_top.vhd
-- | | |
-- | | |-- pf_occ_counter.vhd
-- | | |
-- | | |-- pf_counter_bit.vhd
-- | |
-- | |-- pf_adder.vhd
-- | |
-- | |-- pf_adder_bit.vhd
-- |
-- |---> pf_dpram_select.vhd
-- |
-- |
-- |
-- |
-- |---> srl16_fifo.vhd
-- |
-- |-- pf_counter_top.vhd
-- | |
-- | |-- pf_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |
-- |-- pf_occ_counter_top.vhd
-- | |
-- | |-- pf_occ_counter.vhd
-- | |
-- | |-- pf_counter_bit.vhd
-- |
-- |-- pf_adder.vhd
-- |
-- |-- pf_adder_bit.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- DET March 23,2001 -- V0.00a
--
-- DET APR-24-01
-- - Changed dual port configuration name to
-- rdport_512x32 from dport_512x32.
--
--
-- DET May-04-01
-- - Hardcoded the MIR_ENABLE and Block_ID constant values
-- to simplify the point design compilation into the IPIF.
-- - Commented out the rpfifo_lib declarations.
--
-- DET June-11-01 V1.00b
-- - Modified the IPIF Interface callout for the version b.
--
-- DET June-23-01 V1.00b
-- - Changed the Dual Port core to 3.2 Version and added
-- the ENB nto the core to disable the read port when the
-- FIFO is Empty. This is an attempt to eliminate read
-- warnings during MTI simulation as well as undefined
-- outputs
--
-- DET June-25-01 V1.00b
-- - Upadated the IPIF read control module to version c as part of the
-- removal of redundant logic warnings from Synplicity synthesis.
-- - Updated the Dual Port control module to version d as part of the
-- removal of redundant logic warnings from Synplicity synthesis.
--
--
-- DET July 20, 2001
-- - Changed the C_MIR_ENABLE type to Boolean from std_logic.
--
--
-- DET Aug 19, 2001 v1.01a
-- - Platform Generator compilancy modifications
-- - Added generic to select Virtex E or Virtex II DP core
-- - Imbedded configurations for DP simulation in the design
-- body.
--
--
-- DET Sept. 26, 2001 (part of v1.02a version)
-- - Added the optimization changes
-- - Added additional parameters (generics)
--
--
-- DET Oct. 7, 2001 (part of v1.02a version)
-- - Changes the C_VIRTEX_II input generic to C_FAMILY of type string
-- - Changed the DP core component and instance to new parameterized
-- version (pf_dpram_select.vhd)
--
-- DET Oct. 13, 2001 (part of v1.02a version)
-- - Added the SRL FIFO option
--
-- DET Oct 31, 2001
-- - Changed the input generic C_FAMILY of type string back to the
-- C_VIRTEX_II of type boolean. Changed caused by lack of string
-- support in the XST synthesis tool.
--
--
-- DET 4/1/2004 proc_common_v2 conversion
-- ~~~~~~
-- - Added library reference to proc_common_v2_00_a.
-- ^^^^^^
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library opb_v20_v1_10_d;
Use opb_v20_v1_10_d.pf_dpram_select;
Use opb_v20_v1_10_d.srl16_fifo;
Use opb_v20_v1_10_d.ipif_control_rd;
-------------------------------------------------------------------------------
entity rdpfifo_top is
Generic (
C_MIR_ENABLE : Boolean := true;
-- Enable for MIR synthesis (default for enable)
C_BLOCK_ID : integer range 0 to 255 := 255;
-- Platform Generator assigned ID number
C_FIFO_DEPTH_LOG2X : Integer range 2 to 14 := 9;
-- The number of needed address bits for the
-- required FIFO depth (= log2(fifo_depth)
-- 9 = 512 wds deep, 8 = 256 wds deep, etc.
C_FIFO_WIDTH : Integer range 1 to 128 := 32;
-- Width of FIFO data in bits
C_INCLUDE_PACKET_MODE : Boolean := true;
-- Select for inclusion/omission of packet mode
-- features
C_INCLUDE_VACANCY : Boolean := true;
-- Enable for Vacancy calc feature
C_SUPPORT_BURST : Boolean := true;
-- Enable for IPIF Bus burst support
C_IPIF_DBUS_WIDTH : Integer range 8 to 128 := 32;
-- Width of the IPIF data bus in bits
C_VIRTEX_II : boolean := true
-- Selection of target FPGA technology
-- True = virtex ii family
-- False = virtex family
);
port(
-- Inputs From the IPIF Bus
Bus_rst : In std_logic; -- Master Reset from the IPIF
Bus_Clk : In std_logic; -- Master clock from the IPIF
Bus_RdReq : In std_logic;
Bus_WrReq : In std_logic;
Bus2FIFO_RdCE1 : In std_logic;
Bus2FIFO_RdCE2 : In std_logic;
Bus2FIFO_RdCE3 : In std_logic;
Bus2FIFO_WrCE1 : In std_logic;
Bus2FIFO_WrCE2 : In std_logic;
Bus2FIFO_WrCE3 : In std_logic;
Bus_DBus : In std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
-- Inputs from the IP
IP2RFIFO_WrReq : In std_logic;
IP2RFIFO_WrMark : In std_logic;
IP2RFIFO_WrRestore : In std_logic;
IP2RFIFO_WrRelease : In std_logic;
IP2RFIFO_Data : In std_logic_vector(0 to C_FIFO_WIDTH-1);
-- Outputs to the IP
RFIFO2IP_WrAck : Out std_logic;
RFIFO2IP_AlmostFull : Out std_logic;
RFIFO2IP_Full : Out std_logic;
RFIFO2IP_Vacancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Outputs to the IPIF DMA/SG function
RFIFO2DMA_AlmostEmpty : Out std_logic;
RFIFO2DMA_Empty : Out std_logic;
RFIFO2DMA_Occupancy : Out std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
-- Interrupt Output to IPIF Interrupt Register
FIFO2IRPT_DeadLock : Out std_logic;
-- Outputs to the IPIF Bus
FIFO2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DBUS_WIDTH-1);
FIFO2Bus_WrAck : Out std_logic;
FIFO2Bus_RdAck : Out std_logic;
FIFO2Bus_Error : Out std_logic;
FIFO2Bus_Retry : Out std_logic;
FIFO2Bus_ToutSup : Out std_logic
);
end rdpfifo_top ;
-------------------------------------------------------------------------------
architecture implementation of rdpfifo_top is
-- COMPONENTS
--TYPES
-- no types
-- CONSTANTS
----------------------------------------------------------------------------
-- IMPORTANT!!!!!!!!!!!!!!!!!!!!!
-- Set MODULE Versioning Information Here!!!
--
-- The following three constants indicate the versioning read via the MIR
----------------------------------------------------------------------------
constant VERSION_MAJOR : integer range 0 to 9 := 1;
-- Major versioning the RPFIFO design
constant VERSION_MINOR : integer range 0 to 99:= 1;
-- Minor Version of the RPFIFO design
constant VERSION_REV : integer range 0 to 25:= 1;
-- Revision letter (0 = a, 1 = b, 2 = c, etc)
----------------------------------------------------------------------------
-- Set IPIF Block Protocol Type Here!!!!
--
----------------------------------------------------------------------------
Constant PFIFO_INTFC_TYPE : integer range 0 to 31 := 2;
-- IPIF block protocol Type
-- (Read Packet FIFO = 2, Write PFIFO = 3)
-- General Use Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
--INTERNAL SIGNALS
-- Dual Port interconnect
signal sig_mem_wrreq: std_logic;
signal sig_mem_wr_enable: std_logic;
signal sig_mem_wr_data: std_logic_vector(0 to
C_FIFO_WIDTH-1);
signal sig_mem_wr_addr: std_logic_vector(0 to
C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_addr: std_logic_vector(0 to
C_FIFO_DEPTH_LOG2X-1);
signal sig_mem_rd_data: std_logic_vector(0 to C_FIFO_WIDTH-1);
Signal sig_data_wrack: std_logic;
Signal sig_bramfifo_rdack: std_logic;
Signal sig_srlfifo_rdack: std_logic;
signal sig_fifo_full: std_logic;
signal sig_fifo_empty: std_logic;
signal sig_fifo_almost_full: std_logic;
signal sig_fifo_almost_empty: std_logic;
signal sig_fifo_occupancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
signal sig_fifo_vacancy: std_logic_vector(0 to C_FIFO_DEPTH_LOG2X);
Signal sig_burst_rd_xfer: std_logic;
Signal sig_fifo_logic_reset: std_logic;
signal sig_fifo_deadlock : std_logic;
Signal sig_bram_rdreq : std_logic;
Signal sig_srl_rdreq : std_logic;
signal sig_mem_rd_enable : std_logic;
Signal sig_bus_dbus_lsnib: std_logic_vector(0 to 3);
-------------------------------------------------------------------------------
------------- start processes -------------------------------------------------
begin
sig_bus_dbus_lsnib <= Bus_DBus(C_IPIF_DBUS_WIDTH-4 to C_IPIF_DBUS_WIDTH-1);
-- connect I/O signals to internals
RFIFO2IP_WrAck <= sig_data_wrack;
RFIFO2IP_Full <= sig_fifo_full;
RFIFO2IP_AlmostFull <= sig_fifo_almost_full;
RFIFO2DMA_AlmostEmpty <= sig_fifo_almost_empty;
RFIFO2DMA_Empty <= sig_fifo_empty;
RFIFO2IP_Vacancy <= sig_fifo_vacancy;
RFIFO2DMA_Occupancy <= sig_fifo_occupancy;
-- Some Dual Port signal assignments (vhdl wrapper)
--sig_mem_wr_enable <= not(sig_fifo_full);
sig_mem_wrreq <= IP2RFIFO_WrReq;
sig_mem_wr_data <= IP2RFIFO_Data;
I_IPIF_INTERFACE_BLOCK : entity opb_v20_v1_10_d.ipif_control_rd
Generic map (
C_MIR_ENABLE => C_MIR_ENABLE ,
C_BLOCK_ID => C_BLOCK_ID ,
C_INTFC_TYPE => PFIFO_INTFC_TYPE,
C_VERSION_MAJOR => VERSION_MAJOR,
C_VERSION_MINOR => VERSION_MINOR,
C_VERSION_REV => VERSION_REV,
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_SUPPORT_BURST => C_SUPPORT_BURST,
C_IPIF_DBUS_WIDTH => C_IPIF_DBUS_WIDTH
)
port map (
-- Inputs From the IPIF Bus
Bus_rst => Bus_rst ,
Bus_Clk => Bus_Clk ,
Bus_RdReq => Bus_RdReq ,
Bus_WrReq => Bus_WrReq ,
Bus2FIFO_RdCE1 => Bus2FIFO_RdCE1,
Bus2FIFO_RdCE2 => Bus2FIFO_RdCE2,
Bus2FIFO_RdCE3 => Bus2FIFO_RdCE3,
Bus2FIFO_WrCE1 => Bus2FIFO_WrCE1,
Bus2FIFO_WrCE2 => Bus2FIFO_WrCE2,
Bus2FIFO_WrCE3 => Bus2FIFO_WrCE3,
Bus_DBus => sig_bus_dbus_lsnib,
-- Inputs from the FIFO Interface Logic
Fifo_rd_data => sig_mem_rd_data ,
BRAMFifo_RdAck => sig_bramfifo_rdack ,
SRLFifo_RdAck => sig_srlfifo_rdack ,
Occupancy => sig_fifo_occupancy ,
AlmostEmpty => sig_fifo_almost_empty ,
Empty => sig_fifo_empty ,
Deadlock => sig_fifo_deadlock ,
-- Outputs to the FIFO
Fifo_rst => sig_fifo_logic_reset ,
BRAMFifo_RdReq => sig_bram_rdreq ,
SRLFifo_RdReq => sig_srl_rdreq ,
Fifo_burst_rd_xfer => sig_burst_rd_xfer ,
-- Outputs to the IPIF Bus
FIFO2IRPT_DeadLock => FIFO2IRPT_DeadLock ,
FIFO2Bus_DBus => FIFO2Bus_DBus ,
FIFO2Bus_WrAck => FIFO2Bus_WrAck ,
FIFO2Bus_RdAck => FIFO2Bus_RdAck ,
FIFO2Bus_Error => FIFO2Bus_Error ,
FIFO2Bus_Retry => FIFO2Bus_Retry ,
FIFO2Bus_ToutSup => FIFO2Bus_ToutSup
);
USE_BLOCK_RAM : if (C_FIFO_DEPTH_LOG2X > 4 or
C_INCLUDE_PACKET_MODE = true) generate
begin
sig_srlfifo_rdack <= '0';
-- Connect the Dual Port Address Controller to the VHDL wrapper
I_DP_CONTROLLER: entity opb_v20_v1_10_d.rdpfifo_dp_cntl
Generic map (
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_PACKET_MODE => C_INCLUDE_PACKET_MODE,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map(
-- Inputs
Bus_rst => sig_fifo_logic_reset,
Bus_clk => Bus_Clk ,
Rdreq => sig_bram_rdreq,
Wrreq => sig_mem_wrreq,
Burst_rd_xfer => sig_burst_rd_xfer,
Mark => IP2RFIFO_WrMark ,
Restore => IP2RFIFO_WrRestore,
Release => IP2RFIFO_WrRelease,
-- Outputs
WrAck => sig_data_wrack,
RdAck => sig_bramfifo_rdack,
Full => sig_fifo_full,
Empty => sig_fifo_empty,
Almost_Full => sig_fifo_almost_full,
Almost_Empty => sig_fifo_almost_empty,
DeadLock => sig_fifo_deadlock,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy,
DP_core_wren => sig_mem_wr_enable,
Wr_Addr => sig_mem_wr_addr,
DP_core_rden => sig_mem_rd_enable,
Rd_Addr => sig_mem_rd_addr
);
-- Dual Port Core connection
I_DP_CORE : entity opb_v20_v1_10_d.pf_dpram_select
generic map(
C_DP_DATA_WIDTH => C_FIFO_WIDTH,
C_DP_ADDRESS_WIDTH => C_FIFO_DEPTH_LOG2X,
C_VIRTEX_II => C_VIRTEX_II
)
port map(
-- Write Port signals
Wr_rst => sig_fifo_logic_reset,
Wr_Clk => Bus_Clk,
Wr_Enable => sig_mem_wr_enable,
Wr_Req => sig_mem_wrreq,
Wr_Address => sig_mem_wr_addr,
Wr_Data => sig_mem_wr_data,
-- Read Port Signals
Rd_rst => sig_fifo_logic_reset,
Rd_Clk => Bus_Clk,
Rd_Enable => sig_mem_rd_enable,
Rd_Address => sig_mem_rd_addr,
Rd_Data => sig_mem_rd_data
);
end generate USE_BLOCK_RAM;
USE_SRL_CORE : if (C_FIFO_DEPTH_LOG2X <= 4 and
C_INCLUDE_PACKET_MODE = False) generate
begin
sig_fifo_deadlock <= '0';
sig_srlfifo_rdack <= sig_srl_rdreq and not(sig_fifo_empty);
sig_data_wrack <= sig_mem_wrreq and not(sig_fifo_full);
sig_bramfifo_rdack <= '0';
I_SRL_MEM : entity opb_v20_v1_10_d.srl16_fifo
generic map (
C_FIFO_WIDTH => C_FIFO_WIDTH,
C_FIFO_DEPTH_LOG2X => C_FIFO_DEPTH_LOG2X,
C_INCLUDE_VACANCY => C_INCLUDE_VACANCY
)
port map (
Bus_clk => Bus_Clk,
Bus_rst => sig_fifo_logic_reset,
Wr_Req => sig_mem_wrreq,
Wr_Data => sig_mem_wr_data,
Rd_Req => sig_srl_rdreq,
Rd_Data => sig_mem_rd_data,
Full => sig_fifo_full,
Almostfull => sig_fifo_almost_full,
Empty => sig_fifo_empty,
Almostempty => sig_fifo_almost_empty,
Occupancy => sig_fifo_occupancy,
Vacancy => sig_fifo_vacancy
);
end generate USE_SRL_CORE;
end implementation;
| bsd-3-clause | 0fd139e1252a54b04ddee5f3b011ff3e | 0.451094 | 4.222502 | false | false | false | false |
michaelmiehling/A25_VME | 16z002-01_src/Source/vme_wbm.vhd | 1 | 10,259 | --------------------------------------------------------------------------------
-- Title : Wishbone Master Interface
-- Project : 16z002-01
--------------------------------------------------------------------------------
-- File : vme_wbm.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 11/02/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- The module handles the wishbone master accesses to PCI or SRAM space. If a
-- VME access to the slave gets received, the vme_slave will forward this to
-- vme_wbm. All wishbone accesses are single read/write. If there is a
-- read-modify-write request, the cyc signal between the read and write access
-- on the wishbone bus will be keept asserted to prevent access to the same
-- location in between.
--------------------------------------------------------------------------------
-- Hierarchy:
--
-- vme_ctrl
-- vme_wbm
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.4 $
--
-- $Log: vme_wbm.vhd,v $
-- Revision 1.4 2012/11/12 08:13:04 MMiehling
-- changed comments
--
-- Revision 1.3 2012/09/25 11:21:39 MMiehling
-- added wbm_err signal for error signalling from pcie to vme
--
-- Revision 1.2 2012/08/27 12:57:04 MMiehling
-- added sl_en_vma_dat_out_reg_high for d64 access
--
-- Revision 1.1 2012/03/29 10:14:29 MMiehling
-- Initial Revision
--
-- Revision 1.8 2004/11/02 11:29:40 mmiehling
-- removed iram access
--
-- Revision 1.7 2004/07/27 17:15:25 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.6 2003/12/17 15:51:35 MMiehling
-- optimized performance
--
-- Revision 1.5 2003/12/01 10:03:26 MMiehling
-- changed all
--
-- Revision 1.4 2003/06/24 13:46:47 MMiehling
-- removed burst; added loc_keep
--
-- Revision 1.3 2003/06/13 10:06:16 MMiehling
-- improved timing
--
-- Revision 1.2 2003/04/22 11:02:49 MMiehling
-- improved fsm
--
-- Revision 1.1 2003/04/01 13:04:27 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY vme_wbm IS
PORT (
clk : IN std_logic;
rst : IN std_logic;
-- mensb master
loc_keep : IN std_logic; -- if '1', csn remains active (keeps bus)
wbm_stb_o : OUT std_logic;
wbm_ack_i : IN std_logic;
wbm_err_i : IN std_logic;
wbm_we_o : IN std_logic;
vme_cyc_sram : OUT std_logic; -- keeps bus arbitration to sram as long as active
vme_cyc_pci : OUT std_logic; -- keeps bus arbitration to pci as long as active
-- vme_slave
mensb_mstr_req : IN std_logic; -- mensb master request
mensb_mstr_ack : OUT std_logic; -- mensb master acknoledge
-- vme_du
sel_wbm_dat_o : OUT std_logic;
en_wbm_dat_o : OUT std_logic;
sl_en_vme_data_out_reg : OUT std_logic; -- for normal d32 or d64 low
sl_en_vme_data_out_reg_high : OUT std_logic; -- for d64 high
-- vme_au
inc_loc_adr_m_cnt : OUT std_logic;
sl_acc_wb : IN std_logic_vector(4 DOWNTO 0); -- slave access hits and burst data transmission type
pci_acc : IN std_logic; -- pci access is requested by vmebus
sram_acc : IN std_logic -- sram access is requested by vmebus
);
END vme_wbm;
ARCHITECTURE vme_wbm_arch OF vme_wbm IS
TYPE loc_mstr_states IS (idle, req_bus, req_bus2, wait_on_end);
SIGNAL loc_mstr_state : loc_mstr_states;
SIGNAL wbm_stb_o_int : std_logic;
SIGNAL inc_wbm_cnt : std_logic;
SIGNAL mensb_mstr_ack_int : std_logic;
SIGNAL d64_high : std_logic;
SIGNAL sl_en_vme_data_out_reg_int : std_logic;
BEGIN
wbm_stb_o <= wbm_stb_o_int;
inc_loc_adr_m_cnt <= inc_wbm_cnt;
mensb_mstr_ack <= mensb_mstr_ack_int;
-- the wb-bus arbitration will be released when a single vme-transaction is done (done when asn is deasserted)
-- in case of a rmw-cycle the asn-signal will be asserted between the two transactions => the wb-bus cyc-signal
-- will also be asserted between these two transactions
-- in case of a burst, the asn-signal is asserted all the time, but the wb-bus will be released after each
-- single transaction, in order to prevent bus errors on pci-bus
regs : PROCESS(clk, rst)
BEGIN
IF rst = '1' THEN
vme_cyc_sram <= '0';
vme_cyc_pci <= '0';
d64_high <= '0';
ELSIF clk'EVENT AND clk = '1' then
IF ((wbm_ack_i = '1' OR wbm_err_i = '1') AND (wbm_we_o = '1' OR sl_acc_wb(1) = '1' OR sl_acc_wb(0) = '1')) -- burst or write
OR (loc_keep = '1' AND wbm_we_o = '0') THEN -- read and not burst (read of rmw)
vme_cyc_sram <= '0';
vme_cyc_pci <= '0';
ELSIF mensb_mstr_req = '1' AND mensb_mstr_ack_int = '0' THEN
vme_cyc_sram <= sram_acc;
vme_cyc_pci <= pci_acc;
END IF;
IF d64_high = '0' AND sl_en_vme_data_out_reg_int = '1' AND sl_acc_wb(0) = '1' AND wbm_we_o = '0' THEN
d64_high <= '1';
ELSIF sl_en_vme_data_out_reg_int = '1' THEN
d64_high <= '0';
END IF;
END IF;
END PROCESS regs;
sl_en_vme_data_out_reg <= sl_en_vme_data_out_reg_int WHEN d64_high = '0' ELSE '0';
sl_en_vme_data_out_reg_high <= sl_en_vme_data_out_reg_int WHEN d64_high = '1' ELSE '0';
loc_mstr_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
loc_mstr_state <= idle;
wbm_stb_o_int <= '0';
mensb_mstr_ack_int <= '0';
en_wbm_dat_o <= '1';
sel_wbm_dat_o <= '0';
inc_wbm_cnt <= '0';
sl_en_vme_data_out_reg_int <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE loc_mstr_state IS
WHEN idle =>
sl_en_vme_data_out_reg_int <= '0';
inc_wbm_cnt <= '0';
mensb_mstr_ack_int <= '0';
sel_wbm_dat_o <= '0';
IF mensb_mstr_req = '1' AND (sram_acc = '1' OR pci_acc = '1') THEN
loc_mstr_state <= req_bus;
wbm_stb_o_int <= '1';
en_wbm_dat_o <= '0'; -- stop loading wbm_dat_o
ELSE
loc_mstr_state <= idle;
wbm_stb_o_int <= '0';
en_wbm_dat_o <= '1'; -- always enable
END IF;
WHEN req_bus =>
IF ((wbm_ack_i = '1' OR wbm_err_i = '1') AND sl_acc_wb(0) = '0') OR mensb_mstr_req = '0' THEN
sl_en_vme_data_out_reg_int <= '1';
loc_mstr_state <= wait_on_end;
inc_wbm_cnt <= '0';
mensb_mstr_ack_int <= '1';
wbm_stb_o_int <= '0';
en_wbm_dat_o <= '0';
sel_wbm_dat_o <= '0';
ELSIF ((wbm_ack_i = '1' OR wbm_err_i = '1') AND sl_acc_wb(0) = '1') OR mensb_mstr_req = '0' THEN
sl_en_vme_data_out_reg_int <= '1';
inc_wbm_cnt <= '1'; -- increment wbm_cnt
IF wbm_we_o = '1' THEN
mensb_mstr_ack_int <= '0'; -- not yet ack, because two cycles has to be done
loc_mstr_state <= req_bus2;
ELSE
mensb_mstr_ack_int <= '1'; -- ack, because first d32 can be put to external driver
loc_mstr_state <= wait_on_end;
END IF;
wbm_stb_o_int <= '0'; -- one cycle break
en_wbm_dat_o <= '1'; -- put high d32 in wbm_dat_o
sel_wbm_dat_o <= '1';
ELSE
sl_en_vme_data_out_reg_int <= '0';
loc_mstr_state <= req_bus;
inc_wbm_cnt <= '0';
mensb_mstr_ack_int <= '0';
wbm_stb_o_int <= '1';
en_wbm_dat_o <= '0';
sel_wbm_dat_o <= '0';
END IF;
WHEN req_bus2 =>
sl_en_vme_data_out_reg_int <= '0';
inc_wbm_cnt <= '0';
en_wbm_dat_o <= '0';
sel_wbm_dat_o <= '1';
IF (wbm_ack_i = '1' OR wbm_err_i = '1') OR mensb_mstr_req = '0' THEN
loc_mstr_state <= wait_on_end;
mensb_mstr_ack_int <= '1';
wbm_stb_o_int <= '0';
ELSE
loc_mstr_state <= req_bus2;
mensb_mstr_ack_int <= '0';
wbm_stb_o_int <= '1';
END IF;
WHEN wait_on_end =>
sl_en_vme_data_out_reg_int <= '0';
inc_wbm_cnt <= '0';
en_wbm_dat_o <= '0';
wbm_stb_o_int <= '0';
loc_mstr_state <= idle;
mensb_mstr_ack_int <= '0';
sel_wbm_dat_o <= '0';
WHEN OTHERS =>
sl_en_vme_data_out_reg_int <= '0';
inc_wbm_cnt <= '0';
en_wbm_dat_o <= '0';
loc_mstr_state <= idle;
mensb_mstr_ack_int <= '0';
wbm_stb_o_int <= '0';
sel_wbm_dat_o <= '0';
END CASE;
END IF;
END PROCESS loc_mstr_fsm;
END vme_wbm_arch;
| gpl-3.0 | 2e83560c7d283f677c8b9cfd86434754 | 0.504143 | 3.412841 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/opb_v20_v1_10_d/hdl/vhdl/down_counter.vhd | 3 | 8,396 | -------------------------------------------------------------------------------
-- $Id: down_counter.vhd,v 1.1.2.1 2009/10/06 21:15:00 gburch Exp $
------------------------------------------------------------------------------
-- PLB Arbiter
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: down_counter.vhd
--
-- Description: Parameterizable down counter with synchronous load and
-- reset.
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi-use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/10/01 -- First version
--
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.STD_LOGIC_ARITH.all;
-- PROC_COMMON_PKG contains the RESET_ACTIVE constant
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_CNT_WIDTH -- counter width
--
-- Definition of Ports:
-- input Din -- data to be loaded into counter
-- input Load -- load control signal
-- input Cnt_en -- count enable signal
-- input Clk
-- input Rst
--
-- output Cnt_out -- counter output
-------------------------------------------------------------------------------
entity down_counter is
generic (
-- Select width of counter
C_CNT_WIDTH : INTEGER := 4
);
port (
Din : in std_logic_vector(0 to C_CNT_WIDTH-1);
Load : in std_logic;
Cnt_en : in std_logic;
Cnt_out : out std_logic_vector(0 to C_CNT_WIDTH - 1 );
Clk : in std_logic;
Rst : in std_logic
);
end down_counter;
architecture simulation of down_counter is
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- internal count
signal cnt : unsigned(0 to C_CNT_WIDTH - 1 );
begin
-------------------------------------------------------------------------------
-- COUNTER_PROCESS process
-------------------------------------------------------------------------------
COUNTER_PROCESS:process (Clk, Rst, Cnt_en, cnt)
begin
if Clk'event and Clk = '1' then
if Rst = RESET_ACTIVE then
cnt <= (others => '0');
elsif Load = '1' then
cnt <= unsigned(Din);
elsif Cnt_en = '1' then
cnt <= cnt - 1;
else
cnt <= cnt;
end if;
end if;
end process COUNTER_PROCESS;
CNTOUT_PROCESS:process (cnt)
begin
Cnt_out <= conv_std_logic_vector(cnt, C_CNT_WIDTH);
end process CNTOUT_PROCESS;
end simulation;
| bsd-3-clause | 37657dccdf76bc8ae3c2928922a83f16 | 0.403406 | 5.505574 | false | false | false | false |
jevinskie/aes-over-pcie | source/bridge.vhd | 1 | 19,175 | use work.aes.all;
use work.pcie.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bridge is
port (
clk : in std_logic;
nrst : in std_logic;
rx_data : in byte;
tx_data_aes : in byte;
rx_data_k : in std_logic;
aes_done : in std_logic;
tx_data: out byte;
tx_data_k : out std_logic;
got_key : out std_logic;
got_pt : out std_logic;
send_ct : out std_logic
);
end entity bridge;
architecture behavioral of bridge is
type state_type is (read_special_end, send_byte_count_lo, send_dummy_2, read_dummy_2, send_tag, send_crc_lo, send_dummy_1, send_tlp_type, read_requester_id_hi, send_lcrc_lo_hi, send_completer_id_lo, send_lcrc_hi_lo, read_addr_hi_hi, read_crc_hi, read_addr_lo_lo, send_dllp_seq_num_lo, read_dllp_seq_num_hi, read_dllp_seq_num_lo, read_addr_hi_lo, e_idle, send_crc_hi, read_lcrc_hi_hi, send_lcrc_hi_hi, read_lcrc_lo_hi, read_requestor_id_lo, read_byte_enables, read_addr_lo_hi, send_lcrc_lo_lo, read_length_hi, send_dllp_type, idle, send_requester_id_lo, read_crc_lo, read_lcrc_lo_lo, send_dllp_seq_num_hi, read_tlp_type, send_addr_lo_lo, read_dllp_type, read_dummy_1, read_tag, send_payload, read_tlp_seq_num_lo, send_tlp_length_hi, load_payload, read_lcrc_hi_lo, read_tlp_seq_num_hi, send_requester_id_hi, send_completer_id_hi, read_length_lo, send_byte_count_hi, send_tlp_seq_num_lo, send_tlp_seq_num_hi, send_tlp_length_lo, read_special_char, send_special_char, send_special_end);
signal state, next_state : state_type;
signal dllp_seq_num, next_dllp_seq_num : seq_number_type;
signal tlp_seq_num, next_tlp_seq_num : seq_number_type;
signal tlp_type, next_tlp_type : byte;
signal tag, next_tag : byte;
signal addr, next_addr : dword;
signal i, next_i : g_index;
signal i_up, i_clr : std_logic;
signal crc, next_crc : word;
signal lcrc, next_lcrc : dword;
signal send_completion, send_completion_clr : std_logic;
signal crc_clr, crc_calc : std_logic;
signal lcrc_clr, lcrc_calc : std_logic;
signal rxing : std_logic;
signal tx_data_int : byte;
signal our_crc, next_our_crc : word;
signal our_lcrc, next_our_lcrc : dword;
signal ack_dec, next_ack_dec : std_logic;
signal ack, ack_set :std_logic;
signal last_rx_data : byte;
begin
state_reg : process (clk, nrst)
begin
-- on reset, the RCU goes to the IDLE state, otherwise it goes
-- to the next state.
if (nrst = '0') then
state <= IDLE;
elsif (rising_edge(clk)) then
state <= next_state;
end if;
end process state_reg;
-- leda C_1406 off
i_reg : process(clk)
begin
if rising_edge(clk) then
i <= next_i;
end if;
end process i_reg;
-- leda C_1406 on
i_nsl : process(i, i_up, i_clr)
begin
if (i_clr = '1') then
next_i <= 0;
elsif (i_up = '1') then
next_i <= to_integer(to_unsigned(i, 4) + 1);
else
next_i <= i;
end if;
end process i_nsl;
crc_nsl: process(crc_clr, crc_calc, our_crc, rxing, last_rx_data, tx_data_int)
begin
if (crc_clr = '1') then
next_our_crc <= (others => '1');
elsif (crc_calc = '1') then
if (rxing = '1') then
next_our_crc <= crc_gen(last_rx_data, our_crc);
else
next_our_crc <= crc_gen(tx_data_int, our_crc);
end if;
else
next_our_crc <= our_crc;
end if;
end process crc_nsl;
lcrc_nsl: process(lcrc_clr, lcrc_calc, our_lcrc, rxing, last_rx_data, tx_data_int)
begin
if (lcrc_clr = '1') then
next_our_lcrc <= (others => '1');
elsif (lcrc_calc = '1') then
if (rxing = '1') then
next_our_lcrc <= lcrc_gen(last_rx_data, our_lcrc);
else
next_our_lcrc <= lcrc_gen(tx_data_int, our_lcrc);
end if;
else
next_our_lcrc <= our_lcrc;
end if;
end process lcrc_nsl;
-- leda C_1406 off
register_party : process(clk)
begin
if rising_edge(clk) then
dllp_seq_num <= next_dllp_seq_num;
tlp_seq_num <= next_tlp_seq_num;
tlp_type <= next_tlp_type;
tag <= next_tag;
addr <= next_addr;
crc <= next_crc;
our_crc <= next_our_crc;
lcrc <= next_lcrc;
our_lcrc <= next_our_lcrc;
ack_dec <= next_ack_dec;
last_rx_data <= rx_data;
end if;
end process register_party;
-- leda C_1406 off
ack_dec_nsl: process(ack_dec, ack_set, ack)
begin
if (ack_set = '1') then
next_ack_dec <= ack;
else
next_ack_dec <= ack_dec;
end if;
end process ack_dec_nsl;
completion_reg: process(clk, nrst, aes_done, tlp_type, send_completion_clr)
begin
if (nrst = '0') then
send_completion <= '0';
elsif rising_edge(clk) then
if (aes_done = '1') then
send_completion <= '1';
elsif (send_completion_clr = '1') then
send_completion <= '0';
else
send_completion <= send_completion;
end if;
end if;
end process completion_reg;
rcu_nsl : process(state, rx_data_k, rx_data, last_rx_data, send_completion, addr, i, tlp_type)
begin
next_state <= e_idle;
case state is
when idle =>
if (rx_data /= x"7C" and rx_data_k = '1') then
next_state <= read_special_char;
elsif (send_completion = '1' and tlp_type = x"00") then
next_state <= send_special_char;
else
next_state <= idle;
end if;
when read_special_char =>
if (last_rx_data = x"FB" or last_rx_data = x"5C") then
next_state <= read_dllp_type;
else
next_state <= e_idle;
end if;
when send_special_char =>
next_state <= send_dllp_type;
when send_special_end =>
next_state <= idle;
when read_dllp_type =>
next_state <= read_dummy_1;
when read_dummy_1 =>
next_state <= read_dllp_seq_num_hi;
when read_dllp_seq_num_hi =>
next_state <= read_dllp_seq_num_lo;
when read_dllp_seq_num_lo =>
next_state <= read_crc_hi;
when read_crc_hi =>
next_state <= read_crc_lo;
when read_crc_lo =>
-- done reading dllp, going to lp
next_state <= read_tlp_seq_num_hi;
when read_tlp_seq_num_hi =>
next_state <= read_tlp_seq_num_lo;
when read_tlp_seq_num_lo =>
-- done reading lp, going to tlp
next_state <= read_tlp_type;
when read_tlp_type =>
next_state <= read_dummy_2;
when read_dummy_2 =>
next_state <= read_length_hi;
when read_length_hi =>
next_state <= read_length_lo;
when read_length_lo =>
next_state <= read_requester_id_hi;
when read_requester_id_hi =>
next_state <= read_requestor_id_lo;
when read_requestor_id_lo =>
next_state <= read_tag;
when read_tag =>
next_state <= read_byte_enables;
when read_byte_enables =>
next_state <= read_addr_hi_hi;
when read_addr_hi_hi =>
next_state <= read_addr_hi_lo;
when read_addr_hi_lo =>
next_state <= read_addr_lo_hi;
when read_addr_lo_hi =>
next_state <= read_addr_lo_lo;
when read_addr_lo_lo =>
if (addr(31 downto 8) & last_rx_data = x"00001000") then
next_state <= load_payload;
elsif (addr(31 downto 8) & last_rx_data = x"00002000") then
next_state <= load_payload;
elsif (addr(31 downto 8) & last_rx_data = x"00003000") then
next_state <= read_lcrc_hi_hi;
else
next_state <= e_idle;
end if;
when load_payload =>
if (i /= 15) then
next_state <= load_payload;
else
next_state <= read_lcrc_hi_hi;
end if;
when read_lcrc_hi_hi =>
next_state <= read_lcrc_hi_lo;
when read_lcrc_hi_lo =>
next_state <= read_lcrc_lo_hi;
when read_lcrc_lo_hi =>
next_state <= read_lcrc_lo_lo;
when read_lcrc_lo_lo =>
next_state <= read_special_end;
when send_dllp_type =>
-- sends ack or nak
next_state <= send_dummy_1;
when send_dummy_1 =>
next_state <= send_dllp_seq_num_hi;
when send_dllp_seq_num_hi =>
next_state <= send_dllp_seq_num_lo;
when send_dllp_seq_num_lo =>
next_state <= send_crc_hi;
when send_crc_hi =>
next_state <= send_crc_lo;
when send_crc_lo =>
-- either go to idle after an ack/nak or send the ct
--if (tlp_type = "00001010") then --type is CplD
if (send_completion = '1') then
next_state <= send_tlp_seq_num_hi;
else
next_state <= send_special_end;
end if;
when send_tlp_seq_num_hi =>
next_state <= send_tlp_seq_num_lo;
when send_tlp_seq_num_lo =>
next_state <= send_tlp_type;
when send_tlp_type =>
next_state <= send_dummy_2;
when send_dummy_2 =>
next_state <= send_tlp_length_hi;
when send_tlp_length_hi =>
next_state <= send_tlp_length_lo;
when send_tlp_length_lo =>
next_state <= send_completer_id_hi;
when send_completer_id_hi =>
next_state <= send_completer_id_lo;
when send_completer_id_lo =>
next_state <= send_byte_count_hi;
when send_byte_count_hi =>
next_state <= send_byte_count_lo;
when send_byte_count_lo =>
next_state <= send_requester_id_hi;
when send_requester_id_hi =>
next_state <= send_requester_id_lo;
when send_requester_id_lo =>
next_state <= send_tag;
when send_tag =>
next_state <= send_addr_lo_lo;
when send_addr_lo_lo =>
next_state <= send_payload;
when send_payload =>
if (i /= 15) then
next_state <= send_payload;
else
next_state <= send_lcrc_hi_hi;
end if;
when send_lcrc_hi_hi =>
next_state <= send_lcrc_hi_lo;
when send_lcrc_hi_lo =>
next_state <= send_lcrc_lo_hi;
when send_lcrc_lo_hi =>
next_state <= send_lcrc_lo_lo;
when send_lcrc_lo_lo =>
next_state <= send_special_end;
when read_special_end =>
if (last_rx_data = x"FD") then
next_state <= send_special_char;
else
next_state <= e_idle;
end if;
when others =>
next_state <= e_idle;
end case;
end process rcu_nsl;
bridge_output : process(state, addr, rx_data, tx_data_aes, dllp_seq_num, tlp_seq_num, tlp_type, tag, lcrc, crc, our_crc, ack_dec, last_rx_data, our_lcrc)
begin
tx_data_int <= x"7C"; -- idl
tx_data_k <= '1'; -- control byte
got_key <= '0';
got_pt <= '0';
send_ct <= '0';
send_completion_clr <= '0';
crc_clr <= '0';
lcrc_clr <= '0';
rxing <= '1';
crc_calc <= '0';
lcrc_calc <= '0';
ack <= '0';
ack_set <= '0';
i_clr <= '1';
i_up <= '0';
next_dllp_seq_num <= dllp_seq_num;
next_tlp_seq_num <= tlp_seq_num;
next_tlp_type <= tlp_type;
next_tag <= tag;
next_addr <= addr;
next_lcrc <= lcrc;
next_crc <= crc;
case state is
when idle =>
-- already logic idling
crc_clr <= '1';
lcrc_clr <= '1';
when read_special_char =>
-- nothing?
when read_special_end =>
crc_clr <= '1';
when send_special_char =>
tx_data_int <= x"FB";
tx_data_k <= '1';
when read_dllp_type =>
crc_calc <= '1';
when read_dummy_1 =>
crc_calc <= '1';
when read_addr_lo_lo =>
lcrc_calc <= '1';
next_addr(7 downto 0) <= last_rx_data;
if (addr(31 downto 8) & last_rx_data = x"00001000") then
got_key <= '1';
elsif (addr(31 downto 8) & last_rx_data = x"00002000") then
got_pt <= '1';
end if;
when send_addr_lo_lo =>
tx_data_int <= "0" & addr(6 downto 0);
tx_data_k <= '0';
lcrc_calc <= '1';
rxing <= '0';
send_ct <= '1';
when read_dllp_seq_num_hi =>
next_dllp_seq_num(11 downto 8) <= last_rx_data(3 downto 0);
crc_calc <= '1';
when read_dllp_seq_num_lo =>
next_dllp_seq_num(7 downto 0) <= last_rx_data;
crc_calc <= '1';
when read_tlp_seq_num_hi =>
next_tlp_seq_num(11 downto 8) <= last_rx_data(3 downto 0);
when read_tlp_seq_num_lo =>
next_tlp_seq_num(7 downto 0) <= last_rx_data;
when read_crc_hi =>
next_crc(15 downto 8) <= last_rx_data;
when read_crc_lo => --check vs our calculated CRC to determine ack or nak
next_crc(7 downto 0) <= last_rx_data;
ack_set <= '1';
if (our_crc = crc(15 downto 8) & last_rx_data) then
ack <= '1';
else
ack <= '0';
end if;
when read_lcrc_hi_hi =>
next_lcrc(31 downto 24) <= last_rx_data;
when read_lcrc_hi_lo =>
next_lcrc(23 downto 16) <= last_rx_data;
when read_lcrc_lo_hi =>
next_lcrc(15 downto 8) <= last_rx_data;
when read_lcrc_lo_lo =>
next_lcrc(7 downto 0) <= last_rx_data;
when read_tlp_type =>
lcrc_calc <= '1';
next_tlp_type <= last_rx_data;
when read_length_hi =>
lcrc_calc <= '1';
when read_length_lo =>
lcrc_calc <= '1';
when read_tag =>
lcrc_calc <= '1';
next_tag <= last_rx_data;
when read_addr_hi_hi =>
lcrc_calc <= '1';
next_addr(31 downto 24) <= last_rx_data;
when read_addr_hi_lo =>
lcrc_calc <= '1';
next_addr(23 downto 16) <= last_rx_data;
when read_addr_lo_hi =>
lcrc_calc <= '1';
next_addr(15 downto 8) <= last_rx_data;
when load_payload =>
lcrc_calc <= '1';
i_clr <= '0';
i_up <= '1';
when read_dummy_2 =>
lcrc_calc <= '1';
when read_requester_id_hi =>
lcrc_calc <= '1';
when read_requestor_id_lo =>
lcrc_calc <= '1';
when read_byte_enables =>
lcrc_calc <= '1';
when send_lcrc_hi_hi =>
tx_data_int<= our_lcrc(31 downto 24);
tx_data_k <= '0';
when send_lcrc_hi_lo =>
tx_data_int<= our_lcrc(23 downto 16);
tx_data_k <= '0';
when send_lcrc_lo_hi =>
tx_data_int<= our_lcrc(15 downto 8);
tx_data_k <= '0';
when send_lcrc_lo_lo =>
tx_data_int <= our_lcrc(7 downto 0);
tx_data_k <= '0';
when send_payload =>
i_up <= '1';
i_clr <= '0';
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= tx_data_aes;
tx_data_k <= '0';
when send_tag =>
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= tag;
tx_data_k <= '0';
when send_dllp_type =>
crc_calc <= '1';
rxing <= '0';
tx_data_int <= "000" & ack_dec & "0000";
tx_data_k <= '0';
when send_dummy_1 =>
crc_calc <= '1';
rxing <= '0';
tx_data_int<= "00000000";
tx_data_k <= '0';
when send_dllp_seq_num_hi =>
crc_calc <= '1';
rxing <= '0';
tx_data_int<= "0000" & dllp_seq_num(11 downto 8);
tx_data_k <= '0';
when send_dllp_seq_num_lo =>
crc_calc <= '1';
rxing <= '0';
tx_data_int<= dllp_seq_num(7 downto 0);
tx_data_k <= '0';
when send_crc_hi =>
tx_data_int<= our_crc(15 downto 8);
tx_data_k <= '0';
when send_crc_lo =>
tx_data_int<= our_crc(7 downto 0);
tx_data_k <= '0';
when send_tlp_seq_num_hi =>
send_completion_clr <= '1';
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= "0000" & tlp_seq_num(11 downto 8);
tx_data_k <= '0';
when send_tlp_seq_num_lo =>
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= tlp_seq_num(7 downto 0);
tx_data_k <= '0';
when send_tlp_type =>
lcrc_calc <= '1';
rxing <= '0';
tx_data_int <= "00001010"; -- cpld
tx_data_k <= '0';
when send_dummy_2 =>
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= "00000000";
tx_data_k <= '0';
when send_tlp_length_hi =>
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= "00000000";
tx_data_k <= '0';
when send_tlp_length_lo =>
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= "00000100";
tx_data_k <= '0';
when send_completer_id_hi =>
lcrc_calc <= '1';
rxing <= '0';
send_completion_clr <= '1';
tx_data_int<= "00000000";
tx_data_k <= '0';
when send_completer_id_lo =>
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= "00010001";
tx_data_k <= '0';
when send_byte_count_hi =>
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= "00000000"; ---first 3 bits are status, 000 for success
tx_data_k <= '0';
when send_byte_count_lo =>
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= "00010000";
tx_data_k <= '0';
when send_requester_id_hi =>
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= "00000000";
tx_data_k <= '0';
when send_requester_id_lo =>
lcrc_calc <= '1';
rxing <= '0';
tx_data_int<= "00000001";
tx_data_k <= '0';
when send_special_end =>
tx_data_int <= x"FD";
tx_data_k <= '1';
when others =>
end case;
end process bridge_output;
tx_data <= tx_data_int;
end architecture behavioral;
| bsd-3-clause | a0a3e99437b5b9b03eaec77bfc2501fd | 0.485163 | 3.380642 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/pf_occ_counter.vhd | 2 | 10,963 | -------------------------------------------------------------------------------
-- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_occ_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_occ_counter.vhd
--
-- Description: Implements packet fifo occupancy counter. This special
-- counter provides these functions:
-- - up/down count control
-- - pre-increment/pre-decrement of input load value
-- - count by 2
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_occ_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- D. Thorpe 2001-09-07 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst signal connect to the pf_counter_bit module
--
-- DET 2002-02-24
-- - Changed the use of MUXCY_L to MUXCY.
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_occ_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Cnt_by_2 : In std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_occ_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_occ_counter is
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal i_mux_Count_Out : std_logic_vector(0 to C_COUNT_WIDTH-2);
signal count_clock_en : std_logic;
signal carry_out_lsb : std_logic;
signal carry_in_lsb : std_logic;
signal count_out_lsb : std_logic;
Signal mux_cnt_in_lsb : std_logic;
Signal carry_out_select_di: std_logic;
Signal carry_start : std_logic;
Signal carry_start_select : std_logic;
Signal by_2_carry_start : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
count_clock_en <= Count_Enable or Count_Load;
MUX_THE_LSB_INPUT : process (count_out_lsb, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
mux_cnt_in_lsb <= count_out_lsb;
else
mux_cnt_in_lsb <= Load_In(C_COUNT_WIDTH-1);
End if;
End process MUX_THE_LSB_INPUT;
carry_start <= Count_Down xor Count_Enable;
by_2_carry_start <= Cnt_by_2 and Count_Down;
carry_start_select <= not(Cnt_by_2);
I_MUXCY_LSB_IN : MUXCY
port map (
DI => by_2_carry_start,
CI => carry_start,
S => carry_start_select,
O => carry_in_lsb);
I_COUNTER_BIT_LSB : entity proc_common_v3_00_a.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => mux_cnt_in_lsb,
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => carry_in_lsb,
Clock_Enable => count_clock_en,
Result => count_out_lsb,
Carry_Out => carry_out_lsb);
carry_out_select_di <= Count_Down xor Cnt_by_2;
I_MUXCY_LSB_OUT : MUXCY
port map (
DI => carry_out_select_di,
CI => carry_out_lsb,
S => carry_start_select,
O => alu_cy(C_COUNT_WIDTH-1));
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-2 generate
begin
MUX_THE_INPUT : process (iCount_Out, Load_In, Count_Load)
Begin
If (Count_Load = '0') Then
i_mux_Count_Out(i) <= iCount_Out(i);
else
i_mux_Count_Out(i) <= Load_In(i);
End if;
End process MUX_THE_INPUT;
Counter_Bit_I : entity proc_common_v3_00_a.pf_counter_bit
port map (
Clk => Clk,
Rst => Rst,
Count_In => i_mux_Count_Out(i),
Load_In => '0',
Count_Load => '0',
Count_Down => Count_Down,
Carry_In => alu_cy(i+1),
Clock_Enable => count_clock_en,
Result => iCount_Out(i),
Carry_Out => alu_cy(i));
end generate I_ADDSUB_GEN;
Count_Out <= iCount_Out & count_out_lsb;
Carry_Out <= '0';
end architecture implementation;
| bsd-3-clause | f7bab8d4a796a56cac721d6a3a297418 | 0.438201 | 4.594719 | false | false | false | false |
michaelmiehling/A25_VME | 16z100-00_src/Source/switch_fab_3.vhd | 1 | 18,172 | ---------------------------------------------------------------
-- Title :
-- Project :
---------------------------------------------------------------
-- File : switch_fab_3.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 25/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.4 $
--
-- $Log: switch_fab_3.vhd,v $
-- Revision 1.4 2015/06/15 16:39:57 AGeissler
-- R1: In 16z100- version 1.30 the bte signal was removed from the wb_pkg.vhd
-- M1: Adapted switch fabric
-- R2: Clearness
-- M2: Replaced tabs with spaces
--
-- Revision 1.3 2007/08/13 10:14:21 MMiehling
-- added: master gets no ack if corresponding stb is not active
--
-- Revision 1.2 2007/04/04 13:15:15 smahveen
-- cyc_x handling in SW_2 corrected.
-- (FSM state will not change after WB Master-3 access wishbone slave in SW_2 state)
--
-- Revision 1.1 2004/08/13 15:16:06 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/08/13 15:10:49 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/07/27 17:06:21 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/04/29 15:07:24 MMiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.wb_pkg.all;
ENTITY switch_fab_3 IS
GENERIC (
registered : IN boolean );
PORT (
clk : IN std_logic;
rst : IN std_logic;
cyc_0 : IN std_logic;
ack_0 : OUT std_logic;
err_0 : OUT std_logic;
wbo_0 : IN wbo_type;
cyc_1 : IN std_logic;
ack_1 : OUT std_logic;
err_1 : OUT std_logic;
wbo_1 : IN wbo_type;
cyc_2 : IN std_logic;
ack_2 : OUT std_logic;
err_2 : OUT std_logic;
wbo_2 : IN wbo_type;
wbo_slave : IN wbi_type;
wbi_slave : OUT wbo_type;
wbi_slave_cyc : OUT std_logic
);
END switch_fab_3;
ARCHITECTURE switch_fab_3_arch OF switch_fab_3 IS
SUBTYPE sw_states IS std_logic_vector(1 DOWNTO 0);
CONSTANT sw_0 : sw_states := "01";
CONSTANT sw_1 : sw_states := "10";
CONSTANT sw_2 : sw_states := "11";
SIGNAL sw_state : sw_states;
SIGNAL sw_nxt_state : sw_states;
SIGNAL ack_0_int : std_logic;
SIGNAL ack_1_int : std_logic;
SIGNAL ack_2_int : std_logic;
SIGNAL sel : std_logic_vector(2 DOWNTO 0);
SIGNAL wbi_slave_stb : std_logic;
BEGIN
without_q : IF NOT registered GENERATE
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave_stb <= '0';
sw_state <= sw_0;
ELSIF clk'EVENT AND clk = '1' THEN
sw_state <= sw_nxt_state;
CASE sw_nxt_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_1.stb;
ELSIF wbo_slave.ack = '1' AND wbo_1.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_2 = '1' THEN
wbi_slave_stb <= wbo_2.stb;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_2.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_2.stb;
ELSIF wbo_slave.ack = '1' AND wbo_2.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_2.stb;
END IF;
ELSIF cyc_0 = '1' THEN
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_1 = '1' THEN
wbi_slave_stb <= wbo_1.stb;
ELSE
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1, cyc_2)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSE
sw_nxt_state <= sw_0;
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSIF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSE
sw_nxt_state <= sw_1;
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
sw_nxt_state <= sw_2;
ELSIF cyc_0 = '1' THEN
sw_nxt_state <= sw_0;
ELSIF cyc_1 = '1' THEN
sw_nxt_state <= sw_1;
ELSE
sw_nxt_state <= sw_2;
END IF;
WHEN OTHERS =>
sw_nxt_state <= sw_0;
END CASE;
END PROCESS sw_fsm_sel;
PROCESS(sw_state, wbo_0.dat, wbo_1.dat, wbo_2.dat)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.dat <= wbo_0.dat;
WHEN sw_1 => wbi_slave.dat <= wbo_1.dat;
WHEN sw_2 => wbi_slave.dat <= wbo_2.dat;
WHEN OTHERS => wbi_slave.dat <= wbo_0.dat;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.adr, wbo_1.adr, wbo_2.adr)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.adr <= wbo_0.adr;
WHEN sw_1 => wbi_slave.adr <= wbo_1.adr;
WHEN sw_2 => wbi_slave.adr <= wbo_2.adr;
WHEN OTHERS => wbi_slave.adr <= wbo_0.adr;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.sel, wbo_1.sel, wbo_2.sel)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.sel <= wbo_0.sel;
WHEN sw_1 => wbi_slave.sel <= wbo_1.sel;
WHEN sw_2 => wbi_slave.sel <= wbo_2.sel;
WHEN OTHERS => wbi_slave.sel <= wbo_0.sel;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.we, wbo_1.we, wbo_2.we)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.we <= wbo_0.we;
WHEN sw_1 => wbi_slave.we <= wbo_1.we;
WHEN sw_2 => wbi_slave.we <= wbo_2.we;
WHEN OTHERS => wbi_slave.we <= wbo_0.we;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.cti, wbo_1.cti, wbo_2.cti)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.cti <= wbo_0.cti;
WHEN sw_1 => wbi_slave.cti <= wbo_1.cti;
WHEN sw_2 => wbi_slave.cti <= wbo_2.cti;
WHEN OTHERS => wbi_slave.cti <= wbo_0.cti;
END CASE;
END PROCESS;
PROCESS(sw_state, wbo_0.tga, wbo_1.tga, wbo_2.tga)
BEGIN
CASE sw_state IS
WHEN sw_0 => wbi_slave.tga <= wbo_0.tga;
WHEN sw_1 => wbi_slave.tga <= wbo_1.tga;
WHEN sw_2 => wbi_slave.tga <= wbo_2.tga;
WHEN OTHERS => wbi_slave.tga <= wbo_0.tga;
END CASE;
END PROCESS;
wbi_slave.stb <= wbi_slave_stb;
wbi_slave_cyc <= '1' WHEN (sw_state = sw_0 AND cyc_0 = '1') OR (sw_state = sw_1 AND cyc_1 = '1') OR (sw_state = sw_2 AND cyc_2 = '1') ELSE '0';
ack_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
ack_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
ack_2 <= '1' WHEN sw_state = sw_2 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' ELSE '0';
err_0 <= '1' WHEN sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
err_1 <= '1' WHEN sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
err_2 <= '1' WHEN sw_state = sw_2 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' ELSE '0';
END GENERATE without_q;
---------------------------------------------------------------------
with_q : IF registered GENERATE
ack_0 <= ack_0_int;
ack_1 <= ack_1_int;
ack_2 <= ack_2_int;
wbi_slave.stb <= wbi_slave_stb;
sw_fsm : PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN
sw_state <= sw_0;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave_stb <= wbo_0.stb;
ELSIF (wbo_slave.ack = '1' OR ack_0_int = '1') AND wbo_0.cti /= "010" THEN -- single
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_0.stb;
END IF;
ELSIF cyc_1 = '1' THEN
sw_state <= sw_1;
wbi_slave_stb <= wbo_1.stb;
ELSIF cyc_2 = '1' THEN
sw_state <= sw_2;
wbi_slave_stb <= wbo_2.stb;
ELSE
sw_state <= sw_0;
wbi_slave_stb <= '0';
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN
sw_state <= sw_1;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_1.cti = "010" THEN -- single
wbi_slave_stb <= wbo_0.stb;
ELSIF (wbo_slave.ack = '1' OR ack_1_int = '1') AND wbo_1.cti /= "010" THEN -- burst
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_1.stb;
END IF;
ELSIF cyc_0 = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_2 = '1' THEN
sw_state <= sw_2;
wbi_slave_stb <= wbo_2.stb;
ELSE
sw_state <= sw_1;
wbi_slave_stb <= '0';
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN
sw_state <= sw_2;
IF wbo_slave.err = '1' THEN -- error
wbi_slave_stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_2.cti = "010" THEN -- single
wbi_slave_stb <= wbo_2.stb;
ELSIF (wbo_slave.ack = '1' OR ack_2_int = '1') AND wbo_2.cti /= "010" THEN -- burst
wbi_slave_stb <= '0';
ELSE
wbi_slave_stb <= wbo_2.stb;
END IF;
ELSIF cyc_0 = '1' THEN
sw_state <= sw_0;
wbi_slave_stb <= wbo_0.stb;
ELSIF cyc_1 = '1' THEN
sw_state <= sw_1;
wbi_slave_stb <= wbo_1.stb;
ELSE
sw_state <= sw_2;
wbi_slave_stb <= '0';
END IF;
WHEN OTHERS =>
sw_state <= sw_0;
wbi_slave_stb <= '0';
END CASE;
END IF;
END PROCESS sw_fsm;
sw_fsm_sel : PROCESS(sw_state, cyc_0, cyc_1, cyc_2)
BEGIN
CASE sw_state IS
WHEN sw_0 =>
IF cyc_0 = '1' THEN sel <= "001";
ELSIF cyc_1 = '1' THEN sel <= "010";
ELSIF cyc_2 = '1' THEN sel <= "100";
ELSE sel <= "000";
END IF;
WHEN sw_1 =>
IF cyc_1 = '1' THEN sel <= "010";
ELSIF cyc_2 = '1' THEN sel <= "100";
ELSIF cyc_0 = '1' THEN sel <= "001";
ELSE sel <= "000";
END IF;
WHEN sw_2 =>
IF cyc_2 = '1' THEN sel <= "100";
ELSIF cyc_1 = '1' THEN sel <= "010";
ELSIF cyc_0 = '1' THEN sel <= "001";
ELSE sel <= "000";
END IF;
WHEN OTHERS => sel <= "000";
END CASE;
END PROCESS sw_fsm_sel;
data_sw : PROCESS( clk, rst)
BEGIN
IF rst = '1' THEN
wbi_slave.dat <= (OTHERS => '0');
wbi_slave.adr <= (OTHERS => '0');
wbi_slave.sel <= (OTHERS => '0');
wbi_slave.cti <= (OTHERS => '0');
wbi_slave.tga <= (OTHERS => '0');
wbi_slave.we <= '0';
wbi_slave_cyc <= '0';
ack_0_int <= '0';
err_0 <= '0';
ack_1_int <= '0';
err_1 <= '0';
ack_2_int <= '0';
err_2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
wbi_slave_cyc <= sel(0) OR sel(1) OR sel(2);
IF sw_state = sw_0 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_0_int <= '1';
ELSE
ack_0_int <= '0';
END IF;
IF sw_state = sw_0 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_0 <= '1';
ELSE
err_0 <= '0';
END IF;
IF sw_state = sw_1 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_1_int <= '1';
ELSE
ack_1_int <= '0';
END IF;
IF sw_state = sw_1 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_1 <= '1';
ELSE
err_1 <= '0';
END IF;
IF sw_state = sw_2 AND wbo_slave.ack = '1' AND wbi_slave_stb = '1' THEN
ack_2_int <= '1';
ELSE
ack_2_int <= '0';
END IF;
IF sw_state = sw_2 AND wbo_slave.err = '1' AND wbi_slave_stb = '1' THEN
err_2 <= '1';
ELSE
err_2 <= '0';
END IF;
CASE sel IS
WHEN "001" => wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.tga <= wbo_0.tga;
WHEN "010" => wbi_slave.dat <= wbo_1.dat;
wbi_slave.adr <= wbo_1.adr;
wbi_slave.sel <= wbo_1.sel;
wbi_slave.we <= wbo_1.we;
wbi_slave.cti <= wbo_1.cti;
wbi_slave.tga <= wbo_1.tga;
WHEN OTHERS => wbi_slave.dat <= wbo_2.dat;
wbi_slave.adr <= wbo_2.adr;
wbi_slave.sel <= wbo_2.sel;
wbi_slave.we <= wbo_2.we;
wbi_slave.cti <= wbo_2.cti;
wbi_slave.tga <= wbo_2.tga;
END CASE;
END IF;
END PROCESS data_sw;
END GENERATE with_q;
END switch_fab_3_arch;
| gpl-3.0 | e30ea306875f97764d57ef40c8891b40 | 0.410192 | 3.668147 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/platforms/xilinx/smp3_opbhwti_lbrams/design/pcores/plbv46_opb_bridge_v1_01_a/hdl/vhdl/plbv46_opb_bridge.vhd | 3 | 23,097 | -------------------------------------------------------------------------------
-- $Id: plbv46_opb_bridge.vhd,v 1.1.2.1 2008/12/19 20:58:34 mlovejoy Exp $
-------------------------------------------------------------------------------
-- plbv46_opb_bridge.vhd - Version v1_00_a
-------------------------------------------------------------------------------
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
-- Filename: plbv46_opb_bridge.vhd
-- VHDL Library: plbv46_opb_bridge_v1_01_a
-- Version: v1_00_a $Revision: 1.1.2.1 $
-- Description:
--
-------------------------------------------------------------------------------
-- Structure:
--
-- plbv46_opb_bridge(syn)
-- plbv46_opb_bridge_v1_01_a.opb_master
-- plbv46_slave_burst_v1_01_a.plbv46_slave_burst
--
-------------------------------------------------------------------------------
-- Author: <Tim Davis>
--
-- History:
--
-- TRD 9/8/2006
-- ~~~~~~
-- - Initial release of v1_00_a
-- ^^^^^^
-- MLL 8/28/2008
-- New version plbv46_opb_bridge_v1_01_a to include new
-- plbv46_slave_burst_v1_01_a and proc_common v3.00.a.
-- Also added coverage off/on for code coverage testing.
-- Removed Changelog and DISCLAIMER OF LIABILITY updated.
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY proc_common_v3_00_a;
USE proc_common_v3_00_a.proc_common_pkg.ALL;
USE proc_common_v3_00_a.family.ALL;
USE proc_common_v3_00_a.ipif_pkg.ALL;
-------------------------------------------------------------------------------
ENTITY plbv46_opb_bridge IS
GENERIC (
C_NUM_ADDR_RNG : integer := 1;
C_RNG0_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_RNG0_HIGHADDR : std_logic_vector := X"00000000";
C_RNG1_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_RNG1_HIGHADDR : std_logic_vector := X"00000000";
C_RNG2_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_RNG2_HIGHADDR : std_logic_vector := X"00000000";
C_RNG3_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_RNG3_HIGHADDR : std_logic_vector := X"00000000";
-- Optimize slave interface for a point to point connection
C_SPLB_P2P : integer RANGE 0 TO 1 := 0;
-- Selects the addressing mode to use for Cacheline Read
-- operations.
-- 0 = Legacy Read mode (target word first)
-- 1 = Realign target word address to Cacheline aligned and
-- then do a linear incrementing addressing from start
-- to end of the Cacheline (PCI Bridge enhancement).
-- The width of the Master ID bus
-- This is set to log2(C_SPLB_NUM_MASTERS)
C_SPLB_MID_WIDTH : integer RANGE 1 TO 4 := 3;
-- The number of Master Devices connected to the PLB bus
-- Research this to find out default value
C_SPLB_NUM_MASTERS : integer RANGE 1 TO 16 := 8;
-- The dwidth (in bits) of the smallest master that will
-- access this ipif.
C_SPLB_SMALLEST_MASTER : integer RANGE 32 TO 128 := 32;
-- width of the PLB Address Bus (in bits)
C_SPLB_AWIDTH : integer RANGE 32 TO 36 := 32;
-- Width of the PLB Data Bus (in bits)
C_SPLB_DWIDTH : integer RANGE 32 TO 128 := 32;
-- Ratio of PLB:OPB bus clocks periods. 1=1:1, 2=1:2
C_BUS_CLOCK_PERIOD_RATIO : integer RANGE 1 TO 2 := 1;
-- Select the target architecture type
-- see the family.vhd package in the proc_common library
C_FAMILY : string := virtex4
);
PORT (
-- System signals ---------------------------------------------------------
SPLB_Clk : IN std_logic;
SPLB_Rst : IN std_logic;
-- PLBv46 Bus Slave signals ------------------------------------------------------
PLB_ABus : IN std_logic_vector(0 TO 31);
PLB_UABus : IN std_logic_vector(0 TO 31);
PLB_PAValid : IN std_logic;
PLB_SAValid : IN std_logic;
PLB_rdPrim : IN std_logic;
PLB_wrPrim : IN std_logic;
PLB_masterID : IN std_logic_vector(0 TO C_SPLB_MID_WIDTH-1);
PLB_abort : IN std_logic;
PLB_busLock : IN std_logic;
PLB_RNW : IN std_logic;
PLB_BE : IN std_logic_vector(0 TO (C_SPLB_DWIDTH/8)-1);
PLB_MSize : IN std_logic_vector(0 TO 1);
PLB_size : IN std_logic_vector(0 TO 3);
PLB_type : IN std_logic_vector(0 TO 2);
PLB_lockErr : IN std_logic;
PLB_wrDBus : IN std_logic_vector(0 TO C_SPLB_DWIDTH-1);
PLB_wrBurst : IN std_logic;
PLB_rdBurst : IN std_logic;
PLB_wrPendReq : IN std_logic;
PLB_rdPendReq : IN std_logic;
PLB_wrPendPri : IN std_logic_vector(0 TO 1);
PLB_rdPendPri : IN std_logic_vector(0 TO 1);
PLB_reqPri : IN std_logic_vector(0 TO 1);
PLB_TAttribute : IN std_logic_vector(0 TO 15);
-- Slave Response Signals
Sl_addrAck : OUT std_logic;
Sl_SSize : OUT std_logic_vector(0 TO 1);
Sl_wait : OUT std_logic;
Sl_rearbitrate : OUT std_logic;
Sl_wrDAck : OUT std_logic;
Sl_wrComp : OUT std_logic;
Sl_wrBTerm : OUT std_logic;
Sl_rdDBus : OUT std_logic_vector(0 TO C_SPLB_DWIDTH-1);
Sl_rdWdAddr : OUT std_logic_vector(0 TO 3);
Sl_rdDAck : OUT std_logic;
Sl_rdComp : OUT std_logic;
Sl_rdBTerm : OUT std_logic;
Sl_MBusy : OUT std_logic_vector (0 TO C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : OUT std_logic_vector (0 TO C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : OUT std_logic_vector (0 TO C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : OUT std_logic_vector (0 TO C_SPLB_NUM_MASTERS-1);
-- OPBv20 master signals
OPB_Clk : IN std_logic;
OPB_Rst : IN std_logic;
Mn_request : OUT std_logic;
Mn_busLock : OUT std_logic;
Mn_select : OUT std_logic;
Mn_RNW : OUT std_logic;
Mn_BE : OUT std_logic_vector(0 TO 32/8-1);
Mn_seqAddr : OUT std_logic;
Mn_DBus : OUT std_logic_vector(0 TO 32-1);
Mn_ABus : OUT std_logic_vector(0 TO 31);
OPB_MGrant : IN std_logic;
OPB_xferAck : IN std_logic;
OPB_errAck : IN std_logic;
OPB_retry : IN std_logic;
OPB_timeout : IN std_logic;
OPB_DBus : IN std_logic_vector(0 TO 32 - 1)
);
END plbv46_opb_bridge;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
LIBRARY plbv46_slave_burst_v1_01_a;
LIBRARY plbv46_opb_bridge_v1_01_a;
ARCHITECTURE syn OF plbv46_opb_bridge IS
--coverage off
FUNCTION int2bool (
CONSTANT i : integer)
RETURN boolean IS
BEGIN
IF (i = 0) THEN
RETURN FALSE;
ELSE
RETURN TRUE;
END IF;
END FUNCTION int2bool;
--coverage on
CONSTANT C_SIPIF_DWIDTH : integer := 32;
CONSTANT C_WR_BUFFER_DEPTH : integer := 16;
-- Selects the addressing mode to use for Cacheline Read
-- operations.
-- 0 = Legacy Read mode (target word first). For this mode the cacheline
-- transaction generates a sequence of addresses starting at the target
-- word address and wrapping around to the start of the cache line. The
-- bus2ip_burst signal asserts for all of the addresses. (This is not
-- acceptable for the bridge because the opb_master would violate the
-- OPBv20 spec for the Mn_seqAddr signal.)
-- 1 = Realign target word address to Cacheline aligned and
-- then do a linear incrementing addressing from start
-- to end of the Cacheline (PCI Bridge enhancement).
CONSTANT C_CACHELINE_ADDR_MODE : integer RANGE 0 TO 1 := 1;
-- The chip selects ARD array must be built from all available generics then
-- reduced in size to those that are actually used. The first N pairs are
-- used and the rest are ignored.
CONSTANT C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
proc_common_v3_00_a.ipif_pkg.rebuild_slv64_array(
num_valid_pairs => C_NUM_ADDR_RNG,
slv64_array => (
0 => X"0000_0000" & C_RNG0_BASEADDR,
1 => X"0000_0000" & C_RNG0_HIGHADDR,
2 => X"0000_0000" & C_RNG1_BASEADDR,
3 => X"0000_0000" & C_RNG1_HIGHADDR,
4 => X"0000_0000" & C_RNG2_BASEADDR,
5 => X"0000_0000" & C_RNG2_HIGHADDR,
6 => X"0000_0000" & C_RNG3_BASEADDR,
7 => X"0000_0000" & C_RNG3_HIGHADDR
)
);
-- The chip enables are not decoded/used by the opb_master block but
-- the ipif still needs at least one value defined to avoid creating
-- VHDL errors.
CONSTANT C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE(0 TO C_NUM_ADDR_RNG-1) := (OTHERS => 1);
SIGNAL Bus2IP_Clk : std_logic; -- [IN]
SIGNAL Bus2IP_Reset : std_logic; -- [IN]
SIGNAL IP2Bus_Data : std_logic_vector(0 TO C_SIPIF_DWIDTH-1); -- [OUT]
SIGNAL IP2Bus_WrAck : std_logic; -- [OUT]
SIGNAL IP2Bus_RdAck : std_logic; -- [OUT]
SIGNAL IP2Bus_AddrAck : std_logic; -- [OUT]
SIGNAL IP2Bus_Error : std_logic; -- [OUT]
SIGNAL Bus2IP_Addr : std_logic_vector(0 TO C_SPLB_AWIDTH-1); -- [IN]
SIGNAL Bus2IP_Data : std_logic_vector(0 TO C_SIPIF_DWIDTH-1); -- [IN]
SIGNAL Bus2IP_RNW : std_logic; -- [IN]
SIGNAL Bus2IP_BE : std_logic_vector(0 TO C_SIPIF_DWIDTH/8-1); -- [IN]
SIGNAL Bus2IP_Burst : std_logic; -- [IN]
SIGNAL Bus2IP_BurstLength : std_logic_vector(0 TO log2(16 * (C_SPLB_DWIDTH/8))); -- [IN]
SIGNAL Bus2IP_WrReq : std_logic; -- [IN]
SIGNAL Bus2IP_RdReq : std_logic; -- [IN]
SIGNAL Bus2IP_CS : std_logic_vector(0 TO ((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1); -- [IN]
SIGNAL Bus2IP_RdCE : std_logic_vector(0 TO calc_num_ce(C_ARD_NUM_CE_ARRAY)-1); -- [IN]
SIGNAL Bus2IP_WrCE : std_logic_vector(0 TO calc_num_ce(C_ARD_NUM_CE_ARRAY)-1); -- [IN]
BEGIN
x_plbv46_slave_burst : ENTITY plbv46_slave_burst_v1_01_a.plbv46_slave_burst
GENERIC MAP (
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, -- [SLV64_ARRAY_TYPE]
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, -- [INTEGER_ARRAY_TYPE]
C_SPLB_P2P => C_SPLB_P2P, -- [integer RANGE 0 TO 1]
-- Optimize slave interface for a point to point connection
C_CACHLINE_ADDR_MODE => C_CACHELINE_ADDR_MODE, -- [integer range 0 to 1]
-- Selects the addressing mode to use for Cacheline Read operations.
C_WR_BUFFER_DEPTH => C_WR_BUFFER_DEPTH, -- [integer RANGE 0 TO 16]
-- The number of C_SIPIF_DWIDTH wide storage locations for the write buffer
-- Valid depths are 16, and 32. Setting to 0 removes the
-- buffer.
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH, -- [integer RANGE 0 TO 4]
-- The width of the Master ID bus
-- This is set to log2(C_SPLB_NUM_MASTERS)
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS, -- [integer RANGE 1 TO 16]
-- The number of Master Devices connected to the PLB bus
-- Research this to find out default value
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER, -- [integer RANGE 32 TO 128]
-- The dwidth (in bits) of the smallest master that will
-- access this ipif.
C_SPLB_AWIDTH => C_SPLB_AWIDTH, -- [integer RANGE 32 TO 36]
-- width of the PLB Address Bus (in bits)
C_SPLB_DWIDTH => C_SPLB_DWIDTH, -- [integer RANGE 32 TO 128]
-- Width of the PLB Data Bus (in bits)
C_SIPIF_DWIDTH => C_SIPIF_DWIDTH, -- [integer RANGE 32 TO 128]
-- Width of IPIF Data Bus (in bits)
C_FAMILY => C_FAMILY) -- [string]
PORT MAP (
-- System signals ---------------------------------------------------------
SPLB_Clk => SPLB_Clk, -- [IN std_logic]
SPLB_Rst => SPLB_Rst, -- [IN std_logic]
-- Bus Slave signals ------------------------------------------------------
PLB_ABus => PLB_ABus, -- [IN std_logic_vector(0 TO 31)]
PLB_UABus => PLB_UABus, -- [IN std_logic_vector(0 TO 31)]
PLB_PAValid => PLB_PAValid, -- [IN std_logic]
PLB_SAValid => PLB_SAValid, -- [IN std_logic]
PLB_rdPrim => PLB_rdPrim, -- [IN std_logic]
PLB_wrPrim => PLB_wrPrim, -- [IN std_logic]
PLB_masterID => PLB_masterID, -- [IN std_logic_vector(0 TO C_SPLB_MID_WIDTH-1)]
PLB_abort => PLB_abort, -- [IN std_logic]
PLB_busLock => PLB_busLock, -- [IN std_logic]
PLB_RNW => PLB_RNW, -- [IN std_logic]
PLB_BE => PLB_BE, -- [IN std_logic_vector(0 TO (C_SPLB_DWIDTH/8)-1)]
PLB_MSize => PLB_MSize, -- [IN std_logic_vector(0 TO 1)]
PLB_size => PLB_size, -- [IN std_logic_vector(0 TO 3)]
PLB_type => PLB_type, -- [IN std_logic_vector(0 TO 2)]
PLB_lockErr => PLB_lockErr, -- [IN std_logic]
PLB_wrDBus => PLB_wrDBus, -- [IN std_logic_vector(0 TO C_SPLB_DWIDTH-1)]
PLB_wrBurst => PLB_wrBurst, -- [IN std_logic]
PLB_rdBurst => PLB_rdBurst, -- [IN std_logic]
PLB_wrPendReq => PLB_wrPendReq, -- [IN std_logic]
PLB_rdPendReq => PLB_rdPendReq, -- [IN std_logic]
PLB_wrPendPri => PLB_wrPendPri, -- [IN std_logic_vector(0 TO 1)]
PLB_rdPendPri => PLB_rdPendPri, -- [IN std_logic_vector(0 TO 1)]
PLB_reqPri => PLB_reqPri, -- [IN std_logic_vector(0 TO 1)]
PLB_TAttribute => PLB_TAttribute, -- [IN std_logic_vector(0 TO 15)]
-- Slave Response Signals
Sl_addrAck => Sl_addrAck, -- [OUT std_logic]
Sl_SSize => Sl_SSize, -- [OUT std_logic_vector(0 TO 1)]
Sl_wait => Sl_wait, -- [OUT std_logic]
Sl_rearbitrate => Sl_rearbitrate, -- [OUT std_logic]
Sl_wrDAck => Sl_wrDAck, -- [OUT std_logic]
Sl_wrComp => Sl_wrComp, -- [OUT std_logic]
Sl_wrBTerm => Sl_wrBTerm, -- [OUT std_logic]
Sl_rdDBus => Sl_rdDBus, -- [OUT std_logic_vector(0 TO C_SPLB_DWIDTH-1)]
Sl_rdWdAddr => Sl_rdWdAddr, -- [OUT std_logic_vector(0 TO 3)]
Sl_rdDAck => Sl_rdDAck, -- [OUT std_logic]
Sl_rdComp => Sl_rdComp, -- [OUT std_logic]
Sl_rdBTerm => Sl_rdBTerm, -- [OUT std_logic]
Sl_MBusy => Sl_MBusy, -- [OUT std_logic_vector (0 TO C_SPLB_NUM_MASTERS-1)]
Sl_MWrErr => Sl_MWrErr, -- [OUT std_logic_vector (0 TO C_SPLB_NUM_MASTERS-1)]
Sl_MRdErr => Sl_MRdErr, -- [OUT std_logic_vector (0 TO C_SPLB_NUM_MASTERS-1)]
Sl_MIRQ => Sl_MIRQ, -- [OUT std_logic_vector (0 TO C_SPLB_NUM_MASTERS-1)]
-- IP Interconnect (IPIC) port signals -----------------------------------------
Bus2IP_Clk => Bus2IP_Clk, -- [OUT std_logic]
Bus2IP_Reset => Bus2IP_Reset, -- [OUT std_logic]
IP2Bus_Data => IP2Bus_Data, -- [IN std_logic_vector (0 TO C_SIPIF_DWIDTH-1)]
IP2Bus_WrAck => IP2Bus_WrAck, -- [IN std_logic]
IP2Bus_RdAck => IP2Bus_RdAck, -- [IN std_logic]
IP2Bus_AddrAck => IP2Bus_AddrAck, -- [IN std_logic]
IP2Bus_Error => IP2Bus_Error, -- [IN std_logic]
Bus2IP_Addr => Bus2IP_Addr, -- [OUT std_logic_vector (0 TO C_SPLB_AWIDTH-1)]
Bus2IP_Data => Bus2IP_Data, -- [OUT std_logic_vector (0 TO C_SIPIF_DWIDTH-1)]
Bus2IP_RNW => Bus2IP_RNW, -- [OUT std_logic]
Bus2IP_BE => Bus2IP_BE, -- [OUT std_logic_vector (0 TO (C_SIPIF_DWIDTH/8)-1)]
Bus2IP_Burst => Bus2IP_Burst, -- [OUT std_logic]
Bus2IP_BurstLength => Bus2IP_BurstLength, -- [OUT std_logic_vector (0 TO log2(C_SPLB_DWIDTH))]
Bus2IP_WrReq => Bus2IP_WrReq, -- [OUT std_logic]
Bus2IP_RdReq => Bus2IP_RdReq, -- [OUT std_logic]
Bus2IP_CS => Bus2IP_CS, -- [OUT std_logic_vector (0 TO ((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1)]
Bus2IP_RdCE => Bus2IP_RdCE, -- [OUT std_logic_vector (0 TO calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)]
Bus2IP_WrCE => Bus2IP_WrCE); -- [OUT std_logic_vector (0 TO calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)]
x_opb_master : ENTITY plbv46_opb_bridge_v1_01_a.opb_master
GENERIC MAP (
-- Base address and high address pairs.
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, -- [SLV64_ARRAY_TYPE]
-- This array spcifies the number of Chip Enables (CE) that is
-- required by the coresponding baseaddr pair.
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, -- [INTEGER_ARRAY_TYPE]
C_SPLB_AWIDTH => C_SPLB_AWIDTH, -- [integer RANGE 32 TO 36]
-- width of the PLB Address Bus (in bits)
C_SIPIF_DWIDTH => C_SIPIF_DWIDTH, -- [integer] IPIF/IPIC data width
C_SPLB_DWIDTH => C_SPLB_DWIDTH, -- [integer RANGE 32 TO 128]
C_BUS_CLOCK_PERIOD_RATIO => C_BUS_CLOCK_PERIOD_RATIO, -- [integer]
C_FAMILY => C_FAMILY) -- [string] Select the target architecture type
PORT MAP (
-- IP Interconnect (IPIC) Interface from PLBv46 IPIF
Bus2IP_Clk => Bus2IP_Clk, -- [IN std_logic]
Bus2IP_Reset => Bus2IP_Reset, -- [IN std_logic]
IP2Bus_Data => IP2Bus_Data, -- [OUT std_logic_vector(0 TO 32-1)]
IP2Bus_WrAck => IP2Bus_WrAck, -- [OUT std_logic]
IP2Bus_RdAck => IP2Bus_RdAck, -- [OUT std_logic]
IP2Bus_AddrAck => IP2Bus_AddrAck, -- [OUT std_logic]
IP2Bus_Error => IP2Bus_Error, -- [OUT std_logic]
Bus2IP_Addr => Bus2IP_Addr, -- [IN std_logic_vector(0 TO 32-1)]
Bus2IP_Data => Bus2IP_Data, -- [IN std_logic_vector(0 TO 32-1)]
Bus2IP_RNW => Bus2IP_RNW, -- [IN std_logic]
Bus2IP_BE => Bus2IP_BE, -- [IN std_logic_vector(0 TO 32/8-1)]
Bus2IP_Burst => Bus2IP_Burst, -- [IN std_logic]
Bus2IP_BurstLength => Bus2IP_BurstLength, -- [IN std_logic_vector(0 TO log2(C_SIPIF_DWIDTH))]
Bus2IP_WrReq => Bus2IP_WrReq, -- [IN std_logic]
Bus2IP_RdReq => Bus2IP_RdReq, -- [IN std_logic]
Bus2IP_CS => Bus2IP_CS, -- [IN std_logic_vector(0 TO ((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1)]
Bus2IP_RdCE => Bus2IP_RdCE, -- [IN std_logic_vector(0 TO calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)]
Bus2IP_WrCE => Bus2IP_WrCE, -- [IN std_logic_vector(0 TO calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)]
-- OPB Bus Master Interface
OPB_Clk => OPB_Clk, -- [IN std_logic]
OPB_Rst => OPB_Rst, -- [IN std_logic]
Mn_request => Mn_request, -- [OUT std_logic]
Mn_busLock => Mn_busLock, -- [OUT std_logic]
Mn_select => Mn_select, -- [OUT std_logic]
Mn_RNW => Mn_RNW, -- [OUT std_logic]
Mn_BE => Mn_BE, -- [OUT std_logic_vector(0 TO 32/8-1)]
Mn_seqAddr => Mn_seqAddr, -- [OUT std_logic]
Mn_DBus => Mn_DBus, -- [OUT std_logic_vector(0 TO 32-1)]
Mn_ABus => Mn_ABus, -- [OUT std_logic_vector(0 TO 31)]
OPB_MGrant => OPB_MGrant, -- [IN std_logic := '0']
OPB_xferAck => OPB_xferAck, -- [IN std_logic := '0']
OPB_errAck => OPB_errAck, -- [IN std_logic := '0']
OPB_retry => OPB_retry, -- [IN std_logic := '0']
OPB_timeout => OPB_timeout, -- [IN std_logic := '0']
OPB_DBus => OPB_DBus); -- [IN std_logic_vector(0 TO 32 - 1)]
END ARCHITECTURE syn; -- (architecture)
| bsd-3-clause | fc533cbf7d271fb4f171f42c983090f7 | 0.543577 | 3.48161 | false | false | false | false |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/axi_hthread_cores/proc_common_v3_00_a/hdl/vhdl/direct_path_cntr_ai.vhd | 2 | 11,361 |
--ENTITY_TAG
-------------------------------------------------------------------------------
-- $Id: direct_path_cntr_ai.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- direct_path_cntr_ai.vhd - entity/arch
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: direct_path_cntr_ai.vhd
--
-- Description: Direct-path counter with arbitrary increment.
--
-- This is an up counter with a combinatorial direct pass-
-- through mode. The passed-through value also serves as
-- the initial "loaded" value when the counter switches to
-- count mode. In pass-though mode, Dout <= Din.
--
-- The mode is controlled by two signals, Load_n and Cnt_en.
-- The counter is in direct pass-through mode any time Load_n
-- is true (low) and up to the first cycle where Cnt_en is
-- true after Load_n goes false. When Load_n = '1' (load
-- disabled) Dout increments by Delta each time Cnt_en is
-- true at the positive edge of Clk.
--
-- The implementation has a one-LUT delay from Din to Dout
-- (via the XORCY) in direct pass-through mode and the same
-- delay plus carry-chain propogation in count mode. There
-- is an additional LUT delay (added to the Din to Dout
-- delay) from the Load_n input or from the clock edge that
-- puts the counter into count mode.
-------------------------------------------------------------------------------
-- Structure: direct_path_cntr_ai.vhd
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 12/02/2003 -- First version derived from
-- direct_path_cntr.vhd
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity direct_path_cntr_ai is
generic (
C_WIDTH : natural := 8
);
port (
Clk : in std_logic;
Din : in std_logic_vector(0 to C_WIDTH-1);
Dout : out std_logic_vector(0 to C_WIDTH-1);
Load_n : in std_logic;
Cnt_en : in std_logic;
Delta : in std_logic_vector(0 to C_WIDTH-1)
);
end direct_path_cntr_ai;
library unisim;
use unisim.vcomponents.all;
architecture imp of direct_path_cntr_ai is
signal q_i,
lut_out,
q_i_ns : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
signal sel_cntr : std_logic;
signal sel_cntr_and_Load_n : std_logic; -- AND of sel_cntr and Load_n
signal mdelta : std_logic_vector(0 to Delta'length-1); -- "My delta"
-- Delta, adjusted to assure ascending range referenced from zero.
begin
mdelta <= Delta;
----------------------------------------------------------------------------
-- Load_n takes effect combinatorially, causing Dout to be directly driven
-- from Din when Load_n is asserted. When Load_n is not asserted, then the
-- first clocking of asserted Cnt_en switches modes so that Dout is driven
-- by the register value plus one. The value of Dout is clocked into the
-- register with each Cnt_en, thus realizing the counting behavior.
-- The combinatorial override of Load_n takes place in the LUT and covers
-- the cycle that it takes for the mode to recover (since the mode FF has a
-- synchronous reset). Use of an asynchronous reset is rejected as an
-- option to avoid the requirement that Load_n be generated glitch free.
----------------------------------------------------------------------------
I_MODE_SELECTION : process(Clk)
begin
if Clk'event and Clk='1' then
if Load_n = '0' then
sel_cntr <= '0';
elsif Cnt_en = '1' then
sel_cntr <= '1';
end if;
end if;
end process;
sel_cntr_and_Load_n <= sel_cntr and Load_n;
Dout <= q_i_ns;
cry(C_WIDTH) <= '0';
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
begin
------------------------------------------------------------------------
-- LUT output generation and MUXCY carry handling.
------------------------------------------------------------------------
DELTA_LUT_GEN: if j >= C_WIDTH-mdelta'length generate
signal gen_cry: std_logic;
begin
lut_out(j) <= q_i(j) xor mdelta(mdelta'length + j - C_WIDTH)
when (sel_cntr_and_Load_n)='1'
else
Din(j);
I_MULT_AND : MULT_AND
port map (
LO => gen_cry,
I1 => sel_cntr_and_Load_n,
I0 => q_i(j)
);
MUXCY_i1: MUXCY
port map (
DI => gen_cry,
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
--
--
NON_DELTA_LUT_GEN : if j < C_WIDTH-mdelta'length generate
begin
lut_out(j) <= q_i(j) when (sel_cntr_and_Load_n)='1' else Din(j);
MUXCY_i1: MUXCY
port map (
DI => '0',
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
------------------------------------------------------------------------
-- Apply the effect of carry in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lut_out(j),
CI => cry(j+1),
O => q_i_ns(j)
);
FDE_i1: FDE
port map (
Q => q_i(j),
C => Clk,
CE => Cnt_en,
D => q_i_ns(j)
);
end generate;
end imp;
| bsd-3-clause | 6ea40a70882e547166635420b5cea2c4 | 0.42954 | 4.950327 | false | false | false | false |
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