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stringlengths 32
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classes | has_no_keywords
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fupolarbear/THU-Class-CO-makecomputer
|
src/VGA/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_exdes.vhd
| 2 | 4,659 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END blk_mem_gen_v7_3_exdes;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_v7_3 IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : blk_mem_gen_v7_3
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
mit
|
50dc4a017748c47b11841459ceb8d968
| 0.567504 | 4.581121 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/qspi_occupancy_reg.vhd
| 1 | 10,090 |
-------------------------------------------------------------------------------
-- $Id: qspi_occupancy_reg.vhd
-------------------------------------------------------------------------------
-- qspi_occupancy_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_occupancy_reg.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI4 Bus.Defines logic for occupancy regist
-- -er.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_spi.
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Author: SK
-- ~~~~~~
-- - Redesigned version of axi_quad_spi.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_DBUS_WIDTH -- Width of the slave data bus
-- C_OCCUPANCY_NUM_BITS -- Number of bits in occupancy count
-- C_NUM_BITS_REG -- Width of SPI registers
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Reset -- Reset Signal
-- SLAVE ATTACHMENT INTERFACE
--===========================
-- Bus2IP_OCC_REG_RdCE -- Read CE for occupancy register
-- SPIXfer_done -- SPI transfer done flag
-- FIFO INTERFACE
-- IP2Reg_OCC_Data -- Occupancy data read from FIFO
-- IP2Bus_OCC_REG_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_occupancy_reg is
generic
(
C_OCCUPANCY_NUM_BITS: integer-- --Number of bits in occupancy count
);
port
(
-- Slave attachment ports
Bus2IP_OCC_REG_RdCE : in std_logic;
IP2Reg_OCC_Data : in std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
IP2Bus_OCC_REG_Data : out std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1))
);
end qspi_occupancy_reg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of qspi_occupancy_reg is
-------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
begin
-----
-- OCCUPANCY_REG_RD_GENERATE : Occupancy Register Read Generate
-------------------------------
OCCUPANCY_REG_RD_GENERATE: for j in 0 to C_OCCUPANCY_NUM_BITS-1 generate
begin
IP2Bus_OCC_REG_Data(j) <= IP2Reg_OCC_Data(C_OCCUPANCY_NUM_BITS-1-j) and
Bus2IP_OCC_REG_RdCE;
end generate OCCUPANCY_REG_RD_GENERATE;
end imp;
--------------------------------------------------------------------------------
|
mit
|
e92aea95d4920cf44e89d7f9f478284f
| 0.409415 | 5.236118 | false | false | false | false |
1995parham/FPGA-Homework
|
HW-3/src/p12/p12_t.vhd
| 1 | 948 |
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 26-04-2016
-- Module Name: p12_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity drawstring_t is
end entity;
architecture rtl of drawstring_t is
component drawstring
port (p1, p2 : in std_logic;
clk, reset : in std_logic;
led : out std_logic_vector (9 downto 1));
end component;
for all:drawstring use entity work.drawstring;
signal reset, p1, p2 : std_logic;
signal clk : std_logic := '0';
signal led : std_logic_vector (9 downto 1);
begin
reset <= '1', '0' after 50 ns;
clk <= not clk after 50 ns;
p1 <= '1' after 50 ns, '0' after 110 ns, '1' after 220 ns;
p2 <= '0', '1' after 55 ns, '0' after 65 ns;
m : drawstring port map (p1, p2, clk, reset, led);
end architecture;
|
gpl-3.0
|
62713794587473588b6bd19fd0137a96
| 0.542194 | 3.280277 | false | false | false | false |
bgottschall/reloc
|
zedboard_example/zedboard_example.srcs/sources_1/imports/sources_1/new/axis_lut_buffer.vhd
| 1 | 2,371 |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity axis_lut_buffer is
generic (
DATAWIDTH : integer := 64
);
port (
s_axis_data_tdata : in std_logic_vector(DATAWIDTH-1 downto 0);
s_axis_data_tkeep : in std_logic_vector(DATAWIDTH/8 - 1 downto 0);
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
s_axis_data_tvalid : in std_logic;
m_axis_data_tdata : out std_logic_vector(DATAWIDTH-1 downto 0);
m_axis_data_tkeep : out std_logic_vector(DATAWIDTH/8 - 1 downto 0);
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
m_axis_data_tvalid : out std_logic;
-- Global Clock Signal
clk : in std_logic
);
end axis_lut_buffer;
architecture rtl of axis_lut_buffer is
component LUT1
generic (
INIT: bit_vector(1 downto 0) := "10"
);
port (
O : out std_logic;
I0 : in std_logic
);
end component;
begin
LUTBUF_TDATA:
for I in 0 to DATAWIDTH-1 generate
LUTX:
LUT1
generic map ( INIT => "10" )
port map (
O => m_axis_data_tdata(I),
I0 => s_axis_data_tdata(I)
);
end generate LUTBUF_TDATA;
LUTBUF_TKEEP:
for I in 0 to (DATAWIDTH/8)-1 generate
LUTX:
LUT1
generic map ( INIT => "10" )
port map (
O => m_axis_data_tkeep(I),
I0 => s_axis_data_tkeep(I)
);
end generate LUTBUF_TKEEP;
LUTBUF_TVALID:
LUT1
generic map ( INIT => "10" )
port map (
O => m_axis_data_tvalid,
I0 => s_axis_data_tvalid
);
LUTBUF_TLAST:
LUT1
generic map ( INIT => "10" )
port map (
O => m_axis_data_tlast,
I0 => s_axis_data_tlast
);
LUTBUF_TREADY:
LUT1
generic map ( INIT => "10" )
port map (
O => s_axis_data_tready,
I0 => m_axis_data_tready
);
end rtl;
|
mit
|
21d11e12818bbbbd7637bb713da19527
| 0.47617 | 3.751582 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/VGA/ipcore_dir/char_mem/example_design/char_mem_prod.vhd
| 2 | 9,912 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: char_mem_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : char_mem.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 1
-- C_READ_WIDTH_A : 1
-- C_WRITE_DEPTH_A : 24320
-- C_READ_DEPTH_A : 24320
-- C_ADDRA_WIDTH : 15
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 1
-- C_READ_WIDTH_B : 1
-- C_WRITE_DEPTH_B : 24320
-- C_READ_DEPTH_B : 24320
-- C_ADDRB_WIDTH : 15
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY char_mem_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END char_mem_prod;
ARCHITECTURE xilinx OF char_mem_prod IS
COMPONENT char_mem_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : char_mem_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
mit
|
3084cae9b1981ab98d30c43edf7c6374
| 0.494552 | 3.822599 | false | false | false | false |
meaepeppe/FIR_ISA
|
VHDL/tb_FIR_filter.vhd
| 1 | 3,525 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE STD.textio.all;
ENTITY tb_FIR_filter IS
GENERIC(
N: integer := 8;
Nb: integer := 9;
N_sample: integer := 1000
);
END ENTITY;
ARCHITECTURE test OF tb_FIR_filter IS
TYPE vector_test IS ARRAY (N_sample-1 DOWNTO 0) OF INTEGER;
TYPE coeffs_array IS ARRAY (N DOWNTO 0) OF INTEGER;
TYPE sig_array IS ARRAY (N DOWNTO 0) OF SIGNED(Nb-1 DOWNTO 0);
FILE inputs: text;
FILE coeff_file: text;
SHARED VARIABLE input_samples: vector_test;
SIGNAL CLK, RST_n: STD_LOGIC;
SIGNAL VIN, VOUT: STD_LOGIC;
SIGNAL sample: SIGNED(Nb-1 DOWNTO 0);
SIGNAL DINconverted: STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
SIGNAL filter_out: STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0);
SIGNAL coeffs_std: std_logic_vector ((N+1)*Nb - 1 DOWNTO 0);
SIGNAL visual_coeffs_integer: coeffs_array;
SIGNAL regToDIN: STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
SIGNAL DOUTtoReg: STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0);
COMPONENT FIR_filter IS
GENERIC(
Ord: INTEGER := 8; --Filter Order
Nb: INTEGER := 9 --# of bits
);
PORT(
CLK, RST_n: IN STD_LOGIC;
VIN: IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
Coeffs: IN STD_LOGIC_VECTOR(((Ord+1)*Nb)-1 DOWNTO 0); --# of coeffs IS Ord+1
VOUT: OUT STD_LOGIC;
DOUT: OUT STD_LOGIC_VECTOR(2*Nb-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT Reg_n IS
GENERIC(Nb: INTEGER :=9);
PORT(
CLK, RST_n, EN: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
DINconverted <= std_logic_vector(sample);
DUT: FIR_filter
PORT MAP (CLK => CLK, RST_n => RST_n, VIN => VIN, DIN => regToDIN,
Coeffs => coeffs_std, VOUT => VOUT, DOUT => DOUTtoReg);
REG_IN: Reg_n
GENERIC MAP (Nb => Nb)
PORT MAP (CLK => CLK, RST_n => RST_n, EN => VIN, DIN => DINconverted, DOUT => regToDIN );
REG_OUT: Reg_n
GENERIC MAP (Nb => 2*Nb)
PORT MAP (CLK => CLK, RST_n => RST_n, EN => VIN, DIN => DOUTtoReg, DOUT => filter_out );
CLK_gen: PROCESS
BEGIN
CLK <= '0';
WAIT FOR 10 ns;
CLK <= '1';
WAIT FOR 10 ns;
END PROCESS;
test_input_read: PROCESS
VARIABLE iLine,cLine: LINE;
VARIABLE i,j: INTEGER := 0;
VARIABLE coeffs_integer: coeffs_array;
BEGIN
VIN <= '0';
RST_n <= '0';
file_open(inputs, "input_vectors.txt", READ_MODE);
WHILE (NOT ENDFILE(inputs)) LOOP
READLINE(inputs, iLine);
READ(iLine, input_samples(i));
i := i+1;
END LOOP;
file_close(inputs);
file_open(coeff_file, "coeffs.txt", READ_MODE);
WHILE (NOT ENDFILE(coeff_file)) LOOP
READLINE(coeff_file, cLine);
READ(cLine, coeffs_integer(j));
j := j+1;
END LOOP;
file_close(coeff_file);
visual_coeffs_integer <= coeffs_integer;
FOR i IN 0 TO N LOOP
coeffs_std((i+1)*Nb-1 DOWNTO i*Nb)<= std_logic_vector(to_signed(coeffs_integer(i),Nb));
END LOOP;
WAIT FOR 10 ns;
RST_n <= '1';
WAIT FOR 5 ns;
VIN <= '1';
WAIT;
END PROCESS;
test_results_write: PROCESS(CLK)
VARIABLE oLine: LINE;
VARIABLE i: INTEGER := 0;
FILE results: text is out "output_vectors.txt";
BEGIN
IF CLK'EVENT AND CLK = '1' THEN
sample <= to_signed(input_samples(i),sample'LENGTH);
i:= i+1;
END IF;
IF CLK'EVENT AND CLK = '1' AND VIN = '1' THEN
WRITE(oLine, to_integer(signed(filter_out)));
WRITELINE(results, oLine);
--IF i = N_sample-1 THEN
-- VIN <= '0';
--END IF;
END IF;
END PROCESS;
END test;
|
gpl-3.0
|
7c8348227ed1089f97ad4984c1ce59e8
| 0.622979 | 2.793185 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/CPU/FlashIO.vhd
| 1 | 4,879 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Fu Zuoyou.
--
-- Create Date: 20:30:32 11/30/2013
-- Design Name:
-- Module Name: FlashIO - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FlashIO is
port(
-- ×ÖģʽÏÂΪ22-1£¬×Ö½ÚģʽΪ22-0
addr: in std_logic_vector(22 downto 1);
datain: in std_logic_vector(15 downto 0);
dataout: out std_logic_vector(15 downto 0);
clk: in std_logic;
reset: in std_logic;
-- hard port connecting flash chip
flash_byte : out std_logic;
flash_vpen : out std_logic;
flash_ce : out std_logic;
flash_oe : out std_logic;
flash_we : out std_logic;
flash_rp : out std_logic;
flash_addr : out std_logic_vector(22 downto 1);
flash_data : inout std_logic_vector(15 downto 0);
-- signal to vhdl entity
ctl_read : in std_logic;
ctl_write : in std_logic;
ctl_erase : in std_logic
);
end FlashIO;
architecture Behavioral of FlashIO is
type flash_state is (
waiting,
write1, write2, write3, write4, write5,
read1, read2, read3, read4,
sr1, sr2, sr3, sr4, sr5,
erase1, erase2, erase3, erase4, erase5, erase6,
done
);
signal state : flash_state := waiting;
signal next_state : flash_state := waiting;
signal ctl_read_last, ctl_write_last, ctl_erase_last : std_logic;
begin
-- always set 1 for ×Öģʽ
flash_byte <= '1';
-- write protect, always 1
flash_vpen <= '1';
-- ce is enable, 0 is selected, 1 is not.
flash_ce <= '0';
-- 0 is reset, 1 is work, always 1
flash_rp <= '1';
process(clk, reset)
begin
if (reset = '0') then
dataout <= (others => '0');
flash_oe <= '1';
flash_we <= '1';
state <= waiting;
next_state <= waiting;
ctl_read_last <= ctl_read;
ctl_write_last <= ctl_write;
ctl_erase_last <= ctl_erase;
flash_data <= (others => 'Z');
elsif (clk'event and clk = '1') then
case state is
-- wait(initial)
when waiting =>
-- store last so you can change the value
-- to triggle the action when necessary
if (ctl_read /= ctl_read_last) then
flash_we <= '0';
state <= read1;
ctl_read_last <= ctl_read;
elsif (ctl_write /= ctl_write_last) then
flash_we <= '0';
state <= write1;
ctl_write_last <= ctl_write;
elsif (ctl_erase /= ctl_erase_last) then
flash_we <= '0';
dataout(0) <= '0';
state <= erase1;
ctl_erase_last <= ctl_erase;
end if;
-- write
when write1 =>
flash_data <= x"0040";
state <= write2;
when write2 =>
flash_we <= '1';
state <= write3;
when write3 =>
flash_we <= '0';
state <= write4;
when write4 =>
flash_addr <= addr;
flash_data <= datain;
state <= write5;
when write5 =>
flash_we <= '1';
state <= sr1;
next_state <= done;
-- small loop CM in write
-- write 6 is sr1
when sr1 =>
flash_we <= '0';
flash_data <= x"0070";
state <= sr2;
when sr2 =>
flash_we <= '1';
state <= sr3;
when sr3 =>
flash_data <= (others => 'Z');
state <= sr4;
when sr4 =>
flash_oe <= '0';
state <= sr5;
when sr5 =>
flash_oe <= '1';
if flash_data(7) = '0' then
state <= sr1;
else
state <= next_state;
end if;
-- read
when read1 =>
flash_data <= x"00FF";
state <= read2;
when read2 =>
flash_we <= '1';
state <= read3;
when read3 =>
flash_oe <= '0';
flash_addr <= addr;
flash_data <= (others => 'Z');
state <= read4;
when read4 =>
dataout <= flash_data;
state <= done;
-- erase
when erase1 =>
flash_data <= x"0020";
state <= erase2;
when erase2 =>
flash_we <= '1';
state <= erase3;
when erase3 =>
flash_we <= '0';
state <= erase4;
when erase4 =>
flash_data <= x"00D0";
flash_addr <= addr;
state <= erase5;
when erase5 =>
flash_we <= '1';
next_state <= erase6;
state <= sr1;
-- jump to sr1
-- return back from sr5
when erase6 =>
state <= done;
dataout(0) <= '1';
when others =>
flash_oe <= '1';
flash_we <= '1';
flash_data <= (others => 'Z');
state <= waiting;
end case;
end if;
end process;
end Behavioral;
|
mit
|
45e618bc89b6f56917c294a638a14b40
| 0.547858 | 3.002462 | false | false | false | false |
dsd-g05/lab5
|
g05_comp6.vhd
| 1 | 1,878 |
-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version"
-- CREATED "Thu Sep 24 15:43:45 2015"
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY work;
ENTITY g05_comp6 IS
PORT
(
A : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
AeqB : OUT STD_LOGIC
);
END g05_comp6;
ARCHITECTURE bdf_type OF g05_comp6 IS
SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_5 : STD_LOGIC;
BEGIN
SYNTHESIZED_WIRE_1 <= NOT(A(0) XOR B(0));
SYNTHESIZED_WIRE_2 <= NOT(A(1) XOR B(1));
SYNTHESIZED_WIRE_0 <= NOT(A(2) XOR B(2));
SYNTHESIZED_WIRE_3 <= NOT(A(3) XOR B(3));
SYNTHESIZED_WIRE_4 <= NOT(A(4) XOR B(4));
SYNTHESIZED_WIRE_5 <= NOT(A(5) XOR B(5));
AeqB <= SYNTHESIZED_WIRE_0 AND SYNTHESIZED_WIRE_1 AND SYNTHESIZED_WIRE_2 AND SYNTHESIZED_WIRE_3 AND SYNTHESIZED_WIRE_4 AND SYNTHESIZED_WIRE_5;
END bdf_type;
|
mit
|
d603ce2c7635f287cc75f2644a8b7192
| 0.724707 | 3.288967 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/ecc_gen.vhd
| 8 | 7,490 |
----------------------------------------------------------------------------------------------
--
-- Generated by X-HDL Verilog Translator - Version 4.0.0 Apr. 30, 2006
-- Wed Jun 17 2009 01:03:24
--
-- Input file : /home/samsonn/SandBox_LBranch_11.2/env/Databases/ip/src2/L/mig_v3_2/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ecc/ecc_gen.v
-- Component name : ecc_gen
-- Author :
-- Company :
--
-- Description :
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Generate the ecc code. Note that the synthesizer should
-- generate this as a static logic. Code in this block should
-- never run during simulation phase, or directly impact timing.
--
-- The code generated is a single correct, double detect code.
-- It is the classic Hamming code. Instead, the code is
-- optimized for minimal/balanced tree depth and size. See
-- Hsiao IBM Technial Journal 1970.
--
-- The code is returned as a single bit vector, h_rows. This was
-- the only way to "subroutinize" this with the restrictions of
-- disallowed include files and that matrices cannot be passed
-- in ports.
--
-- Factorial and the combos functions are defined. Combos
-- simply computes the number of combinations from the set
-- size and elements at a time.
--
-- The function next_combo computes the next combination in
-- lexicographical order given the "current" combination. Its
-- output is undefined if given the last combination in the
-- lexicographical order.
--
-- next_combo is insensitive to the number of elements in the
-- combinations.
--
-- An H transpose matrix is generated because that's the easiest
-- way to do it. The H transpose matrix is generated by taking
-- the one at a time combinations, then the 3 at a time, then
-- the 5 at a time. The number combinations used is equal to
-- the width of the code (CODE_WIDTH). The boundaries between
-- the 1, 3 and 5 groups are hardcoded in the for loop.
--
-- At the same time the h_rows vector is generated from the
-- H transpose matrix.
entity ecc_gen is
generic (
CODE_WIDTH : integer := 72;
ECC_WIDTH : integer := 8;
DATA_WIDTH : integer := 64
);
port (
-- Outputs
-- function next_combo
-- Given a combination, return the next combo in lexicographical
-- order. Scans from right to left. Assumes the first combination
-- is k ones all of the way to the left.
--
-- Upon entry, initialize seen0, trig1, and ones. "seen0" means
-- that a zero has been observed while scanning from right to left.
-- "trig1" means that a one have been observed _after_ seen0 is set.
-- "ones" counts the number of ones observed while scanning the input.
--
-- If trig1 is one, just copy the input bit to the output and increment
-- to the next bit. Otherwise set the the output bit to zero, if the
-- input is a one, increment ones. If the input bit is a one and seen0
-- is true, dump out the accumulated ones. Set seen0 to the complement
-- of the input bit. Note that seen0 is not used subsequent to trig1
-- getting set.
-- The stuff above leads to excessive XST execution times. For now, hardwire to 72/64 bit.
h_rows : out std_logic_vector(CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
end entity ecc_gen;
architecture trans of ecc_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of trans : architecture is "yes";
function factorial (ivar: integer) return integer is
variable tmp : integer;
begin
if (ivar = 1) then
return 1;
else
tmp := 1;
for i in ivar downto 2 loop
tmp := tmp * i;
end loop;
end if;
return tmp;
end function factorial;
function combos ( n, k: integer) return integer is
begin
return factorial(n)/(factorial(k)*factorial(n-k));
end function combos;
function next_combo (i: std_logic_vector) return std_logic_vector is
variable seen0: std_logic;
variable trig1: std_logic;
variable ones: std_logic_vector (ECC_WIDTH-1 downto 0);
variable tmp: std_logic_vector (ECC_WIDTH-1 downto 0);
variable tmp_index : integer;
begin
seen0 := '0';
trig1 := '0';
ones := (others => '0');
for index in ECC_WIDTH -1 downto 0 loop
tmp_index := ECC_WIDTH -1 - index;
if (trig1 = '1') then
tmp(tmp_index) := i(tmp_index);
else
tmp(tmp_index) := '0';
ones := ones + i(tmp_index);
if ((i(tmp_index) = '1') and (seen0 = '1')) then
trig1 := '1';
for dump_index in tmp_index-1 downto 0 loop
if (dump_index >= (tmp_index- conv_integer(ones)) ) then
tmp(dump_index) := '1';
end if;
end loop;
end if;
seen0 := not(i(tmp_index));
end if;
end loop;
return tmp;
end function next_combo;
constant COMBOS_3 : integer := combos(ECC_WIDTH, 3);
constant COMBOS_5 : integer := combos(ECC_WIDTH, 5);
type twoDarray is array (CODE_WIDTH -1 downto 0) of std_logic_vector (ECC_WIDTH-1 downto 0);
signal ht_matrix : twoDarray;
begin
columns: for n in CODE_WIDTH - 1 downto 0 generate
column0: if (n = 0) generate
ht_matrix(n) <= "111" & conv_std_logic_vector(0,ECC_WIDTH-3);
end generate;
column_combos3: if ((n = COMBOS_3) and ( n < DATA_WIDTH) ) generate
ht_matrix(n) <= "11111" & conv_std_logic_vector(0,ECC_WIDTH-5);
end generate;
column_combos5: if ((n = COMBOS_3 + COMBOS_5) and ( n < DATA_WIDTH) ) generate
ht_matrix(n) <= "1111111" & conv_std_logic_vector(0,ECC_WIDTH-7);
end generate;
column_datawidth: if (n = DATA_WIDTH) generate
ht_matrix(n) <= "1" & conv_std_logic_vector(0,ECC_WIDTH-1);
end generate;
column_gen: if ( (n /= 0 ) and ((n /= COMBOS_3) or (n > DATA_WIDTH)) and ((n /= COMBOS_3+COMBOS_5) or (n > DATA_WIDTH)) and (n /= DATA_WIDTH) ) generate
ht_matrix(n) <= next_combo(ht_matrix(n-1));
end generate;
out_assign: for s in ECC_WIDTH-1 downto 0 generate
h_rows(s*CODE_WIDTH+n) <= ht_matrix(n)(s);
end generate;
end generate;
--h_row0 <= "100000000100100011101101001101001000110100100010000110100100010000100000";
--h_row1 <= "010000001010010011011010101010100100101010010001000101010010001000010000";
--h_row2 <= "001000001001001010110110010110010010011001001000100011001001000100001000";
--h_row3 <= "000100000111000101110001110001110001000111000100010000111000100010000100";
--h_row4 <= "000010000000111100001111110000001111000000111100001000000111100001000010";
--h_row5 <= "000001001111111100000000001111111111000000000011111000000000011111000001";
--h_row6 <= "000000101111111100000000000000000000111111111111111000000000000000111111";
--h_row7 <= "000000011111111100000000000000000000000000000000000111111111111111111111";
--h_rows <= (h_row7 & h_row6 & h_row5 & h_row4 & h_row3 & h_row2 & h_row1 & h_row0);
end architecture trans;
|
mit
|
d765d83e6d9219ed8f85cd5762344cbf
| 0.621495 | 3.868802 | false | false | false | false |
6769/VHDL
|
Lab_2_part2/clock_second.vhd
| 1 | 642 |
--Intertime clock
library ieee;
use ieee.numeric_bit.all;
entity clock_second is
port(clk:in bit ;
second:buffer bit);
end entity clock_second;
architecture Distribution of clock_second is
signal counter_for_osc_signal:unsigned(31 downto 0);
begin
process
begin
wait until clk'event and clk='1';
if counter_for_osc_signal < 50*1000*1000
then
counter_for_osc_signal<=counter_for_osc_signal+1;
else counter_for_osc_signal<=(others=>'0');
second<=not second;
end if;
end process;
-- second<='1' when counter_for_osc_signal> 25*1000*1000 --High_percent_of_counter
-- else '0' ;
end architecture Distribution;
|
gpl-2.0
|
e1f51b134c595c47e65a079cb2099630
| 0.714953 | 3.07177 | false | false | false | false |
6769/VHDL
|
Lab_5/__FromTextBook/Counter.vhd
| 1 | 504 |
entity Counter is
port(Clk, Roll: in bit;
Sum: out integer range 2 to 12);
end Counter;
architecture Count of Counter is
signal Cnt1, Cnt2: integer range 1 to 6 := 1;
begin
process(Clk)
begin
if Clk = '1' then
if Roll = '1' then
if Cnt1 = 6 then Cnt1 <= 1; else Cnt1 <= Cnt1 + 1; end if;
if Cnt1 = 6 then
if Cnt2 = 6 then Cnt2 <= 1; else Cnt2 <= Cnt2 + 1; end if;
end if;
end if;
end if;
end process;
Sum <= Cnt1 + Cnt2;
end Count;
|
gpl-2.0
|
dfe8b644d09940b20cb616851ab99564
| 0.569444 | 3.15 | false | false | false | false |
sbates130272/capi-textswap
|
rtl/bits_set.vhd
| 1 | 6,120 |
--------------------------------------------------------------------------------
--
-- Copyright 2015 PMC-Sierra, Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License"); you
-- may not use this file except in compliance with the License. You may
-- obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0 Unless required by
-- applicable law or agreed to in writing, software distributed under the
-- License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-- CONDITIONS OF ANY KIND, either express or implied. See the License for
-- the specific language governing permissions and limitations under the
-- License.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company: PMC-Sierra, Inc.
-- Engineer: Logan Gunthorpe
--
-- Description
-- -----------
-- This block determines the index of the first bit set of a given
-- word. Additionally, it has two flags indicating whether there
-- is a single bit set or multiple bits set. The latency of this
-- block must be zero.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library capi;
use capi.misc.all;
entity bits_set is
generic (
width : positive := 32;
step : positive := 8);
port (
d : in std_logic_vector(width-1 downto 0);
frst : out unsigned(log2_ceil(width)-1 downto 0);
one_set : out std_logic;
mult_set : out std_logic
);
end entity bits_set;
architecture main of bits_set is
type frst_arr is array (natural range <>) of unsigned(log2_ceil(step)-1 downto 0);
signal step_frst : frst_arr(0 to width / step - 1);
signal step_one : std_logic_vector(0 to width / step - 1);
signal step_mult : std_logic_vector(0 to width / step - 1);
--Lookup table:
-- Lowest Two Bits:
-- 00 - No bits Set
-- 01 - One bit Set
-- 11 - Multiple bits Set
-- Highest bits: Index of the first set bit.
type lut_t is array (0 to 2**step-1) of unsigned(log2_ceil(step)+2-1 downto 0);
constant lut : lut_t := lut_t'(
"00000", "00001", "00101", "00011", "01001", "00011", "00111", "00011",
"01101", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10001", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10101", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10011", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"11001", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10011", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10011", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"11101", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10011", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10011", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"11011", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10011", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"10011", "00011", "00111", "00011", "01011", "00011", "00111", "00011",
"01111", "00011", "00111", "00011", "01011", "00011", "00111", "00011");
begin
STEPS: for i in step_frst'range generate
step_frst(i) <= lut(to_integer(unsigned(d((i+1)*8-1 downto i*8))))
(step_frst(i)'high+2 downto 2);
step_one(i) <= lut(to_integer(unsigned(d((i+1)*8-1 downto i*8))))(0);
step_mult(i) <= lut(to_integer(unsigned(d((i+1)*8-1 downto i*8))))(1);
end generate STEPS;
-- purpose: Sum the counts and find the first bit
process (step_frst, step_one, step_mult)
variable first_one : std_logic;
begin
one_set <= '0';
mult_set <= '0';
first_one := '0';
for i in step_one'range loop
if step_one(i) = '1' then
one_set <= '1';
if first_one = '1' then
mult_set <= '1';
end if;
first_one := '1';
end if;
if step_mult(i) = '1' then
mult_set <= '1';
end if;
end loop;
frst <= (others=>'0');
for i in step_frst'reverse_range loop
if step_one(i) = '1' or step_mult(i) = '1' then
frst <= to_unsigned(i, log2_ceil(width/step)) & step_frst(i);
end if;
end loop;
end process;
end architecture main;
|
apache-2.0
|
cb53339858b6d542663de3c35cd9f2c2
| 0.514869 | 3.529412 | false | false | false | false |
frankvanbever/MIPS_processor
|
testbenches/sign_extend_tb.vhd
| 1 | 1,274 |
-- Frank Vanbever 03/06/2013
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sign_extend_tb is
end sign_extend_tb;
architecture behavioral of sign_extend_tb is
-- declaration of UUT
component sign_extend
port (
instruction_in : in std_logic_vector(15 downto 0);
instruction_out : out std_logic_vector(31 downto 0)
);
end component;
signal tb_inst_in : std_logic_vector(15 downto 0);
signal tb_inst_out : std_logic_vector(31 downto 0);
signal clk : std_logic;
constant clk_period : time := 10 ns;
begin
uut: sign_extend port map (
instruction_in => tb_inst_in,
instruction_out => tb_inst_out
);
-- Clock process definitions
clk_process : process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc : process
begin
wait for 100 ns;
-- test 1: test with sign bit 1
tb_inst_in <= X"FFFF";
wait for clk_period;
assert tb_inst_out = X"FFFFFFFF" report "error at test 1";
-- test 2: test with sign bit 0
wait for clk_period;
tb_inst_in <= X"0000";
wait for clk_period;
assert tb_inst_out = X"00000000" report "error at test 2";
wait;
end process;
end;
|
mit
|
ae9fb2d8c8acc402d826f1dd20f57dbf
| 0.656986 | 2.997647 | false | true | false | false |
6769/VHDL
|
Lab_2_part2/clock/counter741.vhd
| 1 | 501 |
--741
library ieee;
use ieee.numeric_bit.all;
entity counter741 is
port(clk :in bit;
second:out bit;
Qout:out unsigned(31 downto 0));
end entity counter741;
architecture neibu of counter741 is
signal Q:unsigned(31 downto 0);
--signal Nullth:unsigned(31 downto 0);
begin
Qout<=Q;
second<='0' when Q>25
else '1';
process(clk)
begin
if clk'event and clk='1' and Q<50 then
Q<=Q+1;
elsif clk'event and clk='1' then
Q<=(others=>'0');
end if;
end process;
end architecture neibu;
|
gpl-2.0
|
3db9f114a6b9ef9550fdb7b635d42647
| 0.686627 | 2.767956 | false | false | false | false |
julioamerico/prj_crc_ip
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@a@h@b_@i@p/_primary.vhd
| 3 | 10,169 |
library verilog;
use verilog.vl_types.all;
entity MSS_AHB_IP is
generic(
ACT_CONFIG : integer := 0;
ACT_FCLK : integer := 0;
ACT_DIE : string := "";
ACT_PKG : string := "";
VECTFILE : string := "test.vec"
);
port(
MSSHADDR : out vl_logic_vector(19 downto 0);
MSSHWDATA : out vl_logic_vector(31 downto 0);
MSSHTRANS1 : out vl_logic;
MSSHSIZE : out vl_logic_vector(1 downto 0);
MSSHLOCK : out vl_logic;
MSSHWRITE : out vl_logic;
MSSHRDATA : in vl_logic_vector(31 downto 0);
MSSHREADY : in vl_logic;
MSSHRESP : in vl_logic;
FABHADDR : in vl_logic_vector(31 downto 0);
FABHWDATA : in vl_logic_vector(31 downto 0);
FABHTRANS1 : in vl_logic;
FABHSIZE : in vl_logic_vector(1 downto 0);
FABHMASTLOCK : in vl_logic;
FABHWRITE : in vl_logic;
FABHSEL : in vl_logic;
FABHREADY : in vl_logic;
FABHRDATA : out vl_logic_vector(31 downto 0);
FABHREADYOUT : out vl_logic;
FABHRESP : out vl_logic;
SYNCCLKFDBK : in vl_logic;
CALIBOUT : out vl_logic;
CALIBIN : in vl_logic;
FABINT : in vl_logic;
MSSINT : out vl_logic_vector(7 downto 0);
WDINT : out vl_logic;
F2MRESETn : in vl_logic;
DMAREADY : in vl_logic_vector(1 downto 0);
RXEV : in vl_logic;
VRON : in vl_logic;
M2FRESETn : out vl_logic;
DEEPSLEEP : out vl_logic;
SLEEP : out vl_logic;
TXEV : out vl_logic;
UART0CTSn : in vl_logic;
UART0DSRn : in vl_logic;
UART0RIn : in vl_logic;
UART0DCDn : in vl_logic;
UART0RTSn : out vl_logic;
UART0DTRn : out vl_logic;
UART1CTSn : in vl_logic;
UART1DSRn : in vl_logic;
UART1RIn : in vl_logic;
UART1DCDn : in vl_logic;
UART1RTSn : out vl_logic;
UART1DTRn : out vl_logic;
I2C0SMBUSNI : in vl_logic;
I2C0SMBALERTNI : in vl_logic;
I2C0BCLK : in vl_logic;
I2C0SMBUSNO : out vl_logic;
I2C0SMBALERTNO : out vl_logic;
I2C1SMBUSNI : in vl_logic;
I2C1SMBALERTNI : in vl_logic;
I2C1BCLK : in vl_logic;
I2C1SMBUSNO : out vl_logic;
I2C1SMBALERTNO : out vl_logic;
MACM2FTXD : out vl_logic_vector(1 downto 0);
MACF2MRXD : in vl_logic_vector(1 downto 0);
MACM2FTXEN : out vl_logic;
MACF2MCRSDV : in vl_logic;
MACF2MRXER : in vl_logic;
MACF2MMDI : in vl_logic;
MACM2FMDO : out vl_logic;
MACM2FMDEN : out vl_logic;
MACM2FMDC : out vl_logic;
FABSDD0D : in vl_logic;
FABSDD1D : in vl_logic;
FABSDD2D : in vl_logic;
FABSDD0CLK : in vl_logic;
FABSDD1CLK : in vl_logic;
FABSDD2CLK : in vl_logic;
FABACETRIG : in vl_logic;
ACEFLAGS : out vl_logic_vector(31 downto 0);
CMP0 : out vl_logic;
CMP1 : out vl_logic;
CMP2 : out vl_logic;
CMP3 : out vl_logic;
CMP4 : out vl_logic;
CMP5 : out vl_logic;
CMP6 : out vl_logic;
CMP7 : out vl_logic;
CMP8 : out vl_logic;
CMP9 : out vl_logic;
CMP10 : out vl_logic;
CMP11 : out vl_logic;
LVTTL0EN : in vl_logic;
LVTTL1EN : in vl_logic;
LVTTL2EN : in vl_logic;
LVTTL3EN : in vl_logic;
LVTTL4EN : in vl_logic;
LVTTL5EN : in vl_logic;
LVTTL6EN : in vl_logic;
LVTTL7EN : in vl_logic;
LVTTL8EN : in vl_logic;
LVTTL9EN : in vl_logic;
LVTTL10EN : in vl_logic;
LVTTL11EN : in vl_logic;
LVTTL0 : out vl_logic;
LVTTL1 : out vl_logic;
LVTTL2 : out vl_logic;
LVTTL3 : out vl_logic;
LVTTL4 : out vl_logic;
LVTTL5 : out vl_logic;
LVTTL6 : out vl_logic;
LVTTL7 : out vl_logic;
LVTTL8 : out vl_logic;
LVTTL9 : out vl_logic;
LVTTL10 : out vl_logic;
LVTTL11 : out vl_logic;
PUFABn : out vl_logic;
VCC15GOOD : out vl_logic;
VCC33GOOD : out vl_logic;
FCLK : in vl_logic;
MACCLKCCC : in vl_logic;
RCOSC : in vl_logic;
MACCLK : in vl_logic;
PLLLOCK : in vl_logic;
MSSRESETn : in vl_logic;
GPI : in vl_logic_vector(31 downto 0);
GPO : out vl_logic_vector(31 downto 0);
GPOE : out vl_logic_vector(31 downto 0);
SPI0DO : out vl_logic;
SPI0DOE : out vl_logic;
SPI0DI : in vl_logic;
SPI0CLKI : in vl_logic;
SPI0CLKO : out vl_logic;
SPI0MODE : out vl_logic;
SPI0SSI : in vl_logic;
SPI0SSO : out vl_logic_vector(7 downto 0);
UART0TXD : out vl_logic;
UART0RXD : in vl_logic;
I2C0SDAI : in vl_logic;
I2C0SDAO : out vl_logic;
I2C0SCLI : in vl_logic;
I2C0SCLO : out vl_logic;
SPI1DO : out vl_logic;
SPI1DOE : out vl_logic;
SPI1DI : in vl_logic;
SPI1CLKI : in vl_logic;
SPI1CLKO : out vl_logic;
SPI1MODE : out vl_logic;
SPI1SSI : in vl_logic;
SPI1SSO : out vl_logic_vector(7 downto 0);
UART1TXD : out vl_logic;
UART1RXD : in vl_logic;
I2C1SDAI : in vl_logic;
I2C1SDAO : out vl_logic;
I2C1SCLI : in vl_logic;
I2C1SCLO : out vl_logic;
MACTXD : out vl_logic_vector(1 downto 0);
MACRXD : in vl_logic_vector(1 downto 0);
MACTXEN : out vl_logic;
MACCRSDV : in vl_logic;
MACRXER : in vl_logic;
MACMDI : in vl_logic;
MACMDO : out vl_logic;
MACMDEN : out vl_logic;
MACMDC : out vl_logic;
EMCCLK : out vl_logic;
EMCCLKRTN : in vl_logic;
EMCRDB : in vl_logic_vector(15 downto 0);
EMCAB : out vl_logic_vector(25 downto 0);
EMCWDB : out vl_logic_vector(15 downto 0);
EMCRWn : out vl_logic;
EMCCS0n : out vl_logic;
EMCCS1n : out vl_logic;
EMCOEN0n : out vl_logic;
EMCOEN1n : out vl_logic;
EMCBYTEN : out vl_logic_vector(1 downto 0);
EMCDBOE : out vl_logic;
ADC0 : in vl_logic;
ADC1 : in vl_logic;
ADC2 : in vl_logic;
ADC3 : in vl_logic;
ADC4 : in vl_logic;
ADC5 : in vl_logic;
ADC6 : in vl_logic;
ADC7 : in vl_logic;
ADC8 : in vl_logic;
ADC9 : in vl_logic;
ADC10 : in vl_logic;
ADC11 : in vl_logic;
SDD0 : out vl_logic;
SDD1 : out vl_logic;
SDD2 : out vl_logic;
ABPS0 : in vl_logic;
ABPS1 : in vl_logic;
ABPS2 : in vl_logic;
ABPS3 : in vl_logic;
ABPS4 : in vl_logic;
ABPS5 : in vl_logic;
ABPS6 : in vl_logic;
ABPS7 : in vl_logic;
ABPS8 : in vl_logic;
ABPS9 : in vl_logic;
ABPS10 : in vl_logic;
ABPS11 : in vl_logic;
TM0 : in vl_logic;
TM1 : in vl_logic;
TM2 : in vl_logic;
TM3 : in vl_logic;
TM4 : in vl_logic;
TM5 : in vl_logic;
CM0 : in vl_logic;
CM1 : in vl_logic;
CM2 : in vl_logic;
CM3 : in vl_logic;
CM4 : in vl_logic;
CM5 : in vl_logic;
GNDTM0 : in vl_logic;
GNDTM1 : in vl_logic;
GNDTM2 : in vl_logic;
VAREF0 : in vl_logic;
VAREF1 : in vl_logic;
VAREF2 : in vl_logic;
VAREFOUT : out vl_logic;
GNDVAREF : in vl_logic;
PUn : in vl_logic
);
end MSS_AHB_IP;
|
gpl-3.0
|
a3413a1ef5fa9763cf7121e656952d71
| 0.400334 | 3.673772 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/VHDL_StratixIV_OrphanedGland/top/tb/top_tb_pc.vhd
| 4 | 5,894 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_tb_pc is
end entity top_tb_pc;
architecture top_tb_pc_behav of top_tb_pc is
alias slv is std_logic_vector;
subtype slv512 is slv(511 downto 0);
subtype slv256 is slv(255 downto 0);
subtype slv32 is slv(31 downto 0);
subtype word is unsigned(31 downto 0);
component pll is
port (
inclk0 : in std_logic := '0';
c0 : out std_logic
);
end component pll;
component sha256_pc is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_pc;
component sha256_qp is
generic (
default_h : boolean := true
);
port (
clk : in std_logic;
reset : in std_logic;
msg_in : in std_logic_vector(511 downto 0);
h_in : in std_logic_vector(255 downto 0) := (others => '0');
digest : out std_logic_vector(255 downto 0)
);
end component sha256_qp;
constant NUM_CORES : natural := 4;
-- SHA256_SEL = 0 => sha256_pc, uses precalculated H + K + W technique
-- SHA256_SEL = 1 => sha256_qp, uses quasi-pipelining technique
constant SHA256_SEL : natural := 0;
constant tclk_40 : time := 25 ns;
type data_array is array(NUM_CORES-1 downto 0) of slv512;
type digest_array is array(NUM_CORES-1 downto 0) of slv256;
type nonce_array is array(NUM_CORES-1 downto 0) of word;
signal OSC_CLK : std_logic := '0';
signal clk : std_logic;
signal reset : std_logic := '0';
signal data_1 : data_array;
signal digest_1 : digest_array;
signal data_2 : data_array;
signal digest_2 : digest_array;
signal data_in : slv256;
signal h_in : slv256;
signal q_data_in : slv256 := (others => '0');
signal q_h_in : slv256 := (others => '0');
signal q_nonce : nonce_array;
signal q_golden_nonce : slv32 := (others => '0');
begin
reset <= '1','0' after 2.5 * tclk_40;
data_in <= X"00000000000000000000000080000000000000002194261a9395e64dbed17115";
h_in <= X"228ea4732a3c9ba860c009cda7252b9161a5e75ec8c582a5f106abb3af41f790";
clk_gen: process is
begin
OSC_CLK <= not OSC_CLK;
wait for tclk_40/2;
end process clk_gen;
pll_inst: pll
port map (
inclk0 => OSC_CLK,
c0 => clk
);
sha256_gen: for i in NUM_CORES-1 downto 0 generate
data_1(i) <= X"000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000" & slv(q_nonce(i)) & q_data_in(95 downto 0);
data_2(i) <= X"0000010000000000000000000000000000000000000000000000000080000000" & digest_1(i);
sha256_pc_gen: if SHA256_SEL = 0 generate
sha256_1: sha256_pc
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_pc
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_pc_gen;
sha256_qp_gen: if SHA256_SEL = 1 generate
sha256_1: sha256_qp
generic map (
default_h => false
)
port map (
clk => clk,
reset => reset,
msg_in => data_1(i),
h_in => q_h_in,
digest => digest_1(i)
);
sha256_2: sha256_qp
generic map (
default_h => true
)
port map (
clk => clk,
reset => reset,
msg_in => data_2(i),
digest => digest_2(i)
);
end generate sha256_qp_gen;
end generate sha256_gen;
registers: process(clk, reset)
begin
if reset = '1' then
q_data_in <= (others => '0');
q_h_in <= (others => '0');
q_nonce(0) <= X"0e33337a" - 256;
for i in NUM_CORES-1 downto 1 loop
q_nonce(i) <= q_nonce(0) + i;
end loop;
q_golden_nonce <= (others => '0');
elsif rising_edge(clk) then
q_data_in <= data_in;
q_h_in <= h_in;
for i in NUM_CORES-1 downto 0 loop
q_nonce(i) <= q_nonce(0) + i + NUM_CORES;
if digest_2(i)(255 downto 224) = X"00000000" then
if SHA256_SEL = 0 then
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*131);
else
q_golden_nonce <= slv(q_nonce(i) - NUM_CORES*134);
end if;
end if;
end loop;
end if;
end process registers;
end architecture top_tb_pc_behav;
|
gpl-3.0
|
415736adad65aeb78a534f1ae5bebaf6
| 0.460299 | 3.852288 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/rd_chnl.vhd
| 5 | 207,533 |
-------------------------------------------------------------------------------
-- rd_chnl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: rd_chnl.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller read channel interfaces. Controls all
-- handshaking and data flow on the AXI read address (AR)
-- and read data (R) channels.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/3/2011 v1.03a
-- ~~~~~~
-- Edits for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/14/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter.
-- Similar edits as wr_chnl on Hsiao ECC code.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update for usage of ecc_gen.vhd module directly from MIG.
-- Clean-up XST warnings.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Found issue with ECC decoding on read path. Remove MSB '0' usage
-- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits.
-- Modify read data signal used in single bit error correction.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Move all MIG functions to package body.
-- ^^^^^^
-- JLJ 3/2/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Clean-up unused signal, narrow_addr_inc.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 4/21/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- Add defaults to araddr_pipe_sel & axi_arready_int when in single port mode.
-- Remove use of IF_IS_AXI4 constant.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 5/26/2011 v1.03a
-- ~~~~~~
-- With CR # 609695, update else clause for narrow_burst_cnt_ld to
-- remove simulation warnings when axi_byte_div_curr_arsize = zero.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.wrap_brst;
use work.ua_narrow;
use work.checkbit_handler;
use work.checkbit_handler_64;
use work.correct_one_bit;
use work.correct_one_bit_64;
use work.ecc_gen;
use work.parity;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity rd_chnl is
generic (
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_AXI_ID_WIDTH : integer := 4;
-- AXI ID vector width
C_S_AXI_SUPPORTS_NARROW : integer := 1;
-- Support for narrow burst operations
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to "AXI4LITE" to optimize out burst transaction support
C_SINGLE_PORT_BRAM : integer := 0;
-- Enable single port usage of BRAM
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0 -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
);
port (
-- AXI Global Signals
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI Read Address Channel Signals (AR)
AXI_ARID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_ARADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Specifies the number of data transfers in the burst
-- "0000 0000" 1 data transfer
-- "0000 0001" 2 data transfers
-- ...
-- "1111 1111" 256 data transfers
AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Specifies the max number of data bytes to transfer in each data beat
-- "000" 1 byte to transfer
-- "001" 2 bytes to transfer
-- "010" 3 bytes to transfer
-- ...
AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Specifies burst type
-- "00" FIXED = Fixed burst address (handled as INCR)
-- "01" INCR = Increment burst address
-- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary
-- "11" Reserved (not checked)
AXI_ARLOCK : in std_logic;
AXI_ARCACHE : in std_logic_vector(3 downto 0);
AXI_ARPROT : in std_logic_vector(2 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
AXI_RID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_RDATA : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0);
AXI_RRESP : out std_logic_vector(1 downto 0);
AXI_RLAST : out std_logic;
AXI_RVALID : out std_logic;
AXI_RREADY : in std_logic;
-- ECC Register Interface Signals
Enable_ECC : in std_logic;
BRAM_Addr_En : out std_logic;
CE_Failing_We : out std_logic := '0';
Sl_CE : out std_logic := '0';
Sl_UE : out std_logic := '0';
-- Single Port Arbitration Signals
Arb2AR_Active : in std_logic;
AR2Arb_Active_Clr : out std_logic := '0';
Sng_BRAM_Addr_Ld_En : out std_logic := '0';
Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
Sng_BRAM_Addr_Inc : out std_logic := '0';
Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
-- BRAM Read Port Interface Signals
BRAM_En : out std_logic;
BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0);
BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
);
end entity rd_chnl;
-------------------------------------------------------------------------------
architecture implementation of rd_chnl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Set constants for ARLEN equal to a count of one or two beats.
constant AXI_ARLEN_ONE : std_logic_vector(7 downto 0) := (others => '0');
constant AXI_ARLEN_TWO : std_logic_vector(7 downto 0) := "00000001";
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
-- Move to full_axi module
-- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8);
-- Not used
-- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
-- Determine maximum size for narrow burst length counter
-- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits
-- resulting in a count 3 downto 0 => so minimum counter width = 2 bits.
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits
-- resulting in a count 31 downto 0 => so minimum counter width = 5 bits.
constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8);
constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- Max length burst count AXI4 specification
constant C_MAX_BRST_CNT : integer := 256;
constant C_BRST_CNT_SIZE : integer := log2 (C_MAX_BRST_CNT);
-- When the burst count = 0
constant C_BRST_CNT_ZERO : std_logic_vector(C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- Burst count = 1
constant C_BRST_CNT_ONE : std_logic_vector(7 downto 0) := "00000001";
-- Burst count = 2
constant C_BRST_CNT_TWO : std_logic_vector(7 downto 0) := "00000010";
-- Read data mux select constants (for signal rddata_mux_sel)
-- '0' selects BRAM
-- '1' selects read skid buffer
constant C_RDDATA_MUX_BRAM : std_logic := '0';
constant C_RDDATA_MUX_SKID_BUF : std_logic := '1';
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
-- AXI Burst Types
-- AXI Spec 4.4
constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10";
constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01";
constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00";
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Internal ECC data width size.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH);
-- For use with ECC functions (to use LUT6 components or let synthesis infer the optimal implementation).
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
constant C_USE_LUT6 : boolean := TRUE;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_ADDR_SM_TYPE is ( IDLE,
LD_ARADDR
);
signal rd_addr_sm_cs, rd_addr_sm_ns : RD_ADDR_SM_TYPE;
signal ar_active_set : std_logic := '0';
signal ar_active_set_i : std_logic := '0';
signal ar_active_clr : std_logic := '0';
signal ar_active : std_logic := '0';
signal ar_active_d1 : std_logic := '0';
signal ar_active_re : std_logic := '0';
signal axi_araddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal curr_araddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
signal araddr_pipe_ld : std_logic := '0';
signal araddr_pipe_ld_i : std_logic := '0';
signal araddr_pipe_sel : std_logic := '0';
-- '0' indicates mux select from AXI
-- '1' indicates mux select from AR Addr Register
signal axi_araddr_full : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal axi_early_arready_int : std_logic := '0';
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_d2 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
signal axi_aresetn_re_reg : std_logic := '0';
signal no_ar_ack_cmb : std_logic := '0';
signal no_ar_ack : std_logic := '0';
signal pend_rd_op_cmb : std_logic := '0';
signal pend_rd_op : std_logic := '0';
signal axi_arid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_arsize_pipe : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arsize_pipe_4byte : std_logic := '0';
signal axi_arsize_pipe_8byte : std_logic := '0';
signal axi_arsize_pipe_16byte : std_logic := '0';
signal axi_arsize_pipe_32byte : std_logic := '0';
-- v1.03a
signal axi_arsize_pipe_max : std_logic := '0';
signal curr_arsize : std_logic_vector (2 downto 0) := (others => '0');
signal curr_arsize_reg : std_logic_vector (2 downto 0) := (others => '0');
signal axi_arlen_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arlen_pipe_1_or_2 : std_logic := '0';
signal curr_arlen : std_logic_vector(7 downto 0) := (others => '0');
signal curr_arlen_reg : std_logic_vector(7 downto 0) := (others => '0');
signal axi_arburst_pipe : std_logic_vector(1 downto 0) := (others => '0');
signal axi_arburst_pipe_fixed : std_logic := '0';
signal curr_arburst : std_logic_vector(1 downto 0) := (others => '0');
signal curr_wrap_burst : std_logic := '0';
signal curr_wrap_burst_reg : std_logic := '0';
signal max_wrap_burst : std_logic := '0';
signal curr_incr_burst : std_logic := '0';
signal curr_fixed_burst : std_logic := '0';
signal curr_fixed_burst_reg : std_logic := '0';
-- BRAM Address Counter
signal bram_addr_ld_en : std_logic := '0';
signal bram_addr_ld_en_i : std_logic := '0';
signal bram_addr_ld_en_mod : std_logic := '0';
signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_inc : std_logic := '0';
signal bram_addr_inc_mod : std_logic := '0';
signal bram_addr_inc_wrap_mod : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Read Data Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type RD_DATA_SM_TYPE is ( IDLE,
SNG_ADDR,
SEC_ADDR,
FULL_PIPE,
FULL_THROTTLE,
LAST_ADDR,
LAST_THROTTLE,
LAST_DATA,
LAST_DATA_AR_PEND
);
signal rd_data_sm_cs, rd_data_sm_ns : RD_DATA_SM_TYPE;
signal rd_adv_buf : std_logic := '0';
signal axi_rd_burst : std_logic := '0';
signal axi_rd_burst_two : std_logic := '0';
signal act_rd_burst : std_logic := '0';
signal act_rd_burst_set : std_logic := '0';
signal act_rd_burst_clr : std_logic := '0';
signal act_rd_burst_two : std_logic := '0';
-- Rd Data Buffer/Register
signal rd_skid_buf_ld_cmb : std_logic := '0';
signal rd_skid_buf_ld_reg : std_logic := '0';
signal rd_skid_buf_ld : std_logic := '0';
signal rd_skid_buf_ld_imm : std_logic := '0';
signal rd_skid_buf : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal rddata_mux_sel_cmb : std_logic := '0';
signal rddata_mux_sel : std_logic := '0';
signal axi_rdata_en : std_logic := '0';
signal axi_rdata_mux : std_logic_vector (C_AXI_DATA_WIDTH+8*C_ECC-1 downto 0) := (others => '0');
-- Read Burst Counter
signal brst_cnt_max : std_logic := '0';
signal brst_cnt_max_d1 : std_logic := '0';
signal brst_cnt_max_re : std_logic := '0';
signal end_brst_rd_clr_cmb : std_logic := '0';
signal end_brst_rd_clr : std_logic := '0';
signal end_brst_rd : std_logic := '0';
signal brst_zero : std_logic := '0';
signal brst_one : std_logic := '0';
signal brst_cnt_ld : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
signal brst_cnt_rst : std_logic := '0';
signal brst_cnt_ld_en : std_logic := '0';
signal brst_cnt_ld_en_i : std_logic := '0';
signal brst_cnt_dec : std_logic := '0';
signal brst_cnt : std_logic_vector (C_BRST_CNT_SIZE-1 downto 0) := (others => '0');
-- AXI Read Response Signals
signal axi_rid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp_full : std_logic := '0';
signal axi_rid_temp_full_d1 : std_logic := '0';
signal axi_rid_temp_full_fe : std_logic := '0';
signal axi_rid_temp2 : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rid_temp2_full : std_logic := '0';
signal axi_b2b_rid_adv : std_logic := '0';
signal axi_rid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_rresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_rvalid_clr_ok : std_logic := '0';
signal axi_rvalid_set_cmb : std_logic := '0';
signal axi_rvalid_set : std_logic := '0';
signal axi_rvalid_int : std_logic := '0';
signal axi_rlast_int : std_logic := '0';
signal axi_rlast_set : std_logic := '0';
-- Internal BRAM Signals
signal bram_en_cmb : std_logic := '0';
signal bram_en_int : std_logic := '0';
signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
-- Narrow Burst Signals
signal curr_narrow_burst_cmb : std_logic := '0';
signal curr_narrow_burst : std_logic := '0';
signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_addr_rst : std_logic := '0';
signal narrow_addr_ld_en : std_logic := '0';
signal narrow_addr_dec : std_logic := '0';
signal narrow_bram_addr_inc : std_logic := '0';
signal narrow_bram_addr_inc_d1 : std_logic := '0';
signal narrow_bram_addr_inc_re : std_logic := '0';
signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal curr_ua_narrow_wrap : std_logic := '0';
signal curr_ua_narrow_incr : std_logic := '0';
signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- State machine type declarations
type RLAST_SM_TYPE is ( IDLE,
W8_THROTTLE,
W8_2ND_LAST_DATA,
W8_LAST_DATA,
-- W8_LAST_DATA_B2,
W8_THROTTLE_B2
);
signal rlast_sm_cs, rlast_sm_ns : RLAST_SM_TYPE;
signal last_bram_addr : std_logic := '0';
signal set_last_bram_addr : std_logic := '0';
signal alast_bram_addr : std_logic := '0';
signal rd_b2b_elgible : std_logic := '0';
signal rd_b2b_elgible_no_thr_check : std_logic := '0';
signal throttle_last_data : std_logic := '0';
signal disable_b2b_brst_cmb : std_logic := '0';
signal disable_b2b_brst : std_logic := '0';
signal axi_b2b_brst_cmb : std_logic := '0';
signal axi_b2b_brst : std_logic := '0';
signal do_cmplt_burst_cmb : std_logic := '0';
signal do_cmplt_burst : std_logic := '0';
signal do_cmplt_burst_clr : std_logic := '0';
-------------------------------------------------------------------------------
-- ECC Signals
-------------------------------------------------------------------------------
signal UnCorrectedRdData : std_logic_vector (0 to C_AXI_DATA_WIDTH-1) := (others => '0');
-- Move vector from core ECC module to use in AXI RDATA register output
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to ECC @ 32-bit data width
signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to ECC @ 64-bit data width
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Sl_UE_i : std_logic := '0';
signal UE_Q : std_logic := '0';
-- v1.03a
-- Hsiao ECC
signal syndrome_r : std_logic_vector (C_INT_ECC_WIDTH - 1 downto 0) := (others => '0');
constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- AXI Read Address Channel Output Signals
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_DUAL
-- Purpose: Generate AXI_ARREADY when in dual port mode.
---------------------------------------------------------------------------
GEN_ARREADY_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-- Ensure ARREADY only gets asserted early when acknowledge recognized
-- on AXI read data channel.
AXI_ARREADY <= axi_arready_int or (axi_early_arready_int and rd_adv_buf);
end generate GEN_ARREADY_DUAL;
---------------------------------------------------------------------------
-- Generate: GEN_ARREADY_SNG
-- Purpose: Generate AXI_ARREADY when in single port mode.
---------------------------------------------------------------------------
GEN_ARREADY_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- ARREADY generated by sng_port_arb module
AXI_ARREADY <= '0';
axi_arready_int <= '0';
end generate GEN_ARREADY_SNG;
---------------------------------------------------------------------------
-- AXI Read Data Channel Output Signals
---------------------------------------------------------------------------
-- UE flag is detected is same clock cycle that read data is presented on
-- the AXI bus. Must drive SLVERR combinatorially to align with corrupted
-- detected data word.
AXI_RRESP <= RESP_SLVERR when (C_ECC = 1 and Sl_UE_i = '1') else axi_rresp_int;
AXI_RVALID <= axi_rvalid_int;
AXI_RID <= axi_rid_int;
AXI_RLAST <= axi_rlast_int;
---------------------------------------------------------------------------
--
-- *** AXI Read Address Channel Interface ***
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_SNG
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- Unused AW pipeline (set default values)
araddr_pipe_ld <= '0';
axi_araddr_pipe <= AXI_ARADDR;
axi_arid_pipe <= AXI_ARID;
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
axi_arlen_pipe_1_or_2 <= '0';
axi_arburst_pipe_fixed <= '0';
axi_araddr_full <= '0';
end generate GEN_AR_PIPE_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_AR_PIPE_DUAL
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AR_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-----------------------------------------------------------------------
-- AXI Read Address Buffer/Register
-- (mimic behavior of address pipeline for AXI_ARID)
-----------------------------------------------------------------------
GEN_ARADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate
begin
REG_ARADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
axi_araddr_pipe (i) <= AXI_ARADDR (i);
else
axi_araddr_pipe (i) <= axi_araddr_pipe (i);
end if;
end if;
end process REG_ARADDR;
end generate GEN_ARADDR;
-------------------------------------------------------------------
-- Register ARID
-- No reset condition to save resources/timing
-------------------------------------------------------------------
REG_ARID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arid_pipe <= AXI_ARID;
else
axi_arid_pipe <= axi_arid_pipe;
end if;
end if;
end process REG_ARID;
---------------------------------------------------------------------------
-- In parallel to ARADDR pipeline and ARID
-- Use same control signals to capture AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST.
-- Register AXI_ARSIZE, AXI_ARLEN & AXI_ARBURST
-- No reset condition to save resources/timing
REG_ARCTRL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (araddr_pipe_ld = '1') then
axi_arsize_pipe <= AXI_ARSIZE;
axi_arlen_pipe <= AXI_ARLEN;
axi_arburst_pipe <= AXI_ARBURST;
else
axi_arsize_pipe <= axi_arsize_pipe;
axi_arlen_pipe <= axi_arlen_pipe;
axi_arburst_pipe <= axi_arburst_pipe;
end if;
end if;
end process REG_ARCTRL;
---------------------------------------------------------------------------
-- Create signals that indicate value of AXI_ARLEN in pipeline stage
-- Used to decode length of burst when BRAM address can be loaded early
-- when pipeline is full.
--
-- Add early decode of ARBURST in pipeline.
-- Copy logic from WR_CHNL module (similar logic).
-- Add early decode of ARSIZE = 4 bytes in pipeline.
REG_ARLEN_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- No reset condition to save resources/timing
if (araddr_pipe_ld = '1') then
-- Create merge to decode ARLEN of ONE or TWO
if (AXI_ARLEN = AXI_ARLEN_ONE) or (AXI_ARLEN = AXI_ARLEN_TWO) then
axi_arlen_pipe_1_or_2 <= '1';
else
axi_arlen_pipe_1_or_2 <= '0';
end if;
-- Early decode on value in pipeline of ARBURST
if (AXI_ARBURST = C_AXI_BURST_FIXED) then
axi_arburst_pipe_fixed <= '1';
else
axi_arburst_pipe_fixed <= '0';
end if;
else
axi_arlen_pipe_1_or_2 <= axi_arlen_pipe_1_or_2;
axi_arburst_pipe_fixed <= axi_arburst_pipe_fixed;
end if;
end if;
end process REG_ARLEN_PIPE;
---------------------------------------------------------------------------
-- Create full flag for ARADDR pipeline
-- Set when read address register is loaded.
-- Cleared when read address stored in register is loaded into BRAM
-- address counter.
REG_RDADDR_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- (bram_addr_ld_en = '1' and araddr_pipe_sel = '1') then
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and araddr_pipe_ld = '0') then
axi_araddr_full <= '0';
elsif (araddr_pipe_ld = '1') then
axi_araddr_full <= '1';
else
axi_araddr_full <= axi_araddr_full;
end if;
end if;
end process REG_RDADDR_FULL;
---------------------------------------------------------------------------
end generate GEN_AR_PIPE_DUAL;
---------------------------------------------------------------------------
-- v1.03a
-- Add early decode of ARSIZE = max size in pipeline based on AXI data
-- bus width (use constant, C_AXI_SIZE_MAX)
REG_ARSIZE_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arsize_pipe_max <= '0';
elsif (araddr_pipe_ld = '1') then
-- Early decode of ARSIZE in pipeline equal to max # of bytes
-- based on AXI data bus width
if (AXI_ARSIZE = C_AXI_SIZE_MAX) then
axi_arsize_pipe_max <= '1';
else
axi_arsize_pipe_max <= '0';
end if;
else
axi_arsize_pipe_max <= axi_arsize_pipe_max;
end if;
end if;
end process REG_ARSIZE_PIPE;
---------------------------------------------------------------------------
-- Generate: GE_ARREADY
-- Purpose: ARREADY is only created here when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_ARREADY: if (C_SINGLE_PORT_BRAM = 0) generate
begin
----------------------------------------------------------------------------
-- AXI_ARREADY Output Register
-- Description: Keep AXI_ARREADY output asserted until ARADDR pipeline
-- is full. When a full condition is reached, negate
-- ARREADY as another AR address can not be accepted.
-- Add condition to keep ARReady asserted if loading current
--- ARADDR pipeline value into the BRAM address counter.
-- Indicated by assertion of bram_addr_ld_en & araddr_pipe_sel.
--
----------------------------------------------------------------------------
REG_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_arready_int <= '0';
-- Detect end of S_AXI_AResetn to assert AWREADY and accept
-- new AWADDR values
elsif (axi_aresetn_re_reg = '1') or
-- Add condition for early ARREADY to keep pipeline full
(bram_addr_ld_en = '1' and araddr_pipe_sel = '1' and axi_early_arready_int = '0') then
axi_arready_int <= '1';
-- Add conditional check if ARREADY is asserted (with ARVALID) (one clock cycle later)
-- when the address pipeline is full.
elsif (araddr_pipe_ld = '1') or
(AXI_ARVALID = '1' and axi_arready_int = '1' and axi_araddr_full = '1') then
axi_arready_int <= '0';
else
axi_arready_int <= axi_arready_int;
end if;
end if;
end process REG_ARREADY;
----------------------------------------------------------------------------
REG_EARLY_ARREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_early_arready_int <= '0';
-- Pending ARADDR and ARREADY is not yet asserted to accept
-- operation (due to ARADDR being full)
elsif (AXI_ARVALID = '1' and axi_arready_int = '0' and
axi_araddr_full = '1') and
(alast_bram_addr = '1') and
-- Add check for elgible back-to-back BRAM load
(rd_b2b_elgible = '1') then
axi_early_arready_int <= '1';
else
axi_early_arready_int <= '0';
end if;
end if;
end process REG_EARLY_ARREADY;
---------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert ARREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
axi_aresetn_d2 <= axi_aresetn_d1;
axi_aresetn_re_reg <= axi_aresetn_re;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
----------------------------------------------------------------------------
end generate GEN_ARREADY;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL_ADDR_CNT
-- Purpose: Instantiate BRAM address counter unique for wr_chnl logic
-- only when controller configured in dual port mode.
---------------------------------------------------------------------------
GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- Replace I_ADDR_CNT module usage of pf_counter in proc_common library.
-- Only need to use lower 12-bits of address due to max AXI burst size
-- Since AXI guarantees bursts do not cross 4KB boundary, the counting part
-- of I_ADDR_CNT can be reduced to max 4KB.
--
-- No reset on bram_addr_int.
-- Increment ONLY.
REG_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (bram_addr_ld_en_mod = '1') then
bram_addr_int <= bram_addr_ld;
elsif (bram_addr_inc_mod = '1') then
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process REG_ADDR_CNT;
---------------------------------------------------------------------------
-- Set defaults to shared address counter
-- Only used in single port configurations
Sng_BRAM_Addr_Ld_En <= '0';
Sng_BRAM_Addr_Ld <= (others => '0');
Sng_BRAM_Addr_Inc <= '0';
end generate GEN_DUAL_ADDR_CNT;
---------------------------------------------------------------------------
-- Generate: GEN_SNG_ADDR_CNT
-- Purpose: When configured in single port BRAM mode, address counter
-- is shared with rd_chnl module. Assign output signals here
-- to counter instantiation at full_axi module level.
---------------------------------------------------------------------------
GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod;
Sng_BRAM_Addr_Ld <= bram_addr_ld;
Sng_BRAM_Addr_Inc <= bram_addr_inc_mod;
bram_addr_int <= Sng_BRAM_Addr;
end generate GEN_SNG_ADDR_CNT;
---------------------------------------------------------------------------
-- BRAM address load mux.
-- Either load BRAM counter directly from AXI bus or from stored registered value
-- Use registered signal to indicate current operation is a WRAP burst
--
-- Match bram_addr_ld to what asserts bram_addr_ld_en_mod
-- Include bram_addr_inc_mod when asserted to use bram_addr_ld_wrap value
-- (otherwise use pipelined or AXI bus value to load BRAM address counter)
bram_addr_ld <= bram_addr_ld_wrap when (max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1') else
axi_araddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
---------------------------------------------------------------------------
-- On wrap burst max loads (simultaneous BRAM address increment is asserted).
-- Ensure that load has higher priority over increment.
-- Use registered signal to indicate current operation is a WRAP burst
bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or
(max_wrap_burst = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1'))
else '0';
-- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal
-- logic. No need for the check if the current operation is NOT a fixed AND a wrap
-- burst. The transfer will be one or the other.
-- Found issue when narrow FIXED length burst is incorrectly
-- incrementing BRAM address counter
bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0')
else narrow_bram_addr_inc_re;
----------------------------------------------------------------------------
-- Narrow bursting
--
-- Handle read burst addressing on narrow burst operations
-- Intercept BRAM address increment flag, bram_addr_inc and only
-- increment address when the number of BRAM reads match the width of the
-- AXI data bus.
-- For a 32-bit BRAM, byte burst will increment the BRAM address
-- after four reads from BRAM.
-- For a 256-bit BRAM, a byte burst will increment the BRAM address
-- after 32 reads from BRAM.
-- Based on current operation being a narrow burst, hold off BRAM
-- address increment until narrow burst fits BRAM data width.
-- For non narrow burst operations, use bram_addr_inc from data SM.
--
-- Add in check that burst type is not FIXED, curr_fixed_burst_reg
-- bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
-- narrow_bram_addr_inc_re;
--
--
-- Replace w/ below generate statements based on supporting narrow transfers or not.
-- Create generate statement around the signal assignment for bram_addr_inc_mod.
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_INC_MOD_W_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are supported in design instantiation.
---------------------------------------------------------------------------
GEN_BRAM_INC_MOD_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0') else
(narrow_bram_addr_inc_re and not (curr_fixed_burst_reg));
end generate GEN_BRAM_INC_MOD_W_NARROW;
---------------------------------------------------------------------------
-- Generate: GEN_WO_NARROW
-- Purpose: Assign signal, bram_addr_inc_mod when narrow transfers
-- are not supported in the design instantiation.
-- Drive default values for narrow counter and logic when
-- narrow operation support is disabled.
---------------------------------------------------------------------------
GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
-- Found issue when narrow FIXED length burst is incorrectly incrementing BRAM address counter
bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg);
narrow_addr_rst <= '0';
narrow_burst_cnt_ld_mod <= (others => '0');
narrow_addr_dec <= '0';
narrow_addr_ld_en <= '0';
narrow_bram_addr_inc <= '0';
narrow_bram_addr_inc_d1 <= '0';
narrow_bram_addr_inc_re <= '0';
narrow_addr_int <= (others => '0');
curr_narrow_burst <= '0';
end generate GEN_WO_NARROW;
---------------------------------------------------------------------------
--
-- Only instantiate NARROW_CNT and supporting logic when narrow transfers
-- are supported and utilized by masters in the AXI system.
-- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this.
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT
-- Purpose: Instantiate narrow counter and logic when narrow
-- operation support is enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- Generate seperate smaller counter for narrow burst operations
-- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library.
--
-- Counter size is adjusted based on size of data burst.
--
-- For example, 32-bit data width BRAM, minimum narrow width
-- burst is 8 bits resulting in a count 3 downto 0. So the
-- minimum counter width = 2 bits.
--
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst
-- is 8 bits resulting in a count 31 downto 0. So the
-- minimum counter width = 5 bits.
--
-- Size of counter = C_NARROW_BURST_CNT_LEN
--
---------------------------------------------------------------------------
REG_NARROW_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (narrow_addr_rst = '1') then
narrow_addr_int <= (others => '0');
-- Load enable
elsif (narrow_addr_ld_en = '1') then
narrow_addr_int <= narrow_burst_cnt_ld_mod;
-- Decrement ONLY (no increment functionality)
elsif (narrow_addr_dec = '1') then
narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <=
std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1);
end if;
end if;
end process REG_NARROW_CNT;
---------------------------------------------------------------------------
narrow_addr_rst <= not (S_AXI_AResetn);
-- Modify narrow burst count load value based on
-- unalignment of AXI address value
narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else
narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else
narrow_burst_cnt_ld_reg;
narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0';
narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re;
narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and
(curr_narrow_burst = '1')
-- Ensure that narrow address counter doesn't
-- flag max or get loaded to
-- reset narrow counter until AXI read data
-- bus has acknowledged current
-- data on the AXI bus. Use rd_adv_buf signal
-- to indicate the non throttle
-- condition on the AXI bus.
and (bram_addr_inc = '1')
else '0';
----------------------------------------------------------------------------
-- Detect rising edge of narrow_bram_addr_inc
REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_bram_addr_inc_d1 <= '0';
else
narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc;
end if;
end if;
end process REG_NARROW_BRAM_ADDR_INC;
narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and
(narrow_bram_addr_inc_d1 = '0')
else '0';
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT;
----------------------------------------------------------------------------
-- Specify current ARSIZE signal
-- Address pipeline MUX
curr_arsize <= axi_arsize_pipe when (araddr_pipe_sel = '1') else AXI_ARSIZE;
REG_ARSIZE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_arsize_reg <= (others => '0');
-- Register curr_arsize when bram_addr_ld_en = '1'
elsif (bram_addr_ld_en = '1') then
curr_arsize_reg <= curr_arsize;
else
curr_arsize_reg <= curr_arsize_reg;
end if;
end if;
end process REG_ARSIZE;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_EN
-- Purpose: Only instantiate logic to determine if current burst
-- is a narrow burst when narrow bursting logic is supported.
---------------------------------------------------------------------------
GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-----------------------------------------------------------------------
-- Determine "narrow" burst transfers
-- Compare the ARSIZE to the BRAM data width
-----------------------------------------------------------------------
-- v1.03a
-- Detect if current burst operation is of size /= to the full
-- AXI data bus width. If not, then the current operation is a
-- "narrow" burst.
curr_narrow_burst_cmb <= '1' when (curr_arsize /= C_AXI_SIZE_MAX) else '0';
---------------------------------------------------------------------------
-- Register flag indicating the current operation
-- is a narrow read burst
NARROW_BURST_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Need to reset this flag at end of narrow burst operation
-- Ensure if curr_narrow_burst got set during previous transaction, axi_rlast_set
-- doesn't clear the flag (add check for pend_rd_op negated).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_set = '1' and pend_rd_op = '0' and bram_addr_ld_en = '0') then
curr_narrow_burst <= '0';
-- Add check for burst operation using ARLEN value
-- Ensure that narrow burst flag does not get set during FIXED burst types
elsif (bram_addr_ld_en = '1') and (curr_arlen /= AXI_ARLEN_ONE) and
(curr_fixed_burst = '0') then
curr_narrow_burst <= curr_narrow_burst_cmb;
end if;
end if;
end process NARROW_BURST_REG;
end generate GEN_NARROW_EN;
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT_LD
-- Purpose: Only instantiate logic to determine narrow burst counter
-- load value when narrow bursts are enabled.
---------------------------------------------------------------------------
GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
signal curr_arsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal axi_byte_div_curr_arsize : integer := 1;
begin
-- v1.03a
-- Create narrow burst counter load value based on current operation
-- "narrow" data width (indicated by value of AWSIZE).
curr_arsize_unsigned <= unsigned (curr_arsize);
-- XST does not support divisors that are not constants and powers of 2.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- narrow_burst_cnt_ld <= std_logic_vector (
-- to_unsigned (
-- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_arsize_unsigned))) ) - 1,
-- C_NARROW_BURST_CNT_LEN));
-- -- With this new process and subsequent signal assignment:
-- DIV_AWSIZE: process (curr_arsize_unsigned)
-- begin
--
-- case (to_integer (curr_arsize_unsigned)) is
-- when 0 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
-- when 1 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
-- when 2 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
-- when 3 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
-- when 4 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
-- when 5 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
-- when 6 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
-- when 7 => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
-- --coverage off
-- when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
-- --coverage on
-- end case;
--
-- end process DIV_AWSIZE;
-- w/ CR # 609695
-- With this new process and subsequent signal assignment:
DIV_AWSIZE: process (curr_arsize_unsigned)
begin
case (curr_arsize_unsigned) is
when "000" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES / 128;
--coverage off
when others => axi_byte_div_curr_arsize <= C_AXI_DATA_WIDTH_BYTES;
--coverage on
end case;
end process DIV_AWSIZE;
-- v1.03a
-- Replace with new signal assignment.
-- For synthesis to support only divisors that are constant and powers of two.
-- Updated else clause for simulation warnings w/ CR # 609695
narrow_burst_cnt_ld <= std_logic_vector (
to_unsigned (
(axi_byte_div_curr_arsize) - 1, C_NARROW_BURST_CNT_LEN))
when (axi_byte_div_curr_arsize > 0)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
-- Register narrow burst count load indicator
REG_NAR_BRST_CNT_LD: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_burst_cnt_ld_reg <= (others => '0');
elsif (bram_addr_ld_en = '1') then
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld;
else
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg;
end if;
end if;
end process REG_NAR_BRST_CNT_LD;
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT_LD;
----------------------------------------------------------------------------
-- Handling for WRAP burst types
--
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Boundary is reached based on ARSIZE and ARLEN.
--
-- Goal is to minimize muxing on initial load of counter value.
-- On WRAP burst types, detect when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value set to '0'.
----------------------------------------------------------------------------
-- Detect valid WRAP burst types
curr_wrap_burst <= '1' when (curr_arburst = C_AXI_BURST_WRAP) else '0';
curr_incr_burst <= '1' when (curr_arburst = C_AXI_BURST_INCR) else '0';
curr_fixed_burst <= '1' when (curr_arburst = C_AXI_BURST_FIXED) else '0';
----------------------------------------------------------------------------
-- Register curr_wrap_burst & curr_fixed_burst signals when BRAM
-- address counter is initially loaded
REG_CURR_BRST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_wrap_burst_reg <= '0';
curr_fixed_burst_reg <= '0';
elsif (bram_addr_ld_en = '1') then
curr_wrap_burst_reg <= curr_wrap_burst;
curr_fixed_burst_reg <= curr_fixed_burst;
else
curr_wrap_burst_reg <= curr_wrap_burst_reg;
curr_fixed_burst_reg <= curr_fixed_burst_reg;
end if;
end if;
end process REG_CURR_BRST;
---------------------------------------------------------------------------
-- Instance: I_WRAP_BRST
--
-- Description:
--
-- Instantiate WRAP_BRST module
-- Logic to generate the wrap around value to load into the BRAM address
-- counter on WRAP burst transactions.
-- WRAP value is based on current ARLEN, ARSIZE (for narrows) and
-- data width of BRAM module.
--
---------------------------------------------------------------------------
I_WRAP_BRST : entity work.wrap_brst
generic map (
C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
curr_axlen => curr_arlen ,
curr_axsize => curr_arsize ,
curr_narrow_burst => curr_narrow_burst ,
narrow_bram_addr_inc_re => narrow_bram_addr_inc_re ,
bram_addr_ld_en => bram_addr_ld_en ,
bram_addr_ld => bram_addr_ld ,
bram_addr_int => bram_addr_int ,
bram_addr_ld_wrap => bram_addr_ld_wrap ,
max_wrap_burst_mod => max_wrap_burst
);
----------------------------------------------------------------------------
-- Specify current ARBURST signal
-- Input address pipeline MUX
curr_arburst <= axi_arburst_pipe when (araddr_pipe_sel = '1') else AXI_ARBURST;
----------------------------------------------------------------------------
-- Specify current AWBURST signal
-- Input address pipeline MUX
curr_arlen <= axi_arlen_pipe when (araddr_pipe_sel = '1') else AXI_ARLEN;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_UA_NARROW
-- Purpose: Only instantiate logic for burst narrow WRAP operations when
-- AXI bus protocol is not set for AXI-LITE and narrow
-- burst operations are supported.
--
---------------------------------------------------------------------------
GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
--
-- New logic to detect unaligned address on a narrow WRAP burst transaction.
-- If this condition is met, then the narrow burst counter will be
-- initially loaded with an offset value corresponding to the unalignment
-- in the ARADDR value.
--
--
-- Create a sub module for all logic to determine the narrow burst counter
-- offset value on unaligned WRAP burst operations.
--
-- Module generates the following signals:
--
-- => curr_ua_narrow_wrap, to indicate the current
-- operation is an unaligned narrow WRAP burst.
--
-- => curr_ua_narrow_incr, to load narrow burst counter
-- for unaligned INCR burst operations.
--
-- => ua_narrow_load, narrow counter load value.
-- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0)
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Instance: I_UA_NARROW
--
-- Description:
--
-- Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- Logic is customized for each C_AXI_DATA_WIDTH.
--
---------------------------------------------------------------------------
I_UA_NARROW : entity work.ua_narrow
generic map (
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN
)
port map (
curr_wrap_burst => curr_wrap_burst , -- in
curr_incr_burst => curr_incr_burst , -- in
bram_addr_ld_en => bram_addr_ld_en , -- in
curr_axlen => curr_arlen , -- in
curr_axsize => curr_arsize , -- in
curr_axaddr_lsb => curr_araddr_lsb , -- in
curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out
curr_ua_narrow_incr => curr_ua_narrow_incr , -- out
ua_narrow_load => ua_narrow_load -- out
);
-- Use in all C_AXI_DATA_WIDTH generate statements
-- Only probe least significant BRAM address bits
-- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0.
curr_araddr_lsb <= axi_araddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0)
when (araddr_pipe_sel = '1') else
AXI_ARADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0);
end generate GEN_UA_NARROW;
----------------------------------------------------------------------------
--
-- New logic to detect if pending operation in ARADDR pipeline is
-- elgible for back-to-back no "bubble" performance. And BRAM address
-- counter can be loaded upon last BRAM address presented for the current
-- operation.
-- This condition exists when the ARADDR pipeline is full and the pending
-- operation is a burst >= length of two data beats.
-- And not a FIXED burst type (must be INCR or WRAP type).
-- The DATA SM handles detecting a throttle condition and will void
-- the capability to be a back-to-back in performance transaction.
--
-- Add check if new operation is a narrow burst (to be loaded into BRAM
-- counter)
-- Add check for throttling condition on after last BRAM address is
-- presented
--
----------------------------------------------------------------------------
-- v1.03a
rd_b2b_elgible_no_thr_check <= '1' when (axi_araddr_full = '1') and
(axi_arlen_pipe_1_or_2 /= '1') and
(axi_arburst_pipe_fixed /= '1') and
(disable_b2b_brst = '0') and
(axi_arsize_pipe_max = '1')
else '0';
rd_b2b_elgible <= '1' when (rd_b2b_elgible_no_thr_check = '1') and
(throttle_last_data = '0')
else '0';
-- Check if SM is in LAST_THROTTLE state which also indicates we are throttling at
-- the last data beat in the read burst. Ensures that the bursts are not implemented
-- as back-to-back bursts and RVALID will negate upon recognition of RLAST and RID
-- pipeline will be advanced properly.
-- Fix timing path on araddr_pipe_sel generated in RDADDR SM
-- SM uses rd_b2b_elgible signal which checks throttle condition on
-- last data beat to hold off loading new BRAM address counter for next
-- back-to-back operation.
-- Attempt to modify logic in generation of throttle_last_data signal.
throttle_last_data <= '1' when ((brst_zero = '1') and (rd_adv_buf = '0')) or
(rd_data_sm_cs = LAST_THROTTLE)
else '0';
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_AR_SNG
-- Purpose: If single port BRAM configuration, set all AR flags from
-- logic generated in sng_port_arb module.
--
---------------------------------------------------------------------------
GEN_AR_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
araddr_pipe_sel <= '0'; -- Unused in single port configuration
ar_active <= Arb2AR_Active;
bram_addr_ld_en <= ar_active_re;
brst_cnt_ld_en <= ar_active_re;
AR2Arb_Active_Clr <= axi_rlast_int and AXI_RREADY;
-- Rising edge detect of Arb2AR_Active
RE_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Clear ar_active_d1 early w/ ar_active
-- So back to back ar_active assertions see the new transaction
-- and initiate the read transfer.
if (S_AXI_AResetn = C_RESET_ACTIVE) or ((axi_rlast_int and AXI_RREADY) = '1') then
ar_active_d1 <= '0';
else
ar_active_d1 <= ar_active;
end if;
end if;
end process RE_AR_ACT;
ar_active_re <= '1' when (ar_active = '1' and ar_active_d1 = '0') else '0';
end generate GEN_AR_SNG;
---------------------------------------------------------------------------
--
-- Generate: GEN_AW_DUAL
-- Purpose: Generate AW control state machine logic only when AXI4
-- controller is configured for dual port mode. In dual port
-- mode, wr_chnl has full access over AW & port A of BRAM.
--
---------------------------------------------------------------------------
GEN_AR_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
AR2Arb_Active_Clr <= '0'; -- Only used in single port case
---------------------------------------------------------------------------
-- RD ADDR State Machine
--
-- Description: Central processing unit for AXI write address
-- channel interface handling and handshaking.
--
-- Outputs: araddr_pipe_ld Not Registered
-- araddr_pipe_sel Not Registered
-- bram_addr_ld_en Not Registered
-- brst_cnt_ld_en Not Registered
-- ar_active_set Not Registered
--
-- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_ADDR_SM_CMB_PROCESS: process ( AXI_ARVALID,
axi_araddr_full,
ar_active,
no_ar_ack,
pend_rd_op,
last_bram_addr,
rd_b2b_elgible,
rd_addr_sm_cs )
begin
-- assign default values for state machine outputs
rd_addr_sm_ns <= rd_addr_sm_cs;
araddr_pipe_ld_i <= '0';
bram_addr_ld_en_i <= '0';
brst_cnt_ld_en_i <= '0';
ar_active_set_i <= '0';
case rd_addr_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
else
rd_addr_sm_ns <= IDLE;
end if;
elsif (AXI_ARVALID = '1') then
-- If address pipeline is full
-- ARReady output is negated
-- Remain in this state
--
-- Add check for already pending read operation
-- in data SM, but waiting on throttle (even though ar_active is
-- already set to '0').
if (ar_active = '0') and (no_ar_ack = '0') and (pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- Address counter is currently busy
else
-- Check if ARADDR pipeline is not full and can be loaded
if (axi_araddr_full = '0') then
rd_addr_sm_ns <= LD_ARADDR;
araddr_pipe_ld_i <= '1';
end if;
end if; -- ar_active
-- Pending operation in pipeline that is waiting
-- until current operation is complete (ar_active = '0')
elsif (axi_araddr_full = '1') and
(ar_active = '0') and
(no_ar_ack = '0') and
(pend_rd_op = '0') then
rd_addr_sm_ns <= IDLE;
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
end if; -- ARVALID
---------------------------- LD_ARADDR State ---------------------------
when LD_ARADDR =>
-- Check here for subsequent BRAM address load when ARADDR pipe is loaded
-- in previous clock cycle.
--
-- Reload BRAM address counter on last BRAM address of current burst
-- if a new address is pending in the AR pipeline and is elgible to
-- be loaded for subsequent back-to-back performance.
if (last_bram_addr = '1' and rd_b2b_elgible = '1') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
brst_cnt_ld_en_i <= '1';
ar_active_set_i <= '1';
-- If loading BRAM counter for subsequent operation
-- AND ARVALID is pending on the bus, go ahead and respond
-- and fill ARADDR pipeline with next operation.
--
-- Asserting the signal to load the ARADDR pipeline here
-- allows the full bandwidth utilization to BRAM on
-- back to back bursts of two data beats.
if (AXI_ARVALID = '1') then
araddr_pipe_ld_i <= '1';
rd_addr_sm_ns <= LD_ARADDR;
-- Stay in this state another clock cycle
else
rd_addr_sm_ns <= IDLE;
end if;
else
rd_addr_sm_ns <= IDLE;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_addr_sm_ns <= IDLE;
--coverage on
end case;
end process RD_ADDR_SM_CMB_PROCESS;
---------------------------------------------------------------------------
-- CR # 582705
-- Ensure combinatorial SM output signals do not get set before
-- the end of the reset (and ARREAADY can be set).
bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2;
brst_cnt_ld_en <= brst_cnt_ld_en_i and axi_aresetn_d2;
ar_active_set <= ar_active_set_i and axi_aresetn_d2;
araddr_pipe_ld <= araddr_pipe_ld_i and axi_aresetn_d2;
RD_ADDR_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
-- Ensure that ar_active does not get asserted (from SM) before
-- the end of reset and the ARREADY flag is set.
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
rd_addr_sm_cs <= IDLE;
else
rd_addr_sm_cs <= rd_addr_sm_ns;
end if;
end if;
end process RD_ADDR_SM_REG_PROCESS;
---------------------------------------------------------------------------
-- Assert araddr_pipe_sel outside of SM logic
-- The BRAM address counter will get loaded with value in ARADDR pipeline
-- when data is stored in the ARADDR pipeline.
araddr_pipe_sel <= '1' when (axi_araddr_full = '1') else '0';
---------------------------------------------------------------------------
-- Register for ar_active
REG_AR_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
ar_active <= '0';
elsif (ar_active_set = '1') then
ar_active <= '1';
-- For code coverage closure, ensure priority encoding in if/else clause
-- to prevent checking ar_active_set in reset clause.
elsif (ar_active_clr = '1') then
ar_active <= '0';
else
ar_active <= ar_active;
end if;
end if;
end process REG_AR_ACT;
end generate GEN_AR_DUAL;
---------------------------------------------------------------------------
--
-- REG_BRST_CNT.
-- Read Burst Counter.
-- No need to decrement burst counter.
-- Able to load with fixed burst length value.
-- Replace usage of proc_common_v4_0 library with direct HDL.
--
-- Size of counter = C_BRST_CNT_SIZE
-- Max size of burst transfer = 256 data beats
--
---------------------------------------------------------------------------
REG_BRST_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (brst_cnt_rst = '1') then
brst_cnt <= (others => '0');
-- Load burst counter
elsif (brst_cnt_ld_en = '1') then
brst_cnt <= brst_cnt_ld;
-- Decrement ONLY (no increment functionality)
elsif (brst_cnt_dec = '1') then
brst_cnt (C_BRST_CNT_SIZE-1 downto 0) <=
std_logic_vector (unsigned (brst_cnt (C_BRST_CNT_SIZE-1 downto 0)) - 1);
end if;
end if;
end process REG_BRST_CNT;
---------------------------------------------------------------------------
brst_cnt_rst <= not (S_AXI_AResetn);
-- Determine burst count load value
-- Either load BRAM counter directly from AXI bus or from stored registered value.
-- Use mux signal for ARLEN
BRST_CNT_LD_PROCESS : process (curr_arlen)
variable brst_cnt_ld_int : integer := 0;
begin
brst_cnt_ld_int := to_integer (unsigned (curr_arlen (7 downto 0)));
brst_cnt_ld <= std_logic_vector (to_unsigned (brst_cnt_ld_int, 8));
end process BRST_CNT_LD_PROCESS;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_W_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation supports narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_W_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1')
-- Added with single port (13.1 release)
or (end_brst_rd_clr = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- Hold off assertion of brst_cnt_max on narrow burst transfers
-- Must wait until narrow burst count = 0.
if (curr_narrow_burst = '1') then
if (narrow_bram_addr_inc = '1') then
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= '1';
end if;
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_W_NARROW;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRST_MAX_WO_NARROW
-- Purpose: Generate registered logic for brst_cnt_max when the
-- design instantiation does not support narrow operations.
--
---------------------------------------------------------------------------
GEN_BRST_MAX_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
REG_BRST_MAX: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_cnt_ld_en = '1') then
brst_cnt_max <= '0';
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
elsif (brst_zero = '1') and (ar_active = '1') and (pend_rd_op = '0') then
-- When narrow operations are not supported in the core
-- configuration, no check for curr_narrow_burst on assertion.
brst_cnt_max <= '1';
else
brst_cnt_max <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX;
end generate GEN_BRST_MAX_WO_NARROW;
---------------------------------------------------------------------------
REG_BRST_MAX_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
brst_cnt_max_d1 <= '0';
else
brst_cnt_max_d1 <= brst_cnt_max;
end if;
end if;
end process REG_BRST_MAX_D1;
brst_cnt_max_re <= '1' when (brst_cnt_max = '1') and (brst_cnt_max_d1 = '0') else '0';
-- Set flag that end of burst is reached
-- Need to capture this condition as the burst
-- counter may get reloaded for a subsequent read burst
REG_END_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- SM may assert clear flag early (in case of narrow bursts)
-- Wait until the end_brst_rd flag is asserted to clear the flag.
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(end_brst_rd_clr = '1' and end_brst_rd = '1') then
end_brst_rd <= '0';
elsif (brst_cnt_max_re = '1') then
end_brst_rd <= '1';
end if;
end if;
end process REG_END_BURST;
---------------------------------------------------------------------------
-- Create flag that indicates burst counter is reaching ZEROs (max of burst
-- length)
REG_BURST_ZERO: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ZERO)) then
brst_zero <= '0';
elsif (brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE) then
brst_zero <= '1';
else
brst_zero <= brst_zero;
end if;
end if;
end process REG_BURST_ZERO;
---------------------------------------------------------------------------
-- Create additional flag that indicates burst counter is reaching ONEs
-- (near end of burst length). Used to disable back-to-back condition in SM.
REG_BURST_ONE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld /= C_BRST_CNT_ONE)) or
((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_ONE)) then
brst_one <= '0';
elsif ((brst_cnt_dec = '1') and (brst_cnt = C_BRST_CNT_TWO)) or
((brst_cnt_ld_en = '1') and (brst_cnt_ld = C_BRST_CNT_ONE)) then
brst_one <= '1';
else
brst_one <= brst_one;
end if;
end if;
end process REG_BURST_ONE;
---------------------------------------------------------------------------
-- Register flags for read burst operation
REG_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear axi_rd_burst flags when burst count gets to zeros (unless the burst
-- counter is getting subsequently loaded for the new burst operation)
--
-- Replace usage of brst_cnt in this logic.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (S_AXI_AResetn = C_RESET_ACTIVE) or (brst_zero = '1' and brst_cnt_ld_en = '0') then
axi_rd_burst <= '0';
axi_rd_burst_two <= '0';
elsif (brst_cnt_ld_en = '1') then
if (curr_arlen /= AXI_ARLEN_ONE and curr_arlen /= AXI_ARLEN_TWO) then
axi_rd_burst <= '1';
else
axi_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
axi_rd_burst_two <= '1';
else
axi_rd_burst_two <= '0';
end if;
else
axi_rd_burst <= axi_rd_burst;
axi_rd_burst_two <= axi_rd_burst_two;
end if;
end if;
end process REG_RD_BURST;
---------------------------------------------------------------------------
-- Seeing issue with axi_rd_burst getting cleared too soon
-- on subsquent brst_cnt_ld_en early assertion and pend_rd_op is asserted.
-- Create flag for currently active read burst operation
-- Gets asserted when burst counter is loaded, but does not
-- get cleared until the RD_DATA_SM has completed the read
-- burst operation
REG_ACT_RD_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (act_rd_burst_clr = '1') then
act_rd_burst <= '0';
act_rd_burst_two <= '0';
elsif (act_rd_burst_set = '1') then
-- If not loading the burst counter for a B2B operation
-- Then act_rd_burst follows axi_rd_burst and
-- act_rd_burst_two follows axi_rd_burst_two.
-- Get registered value of axi_* signal.
if (brst_cnt_ld_en = '0') then
act_rd_burst <= axi_rd_burst;
act_rd_burst_two <= axi_rd_burst_two;
else
-- Otherwise, duplicate logic for axi_* signals if burst counter
-- is getting loaded.
-- For improved code coverage here
-- The act_rd_burst_set signal will never get asserted if the burst
-- size is less than two data beats. So, the conditional check
-- for (curr_arlen /= AXI_ARLEN_ONE) is never evaluated. Removed
-- from this if clause.
if (curr_arlen /= AXI_ARLEN_TWO) then
act_rd_burst <= '1';
else
act_rd_burst <= '0';
end if;
if (curr_arlen = AXI_ARLEN_TWO) then
act_rd_burst_two <= '1';
else
act_rd_burst_two <= '0';
end if;
-- Note: re-code this if/else clause.
end if;
else
act_rd_burst <= act_rd_burst;
act_rd_burst_two <= act_rd_burst_two;
end if;
end if;
end process REG_ACT_RD_BURST;
---------------------------------------------------------------------------
rd_adv_buf <= axi_rvalid_int and AXI_RREADY;
---------------------------------------------------------------------------
-- RD DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking.
--
-- Outputs: Name Type
--
-- bram_en_int Registered
-- bram_addr_inc Not Registered
-- brst_cnt_dec Not Registered
-- rddata_mux_sel Registered
-- axi_rdata_en Not Registered
-- axi_rvalid_set Registered
--
--
-- RD_DATA_SM_CMB_PROCESS: Combinational process to determine next state.
-- RD_DATA_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RD_DATA_SM_CMB_PROCESS: process ( bram_addr_ld_en,
rd_adv_buf,
ar_active,
axi_araddr_full,
rd_b2b_elgible_no_thr_check,
disable_b2b_brst,
curr_arlen,
axi_rd_burst,
axi_rd_burst_two,
act_rd_burst,
act_rd_burst_two,
end_brst_rd,
brst_zero,
brst_one,
axi_b2b_brst,
bram_en_int,
rddata_mux_sel,
end_brst_rd_clr,
no_ar_ack,
pend_rd_op,
axi_rlast_int,
rd_data_sm_cs )
begin
-- assign default values for state machine outputs
rd_data_sm_ns <= rd_data_sm_cs;
bram_en_cmb <= bram_en_int;
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_skid_buf_ld_cmb <= '0';
rd_skid_buf_ld_imm <= '0';
rddata_mux_sel_cmb <= rddata_mux_sel;
-- Change axi_rdata_en generated from SM to be a combinatorial signal
-- Can't afford the latency when throttling on the AXI bus.
axi_rdata_en <= '0';
axi_rvalid_set_cmb <= '0';
end_brst_rd_clr_cmb <= end_brst_rd_clr;
no_ar_ack_cmb <= no_ar_ack;
pend_rd_op_cmb <= pend_rd_op;
act_rd_burst_set <= '0';
act_rd_burst_clr <= '0';
set_last_bram_addr <= '0';
alast_bram_addr <= '0';
axi_b2b_brst_cmb <= axi_b2b_brst;
disable_b2b_brst_cmb <= disable_b2b_brst;
ar_active_clr <= '0';
case rd_data_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Initiate BRAM read when address is available in controller
-- Indicated by load of BRAM address counter
-- Remove use of pend_rd_op signal.
-- Never asserted as we transition back to IDLE
-- Detected in code coverage
if (bram_addr_ld_en = '1') then
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- If currently loading BRAM address counter
-- Must check curr_arlen (mux output from pipe or AXI bus)
-- to determine length of next operation.
-- If ARLEN = 1 data beat, then set last_bram_addr signal
-- Otherwise, increment BRAM address counter.
if (curr_arlen /= AXI_ARLEN_ONE) then
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
else
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
-- Go to single active read address state
rd_data_sm_ns <= SNG_ADDR;
end if;
------------------------- SNG_ADDR State --------------------------
when SNG_ADDR =>
-- Clear flag once pending read is recognized
-- Duplicate logic here in case combinatorial flag was getting
-- set as the SM transitioned into this state.
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- At start of new read, clear end burst signal
end_brst_rd_clr_cmb <= '0';
-- Reach this state on first BRAM address & enable assertion
-- For burst operation, create next BRAM address and keep enable
-- asserted
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Reset data mux select between skid buffer and BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Assert RVALID on AXI when 1st data beat available
-- from BRAM
axi_rvalid_set_cmb <= '1';
-- Reach this state when BRAM address counter is loaded
-- Use axi_rd_burst and axi_rd_burst_two to indicate if
-- operation is a single data beat burst.
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Proceed directly to get BRAM read data
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Read burst
else
-- Increment BRAM address counter (2nd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (2nd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= SEC_ADDR;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Start of new operation, update act_rd_burst and
-- act_rd_burst_two signals
act_rd_burst_set <= '1';
-- If new burst is 2 data beats
-- Then disable capability on back-to-back bursts
if (axi_rd_burst_two = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
else
-- Support back-to-back for all other burst lengths
disable_b2b_brst_cmb <= '0';
end if;
end if;
------------------------- SEC_ADDR State --------------------------
when SEC_ADDR =>
-- Reach this state when the 2nd incremented address of the burst
-- is presented to the BRAM.
-- Only reach this state when axi_rd_burst = '1',
-- an active read burst.
-- Note:
-- No ability to throttle yet as RVALID has not yet been
-- asserted on the AXI bus
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- If we see the next address get loaded into the BRAM counter
-- then set flag for pending operation
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
end if;
-- Check here for burst length of two data transfers
-- If so, then the SM will NOT hit the condition of a full
-- pipeline:
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAm address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
--
-- Full pipeline condition is hit for any read burst
-- length greater than 2 data beats.
if (axi_rd_burst_two = '1') then
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
rd_data_sm_ns <= LAST_ADDR;
-- End of active current read address
ar_active_clr <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- Load read data skid buffer for BRAM capture
-- in next clock cycle.
-- This signal will negate in the next state
-- if the data is not accepted on the AXI bus.
-- So that no new data from BRAM is registered into the
-- read channel controller.
rd_skid_buf_ld_cmb <= '1';
else
-- Burst length will hit full pipeline condition
-- Increment BRAM address counter (3rd data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (3rd data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Load read data skid buffer for BRAM capture
-- in next clock cycle
rd_skid_buf_ld_cmb <= '1';
end if; -- ARLEN = "0000 0001"
------------------------- FULL_PIPE State -------------------------
when FULL_PIPE =>
-- Reach this state when all three data beats in the burst
-- are active
--
-- Operation A) 1st BRAM address data on AXI bus
-- Operation B) 2nd BRAM address data read from BRAM
-- Operation C) 3rd BRAM address presented to BRAM
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- With new pipelining capability BRAM address counter may be
-- loaded in this state. This only occurs on back-to-back
-- bursts (when enabled).
-- No flag set for pending operation.
-- Modify the if clause here to check for back-to-back burst operations
-- If we load the BRAM address in this state for a subsequent burst, then
-- this condition indicates a back-to-back burst and no need to assert
-- the pending read operation flag.
-- Seeing corner case when pend_rd_op needs to be asserted and cleared
-- in this state. If the BRAM address counter is loaded early, but
-- axi_rlast_set is delayed in getting asserted (all while in this state).
-- The signal, curr_narrow_burst can not get cleared.
-- Only in dual port mode can the address counter get loaded early
if C_SINGLE_PORT_BRAM = 0 then
-- Set flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
end if;
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat of burst.
-- If not, then go to FULL_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Load read data skid buffer for BRAM capture in next clock cycle
rd_skid_buf_ld_cmb <= '1';
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- Replace usage of brst_cnt with signal, brst_one.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1' and axi_b2b_brst = '0') then
-- Check for elgible pending read operation to support back-to-back performance.
-- If so, load BRAM address counter.
--
-- Replace rd_b2b_elgible signal check to remove path from
-- arlen_pipe through rd_b2b_elgible
-- (with data throttle check)
if (rd_b2b_elgible_no_thr_check = '1') then
rd_data_sm_ns <= FULL_PIPE;
-- Set flag to indicate back-to-back read burst
-- RVALID will not clear in this case and remain asserted
axi_b2b_brst_cmb <= '1';
-- Set flag to update active read burst or
-- read burst of two flag
act_rd_burst_set <= '1';
-- Otherwise, complete current transaction
else
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
end if;
else
-- Remain in this state until burst count reaches zero
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
-- Skid buffer load will remain asserted
-- AXI read data register is asserted
end if;
else
-- Throttling condition detected
rd_data_sm_ns <= FULL_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Negate load of read data skid buffer for BRAM capture
-- in next clock cycle due to detection of Throttle condition
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- If transitioning to throttle state
-- Then next register enable assertion of the AXI read data
-- output register needs to come from the skid buffer
-- Set read data mux select here for SKID_BUFFER data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Detect if at end of burst read as we transition to FULL_THROTTLE
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back to back "non bubble" support when AXI master
-- is throttling on current burst.
-- Seperate signal throttle_last_data will be asserted outside SM.
-- End of burst read, negate BRAM enable
bram_en_cmb <= '0';
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Disable B2B capability if throttling detected when
-- burst count is equal to one.
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
elsif (brst_one = '1') then
-- Assert new flag to disable back-to-back bursts
-- due to throttling
disable_b2b_brst_cmb <= '1';
-- Throttle, but not end of burst
else
bram_en_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------- FULL_THROTTLE State ---------------------
when FULL_THROTTLE =>
-- Reach this state when the AXI bus throttles on the AXI data
-- beat read from BRAM (when the read pipeline is fully active)
-- Flag disable_b2b_brst_cmb should be asserted as we transition
-- to this state. Flag is asserted near the end of a read burst
-- to prevent the back-to-back performance pipelining in the BRAM
-- address counter.
-- Detect if at end of burst read
-- If so, negate the BRAM enable even if prior to throttle condition
-- on AXI bus. Read skid buffer will hold last beat of data in burst.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
bram_en_cmb <= '0';
end if;
-- Set new flag for pending operation if bram_addr_ld_en is asserted (BRAM
-- address is loaded) and we are waiting for the current read burst to complete.
if (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
-- Clear flag once pending read is recognized and
-- earlier read data phase is complete.
elsif (pend_rd_op = '1') and (axi_rlast_int = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Ensure read data mux is set for skid buffer data
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- Ensure that AXI read data output register is enabled
axi_rdata_en <= '1';
-- Must reload skid buffer here from BRAM data
-- so if needed can be presented to AXI bus on the following clock cycle
rd_skid_buf_ld_imm <= '1';
-- When detecting end of throttle condition
-- Check first if burst count is complete
-- Check burst counter for max
-- If max burst count is reached, no new addresses
-- presented to BRAM, advance to last capture data states.
--
-- For timing, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_zero, indicating the
-- brst_cnt to be zero when decrement.
if (brst_zero = '1') or (end_brst_rd = '1') then
-- No back-to-back performance when AXI master throttles
-- If we reach the end of the burst, proceed to LAST_ADDR state.
-- No increment of BRAM address
-- or decrement of burst counter
-- Burst counter should be = zero
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
rd_data_sm_ns <= LAST_ADDR;
-- Negate BRAM enable
bram_en_cmb <= '0';
-- End of active current read address
ar_active_clr <= '1';
-- Not end of current burst w/ throttle condition
else
-- Go back to FULL_PIPE
rd_data_sm_ns <= FULL_PIPE;
-- Assert almost last BRAM address flag
-- so that ARVALID logic output can remain registered
--
-- For timing purposes, replace usage of brst_cnt in this SM.
-- Replace with registered signal, brst_one, indicating the
-- brst_cnt to be one when decrement.
if (brst_one = '1') then
alast_bram_addr <= '1';
end if;
-- Increment BRAM address counter (Nth data beat)
bram_addr_inc <= '1';
-- Decrement BRAM burst counter (Nth data beat)
brst_cnt_dec <= '1';
-- Keep BRAM enable asserted
bram_en_cmb <= '1';
end if; -- Burst Max
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_ADDR State -------------------------
when LAST_ADDR =>
-- Reach this state in the clock cycle following the last address
-- presented to the BRAM. Capture the last BRAM data beat in the
-- next clock cycle.
--
-- Data is presented to AXI bus (if no throttling detected) and
-- loaded into the skid buffer.
-- If we reach this state after back to back burst transfers
-- then clear the flag to ensure that RVALID will clear when RLAST
-- is recognized
if (axi_b2b_brst = '1') then
axi_b2b_brst_cmb <= '0';
end if;
-- Clear flag that indicates end of read burst
-- Once we reach this state, we have recognized the burst complete.
--
-- It is getting asserted too early
-- and recognition of the end of the burst is missed when throttling
-- on the last two data beats in the read.
end_brst_rd_clr_cmb <= '1';
-- Set new flag for pending operation if ar_active is asserted (BRAM
-- address has already been loaded) and we are waiting for the current
-- read burst to complete. If those two conditions apply, set this flag.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-backs for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- if (ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1') then
pend_rd_op_cmb <= '1';
end if;
-- Load read data skid buffer for BRAM is asserted on transition
-- into this state. Only gets negated if done with operation
-- as detected in below if clause.
-- Check flag for no subsequent operations
-- Clear that now, with current operation completing
if (no_ar_ack = '1') then
no_ar_ack_cmb <= '0';
end if;
-- Check for single AXI read operations
-- If so, wait for RREADY to be asserted
-- Check for burst and bursts of two as seperate signals.
if (act_rd_burst = '0') and (act_rd_burst_two = '0') then
-- Create rvalid_set to only be asserted for a single clock
-- cycle.
-- Will get set as transitioning to LAST_ADDR on single read operations
-- Only assert RVALID here on single operations
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Data will not yet be acknowledged on AXI
-- in this state.
-- Go to wait for last data beat
rd_data_sm_ns <= LAST_DATA;
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
else
-- Only check throttling on AXI during read data burst operations
-- Check AXI throttling condition
-- If AXI bus advances and accepts read data, SM can
-- proceed with next data beat.
-- If not, then go to LAST_THROTTLE state to wait for
-- AXI_RREADY = '1'.
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
-- in next clock cycle
-- Enable AXI read data register
axi_rdata_en <= '1';
-- Ensure read data mux is set for BRAM data
rddata_mux_sel_cmb <= C_RDDATA_MUX_BRAM;
-- Burst counter already at zero. Reached this state due to NO
-- pending ARADDR in the read address pipeline. However, check
-- here for any new read addresses.
-- New ARADDR detected and loaded into BRAM address counter
-- Add check here for previously loaded BRAM address
-- ar_active will be asserted (and qualify that with the
-- condition that the read burst is complete, for narrow reads).
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Instead of transitioning to SNG_ADDR
-- go to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
else
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
end if; -- bram_addr_ld_en (New read burst)
else
-- Throttling condition detected
rd_data_sm_ns <= LAST_THROTTLE;
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- Skid buffer gets loaded from BRAM read data in next clock
-- cycle ONLY.
-- Only on transition to THROTTLE state does skid buffer get loaded.
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
end if; -- rd_adv_buf (RREADY throttle)
end if; -- AXI read burst
------------------------- LAST_THROTTLE State ---------------------
when LAST_THROTTLE =>
-- Reach this state when the AXI bus throttles on the last data
-- beat read from BRAM
-- Data to be sourced from read skid buffer
-- Add check in LAST_THROTTLE as well as LAST_ADDR
-- as we may miss the setting of this flag for a subsequent operation.
-- For dual port, support checking for early writes into BRAM address counter
if (C_SINGLE_PORT_BRAM = 0) and ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
-- Support back-to-back for single AND dual port modes.
-- if ((ar_active = '1' and end_brst_rd = '1') or (bram_addr_ld_en = '1')) then
pend_rd_op_cmb <= '1';
end if;
-- Wait for RREADY to be asserted w/ RVALID on AXI bus
if (rd_adv_buf = '1') then
-- Assert AXI read data enable for BRAM capture
axi_rdata_en <= '1';
-- Set read data mux select for SKID BUF
rddata_mux_sel_cmb <= C_RDDATA_MUX_SKID_BUF;
-- No pending read address to initiate next read burst
-- Go to capture last data beat from BRAM and present on AXI bus.
rd_data_sm_ns <= LAST_DATA;
-- Load read data skid buffer for BRAM capture in next clock cycle
-- of last data read
-- Read Skid buffer already loaded with last data beat from BRAM
-- Does not need to be asserted again in this state
else
-- Stay in this state
-- Ensure that AXI read data output register is disabled
axi_rdata_en <= '0';
-- Ensure that skid buffer is not getting loaded with
-- current read data from BRAM
rd_skid_buf_ld_cmb <= '0';
-- BRAM address is NOT getting incremented
-- (same for burst counter)
bram_addr_inc <= '0';
brst_cnt_dec <= '0';
-- Keep RVALID asserted on AXI
-- No need to assert RVALID again
end if; -- rd_adv_buf (RREADY throttle)
------------------------- LAST_DATA State -------------------------
when LAST_DATA =>
-- Reach this state when last BRAM data beat is
-- presented on AXI bus.
-- For a read burst, RLAST is not asserted until SM reaches
-- this state.
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Stay in this state until RREADY is asserted on AXI bus
-- Indicated by assertion of rd_adv_buf
if (rd_adv_buf = '1') then
-- Last data beat acknowledged on AXI bus
-- Check for new read burst or proceed back to IDLE
-- New ARADDR detected and loaded into BRAM address counter
-- Note: this condition may occur when C_SINGLE_PORT_BRAM = 0 or 1
if (bram_addr_ld_en = '1') or (pend_rd_op = '1') then
-- Clear flag once pending read is recognized
if (pend_rd_op = '1') then
pend_rd_op_cmb <= '0';
end if;
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- If we are loading the BRAM, then we have to view the curr_arlen
-- signal to determine if the next operation is a single transfer.
-- Or if the BRAM address counter is already loaded (and we reach
-- this if clause due to pend_rd_op then the axi_* signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (bram_addr_ld_en = '1') then
if (curr_arlen = AXI_ARLEN_ONE) then
-- Set flag for last_bram_addr on transition
-- to SNG_ADDR on single operations.
set_last_bram_addr <= '1';
end if;
elsif (pend_rd_op = '1') then
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
end if;
else
-- No pending read address to initiate next read burst.
-- Go to IDLE
rd_data_sm_ns <= IDLE;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
end if;
else
-- Throttling condition detected
-- Ensure that AXI read data output register is disabled
-- due to throttle condition.
axi_rdata_en <= '0';
-- If new ARADDR detected and loaded into BRAM address counter
if (bram_addr_ld_en = '1') then
-- Initiate BRAM read transfer
bram_en_cmb <= '1';
-- Only count addresses & burst length for read
-- burst operations
-- Instead of transitioning to SNG_ADDR
-- to wait for last data beat.
rd_data_sm_ns <= LAST_DATA_AR_PEND;
-- For singles, block any subsequent loads into BRAM address
-- counter from AR SM
no_ar_ack_cmb <= '1';
end if;
end if; -- rd_adv_buf (RREADY throttle)
------------------------ LAST_DATA_AR_PEND --------------------
when LAST_DATA_AR_PEND =>
-- Ok to accept new operation if throttling detected
-- during current operation (and flag was previously set
-- to disable the back-to-back performance).
disable_b2b_brst_cmb <= '0';
-- Reach this state when new BRAM address is loaded into
-- BRAM address counter
-- But waiting for last RREADY/RVALID/RLAST to be asserted
-- Once this occurs, continue with pending AR operation
if (rd_adv_buf = '1') then
-- Go to SNG_ADDR state
rd_data_sm_ns <= SNG_ADDR;
-- If current operation was a burst, clear the active
-- burst flag
if (act_rd_burst = '1') or (act_rd_burst_two = '1') then
act_rd_burst_clr <= '1';
end if;
-- In this state, the BRAM address counter is already loaded,
-- the axi_rd_burst and axi_rd_burst_two signals will indicate
-- if the next operation is a burst or not.
-- If the operation is a single transaction, then set the last_bram_addr
-- signal when we reach SNG_ADDR.
if (axi_rd_burst = '0' and axi_rd_burst_two = '0') then
set_last_bram_addr <= '1';
end if;
-- Code coverage tests are reporting that reaching this state
-- always when axi_rd_burst = '0' and axi_rd_burst_two = '0',
-- so no bursting operations.
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rd_data_sm_ns <= IDLE;
--coverage on
end case;
end process RD_DATA_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RD_DATA_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_data_sm_cs <= IDLE;
bram_en_int <= '0';
rd_skid_buf_ld_reg <= '0';
rddata_mux_sel <= C_RDDATA_MUX_BRAM;
axi_rvalid_set <= '0';
end_brst_rd_clr <= '0';
no_ar_ack <= '0';
pend_rd_op <= '0';
axi_b2b_brst <= '0';
disable_b2b_brst <= '0';
else
rd_data_sm_cs <= rd_data_sm_ns;
bram_en_int <= bram_en_cmb;
rd_skid_buf_ld_reg <= rd_skid_buf_ld_cmb;
rddata_mux_sel <= rddata_mux_sel_cmb;
axi_rvalid_set <= axi_rvalid_set_cmb;
end_brst_rd_clr <= end_brst_rd_clr_cmb;
no_ar_ack <= no_ar_ack_cmb;
pend_rd_op <= pend_rd_op_cmb;
axi_b2b_brst <= axi_b2b_brst_cmb;
disable_b2b_brst <= disable_b2b_brst_cmb;
end if;
end if;
end process RD_DATA_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Create seperate registered process for last_bram_addr signal.
-- Only asserted for a single clock cycle
-- Gets set when the burst counter is loaded with 0's (for a single data beat operation)
-- (indicated by set_last_bram_addr from DATA SM)
-- or when the burst counter is decrement and the current value = 1
REG_LAST_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
last_bram_addr <= '0';
-- The signal, set_last_bram_addr, is asserted when the DATA SM transitions to SNG_ADDR
-- on a single data beat burst. Can not use condition of loading burst counter
-- with the value of 0's (as the burst counter may be loaded during prior single operation
-- when waiting on last throttle/data beat, ie. rd_adv_buf not yet asserted).
elsif (set_last_bram_addr = '1') or
-- On burst operations at the last BRAM address presented to BRAM
(brst_cnt_dec = '1' and brst_cnt = C_BRST_CNT_ONE) then
last_bram_addr <= '1';
else
last_bram_addr <= '0';
end if;
end if;
end process REG_LAST_BRAM_ADDR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- *** AXI Read Data Channel Interface ***
--
---------------------------------------------------------------------------
rd_skid_buf_ld <= rd_skid_buf_ld_reg or rd_skid_buf_ld_imm;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_NO_ECC
-- Purpose: Generation of AXI_RDATA output register without ECC
-- logic (C_ECC = 0 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_NO_ECC: if C_ECC = 0 generate
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
---------------------------------------------------------------------------
-- AXI RdData Skid Buffer/Register
-- Sized according to size of AXI/BRAM data width
---------------------------------------------------------------------------
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0);
else
rd_skid_buf <= rd_skid_buf;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
rd_skid_buf;
---------------------------------------------------------------------------
-- Generate: GEN_RDATA
-- Purpose: Generate each bit of AXI_RDATA.
---------------------------------------------------------------------------
GEN_RDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate
begin
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear output after last data beat accepted by requesting AXI master
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Don't clear RDDATA when a back to back burst is occuring on RLAST & RVALID assertion
-- For improved code coverage, can remove the signal, axi_rvalid_int from this if clause.
-- It will always be asserted in this case.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int (i) <= '0';
elsif (axi_rdata_en = '1') then
axi_rdata_int (i) <= axi_rdata_mux (i);
else
axi_rdata_int (i) <= axi_rdata_int (i);
end if;
end if;
end process REG_RDATA;
end generate GEN_RDATA;
-- If C_ECC = 0, direct output assignment to AXI_RDATA
AXI_RDATA <= axi_rdata_int;
end generate GEN_RDATA_NO_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RDATA_ECC
-- Purpose: Generation of AXI_RDATA output register when ECC
-- logic is enabled (C_ECC = 1 parameterization in design)
---------------------------------------------------------------------------
GEN_RDATA_ECC: if C_ECC = 1 generate
subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1);
-- 0:6 for 32-bit ECC
-- 0:7 for 64-bit ECC
type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits;
signal rd_skid_buf_i : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi_rdata_int_corr : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- Remove GEN_RD_BUF that was doing bit reversal.
-- Replace with direct register assignments. Sized according to AXI data width.
REG_RD_BUF: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rd_skid_buf_i <= (others => '0');
-- Add immediate load of read skid buffer
-- Occurs in the case when at full throttle and RREADY/RVALID are asserted
elsif (rd_skid_buf_ld = '1') then
rd_skid_buf_i (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
rd_skid_buf_i <= rd_skid_buf_i;
end if;
end if;
end process REG_RD_BUF;
-- Rd Data Mux (selects between skid buffer and BRAM read data)
-- Select control signal from SM determines register load value
-- axi_rdata_mux holds data + ECC bits.
-- Previous mux on input to checkbit_handler logic.
-- Removed now (mux inserted after checkbit_handler logic before register stage)
--
-- axi_rdata_mux <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) when (rddata_mux_sel = C_RDDATA_MUX_BRAM) else
-- rd_skid_buf_i;
-- Remove GEN_RDATA that was doing bit reversal.
REG_RDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rdata_int <= (others => '0');
elsif (axi_rdata_en = '1') then
-- Track uncorrected data vector with AXI RDATA output pipeline
-- Mimic mux logic here (from previous post checkbit XOR logic register)
if (rddata_mux_sel = C_RDDATA_MUX_BRAM) then
axi_rdata_int (C_AXI_DATA_WIDTH-1 downto 0) <= UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1);
else
axi_rdata_int <= rd_skid_buf_i;
end if;
else
axi_rdata_int <= axi_rdata_int;
end if;
end if;
end process REG_RDATA;
-- When C_ECC = 1, correct any single bit errors on output read data.
-- Post register stage to improve timing on ECC logic data path.
-- Use registers in AXI Interconnect IP core.
-- Perform bit swapping on output of correct_one_bit
-- module (axi_rdata_int_corr signal).
-- AXI_RDATA (i) <= axi_rdata_int (i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Found in HW debug
-- axi_rdata_int is reversed to be returned on AXI bus.
-- AXI_RDATA (i) <= axi_rdata_int (C_AXI_DATA_WIDTH-1-i) when (Enable_ECC = '0')
-- else axi_rdata_int_corr (C_AXI_DATA_WIDTH-1-i);
-- Remove bit reversal on AXI_RDATA output.
AXI_RDATA <= axi_rdata_int when (Enable_ECC = '0' or Sl_UE_i = '1') else axi_rdata_int_corr;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HAMMING_ECC_CORR: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: CHK_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
constant correct_data_table_32 : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Only used in 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
syndrome_reg <= (others => '0');
syndrome_4_reg <= (others => '0');
syndrome_6_reg <= (others => '0');
-- Align register stage of syndrome with AXI read data pipeline
elsif (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
else
syndrome_reg <= syndrome_reg;
syndrome_4_reg <= syndrome_4_reg;
syndrome_6_reg <= syndrome_6_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on specific syndrome bits after pipeline stage before
-- correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-- Input signal is declared (N:0).
-- Output signal is (N:0).
-- In order to reuse correct_one_bit module,
-- the single data bit correction is done LSB to MSB
-- in generate statement loop.
-----------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_32 (i))
port map (
DIn => axi_rdata_int (31-i), -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal)
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (31-i)); -- This is to match with LMB Controller Hamming Encoder logic (Bit Reversal)
end generate GEN_CORR_32;
end generate CHK_ECC_32;
------------------------------------------------------------------------
-- Generate: CHK_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
------------------------------------------------------------------------
CHK_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
constant correct_data_table_64 : correct_data_table_type := (
0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001",
4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001",
8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001",
12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001",
16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001",
20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001",
24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101",
28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101",
32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101",
36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101",
40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101",
44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101",
48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101",
52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101",
56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011",
60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011"
);
signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0'); -- Specific for 64-bit ECC
signal syndrome_7_a : std_logic;
signal syndrome_7_b : std_logic;
begin
---------------------------------------------------------------------------
-- Register ECC syndrome value to correct any single bit errors
-- post-register on AXI read data.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Align register stage of syndrome with AXI read data pipeline
if (axi_rdata_en = '1') then
syndrome_reg <= Syndrome;
syndrome_7_reg <= Syndrome_7;
else
syndrome_reg <= syndrome_reg;
syndrome_7_reg <= syndrome_7_reg;
end if;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits after pipeline stage
-- before correct_one_bit_64 module.
PARITY_CHK7_A: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_a ); -- [out std_logic]
PARITY_CHK7_B: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_7_b ); -- [out std_logic]
-- Do last XOR on Syndrome MSB after pipeline stage before correct_one_bit module
-- PASSES: syndrome_reg_i (7) <= syndrome_reg (7) xor syndrome_7_b_reg;
syndrome_reg_i (7) <= syndrome_7_a xor syndrome_7_b;
syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6);
---------------------------------------------------------------------------
-- Generate: GEN_CORR_64
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
-----------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_64
-- Description: Correct output read data based on syndrome vector.
-- A single error can be corrected by decoding the
-- syndrome value.
-----------------------------------------------------------------------
CORR_ONE_BIT_64: entity work.correct_one_bit_64
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_64 (i))
port map (
DIn => axi_rdata_int (i),
Syndrome => syndrome_reg_i,
DCorr => axi_rdata_int_corr (i));
end generate GEN_CORR_64;
end generate CHK_ECC_64;
end generate GEN_HAMMING_ECC_CORR;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC_CORR
--
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
-- Generate statements to correct BRAM read data
-- dependent on ECC type.
------------------------------------------------------------------------
GEN_HSIAO_ECC_CORR: if C_ECC_TYPE = 1 generate
type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
begin
-- Reconstruct H-matrix
H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
-- Based on syndrome value, determine bits to flip in BRAM read data.
GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
ecc_rddata_r <= axi_rdata_int;
axi_rdata_int_corr (C_AXI_DATA_WIDTH-1 downto 0) <= -- UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) xor
ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_AXI_DATA_WIDTH-1 downto 0);
end generate GEN_HSIAO_ECC_CORR;
end generate GEN_RDATA_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_RID_SNG
-- Purpose: Generate RID output pipeline when the core is configured
-- in a single port mode.
---------------------------------------------------------------------------
GEN_RID_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_temp <= AXI_ARID;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rid_int <= (others => '0');
elsif (bram_addr_ld_en = '1') then
axi_rid_int <= AXI_ARID;
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_RID
-- Purpose: Generate RID in dual port mode (with read address pipeline).
---------------------------------------------------------------------------
GEN_RID: if (C_SINGLE_PORT_BRAM = 0) generate
begin
---------------------------------------------------------------------------
-- RID Output Register
--
-- Output RID value either comes from pipelined value or directly wrapped
-- ARID value. Determined by address pipeline usage.
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '0') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp <= axi_arid_pipe;
end if;
-- Add condition to check for temp utilized (temp_full now = '0'), but a
-- pending RID is stored in temp2. Must advance the pipeline.
elsif ((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp <= axi_rid_temp2;
else
axi_rid_temp <= axi_rid_temp;
end if;
end if;
end process REG_RID_TEMP;
-- Create flag that indicates if axi_rid_temp is full
REG_RID_TEMP_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp_full = '1' and
(axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and
axi_rid_temp2_full = '0') then
axi_rid_temp_full <= '0';
elsif (bram_addr_ld_en = '1') or
((axi_rvalid_set = '1' or axi_b2b_rid_adv = '1') and (axi_rid_temp2_full = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp_full <= '1';
else
axi_rid_temp_full <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL;
-- Create flag to detect falling edge of axi_rid_temp_full flag
REG_RID_TEMP_FULL_D1: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp_full_d1 <= '0';
else
axi_rid_temp_full_d1 <= axi_rid_temp_full;
end if;
end if;
end process REG_RID_TEMP_FULL_D1;
axi_rid_temp_full_fe <= '1' when (axi_rid_temp_full = '0' and
axi_rid_temp_full_d1 = '1') else '0';
---------------------------------------------------------------------------
-- Create intermediate temporary RID output register
REG_RID_TEMP2: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rid_temp2 <= (others => '0');
-- When BRAM address counter gets loaded
-- Set output RID value based on address source
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
-- If BRAM address counter gets loaded directly from
-- AXI bus, then save ARID value for wrapping to RID
if (araddr_pipe_sel = '0') then
axi_rid_temp2 <= AXI_ARID;
else
-- Use pipelined AWID value
axi_rid_temp2 <= axi_arid_pipe;
end if;
else
axi_rid_temp2 <= axi_rid_temp2;
end if;
end if;
end process REG_RID_TEMP2;
-- Create flag that indicates if axi_rid_temp2 is full
REG_RID_TEMP2_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rid_temp2_full = '1' and (axi_rvalid_set = '1' or axi_b2b_rid_adv = '1')) or
(axi_rid_temp_full_fe = '1' and axi_rid_temp2_full = '1') then
axi_rid_temp2_full <= '0';
elsif (bram_addr_ld_en = '1') and (axi_rid_temp_full = '1') then
axi_rid_temp2_full <= '1';
else
axi_rid_temp2_full <= axi_rid_temp2_full;
end if;
end if;
end process REG_RID_TEMP2_FULL;
---------------------------------------------------------------------------
-- Output RID register is enabeld when RVALID is asserted on the AXI bus
-- Clear RID when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
REG_RID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, can remove the signal, axi_rvalid_int from statement.
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_b2b_brst = '0') then
axi_rid_int <= (others => '0');
-- Add back to back case to advance RID
elsif (axi_rvalid_set = '1') or (axi_b2b_rid_adv = '1') then
axi_rid_int <= axi_rid_temp;
else
axi_rid_int <= axi_rid_int;
end if;
end if;
end process REG_RID;
-- Advance RID pipeline values
axi_b2b_rid_adv <= '1' when (axi_rlast_int = '1' and
AXI_RREADY = '1' and
axi_b2b_brst = '1')
else '0';
end generate GEN_RID;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP: if C_ECC = 0 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
axi_rresp_int <= RESP_OKAY;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP;
---------------------------------------------------------------------------
-- Generate: GEN_RRESP_ECC
-- Purpose: Create register output unique when ECC is disabled.
-- Only possible output value = OKAY response.
---------------------------------------------------------------------------
GEN_RRESP_ECC: if C_ECC = 1 generate
begin
-----------------------------------------------------------------------
-- AXI_RRESP Output Register
--
-- Set when RVALID is asserted on AXI bus.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking
-- sequence and recognized by AXI requesting master.
-----------------------------------------------------------------------
REG_RRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- For improved code coverage, remove signal, axi_rvalid_int, it will always be asserted.
(axi_rlast_int = '1' and AXI_RREADY = '1') then
axi_rresp_int <= (others => '0');
elsif (axi_rvalid_set = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
-- For ECC implementation
-- Check that an uncorrectable error has not occured.
-- If so, then respond with RESP_SLVERR on AXI.
-- Ok to use combinatorial signal here. The Sl_UE_i
-- flag is generated based on the registered syndrome value.
-- if (Sl_UE_i = '1') then
-- axi_rresp_int <= RESP_SLVERR;
-- else
axi_rresp_int <= RESP_OKAY;
-- end if;
else
axi_rresp_int <= axi_rresp_int;
end if;
end if;
end process REG_RRESP;
end generate GEN_RRESP_ECC;
---------------------------------------------------------------------------
-- AXI_RVALID Output Register
--
-- Set AXI_RVALID when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Clear AXI_RVALID at the end of tranfer when able to clear
-- (axi_rlast_int = '1' and axi_rvalid_int = '1' and AXI_RREADY = '1' and
-- For improved code coverage, remove signal axi_rvalid_int.
(axi_rlast_int = '1' and AXI_RREADY = '1' and
-- Added axi_rvalid_clr_ok to check if during a back-to-back burst
-- and the back-to-back is elgible for streaming performance
axi_rvalid_clr_ok = '1') then
axi_rvalid_int <= '0';
elsif (axi_rvalid_set = '1') then
axi_rvalid_int <= '1';
else
axi_rvalid_int <= axi_rvalid_int;
end if;
end if;
end process REG_RVALID;
-- Create flag that gets set when we load BRAM address early in a B2B scenario
-- This will prevent the RVALID from getting cleared at the end of the current burst
-- Otherwise, the RVALID gets cleared after RLAST/RREADY dual assertion
REG_RVALID_CLR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_rvalid_clr_ok <= '0';
-- When the new address loaded into the BRAM counter is for a back-to-back operation
-- Do not clear the RVALID
elsif (rd_b2b_elgible = '1' and bram_addr_ld_en = '1') then
axi_rvalid_clr_ok <= '0';
-- Else when we start a new transaction (that is not back-to-back)
-- Then enable the RVALID to get cleared upon RLAST/RREADY
elsif (bram_addr_ld_en = '1') or
(axi_rvalid_clr_ok = '0' and
(disable_b2b_brst = '1' or disable_b2b_brst_cmb = '1') and
last_bram_addr = '1') or
-- Add check for current SM state
-- If LAST_ADDR state reached, no longer performing back-to-back
-- transfers and keeping data streaming on AXI bus.
(rd_data_sm_cs = LAST_ADDR) then
axi_rvalid_clr_ok <= '1';
else
axi_rvalid_clr_ok <= axi_rvalid_clr_ok;
end if;
end if;
end process REG_RVALID_CLR;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- AXI_RLAST Output Register
--
-- Set AXI_RLAST when read data SM indicates.
-- Clear when AXI_RLAST is asserted on AXI bus during handshaking sequence
-- and recognized by AXI requesting master.
---------------------------------------------------------------------------
REG_RLAST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- To improve code coverage, remove
-- use of axi_rvalid_int (it will always be asserted with RLAST).
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(axi_rlast_int = '1' and AXI_RREADY = '1' and axi_rlast_set = '0') then
axi_rlast_int <= '0';
elsif (axi_rlast_set = '1') then
axi_rlast_int <= '1';
else
axi_rlast_int <= axi_rlast_int;
end if;
end if;
end process REG_RLAST;
---------------------------------------------------------------------------
-- Generate complete flag
do_cmplt_burst_cmb <= '1' when (last_bram_addr = '1' and
axi_rd_burst = '1' and
axi_rd_burst_two = '0') else '0';
-- Register complete flags
REG_CMPLT_BURST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or (do_cmplt_burst_clr = '1') then
do_cmplt_burst <= '0';
elsif (do_cmplt_burst_cmb = '1') then
do_cmplt_burst <= '1';
else
do_cmplt_burst <= do_cmplt_burst;
end if;
end if;
end process REG_CMPLT_BURST;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- RLAST State Machine
--
-- Description: SM to generate axi_rlast_set signal.
-- Created based on IR # 555346 to track when RLAST needs
-- to be asserted for back to back transfers
-- Uses the indication when last BRAM address is presented
-- and then counts the handshaking cycles on the AXI bus
-- (RVALID and RREADY both asserted).
-- Uses rd_adv_buf to perform this operation.
--
-- Output: Name Type
-- axi_rlast_set Not Registered
-- do_cmplt_burst_clr Not Registered
--
--
-- RLAST_SM_CMB_PROCESS: Combinational process to determine next state.
-- RLAST_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
RLAST_SM_CMB_PROCESS: process (
do_cmplt_burst,
last_bram_addr,
rd_adv_buf,
act_rd_burst,
axi_rd_burst,
act_rd_burst_two,
axi_rd_burst_two,
axi_rlast_int,
rlast_sm_cs )
begin
-- assign default values for state machine outputs
rlast_sm_ns <= rlast_sm_cs;
axi_rlast_set <= '0';
do_cmplt_burst_clr <= '0';
case rlast_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- If last read address is presented to BRAM
if (last_bram_addr = '1') then
-- If the operation is a single read operation
if (axi_rd_burst = '0') and (axi_rd_burst_two = '0') then
-- Go to wait for last data beat
rlast_sm_ns <= W8_LAST_DATA;
-- Else the transaction is a burst
else
-- Throttle condition on 3rd to last data beat
if (rd_adv_buf = '0') then
-- If AXI read burst = 2 (only two data beats to capture)
if (axi_rd_burst_two = '1' or act_rd_burst_two = '1') then
rlast_sm_ns <= W8_THROTTLE_B2;
else
rlast_sm_ns <= W8_THROTTLE;
end if;
-- No throttle on 3rd to last data beat
else
-- Only back-to-back support when burst size is greater
-- than two data beats. We will never toggle on a burst > 2
-- when last_bram_addr is asserted (as this is no toggle
-- condition)
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
do_cmplt_burst_clr <= '1';
end if;
end if;
end if;
------------------------- W8_THROTTLE State -----------------------
when W8_THROTTLE =>
if (rd_adv_buf = '1') then
-- Go to wait for 2nd to last data beat
rlast_sm_ns <= W8_2ND_LAST_DATA;
-- If do_cmplt_burst flag is set, then clear it
if (do_cmplt_burst = '1') then
do_cmplt_burst_clr <= '1';
end if;
end if;
---------------------- W8_2ND_LAST_DATA State ---------------------
when W8_2ND_LAST_DATA =>
if (rd_adv_buf = '1') then
-- Assert RLAST on AXI
axi_rlast_set <= '1';
rlast_sm_ns <= W8_LAST_DATA;
end if;
------------------------- W8_LAST_DATA State ----------------------
when W8_LAST_DATA =>
-- If pending single to complete, keep RLAST asserted
-- Added to only assert axi_rlast_set for a single clock cycle
-- when we enter this state and are here waiting for the
-- throttle on the AXI bus.
if (axi_rlast_int = '1') then
axi_rlast_set <= '0';
else
axi_rlast_set <= '1';
end if;
-- Wait for last data beat to transition back to IDLE
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
end if;
-------------------------- W8_THROTTLE_B2 ------------------------
when W8_THROTTLE_B2 =>
-- Wait for last data beat to transition back to IDLE
-- and set RLAST
if (rd_adv_buf = '1') then
rlast_sm_ns <= IDLE;
axi_rlast_set <= '1';
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
rlast_sm_ns <= IDLE;
--coverage on
end case;
end process RLAST_SM_CMB_PROCESS;
---------------------------------------------------------------------------
RLAST_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
rlast_sm_cs <= IDLE;
else
rlast_sm_cs <= rlast_sm_ns;
end if;
end if;
end process RLAST_SM_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal CE_Q : std_logic := '0';
signal Sl_CE_i : std_logic := '0';
signal bram_en_int_d1 : std_logic := '0';
signal bram_en_int_d2 : std_logic := '0';
begin
-- Generate signal to advance BRAM read address pipeline to
-- capture address for ECC error conditions (in lite_ecc_reg module).
-- BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or
-- ((bram_en_int or bram_en_int_reg) and not (axi_rd_burst) and not (axi_rd_burst_two));
BRAM_Addr_En <= bram_addr_inc or narrow_bram_addr_inc_re or rd_adv_buf or
((bram_en_int or bram_en_int_d1 or bram_en_int_d2) and not (axi_rd_burst) and not (axi_rd_burst_two));
-- Enable 2nd & 3rd pipeline stage for BRAM address storage with single read transfers.
BRAM_EN_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
bram_en_int_d1 <= bram_en_int;
bram_en_int_d2 <= bram_en_int_d1;
end if;
end process BRAM_EN_REG;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
------------------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: Check ECC data unique for 32-bit BRAM.
-- Add extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 32-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
signal bram_din_a_rev : std_logic_vector(31 downto 0) := (others => '0'); -- Specific to BRAM data width
signal bram_din_ecc_a_rev : std_logic_vector(6 downto 0) := (others => '0'); -- Specific to BRAM data width
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
-- process (bram_din_a_i) begin
-- for k in 0 to 31 loop
-- bram_din_a_rev(k) <= bram_din_a_i(39-k);
-- end loop;
-- for k in 0 to 6 loop
-- bram_din_ecc_a_rev(0) <= bram_din_a_i(6-k);
-- end loop;
-- end process;
CHK_HANDLER_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- In 32-bit BRAM use case: DataIn (8:39)
-- CheckIn (1:7)
DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)]
--DataIn => bram_din_a_rev, -- [in std_logic_vector(0 to 31)]
--CheckIn => bram_din_ecc_a_rev, -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [out std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_32 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_32;
------------------------------------------------------------------------
-- Generate: GEN_ECC_64
-- Purpose: Check ECC data unique for 64-bit BRAM.
-- No extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 64-bit BRAM data widths.
-- ECC bits are in upper order bits.
------------------------------------------------------------------------
GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_64
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_64: entity work.checkbit_handler_64
generic map (
C_ENCODE => false, -- [boolean]
C_REG => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
Clk => S_AXI_AClk, -- [in std_logic]
-- In 64-bit BRAM use case: DataIn (8:71)
-- CheckIn (0:7)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)]
CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 7)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)]
Syndrome_7 => Syndrome_7,
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
-- GEN_CORR_64 generate & correct_one_bit instantiation moved to generate
-- of AXI RDATA output register logic.
end generate GEN_ECC_64;
end generate GEN_HAMMING_ECC;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal syndrome_ns : std_logic_vector (ECC_WIDTH - 1 downto 0) := (others => '0');
begin
-- Generate ECC check bits and syndrome values based on
-- BRAM read data.
-- Generate appropriate single or double bit error flags.
-- Instantiate ecc_gen_hsiao module, generated from MIG
I_ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( -- bram_din_a_i (0 to CODE_WIDTH-1)
BRAM_RdData (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome.
-- Same as Hamming ECC code. Syndrome value is registered.
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
end if;
end process REG_SYNDROME;
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not(REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
-- Capture correctable/uncorrectable error from BRAM read
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (Enable_ECC = '1') and
(axi_rvalid_int = '1' and AXI_RREADY = '1') then -- Capture error flags
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- The signal, axi_rdata_en loads the syndrome_reg.
-- Use the AXI RVALID/READY signals to capture state of UE and CE.
-- Since flag generation uses the registered syndrome value.
-- ECC register block gets registered UE or CE conditions to update
-- ECC registers/interrupt/flag outputs.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
-- CE_Failing_We <= Sl_CE_i and Enable_ECC and axi_rvalid_set;
CE_Failing_We <= CE_Q;
---------------------------------------------------------------------------
-- Generate BRAM read data vector assignment to always be from Port A
-- in a single port BRAM configuration.
-- Map BRAM_RdData (Port A) (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
--
-- Port A or Port B sourcing done at full_axi module level
---------------------------------------------------------------------------
-- Original design with mux (BRAM vs. Skid Buffer) on input side of checkbit_handler logic.
-- Move mux to enable on AXI RDATA register.
bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <= BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
-- Map data vector from BRAM to use in correct_one_bit module with
-- register syndrome (post AXI RDATA register).
UnCorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= bram_din_a_i (C_ECC_WIDTH to C_ECC_WIDTH+C_AXI_DATA_WIDTH-1);
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Drive default output signals when ECC is diabled.
---------------------------------------------------------------------------
GEN_NO_ECC: if C_ECC = 0 generate
begin
BRAM_Addr_En <= '0';
CE_Failing_We <= '0';
Sl_CE <= '0';
Sl_UE <= '0';
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
--
-- *** BRAM Interface Signals ***
--
---------------------------------------------------------------------------
BRAM_En <= bram_en_int;
---------------------------------------------------------------------------
-- BRAM Address Generate
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
--
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
--
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
---------------------------------------------------------------------------
end architecture implementation;
|
mit
|
8135ab22ae329b114cf2ab6da1bdecdc
| 0.432192 | 4.760586 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/VGA/ipcore_dir/fifo_mem/simulation/fifo_mem_synth.vhd
| 2 | 8,884 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_mem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY fifo_mem_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE fifo_mem_synth_ARCH OF fifo_mem_synth IS
COMPONENT fifo_mem_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ADDRB: STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(10 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => clkb_in_i,
RST => RSTB,
EN => CHECKER_EN_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(0)
);
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
IF(RSTB='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => clk_in_i,
CLKB => clkb_in_i,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
ADDRB => ADDRB,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: fifo_mem_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
CLKA => CLKA,
--Port B
ADDRB => ADDRB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
|
mit
|
426e26ecb911b390e6bf942de52d522b
| 0.568213 | 3.588045 | false | false | false | false |
julioamerico/prj_crc_ip
|
src/SoC/component/Actel/DirectCore/CoreAHBLite/5.0.100/mti/user_vlog/COREAHBLITE_LIB/@b@f@m_@a@h@b@s@l@a@v@e@e@x@t/_primary.vhd
| 2 | 2,196 |
library verilog;
use verilog.vl_types.all;
entity BFM_AHBSLAVEEXT is
generic(
AWIDTH : integer := 10;
DEPTH : integer := 256;
EXT_SIZE : integer := 2;
INITFILE : string := " ";
ID : integer := 0;
ENFUNC : integer := 0;
ENFIFO : integer := 0;
TPD : integer := 1;
DEBUG : integer := -1
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector;
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic;
EXT_EN : in vl_logic;
EXT_WR : in vl_logic;
EXT_RD : in vl_logic;
EXT_ADDR : in vl_logic_vector;
EXT_DATA : inout vl_logic_vector(31 downto 0);
TXREADY : out vl_logic;
RXREADY : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AWIDTH : constant is 1;
attribute mti_svvh_generic_type of DEPTH : constant is 1;
attribute mti_svvh_generic_type of EXT_SIZE : constant is 1;
attribute mti_svvh_generic_type of INITFILE : constant is 1;
attribute mti_svvh_generic_type of ID : constant is 1;
attribute mti_svvh_generic_type of ENFUNC : constant is 1;
attribute mti_svvh_generic_type of ENFIFO : constant is 1;
attribute mti_svvh_generic_type of TPD : constant is 1;
attribute mti_svvh_generic_type of DEBUG : constant is 1;
end BFM_AHBSLAVEEXT;
|
gpl-3.0
|
4a95bc9e49106f43f5cee542a4114f67
| 0.500911 | 3.928444 | false | false | false | false |
julioamerico/prj_crc_ip
|
src/SoC/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@b@f@m_@m@a@i@n/_primary.vhd
| 3 | 9,125 |
library verilog;
use verilog.vl_types.all;
entity BFM_MAIN is
generic(
OPMODE : integer := 0;
VECTFILE : string := "test.vec";
MAX_INSTRUCTIONS: integer := 16384;
MAX_STACK : integer := 1024;
MAX_MEMTEST : integer := 65536;
TPD : integer := 1;
DEBUGLEVEL : integer := -1;
CON_SPULSE : integer := 0;
ARGVALUE0 : integer := 0;
ARGVALUE1 : integer := 0;
ARGVALUE2 : integer := 0;
ARGVALUE3 : integer := 0;
ARGVALUE4 : integer := 0;
ARGVALUE5 : integer := 0;
ARGVALUE6 : integer := 0;
ARGVALUE7 : integer := 0;
ARGVALUE8 : integer := 0;
ARGVALUE9 : integer := 0;
ARGVALUE10 : integer := 0;
ARGVALUE11 : integer := 0;
ARGVALUE12 : integer := 0;
ARGVALUE13 : integer := 0;
ARGVALUE14 : integer := 0;
ARGVALUE15 : integer := 0;
ARGVALUE16 : integer := 0;
ARGVALUE17 : integer := 0;
ARGVALUE18 : integer := 0;
ARGVALUE19 : integer := 0;
ARGVALUE20 : integer := 0;
ARGVALUE21 : integer := 0;
ARGVALUE22 : integer := 0;
ARGVALUE23 : integer := 0;
ARGVALUE24 : integer := 0;
ARGVALUE25 : integer := 0;
ARGVALUE26 : integer := 0;
ARGVALUE27 : integer := 0;
ARGVALUE28 : integer := 0;
ARGVALUE29 : integer := 0;
ARGVALUE30 : integer := 0;
ARGVALUE31 : integer := 0;
ARGVALUE32 : integer := 0;
ARGVALUE33 : integer := 0;
ARGVALUE34 : integer := 0;
ARGVALUE35 : integer := 0;
ARGVALUE36 : integer := 0;
ARGVALUE37 : integer := 0;
ARGVALUE38 : integer := 0;
ARGVALUE39 : integer := 0;
ARGVALUE40 : integer := 0;
ARGVALUE41 : integer := 0;
ARGVALUE42 : integer := 0;
ARGVALUE43 : integer := 0;
ARGVALUE44 : integer := 0;
ARGVALUE45 : integer := 0;
ARGVALUE46 : integer := 0;
ARGVALUE47 : integer := 0;
ARGVALUE48 : integer := 0;
ARGVALUE49 : integer := 0;
ARGVALUE50 : integer := 0;
ARGVALUE51 : integer := 0;
ARGVALUE52 : integer := 0;
ARGVALUE53 : integer := 0;
ARGVALUE54 : integer := 0;
ARGVALUE55 : integer := 0;
ARGVALUE56 : integer := 0;
ARGVALUE57 : integer := 0;
ARGVALUE58 : integer := 0;
ARGVALUE59 : integer := 0;
ARGVALUE60 : integer := 0;
ARGVALUE61 : integer := 0;
ARGVALUE62 : integer := 0;
ARGVALUE63 : integer := 0;
ARGVALUE64 : integer := 0;
ARGVALUE65 : integer := 0;
ARGVALUE66 : integer := 0;
ARGVALUE67 : integer := 0;
ARGVALUE68 : integer := 0;
ARGVALUE69 : integer := 0;
ARGVALUE70 : integer := 0;
ARGVALUE71 : integer := 0;
ARGVALUE72 : integer := 0;
ARGVALUE73 : integer := 0;
ARGVALUE74 : integer := 0;
ARGVALUE75 : integer := 0;
ARGVALUE76 : integer := 0;
ARGVALUE77 : integer := 0;
ARGVALUE78 : integer := 0;
ARGVALUE79 : integer := 0;
ARGVALUE80 : integer := 0;
ARGVALUE81 : integer := 0;
ARGVALUE82 : integer := 0;
ARGVALUE83 : integer := 0;
ARGVALUE84 : integer := 0;
ARGVALUE85 : integer := 0;
ARGVALUE86 : integer := 0;
ARGVALUE87 : integer := 0;
ARGVALUE88 : integer := 0;
ARGVALUE89 : integer := 0;
ARGVALUE90 : integer := 0;
ARGVALUE91 : integer := 0;
ARGVALUE92 : integer := 0;
ARGVALUE93 : integer := 0;
ARGVALUE94 : integer := 0;
ARGVALUE95 : integer := 0;
ARGVALUE96 : integer := 0;
ARGVALUE97 : integer := 0;
ARGVALUE98 : integer := 0;
ARGVALUE99 : integer := 0;
ZEROLV : vl_logic_vector(31 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
ZERO256 : vl_logic_vector(255 downto 0) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0);
idle : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
init : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1);
active : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0);
done : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi1);
fill : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi0);
scan : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1)
);
port(
SYSCLK : in vl_logic;
SYSRSTN : in vl_logic;
PCLK : out vl_logic;
HCLK : out vl_logic;
HRESETN : out vl_logic;
HADDR : out vl_logic_vector(31 downto 0);
HBURST : out vl_logic_vector(2 downto 0);
HMASTLOCK : out vl_logic;
HPROT : out vl_logic_vector(3 downto 0);
HSIZE : out vl_logic_vector(2 downto 0);
HTRANS : out vl_logic_vector(1 downto 0);
HWRITE : out vl_logic;
HWDATA : out vl_logic_vector(31 downto 0);
HRDATA : in vl_logic_vector(31 downto 0);
HREADY : in vl_logic;
HRESP : in vl_logic;
HSEL : out vl_logic_vector(15 downto 0);
INTERRUPT : in vl_logic_vector(255 downto 0);
GP_OUT : out vl_logic_vector(31 downto 0);
GP_IN : in vl_logic_vector(31 downto 0);
EXT_WR : out vl_logic;
EXT_RD : out vl_logic;
EXT_ADDR : out vl_logic_vector(31 downto 0);
EXT_DATA : inout vl_logic_vector(31 downto 0);
EXT_WAIT : in vl_logic;
CON_ADDR : in vl_logic_vector(15 downto 0);
CON_DATA : inout vl_logic_vector(31 downto 0);
CON_RD : in vl_logic;
CON_WR : in vl_logic;
CON_BUSY : out vl_logic;
INSTR_OUT : out vl_logic_vector(31 downto 0);
INSTR_IN : in vl_logic_vector(31 downto 0);
FINISHED : out vl_logic;
FAILED : out vl_logic
);
attribute ZEROLV_mti_vect_attrib : integer;
attribute ZEROLV_mti_vect_attrib of ZEROLV : constant is 0;
attribute ZERO256_mti_vect_attrib : integer;
attribute ZERO256_mti_vect_attrib of ZERO256 : constant is 0;
attribute idle_mti_vect_attrib : integer;
attribute idle_mti_vect_attrib of idle : constant is 0;
attribute init_mti_vect_attrib : integer;
attribute init_mti_vect_attrib of init : constant is 1;
attribute active_mti_vect_attrib : integer;
attribute active_mti_vect_attrib of active : constant is 2;
attribute done_mti_vect_attrib : integer;
attribute done_mti_vect_attrib of done : constant is 3;
attribute fill_mti_vect_attrib : integer;
attribute fill_mti_vect_attrib of fill : constant is 4;
attribute scan_mti_vect_attrib : integer;
attribute scan_mti_vect_attrib of scan : constant is 5;
end BFM_MAIN;
|
gpl-3.0
|
092ed71a3729134d332c17e7de3902ce
| 0.499288 | 3.301375 | false | false | false | false |
dsd-g05/lab5
|
g05_score_encoder.vhd
| 1 | 1,611 |
-- Descp. Encode the score of the Mastermind game in a 4 bit number #### => (num_exact, num_color_matches)
--0000 (4,0)
--0001 (3,0)
--0010 (2,0)
--0011 (2,1)
--0100 (2,2)
--0101 (1,0)
--0110 (1,1)
--0111 (1,2)
--1000 (1,3)
--1001 (0,0)
--1010 (0,1)
--1011 (0,2)
--1100 (0,3)
--1101 (0,4)
--
--
-- entity name: g05_score_encoder
--
-- Version 1.0
-- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected]
-- Date: October 18, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_score_encoder is
port (
score_code : out std_logic_vector(3 downto 0);
num_exact_matches : in std_logic_vector(2 downto 0);
num_color_matches : in std_logic_vector(2 downto 0)
);
end g05_score_encoder;
architecture behavior of g05_score_encoder is
signal score : std_logic_vector(5 downto 0);
begin
score <= num_exact_matches&num_color_matches;
process(score)
begin
case score is
when "100000" =>
score_code <= "0000";
when "011000" =>
score_code <= "0001";
when "010000" =>
score_code <= "0010";
when "010001" =>
score_code <= "0011";
when "010010" =>
score_code <= "0100";
when "001000" =>
score_code <= "0101";
when "001001" =>
score_code <= "0110";
when "001010" =>
score_code <= "0111";
when "001011" =>
score_code <= "1000";
when "000000" =>
score_code <= "1001";
when "000001" =>
score_code <= "1010";
when "000010" =>
score_code <= "1011";
when "000011" =>
score_code <= "1100";
when others =>
score_code <= "1101";
end case;
end process;
end behavior;
|
mit
|
a3ad5dad7c853ccee65fcb02a6048292
| 0.599007 | 2.716695 | false | false | false | false |
6769/VHDL
|
Lab_5/__FromSaru/lab50/decoder_1_6.vhd
| 1 | 741 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY decoder_1_6 IS
PORT(
m:IN STD_LOGIC_vector(3 downto 0);
led_vector:out bit_vector(7 DOWNTO 0));
END decoder_1_6;
ARCHITECTURE decoder_architecture OF decoder_1_6 IS
BEGIN
PROCESS(m)
BEGIN
CASE m IS
WHEN "0001" => led_vector<="11111001";--F9=>1
WHEN "0010" => led_vector<="10100100";--A4=>2
WHEN "0011" => led_vector<="10110000";--B0=>3
WHEN "0100" => led_vector<="10011001";--99=>4
WHEN "0101" => led_vector<="10010010";--92=>5
WHEN "0110" => led_vector<="10000010";--82=>6
WHEN others => led_vector<="11111111";--FF=>²»ÁÁ
END CASE;
END PROCESS;
END decoder_architecture;
|
gpl-2.0
|
643e2c292d46901651abec9642737d9f
| 0.612686 | 3.308036 | false | false | false | false |
6769/VHDL
|
Lab_3/Part1/__report_sum_up_Part2.vhd
| 1 | 3,373 |
--------------------------------------------------------------
------------------------------------------------------------
-- FSM_core.vhd
------------------------------------------------------------
--------------------------------------------------------------
--lab3-Part1
--FSM with 0-8 state
entity FSM_core is
port(X:in bit;
CLK:in bit;
reset:in bit;
stateout:out integer range 0 to 8;
Z:out bit);
end entity FSM_core;
architecture Behavior of FSM_core is
signal State,nextState:integer range 0 to 8;
begin
stateout<=state;
process(X,State)
begin
case State is
when 0=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=1;
end if;
when 1=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=2;
end if;
when 2=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=3;
end if;
when 3=>
Z<='0';
if X='0' then nextState<=5;
else nextState<=4;
end if;
when 4=>
Z<='1';
if X='0' then nextState<=5;
else nextState<=4;
end if;
when 5=>
Z<='0';
if X='0' then nextState<=6;
else nextState<=1;
end if;
when 6=>
Z<='0';
if X='0' then nextState<=7;
else nextState<=1;
end if;
when 7=>
Z<='0';
if X='0' then nextState<=8;
else nextState<=1;
end if;
when 8=>
Z<='1';
if X='0' then nextState<=8;
else nextState<=1;
end if;
when others=>null;
end case;
end process;
--nextStateRegister
process(CLK,reset)
begin
if reset='0' then State<=0;
elsif CLK'event and CLK='1' then
State<=nextState;
end if;
end process;
end architecture Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- View_input.vhd
------------------------------------------------------------
--------------------------------------------------------------
entity View_input is
port (reset:in bit;
w: in bit;
clk:in bit;
z: out bit;
state8_0:out bit_vector(8 downto 0));--LED Red for showing State table
end entity View_input;
architecture match of View_input is
component FSM_core
port(
X: in bit;
CLK: in bit;
reset:in bit;
stateout:out integer range 0 to 8;
Z: out bit);
end component;
signal stateout:integer range 0 to 8;
begin
lable_1:fsm_core port map(w,clk,reset,stateout,z);
with stateout select --mux choice
state8_0 <= "000000001" when 0,
"000000010" when 1,
"000000100" when 2,
"000001000" when 3,
"000010000" when 4,
"000100000" when 5,
"001000000" when 6,
"010000000" when 7,
"100000000" when 8;
end architecture match;
|
gpl-2.0
|
768991ba88486ee88f43ffe6a1fa4c21
| 0.387192 | 4.515395 | false | false | false | false |
6769/VHDL
|
Lab_5/Controller.vhd
| 1 | 1,090 |
entity Controller is
port(
Rb,Reset, Eq,D7,D711,D2312,CLK:in bit;
State_debug:out integer range 0 to 3;
Sp,Roll,Win,Lose,Clear:out bit:='0');
end entity Controller;
architecture Behavior of Controller is
signal State,NextState:integer range 0 to 3:=0;
begin
State_debug<=State;
process(Rb,Reset,State)
begin
if( Rb='1' or Reset='1' ) then
--Roll<=Rb;
case State is
when 0 =>
if(D711='1')then Win<='1';NextState<=2;
elsif(D2312='1') then Lose<='1';NextState<=3;
else NextState<=1;Sp<='1';
end if;
when 2=>
if(Reset='1') then Win<='0';Lose<='0';NextState<=0;Sp<='0';--Clear<='1';
end if;
when 3=>
if(Reset='1') then Lose<='0';Win<='0';NextState<=0;Sp<='0';--Clear<='1';
end if;
when 1=>
if(Eq='1')then Win<='1' ;NextState<=2;
elsif(D7='1')then Lose<='1';NextState<=3;
end if;
end case;
end if;
end process;
Roll<=Rb;
Clear<='1' when Reset='1' and (State=2 or State=3) else '0';
process(CLK)
begin
if CLK'event and CLK = '1' then
State <= NextState;
end if;
end process;
end architecture Behavior;
|
gpl-2.0
|
81790afa66800c211dcb2ceb378f0a26
| 0.612844 | 2.678133 | false | false | false | false |
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/cache.vhd
| 12 | 6,290 |
---------------------------------------------------------------------
-- TITLE: Cache Controller
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 12/22/08
-- FILENAME: cache.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Control 4KB unified cache that uses the upper 4KB of the 8KB
-- internal RAM. Only lowest 2MB of DDR is cached.
-- Only include file for Xilinx FPGAs.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
use work.mlite_pack.all;
entity cache is
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end; --cache
architecture logic of cache is
subtype state_type is std_logic_vector(1 downto 0);
constant STATE_IDLE : state_type := "00";
constant STATE_CHECKING : state_type := "01";
constant STATE_MISSED : state_type := "10";
constant STATE_WAITING : state_type := "11";
signal state_reg : state_type;
signal state : state_type;
signal state_next : state_type;
signal cache_address : std_logic_vector(10 downto 0);
signal cache_tag_in : std_logic_vector(8 downto 0);
signal cache_tag_reg : std_logic_vector(8 downto 0);
signal cache_tag_out : std_logic_vector(8 downto 0);
signal cache_we : std_logic;
begin
cache_proc: process(clk, reset, mem_busy, cache_address,
state_reg, state, state_next,
address_next, byte_we_next, cache_tag_in, --Stage1
cache_tag_reg, cache_tag_out, --Stage2
cpu_address) --Stage3
begin
case state_reg is
when STATE_IDLE => --cache idle
cache_checking <= '0';
cache_miss <= '0';
state <= STATE_IDLE;
when STATE_CHECKING => --current read in cached range, check if match
cache_checking <= '1';
if cache_tag_out /= cache_tag_reg or cache_tag_out = ONES(8 downto 0) then
cache_miss <= '1';
state <= STATE_MISSED;
else
cache_miss <= '0';
state <= STATE_IDLE;
end if;
when STATE_MISSED => --current read cache miss
cache_checking <= '0';
cache_miss <= '1';
if mem_busy = '1' then
state <= STATE_MISSED;
else
state <= STATE_WAITING;
end if;
when STATE_WAITING => --waiting for memory access to complete
cache_checking <= '0';
cache_miss <= '0';
if mem_busy = '1' then
state <= STATE_WAITING;
else
state <= STATE_IDLE;
end if;
when others =>
cache_checking <= '0';
cache_miss <= '0';
state <= STATE_IDLE;
end case; --state
if state = STATE_IDLE then --check if next access in cached range
cache_address <= '0' & address_next(11 downto 2);
if address_next(30 downto 21) = "0010000000" then --first 2MB of DDR
cache_access <= '1';
if byte_we_next = "0000" then --read cycle
cache_we <= '0';
state_next <= STATE_CHECKING; --need to check if match
else
cache_we <= '1'; --update cache tag
state_next <= STATE_WAITING;
end if;
else
cache_access <= '0';
cache_we <= '0';
state_next <= STATE_IDLE;
end if;
else
cache_address <= '0' & cpu_address(11 downto 2);
cache_access <= '0';
if state = STATE_MISSED then
cache_we <= '1'; --update cache tag
else
cache_we <= '0';
end if;
state_next <= state;
end if;
if byte_we_next = "0000" or byte_we_next = "1111" then --read or 32-bit write
cache_tag_in <= address_next(20 downto 12);
else
cache_tag_in <= ONES(8 downto 0); --invalid tag
end if;
if reset = '1' then
state_reg <= STATE_IDLE;
cache_tag_reg <= ZERO(8 downto 0);
elsif rising_edge(clk) then
state_reg <= state_next;
if state = STATE_IDLE and state_reg /= STATE_MISSED then
cache_tag_reg <= cache_tag_in;
end if;
end if;
end process;
-- cache_xilinx: if memory_type = "XILINX_16X" generate
-- begin
-- cache_tag: RAMB16_S9 --Xilinx specific
-- port map (
-- DO => cache_tag_out(7 downto 0),
-- DOP => cache_tag_out(8 downto 8),
-- ADDR => cache_address, --registered
-- CLK => clk,
-- DI => cache_tag_in(7 downto 0), --registered
-- DIP => cache_tag_in(8 downto 8),
-- EN => '1',
-- SSR => ZERO(0),
-- WE => cache_we);
-- end generate; --cache_xilinx
cache_generic: if memory_type /= "XILINX_16X" generate
begin
cache_tag: process(clk, cache_address, cache_tag_in, cache_we)
constant ADDRESS_WIDTH : natural := 10;
type storage_array is
array(natural range 0 to 2 ** ADDRESS_WIDTH - 1) of
std_logic_vector(8 downto 0);
variable storage : storage_array;
variable index : natural := 0;
begin
if rising_edge(clk) then
index := conv_integer(cache_address(ADDRESS_WIDTH-1 downto 0));
if cache_we = '1' then
storage(index) := cache_tag_in;
end if;
cache_tag_out <= storage(index);
end if;
end process; --cache_tag
end generate; --cache_generic
end; --logic
|
gpl-3.0
|
33b2c046d9eaae0eecfc635bbf9197e5
| 0.530048 | 3.823708 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/qspi_startup_block.vhd
| 1 | 16,675 |
-------------------------------------------------------------------------------
-- $Id: qqspi_startup_block.vhd
-------------------------------------------------------------------------------
-- qspi_startup_block.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_startup_block.vhd
-- Version: v3.0
-- Description: This module uses the STARTUP primitive based upon the generic.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- Soft_Reset_op signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Author: SK
-- ~~~~~~
-- - Designed version of axi_quad_spi.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library unisim;
--use unisim.vcomponents.STARTUP_SPARTAN6;
--use unisim.vcomponents.STARTUP_VIRTEX6;
use unisim.vcomponents.STARTUPE2; -- for 7-series FPGA's
use unisim.vcomponents.STARTUPE3; -- for 8 series FPGA's
------------------------------
entity qspi_startup_block is
generic
(
C_SUB_FAMILY : string ;
---------------------
C_USE_STARTUP : integer ;
---------------------
C_SPI_MODE : integer
---------------------
);
port
(
SCK_O : in std_logic; -- input from the spi_mode_0_module
IO1_I_startup : in std_logic; -- input from the top level port list
IO1_Int : out std_logic;
Bus2IP_Clk : in std_logic;
reset2ip_reset : in std_logic
);
end entity qspi_startup_block;
------------------------------
architecture imp of qspi_startup_block is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- 19-11-2012 added below parameter and signals to fix the CR #679609
constant ADD_PIPELINTE : integer := 8;
signal pipe_signal : std_logic_vector(ADD_PIPELINTE-1 downto 0);
signal PREQ_int : std_logic;
signal PACK_int : std_logic;
-----
begin
-----
PREQ_REG_P:process(Bus2IP_Clk)is -- 19-11-2012
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset = '1')then
pipe_signal(0) <= '0';
elsif(PREQ_int = '1')then
pipe_signal(0) <= '1';
end if;
end if;
end process PREQ_REG_P;
PIPE_PACK_P:process(Bus2IP_Clk)is -- 19-11-2012
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset = '1')then
pipe_signal(ADD_PIPELINTE-1 downto 1) <= (others => '0');
else
pipe_signal(1) <= pipe_signal(0);
pipe_signal(2) <= pipe_signal(1);
pipe_signal(3) <= pipe_signal(2);
pipe_signal(4) <= pipe_signal(3);
pipe_signal(5) <= pipe_signal(4);
pipe_signal(6) <= pipe_signal(5);
pipe_signal(7) <= pipe_signal(6);
-- pipe_signal(8) <= pipe_signal(7);
end if;
end if;
end process PIPE_PACK_P;
PACK_int <= pipe_signal(7); -- 19-11-2012
-- STARTUP_7SERIES_GEN: Logic instantiation of STARTUP primitive in the core.
STARTUP_7SERIES_GEN: if ( -- In 7-series, the start up is allowed in all C_SPI_MODE values.
C_SUB_FAMILY = "virtex7" or
C_SUB_FAMILY = "kintex7" or
C_SUB_FAMILY = "artix7"
) and C_USE_STARTUP = 1 generate
-----
begin
-----
ASSERT (
( -- no check for C_SPI_MODE is needed here. On S6 the startup is not supported.
-- (C_SUB_FAMILY = "virtex6") or
(C_SUB_FAMILY = "virtex7") or
(C_SUB_FAMILY = "kintex7") or
(C_SUB_FAMILY = "artix7")
)and
(C_USE_STARTUP = 1)
)
REPORT "*** The use of STARTUP primitive is not supported on this targeted device. ***"
SEVERITY error;
-------------------
IO1_Int <= IO1_I_startup;
-------------------
STARTUP2_7SERIES_inst : component STARTUPE2
-----------------------
generic map
(
PROG_USR => "FALSE", -- Activate program event security feature.
SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map
(
USRCCLKO => SCK_O, -- SRCCLKO , -- 1-bit input: User CCLK input
----------
CFGCLK => open, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => open, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- REQ , -- 1-bit output: PROGRAM request to fabric output
----------
CLK => '0', -- LK , -- 1-bit input: User start-up clock input
GSR => '0', -- SR , -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- TS , -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- EYCLEARB , -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => PACK_int, -- '1', -- ACK , -- 1-bit input: PROGRAM acknowledge input
USRCCLKTS => '0', -- SRCCLKTS , -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- SRDONEO , -- 1-bit input: User DONE pin output control
USRDONETS => '1' -- SRDONETS -- 1-bit input: User DONE 3-state enable output
);
end generate STARTUP_7SERIES_GEN;
---------------------------------
---STARTUP for 8 series STARTUPE3
---------------------------------
STARTUP_8SERIES_GEN: if ( -- In 8-series, the start up is allowed in all C_SPI_MODE values.
C_SUB_FAMILY = "virtex8" or
C_SUB_FAMILY = "kintex8" or
C_SUB_FAMILY = "artix8"
) and C_USE_STARTUP = 1 generate
-- -----
begin
-- -----
ASSERT (
(
(C_SUB_FAMILY = "virtex8") or
(C_SUB_FAMILY = "kintex8") or
(C_SUB_FAMILY = "artix8")
)and
(C_USE_STARTUP = 1)
)
REPORT "*** The use of STARTUP primitive is not supported on this targeted device. ***"
SEVERITY error;
-------------------
IO1_Int <= IO1_I_startup;
-------------------
STARTUP3_8SERIES_inst : component STARTUPE3
-----------------------
generic map
(
PROG_USR => "FALSE", -- Activate program event security feature.
SIM_CCLK_FREQ => 0.0 -- Set the Configuration Clock Frequency(ns) for simulation.
)
port map
(
USRCCLKO => SCK_O, -- SRCCLKO , -- 1-bit input: User CCLK input
----------
CFGCLK => open, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => open, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => open, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => open, -- REQ , -- 1-bit output: PROGRAM request to fabric output
----------
DO => "0000", -- input
DI => open, -- output
DTS => "0000", -- input
FCSBO => '0', -- input
FCSBTS => '0', -- input
GSR => '0', -- SR , -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
GTS => '0', -- TS , -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
KEYCLEARB => '0', -- EYCLEARB , -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
PACK => PACK_int, -- '1', -- ACK , -- 1-bit input: PROGRAM acknowledge input
USRCCLKTS => '0', -- SRCCLKTS , -- 1-bit input: User CCLK 3-state enable input
USRDONEO => '1', -- SRDONEO , -- 1-bit input: User DONE pin output control
USRDONETS => '1' -- SRDONETS -- 1-bit input: User DONE 3-state enable output
);
end generate STARTUP_8SERIES_GEN;
end architecture imp;
|
mit
|
2e7d3510161eb7bd6b2644d1357d83e6
| 0.448036 | 4.596196 | false | false | false | false |
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/FIFO_one_hot_credit_based_packet_drop_classifier_support.vhd
| 3 | 16,854 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
constant fake_tail : std_logic_vector := "10000000000000000000000000000001";
alias flit_type : std_logic_vector(2 downto 0) is RX(DATA_WIDTH-1 downto DATA_WIDTH-3);
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit, Packet_drop);
signal state_out, state_in : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0');
FIFO_MEM_2 <= (others=>'0');
FIFO_MEM_3 <= (others=>'0');
FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in;
FIFO_MEM_2 <= FIFO_MEM_2_in;
FIFO_MEM_3 <= FIFO_MEM_3_in;
FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
end if;
end process;
-- anything below here is pure combinational
-- combinatorial part
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
else
xor_all <= '0';
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, flit_type, valid_in)begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
--some defaults
fault_info <= '0';
health_info <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= Body_flit;
elsif flit_type ="100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "010" then
state_in <= state_out;
elsif flit_type = "100" then
state_in <= Tail_flit;
health_info <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if flit_type = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
if faulty_packet_out = '1' then
if valid_in = '1' and flit_type = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
end case ;
elsif valid_in = '1' and flit_type ="100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else
if valid_in = '1' and flit_type = "001" then
fault_info <= '1';
end if;
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
else
-- we should not be here!
state_in <= state_out;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when "1000" => Data_out <= FIFO_MEM_4;
when others => Data_out <= FIFO_MEM_1;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
else
write_pointer_in <= write_pointer;
end if;
end process;
process(read_en, empty, read_pointer)begin
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
else
read_pointer_in <= read_pointer;
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
else
write_en <= '0';
end if;
end process;
process(write_pointer, read_pointer) begin
if read_pointer = write_pointer then
empty <= '1';
else
empty <= '0';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
else
full <= '0';
end if;
end process;
end;
|
gpl-3.0
|
57a902b1091e4d7c3b891fa0c1c37cca
| 0.4075 | 3.676702 | false | false | false | false |
1995parham/FPGA-Homework
|
Project-Phase2/hw/FSM.vhd
| 1 | 3,898 |
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 13-05-2016
-- Module Name: FSM.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity FSM is
port (start_state : in std_logic_vector(3 downto 0);
end_state : out std_logic_vector(3 downto 0);
str : in std_logic_vector(31 downto 0);
enable, clk : in std_logic;
done : out std_logic);
end entity;
architecture rtl of FSM is
type state is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9);
signal current_state, next_state : state;
signal current_index, next_index : std_logic_vector(5 downto 0);
signal str_buff : std_logic_vector(31 downto 0);
begin
process(clk)
begin
if clk'event and clk = '1' then
if enable = '1' then
current_index <= "000000";
str_buff <= str;
case start_state is
when "0000" => current_state <= S0;
when "0001" => current_state <= S1;
when "0010" => current_state <= S2;
when "0011" => current_state <= S3;
when "0100" => current_state <= S4;
when "0101" => current_state <= S5;
when "0110" => current_state <= S6;
when "0111" => current_state <= S7;
when "1000" => current_state <= S8;
when "1001" => current_state <= S9;
when others => current_state <= S0;
end case;
else
current_state <= next_state;
current_index <= next_index;
end if;
end if;
end process;
process(current_state)
begin
if current_index = "100000" then
done <= '1';
else
done <= '1';
end if;
case current_state is
when S0 => end_state <= "0000";
when S1 => end_state <= "0001";
when S2 => end_state <= "0010";
when S3 => end_state <= "0011";
when S4 => end_state <= "0100";
when S5 => end_state <= "0101";
when S6 => end_state <= "0110";
when S7 => end_state <= "0111";
when S8 => end_state <= "1000";
when S9 => end_state <= "1001";
when others => end_state <= "0000";
end case;
end process;
process(current_state)
begin
if current_index = "100000" then
next_state <= current_state;
next_index <= "000000";
else
case current_state is
when S0 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S5;
else
next_state <= S1;
end if;
when S1 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S2;
else
next_state <= S7;
end if;
when S2 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S8;
else
next_state <= S3;
end if;
when S3 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S0;
else
next_state <= S7;
end if;
when S4 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S4;
else
next_state <= S9;
end if;
when S5 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S0;
else
next_state <= S6;
end if;
when S6 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S1;
else
next_state <= S7;
end if;
when S7 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S9;
else
next_state <= S2;
end if;
when S8 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S4;
else
next_state <= S3;
end if;
when S9 =>
if str(to_integer(unsigned(current_index))) = '1' then
next_state <= S3;
else
next_state <= S8;
end if;
when others =>
next_state <= S0;
end case;
next_index <= current_index + "000001";
end if;
end process;
end architecture;
|
gpl-3.0
|
4f70461b58c4cdac5224b1000e3469e2
| 0.550026 | 2.939668 | false | false | false | false |
frankvanbever/MIPS_processor
|
programcounter.vhd
| 1 | 2,001 |
-------------------------------------------------------------------------------
-- Title : program counter
-- Project :
-------------------------------------------------------------------------------
-- File : programcounter.vhd
-- Author : Frank Vanbever <frank@neuromancer>
-- Company :
-- Created : 2013-02-13
-- Last update: 2013-02-13
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: program counter for a MIPS processor
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-13 1.0 frank Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pc is
port (
clk : in std_logic;
reset : in std_logic;
PC_in : in std_logic_vector(31 downto 0);
PC_out : out std_logic_vector(31 downto 0));
end pc;
architecture behavioral of pc is
signal PC_reset : std_logic;
begin -- behavioral
-----------------------------------------------------------------------------
setPCd : process (clk, PC_in, PC_reset)
begin -- process setPCd
if rising_edge(clk) then
if PC_reset = '1' then
PC_out <= (others => '0');
else
PC_out <= PC_in;
end if;
end if;
end process setPCd;
-------------------------------------------------------------------------------
resetPC : process (clk, reset)
begin -- process resetPC
if reset = '1' then -- asynchronous reset
PC_reset <= '1';
elsif (rising_edge(clk)) and (reset = '0') then -- rising clock edge
PC_reset <= '0';
end if;
end process resetPC;
end behavioral;
|
mit
|
d024bb66ea4a0092888a4bf4a1cbf0b5
| 0.403798 | 4.631944 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/VHDL_Xilinx_Port/sha256_transform.vhd
| 4 | 3,516 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:05 05/28/2011
-- Design Name:
-- Module Name: sha256_transform - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_transform is
Port ( clk : in STD_LOGIC;
w_in : in STD_LOGIC_VECTOR (511 downto 0);
w_out : out STD_LOGIC_VECTOR (511 downto 0);
s_in : in STD_LOGIC_VECTOR (255 downto 0);
s_out : out STD_LOGIC_VECTOR (255 downto 0);
k : std_logic_vector(31 downto 0));
end sha256_transform;
architecture Behavioral of sha256_transform is
COMPONENT sha256_e0
PORT(
d : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT sha256_e1
PORT(
d : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT sha256_ch
PORT(
x : IN std_logic_vector(31 downto 0);
y : IN std_logic_vector(31 downto 0);
z : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT sha256_maj
PORT(
x : IN std_logic_vector(31 downto 0);
y : IN std_logic_vector(31 downto 0);
z : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT sha256_s0
PORT(
d : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
COMPONENT sha256_s1
PORT(
d : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
signal e0 : std_logic_vector(31 downto 0);
signal e1 : std_logic_vector(31 downto 0);
signal ch : std_logic_vector(31 downto 0);
signal maj : std_logic_vector(31 downto 0);
signal s0 : std_logic_vector(31 downto 0);
signal s1 : std_logic_vector(31 downto 0);
signal t : std_logic_vector(31 downto 0);
begin
calc_e0: sha256_e0
port map (
d => s_in(31 downto 0),
q => e0
);
calc_e1: sha256_e1
port map (
d => s_in(159 downto 128),
q => e1
);
calc_ch: sha256_ch
port map (
x => s_in(159 downto 128),
y => s_in(191 downto 160),
z => s_in(223 downto 192),
q => ch
);
calc_maj: sha256_maj
port map (
x => s_in(31 downto 0),
y => s_in(63 downto 32),
z => s_in(95 downto 64),
q => maj
);
calc_s0: sha256_s0
port map (
d => w_in(63 downto 32),
q => s0
);
calc_s1: sha256_s1
port map (
d => w_in(479 downto 448),
q => s1
);
t <= s_in(255 downto 224) + e1 + ch + w_in(31 downto 0) + k;
process(clk)
begin
if rising_edge(clk) then
w_out(511 downto 480) <= s1 + w_in(319 downto 288) + s0 + w_in(31 downto 0);
w_out(479 downto 0) <= w_in(511 downto 32);
s_out(255 downto 160) <= s_in(223 downto 128);
s_out(159 downto 128) <= s_in(127 downto 96) + t;
s_out(127 downto 32) <= s_in(95 downto 0);
s_out(31 downto 0) <= t + e0 + maj;
end if;
end process;
end Behavioral;
|
gpl-3.0
|
0fb8e3f5ce63d4b5efffbcfa83697d65
| 0.583333 | 2.858537 | false | false | false | false |
frankvanbever/MIPS_processor
|
testbenches/PCAdder_tb.vhd
| 1 | 2,411 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:41:51 02/20/2013
-- Design Name:
-- Module Name: /home/frank/testproject/PCAdder_tb.vhd
-- Project Name: testproject
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: PCA
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY PCAdder_tb IS
END PCAdder_tb;
ARCHITECTURE behavior OF PCAdder_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PCA
PORT(
PC : IN std_logic_vector(31 downto 0);
PC4 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
signal clk : std_logic;
--Inputs
signal PC : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal PC4 : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace clk below with
-- appropriate port name
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PCA PORT MAP (
PC => PC,
PC4 => PC4
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
PC <= X"00000000";
wait for clk_period;
PC <= PC4;
wait for clk_period;
PC <= PC4;
wait for clk_period;
PC <= PC4;
wait for clk_period;
PC <= PC4;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
717cda8eee1332dae3ecd57064853a0b
| 0.603069 | 3.767188 | false | true | false | false |
sunoc/vhdl-lz4-variation
|
z_old/sha1/sha_pre_proc.vhd
| 1 | 34,243 |
-----------------------------------------------------------------------------------
--! @file sha_pre_proc.vhd
--! @brief SHA-1/2 Pre Processing Module :
--! SHA-1/2用プリプロセッシングモジュール.
--! @version 0.9.0
--! @date 2012/11/20
--! @author Ichiro Kawazome <[email protected]>
-----------------------------------------------------------------------------------
--
-- Copyright (C) 2012 Ichiro Kawazome
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------------
--! @brief SHA_PRE_PROC :
--! SHA-1/2用プリプロセッシングモジュール.
--! ブロック単位でのパディング、入力ビット数の付加等の処理を行う.
-----------------------------------------------------------------------------------
entity SHA_PRE_PROC is
generic (
WORD_BITS : --! @brief SHA-1/2 WORD BITS :
--! １ワードのビット数を指定する.
--! * SHA-1/SHA-256の場合は32を設定する.
--! * SHA-512の場合は64を設定する.
integer := 32;
WORDS : --! @brief SHA-1/2 WORD SIZE :
--! １クロックで処理するワード数を指定する.
integer := 1;
SYMBOL_BITS : --! @brief INPUT SYMBOL BITS :
--! 入力データの１シンボルのビット数を指定する.
integer := 8;
SYMBOLS : --! @brief INPUT SYMBOL SIZE :
--! 入力データのシンボル数を指定する.
integer := 4;
REVERSE : --! @brief INPUT SYMBOL REVERSE :
--! 入力データのシンボルのビット並びを逆にするかどうかを指定する.
integer := 1
);
port (
-------------------------------------------------------------------------------
-- クロック&リセット信号
-------------------------------------------------------------------------------
CLK : --! @brief CLOCK :
--! クロック信号
in std_logic;
RST : --! @brief ASYNCRONOUSE RESET :
--! 非同期リセット信号.アクティブハイ.
in std_logic;
CLR : --! @brief SYNCRONOUSE RESET :
--! 同期リセット信号.アクティブハイ.
in std_logic;
-------------------------------------------------------------------------------
-- 入力側 I/F
-------------------------------------------------------------------------------
I_DATA : --! @brief INPUT SYMBOL DATA :
in std_logic_vector(SYMBOL_BITS*SYMBOLS-1 downto 0);
I_ENA : --! @brief INPUT SYMBOL DATA ENABLE :
in std_logic_vector( SYMBOLS-1 downto 0);
I_DONE : --! @brief INPUT SYMBOL DATA DONE :
in std_logic;
I_LAST : --! @brief INPUT SYMBOL DATA LAST :
in std_logic;
I_VAL : --! @brief INPUT SYMBOL DATA VALID :
in std_logic;
I_RDY : --! @brief INPUT SYMBOL DATA READY :
out std_logic;
-------------------------------------------------------------------------------
-- 出力側 I/F
-------------------------------------------------------------------------------
M_DATA : --! @brief OUTPUT MESSAGE DATA :
out std_logic_vector(WORD_BITS*WORDS-1 downto 0);
M_DONE : --! @brief OUTPUT MESSAGE DONE :
out std_logic;
M_VAL : --! @brief OUTPUT MESSAGE VALID :
out std_logic;
M_RDY : --! @brief OUTPUE MESSAGE READY :
in std_logic
);
end SHA_PRE_PROC;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture RTL of SHA_PRE_PROC is
-------------------------------------------------------------------------------
-- １ブロックのビット数
-------------------------------------------------------------------------------
constant BLOCK_BITS : integer := 16*WORD_BITS;
-------------------------------------------------------------------------------
-- 出力側ワードデータのビット数
-------------------------------------------------------------------------------
constant OUT_BITS : integer := WORD_BITS*WORDS;
-------------------------------------------------------------------------------
-- 出力側ワードデータのシンボルの数(出力側データの総ビット数をシンボルのビット数で割った値)
-------------------------------------------------------------------------------
constant OUT_SYMBOLS : integer := OUT_BITS/SYMBOL_BITS;
-------------------------------------------------------------------------------
-- IBUFの入力側の信号達
-------------------------------------------------------------------------------
signal in_symbol : std_logic_vector(SYMBOL_BITS*SYMBOLS-1 downto 0);
signal in_ready : std_logic;
constant in_flush : std_logic := '0';
-------------------------------------------------------------------------------
-- IBUFの制御信号達
-------------------------------------------------------------------------------
constant ibuf_start : std_logic := '0';
constant ibuf_flush : std_logic := '0';
constant ibuf_offset : std_logic_vector(OUT_SYMBOLS-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- IBUFの出力側の信号達
-------------------------------------------------------------------------------
signal ibuf_word_data : std_logic_vector(OUT_BITS -1 downto 0);
signal ibuf_word_valid : std_logic_vector(OUT_SYMBOLS-1 downto 0);
signal ibuf_done : std_logic;
signal ibuf_valid : std_logic;
signal ibuf_ready : std_logic;
-------------------------------------------------------------------------------
-- 入力したシンボルの総ビット数をカウントするカウンタ.
-------------------------------------------------------------------------------
signal symbol_size : std_logic_vector(2*WORD_BITS-1 downto 0);
-------------------------------------------------------------------------------
-- ステートマシンの型宣言.
-------------------------------------------------------------------------------
type STATE_TYPE is ( INPUT_STATE ,
PADDING_STATE,
LAST_STATE
);
-------------------------------------------------------------------------------
-- 各種内部状態信号.
-------------------------------------------------------------------------------
signal curr_state : STATE_TYPE;
signal next_state : STATE_TYPE;
signal curr_delimiter : std_logic_vector(0 downto 0);
signal next_delimiter : std_logic_vector(0 downto 0);
constant MAX_OUT_SIZE : integer := BLOCK_BITS/(OUT_BITS)-1;
signal remain_out_size : integer range 0 to MAX_OUT_SIZE;
-------------------------------------------------------------------------------
-- OBUFへの入力信号
-------------------------------------------------------------------------------
signal out_word_data : std_logic_vector(OUT_BITS-1 downto 0);
signal out_done : std_logic;
signal out_valid : std_logic;
signal out_ready : std_logic;
constant out_flush : std_logic := '0';
constant out_word_valid : std_logic_vector(WORDS-1 downto 0) := (others => '1');
-------------------------------------------------------------------------------
-- OBUFの制御信号達
-------------------------------------------------------------------------------
constant obuf_start : std_logic := '0';
constant obuf_done : std_logic := '0';
constant obuf_flush : std_logic := '0';
constant obuf_offset : std_logic_vector(WORDS-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
--! @brief ビットを逆順にする関数.
-------------------------------------------------------------------------------
function REVERSE_BIT(ARG:std_logic_vector) return std_logic_vector is
alias i_vec : std_logic_vector(0 to ARG'length-1) is ARG;
variable o_vec : std_logic_vector(ARG'length-1 downto 0);
begin
for i in o_vec'range loop
o_vec(i) := i_vec(i);
end loop;
return o_vec;
end function;
-------------------------------------------------------------------------------
-- REDUCERのコンポーネント宣言
-------------------------------------------------------------------------------
component REDUCER
generic (
WORD_BITS : integer := 8;
ENBL_BITS : integer := 1;
I_WIDTH : integer := 4;
O_WIDTH : integer := 4;
QUEUE_SIZE : integer := 0;
VALID_MIN : integer := 0;
VALID_MAX : integer := 0;
I_JUSTIFIED : integer := 0;
FLUSH_ENABLE: integer := 1
);
port (
CLK : in std_logic;
RST : in std_logic;
CLR : in std_logic;
START : in std_logic;
OFFSET : in std_logic_vector(O_WIDTH-1 downto 0);
DONE : in std_logic;
FLUSH : in std_logic;
BUSY : out std_logic;
VALID : out std_logic_vector(VALID_MAX downto VALID_MIN);
I_DATA : in std_logic_vector(I_WIDTH*WORD_BITS-1 downto 0);
I_ENBL : in std_logic_vector(I_WIDTH*ENBL_BITS-1 downto 0);
I_DONE : in std_logic;
I_FLUSH : in std_logic;
I_VAL : in std_logic;
I_RDY : out std_logic;
O_DATA : out std_logic_vector(O_WIDTH*WORD_BITS-1 downto 0);
O_ENBL : out std_logic_vector(O_WIDTH*ENBL_BITS-1 downto 0);
O_DONE : out std_logic;
O_FLUSH : out std_logic;
O_VAL : out std_logic;
O_RDY : in std_logic
);
end component;
begin
-------------------------------------------------------------------------------
-- リバースの場合はシンボル内でビットの並びを逆順にする.
-------------------------------------------------------------------------------
SYM_REVERSE : if (REVERSE > 0) generate
N_GEN: for i in 0 to SYMBOLS-1 generate
in_symbol(SYMBOL_BITS*(i+1)-1 downto SYMBOL_BITS*i) <=
REVERSE_BIT(I_DATA(SYMBOL_BITS*(i+1)-1 downto SYMBOL_BITS*i));
end generate;
end generate;
-------------------------------------------------------------------------------
-- ストレートの場合はシンボル内でビットの並びはそのまま.
-------------------------------------------------------------------------------
SYM_STRAIGHT: if (REVERSE = 0) generate
in_symbol <= I_DATA;
end generate;
-------------------------------------------------------------------------------
-- 入力バッファ.
-------------------------------------------------------------------------------
I_BUF: REDUCER
generic map (
WORD_BITS => SYMBOL_BITS , -- シンボルのビット数を指定.
ENBL_BITS => 1 , -- I_ENAはシンボル毎に1ビット.
I_WIDTH => SYMBOLS , -- 入力側のシンボル数.
O_WIDTH => OUT_SYMBOLS , -- 出力側のシンボル数.
QUEUE_SIZE => OUT_SYMBOLS+SYMBOLS -- キューのサイズ
+SYMBOLS-1 , --
VALID_MIN => ibuf_word_valid'low , -- ibuf_word_validの範囲の最小値.
VALID_MAX => ibuf_word_valid'high , -- ibuf_word_validの範囲の最大値.
I_JUSTIFIED => 0 , -- 入力シンボルはLSB側に詰められているわけではない.
FLUSH_ENABLE=> 0 -- FLUSHは未使用にする.
)
port map (
---------------------------------------------------------------------------
-- クロック&リセット信号
---------------------------------------------------------------------------
CLK => CLK , -- In : クロック.
RST => RST , -- In : 非同期リセット.
CLR => CLR , -- In : 同期リセット.
---------------------------------------------------------------------------
-- 各種制御信号
---------------------------------------------------------------------------
START => ibuf_start , -- In : 未使用のため'0'に固定.
OFFSET => ibuf_offset , -- In : 未使用のためALL'0'に固定.
DONE => I_DONE , -- In :
FLUSH => ibuf_flush , -- In : 未使用のため'0'に固定.
BUSY => open , -- Out : 未使用のためオープン.
VALID => ibuf_word_valid , -- Out :
---------------------------------------------------------------------------
-- 入力側 I/F
---------------------------------------------------------------------------
I_DATA => in_symbol , -- In : 入力データ.
I_ENBL => I_ENA , -- In :
I_DONE => I_LAST , -- In :
I_FLUSH => in_flush , -- In : 未使用のため'0'に固定.
I_VAL => I_VAL , -- In :
I_RDY => in_ready , -- Out :
---------------------------------------------------------------------------
-- 出力側 I/F
---------------------------------------------------------------------------
O_DATA => ibuf_word_data , -- Out : ワードデータ出力.
O_ENBL => open , -- Out : 未使用のためオープン.
O_DONE => ibuf_done , -- Out :
O_FLUSH => open , -- Out : 未使用のためオープン.
O_VAL => ibuf_valid , -- Out : ワードデータ有効信号.
O_RDY => ibuf_ready -- In : ワードデータ応答信号.
);
I_RDY <= in_ready when (curr_state = INPUT_STATE) else '0';
-------------------------------------------------------------------------------
-- 入力したシンボルの総ビット数をカウントするカウンタ.
-------------------------------------------------------------------------------
process (CLK, RST)
subtype SYMBOL_SIZE_TYPE is integer range 0 to SYMBOLS*SYMBOL_BITS;
subtype SYMBOL_COUNT_TYPE is integer range 0 to SYMBOLS;
function COUNT_BIT_1(ARG:std_logic_vector) return SYMBOL_COUNT_TYPE is
alias ENA : std_logic_vector(ARG'length-1 downto 0) is ARG;
begin
if (ENA'length = 1) then
if (ENA(0) = '1') then
return 1;
else
return 0;
end if;
else
return COUNT_BIT_1(ENA(ENA'high downto (ENA'high+1)/2))
+ COUNT_BIT_1(ENA((ENA'high+1)/2-1 downto ENA'low ));
end if;
end function;
variable in_size : SYMBOL_SIZE_TYPE;
begin
if (RST = '1') then
symbol_size <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (CLR = '1') or
(out_valid = '1' and out_ready = '1' and out_done = '1') then
symbol_size <= (others => '0');
elsif (I_VAL = '1' and in_ready = '1' and curr_state = INPUT_STATE) then
in_size := COUNT_BIT_1(I_ENA) * SYMBOL_BITS;
symbol_size <= std_logic_vector(unsigned(symbol_size) + in_size);
end if;
end if;
end process;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
process (curr_state, remain_out_size, curr_delimiter, symbol_size,
ibuf_word_valid, ibuf_word_data, ibuf_valid, ibuf_done)
variable prev_valid : boolean;
variable padding_done : boolean;
variable out_sym_size : boolean;
variable out_data : std_logic_vector(OUT_BITS-1 downto 0);
variable in_data : std_logic_vector(OUT_BITS-1 downto 0);
constant DELIMITER_SYMBOL : std_logic_vector(SYMBOL_BITS-1 downto 0) := (0 downto 0 => '1', others => '0');
constant PADDING_SYMBOL : std_logic_vector(SYMBOL_BITS-1 downto 0) := (others => '0');
begin
---------------------------------------------------------------------------
-- in_data : INPUT_STATE時に出力するワードデータ.
-- prev_valid : ワードデータがすべて有効であることを示す.
-- padding_done : パディング済みであることを示すフラグ.
---------------------------------------------------------------------------
if (ibuf_done = '1') then
prev_valid := TRUE;
padding_done := FALSE;
out_sym_size := FALSE;
for i in ibuf_word_valid'low to ibuf_word_valid'high loop
if (ibuf_word_valid(i) = '1') then
in_data(SYMBOL_BITS*(i+1)-1 downto SYMBOL_BITS*i) :=
ibuf_word_data(SYMBOL_BITS*(i+1)-1 downto SYMBOL_BITS*i);
prev_valid := TRUE;
padding_done := FALSE;
elsif (prev_valid and SYMBOL_BITS > 1) then
in_data(SYMBOL_BITS*(i+1)-1 downto SYMBOL_BITS*i) := DELIMITER_SYMBOL;
prev_valid := FALSE;
padding_done := TRUE;
elsif (prev_valid and SYMBOL_BITS = 1) then
in_data(SYMBOL_BITS*(i+1)-1 downto SYMBOL_BITS*i) := DELIMITER_SYMBOL;
prev_valid := FALSE;
padding_done := FALSE;
else
in_data(SYMBOL_BITS*(i+1)-1 downto SYMBOL_BITS*i) := PADDING_SYMBOL;
prev_valid := FALSE;
padding_done := TRUE;
end if;
if (WORDS > 2 and padding_done and ibuf_word_valid(i) = '0' and
ibuf_word_valid'high - i >= symbol_size'length/SYMBOL_BITS) then
out_sym_size := TRUE;
end if;
end loop;
else
in_data := ibuf_word_data;
prev_valid := TRUE;
padding_done := FALSE;
out_sym_size := FALSE;
end if;
---------------------------------------------------------------------------
-- next_delimiter :
---------------------------------------------------------------------------
if (curr_state = INPUT_STATE and ibuf_done = '1' and prev_valid and SYMBOL_BITS > 0) then
next_delimiter <= "1";
else
next_delimiter <= "0";
end if;
---------------------------------------------------------------------------
-- 出力側のワード数が１ワードの場合.
---------------------------------------------------------------------------
if (WORDS = 1) then
case curr_state is
when INPUT_STATE =>
out_data := in_data;
out_done <= '0';
out_valid <= ibuf_valid;
if (ibuf_done = '1') then
if (remain_out_size = 2 and padding_done) then
next_state <= LAST_STATE;
else
next_state <= PADDING_STATE;
end if;
else
next_state <= INPUT_STATE;
end if;
when PADDING_STATE =>
out_data := (out_data'high downto 1 => '0') & curr_delimiter;
out_done <= '0';
out_valid <= '1';
if (remain_out_size = 2) then
next_state <= LAST_STATE;
else
next_state <= PADDING_STATE;
end if;
when LAST_STATE =>
if (remain_out_size = 1) then
out_data := REVERSE_BIT(symbol_size(WORD_BITS*2-1 downto WORD_BITS));
out_done <= '0';
out_valid <= '1';
next_state <= LAST_STATE;
else
out_data := REVERSE_BIT(symbol_size(WORD_BITS -1 downto 0));
out_done <= '1';
out_valid <= '1';
next_state <= INPUT_STATE;
end if;
when others =>
out_data := ibuf_word_data;
out_done <= '0';
out_valid <= ibuf_valid;
next_state <= INPUT_STATE;
end case;
---------------------------------------------------------------------------
-- 出力側のワード数が２ワードの場合.
---------------------------------------------------------------------------
elsif (WORDS = 2) then
case curr_state is
when INPUT_STATE =>
out_data := in_data;
out_done <= '0';
out_valid <= ibuf_valid;
if (ibuf_done = '1') then
if (remain_out_size = 1 and padding_done) then
next_state <= LAST_STATE;
else
next_state <= PADDING_STATE;
end if;
else
next_state <= INPUT_STATE;
end if;
when PADDING_STATE =>
out_data := (out_data'high downto 1 => '0') & curr_delimiter;
out_done <= '0';
out_valid <= '1';
if (remain_out_size = 1) then
next_state <= LAST_STATE;
else
next_state <= PADDING_STATE;
end if;
when LAST_STATE =>
out_data := REVERSE_BIT(symbol_size(WORD_BITS*2-1 downto 0));
out_done <= '1';
out_valid <= '1';
next_state <= INPUT_STATE;
when others =>
out_data := ibuf_word_data;
out_done <= '0';
out_valid <= ibuf_valid;
next_state <= INPUT_STATE;
end case;
---------------------------------------------------------------------------
-- 出力側のワード数が３ワード以上場合.
---------------------------------------------------------------------------
elsif (WORDS > 2) then
case curr_state is
when INPUT_STATE =>
if (ibuf_done = '1') then
if (remain_out_size = 0 and out_sym_size) then
out_data := REVERSE_BIT(symbol_size) &
in_data(out_data'high-symbol_size'length downto 0);
out_done <= '1';
out_valid <= ibuf_valid;
next_state <= INPUT_STATE;
elsif (remain_out_size = 1) then
out_data := in_data;
out_done <= '0';
out_valid <= ibuf_valid;
next_state <= LAST_STATE;
else
out_data := in_data;
out_done <= '0';
out_valid <= ibuf_valid;
next_state <= PADDING_STATE;
end if;
else
out_data := in_data;
out_done <= '0';
out_valid <= ibuf_valid;
next_state <= INPUT_STATE;
end if;
when PADDING_STATE =>
out_data := (out_data'high downto 1 => '0') & curr_delimiter;
out_done <= '0';
out_valid <= '1';
if (remain_out_size = 1) then
next_state <= LAST_STATE;
else
next_state <= PADDING_STATE;
end if;
when LAST_STATE =>
out_data := REVERSE_BIT(symbol_size) &
(out_data'high-symbol_size'length downto 1 => '0') & curr_delimiter;
out_done <= '1';
out_valid <= '1';
next_state <= INPUT_STATE;
when others =>
out_data := ibuf_word_data;
out_done <= '0';
out_valid <= ibuf_valid;
next_state <= INPUT_STATE;
end case;
---------------------------------------------------------------------------
-- 出力側のワード数が０ワードの場合(あり得ないが一応).
---------------------------------------------------------------------------
else
out_data := ibuf_word_data;
out_done <= '0';
out_valid <= ibuf_valid;
next_state <= INPUT_STATE;
end if;
---------------------------------------------------------------------------
-- ワード毎にビットをひっくり返す.
---------------------------------------------------------------------------
for i in 0 to WORDS-1 loop
out_word_data(WORD_BITS*(i+1)-1 downto WORD_BITS*i) <=
REVERSE_BIT(out_data(WORD_BITS*(i+1)-1 downto WORD_BITS*i));
end loop;
end process;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
ibuf_ready <= '1' when (curr_state = INPUT_STATE and out_ready = '1') else '0';
-------------------------------------------------------------------------------
-- curr_state : 現在の状態.
-- curr_delimiter : 現在のデリミタ出力フラグ.
-- remain_out_size : 出力した数をカウントするカウンタ.
-------------------------------------------------------------------------------
process (CLK, RST) begin
if (RST = '1') then
curr_state <= INPUT_STATE;
curr_delimiter <= "0";
remain_out_size <= MAX_OUT_SIZE;
elsif (CLK'event and CLK = '1') then
if (CLR = '1') then
curr_state <= INPUT_STATE;
curr_delimiter <= "0";
remain_out_size <= MAX_OUT_SIZE;
elsif (out_valid = '1' and out_ready = '1') then
curr_state <= next_state;
curr_delimiter <= next_delimiter;
if (out_done = '1' or remain_out_size = 0) then
remain_out_size <= MAX_OUT_SIZE;
else
remain_out_size <= remain_out_size - 1;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- 出力バッファ
-------------------------------------------------------------------------------
O_BUF: REDUCER
generic map (
WORD_BITS => WORD_BITS , -- ワードのビット数を指定.
ENBL_BITS => 1 , --
I_WIDTH => WORDS , -- 入力側のワード数.
O_WIDTH => WORDS , -- 出力側のワード数.
QUEUE_SIZE => 0 , -- キューのサイズはO_BUFにおまかせ.
VALID_MIN => 0 , -- VALIDは未使用だけどとりあえず.
VALID_MAX => 0 , -- VALIDは未使用だけどとりあえず.
I_JUSTIFIED => 1 , -- 入力ワードはLSB側に詰められている.
FLUSH_ENABLE=> 0 -- FLUSHは未使用にする.
)
port map (
---------------------------------------------------------------------------
-- クロック&リセット信号
---------------------------------------------------------------------------
CLK => CLK , -- In : クロック.
RST => RST , -- In : 非同期リセット.
CLR => CLR , -- In : 同期リセット.
---------------------------------------------------------------------------
-- 各種制御信号
---------------------------------------------------------------------------
START => obuf_start , -- In : 未使用のため'0'に固定.
OFFSET => obuf_offset , -- In : 未使用のためALL'0'に固定.
DONE => obuf_done , -- In : 未使用のため'0'に固定.
FLUSH => obuf_flush , -- In : 未使用のため'0'に固定.
BUSY => open , -- Out : 未使用のためオープン.
VALID => open , -- Out : 未使用のためオープン.
---------------------------------------------------------------------------
-- 入力側 I/F
---------------------------------------------------------------------------
I_DATA => out_word_data , -- In : 入力データ.
I_ENBL => out_word_valid , -- In : ALL'1'にしとく.
I_DONE => out_done , -- In :
I_FLUSH => out_flush , -- In : 未使用のため'0'に固定.
I_VAL => out_valid , -- In :
I_RDY => out_ready , -- Out :
---------------------------------------------------------------------------
-- 出力側 I/F
---------------------------------------------------------------------------
O_DATA => M_DATA , -- Out : メッセージ出力.
O_ENBL => open , -- Out : 未使用のためオープン.
O_DONE => M_DONE , -- Out :
O_FLUSH => open , -- Out : 未使用のためオープン.
O_VAL => M_VAL , -- Out : メッセージ有効信号.
O_RDY => M_RDY -- In : メッセージ許可信号.
);
end RTL;
|
gpl-3.0
|
a6caa88118ae239cfc64e05f86bf3290
| 0.341879 | 4.854303 | false | false | false | false |
dsd-g05/lab5
|
g05_num_matches.vhd
| 1 | 1,707 |
-- Descp: counts number of exact matches
--
-- entity name: g05_num_matches
--
-- Version 1.0
-- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected]
-- Date: October 1, 2015
library ieee;
use ieee.std_logic_1164.all;
entity g05_num_matches is
port (
P1, P2, P3, P4 : in std_logic_vector(2 downto 0);
G1, G2, G3, G4 : in std_logic_vector(2 downto 0);
N : out std_logic_vector(2 downto 0)
);
end g05_num_matches;
architecture behavior of g05_num_matches is
component g05_comp6 is
port (
A : in std_logic_vector(5 downto 0);
B : in std_logic_vector(5 downto 0);
AeqB : out std_logic
);
end component;
component g05_num1s is
port (
X : in std_logic_vector(3 downto 0);
num1s : out std_logic_vector(2 downto 0)
);
end component;
signal X : std_logic_vector(3 downto 0);
begin
compX0 : g05_comp6
port map (A(5 downto 3) => "000", A(2 downto 0) => P1,
B(5 downto 3) => "000", B(2 downto 0) => G1, AeqB => X(0));
compX1 : g05_comp6
port map (A(5 downto 3) => "000", A(2 downto 0) => P2,
B(5 downto 3) => "000", B(2 downto 0) => G2, AeqB => X(1));
compX2 : g05_comp6
port map (A(5 downto 3) => "000", A(2 downto 0) => P3,
B(5 downto 3) => "000", B(2 downto 0) => G3, AeqB => X(2));
compX3 : g05_comp6
port map (A(5 downto 3) => "000", A(2 downto 0) => P4,
B(5 downto 3) => "000", B(2 downto 0) => G4, AeqB => X(3));
matches : g05_num1s
port map (X => X, num1s => N);
end behavior;
|
mit
|
b3796f49ceaf9ba623b905dce5c5b02f
| 0.534856 | 2.994737 | false | false | false | false |
6769/VHDL
|
Lab_4/Part2/clock_signal_per_second.vhd
| 1 | 647 |
library ieee;
use ieee.numeric_bit.all;
entity clock_signal_per_second is
port(clk:in bit;
second_output:buffer bit);
end entity clock_signal_per_second;
architecture behavior of clock_signal_per_second is
signal counter_for_osc_signal:unsigned(31 downto 0);
constant Terminator:integer:=2500000;--25*1000*1000
begin
process
begin
wait until clk'event and clk='1';
if counter_for_osc_signal<Terminator then counter_for_osc_signal<=counter_for_osc_signal+1;
else counter_for_osc_signal<=(others=>'0');
second_output<=not second_output;
end if;
end process;
end architecture behavior;
|
gpl-2.0
|
2038968bde3f5b412fafb6ea3bf494b0
| 0.709428 | 3.535519 | false | false | false | false |
6769/VHDL
|
Lab_4/Part1/counter_max10.vhd
| 1 | 602 |
library ieee;
use ieee.numeric_bit.all;
entity counter_max10 is
port(clk:in bit ;reset:in bit;limit:in bit;
carry:out bit;
CountedNumber:buffer unsigned(3 downto 0));
end entity counter_max10;
architecture behavior of counter_max10 is
begin
carry<=CountedNumber(3)and CountedNumber(0)and limit;--"1001"
process(clk,reset,limit)
begin
if(reset='0') then CountedNumber<=(others=>'0');
elsif (clk'event and clk='1' and limit='1') then
if(CountedNumber< 9) then CountedNumber<=CountedNumber+1;
else CountedNumber<="0000";
end if;
end if;
end process;
end architecture behavior;
|
gpl-2.0
|
9708e91febfdfe09632da48c2a1d1492
| 0.730897 | 3.219251 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/sim/zynq_1_axi_bram_ctrl_0_0.vhd
| 1 | 15,617 |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:3.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v3_0;
USE axi_bram_ctrl_v3_0.axi_bram_ctrl;
ENTITY zynq_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_1_axi_bram_ctrl_0_0;
ARCHITECTURE zynq_1_axi_bram_ctrl_0_0_arch OF zynq_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_MEMORY_DEPTH : INTEGER;
C_FAMILY : STRING;
C_BRAM_INST_MODE : STRING;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_MEMORY_DEPTH => 1024,
C_FAMILY => "zynq",
C_BRAM_INST_MODE => "EXTERNAL",
C_BRAM_ADDR_WIDTH => 10,
C_S_AXI_ADDR_WIDTH => 12,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zynq_1_axi_bram_ctrl_0_0_arch;
|
mit
|
76e4693ebbab0cca28df1a69309c51b0
| 0.670487 | 3.097996 | false | false | false | false |
6769/VHDL
|
Lab_1_partC/Input_Display.vhd
| 1 | 2,175 |
--------------------------------------------------------
---------------------partC------------------------------
--------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--finally synthesis all component;
entity Input_Display is
port(adder1,adder2:in std_logic_vector(7 downto 0);
adder1_hex_display,adder2_hex_display:out std_logic_vector(15 downto 0);
sum: out std_logic_vector(23 downto 0)
);
end entity Input_Display;
architecture combination of Input_Display is
--signal A0,B0,T0,Z0,A1,B1,T1,Z1,S0,S1,S2:std_logic_vector(3 downto 0):="0000";
signal A1,B1,A0,B0,Z0,Z1,S0,S1,S2:std_logic_vector(3 downto 0);
signal T0,T1:std_logic_vector(4 downto 0);
signal c1,c2:std_logic;
component Segment7Decoder
port (bcd : in std_logic_vector(3 downto 0); --BCD input
segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output.
);
end component;
begin
A0<=adder1(3 downto 0);B0<=adder2(3 downto 0);
A1<=adder1(7 downto 4);B1<=adder2(7 downto 4);
process(adder1,adder2)
begin
T0<=('0'&A0)+('0'&B0);
if T0>9 then Z0<="1010";c1<='1';
else Z0<="0000";c1<='0';
end if;
S0<=std_logic_vector(T0-('0'&Z0))(3 downto 0);
T1<=('0'&A1)+('0'&B1)+c1;
if(T1>9) then Z1<="1010";c2<='1';
else Z1<="0000";c2<='0';
end if;
S1<=std_logic_vector(T1-('0'&Z1))(3 downto 0);
S2<="000"&c2;
end process;
--adder1
Display_adder1_lower:Segment7Decoder port map(A0,adder1_hex_display(7 downto 1));
Display_adder1_higer:Segment7Decoder port map(A1,adder1_hex_display(15 downto 9));
--adder2
Display_adder2_lower:Segment7Decoder port map(B0,adder2_hex_display(7 downto 1));
Display_adder2_higer:Segment7Decoder port map(B1,adder2_hex_display(15 downto 9));
--result
Res_lower:Segment7Decoder port map(S0,sum(7 downto 1));
Res_higer:Segment7Decoder port map(S1,sum(15 downto 9));
Res_tower:Segment7Decoder port map(S2,sum(23 downto 17));
--point
sum(0)<='1';
sum(8)<='1';
sum(16)<='1';
adder1_hex_display(0)<='1';
adder1_hex_display(8)<='1';
adder2_hex_display(0)<='1';
adder2_hex_display(8)<='1';
end architecture combination;
|
gpl-2.0
|
6b590fdee2e420eb540c0bca734b36ad
| 0.628506 | 2.649208 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/CPU/Decoder.vhd
| 1 | 4,862 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:07:46 11/21/2013
-- Design Name:
-- Module Name: Decoder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder is
Port (
Instruction : in STD_LOGIC_VECTOR (15 downto 0);
Op : out STD_LOGIC_VECTOR (4 downto 0);
Reg1 : out STD_LOGIC_VECTOR (3 downto 0); --for read
Reg2 : out STD_LOGIC_VECTOR (3 downto 0); --for read
Reg3 : out STD_LOGIC_VECTOR (3 downto 0); --for write
Imm : out STD_LOGIC_VECTOR (15 downto 0)
);
end Decoder;
architecture Behavioral of Decoder is
begin
process(Instruction)
begin
op <= Instruction(15 downto 11);
Reg1 <= Zero_Reg;
Reg2 <= Zero_Reg;
Reg3 <= Zero_Reg;
Imm <= Int16_Zero;
case Instruction(15 downto 11) is
when "00000" => null; --NOP
when "00001" => --MFIH
Reg1 <= IH_reg;
Reg3 <= '0' & Instruction(10 downto 8);
when "00010" => --MFPC
Reg1 <= PC_reg;
Reg3 <= '0' & Instruction(10 downto 8);
when "00011" => --MTIH
Reg3 <= IH_reg;
Reg1 <= '0' & Instruction(10 downto 8);
when "00100" => --MTSP
Reg3 <= SP_reg;
Reg1 <= '0' & Instruction(10 downto 8);
when "00101" | "00110" => --AND, OR
Reg1 <= '0' & Instruction(10 downto 8);
Reg2 <= '0' & Instruction(7 downto 5);
Reg3 <= '0' & Instruction(10 downto 8);
when "00111" => --NOT*
Reg1 <= '0' & Instruction(7 downto 5);
Reg3 <= '0' & Instruction(10 downto 8);
when "01000" | "01001" => --SLT*, CMP
Reg1 <= '0' & Instruction(10 downto 8);
Reg2 <= '0' & Instruction(7 downto 5);
when "01010" | "01011" => --SLL, SRA
Reg3 <= '0' & Instruction(10 downto 8);
Reg1 <= '0' & Instruction(7 downto 5);
if Instruction(4 downto 2) /= "000" then
Imm <= extend("0000000000000" & Instruction(4 downto 2), "0011", '0');
else
Imm <= Int16_eight;
end if;
when "01100" | "01101" =>
Reg1 <= '0' & Instruction(10 downto 8);
Reg2 <= '0' & Instruction(7 downto 5);
Reg3 <= '0' & Instruction(4 downto 2);
when "01110" => --ADDSP
Reg1 <= SP_reg;
Reg3 <= SP_reg;
Imm <= extend(Int8_zero & Instruction(10 downto 3), "1000", '1');
when "01111" | "10011" => -- LW_SP, ADDSP3*
Reg3 <= '0' & Instruction(10 downto 8);
Reg1 <= SP_reg;
Imm <= extend(Int8_zero & Instruction(7 downto 0), "1000", '1');
when "10000" => --SW_SP
Reg2 <= '0' & Instruction(10 downto 8);
Reg1 <= SP_reg;
Imm <= extend(Int8_zero & Instruction(7 downto 0), "1000", '1');
when "10001" => --ADDIU
Reg1 <= '0' & Instruction(10 downto 8);
Reg3 <= '0' & Instruction(10 downto 8);
Imm <= extend(Int8_zero & Instruction(7 downto 0), "1000", '1');
when "10010" => --SLTI
Reg1 <= '0' & Instruction(10 downto 8);
Imm <= extend(Int8_zero & Instruction(7 downto 0), "1000", '1');
when "10100" =>
Reg3 <= '0' & Instruction(10 downto 8);
Imm <= extend(Int8_zero & Instruction(7 downto 0), "1000", '0');
when "10101" => --ADDIU3
Reg1 <= '0' & Instruction(10 downto 8);
Reg3 <= '0' & Instruction(7 downto 5);
Imm <= extend("000000000000" & Instruction(3 downto 0), "0100", '1');
when "10110" => --LW
Reg1 <= '0' & Instruction(10 downto 8);
Reg3 <= '0' & Instruction(7 downto 5);
Imm <= extend("00000000000" & Instruction(4 downto 0), "0101", '1');
when "10111" => --SW
Reg1 <= '0' & Instruction(10 downto 8);
Reg2 <= '0' & Instruction(7 downto 5);
Imm <= extend("00000000000" & Instruction(4 downto 0), "0101", '1');
when "11000" => --B
-- Reg1 <= PC_reg;
-- Reg3 <= PC_reg;
Imm <= extend(Int5_Zero & Instruction(10 downto 0), "1011", '1');
when "11001" => --BTEQZ
-- Reg1 <= PC_reg;
-- Reg3 <= PC_reg;
Imm <= extend(Int8_Zero & Instruction(10 downto 3), "1000", '1');
when "11010" | "11011"=> --BEQZ, BNEZ
Reg1 <= '0' & Instruction(10 downto 8);
-- Reg2 <= PC_reg;
-- Reg3 <= PC_reg;
Imm <= extend(Int8_zero & Instruction(7 downto 0), "1000", '1');
when "11100" => --JRRA*
Reg1 <= RA_reg;
-- Reg3 <= PC_reg;
when "11101" => --JR
Reg1 <= '0' & Instruction(10 downto 8);
-- Reg3 <= PC_reg;
when others => null;
end case;
end process;
end Behavioral;
|
mit
|
9de1e0d1380331f3a3dec32e66ca950f
| 0.56232 | 3.03875 | false | false | false | false |
zzhou007/161lab
|
lab04/control_unit.vhd
| 1 | 2,068 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity control_unit is
port (
instr_op : in std_logic_vector(5 downto 0);
reg_dst : out std_logic;
branch : out std_logic;
mem_read : out std_logic;
mem_to_reg : out std_logic;
alu_op : out std_logic_vector(1 downto 0);
mem_write : out std_logic;
alu_src : out std_logic;
reg_write : out std_logic
);
end control_unit;
architecture Behavioral of control_unit is
begin
process(instr_op) begin
case instr_op is
when "000000" =>
reg_dst <= '1';
alu_src <= '0';
mem_to_reg <= '0';
reg_write <= '1';
mem_read <= '0';
mem_write <= '0';
branch <= '0';
alu_op <= "10";
when "100011" =>
reg_dst <= '0';
alu_src <= '1';
mem_to_reg <= '1';
reg_write <= '1';
mem_read <= '1';
mem_write <= '0';
branch <= '0';
alu_op <= "00";
when "101011" =>
--reg_dst <= '0';
alu_src <= '1';
--mem_to_reg <= '1';
reg_write <= '0';
mem_read <= '0';
mem_write <= '1';
branch <= '0';
alu_op <= "00";
when "000100" =>
--reg_dst <= '0';
alu_src <= '0';
--mem_to_reg <= '1';
reg_write <= '0';
mem_read <= '0';
mem_write <= '0';
branch <= '1';
alu_op <= "01";
when "001000" =>
-- Add immediate
reg_dst <= '1';
alu_src <= '1';
mem_to_reg <= '0';
reg_write <= '1';
mem_read <= '0';
mem_write <= '0';
branch <= '0';
alu_op <= "00";
when others =>
end case;
end process;
end Behavioral;
|
gpl-2.0
|
445bcee304d99f252b67bd5a8a316781
| 0.361702 | 3.640845 | false | false | false | false |
1995parham/FPGA-Homework
|
HW-3/src/p5/parity-generator.vhd
| 1 | 1,096 |
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 25-04-2016
-- Module Name: parity-generator.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity parity_generator is
port (w, clk, reset : in std_logic;
p : out std_logic);
end entity parity_generator;
architecture rtl of parity_generator is
type state is (even, odd);
signal current_state, next_state : state;
begin
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
current_state <= even;
else
current_state <= next_state;
end if;
end if;
end process;
process (current_state, w)
begin
if current_state = even then
if w = '1' then
p <= '1';
next_state <= odd;
else
p <= '0';
next_state <= even;
end if;
else
if w = '1' then
p <= '0';
next_state <= even;
else
p <= '1';
next_state <= odd;
end if;
end if;
end process;
end architecture rtl;
|
gpl-3.0
|
f0cc78e8abd56cb51a992046a62a88f4
| 0.52281 | 3.291291 | false | false | false | false |
1995parham/FPGA-Homework
|
HW-1/src/p4-5/p4-5.vhd
| 1 | 1,063 |
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 04-03-2016
-- Module Name: p4-5.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity counter is
generic (N : natural := 4);
port (clk : in std_logic;
d : out std_logic_vector(N - 1 downto 0));
end entity counter;
architecture structural of counter is
component t_flipflop is
port( t, clk : in std_logic;
q, q_bar : out std_logic);
end component;
signal C : std_logic_vector(N - 1 downto 0);
signal B : std_logic_vector(N - 1 downto 0) := (others => '0');
for all:t_flipflop use entity work.t_flipflop;
begin
C(0) <= '1';
c0: t_flipflop port map ('1', clk, B(0), open);
cs: for I in 1 to N - 1 generate
C(I) <= C(I - 1) and B(I - 1);
cI: t_flipflop port map (C(I), clk, B(I), open);
end generate;
Bs: for I in 0 to N - 1 generate
d(I) <= B(I);
end generate;
end architecture structural;
|
gpl-3.0
|
1528b1a7a649bf2dae32620aea1de0f7
| 0.534337 | 3.14497 | false | false | false | false |
sunoc/vhdl-lz4-variation
|
lz4_top.vhdl
| 1 | 3,174 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all; -- Imports the standard textio package. For test here
use work.lz4_pkg.all;
entity lz4_top is
port (
clk_i : in std_logic;
reset_i : in std_logic;
entryStream_i : in std_logic;
outputStream_o : out std_logic;
outputFlag_o : out std_logic
);
end lz4_top;
architecture behavior of lz4_top is
signal litLength_s : std_logic_vector(9 downto 0);
signal offset_s : std_logic_vector(9 downto 0);
signal matchLength_s : std_logic_vector(9 downto 0);
signal internalBytes_s : std_logic_vector(7 downto 0);
signal internalStream_s : std_logic;
signal entryBytes_s : std_logic_vector(7 downto 0);
begin
assembly: lz4_assembly
port map(
clk_i => clk_i ,
reset_i => reset_i ,
litLength_i => litLength_s ,
offset_i => offset_s ,
matchLength_i => matchLength_s ,
internalStream_i => internalStream_s ,
-- main output
outputStream_o => outputStream_o ,
outputFlag_o => outputFlag_o
);
entryDict: lz4_entryDict
port map(
clk_i => clk_i ,
reset_i => reset_i ,
entryBytes_i => entryBytes_s ,
litLength_o => litLength_s ,
offset_o => offset_s ,
matchLength_o => matchLength_s ,
internalStream_o => internalBytes_s
);
-- entry stream process
-- turns the single bit entry into a byte signal
process (clk_i, reset_i)
variable pos : integer range 0 to 8 := 0;
variable byteBuff : std_logic_vector(7 downto 0);
begin
if reset_i = '1' then
pos := 0;
byteBuff := (others => '0');
elsif rising_edge(clk_i) or falling_edge(clk_i) then
byteBuff(pos) := entryStream_i;
pos := pos + 1;
if pos = 8 then
pos := 0;
entryBytes_s <= byteBuff;
end if;
end if;
end process;
-- internal stream process
-- turn back bytes from the dict into a single bit stream
process (clk_i, reset_i)
variable pos : integer range 0 to 8 := 0;
variable byteBuff : std_logic_vector(7 downto 0);
begin
if reset_i = '1' then
pos := 0;
byteBuff := (others => '0');
elsif rising_edge(clk_i) or falling_edge(clk_i) then
if pos = 7 then
pos := 0;
byteBuff := internalBytes_s;
else
internalStream_s <= byteBuff(pos);
pos := pos + 1;
end if;
end if;
end process;
-- dummy test process
process
variable l : line;
begin
write (l, String'("This is the lz4 top level architecture!"));
writeline (output, l);
wait;
end process;
end;
|
gpl-3.0
|
2012f0d04e9117b99a68ef480798c6c4
| 0.501575 | 4.012642 | false | false | false | false |
Project-Bonfire/EHA
|
RTL/Processor_NI/reg_bank_tri_port.vhd
| 6 | 5,215 |
---------------------------------------------------------------------
-- TITLE: Register Bank
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/2/01
-- FILENAME: reg_bank.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements a register bank with 32 registers that are 32-bits wide.
-- There are two read-ports and one write port.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
--library UNISIM; --May need to uncomment for ModelSim
--use UNISIM.vcomponents.all; --May need to uncomment for ModelSim
entity reg_bank is
generic(memory_type : string := "TRI_PORT_X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end; --entity reg_bank
--------------------------------------------------------------------
-- The ram_block architecture attempts to use TWO dual-port memories.
-- Different FPGAs and ASICs need different implementations.
-- Choose one of the RAM implementations below.
-- I need feedback on this section!
--------------------------------------------------------------------
architecture ram_block of reg_bank is
signal intr_enable_reg : std_logic;
type ram_type is array(31 downto 0) of std_logic_vector(31 downto 0);
signal tri_port_ram : ram_type := (others => ZERO);
--controls access to dual-port memories
signal addr_read1, addr_read2 : std_logic_vector(4 downto 0);
signal addr_write : std_logic_vector(4 downto 0);
signal data_out1, data_out2 : std_logic_vector(31 downto 0);
signal write_enable : std_logic;
begin
--------------------------------------
-- Implements register bank control --
--------------------------------------
reg_proc: process(clk, rs_index, rt_index, rd_index, reg_dest_new, intr_enable_reg,
data_out1, data_out2, reset_in, pause)
begin
--setup for first dual-port memory
if rs_index = "101110" then --reg_epc CP0 14
addr_read1 <= "00000";
else
addr_read1 <= rs_index(4 downto 0);
end if;
case rs_index is
when "000000" => reg_source_out <= ZERO;
when "101100" => reg_source_out <= ZERO(31 downto 1) & intr_enable_reg;
--interrupt vector address = 0x3c
when "111111" => reg_source_out <= ZERO(31 downto 8) & "00111100";
when others => reg_source_out <= data_out1;
end case;
--setup for second dual-port memory
addr_read2 <= rt_index(4 downto 0);
case rt_index is
when "000000" => reg_target_out <= ZERO;
when others => reg_target_out <= data_out2;
end case;
--setup write port for both dual-port memories
if rd_index /= "000000" and rd_index /= "101100" and pause = '0' then
write_enable <= '1';
else
write_enable <= '0';
end if;
if rd_index = "101110" then --reg_epc CP0 14
addr_write <= "00000";--"01110" --"11010"; -- Reg $26 to save PC when interrupt occurs, but is it safe ??
else
addr_write <= rd_index(4 downto 0);
end if;
if reset_in = '1' then
intr_enable_reg <= '0';
elsif rising_edge(clk) then
if rd_index = "101110" then --reg_epc CP0 14
intr_enable_reg <= '0'; --disable interrupts
elsif rd_index = "101100" then
intr_enable_reg <= reg_dest_new(0); -- Check the IEc (Interrupt Enable current) bit (bit 0 of the status register)
end if;
end if;
intr_enable <= intr_enable_reg;
end process;
-----------------------
-- Implements memory --
-----------------------
-- One tri-port RAM, two read-ports, one write-port
-- 32 registers 32-bits wide
ram_proc: process(clk, addr_read1, addr_read2, addr_write,
reg_dest_new, write_enable)
begin
data_out1 <= tri_port_ram(conv_integer(addr_read1));
data_out2 <= tri_port_ram(conv_integer(addr_read2));
if rising_edge(clk) then
if write_enable = '1' then
tri_port_ram(conv_integer(addr_write)) <= reg_dest_new;
end if;
end if;
end process;
end; --architecture ram_block
|
gpl-3.0
|
64b83f1e2e03dca20bbd46269abfe45b
| 0.524257 | 3.990054 | false | false | false | false |
6769/VHDL
|
Lab_4/Part2/H24_Min60_Sec60.vhd
| 1 | 1,904 |
library ieee;
use ieee.numeric_bit.all;
entity H24_Min60_Sec60 is
port(Clk,Ldn:in bit;
Din :in unsigned(16 downto 1);
Qout:out unsigned(23 downto 0));
end entity H24_Min60_Sec60;
architecture Behavior of H24_Min60_Sec60 is
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 downto 0) is Q(3 downto 0);
alias Second_hig:unsigned(3 downto 0) is Q(7 downto 4);
alias Min_low: unsigned(3 downto 0) is Q(11 downto 8);
alias Min_hig: unsigned(3 downto 0) is Q(15 downto 12);
alias Hour_low: unsigned(3 downto 0) is Q(19 downto 16);
alias Hour_hig: unsigned(3 downto 0) is Q(23 downto 20);
--internal logic
signal second_count,min_count:integer range 0 to 59;--(63 downto 0);
signal hour_count: integer range 0 to 23;--(31 downto 0);
--signal carry_from_second,carry_from_min:bit;
begin
Qout<=Q;
process(Clk,Ldn,Din)
begin
if(Ldn='0') then min_count<=to_integer(Din(6 downto 1));hour_count<=to_integer(Din(13 downto 9));
elsif(Clk'event and Clk='1') then
if(second_count=59) then second_count<=0;
if(min_count=59) then min_count<=0;
if(hour_count=23) then hour_count<=0;
else hour_count<=hour_count+1;
end if;
--carry_from_min<='1';
else min_count<=min_count+1;
end if;
--carry_from_second<='1';
else second_count<=second_count+1;
end if;
end if;
end process;
Second_low<=to_unsigned(second_count mod 10,4);
Second_hig<=to_unsigned(second_count/10,4);
Min_low<=to_unsigned(min_count mod 10,4);
Min_hig<=to_unsigned(min_count/10,4);
Hour_low<=to_unsigned(hour_count mod 10,4);
Hour_hig<=to_unsigned(hour_count/10,4);
end architecture Behavior;
|
gpl-2.0
|
b8d4a605543a7b52790d922a5c81a9d4
| 0.591387 | 3.358025 | false | false | false | false |
1995parham/FPGA-Homework
|
HW-3/src/p10/p10.vhd
| 1 | 1,673 |
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 25-04-2016
-- Module Name: p10.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity alu is
port (a, b : in std_logic_vector (3 downto 0);
alucode : in std_logic_vector (2 downto 0);
result : out std_logic_vector (3 downto 0);
z, o : out std_logic);
end entity;
architecture rtl of alu is
begin
process (alucode, a, b)
variable im : std_logic_vector (4 downto 0);
begin
case alucode is
-- ADD
when "000" =>
im := ('0' & a) + ('0' & b);
result <= im(3 downto 0);
z <= im(4);
-- SUB
when "001" =>
im := ('0' & a) - ('0' & b);
result <= im(3 downto 0);
z <= im(4);
-- AND
when "010" =>
im(3 downto 0) := (a(0) and b(0)) & (a(1) and b(1)) & (a(2) and b(2)) & (a(3) and b(3));
if im(3 downto 0) = "111" then
z <= '1';
else
z <= '0';
end if;
result <= im(3 downto 0);
-- CMP
when "011" =>
if a < b then
result <= a;
z <= '0';
elsif a = b then
result <= a;
z <= '1';
else
result <= b;
z <= '0';
end if;
-- RT
when "100" =>
result <= '0' & a(2 downto 0);
z <= a(3);
-- RR
when "101" =>
result <= a(3 downto 1) & '0';
z <= a(0);
-- Parity
when "110" =>
result <= a;
z <= a(0) xor a(1) xor a(2) xor a(3);
when others =>
result <= (others => '0');
z <= '0';
o <= '0';
end case;
end process;
end architecture;
|
gpl-3.0
|
ac20cf3e3cbebe7a104d1c2e4fe96cca
| 0.439331 | 2.756178 | false | false | false | false |
HighlandersFRC/fpga
|
oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/sync_fifo_fg.vhd
| 12 | 68,755 |
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- sync_fifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: sync_fifo_fg.vhd
--
-- Description:
-- This HDL file adapts the legacy CoreGen Sync FIFO interface to the new
-- FIFO Generator Sync FIFO interface. This wrapper facilitates the "on
-- the fly" call of FIFO Generator during design implementation.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- sync_fifo_fg.vhd
-- |
-- |-- fifo_generator_v4_3
-- |
-- |-- fifo_generator_v9_3
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.5.2.68 $
-- Date: $1/16/2008$
--
-- History:
-- DET 1/16/2008 Initial Version
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Replaced fifo_generator_v4_2 component with fifo_generator_v4_3
-- ^^^^^^
--
-- MSH and DET 3/2/2009 For Lava SP2
-- ~~~~~~
-- - Added FIFO Generator version 5.1 for use with Virtex6 and Spartan6
-- devices.
-- - IfGen used so that legacy FPGA families still use Fifo Generator
-- version 4.3.
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Replaced FIFO Generator version 5.1 with 5.2.
-- ^^^^^^
--
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the S6/V6 FIFO Generator version from V5.2 to V5.3.
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the S6/V6 FIFO Generator version from V5.3 to V6.1.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/30/2010 EDK_MS4
-- ~~~~~~
-- -- Per CR573867
-- - Updated the S6/V6 FIFO Generator version from V6.1 to 7.2.
-- - Added all of the AXI parameters and ports. They are not used
-- in this application.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated the FIFO Generator version from V7.2 to 7.3.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated the FIFO Generator version from V7.3 to 8.1.
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- ^^^^^^
--
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-- RBODDU 06/07/2012 EDK 14.2
-- ~~~~~~
-- - Update to use fifo_generator_v9_1
-- ^^^^^^
-- RBODDU 06/11/2012 EDK 14.4
-- ~~~~~~
-- - Update to use fifo_generator_v9_2
-- ^^^^^^
-- RBODDU 07/12/2012 EDK 14.5
-- ~~~~~~
-- - Update to use fifo_generator_v9_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
library fifo_generator_v11_0;
--use proc_common_v4_0.coregen_comp_defs.all;
use fifo_generator_v11_0.all;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.family_support.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity sync_fifo_fg is
generic (
C_FAMILY : String := "virtex5"; -- new for FIFO Gen
C_DCOUNT_WIDTH : integer := 4 ;
C_ENABLE_RLOCS : integer := 0 ; -- not supported in sync fifo
C_HAS_DCOUNT : integer := 1 ;
C_HAS_RD_ACK : integer := 0 ;
C_HAS_RD_ERR : integer := 0 ;
C_HAS_WR_ACK : integer := 0 ;
C_HAS_WR_ERR : integer := 0 ;
C_HAS_ALMOST_FULL : integer := 0 ;
C_MEMORY_TYPE : integer := 0 ; -- 0 = distributed RAM, 1 = BRAM
C_PORTS_DIFFER : integer := 0 ;
C_RD_ACK_LOW : integer := 0 ;
C_USE_EMBEDDED_REG : integer := 0 ;
C_READ_DATA_WIDTH : integer := 16;
C_READ_DEPTH : integer := 16;
C_RD_ERR_LOW : integer := 0 ;
C_WR_ACK_LOW : integer := 0 ;
C_WR_ERR_LOW : integer := 0 ;
C_PRELOAD_REGS : integer := 0 ; -- 1 = first word fall through
C_PRELOAD_LATENCY : integer := 1 ; -- 0 = first word fall through
C_WRITE_DATA_WIDTH : integer := 16;
C_WRITE_DEPTH : integer := 16;
C_SYNCHRONIZER_STAGE : integer := 2 -- Valid values are 0 to 8
);
port (
Clk : in std_logic;
Sinit : in std_logic;
Din : in std_logic_vector(C_WRITE_DATA_WIDTH-1 downto 0);
Wr_en : in std_logic;
Rd_en : in std_logic;
Dout : out std_logic_vector(C_READ_DATA_WIDTH-1 downto 0);
Almost_full : out std_logic;
Full : out std_logic;
Empty : out std_logic;
Rd_ack : out std_logic;
Wr_ack : out std_logic;
Rd_err : out std_logic;
Wr_err : out std_logic;
Data_count : out std_logic_vector(C_DCOUNT_WIDTH-1 downto 0)
);
end entity sync_fifo_fg;
architecture implementation of sync_fifo_fg is
-- Function delarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMaxDepth
--
-- Function Description:
-- Returns the largest value of either Write depth or Read depth
-- requested by input parameters.
--
-------------------------------------------------------------------
function GetMaxDepth (rd_depth : integer;
wr_depth : integer)
return integer is
Variable max_value : integer := 0;
begin
If (rd_depth < wr_depth) Then
max_value := wr_depth;
else
max_value := rd_depth;
End if;
return(max_value);
end function GetMaxDepth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: GetMemType
--
-- Function Description:
-- Generates the required integer value for the FG instance assignment
-- of the C_MEMORY_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- FIFO Generator values
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
--
-------------------------------------------------------------------
function GetMemType (inputmemtype : integer) return integer is
Variable memtype : Integer := 0;
begin
If (inputmemtype = 0) Then -- distributed Memory
memtype := 2;
else
memtype := 1; -- BRAM
End if;
return(memtype);
end function GetMemType;
-- Constant Declarations ----------------------------------------------
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
--Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
-- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
-- FAMILY_IS_SUPPORTED;
--Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
-- FAMILY_IS_SUPPORTED;
-- Calculate associated FIFO characteristics
Constant MAX_DEPTH : integer := GetMaxDepth(C_READ_DEPTH,C_WRITE_DEPTH);
Constant FGEN_CNT_WIDTH : integer := log2(MAX_DEPTH)+1;
Constant ADJ_FGEN_CNT_WIDTH : integer := FGEN_CNT_WIDTH-1;
-- Get the integer value for a Block memory type fifo generator call
Constant FG_MEM_TYPE : integer := GetMemType(C_MEMORY_TYPE);
-- Set the required integer value for the FG instance assignment
-- of the C_IMPLEMENTATION_TYPE parameter. Derived from
-- the input memory type parameter C_MEMORY_TYPE.
--
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
-- 2 = Independent Clock BRAM/Distributed RAM (Asynchronous FIFO)
-- 3 = Independent/Common Clock V4 Built In Memory -- not used in legacy fifo calls
-- 5 = Independent/Common Clock V5 Built in Memory -- not used in legacy fifo calls
--
Constant FG_IMP_TYPE : integer := 0;
-- The programable thresholds are not used so this is housekeeping.
Constant PROG_FULL_THRESH_ASSERT_VAL : integer := MAX_DEPTH-3;
Constant PROG_FULL_THRESH_NEGATE_VAL : integer := MAX_DEPTH-4;
-- Constant zeros for programmable threshold inputs
signal PROG_RDTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
signal PROG_WRTHRESH_ZEROS : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
signal sig_full : std_logic;
signal sig_full_fg_datacnt : std_logic_vector(FGEN_CNT_WIDTH-1 downto 0);
signal sig_prim_fg_datacnt : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
--Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE"
signal ALMOST_EMPTY : std_logic;
signal RD_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal WR_DATA_COUNT : std_logic_vector(ADJ_FGEN_CNT_WIDTH-1 downto 0);
signal PROG_FULL : std_logic;
signal PROG_EMPTY : std_logic;
signal SBITERR : std_logic;
signal DBITERR : std_logic;
signal S_AXI_AWREADY : std_logic;
signal S_AXI_WREADY : std_logic;
signal S_AXI_BID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_BUSER : std_logic_vector(0 downto 0);
signal S_AXI_BVALID : std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_AWUSER : std_logic_vector(0 downto 0);
signal M_AXI_AWVALID : std_logic;
signal M_AXI_WID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0);
signal M_AXI_WLAST : std_logic;
signal M_AXI_WUSER : std_logic_vector(0 downto 0);
signal M_AXI_WVALID : std_logic;
signal M_AXI_BREADY : std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
signal S_AXI_ARREADY : std_logic;
signal S_AXI_RID : std_logic_vector(3 DOWNTO 0);
signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0);
signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0);
signal S_AXI_RLAST : std_logic;
signal S_AXI_RUSER : std_logic_vector(0 downto 0);
signal S_AXI_RVALID : std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0);
signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0);
signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0);
signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0);
signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0);
signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0);
signal M_AXI_ARUSER : std_logic_vector(0 downto 0);
signal M_AXI_ARVALID : std_logic;
signal M_AXI_RREADY : std_logic;
-- AXI Streaming Slave Signals (Write side)
signal S_AXIS_TREADY : std_logic;
-- AXI Streaming Master Signals (Read side)
signal M_AXIS_TVALID : std_logic;
signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0);
signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TLAST : std_logic;
signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0);
signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0);
signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AW_SBITERR : std_logic;
signal AXI_AW_DBITERR : std_logic;
signal AXI_AW_OVERFLOW : std_logic;
signal AXI_AW_UNDERFLOW : std_logic;
signal AXI_AW_PROG_FULL : STD_LOGIC;
signal AXI_AW_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Data Channel Signals
signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_W_SBITERR : std_logic;
signal AXI_W_DBITERR : std_logic;
signal AXI_W_OVERFLOW : std_logic;
signal AXI_W_UNDERFLOW : std_logic;
signal AXI_W_PROG_FULL : STD_LOGIC;
signal AXI_W_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Write Response Channel Signals
signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_B_SBITERR : std_logic;
signal AXI_B_DBITERR : std_logic;
signal AXI_B_OVERFLOW : std_logic;
signal AXI_B_UNDERFLOW : std_logic;
signal AXI_B_PROG_FULL : STD_LOGIC;
signal AXI_B_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Address Channel Signals
signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0);
signal AXI_AR_SBITERR : std_logic;
signal AXI_AR_DBITERR : std_logic;
signal AXI_AR_OVERFLOW : std_logic;
signal AXI_AR_UNDERFLOW : std_logic;
signal AXI_AR_PROG_FULL : STD_LOGIC;
signal AXI_AR_PROG_EMPTY : STD_LOGIC;
-- AXI Full/Lite Read Data Channel Signals
signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXI_R_SBITERR : std_logic;
signal AXI_R_DBITERR : std_logic;
signal AXI_R_OVERFLOW : std_logic;
signal AXI_R_UNDERFLOW : std_logic;
signal AXI_R_PROG_FULL : STD_LOGIC;
signal AXI_R_PROG_EMPTY : STD_LOGIC;
-- AXI Streaming FIFO Related Signals
signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0);
signal AXIS_SBITERR : std_logic;
signal AXIS_DBITERR : std_logic;
signal AXIS_OVERFLOW : std_logic;
signal AXIS_UNDERFLOW : std_logic;
signal AXIS_PROG_FULL : STD_LOGIC;
signal AXIS_PROG_EMPTY : STD_LOGIC;
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until Clk = '1';
wait until Clk = '0';
Wait until Clk = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait;-- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low or logic high as required
Dout <= (others => '0'); -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Almost_full <= '0' ; -- : out std_logic;
Full <= '0' ; -- : out std_logic;
Empty <= '1' ; -- : out std_logic;
Rd_ack <= '0' ; -- : out std_logic;
Wr_ack <= '0' ; -- : out std_logic;
Rd_err <= '1' ; -- : out std_logic;
Wr_err <= '1' ; -- : out std_logic
Data_count <= (others => '0'); -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IfGen implements the fifo using fifo_generator_v9_3
-- when the designated FPGA Family is Spartan-6, Virtex-6 or
-- later.
--
------------------------------------------------------------
FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate
begin
Full <= sig_full;
-- Create legacy data count by concatonating the Full flag to the
-- MS Bit position of the FIFO data count
-- This is per the Fifo Generator Migration Guide
sig_full_fg_datacnt <= sig_full & sig_prim_fg_datacnt;
Data_count <= sig_full_fg_datacnt(FGEN_CNT_WIDTH-1 downto
FGEN_CNT_WIDTH-C_DCOUNT_WIDTH);
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a legacy Sync FIFO
--
-------------------------------------------------------------------------------
I_SYNC_FIFO_BRAM : entity fifo_generator_v11_0.fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH, -- what to do here ???
C_DEFAULT_VALUE => "BlankString", -- what to do here ???
C_DIN_WIDTH => C_WRITE_DATA_WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_READ_DATA_WIDTH,
C_ENABLE_RLOCS => 0, -- not supported
C_FAMILY => FAMILY_TO_USE,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => C_HAS_DCOUNT,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => C_HAS_WR_ERR,
C_HAS_RD_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_RD_RST => 0, -- not used for sync FIFO
C_HAS_RST => 0, -- not used for sync FIFO
C_HAS_SRST => 1,
C_HAS_UNDERFLOW => C_HAS_RD_ERR,
C_HAS_VALID => C_HAS_RD_ACK,
C_HAS_WR_ACK => C_HAS_WR_ACK,
C_HAS_WR_DATA_COUNT => 0, -- not used for sync FIFO
C_HAS_WR_RST => 0, -- not used for sync FIFO
C_IMPLEMENTATION_TYPE => FG_IMP_TYPE,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => FG_MEM_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => C_WR_ERR_LOW,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, -- 0 = first word fall through
C_PRELOAD_REGS => C_PRELOAD_REGS, -- 1 = first word fall through
C_PRIM_FIFO_TYPE => "512x36", -- only used for V5 Hard FIFO
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => PROG_FULL_THRESH_ASSERT_VAL,
C_PROG_FULL_THRESH_NEGATE_VAL => PROG_FULL_THRESH_NEGATE_VAL,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_RD_DEPTH => MAX_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_UNDERFLOW_LOW => C_RD_ERR_LOW,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, ----0, Fixed CR#658129
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => C_RD_ACK_LOW,
C_WR_ACK_LOW => C_WR_ACK_LOW,
C_WR_DATA_COUNT_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_DEPTH => MAX_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADJ_FGEN_CNT_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
backup => '0',
backup_marker => '0',
clk => Clk,
rst => '0',
srst => Sinit,
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => Din,
wr_en => Wr_en,
rd_en => Rd_en,
prog_empty_thresh => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS,
prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS,
prog_full_thresh => PROG_WRTHRESH_ZEROS,
prog_full_thresh_assert => PROG_WRTHRESH_ZEROS,
prog_full_thresh_negate => PROG_WRTHRESH_ZEROS,
int_clk => '0',
injectdbiterr => '0', -- new FG 5.1/5.2
injectsbiterr => '0', -- new FG 5.1/5.2
dout => Dout,
full => sig_full,
almost_full => Almost_full,
wr_ack => Wr_ack,
overflow => Wr_err,
empty => Empty,
almost_empty => ALMOST_EMPTY,
valid => Rd_ack,
underflow => Rd_err,
data_count => sig_prim_fg_datacnt,
rd_data_count => RD_DATA_COUNT,
wr_data_count => WR_DATA_COUNT,
prog_full => PROG_FULL,
prog_empty => PROG_EMPTY,
sbiterr => SBITERR,
dbiterr => DBITERR,
-- AXI Global Signal
m_aclk => '0', -- : IN std_logic := '0';
s_aclk => '0', -- : IN std_logic := '0';
s_aresetn => '0', -- : IN std_logic := '0';
m_aclk_en => '0', -- : IN std_logic := '0';
s_aclk_en => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid => '0', -- : IN std_logic := '0';
s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic;
s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast => '0', -- : IN std_logic := '0';
s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wvalid => '0', -- : IN std_logic := '0';
s_axi_wready => S_AXI_WREADY, -- : OUT std_logic;
s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic;
s_axi_bready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic;
m_axi_awready => '0', -- : IN std_logic := '0';
m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic;
m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic;
m_axi_wready => '0', -- : IN std_logic := '0';
m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_bvalid => '0', -- : IN std_logic := '0';
m_axi_bready => M_AXI_BREADY, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid => '0', -- : IN std_logic := '0';
s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic;
s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0);
s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic;
s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic;
s_axi_rready => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0);
m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0);
m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0);
m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0);
m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic;
m_axi_arready => '0', -- : IN std_logic := '0';
m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rlast => '0', -- : IN std_logic := '0';
m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
m_axi_rvalid => '0', -- : IN std_logic := '0';
m_axi_rready => M_AXI_RREADY, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
s_axis_tvalid => '0', -- : IN std_logic := '0';
s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic;
s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tlast => '0', -- : IN std_logic := '0';
s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic;
m_axis_tready => '0', -- : IN std_logic := '0';
m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic;
m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
axi_aw_injectsbiterr => '0', -- : IN std_logic := '0';
axi_aw_injectdbiterr => '0', -- : IN std_logic := '0';
axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic;
axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic;
axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic;
axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic;
axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
axi_w_injectsbiterr => '0', -- : IN std_logic := '0';
axi_w_injectdbiterr => '0', -- : IN std_logic := '0';
axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic;
axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic;
axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic;
axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic;
axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
axi_b_injectsbiterr => '0', -- : IN std_logic := '0';
axi_b_injectdbiterr => '0', -- : IN std_logic := '0';
axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic;
axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic;
axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic;
axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic;
axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
axi_ar_injectsbiterr => '0', -- : IN std_logic := '0';
axi_ar_injectdbiterr => '0', -- : IN std_logic := '0';
axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic;
axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic;
axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic;
axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic;
axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
axi_r_injectsbiterr => '0', -- : IN std_logic := '0';
axi_r_injectdbiterr => '0', -- : IN std_logic := '0';
axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic;
axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic;
axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic;
axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic;
axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0';
axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
axis_injectsbiterr => '0', -- : IN std_logic := '0';
axis_injectdbiterr => '0', -- : IN std_logic := '0';
axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic;
axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic;
axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic;
axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic
axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0';
axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1';
);
end generate FAMILY_SUPPORTED;
end implementation;
|
mit
|
f81ef1e3a75d58074a24d240dba6f160
| 0.420697 | 3.889077 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/CPU/CPU.vhd
| 1 | 26,052 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: tuk
--
-- Create Date: 18:57:52 11/21/2013
-- Design Name:
-- Module Name: CPU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
--Ram1Addr : out STD_LOGIC_VECTOR (17 downto 0);
--Ram1Data : inout STD_LOGIC_VECTOR (15 downto 0);
Ram1Data : inout STD_LOGIC_VECTOR (7 downto 0);
Ram1OE : out STD_LOGIC;
Ram1WE : out STD_LOGIC;
Ram1EN : out STD_LOGIC;
Ram2Addr : out STD_LOGIC_VECTOR (17 downto 0);
Ram2Data : inout STD_LOGIC_VECTOR (15 downto 0);
Ram2OE : out STD_LOGIC;
Ram2WE : out STD_LOGIC;
Ram2EN : out STD_LOGIC;
LED_output : out std_logic_vector(15 downto 0);
ledseg1: out std_logic_vector(6 downto 0);
ledseg2: out std_logic_vector(6 downto 0);
KEY16_INPUT: in std_logic_vector(4 downto 0);
CLK_0: in std_logic; -- must 50M
-- vga port
R: out std_logic_vector(2 downto 0) := "000";
G: out std_logic_vector(2 downto 0) := "000";
B: out std_logic_vector(2 downto 0) := "000";
Hs: out std_logic := '0';
Vs: out std_logic := '0';
flash_byte : out std_logic;
flash_vpen : out std_logic;
flash_ce : out std_logic;
flash_oe : out std_logic;
flash_we : out std_logic;
flash_rp : out std_logic;
flash_addr : out std_logic_vector(22 downto 1);
flash_data : inout std_logic_vector(15 downto 0);
serialWRN : out STD_LOGIC;
serialRDN : out STD_LOGIC;
DATAREADY : in STD_LOGIC;
serialTSRE : in STD_LOGIC;
serialTBRE : in STD_LOGIC;
basicDatabus : inout STD_LOGIC_VECTOR(7 downto 0);
--ram1EN : out STD_LOGIC;
-- keyboard
keydatain: in std_logic;
keyclkin: in std_logic
);
end CPU;
architecture Behavioral of CPU is
--IF
component PCReg is
Port ( Input : in Int16;
Output : out Int16;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
PCWrite : in STD_LOGIC);
end component;
component Mux is
Port ( choice : in STD_LOGIC_VECTOR (1 downto 0);
Input1 : in Int16;
Input2 : in Int16;
Input3 : in Int16;
Output : out Int16);
end component;
component Mux2 is
Port ( choice : in STD_LOGIC;
Input1 : in STD_LOGIC_VECTOR (15 downto 0);
Input2 : in STD_LOGIC_VECTOR (15 downto 0);
Output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component Add is
Port ( Input1 : in Int16;
Input2 : in Int16;
Output : out Int16);
end component;
-- component InstructionMem is
-- Port (
-- rst : in std_logic;
-- clk : in std_logic;
-- Address : in Int16;
-- Data : out Int16;
-- ramdata : INOUT std_logic_vector(15 downto 0);
-- ramaddr : OUT std_logic_vector(17 downto 0);
-- OE : OUT std_logic;
-- WE : OUT std_logic;
-- EN : OUT std_logic
-- );
-- end component;
component IF_ID is
Port ( Instruction_in : in Int16;
Instruction_out : out Int16;
PC_in : in Int16;
PC_out : out Int16;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteIn : in STD_LOGIC);
end component;
--ID
component Decoder is
Port ( Instruction : in STD_LOGIC_VECTOR (15 downto 0);
Op : out STD_LOGIC_VECTOR (4 downto 0);
Reg1 : out STD_LOGIC_VECTOR (3 downto 0);
Reg2 : out STD_LOGIC_VECTOR (3 downto 0);
Reg3 : out STD_LOGIC_VECTOR (3 downto 0);
Imm : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component Controller is
Port ( Op : in STD_LOGIC_VECTOR (4 downto 0);
rst : in STD_LOGIC;
ALUop : out STD_LOGIC_VECTOR (2 downto 0);
ALUsrc : out STD_LOGIC;
TType : out STD_LOGIC;
TWrite : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
MemtoReg : out STD_LOGIC;
RegWrite: out STD_LOGIC;
ret: out std_logic);
end component;
component BranchSelector is
Port ( Op : in STD_LOGIC_VECTOR (4 downto 0);
RegInput : in STD_LOGIC_VECTOR (15 downto 0);
T : in STD_LOGIC;
Branch : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component RegFile is
Port ( ReadAddress1 : in STD_LOGIC_VECTOR (3 downto 0);
ReadAddress2 : in STD_LOGIC_VECTOR (3 downto 0);
WriteAddress : in STD_LOGIC_VECTOR (3 downto 0);
WriteData : in STD_LOGIC_VECTOR (15 downto 0);
PCinput: in STD_LOGIC_VECTOR (15 downto 0);
Reg1 : out STD_LOGIC_VECTOR (15 downto 0);
Reg2 : out STD_LOGIC_VECTOR (15 downto 0);
RegWrite : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sel: in std_logic_vector(3 downto 0);
LED_output: out std_logic_vector(15 downto 0);
debug: in std_logic_vector(15 downto 0);
vga_reg1: out std_logic_vector(15 downto 0)
);
end component;
component RiskChecker is
Port ( PCWrite : out STD_LOGIC;
IFIDWrite : out STD_LOGIC;
ControlRst : out STD_LOGIC;
IDEX_MemWrite : in STD_LOGIC;
IDEX_W : in Int4;
IFID_R1 : in Int4;
IFID_R2 : in Int4;
op : in Int5;
forwardBEQZ: out std_logic_vector(1 downto 0);
EXMEM_W : in Int4
);
end component;
component ID_EX is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteIn : in STD_LOGIC;
ALUopInput : in STD_LOGIC_VECTOR (2 downto 0);
ALUsrcInput : in STD_LOGIC;
TTypeInput : in STD_LOGIC;
TWriteInput : in STD_LOGIC;
MemReadInput : in STD_LOGIC;
MemWriteInput : in STD_LOGIC;
MemtoRegInput : in STD_LOGIC;
ALUopOutput : out STD_LOGIC_VECTOR (2 downto 0);
ALUsrcOutput : out STD_LOGIC;
TTypeOutput : out STD_LOGIC;
TWriteOutput : out STD_LOGIC;
MemReadOutput : out STD_LOGIC;
MemWriteOutput : out STD_LOGIC;
MemtoRegOutput : out STD_LOGIC;
RegWriteInput: in STD_LOGIC;
RegWriteOutput: out STD_LOGIC;
DataInput1 : in STD_LOGIC_VECTOR (15 downto 0);
DataInput2 : in STD_LOGIC_VECTOR (15 downto 0);
ImmediateInput : in STD_LOGIC_VECTOR (15 downto 0);
RegResult: out Int16;
ALUdata1 : out STD_LOGIC_VECTOR (15 downto 0);
ALUdata2 : out STD_LOGIC_VECTOR (15 downto 0);
RegReadInput1 : in STD_LOGIC_VECTOR (3 downto 0);
RegReadInput2 : in STD_LOGIC_VECTOR (3 downto 0);
RegWriteToInput : in STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput1 : out STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput2 : out STD_LOGIC_VECTOR (3 downto 0);
RegWriteToOutput : out STD_LOGIC_VECTOR (3 downto 0);
retinput: in std_logic;
retoutput: out std_logic
);
end component;
--EX
component ALU is
Port ( Input1 : in STD_LOGIC_VECTOR (15 downto 0);
Input2 : in STD_LOGIC_VECTOR (15 downto 0);
Output : out STD_LOGIC_VECTOR (15 downto 0);
ALUop : in STD_LOGIC_VECTOR (2 downto 0));
end component;
component TReg is
Port ( Input : in STD_LOGIC_VECTOR (15 downto 0);
TType : in STD_LOGIC;
TWrite : in STD_LOGIC;
T : out STD_LOGIC);
end component;
component Passer is
Port (
IDEX_alusrc: in std_logic;
EXMEM_RegWrite : in STD_LOGIC;
MEMWB_RegWrite : in STD_LOGIC;
EXMEM_W : in STD_LOGIC_VECTOR (3 downto 0);
MEMWB_W : in STD_LOGIC_VECTOR (3 downto 0);
IDEX_R1 : in STD_LOGIC_VECTOR (3 downto 0);
IDEX_R2 : in STD_LOGIC_VECTOR (3 downto 0);
ForwardA : out STD_LOGIC_VECTOR (1 downto 0);
ForwardB : out STD_LOGIC_VECTOR (1 downto 0);
ForwardC : out STD_LOGIC_VECTOR (1 downto 0));
end component;
component EX_MEM is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteIn : in STD_LOGIC;
MemReadInput : in STD_LOGIC;
MemWriteInput : in STD_LOGIC;
MemtoRegInput : in STD_LOGIC;
RegWriteInput: in STD_LOGIC;
RegWriteOutput: out STD_LOGIC;
MemReadOutput : out STD_LOGIC;
MemWriteOutput : out STD_LOGIC;
MemtoRegOutput : out STD_LOGIC;
RegResultInput: in Int16;
RegResultOutput: out Int16;
DataInput : in STD_LOGIC_VECTOR (15 downto 0);
DataOutput : out STD_LOGIC_VECTOR (15 downto 0);
RegReadInput1 : in STD_LOGIC_VECTOR (3 downto 0);
RegReadInput2 : in STD_LOGIC_VECTOR (3 downto 0);
RegWriteToInput : in STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput1 : out STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput2 : out STD_LOGIC_VECTOR (3 downto 0);
RegWriteToOutput : out STD_LOGIC_VECTOR (3 downto 0);
retinput: in std_logic;
retoutput: out std_logic
);
end component;
-- MEM
-- component DataMem is
-- Port ( Address : in STD_LOGIC_VECTOR (15 downto 0);
-- Input : in STD_LOGIC_VECTOR (15 downto 0);
-- Output : out STD_LOGIC_VECTOR (15 downto 0);
-- MemWrite : in STD_LOGIC;
-- MemRead : in STD_LOGIC);
-- end component;
component MEM_WB is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteIn : in STD_LOGIC;
MemtoRegInput : in STD_LOGIC;
MemtoRegOutput : out STD_LOGIC;
RegWriteInput: in STD_LOGIC;
RegWriteOutput: out STD_LOGIC;
AluResultInput : in STD_LOGIC_VECTOR (15 downto 0);
AluResultOutput : out STD_LOGIC_VECTOR (15 downto 0);
MemResultInput: in STD_LOGIC_VECTOR (15 downto 0);
MemResultOutput: out STD_LOGIC_VECTOR (15 downto 0);
RegReadInput1 : in STD_LOGIC_VECTOR (3 downto 0);
RegReadInput2 : in STD_LOGIC_VECTOR (3 downto 0);
RegWriteToInput : in STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput1 : out STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput2 : out STD_LOGIC_VECTOR (3 downto 0);
RegWriteToOutput : out STD_LOGIC_VECTOR (3 downto 0);
retinput: in std_logic;
retoutput: out std_logic
);
end component;
component divClk is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
clk0 : out STD_LOGIC);
end component;
component LED_seg7 is
Port(
input : in STD_LOGIC_VECTOR (3 downto 0);
output : out STD_LOGIC_VECTOR (6 downto 0)
);
end component;
-- component VGA_top is
-- port(
-- pc: in std_logic_vector(15 downto 0);
-- control: in std_logic_vector(15 downto 0);
-- vga_reg1: in std_logic_vector(15 downto 0);
-- CLK_0: in std_logic; -- must 50M
-- clk_out: out std_logic; -- used to sync
-- reset: in std_logic;
-- -- vga port
-- R: out std_logic_vector(2 downto 0) := "000";
-- G: out std_logic_vector(2 downto 0) := "000";
-- B: out std_logic_vector(2 downto 0) := "000";
-- Hs: out std_logic := '0';
-- Vs: out std_logic := '0'
-- );
-- end component;
component VGA_play
Port(
-- common port
CLK_0: in std_logic; -- must 50M
clkout: out std_logic; -- used to sync
reset: in std_logic;
-- vga port
R: out std_logic_vector(2 downto 0) := "000";
G: out std_logic_vector(2 downto 0) := "000";
B: out std_logic_vector(2 downto 0) := "000";
Hs: out std_logic := '0';
Vs: out std_logic := '0';
-- fifo memory
wctrl: in std_logic_vector(0 downto 0); -- 1 is write
waddr: in std_logic_vector(10 downto 0);
wdata : in std_logic_vector(7 downto 0)
);
end component;
COMPONENT MemoryTop
PORT(
address1 : IN std_logic_vector(15 downto 0);
address2 : IN std_logic_vector(15 downto 0);
clock : IN std_logic;
dataInput : IN std_logic_vector(15 downto 0);
MemWrite : IN std_logic;
MemRead : IN std_logic;
serial_dataready : IN std_logic;
serial_tsre : IN std_logic;
serial_tbre : IN std_logic;
reset : IN std_logic;
extendDatabus : INOUT std_logic_vector(15 downto 0);
flash_data : INOUT std_logic_vector(15 downto 0);
basicdatabus : INOUT std_logic_vector(7 downto 0);
output1 : OUT std_logic_vector(15 downto 0);
output2 : OUT std_logic_vector(15 downto 0);
cpuclock : OUT std_logic;
memoryAddress : OUT std_logic_vector(17 downto 0);
memoryEN : OUT std_logic;
memoryOE : OUT std_logic;
memoryRW : OUT std_logic;
flash_byte : OUT std_logic;
flash_vpen : OUT std_logic;
flash_ce : OUT std_logic;
flash_oe : OUT std_logic;
flash_we : OUT std_logic;
flash_rp : OUT std_logic;
flash_addr : OUT std_logic_vector(22 downto 1);
serial_wrn : OUT std_logic;
serial_rdn : OUT std_logic;
ram1_en : OUT std_logic;
Keyboard_Data : in std_logic_vector(7 downto 0);
Keyboard_Dataready : in std_logic;
Keyboard_wrn : out std_logic;
VGA_addr : out std_logic_vector(10 downto 0);
VGA_write : out std_LOGIC_vector(0 downto 0);
VGA_char : out std_logic_vector(7 downto 0)
);
END COMPONENT;
-------------------------------------
-- KeyTop
component KeyTop
port(
datain,clkin,clk50,rst_in: in std_logic;
dataready_out: out std_logic;
datareceived: in std_logic;
out_char: out std_logic_vector(7 downto 0)
);
end component;
signal pcreg_input: Int16:= Int16_Zero;
signal pcreg_output: Int16:= Int16_Zero;
signal pc_add4: Int16:= Int16_Zero;
signal pc_imm: Int16:= Int16_Zero;
-- signal pc_reg: Int16:= Int16_Zero;
signal instmem_data: Int16:= Int16_Zero;
signal IFID_inst_out: Int16:= Int16_Zero;
signal IFID_pc_out: Int16:= Int16_Zero;
signal IFID_writein: std_logic:= '1';
signal decoder_op: Int5 := Int5_Zero;
signal decoder_reg1: Int4 := Int4_One;
signal decoder_reg2: Int4 := Int4_One;
signal decoder_reg3: Int4 := Int4_One;
signal decoder_imm: Int16 := Int16_Zero;
signal controller_rst: std_logic := '0';
signal regfile_reg1: Int16:= Int16_Zero;
signal regfile_reg2: Int16:= Int16_Zero;
signal regfile_writedata: Int16:= Int16_Zero;
signal IDEX_aluop: Int3 := Int3_Zero;
signal IDEX_alusrc: std_logic:= '0';
signal IDEX_ttype: std_logic:= '0';
signal IDEX_twrite: std_logic:= '0';
signal IDEX_memread: std_logic:= '0';
signal IDEX_memwrite: std_logic:= '0';
signal IDEX_memtoreg: std_logic:= '0';
signal IDEX_regwrite: std_logic:= '0';
signal IDEX_aludata1: Int16 := Int16_Zero;
signal IDEX_aludata2: Int16 := Int16_Zero;
signal IDEX_regread1: Int4 := Int4_One;
signal IDEX_regread2: Int4 := Int4_One;
signal IDEX_regwriteto: Int4 := Int4_One;
signal IDEX_regresult: Int16:= Int16_Zero;
-- EXE
signal T_sign: std_logic:= '0';
signal alu_input1: Int16:= Int16_Zero;
signal alu_input2: Int16:= Int16_Zero;
signal alu_output: Int16:= Int16_Zero;
signal EXMEM_memread: std_logic:= '0';
signal EXMEM_memwrite: std_logic:= '0';
signal EXMEM_memtoreg: std_logic:= '0';
signal EXMEM_regwrite: std_logic:= '0';
signal EXMEM_regread1: Int4 := Int4_One;
signal EXMEM_regread2: Int4 := Int4_One;
signal EXMEM_regwriteto: Int4 := Int4_One;
signal EXMEM_data: Int16:= Int16_Zero;
signal EXMEM_regresult: Int16:= Int16_Zero;
signal EXMEM_regresultinput: int16:= Int16_Zero;
signal MEMWB_regwrite: std_logic:= '0';
signal MEMWB_regread1: Int4 := Int4_One;
signal MEMWB_regread2: Int4 := Int4_One;
signal MEMWB_regwriteto: Int4 := Int4_One;
signal MEMWB_aluresult: Int16:= Int16_Zero;
signal MEMWB_memresult: Int16:= Int16_Zero;
signal MEMWB_memtoreg: std_logic:= '0';
--MEM
signal DataMem_output: Int16:= Int16_Zero;
-- control signal
signal pcwrite: std_logic:= '1';
signal branch: std_logic_vector(1 downto 0):= "00";
signal aluop: Int3:= Int3_Zero;
signal alusrc: std_logic:= '0';
signal ttype: std_logic:= '0';
signal twrite: std_logic:= '0';
signal memread: std_logic:= '0';
signal memwrite: std_logic:= '0';
signal memtoreg: std_logic:= '0';
signal regwrite: std_logic:= '0';
signal forwardA: std_logic_vector(1 downto 0):= "00";
signal forwardB: std_logic_vector(1 downto 0):= "00";
signal forwardC: std_logic_vector(1 downto 0):= "00";
signal forwardBEQZ: std_logic_vector(1 downto 0):= "00";
signal BranchReg: Int16:= Int16_Zero;
signal clk25: std_logic:='0';
signal clk0: std_logic:='0';
signal clk_out : std_logic:= '0';
signal fuck: std_logic_vector(15 downto 0):=Int16_Zero;
signal control_temp: std_logic_vector(15 downto 0):=Int16_Zero;
signal vga_reg1: std_logic_vector(15 downto 0):=Int16_Zero;
signal debug_serialwrn: std_logic;
signal debug_serialrdn: std_logic;
signal ret: std_logic:='0';
signal IDEX_ret: std_logic:='0';
signal EXMEM_ret: std_logic:='0';
signal MEMWB_ret: std_logic:='0';
signal clk0_S: std_logic:='0';
signal clk1 : std_logic:='0';
signal keyb_data: std_logic_vector(7 downto 0);
signal Keyb_dataready: std_logic;
signal Keyb_wrn: std_logic;
signal vgawctrl: std_logic_vector(0 downto 0); -- 1 is write
signal vgawaddr: std_logic_vector(10 downto 0);
signal vgawdata: std_logic_vector(7 downto 0);
begin
PCReg_1: PCReg port map(
Input => pcreg_input,
Output => pcreg_output,
clk => clk0,
rst => rst,
PCWrite => pcwrite
);
Mux_PC: Mux port map(
choice => branch,
Input1 => pc_add4,
Input2 => pc_imm,
Input3 => regfile_reg1,
Output => pcreg_input
);
Add_PC: Add port map(
Input1 => pcreg_output,
Input2 => "0000000000000001",
Output => pc_add4
);
-- InstructionMem_1: InstructionMem port map(
-- clk => clk,
-- rst => rst,
-- Address => pcreg_output,
-- Data => instmem_data,
-- ramaddr => Ram1Addr,
-- ramdata => Ram1Data,
-- OE => Ram1OE,
-- WE => Ram1WE,
-- EN => Ram1EN
-- );
IF_ID_1: IF_ID port map(
Instruction_in => instmem_data,
Instruction_out => IFID_inst_out,
PC_in => pc_add4,
PC_out => IFID_pc_out,
clk => clk0,
rst => rst,
WriteIn => IFID_writein
);
Decoder_1: Decoder port map(
Instruction => IFID_inst_out,
Op => decoder_op,
Reg1 => decoder_reg1,
Reg2 => decoder_reg2,
Reg3 => decoder_reg3,
Imm => decoder_imm
);
Add_imm: Add port map(
Input1 => decoder_imm,
Input2 => pcreg_output,
Output => pc_imm
);
Controller_1: Controller port map(
Op => decoder_op,
rst => controller_rst,
ALUop => aluop,
ALUsrc => alusrc,
TType => ttype,
TWrite => twrite,
MemRead => memread,
MemWrite => memwrite,
MemToReg => memtoreg,
RegWrite => regwrite,
ret => ret
);
BranchSelector_1: BranchSelector port map(
Op => decoder_op,
RegInput => BranchReg,
T => T_sign,
Branch => branch
);
RegFile_1: RegFile port map(
ReadAddress1 => decoder_reg1,
ReadAddress2 => decoder_reg2,
WriteAddress => MEMWB_regwriteto,
WriteData => regfile_writedata,
pcinput => IFID_pc_out,
Reg1 => regfile_reg1,
Reg2 => regfile_reg2,
RegWrite => MEMWB_regwrite,
clk => clk0,
rst => rst,
sel => KEY16_INPUT(3 downto 0),
LED_output => LED_output,
debug => fuck,
vga_reg1 => vga_reg1
);
RiskChecker_1: RiskChecker port map(
op => decoder_op,
PCWrite => pcwrite,
IFIDWrite => IFID_writein,
ControlRst => controller_rst,
IDEX_MemWrite => IDEX_memwrite,
IDEX_W => IDEX_regwriteto,
IFID_R1 => decoder_reg1,
IFID_R2 => decoder_reg2,
forwardBEQZ => forwardBEQZ,
EXMEM_W => EXMEM_regwriteto
);
ID_EX_1: ID_EX port map(
clk => clk0,
rst => rst,
WriteIn => '1',
ALUopInput => aluop,
ALUsrcInput => alusrc,
TTypeInput => ttype,
TWriteInput => twrite,
MemReadInput => memread,
MemWriteInput => memwrite,
MemtoRegInput => memtoreg,
RegWriteInput => regwrite,
RegWriteOutput => IDEX_regwrite,
ALUopOutput => IDEX_aluop,
ALUsrcOutput => IDEX_alusrc,
TTypeOutput => IDEX_ttype,
TWriteOutput => IDEX_twrite,
MemReadOutput => IDEX_memread,
MemWriteOutput => IDEX_memwrite,
MemtoRegOutput => IDEX_memtoreg,
DataInput1 => regfile_reg1,
DataInput2 => regfile_reg2,
ImmediateInput => decoder_imm,
ALUdata1 => IDEX_aludata1,
ALUdata2 => IDEX_aludata2,
RegResult => IDEX_regresult,
RegReadInput1 => decoder_reg1,
RegReadInput2 => decoder_reg2,
RegWriteToInput => decoder_reg3,
RegReadOutput1 => IDEX_regread1,
RegReadOutput2 => IDEX_regread2,
RegWriteToOutput => IDEX_regwriteto,
retinput => ret,
retoutput => IDEX_ret
);
ALU_1: ALU port map(
Input1 => alu_input1,
Input2 => alu_input2,
Output => alu_output,
ALUOp => IDEX_aluop
);
TReg_1: TReg port map(
Input => alu_output,
TType => IDEX_ttype,
TWrite => IDEX_twrite,
T => T_sign
);
Mux_alusrc1: Mux port map(
choice => forwardA,
Input1 => IDEX_aludata1,
Input2 => regfile_writedata,
Input3 => EXMEM_data,
Output => alu_input1
);
Mux_alusrc2: Mux port map(
choice => forwardB,
Input1 => IDEX_aludata2,
Input2 => regfile_writedata,
Input3 => EXMEM_data,
Output => alu_input2
);
Mux_BEQZ: Mux port map(
choice => forwardBEQZ,
Input1 => regfile_reg1,
Input2 => alu_output,
Input3 => EXMEM_data,
Output => BranchReg
);
Mux_regsultsrc: Mux port map(
choice => forwardC,
Input1 => IDEX_regresult,
Input2 => regfile_writedata,
Input3 => EXMEM_data,
Output => EXMEM_regresultinput
);
Passer_1: Passer port map(
IDEX_alusrc => IDEX_alusrc,
EXMEM_RegWrite => EXMEM_regwrite,
MEMWB_RegWrite => MEMWB_regwrite,
EXMEM_W => EXMEM_regwriteto,
MEMWB_W => MEMWB_regwriteto,
IDEX_R1 => IDEX_regread1,
IDEX_R2 => IDEX_regread2,
ForwardA => forwardA,
ForwardB => forwardB,
ForwardC => forwardC
);
EX_MEM_1: EX_MEM port map(
clk => clk0,
rst => rst,
WriteIn => '1',
MemReadInput => IDEX_memread,
MemWriteInput => IDEX_memwrite,
MemtoRegInput => IDEX_memtoreg,
MemReadOutput => EXMEM_memread,
MemWriteOutput => EXMEM_memwrite,
MemtoRegOutput => EXMEM_memtoreg,
RegWriteInput => IDEX_regwrite,
RegWriteOutput => EXMEM_regwrite,
DataInput => alu_output,
DataOutput => EXMEM_data,
RegResultInput => EXMEM_regresultinput,
RegResultOutput => EXMEM_regresult,
RegReadInput1 => IDEX_regread1,
RegReadInput2 => IDEX_regread2,
RegWriteToInput => IDEX_regwriteto,
RegReadOutput1 => EXMEM_regread1,
RegReadOutput2 => EXMEM_regread2,
RegWriteToOutput => EXMEM_regwriteto,
retinput => IDEX_ret,
retoutput => EXMEM_ret
);
-- DataMem_1: DataMem port map(
-- Address => EXMEM_data,
-- Input => EXMEM_regresult,
-- Output => DataMem_output,
-- MemWrite => EXMEM_memwrite,
-- MemRead => EXMEM_memread
-- );
MEM_WB_1: MEM_WB port map(
clk => clk0,
rst => rst,
WriteIn => '1',
RegWriteInput => EXMEM_regwrite,
RegWriteOutput => MEMWB_regwrite,
MemtoRegInput => EXMEM_memtoreg,
MemtoRegOutput => MEMWB_memtoreg,
AluResultInput => EXMEM_data,
AluResultOutput => MEMWB_aluresult,
MemResultInput => DataMem_output,
MemResultOutput => MEMWB_memresult,
RegReadInput1 => EXMEM_regread1,
RegReadInput2 => EXMEM_regread2,
RegWriteToInput => EXMEM_regwriteto,
RegReadOutput1 => MEMWB_regread1,
RegReadOutput2 => MEMWB_regread2,
RegWriteToOutput => MEMWB_regwriteto,
retinput => EXMEM_ret,
retoutput => MEMWB_ret
);
Mux_wb: Mux2 port map(
choice => MEMWB_memtoreg,
Input1 => MEMWB_aluresult,
Input2 => MEMWB_memresult,
Output => regfile_writedata
);
divClk_1: divClk port map(
rst => rst,
clk => clk_0,
clk0 => clk1
);
LED_left: LED_seg7 port map(
input => keyb_data(7 downto 4),
output => ledseg2
);
LED_right: LED_seg7 port map(
input => keyb_data(3 downto 0),
output => ledseg1
);
fuck <= alu_input1(3 downto 0) & alu_input2(3 downto 0) & alu_output(3 downto 0) & IDEX_aluop & '0';
--EXMEM_regwrite & EXMEM_regwriteto(2 downto 0) & IDEX_regread1 & IDEX_regread2 & ForwardA & ForwardB;
control_temp <= EXMEM_memwrite & EXMEM_memread & debug_serialwrn & debug_serialrdn & '0' & controller_rst & aluop & alusrc & ttype & twrite & memread & memwrite & memtoreg & regwrite;
-- Inst_VGA_top: VGA_top PORT MAP(
-- pc => pcreg_output,
-- control => control_temp,
-- vga_reg1 => EXMEM_data,
-- CLK_0 => CLK_0,
-- clk_out => clk25,
-- reset => rst,
-- R => R,
-- G => G,
-- B => B,
-- Hs => Hs,
-- Vs => Vs
-- );
Inst_VGA_play: VGA_play PORT MAP(
wctrl => vgawctrl,
waddr => vgawaddr,
wdata => vgawdata,
CLK_0 => CLK_0,
clkout => clk25,
reset => rst,
R => R,
G => G,
B => B,
Hs => Hs,
Vs => Vs
);
clk0 <= clk0_s and (not MEMWB_ret);
Inst_MemoryTop: MemoryTop PORT MAP(
address1 => pcreg_output,
output1 => instmem_data,
address2 => EXMEM_data,
output2 => DataMem_output,
clock => clk_out,
cpuclock => clk0_S,
dataInput => EXMEM_regresult,
MemWrite => EXMEM_memwrite,
MemRead => EXMEM_memread,
memoryAddress => Ram2Addr,
extendDatabus => Ram2Data,
memoryEN => Ram2EN,
memoryOE => Ram2OE,
memoryRW => Ram2WE,
flash_byte => flash_byte,
flash_vpen => flash_vpen,
flash_ce => flash_ce,
flash_oe => flash_oe,
flash_we => flash_we,
flash_rp => flash_rp,
flash_addr => flash_addr,
flash_data => flash_data,
serial_wrn => debug_serialwrn,
serial_rdn => debug_serialrdn,
serial_dataready => dataReady,
serial_tsre => serialTSRE,
serial_tbre => serialTBRE,
basicdatabus => Ram1Data(7 downto 0),
ram1_en => Ram1EN,
reset => rst,
Keyboard_Data => keyb_data,
Keyboard_Dataready => keyb_dataready,
Keyboard_wrn => keyb_wrn,
VGA_addr => vgawaddr,
VGA_write => vgawctrl,
VGA_char => vgawdata
);
serialwrn <= debug_serialwrn;
serialrdn <= debug_serialrdn;
board: KeyTop
port map(
datain => keydatain,
clkin => keyclkin,
clk50 => clk_0,
rst_in => rst,
dataready_out => keyb_dataready,
datareceived => keyb_wrn,
out_char => keyb_data
);
with KEY16_INPUT(4) select
clk_out <= clk when '0', clk1 when others;
Ram1OE <= '1';
Ram1WE <= '1';
end Behavioral;
|
mit
|
e35723d81c73086001927ab3001a329a
| 0.63569 | 2.994139 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/VGA/ipcore_dir/blk_mem_gen_v7_3/simulation/blk_mem_gen_v7_3_synth.vhd
| 2 | 7,931 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
mit
|
1be994be3fa7142916c4ddce63786ebf
| 0.56525 | 3.719981 | false | false | false | false |
gregani/la16fw
|
clock.vhd
| 1 | 3,843 |
--
-- This file is part of the la16fw project.
--
-- Copyright (C) 2014-2015 Gregor Anich
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
generic(
CLK_FAST_DIV : integer;
CLK_FAST_MUL : integer;
STARTUP_WAIT : boolean := false
);
port(
clk_in : in std_logic;
reset : in std_logic;
clk : out std_logic;
clk_fb : in std_logic;
clk_fast : out std_logic;
locked : out std_logic
);
end clock;
architecture behavioral of clock is
begin
-- DCM_SP: Digital Clock Manager Circuit
-- Spartan-3A
-- Xilinx HDL Language Template, version 14.7
DCM_SP_inst : DCM_SP
generic map(
CLKDV_DIVIDE => 12.0, -- 4MHz on CLKDV
CLKFX_DIVIDE => CLK_FAST_DIV,
CLKFX_MULTIPLY => CLK_FAST_MUL, -- 100MHz on CLKFX
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.83333333333333333, -- 48MHz
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE"
CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X"
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or an integer from 0 to 15
DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
STARTUP_WAIT => TRUE--STARTUP_WAIT -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
)
port map(
CLKIN => clk_in, -- 48MHz clock input (from IBUFG, BUFG or DCM)
RST => reset, -- DCM asynchronous reset input
CLK0 => clk, -- 0 degree DCM CLK ouptput
CLK90 => open, -- 90 degree DCM CLK output
CLK180 => open, -- 180 degree DCM CLK output
CLK270 => open, -- 270 degree DCM CLK output
CLK2X => open, -- 2X DCM CLK output
CLK2X180 => open, -- 2X, 180 degree DCM CLK out
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
CLKFX => clk_fast, -- DCM CLK synthesis out (M/D)
CLKFX180 => open, -- 180 degree CLK synthesis out
LOCKED => locked, -- DCM LOCK status output
STATUS => open, -- 8-bit DCM status bits output
CLKFB => clk_fb, -- DCM clock feedback
PSCLK => '0', -- Dynamic phase adjust clock input
PSEN => '0', -- Dynamic phase adjust enable input
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
PSDONE => open -- Dynamic phase adjust done output
);
end behavioral;
|
gpl-2.0
|
96047c948fa68bbe0cf42241d985b66b
| 0.562061 | 4.223077 | false | false | false | false |
6769/VHDL
|
Lab_5/__FromTextBook/DiceGame.vhd
| 1 | 1,297 |
entity DiceGame is
port(Rb, Reset, CLK: in bit;
Sum: in integer range 2 to 12;
Roll, Win, Lose: out bit);
end DiceGame;
architecture DiceBehave of DiceGame is
signal State, Nextstate: integer range 0 to 5;
signal Point: integer range 2 to 12;
signal Sp: bit;
begin
process(Rb, Reset, Sum, State)
begin
Sp <= '0'; Roll <= '0'; Win <= '0'; Lose <= '0';
case State is
when 0 => if Rb = '1' then Nextstate <= 1; end if;
when 1 =>
if Rb = '1' then Roll <= '1';
elsif Sum = 7 or Sum = 11 then Nextstate <= 2;
elsif Sum = 2 or Sum = 3 or Sum =12 then Nextstate <= 3;
else Sp <= '1'; Nextstate <= 4;
end if;
when 2 => Win <= '1';
if Reset = '1' then Nextstate <= 0; end if;
when 3 => Lose <= '1';
if Reset = '1' then Nextstate <= 0; end if;
when 4 => if Rb = '1' then Nextstate <= 5; end if;
when 5 =>
if Rb = '1' then Roll <= '1';
elsif Sum = Point then Nextstate <= 2;
elsif Sum = 7 then Nextstate <= 3;
else Nextstate <= 4;
end if;
end case;
end process;
process(CLK)
begin
if CLK'event and CLK = '1' then
State <= Nextstate;
if Sp = '1' then Point <= Sum; end if;
end if;
end process;
end DiceBehave;
|
gpl-2.0
|
56d7cbaf99c1a850eb05cc750f8971b4
| 0.537394 | 3.467914 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/CPU/Controller.vhd
| 1 | 2,775 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:30:29 11/21/2013
-- Design Name:
-- Module Name: Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Controller is
Port(
Op : in STD_LOGIC_VECTOR(4 downto 0);
rst : in STD_LOGIC;
ALUop : out STD_LOGIC_VECTOR(2 downto 0);
ALUsrc : out STD_LOGIC;
TType : out STD_LOGIC;
TWrite : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
MemtoReg : out STD_LOGIC;
RegWrite: out STD_LOGIC;
ret: out std_logic
);
end Controller;
architecture Behavioral of Controller is
begin
process(Op, rst)
begin
if rst = '0' then
ALUop <= "000";
TType <= '0';
MemRead <= '0';
MemWrite <= '0';
MemtoReg <= '0';
RegWrite <= '0';
ret <= '0';
else
case Op is
when "01000" | "01001" | "01101" | "10010" =>
ALUop <= "001";
when "00101" =>
ALUop <= "010";
when "00110" =>
ALUop <= "011";
when "00111" =>
ALUop <= "100";
when "01010" =>
ALUop <= "101";
when "01011" =>
ALUop <= "110";
when others =>
ALUop <= "000";
end case;
if Op = "01010" or Op = "01011" or (Op >= "01110" and Op <= "10111") then
ALUsrc <= '1';
else
ALUsrc <= '0';
end if;
if Op = "01001" then
TType <= '1';
else
TType <= '0';
end if;
if Op = "01000" or Op = "01001" or Op = "10010" then
TWrite <= '1';
else
TWrite <= '0';
end if;
if Op = "01111" or Op = "10110" then
MemRead <= '1';
else
MemRead <= '0';
end if;
if Op = "10000" or Op = "10111" then
MemWrite <= '1';
else
MemWrite <= '0';
end if;
if Op = "01000" or Op = "10110" then
MemtoReg <= '1';
else
MemtoReg <= '0';
end if;
if (Op >= "00001" and Op <= "00111") or
(Op >= "01010" and Op <= "01111") or (Op = "10001") or
(Op >= "10011" and Op <= "10110") then
RegWrite <= '1';
else
RegWrite <= '0';
end if;
if Op = "11111" then
ret <= '1';
else
ret <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
920c7127edbe5a214a354aab3c0b0e11
| 0.517117 | 3.13914 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/qspi_core_interface.vhd
| 1 | 153,390 |
-------------------------------------------------------------------------------
-- qspi_core_interface Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_core_interface.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI bus.
--
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_quad_spi.
--
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author: SK
-- ~~~~~~
-- - First version of axi_spi.
-- ^^^^^^
-- ~~~~~~
-- SK 11/12/11 -- created v2.00.a version
-- ^^^^^^
-- 1. Update the core with SPI perormance. Removed idle time between each SPI transfer.
-- 2. added async FIFO for transmit and receive FIFO.
-- 3. added CDC logic for FIFO exists and no FIFO mode.
-- 4. added support of AXI Lite, AXI4 full and XIP mode support.
-- ~~~~~~
--
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.proc_common_pkg.max2;
use proc_common_v4_0.family_support.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.srl_fifo_f;
use proc_common_v4_0.async_fifo_fg;-- 1/8/2013
library interrupt_control_v3_0;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
-------------------------------------------------------------------------------
entity qspi_core_interface is
generic(
C_FAMILY : string;
C_SUB_FAMILY : string;
C_S_AXI_DATA_WIDTH : integer;
----------------------
-- local parameters
C_NUM_CE_SIGNALS : integer;
----------------------
-- SPI parameters
--C_AXI4_CLK_PS : integer;
--C_EXT_SPI_CLK_PS : integer;
C_FIFO_DEPTH : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_SPI_MODE : integer;
C_USE_STARTUP : integer;
C_SPI_MEMORY : integer;
C_TYPE_OF_AXI4_INTERFACE : integer;
----------------------
-- local constants
C_FIFO_EXIST : integer;
C_SPI_NUM_BITS_REG : integer;
C_OCCUPANCY_NUM_BITS : integer;
----------------------
-- local constants
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE;
----------------------
-- local constants
C_SPICR_REG_WIDTH : integer;
C_SPISR_REG_WIDTH : integer
);
port(
EXT_SPI_CLK : in std_logic;
------------------------------------------------
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
------------------------------------------------
Bus2IP_BE : in std_logic_vector(0 to ((C_S_AXI_DATA_WIDTH/8)-1));
Bus2IP_RdCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_WrCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
------------------------------------------------
IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_Error : out std_logic;
------------------------------------------------
burst_tr : in std_logic;
rready : in std_logic;
WVALID : in std_logic;
--SPI Ports
SCK_I : in std_logic;
SCK_O : out std_logic;
SCK_T : out std_logic;
------------------------------------------------
IO0_I : in std_logic;
IO0_O : out std_logic;
IO0_T : out std_logic;
------------------------------------------------
IO1_I : in std_logic;
IO1_O : out std_logic;
IO1_T : out std_logic;
------------------------------------------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
------------------------------------------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
------------------------------------------------
SPISEL : in std_logic;
------------------------------------------------
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
------------------------------------------------
IP2INTC_Irpt : out std_logic
------------------------------------------------
);
end entity qspi_core_interface;
-------------------------------------------------------------------------------
------------
architecture imp of qspi_core_interface is
------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- function definition
----------------------
-------------------------------------------------------------------------------
-- constant definition
constant NEW_LOGIC : integer := 0;
-- These constants are indices into the "CE" arrays for the various registers.
constant INTR_LO : natural := 0;
constant INTR_HI : natural := 15;
constant SWRESET : natural := 16; -- at address C_BASEADDR + 40 h
constant SPICR : natural := 24; -- 17; -- at address C_BASEADDR + 60 h
constant SPISR : natural := 25; -- 18;
constant SPIDTR : natural := 26; -- 19;
constant SPIDRR : natural := 27; -- 20;
constant SPISSR : natural := 28; -- 21;
constant SPITFOR : natural := 29; -- 22;
constant SPIRFOR : natural := 30; -- 23; -- at address C_BASEADDR + 78 h
constant REG_HOLE : natural := 31; -- 24; -- at address C_BASEADDR + 7C h
--SPI MODULE SIGNALS
signal spiXfer_done_int : std_logic;
signal dtr_underrun_int : std_logic;
signal modf_strobe_int : std_logic;
signal slave_MODF_strobe_int : std_logic;
--OR REGISTER/FIFO SIGNALS
--TO/FROM REG/FIFO DATA
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--Extra bit required for signal Register_Data_ctrl
signal register_Data_cntrl_int :std_logic_vector(0 to (C_SPI_NUM_BITS_REG+1));
signal register_Data_slvsel_int:std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_SPICR_Data_int :std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
signal IP2Bus_SPISR_Data_int :std_logic_vector(0 to (C_SPISR_REG_WIDTH-1));
signal IP2Bus_Receive_Reg_Data_int :std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal IP2Bus_Data_received_int:
std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal IP2Bus_SPISSR_Data_int : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
--STATUS REGISTER SIGNALS
signal sr_3_MODF_int : std_logic;
signal Tx_FIFO_Full_int : std_logic;
signal sr_5_Tx_Empty_int : std_logic;
signal sr_6_Rx_Full_int : std_logic;
signal Rc_FIFO_Empty_int : std_logic;
--RECEIVE AND TRANSMIT REGISTER SIGNALS
signal drr_Overrun_int : std_logic;
signal dtr_Underrun_strobe_int : std_logic;
--FIFO SIGNALS
signal rc_FIFO_Full_strobe_int : std_logic;
signal rc_FIFO_occ_Reversed_int :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_occ_Reversed_int_2 :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_Data_Out_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal sr_6_Rx_Full_int_1 : std_logic;
signal FIFO_Empty_rx_1 : std_logic;
signal FIFO_Empty_rx : std_logic;
signal data_Exists_RcFIFO_int : std_logic;
signal tx_FIFO_Empty_strobe_int : std_logic;
signal tx_FIFO_occ_Reversed_int : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal tx_FIFO_occ_Reversed_int_2 : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal data_Exists_TxFIFO_int : std_logic;
signal data_Exists_TxFIFO_int_1 : std_logic;
signal data_From_TxFIFO_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_FIFO_less_half_int : std_logic;
signal Tx_FIFO_Full_int_1 : std_logic;
signal FIFO_Empty_tx : std_logic;
signal data_From_TxFIFO_int_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_occ_msb : std_logic;
signal tx_occ_msb_1 : std_logic:= '0';
signal tx_occ_msb_2 : std_logic;
signal tx_occ_msb_3 : std_logic;
signal tx_occ_msb_4 : std_logic;
signal reset_TxFIFO_ptr_int : std_logic;
signal reset_RcFIFO_ptr_int : std_logic;
signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal ip2Bus_Data_Reg_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_occupancy_int: std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_SS_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
-- interface between signals on instance basis
signal bus2IP_Reset_int : std_logic;
signal bus2IP_Data_for_interrupt_core : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2Bus_Error_int : std_logic;
signal ip2Bus_WrAck_int : std_logic;-- := '0';
signal ip2Bus_RdAck_int : std_logic;-- := '0';
signal ip2Bus_IntrEvent_int : std_logic_vector
(0 to (C_IP_INTR_MODE_ARRAY'length-1));
signal transmit_ip2bus_error : std_logic;
signal receive_ip2bus_error : std_logic;
-- SOFT RESET SIGNALS
signal reset2ip_reset_int : std_logic;
signal rst_ip2bus_wrack : std_logic;
signal rst_ip2bus_error : std_logic;
signal rst_ip2bus_rdack : std_logic;
-- INTERRUPT SIGNALS
signal intr_ip2bus_data : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal intr_ip2bus_rdack : std_logic;
signal intr_ip2bus_wrack : std_logic;
signal intr_ip2bus_error : std_logic;
signal ip2bus_error_RdWr : std_logic;
--
signal wr_ce_reduce_ack_gen: std_logic;
--
signal rd_ce_reduce_ack_gen : std_logic;
--
signal control_bit_7_8_int : std_logic_vector(0 to 1);
signal spisel_pulse_o_int : std_logic;
signal spisel_d1_reg : std_logic;
signal Mst_N_Slv_mode : std_logic;
-----
signal bus2ip_intr_rdce : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_intr_wrce : std_logic_vector(INTR_LO to INTR_HI);
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal intr_controller_rd_ce_or_reduce : std_logic;
signal intr_controller_wr_ce_or_reduce : std_logic;
signal wr_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_WrAck_core_reg_d1 : std_logic;
signal ip2Bus_WrAck_core_reg : std_logic;
signal rd_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_RdAck_core_reg_d1 : std_logic;
signal ip2Bus_RdAck_core_reg : std_logic;
signal SPISR_0_CMD_Error_int : std_logic;
signal SPISR_1_LOOP_Back_Error_int : std_logic;
signal SPISR_2_MSB_Error_int : std_logic;
signal SPISR_3_Slave_Mode_Error_int : std_logic;
signal SPISR_4_CPOL_CPHA_Error_int : std_logic;
signal SPISR_Ext_SPISEL_slave_int : std_logic;
signal SPICR_5_TXFIFO_RST_int : std_logic;
-- signal SPICR_6_RXFIFO_RST_int : std_logic;
signal pr_state_idle_int : std_logic;
signal Quad_Phase_int : std_logic;
signal SPICR_0_LOOP_frm_axi :std_logic;
signal SPICR_0_LOOP_to_spi :std_logic;
signal SPICR_1_SPE_frm_axi :std_logic;
signal SPICR_1_SPE_to_spi :std_logic;
signal SPICR_2_MST_N_SLV_frm_axi :std_logic;
signal SPICR_2_MST_N_SLV_to_spi :std_logic;
signal SPICR_3_CPOL_frm_axi :std_logic;
signal SPICR_3_CPOL_to_spi :std_logic;
signal SPICR_4_CPHA_frm_axi :std_logic;
signal SPICR_4_CPHA_to_spi :std_logic;
signal SPICR_5_TXFIFO_frm_axi :std_logic;
signal SPICR_5_TXFIFO_to_spi :std_logic;
--signal SPICR_6_RXFIFO_RST_frm_axi:std_logic;
--signal SPICR_6_RXFIFO_RST_to_spi :std_logic;
signal SPICR_7_SS_frm_axi :std_logic;
signal SPICR_7_SS_to_spi :std_logic;
signal SPICR_8_TR_INHIBIT_frm_axi:std_logic;
signal SPICR_8_TR_INHIBIT_to_spi :std_logic;
signal SPICR_9_LSB_frm_axi :std_logic;
signal SPICR_9_LSB_to_spi :std_logic;
signal SPICR_bits_7_8_frm_spi :std_logic;
signal SPICR_bits_7_8_to_axi :std_logic;
signal Rx_FIFO_Empty : std_logic;
signal rx_fifo_full_to_axi_clk : std_logic;
signal tx_fifo_empty_to_axi_clk : std_logic;
signal tx_fifo_full : std_logic;
signal spisel_d1_reg_to_axi_clk : std_logic;
signal spicr_bits_7_8_frm_axi_clk : std_logic_vector(1 downto 0);
signal spicr_8_tr_inhibit_to_spi_clk : std_logic;
signal spicr_9_lsb_to_spi_clk : std_logic;
signal spicr_bits_7_8_to_spi_clk : std_logic_vector(0 to 1);
signal spicr_0_loop_frm_axi_clk : std_logic;
signal spicr_1_spe_frm_axi_clk : std_logic;
signal spicr_2_mst_n_slv_frm_axi_clk : std_logic;
signal spicr_3_cpol_frm_axi_clk : std_logic;
signal spicr_4_cpha_frm_axi_clk : std_logic;
signal spicr_5_txfifo_rst_frm_axi_clk : std_logic;
signal spicr_6_rxfifo_rst_frm_axi_clk : std_logic;
signal spicr_7_ss_frm_axi_clk : std_logic;
signal spicr_8_tr_inhibit_frm_axi_clk : std_logic;
signal spicr_9_lsb_frm_axi_clk : std_logic;
signal Tx_FIFO_wr_ack_1 : std_logic;
signal rst_to_spi_int : std_logic;
signal spicr_0_loop_to_spi_clk : std_logic;
signal spicr_1_spe_to_spi_clk : std_logic;
signal spicr_2_mas_n_slv_to_spi_clk : std_logic;
signal spicr_3_cpol_to_spi_clk : std_logic;
signal spicr_4_cpha_to_spi_clk : std_logic;
signal spicr_5_txfifo_rst_to_spi_clk : std_logic;
signal spicr_6_rxfifo_rst_to_spi_clk : std_logic;
signal spicr_7_ss_to_spi_clk : std_logic;
signal sr_3_modf_to_spi_clk : std_logic;
signal sr_3_modf_frm_axi_clk : std_logic;
signal data_from_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Bus2IP_WrCE_d1 : std_logic;
signal Bus2IP_WrCE_d2 : std_logic;
signal Bus2IP_WrCE_d3 : std_logic;
signal Bus2IP_WrCE_pulse_1 : std_logic;
signal Bus2IP_WrCE_pulse_2 : std_logic;
signal Bus2IP_WrCE_pulse_3 : std_logic;
signal data_to_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_fifo_wr_ack : std_logic;
-- signal ext_spi_clk : std_logic;
signal tx_fifo_rd_ack_open : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_almost_full : std_logic;
signal tx_fifo_almost_empty : std_logic;
signal tx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal c_wr_count_width : std_logic;
signal rx_fifo_wr_ack_open : std_logic;
signal data_from_rx_fifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal rx_fifo_rd_ack : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_almost_full : std_logic;
signal rx_fifo_almost_empty : std_logic;
signal rx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal SPISSR_frm_axi_clk : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal modf_strobe_frm_spi_clk : std_logic;
signal modf_strobe_to_axi_clk : std_logic;
signal dtr_underrun_frm_spi_clk : std_logic;
signal dtr_underrun_to_axi_clk : std_logic;
signal data_to_rx_fifo : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal spisel_d1_reg_frm_spi_clk : std_logic;
signal Mst_N_Slv_mode_frm_spi_clk: std_logic;
signal Mst_N_Slv_mode_to_axi_clk : std_logic;
signal SPICR_2_MST_N_SLV_to_spi_clk : std_logic;
signal spicr_5_txfifo_frm_axi_clk : std_logic;
signal spicr_5_txfifo_to_spi_clk: std_logic;
signal reset_RcFIFO_ptr_frm_axi_clk : std_logic;
-- signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal Data_To_Rx_FIFO_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal SPIXfer_done_Rx_Wr_en, SPIXfer_done_rd_tx_en: std_logic;
signal Tx_FIFO_Empty_SPISR_frm_spi_clk : std_logic;
signal Tx_FIFO_Empty_SPISR_to_axi_clk : std_logic;
signal Tx_FIFO_Empty_frm_spi_clk : std_logic;
signal Rx_FIFO_Full_frm_spi_clk : std_logic;
signal Rx_FIFO_Full_int,Rx_FIFO_Full_i,RX_one_less_than_full : std_logic;
signal updown_cnt_en_tx, updown_cnt_en_rx : std_logic;
signal TX_one_less_than_full : std_logic;
signal tx_cntr_xfer_done : std_logic;
signal Tx_FIFO_one_less_to_Empty, Tx_FIFO_Full_i: std_logic;
signal Tx_FIFO_Empty_i, Tx_FIFO_Empty_int : std_logic;
signal Tx_FIFO_Empty_frm_axi_clk : std_logic;
signal rx_fifo_empty_i : std_logic;
signal Rx_FIFO_Empty_int : std_logic;
signal IP2Bus_WrAck_1 : std_logic;
signal ip2Bus_WrAck_core_reg_1 : std_logic;
signal IP2Bus_RdAck_1 : std_logic;
signal ip2Bus_RdAck_core_reg_1 : std_logic;
signal IP2Bus_Error_1 : std_logic;
signal ip2Bus_Data_1 : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1)) ;
signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
signal rx_fifo_reset, tx_fifo_reset : std_logic;
signal reg_hole_wr_ack: std_logic;
signal reg_hole_rd_ack: std_logic;
signal read_ack_delay_1: std_logic;
signal read_ack_delay_2: std_logic;
signal read_ack_delay_3: std_logic;
signal read_ack_delay_4: std_logic;
signal read_ack_delay_5: std_logic;
signal read_ack_delay_6: std_logic;
signal read_ack_delay_7: std_logic;
signal read_ack_delay_8: std_logic;
signal write_ack_delay_1: std_logic;
signal write_ack_delay_2: std_logic;
signal write_ack_delay_3: std_logic;
signal write_ack_delay_4: std_logic;
signal write_ack_delay_5: std_logic;
signal write_ack_delay_6: std_logic;
signal write_ack_delay_7: std_logic;
signal write_ack_delay_8: std_logic;
signal error_ack_delay_1: std_logic;
signal error_ack_delay_2: std_logic;
signal error_ack_delay_3: std_logic;
signal error_ack_delay_4: std_logic;
signal error_ack_delay_5: std_logic;
signal error_ack_delay_6: std_logic;
signal error_ack_delay_7: std_logic;
signal error_ack_delay_8: std_logic;
--------------------------------------------------------------------------------
begin
-----
-----------------------------------
-- Combinatorial operations for SPI
-----------------------------------
---- A write to read only register wont have any effect on register.
---- The transaction is completed by generating WrAck only.
LEGACY_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error_1 <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
REG_ERR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_Error <= '0';
else
IP2Bus_Error <= IP2Bus_Error_1;
end if;
end if;
end process REG_ERR_ACK_P;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
Bus2IP_WrCE(SPIDTR) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
--end generate WR_ACK_OR_REDUCE_FIFO_1_GEN;
-----------------------------------------
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg_1;
-------------------------------------------------
-- common WrAck to IPIF
IP2Bus_WrAck_1 <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
ip2Bus_WrAck_core_reg;-- or
--Tx_FIFO_wr_ack; -- newly added
REG_WR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_WrAck <= '0';
else
IP2Bus_WrAck <= IP2Bus_WrAck_1;
end if;
end if;
end process REG_WR_ACK_P;
-------------------------------------------------
--end generate LEGACY_MD_WR_ACK_GEN;
-------------------------------------------------
--LEGACY_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
--begin
-----
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck_1 <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg;
REG_RD_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_RdAck <= '0';
else
IP2Bus_RdAck <= IP2Bus_RdAck_1;
end if;
end if;
end process REG_RD_ACK_P;
---------------------------------------------------
end generate LEGACY_MD_WR_RD_ACK_GEN;
-------------------------------------------------
ENHANCED_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
Bus2IP_WrCE(SPIDTR) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register; -- register hole
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg;--_1;
-------------------------------------------------
-- common WrAck to IPIF
-- in the enhanced mode for FIFO, the IP2bus_Wrack is provided by the enhanced mode statemachine only.
IP2Bus_WrAck <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
(ip2Bus_WrAck_core_reg and (not burst_tr));-- or
--(Tx_FIFO_wr_ack and burst_tr); -- newly added
-------------------------------------------------
--ENHANCED_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
--begin
-----
FIFO_NO_RD_CE_GEN: if C_FIFO_EXIST = 0 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_NO_RD_CE_GEN;
FIFO_YES_RD_CE_GEN: if C_FIFO_EXIST = 1 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
--Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_YES_RD_CE_GEN;
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
--ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg; --_1;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg or
(Rx_FIFO_rd_ack and rready);
-----------------------------------------------------
end generate ENHANCED_MD_WR_RD_ACK_GEN;
-------------------------------------------------
--=============================================================================
TX_FIFO_OCC_DATA_FIFO_16: if C_FIFO_DEPTH = 16 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty); --(FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_16;
--------------------------------------
TX_FIFO_OCC_DATA_FIFO_256: if C_FIFO_DEPTH = 256 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(4)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(5)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(6)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(7)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);-- (FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(4)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(5)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(6)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(7)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_256;
--*****************************************************************************
ip2Bus_Data_occupancy_int(0 to (C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS-1))
<= (others => '0');
ip2Bus_Data_occupancy_int((C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS)
to (C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 or
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1;
-------------------------------------------------------------------------------
-- SPECIAL_CASE_WHEN_SS_NOT_EQL_32 : The Special case is executed whenever
-- C_NUM_SS_BITS is less than 32
-------------------------------------------------------------------------------
SPECIAL_CASE_WHEN_SS_NOT_EQL_32: if(C_NUM_SS_BITS /= 32) generate
-----
begin
-----
ip2Bus_Data_SS_int(0 to (C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS-1))
<= (others => '0');
end generate SPECIAL_CASE_WHEN_SS_NOT_EQL_32;
---------------------------------------------
ip2Bus_Data_SS_int((C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS) to
(C_S_AXI_DATA_WIDTH-1)) <= IP2Bus_SPISSR_Data_int;
-------------------------------------------------------------------------------
ip2Bus_Data_Reg_int(0 to C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH-1) <= (others => '0');
ip2Bus_Data_Reg_int(C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH to C_S_AXI_DATA_WIDTH-1)
<= IP2Bus_SPISR_Data_int or -- SPISR - 11 bit
('0' & IP2Bus_SPICR_Data_int); -- SPICR - 10 bit
-------------------------------------------------------------------------------
-----------------------
Receive_Reg_width_is_32: if(C_NUM_TRANSFER_BITS = 32) generate
-----------------------
begin
-----
IP2Bus_Data_received_int <= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_32;
-----------------------------------------
---------------------------
Receive_Reg_width_is_not_32: if(C_NUM_TRANSFER_BITS /= 32) generate
---------------------------
begin
-----
IP2Bus_Data_received_int(0 to C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS-1)
<= (others => '0');
IP2Bus_Data_received_int((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to
(C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_not_32;
-----------------------------------------
-------------------------------------------------------------------------------
LEGACY_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
ip2Bus_Data_1 <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
REG_IP2BUS_DATA_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_Data <= (others => '0');
else
ip2Bus_Data <= ip2Bus_Data_1;
end if;
end if;
end process REG_IP2BUS_DATA_P;
end generate LEGACY_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
ENHANCED_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
ip2Bus_Data <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
end generate ENHANCED_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_1.reset_sync_module
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic;
--Bus2IP_Clk => Bus2IP_Clk ,-- in std_logic;
Soft_Reset_frm_axi => reset2ip_reset_int,-- in std_logic;
Rst_to_spi => Rst_to_spi_int -- out std_logic;
);
--------------------------------------
-- NO_FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 0
--------------------------------------
NO_FIFO_EXISTS: if(C_FIFO_EXIST = 0) generate
----------------------------------
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal modf_strobe_frm_spi_clk : std_logic;
-- signal modf_strobe_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal receive_data_frm_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal receive_data_to_axi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_frm_axi_clk: std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_to_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_fifo_0 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal drr_Overrun_int_frm_spi_clk: std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
-----
begin
-----
Rx_FIFO_rd_ack <= '0';
--------------------------------------------------------------------------
-- I_RECEIVE_REG : INSTANTIATE RECEIVE REGISTER
--------------------------------------------------------------------------
QSPI_RX_TX_REG: entity axi_quad_spi_v3_1.qspi_receive_transmit_reg
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int, -- in
--SPI Receiver signals -- From AXI clock
Bus2IP_Receive_Reg_RdCE => Bus2IP_RdCE(SPIDRR), -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
IP2Bus_Receive_Reg_Data => IP2Bus_Receive_Reg_Data_int, -- out
--SPI module ports From SPI clock
SPIXfer_done => spiXfer_done_to_axi_clk,--spiXfer_done_int,-- in
SPI_Received_Data => receive_data_to_axi_clk,--receive_Data_int,-- in vec
-- receive & transmit reg signals
-- DRR_Overrun => drr_Overrun_int,-- drr_Overrun_int,-- out
SR_7_Rx_Empty => Rx_FIFO_Empty_i, -- out
-- From AXI clock
Bus2IP_Transmit_Reg_Data=> Bus2IP_Data, -- in vec
Bus2IP_Transmit_Reg_WrCE=> Bus2IP_WrCE(SPIDTR), -- in
Wr_ce_reduce_ack_gen => wr_ce_reduce_ack_gen, -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen, -- in
--SPI Transmitter signals from AXI clock
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
--SPI module ports
DTR_underrun => dtr_underrun_to_axi_clk,--dtr_underrun_int,-- in
SR_5_Tx_Empty => sr_5_Tx_Empty_int, -- out
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
Transmit_Reg_Data_Out => transmit_Data_fifo_0--transmit_Data_int -- out vec
);
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
spiXfer_done_frm_spi_clk <= spiXfer_done_int ;-- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int ;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int;-- from SPI module
receive_data_frm_spi_clk <= Data_To_Rx_FIFO ; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
transmit_Data_frm_axi_clk <= transmit_Data_fifo_0; -- From AXI clock
Tx_FIFO_Empty_frm_axi_clk <= sr_5_Tx_Empty_int;
Tx_FIFO_Empty_SPISR_frm_spi_clk <= sr_5_Tx_Empty_int;
--Rx_FIFO_Empty_int <= Rx_FIFO_Empty;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty_i;
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
CROSS_CLK_FIFO_0_INST:entity axi_quad_spi_v3_1.cross_clk_sync_fifo_0
generic map(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
--C_AXI_SPI_CLK_EQ_DIFF => C_AXI_SPI_CLK_EQ_DIFF,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK,
Bus2IP_Clk => Bus2IP_Clk ,
Soft_Reset_op => reset2ip_reset_int,
Rst_from_axi_cdc_to_spi => Rst_to_spi_int, -- out std_logic;
----------------------------------------------------------
Tx_FIFO_Empty_cdc_from_axi => Tx_FIFO_Empty_frm_axi_clk,
Tx_FIFO_Empty_cdc_to_spi => Tx_FIFO_Empty,
----------------------------------------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------------------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk , -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk , -- out
----------------------------------------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk, -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------------------------------------
Slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk,-- in
Slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk ,-- out
----------------------------------------------------------
receive_Data_cdc_from_spi => receive_Data_frm_spi_clk, -- in
receive_Data_cdc_to_axi => receive_data_to_axi_clk, -- out
----------------------------------------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk, -- in
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk, -- out
----------------------------------------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk, -- out
----------------------------------------------------------
transmit_Data_cdc_from_axi => transmit_Data_frm_axi_clk, -- in
transmit_Data_cdc_to_spi => transmit_Data_to_spi_clk, -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk ,-- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int -- out
----------------------------
);
Data_From_TxFIFO <= transmit_Data_to_spi_clk;
rc_FIFO_Full_strobe_int <= '0';
rc_FIFO_occ_Reversed_int <= (others => '0');
rc_FIFO_Data_Out_int <= (others => '0');
data_Exists_RcFIFO_int <= '0';
tx_FIFO_Empty_strobe_int <= '0';
tx_FIFO_occ_Reversed_int <= (others => '0');
data_Exists_TxFIFO_int <= '0';
data_From_TxFIFO_int <= (others => '0');
tx_FIFO_less_half_int <= '0';
reset_TxFIFO_ptr_int <= '0';
reset_RcFIFO_ptr_int <= '0';
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
Tx_FIFO_Full_int <= not(sr_5_Tx_Empty_int); -- Tx_FIFO_Empty_to_axi_clk);
Rx_FIFO_Full_int <= not(Rx_FIFO_Empty_i);
--------------------------------------------------------------------------
bus2IP_Data_for_interrupt_core(0 to 14) <= Bus2IP_Data(0 to 14);
bus2IP_Data_for_interrupt_core(15 to 22) <= (others => '0');
-- below code manipulates the bus2ip_data going towards interrupt control
-- unit. In FIFO=0, case bit 23 and 25 of IPIER are not applicable.
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 22 23 31
-- <---NA---> <-used->
-- 23 24 25 26 27 28 29 30 31
-- DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- NA-fifo-0 NA -fifo-0
bus2IP_Data_for_interrupt_core(23) <= '0'; -- DRR_Not_Empty bit in IPIER/IPISR
bus2IP_Data_for_interrupt_core(24) <= Bus2IP_Data(24);
bus2IP_Data_for_interrupt_core(25) <= '0'; -- Tx FIFO Half Empty
bus2IP_Data_for_interrupt_core(26 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(26 to (C_S_AXI_DATA_WIDTH-1));
--------------------------------------------------------------------------
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(12) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(11) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(10) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(9) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(8) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk; -- spisel_pulse_o_int;
ip2Bus_IntrEvent_int(6) <= '0'; --
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int_to_axi_clk;
ip2Bus_IntrEvent_int(4) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int;
ip2Bus_IntrEvent_int(2) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; -- slave_MODF_strobe_int;
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int;
end generate NO_FIFO_EXISTS;
-------------------------------------------------------------------------------
-- FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 1
-------------------------------------------------------------------------------
FIFO_EXISTS: if(C_FIFO_EXIST = 1) generate
------------------------------
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant TX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
constant ZERO_TX_FIFO_CNT : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d1: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d2: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal Tx_FIFO_Empty_1 : std_logic;
signal Tx_FIFO_Empty_intr : std_logic;
signal IP2Bus_RdAck_receive_enable : std_logic;
signal IP2Bus_WrAck_transmit_enable : std_logic;
constant ALL_0 : std_logic_vector(0 to TX_FIFO_CNTR_WIDTH-1)
:= (others => '1');
signal data_Exists_RcFIFO_int_d1: std_logic;
signal data_Exists_RcFIFO_pulse : std_logic;
--signal FIFO_Empty_rx : std_logic;
--signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
--signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
--signal spisel_d1_reg_frm_spi_clk : std_logic;
--signal spisel_d1_reg_to_axi_clk : std_logic;
signal tx_occ_msb_111 : std_logic:= '0';
signal tx_occ_msb_11 : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal Rx_FIFO_Empty_frm_axi_clk : std_logic;
signal Rx_FIFO_Empty_to_spi_clk : std_logic;
signal Tx_FIFO_Full_frm_axi_clk : std_logic;
signal Tx_FIFO_Full_to_spi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal SR_3_modf_frm_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal spiXfer_done_to_axi_d1 : std_logic;
signal updown_cnt_en : std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
signal drr_Overrun_int_frm_spi_clk: std_logic;
-----
begin
-----
SPISR_0_CMD_Error_frm_spi_clk <= SPISR_0_CMD_Error_int;
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int; -- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int; -- spi module
Rx_FIFO_Full_frm_spi_clk <= Rx_FIFO_Full; -- from Async Receive FIFO
Tx_FIFO_Empty_frm_spi_clk <= Tx_FIFO_Empty_intr; -- Tx_FIFO_Empty; -- from Async Transmit FIFO
spiXfer_done_frm_spi_clk <= spiXfer_done_int; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
Tx_FIFO_Empty_SPISR_frm_spi_clk <= Tx_FIFO_Empty;-- from TX FIFO for SPI Status register
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
-- SPICR_6_RXFIFO_RST_frm_axi_clk<= SPICR_6_RXFIFO_RST_frm_axi_clk; -- from SPICR
reset_RcFIFO_ptr_frm_axi_clk <= reset_RcFIFO_ptr_int; -- from AXI clock
Rx_FIFO_Empty_frm_axi_clk <= Rx_FIFO_Empty; -- from Async Receive FIFO AXI side
Tx_FIFO_Full_frm_axi_clk <= Tx_FIFO_Full; -- from Async Transmit FIFO AXI side
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
--CLK_CROSS_I:
CLK_CROSS_I:entity axi_quad_spi_v3_1.cross_clk_sync_fifo_1
generic map(
C_FAMILY => C_FAMILY ,
C_FIFO_DEPTH => C_FIFO_DEPTH ,
C_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK , -- in std_logic;
Bus2IP_Clk => Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => reset2ip_reset_int ,
--Soft_Reset_op => Soft_Reset_op , -- in std_logic;
Rst_cdc_to_spi => Rst_to_spi_int , -- out std_logic;
----------------------------
SPISR_0_CMD_Error_cdc_from_spi => SPISR_0_CMD_Error_frm_spi_clk ,
SPISR_0_CMD_Error_cdc_to_axi => SPISR_0_CMD_Error_to_axi_clk ,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------
Mst_N_Slv_mode_cdc_from_spi => Mst_N_Slv_mode_frm_spi_clk , -- in
Mst_N_Slv_mode_cdc_to_axi => Mst_N_Slv_mode_to_axi_clk , -- out
----------------------------
slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk, -- in
slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk , -- out
----------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk , -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk, -- in
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk , -- out
----------------------------
Rx_FIFO_Full_cdc_from_spi => Rx_FIFO_Full_frm_spi_clk, -- in
Rx_FIFO_Full_cdc_to_axi => Rx_FIFO_Full_to_axi_clk , -- out
----------------------------
reset_RcFIFO_ptr_cdc_from_axi => reset_RcFIFO_ptr_frm_axi_clk, -- in
reset_RcFIFO_ptr_cdc_to_spi => reset_RcFIFO_ptr_to_spi_clk , -- out
----------------------------
Rx_FIFO_Empty_cdc_from_axi => Rx_FIFO_Empty_frm_axi_clk , -- in
Rx_FIFO_Empty_cdc_to_spi => Rx_FIFO_Empty_to_spi_clk , -- out
----------------------------
Tx_FIFO_Empty_cdc_from_spi => Tx_FIFO_Empty_frm_spi_clk, -- in
Tx_FIFO_Empty_cdc_to_axi => Tx_FIFO_Empty_to_Axi_clk, -- out
----------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_cdc_from_axi => Tx_FIFO_Full_frm_axi_clk,-- in
Tx_FIFO_Full_cdc_to_spi => Tx_FIFO_Full_to_spi_clk ,-- out
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk, -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk, -- out
----------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk , -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int, -- out
----------------------------
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1,
----------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk,
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk
----------------------------
);
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 17 18 31
-- <---NA---> <-used->
-- 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-- CMD_ Loop_Bk MSB Slave_Mode CPOL_CPHA DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- Error Error Error Error Error _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- In Slave
-- mode_only
-- <---------------------------------------> <------------------------------------------------------------->
-- In C_SPI_MODE 1 or 2 only Present in all conditions
-- IPISR Write
-- when FIFO = 1,all other the IPIER, IPISR interrupt bits are applicable based upon the SPI mode.
-- DRR_Not_Empty bit (bit 23) - available only in case of core is selected in
-- slave mode and control register mst_n_slv bit is '0'.
-- Slave_select_mode bit-available only in case of core is selected in slave mode
-- common assignment to SPI_MODE 1/2 and SPI_MODE = 0
bus2IP_Data_for_interrupt_core(0 to 17) <= Bus2IP_Data(0 to 17);
DUAL_MD_IPISR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22) <= Bus2IP_Data(18 to 22);
end generate DUAL_MD_IPISR_GEN;
---------------------------------------------
STD_MD_IPISR_GEN: if C_SPI_MODE = 0 generate
-----------------------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22)<= (others => '0');
end generate STD_MD_IPISR_GEN;
------------------------------------------------
bus2IP_Data_for_interrupt_core(23) <= Bus2IP_Data(23) and -- exists only when FIFO = exists AND
((not spisel_d1_reg_to_axi_clk) --spisel_d1_reg)
or -- core is selected by asserting SPISEL by ext. master AND
(not Mst_N_Slv_mode) --Mst_N_Slv_mode) -- core is in slave mode
);
bus2IP_Data_for_interrupt_core(24 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(24 to (C_S_AXI_DATA_WIDTH-1));
--
----------------------------------------------------
-- _____|------------- data_Exists_RcFIFO_int
-- ________|---------- data_Exists_RcFIFO_int_d1
-- _____|--|__________ data_Exists_RcFIFO_pulse
----------------------------------------------------
DRR_NOT_EMPTY_PULSE_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
data_Exists_RcFIFO_int_d1 <= '0';
else
data_Exists_RcFIFO_int_d1 <= not rx_fifo_empty_i; -- data_Exists_RcFIFO_int;
end if;
end if;
end process DRR_NOT_EMPTY_PULSE_P;
------------------------------------
data_Exists_RcFIFO_pulse <= not rx_fifo_empty_i and
(not data_Exists_RcFIFO_int_d1);
------------------------------------
---------------------------------------------------------------------------
DUAL_MD_INTR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
signal SPISR_4_CPOL_CPHA_Error_d1 : std_logic;
signal SPISR_3_Slave_Mode_Error_d1 : std_logic;
signal SPISR_2_MSB_Error_d1 : std_logic;
signal SPISR_1_LOOP_Back_Error_d1 : std_logic;
signal SPISR_0_CMD_Error_d1 : std_logic;
signal SPISR_4_CPOL_CPHA_Error_pulse : std_logic;
signal SPISR_3_Slave_Mode_Error_pulse: std_logic;
signal SPISR_2_MSB_Error_pulse : std_logic;
signal SPISR_1_LOOP_Back_Error_pulse : std_logic;
signal SPISR_0_CMD_Error_pulse : std_logic;
-----
begin
-----
INTR_UPPER_BITS_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
SPISR_0_CMD_Error_d1 <= '0';
SPISR_1_LOOP_Back_Error_d1 <= '0';
SPISR_2_MSB_Error_d1 <= '0';
SPISR_3_Slave_Mode_Error_d1 <= '0';
SPISR_4_CPOL_CPHA_Error_d1 <= '0';
else
SPISR_0_CMD_Error_d1 <= SPISR_0_CMD_Error_to_axi_clk; -- SPISR_0_CMD_Error_int;
SPISR_1_LOOP_Back_Error_d1 <= SPISR_1_LOOP_Back_Error_int; -- from SPICR
SPISR_2_MSB_Error_d1 <= SPISR_2_MSB_Error_int; -- from SPICR
SPISR_3_Slave_Mode_Error_d1 <= SPISR_3_Slave_Mode_Error_int;-- from SPICR
SPISR_4_CPOL_CPHA_Error_d1 <= SPISR_4_CPOL_CPHA_Error_int; -- from SPICR
end if;
end if;
end process INTR_UPPER_BITS_P;
------------------------------------
SPISR_0_CMD_Error_pulse <= SPISR_0_CMD_Error_to_axi_clk -- SPISR_0_CMD_Error_int
and (not SPISR_0_CMD_Error_d1);
SPISR_1_LOOP_Back_Error_pulse <= SPISR_1_LOOP_Back_Error_int
and (not SPISR_1_LOOP_Back_Error_d1);
SPISR_2_MSB_Error_pulse <= SPISR_2_MSB_Error_int
and (not SPISR_2_MSB_Error_d1);
SPISR_3_Slave_Mode_Error_pulse <= SPISR_3_Slave_Mode_Error_int
and (not SPISR_3_Slave_Mode_Error_d1);
SPISR_4_CPOL_CPHA_Error_pulse <= SPISR_4_CPOL_CPHA_Error_int
and (not SPISR_4_CPOL_CPHA_Error_d1);
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= SPISR_0_CMD_Error_pulse;
ip2Bus_IntrEvent_int(12) <= SPISR_1_LOOP_Back_Error_pulse;
ip2Bus_IntrEvent_int(11) <= SPISR_2_MSB_Error_pulse;
ip2Bus_IntrEvent_int(10) <= SPISR_3_Slave_Mode_Error_pulse;
ip2Bus_IntrEvent_int(9) <= SPISR_4_CPOL_CPHA_Error_pulse ;
end generate DUAL_MD_INTR_GEN;
--------------------------------------------
STD_MD_INTR_GEN: if C_SPI_MODE = 0 generate
-----------------------
begin
-----
ip2Bus_IntrEvent_int(13) <= '0';
ip2Bus_IntrEvent_int(12) <= '0';
ip2Bus_IntrEvent_int(11) <= '0';
ip2Bus_IntrEvent_int(10) <= '0';
ip2Bus_IntrEvent_int(9) <= '0';
end generate STD_MD_INTR_GEN;
-----------------------------------------------
ip2Bus_IntrEvent_int(8) <= data_Exists_RcFIFO_pulse and
((not spisel_d1_reg_to_axi_clk) -- spisel_d1_reg)
or
(not SPICR_2_MST_N_SLV_frm_axi_clk) -- Mst_N_Slv_mode)
);
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk;-- and not SPICR_2_MST_N_SLV_frm_axi_clk; -- spisel_pulse_o_int;-- spi_module
ip2Bus_IntrEvent_int(6) <= tx_FIFO_less_half_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(4) <= rc_FIFO_Full_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(2) <= tx_FIFO_Empty_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; --slave_MODF_strobe_int;-- spi_module
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int; -- spi_module
--Combinatorial operations
reset_TxFIFO_ptr_int <= reset2ip_reset_int or SPICR_5_TXFIFO_RST_frm_axi_clk;
--reset_RcFIFO_ptr_int <= Rst_to_spi_int or SPICR_6_RXFIFO_RST_to_spi_clk; -- SPICR_6_RXFIFO_RST_int;
reset_RcFIFO_ptr_int <= reset2ip_reset_int or SPICR_6_RXFIFO_RST_frm_axi_clk;
sr_5_Tx_Empty_int <= not (data_Exists_TxFIFO_int);
Rc_FIFO_Empty_int <= Rx_FIFO_Empty;--not (data_Exists_RcFIFO_int);
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
RX_RD_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_RdAck_receive_enable <= (rd_ce_reduce_ack_gen and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_LEG_MD_GEN;
RX_RD_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
begin
-----
IP2Bus_RdAck_receive_enable <= --(rd_ce_reduce_ack_gen and
(rready and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_ENHAN_MD_GEN;
-- Receive FIFO Logic
rx_fifo_reset <= Rst_to_spi_int or reset_RcFIFO_ptr_to_spi_clk;
RX_FIFO_II: entity proc_common_v4_0.async_fifo_fg --axi_quad_spi_v3_1.async_fifo_fg --proc_common_v4_0.async_fifo_fg
generic map(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => spiXfer_done_int, --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => Rx_FIFO_wr_ack_open , -- : out std_logic;
------
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => IP2Bus_RdAck_receive_enable , -- : in std_logic := '0';
Rd_clk => Bus2IP_Clk , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Full => open, --Rx_FIFO_Full , -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => Rx_FIFO_occ_Reversed , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => rx_fifo_reset, -- reset_RcFIFO_ptr_to_spi_clk ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
RX_FIFO_FULL_CNTR_I : entity proc_common_v4_0.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => reset_RcFIFO_ptr_int, -- in
----------------
Count_Down => IP2Bus_RdAck_receive_enable, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en_rx <= IP2Bus_RdAck_receive_enable or spiXfer_done_to_axi_1;
RX_one_less_than_full <= and_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto RX_FIFO_CNTR_WIDTH-RX_FIFO_CNTR_WIDTH+1)) and
(not rx_fifo_count(0))and spiXfer_done_to_axi_1;
RX_FULL_EMP_MD_12_INTR_GEN: if C_SPI_MODE /= 0 generate
-----
--signal rx_fifo_empty_i : std_logic;
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
RX_FIFO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then --(drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(RX_one_less_than_full = '1' and
spiXfer_done_to_axi_1 = '1' and
rx_fifo_empty_i = '0')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
end generate RX_FULL_EMP_MD_12_INTR_GEN;
------------------------------------
RX_FULL_EMP_MD_0_GEN: if C_SPI_MODE = 0 generate
--signal rx_fifo_empty_i : std_logic;
-----
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
-------------------------------------------
RX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_i <= '0';
elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(Rx_FIFO_Full_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(RX_one_less_than_full = '1')then
Rx_FIFO_Full_i <= '1';
end if;
end if;
end process RX_FIFO_ABT_TO_FULL_P;
-------------------------------------
RX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_int = '1' and IP2Bus_RdAck_receive_enable = '1') then -- IP2Bus_RdAck_receive_enable = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_i = '1')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
---------------------------------
Rx_FIFO_Full <= Rx_FIFO_Full_int;
end generate RX_FULL_EMP_MD_0_GEN;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty or Rx_FIFO_Empty_i;
-----------------------------------------------------------------------------
-- AXI Clk domain -- __________________ SPI clk domain
--Din --|AXI clk |-- Dout
--Wr_en --| |-- Rd_en
--Wr_clk --| |-- Rd_clk
--| |--
--Tx_FIFO_Full --| Tx FIFO |-- Tx_FIFO_Empty
--Tx_FIFO_almost_Full --| |-- Tx_FIFO_almost_Empty
--Tx_FIFO_occ_Reversed --| |-- Tx_FIFO_rd_ack
--Tx_FIFO_wr_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
TX_TR_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
Bus2IP_WrCE(SPIDTR)
) and
(not Tx_FIFO_Full);-- after 100 ps;
end generate TX_TR_EN_LEG_MD_GEN;
TX_TR_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
signal local_tr_en : std_logic;
begin
-----
--IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
-- Bus2IP_WrCE(SPIDTR)
-- ) and
-- (not Tx_FIFO_Full)
-- when burst_tr = '0' else
-- (Bus2IP_WrCE(SPIDTR)
-- and
-- (not Tx_FIFO_Full));-- after 100 ps;
local_tr_en <= Bus2IP_WrCE(SPIDTR) and (not Tx_FIFO_Full);
--local_tr_en1 <= Bus2IP_WrCE_d1 and (not Tx_FIFO_Full);
TR_EN_P:process(wr_ce_reduce_ack_gen,
local_tr_en,
burst_tr,
WVALID)is
begin
if(burst_tr = '1') then
IP2Bus_WrAck_transmit_enable <= local_tr_en and WVALID; -- Bus2IP_WrCE_d1 and (not Tx_FIFO_Full); --local_tr_en;
else
IP2Bus_WrAck_transmit_enable <= local_tr_en and wr_ce_reduce_ack_gen;
end if;
end process TR_EN_P;
end generate TX_TR_EN_ENHAN_MD_GEN;
Data_To_TxFIFO <= Bus2IP_Data((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to(C_S_AXI_DATA_WIDTH-1));-- after 100 ps;
-- Transmit FIFO Logic
tx_fifo_reset <= reset2ip_reset_int or reset_TxFIFO_ptr_int;
TX_FIFO_II: entity proc_common_v4_0.async_fifo_fg -- entity axi_quad_spi_v3_1.async_fifo_fg -- proc_common_v4_0.async_fifo_fg
generic map
(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map
(
-- writing will be through AXI clock
Wr_clk => Bus2IP_Clk , -- : in std_logic := '1';
Din => Data_To_TxFIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => IP2Bus_WrAck_transmit_enable, -- : in std_logic := '1';
Wr_ack => Tx_FIFO_wr_ack , -- : out std_logic;
------
-- reading will be through SPI clock
Rd_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Dout => Data_From_TxFIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => SPIXfer_done_rd_tx_en , -- : in std_logic := '0';
Rd_ack => Tx_FIFO_rd_ack_open , -- : out std_logic;
------
Full => Tx_FIFO_Full , -- : out std_logic;
Empty => Tx_FIFO_Empty , -- : out std_logic;
Almost_full => Tx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Tx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => reset_TxFIFO_ptr_int ,--Tx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => Tx_FIFO_occ_Reversed , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
--tx_occ_msb <= tx_fifo_count(TX_FIFO_CNTR_WIDTH-1); -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
--tx_occ_msb_1 <= (tx_fifo_count(TX_FIFO_CNTR_WIDTH-1));-- and not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-2 downto 0))) ;--
--and not Tx_FIFO_Empty_SPISR_to_axi_clk;-- and not Tx_FIFO_Full_int; -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
tx_occ_msb_11 <= (tx_fifo_count);
FIFO_16_OCC_MSB_GEN: if C_FIFO_DEPTH = 16 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(3);
end generate FIFO_16_OCC_MSB_GEN;
FIFO_256_OCC_MSB_GEN: if C_FIFO_DEPTH = 256 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(7);
end generate FIFO_256_OCC_MSB_GEN;
TX_OCC_MSB_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_occ_msb_2 <= '0';
tx_occ_msb_3 <= '0';
tx_occ_msb_4 <= '0';
else
tx_occ_msb_2 <= tx_occ_msb_1;
tx_occ_msb_3 <= tx_occ_msb_2;
tx_occ_msb_4 <= tx_occ_msb_3;
end if;
end if;
end process TX_OCC_MSB_P;
tx_occ_msb <= tx_occ_msb_4 and not Tx_FIFO_Empty_SPISR_to_axi_clk;
data_Exists_TxFIFO_int <= not (Tx_FIFO_Empty);
-----------------------------------------------------------
TX_FIFO_EMPTY_CNTR_I : entity proc_common_v4_0.counter_f
generic map(
C_NUM_BITS => TX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en, -- in
----------------
Count_Load => reset_TxFIFO_ptr_int, -- in
----------------
Count_Down => spiXfer_done_to_axi_1, -- in
Count_Out => tx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en <= IP2Bus_WrAck_transmit_enable or spiXfer_done_to_axi_1;
----------------------------------------
TX_FULL_EMP_INTR_MD_12_GEN: if C_SPI_MODE /=0 generate
-----
begin
-----
Tx_FIFO_Empty_intr <= not (or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk); -- and ( Tx_FIFO_Empty);
Tx_FIFO_Full_int <= Tx_FIFO_Full;
end generate TX_FULL_EMP_INTR_MD_12_GEN;
----------------------------------------
----------------------------------------
TX_FULL_EMP_INTR_MD_0_GEN: if C_SPI_MODE =0 generate
-----
begin
-----
-- Tx_FIFO_one_less_to_Empty <= not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- --and (tx_fifo_count(0))
-- and spiXfer_done_to_axi_1;--tx_cntr_xfer_done_to_axi_1_clk; --
-- --------------------------------------------
-- TX_FIFO_ABT_TO_EMPTY_P:process(Bus2IP_Clk)is
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_Empty_int = '1')then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_one_less_to_Empty = '1') or then
-- Tx_FIFO_Empty_i <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_ABT_TO_EMPTY_P;
-- --------------------------------------
-- TX_FIFO_EMPTY_P: process(Bus2IP_Clk)is
-- begin
-- -----
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_int = '1' and spiXfer_done_to_axi_1 = '1')then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_i = '1')then
-- Tx_FIFO_Empty_int <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_EMPTY_P;
--------------------------------
-- Tx_FIFO_Empty_intr <= Tx_FIFO_Empty_int and spiXfer_done_to_axi_1;
--------------------------------
TX_FIFO_CNTR_DELAY_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_fifo_count_d1 <= (others => '0');
tx_fifo_count_d2 <= (others => '0');
spiXfer_done_to_axi_d1 <= '0';
else
tx_fifo_count_d1 <= tx_fifo_count;
tx_fifo_count_d2 <= tx_fifo_count_d1;
spiXfer_done_to_axi_d1 <= spiXfer_done_to_axi_1;
end if;
end if;
end process TX_FIFO_CNTR_DELAY_P;
Tx_FIFO_Empty_intr <= (not (or_reduce(tx_fifo_count_d2(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_d1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk));
TX_one_less_than_full <= and_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto TX_FIFO_CNTR_WIDTH-TX_FIFO_CNTR_WIDTH+1)) and
(not tx_fifo_count(0))and IP2Bus_WrAck_transmit_enable;
-------------------------------------------
TX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_i <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(Tx_FIFO_Full_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(TX_one_less_than_full = '1')then
Tx_FIFO_Full_i <= '1';
end if;
end if;
end process TX_FIFO_ABT_TO_FULL_P;
----------------------------------
TX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_int <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_int = '1' and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_i = '1') then -- and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '1';
end if;
end if;
end process TX_FIFO_FULL_P;
---------------------------
end generate TX_FULL_EMP_INTR_MD_0_GEN;
----------------------------------------
-------------------------------------------------------------------------------
-- I_FIFO_IF_MODULE : INSTANTIATE FIFO INTERFACE MODULE
-------------------------------------------------------------------------------
FIFO_IF_MODULE_I: entity axi_quad_spi_v3_1.qspi_fifo_ifmodule
generic map
(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int, -- in
-- Slave attachment ports from AXI clock
Bus2IP_RcFIFO_RdCE => Bus2IP_RdCE(SPIDRR),-- axiclk -- in
Bus2IP_TxFIFO_WrCE => Bus2IP_WrCE(SPIDTR),-- axi clk -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen,-- axi clk -- in
-- FIFO ports
Data_From_TxFIFO => Data_From_TxFIFO ,-- spi clk -- in vec
Data_From_Rc_FIFO => Data_From_Rx_FIFO ,-- axi clk -- in vec
Tx_FIFO_Data_WithZero => transmit_Data_int ,-- spi clk -- out vec
IP2Bus_RX_FIFO_Data => IP2Bus_Receive_Reg_Data_int, -- out vec
---------------------
Rc_FIFO_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk, -- in
Rc_FIFO_Full_strobe => rc_FIFO_Full_strobe_int, -- out
---------------------
Tx_FIFO_Empty => Tx_FIFO_Empty_intr , -- Tx_FIFO_Empty_to_Axi_clk, -- sr_5_Tx_Empty_int,-- spi clk -- in
Tx_FIFO_Empty_strobe => tx_FIFO_Empty_strobe_int, -- out
---------------------
Rc_FIFO_Empty => Rx_FIFO_Empty_int, -- 13-09-2012 rx_fifo_empty_i, -- Rx_FIFO_Empty , -- Rc_FIFO_Empty_int, -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
Tx_FIFO_Full => Tx_FIFO_Full_int, -- in
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
---------------------
Tx_FIFO_Occpncy_MSB => tx_occ_msb, -- in
Tx_FIFO_less_half => tx_FIFO_less_half_int, -- out
---------------------
DTR_underrun => dtr_underrun_to_axi_clk,-- dtr_underrun_int,-- in
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
---------------------
SPIXfer_done => spiXfer_done_to_axi_1, -- spiXfer_done_int, -- in
rready => rready
-- DRR_Overrun_reg => drr_Overrun_int -- out
);
-------------------------------------------------------------------------------
-- TX_OCCUPANCY_I : INSTANTIATE TRANSMIT OCCUPANCY REGISTER
-------------------------------------------------------------------------------
TX_OCCUPANCY_I: entity axi_quad_spi_v3_1.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPITFOR), -- in
--FIFO port
IP2Reg_OCC_Data => tx_fifo_count, -- tx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Tx_FIFO_OCC_Reg_Data_int -- out vec
);
-------------------------------------------------------------------------------
-- RX_OCCUPANCY_I : INSTANTIATE RECEIVE OCCUPANCY REGISTER
-------------------------------------------------------------------------------
RX_OCCUPANCY_I: entity axi_quad_spi_v3_1.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS--,
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPIRFOR), -- in
--FIFO port
IP2Reg_OCC_Data => rx_fifo_count, --rx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Rx_FIFO_OCC_Reg_Data_int -- out vec
);
end generate FIFO_EXISTS;
--------------------------------------------
-- LOGIC_FOR_MD_0_GEN: in stantiate the original SPI module when the core is configured in Standard SPI mode.
------------------------------
LOGIC_FOR_MD_0_GEN: if C_SPI_MODE = 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
-----
begin
-----
-- un used IO2 and IO3 O/P ports are tied to 0 and T ports are tied to '1'
IO2_O <= '0';
IO2_T <= '1';
IO3_O <= '0';
IO3_T <= '1';
SPISR_0_CMD_Error_int <= '0'; -- no command error when C_SPI_MODE= 0
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_1.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => Rst_to_spi_int
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
----------------------------------------------------------------------------
-- SPI_MODULE_I : INSTANTIATE SPI MODULE
----------------------------------------------------------------------------
SPI_MODULE_I: entity axi_quad_spi_v3_1.qspi_mode_0_module
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SUB_FAMILY => C_SUB_FAMILY ,
C_FIFO_EXIST => C_FIFO_EXIST
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK, -- in
Soft_Reset_op => Rst_to_spi_int, -- in
------------------------
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk,--_int,
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk,--_int,
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int,
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk,--_int,
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk,--_int,
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_to_spi_clk, -- SPICR_5_TXFIFO_RST_to_spi_clk,--_int,
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int,
SPICR_7_SS => SPICR_7_SS_to_spi_clk,--_int,
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int,
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk,--_int,
------------------------
SR_3_MODF => SR_3_modf_to_spi_clk, -- in
SR_5_Tx_Empty => Tx_FIFO_Empty, -- sr_5_Tx_Empty_int, -- in
Slave_MODF_strobe => slave_MODF_strobe_int, -- out
MODF_strobe => modf_strobe_int, -- out
Slave_Select_Reg => register_Data_slvsel_int, -- already updated -- in vec
Transmit_Data => Data_From_TxFIFO, -- transmit_Data_int, -- in vec
Receive_Data => Data_To_Rx_FIFO, -- receive_Data_int, -- out vec
SPIXfer_done => spiXfer_done_int, -- out
-- SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
DTR_underrun => dtr_underrun_int, -- out
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--SPI Ports
SCK_I => SCK_I, -- in
SCK_O_reg => SCK_O_int, -- out
SCK_T => SCK_T, -- out
MISO_I => MISO_I_int, -- IO1_I, -- MISO_I, -- in
MISO_O => IO1_O, -- MISO_O, -- out
MISO_T => IO1_T, -- MISO_T, -- out
MOSI_I => IO0_I, -- MOSI_I, -- in
MOSI_O => IO0_O, -- MOSI_O, -- out
MOSI_T => IO0_T, -- MOSI_T, -- out
SPISEL => SPISEL, -- in
SS_I => SS_I, -- in
SS_O => SS_O, -- out
SS_T => SS_T, -- out
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
control_bit_7_8 => SPICR_bits_7_8_to_spi_clk, -- in vec
Mst_N_Slv_mode => Mst_N_Slv_mode ,
Rx_FIFO_Full => Rx_FIFO_Full,
DRR_Overrun_reg => drr_Overrun_int, -- out
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk,
tx_cntr_xfer_done => tx_cntr_xfer_done
);
-------------
end generate LOGIC_FOR_MD_0_GEN;
----------------------------------------
-- LOGIC_FOR_MD_12_GEN: to generate the functionality for mode 1 and 2.
------------------------------
LOGIC_FOR_MD_12_GEN: if C_SPI_MODE /= 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
signal Data_Dir_int : std_logic;
signal Data_Mode_1_int : std_logic;
signal Data_Mode_0_int : std_logic;
signal Data_Phase_int : std_logic;
signal Addr_Mode_1_int : std_logic;
signal Addr_Mode_0_int : std_logic;
signal Addr_Bit_int : std_logic;
signal Addr_Phase_int : std_logic;
signal CMD_Mode_1_int : std_logic;
signal CMD_Mode_0_int : std_logic;
signal CMD_Error_int : std_logic;
signal CMD_decoded_int : std_logic;
signal Dummy_Bits_int : std_logic_vector(3 downto 0);
signal IO2_O_int : std_logic;
signal IO2_T_int : std_logic;
signal IO3_O_int : std_logic;
signal IO3_T_int : std_logic;
signal IO2_I_int : std_logic;
signal IO3_I_int : std_logic;
-----
begin
-----
LOGIC_FOR_C_SPI_MODE_1_GEN: if C_SPI_MODE = 1 generate
-------
begin
-------
IO2_O <= '0'; -- not used in the logic
IO3_O <= '0'; -- not used in the logic
IO2_T <= '1'; -- disable the tri-state buffers
IO3_T <= '1'; -- disable the tri-state buffers
IO2_I_int <= '0';-- assign default value as this bit is not used in thid mode
IO3_I_int <= '0';-- assign default value as this bit is not used in thid mode
end generate LOGIC_FOR_C_SPI_MODE_1_GEN;
---------------------------------------
LOGIC_FOR_C_SPI_MODE_2_GEN: if C_SPI_MODE = 2 generate
-------
begin
-------
IO2_I_int <= IO2_I; -- assign this bit from the top level port
IO2_O <= IO2_O_int;
IO2_T <= IO2_T_int;
IO3_I_int <= IO3_I; -- assign this bit from the top level port
IO3_O <= IO3_O_int;
IO3_T <= IO3_T_int;
end generate LOGIC_FOR_C_SPI_MODE_2_GEN;
---------------------------------------
SPISR_0_CMD_Error_int <= CMD_Error_int;
dtr_underrun_int <= '0'; -- SPI MODE 1 & 2 are master modes, so DTR under run wont be present
slave_MODF_strobe_int <= '0'; -- SPI MODE 1 & 2 are master modes, so the slave mode fault error wont appear
Mst_N_Slv_mode <= '1';
-------------------------------------------------------
-- SCK_O <= SCK_O_int; -- output from the core
-- MISO_I_int <= IO1_I; -- input to the core
-- *
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_1.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => Rst_to_spi_int
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
-- *
-- Add instance for Look up table logic
SPI_MODE_1_LUT_LOGIC_I: entity axi_quad_spi_v3_1.qspi_look_up_logic
-------------
generic map
(
C_FAMILY => C_FAMILY ,
C_SPI_MODE => C_SPI_MODE ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
EXT_SPI_CLK => EXT_SPI_CLK , -- : in std_logic;
Rst_to_spi => Rst_to_spi_int , -- : in std_logic;
TXFIFO_RST => reset_TxFIFO_ptr_int, -- : in std_logic;
-------------------- --
DTR_FIFO_Data_Exists=> data_Exists_TxFIFO_int, -- : in std_logic;
Data_From_TxFIFO => Data_From_TxFIFO , -- : in std_logic_vector
-- (0 to (C_NUM_TRANSFER_BITS-1))
pr_state_idle => pr_state_idle_int , --
-------------------- --
Data_Dir => Data_Dir_int , -- : out std_logic;
Data_Mode_1 => Data_Mode_1_int , -- : out std_logic;
Data_Mode_0 => Data_Mode_0_int , -- : out std_logic;
Data_Phase => Data_Phase_int , -- : out std_logic;
-------------------- --
Quad_Phase => Quad_Phase_int ,
-------------------- --
Addr_Mode_1 => Addr_Mode_1_int , -- : out std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- : out std_logic;
Addr_Bit => Addr_Bit_int , -- : out std_logic;
Addr_Phase => Addr_Phase_int , -- : out std_logic;
-------------------- --
CMD_Mode_1 => CMD_Mode_1_int , -- : out std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- : out std_logic;
CMD_Error => CMD_Error_int , -- : out std_logic;
-------------------- -- -
CMD_decoded => CMD_decoded_int -- : out std_logic
);
---------
SPI_MODE_CONTROL_LOGIC_I: entity axi_quad_spi_v3_1.qspi_mode_control_logic
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_SUB_FAMILY => C_SUB_FAMILY
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK , -- Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => Rst_to_spi_int , -- in std_logic;
-------------------- , --
DTR_FIFO_Data_Exists => data_Exists_TxFIFO_int , -- in std_logic;
Slave_Select_Reg => register_Data_slvsel_int , -- already updated -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data => Data_From_TxFIFO,--transmit_Data_int , -- already updated -- in std_logic_vector(0 to (C_NUM_TRANSFER_BITS
Receive_Data => Data_To_Rx_FIFO , -- out std_logic_vector(0 to (C_NUM_TRANSFER_BITS
--Data_To_Rx_FIFO_1 => Data_To_Rx_FIFO_1,
SPIXfer_done => spiXfer_done_int , -- already updated -- out std_logic;
SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
MODF_strobe => modf_strobe_int , -- already updated
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--------------------- --
SR_3_MODF => SR_3_modf_to_spi_clk , -- in std_logic;
SR_5_Tx_Empty => Tx_FIFO_Empty , -- sr_5_Tx_Empty_int -- in std_logic;
--SR_6_Rx_Full => Rx_FIFO_Full , -- in
pr_state_idle => pr_state_idle_int , --
--------------------- -- from control register
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk ,--SPICR_0_LOOP_int , -- in std_logic;
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk ,--_int , -- in std_logic;
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int , -- in std_logic;
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk ,--_int , -- in std_logic;
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk ,--_int , -- in std_logic;
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_7_SS => SPICR_7_SS_to_spi_clk ,--_int , -- in std_logic;
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int , -- in std_logic;
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk ,--_int , -- in std_logic;
--------------------- --
--------------------- -- from look up table
Data_Dir => Data_Dir_int , -- in std_logic;
Data_Mode_1 => Data_Mode_1_int , -- in std_logic;
Data_Mode_0 => Data_Mode_0_int , -- in std_logic;
Data_Phase => Data_Phase_int ,
---------------------
--Dummy_Bits => Dummy_Bits_int , -- in std_logic_vector(3 downto 0);
Quad_Phase => Quad_Phase_int ,
--------------------- -- in std_logic;
Addr_Mode_1 => Addr_Mode_1_int , -- in std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- in std_logic;
Addr_Bit => Addr_Bit_int , -- in std_logic;
Addr_Phase => Addr_Phase_int , -- in std_logic;
---------------------
CMD_Mode_1 => CMD_Mode_1_int , -- in std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- in std_logic;
CMD_Error => CMD_Error_int , -- in std_logic;
--------------------- --
CMD_decoded => CMD_decoded_int , -- in std_logic;
--SPI Interface --
SCK_I => SCK_I, -- in std_logic;
SCK_O_reg => SCK_O_int, -- out std_logic;
SCK_T => SCK_T, -- out std_logic;
--
IO0_I => IO0_I, -- MOSI_I, -- in std_logic; -- MISO
IO0_O => IO0_O, -- MOSI_O, -- out std_logic;
IO0_T => IO0_T, -- MOSI_T, -- out std_logic;
IO1_I => MISO_I_int, -- IO1_I, -- MISO_I, -- in std_logic;
IO1_O => IO1_O, -- MISO_O, -- out std_logic; -- MOSI
IO1_T => IO1_T, -- MISO_T, -- out std_logic;
--
IO2_I => IO2_I_int, -- -- in std_logic;
IO2_O => IO2_O_int, -- -- out std_logic;
IO2_T => IO2_T_int, -- -- out std_logic;
--
IO3_I => IO3_I_int, -- -- in std_logic;
IO3_O => IO3_O_int, -- -- out std_logic;
IO3_T => IO3_T_int, -- -- out std_logic;
--
SPISEL => SPISEL, -- in std_logic;
--
SS_I => SS_I, -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_O => SS_O, -- out std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_T => SS_T, -- out std_logic;
--
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
Control_bit_7_8 => SPICR_bits_7_8_to_spi_clk , -- in std_logic_vector(0 to 1) --(7 to 8)
Rx_FIFO_Full => Rx_FIFO_Full,
DRR_Overrun_reg => drr_Overrun_int,
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk
);
-------------
end generate LOGIC_FOR_MD_12_GEN;
------------------------------------------
--------------------------------------------------------------------------------
CONTROL_REG_I: entity axi_quad_spi_v3_1.qspi_cntrl_reg
generic map
(
--------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
--------------------------
-- Number of bits in regis
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
--------------------------
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH,
--------------------------
C_SPI_MODE => C_SPI_MODE
--------------------------
)
port map
( -- in
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int,
---------------------------
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen, -- in
Bus2IP_SPICR_WrCE => Bus2IP_WrCE(SPICR), -- in
Bus2IP_SPICR_RdCE => Bus2IP_RdCE(SPICR), -- in
Bus2IP_SPICR_data => Bus2IP_Data, -- in vec
---------------------------
SPICR_0_LOOP => SPICR_0_LOOP_frm_axi_clk, -- out
SPICR_1_SPE => SPICR_1_SPE_frm_axi_clk, -- out
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_frm_axi_clk, -- out
SPICR_3_CPOL => SPICR_3_CPOL_frm_axi_clk, -- out
SPICR_4_CPHA => SPICR_4_CPHA_frm_axi_clk, -- out
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_frm_axi_clk, -- out
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_frm_axi_clk, -- out
SPICR_7_SS => SPICR_7_SS_frm_axi_clk, -- out
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_frm_axi_clk, -- out
SPICR_9_LSB => SPICR_9_LSB_frm_axi_clk, -- out
-- to Status Register
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int, -- out
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int, -- out
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int, -- out
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int, -- out
---------------------------
IP2Bus_SPICR_Data => IP2Bus_SPICR_Data_int, -- out vec
---------------------------
Control_bit_7_8 => SPICR_bits_7_8_frm_axi_clk -- out vec
---------------------------
);
-------------------------------------------------------------------------------
-- STATUS_REG_I : INSTANTIATE STATUS REGISTER
-------------------------------------------------------------------------------
STATUS_REG_MODE_0_GEN: if C_SPI_MODE = 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_1.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => '0' , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_0_GEN;
STATUS_REG_MODE_12_GEN: if C_SPI_MODE /= 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_1.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => SPISR_0_CMD_Error_to_axi_clk , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_12_GEN;
-------------------------------------------------------------------------------
-- SOFT_RESET_I : INSTANTIATE SOFT RESET
-------------------------------------------------------------------------------
SOFT_RESET_I: entity proc_common_v4_0.soft_reset
generic map
(
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH,
-- Width of triggered reset in Bus Clocks
C_RESET_WIDTH => 16
)
port map
(
-- Inputs From the PLBv46 Slave Single Bus
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => Bus2IP_Reset, -- in
Bus2IP_WrCE => Bus2IP_WrCE(SWRESET), -- in
Bus2IP_Data => Bus2IP_Data, -- in
Bus2IP_BE => Bus2IP_BE, -- in
-- Final Device Reset Output
Reset2IP_Reset => reset2ip_reset_int, -- out
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck => rst_ip2bus_wrack, -- out
Reset2Bus_Error => rst_ip2bus_error, -- out
Reset2Bus_ToutSup => open -- out
);
-------------------------------------------------------------------------------
-- INTERRUPT_CONTROL_I : INSTANTIATE INTERRUPT CONTROLLER
-------------------------------------------------------------------------------
bus2ip_intr_rdce <= "0000000" &
Bus2IP_RdCE(7) &
Bus2IP_RdCE(8) &
'0' &
Bus2IP_RdCE(10)&
"00000";
bus2ip_intr_wrce <= "0000000" &
Bus2IP_WrCE(7) &
Bus2IP_WrCE(8) &
'0' &
Bus2IP_WrCE(10)&
"00000";
------------------------------------------------------------------------------
intr_controller_rd_ce_or_reduce <= or_reduce(Bus2IP_RdCE(0 to 6)) or
Bus2IP_RdCE(9) or
or_reduce(Bus2IP_RdCE(11 to 15));
------------------------------------------------------------------------------
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_controller_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_controller_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
------------------------------------------------------------------------------
intr_controller_wr_ce_or_reduce <= or_reduce(Bus2IP_WrCE(0 to 6)) or
Bus2IP_WrCE(9) or
or_reduce(Bus2IP_WrCE(11 to 15));
------------------------------------------------------------------------------
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_controller_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_controller_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
------------------------------------------------------------------------------
INTERRUPT_CONTROL_I: entity interrupt_control_v3_0.interrupt_control
generic map
(
C_NUM_CE => 16,
C_NUM_IPIF_IRPT_SRC => 1, -- Set to 1 to avoid null array
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_PENCODER => false,
-- Specifies device ISC hierarchy
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => reset2ip_reset_int, -- in
Bus2IP_Data => bus2IP_Data_for_interrupt_core, -- in vec
Bus2IP_BE => Bus2IP_BE, -- in vec
Interrupt_RdCE => bus2ip_intr_rdce, -- in vec
Interrupt_WrCE => bus2ip_intr_wrce, -- in vec
IPIF_Reg_Interrupts => "00", -- Tie off the unused reg intrs
IPIF_Lvl_Interrupts => "0", -- Tie off the dummy lvl intr
IP2Bus_IntrEvent => ip2Bus_IntrEvent_int, -- in
Intr2Bus_DevIntr => IP2INTC_Irpt, -- out
Intr2Bus_DBus => intr_ip2bus_data, -- out vec
Intr2Bus_WrAck => intr_ip2bus_wrack, -- out
Intr2Bus_RdAck => intr_ip2bus_rdack, -- out
Intr2Bus_Error => intr_ip2bus_error, -- out
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
--------------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
|
mit
|
a9f6662ee3868d8f8266fa4dac4ee43f
| 0.441952 | 3.741767 | false | false | false | false |
6769/VHDL
|
Lab_0/Adder4.vhd
| 1 | 1,446 |
--another function is adjust BCD ,like the instruct DA in 8051;
entity Adder4 is
port(A,B:in bit_vector (3 downto 0);
cin:in bit ;
S:out bit_vector(3 downto 0);
cout:buffer bit
);
end Adder4;
architecture Bcd4bit_fullAdder of Adder4 is
component FullAdder
port(a,b,cin:in bit ;
s,cout:out bit );
end component;
signal C:bit_vector(3 downto 1);--internal carry bit ;
signal s_mid:bit_vector(3 downto 0);
signal z,cout_mid:bit;
begin
-- process(A,B,cin)
-- begin
FA0:FullAdder port map(A(0),B(0),cin ,s_mid(0),C(1));
FA1:FullAdder port map(A(1),B(1),C(1),s_mid(1),C(2));
FA2:FullAdder port map(A(2),B(2),C(2),s_mid(2),C(3));
FA3:FullAdder port map(A(3),B(3),C(3),s_mid(3),cout_mid);
-- z<= cout_mid or s_mid(3)or (s_mid(2)and s_mid(1));
-- if z='0' then S<=s_mid;
-- else Adder4 port map (s_mid,"0110",'0',S,cout);
-- end if;
-- cout<=z;
-- end process;
process( A)
begin
report " 9 mod 5 = " & integer'image(9 mod 5);
report " 9 rem 5 = " & integer'image(9 rem 5);
report " 9 mod (-5) = " & integer'image(9 mod (-5));
report " 9 rem (-5) = " & integer'image(9 rem (-5));
report "(-9) mod 5 = " & integer'image((-9) mod 5);
report "(-9) rem 5 = " & integer'image((-9) rem 5);
report "(-9) mod (-5) = " & integer'image((-9) mod (-5));
report "(-9) rem (-5) = " & integer'image((-9) rem (-5));
--wait for 0 us;
end process;
S<=s_mid;
end Bcd4bit_fullAdder;
|
gpl-2.0
|
46998cdd1d644d593315b745e862edd4
| 0.585754 | 2.382208 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/axi_quad_spi_v3_1/hdl/src/vhdl/xip_cntrl_reg.vhd
| 1 | 12,515 |
-------------------------------------------------------------------------------
-- $Id: xip_cntrl_reg.vhd
-------------------------------------------------------------------------------
-- xip_cntrl_reg.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: xip_cntrl_reg.vhd
-- Version: v3.0
-- Description: control register module for axi quad spi in XIP mode.
--
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_quad_spi.
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-------------------------------------------------------------------------------
-- Author: SK
-- ^^^^^^
-- 1. Added the XIP Cntrl register for the first time in this release.
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.RESET_ACTIVE;
--library unisim;
-- use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- Width of the slave data bus
-- C_XIP_SPICR_REG_WIDTH -- Width of SPI registers
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- SLAVE ATTACHMENT INTERFACE
-- Wr_ce_reduce_ack_gen -- common write ack generation logic input
-- Bus2IP_XIPCR_data -- Data written from the PLB bus
-- Bus2IP_XIPCR_WrCE -- Write CE for control register
-- Bus2IP_XIPCR_RdCE -- Read CE for control register
-- IP2Bus_XIPCR_Data -- Data to be send on the bus
-- SPI MODULE INTERFACE
-- Control_Register_Data -- Data to be send on the bus
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity xip_cntrl_reg is
generic
(
----------------------------
C_S_AXI_DATA_WIDTH : integer; -- 32 bits
----------------------------
-- Number of bits in register,10 for control reg - 8 for cmd + 2 CPOL/CPHA
C_XIP_SPICR_REG_WIDTH : integer;
----------------------------
C_SPI_MODE : integer
----------------------------
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
-- Slave attachment ports
Bus2IP_XIPCR_WrCE : in std_logic;
Bus2IP_XIPCR_RdCE : in std_logic;
Bus2IP_XIPCR_data : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
ip2Bus_RdAck_core : in std_logic;
ip2Bus_WrAck_core : in std_logic;
XIPCR_1_CPOL : out std_logic;
XIPCR_0_CPHA : out std_logic;
--------------------------
IP2Bus_XIPCR_Data : out std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
--------------------------
TO_XIPSR_CPHA_CPOL_ERR : out std_logic
);
end xip_cntrl_reg;
-------------------------------------------------------------------------------
-- Architecture
--------------------------------------
architecture imp of xip_cntrl_reg is
-------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- Signal Declarations
----------------------
signal XIPCR_data_int : std_logic_vector((C_XIP_SPICR_REG_WIDTH-1) downto 0);
-----
begin
-----
---------------------------------------
XIPCR_CPHA_CPOL_STORE_P:process(Bus2IP_Clk)is
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
XIPCR_data_int((C_XIP_SPICR_REG_WIDTH-1) downto (C_XIP_SPICR_REG_WIDTH-C_XIP_SPICR_REG_WIDTH))
<= "00";
elsif(ip2Bus_WrAck_core = '1') and (Bus2IP_XIPCR_WrCE = '1')then
XIPCR_data_int((C_XIP_SPICR_REG_WIDTH-1) downto (0))
<= Bus2IP_XIPCR_data
((C_XIP_SPICR_REG_WIDTH-1) downto (0));
end if;
end if;
end process XIPCR_CPHA_CPOL_STORE_P;
------------------------------------
XIPCR_1_CPOL <= XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-1);
XIPCR_0_CPHA <= XIPCR_data_int(0);
XIPCR_REG_RD_GENERATE: for i in C_XIP_SPICR_REG_WIDTH-1 downto 0 generate
-----
begin
-----
IP2Bus_XIPCR_Data(i) <= XIPCR_data_int(i) and Bus2IP_XIPCR_RdCE;
end generate XIPCR_REG_RD_GENERATE;
-----------------------------------
TO_XIPSR_CPHA_CPOL_ERR <= (XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-1)) xor
(XIPCR_data_int(C_XIP_SPICR_REG_WIDTH-C_XIP_SPICR_REG_WIDTH));
end imp;
--------------------------------------------------------------------------------
|
mit
|
9cd7214267379b750250b287e1451502
| 0.422133 | 4.784021 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/CPU/EX_MEM.vhd
| 1 | 2,489 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:25:31 11/21/2013
-- Design Name:
-- Module Name: EX_MEM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity EX_MEM is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteIn : in STD_LOGIC;
MemReadInput : in STD_LOGIC;
MemWriteInput : in STD_LOGIC;
MemtoRegInput : in STD_LOGIC;
RegWriteInput: in STD_LOGIC;
RegWriteOutput: out STD_LOGIC;
MemReadOutput : out STD_LOGIC;
MemWriteOutput : out STD_LOGIC;
MemtoRegOutput : out STD_LOGIC;
RegResultInput: in Int16;
RegResultOutput: out Int16;
DataInput : in STD_LOGIC_VECTOR (15 downto 0);
DataOutput : out STD_LOGIC_VECTOR (15 downto 0);
RegReadInput1 : in STD_LOGIC_VECTOR (3 downto 0);
RegReadInput2 : in STD_LOGIC_VECTOR (3 downto 0);
RegWriteToInput : in STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput1 : out STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput2 : out STD_LOGIC_VECTOR (3 downto 0);
RegWriteToOutput : out STD_LOGIC_VECTOR (3 downto 0);
retinput: in std_logic;
retoutput: out std_logic
);
end EX_MEM;
architecture Behavioral of EX_MEM is
begin
process (rst, clk, WriteIn)
begin
if (rst = '0') then
MemReadOutput <= '0';
MemWriteOutput <= '0';
MemtoRegOutput <= '0';
RegWriteOutput <= '0';
RegResultOutput <= RegResultInput;
retoutput <= '0';
elsif (clk'event and clk = '1') then
if (WriteIn = '1') then
MemReadOutput <= MemReadInput;
MemWriteOutput <= MemWriteInput;
MemtoRegOutput <= MemtoRegInput;
RegWriteOutput <= RegWriteInput;
RegReadOutput1 <= RegReadInput1;
RegReadOutput2 <= RegReadInput2;
RegWriteToOutput <= RegWriteToInput;
RegResultOutput <= RegResultInput;
DataOutput <= DataInput;
retoutput <= retinput;
end if;
end if;
end process;
end Behavioral;
|
mit
|
91bfcb95409ea4dadce23fca4a2fb194
| 0.642025 | 3.607246 | false | false | false | false |
1995parham/FPGA-Homework
|
Project-Phase1/src/concurrent/controller.vhd
| 1 | 1,974 |
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 23-04-2016
-- Module Name: controller.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity controller is
port (clk, reset : in std_logic;
sel : out std_logic_vector(7 downto 0);
memory_rwbar, memory_en, memory_reset : out std_logic);
end entity controller;
architecture rtl of controller is
type state is (rst, fitness_process, memory_read, increase, memory_write);
signal next_state, current_state : state;
begin
-- next
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
current_state <= rst;
else
current_state <= next_state;
end if;
end if;
end process;
-- outputs
process (current_state)
variable I : std_logic_vector(7 downto 0) := (0 => '1', others => '0');
begin
if current_state = rst then
I := (0 => '1', others => '0');
memory_reset <= '1';
memory_en <= '0';
elsif current_state = fitness_process then
memory_reset <= '0';
memory_en <= '0';
elsif current_state = memory_read then
sel <= I;
memory_en <= '1';
memory_rwbar <= '1';
elsif current_state = memory_write then
memory_rwbar <= '0';
I := I + 1;
end if;
end process;
-- next_state
process (current_state)
variable I : integer := 1;
begin
if current_state = rst then
I := 1;
next_state <= fitness_process;
elsif current_state = fitness_process then
next_state <= memory_read;
elsif current_state = memory_read then
next_state <= increase;
elsif current_state = increase then
next_state <= memory_write;
elsif current_state = memory_write then
I := I + 1;
if I < 120 then
next_state <= fitness_process;
else
next_state <= rst;
end if;
end if;
end process;
end architecture rtl;
|
gpl-3.0
|
4a498cb1e8fd39a304818ee26c6844c5
| 0.591185 | 3.26281 | false | false | false | false |
sunoc/vhdl-lz4-variation
|
z_old/lz4_entryBuffer.vhdl
| 1 | 2,802 |
library ieee;
use ieee.std_logic_1164.all;
use work.lz4_pkg.all;
entity lz4_entryBuffer is
port (
clk_i : in std_logic;
reset_i : in std_logic;
entryStream_i : in std_logic;
toUTVal_o : out std_logic_vector(31 downto 0);
buffPoint_o : out std_logic_vector(12 downto 0);
-- flags:
Fs : in std_logic_vector(2 downto 0);
eof : out std_logic;
-- data to the output level
pos_i : in std_logic_vector(12 downto 0);
len_i : in std_logic_vector(12 downto 0);
literal_o : out std_logic_vector(31 downto 0);
-- output to the hash
CLR_o : out std_logic;
I_DATA_o : out std_logic_vector(31 downto 0);
I_ENA_o : out std_logic_vector(3 downto 0);
I_DONE_o : out std_logic;
I_LAST_o : out std_logic;
I_VAL_o : out std_logic;
O_RDY_o : out std_logic
);
end lz4_entryBuffer;
architecture behavior of lz4_entryBuffer is
signal entryBuffer_s : std_logic_vector(80000 downto 0); -- about 10kB entry
-- buffer
signal buffPoint_f : integer;
begin
-- process to fill the entry buffer
process
begin
-- maybe change the clk rising edge with a signal from the data steam
if rising_edge(clk_i) then
for i in entryBuffer_s'low to entryBuffer_s'high loop
entryBuffer_s(i) <= entryStream_i;
end loop;
end if;
end process;
-- process to manage the flags from the FSM
process
begin
-- wait for a change in the Fe flag
if (Fs'event) then
if (Fs = "000") then -- "beginning" state
toUTVal_o <= entryBuffer_s(buffPoint_f+31 downto buffPoint_f); -- minmatch
buffPoint_f <= buffPoint_f+4;
-- check for the end of the buffer
if (buffPoint_f >= entryBuffer_s'high) then
eof <= '1';
end if;
elsif (Fs = "001" or Fs = "010") then -- "(no) match" states
toUTVal_o(7 downto 0) <= entryBuffer_s(buffPoint_f+7 downto buffPoint_f);
-- one more byte
buffPoint_f <= buffPoint_f+4;
-- check for the end of the buffer
if (buffPoint_f >= entryBuffer_s'high) then
eof <= '1';
end if;
elsif (Fs = "100") then -- "no more match" state
-- wait for the next state
elsif (Fs = "111") then -- "end" state
--hash all the buffer and send the result to the assembly
else
report "Error with the Fs flag in entrybuffer" severity error;
end if;
end if;
end process;
end;
|
gpl-3.0
|
a25eaec1502f1b21d277f6ae44831974
| 0.532834 | 3.756032 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/synth/zynq_1_axi_bram_ctrl_0_0.vhd
| 1 | 16,574 |
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:3.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v3_0;
USE axi_bram_ctrl_v3_0.axi_bram_ctrl;
ENTITY zynq_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_1_axi_bram_ctrl_0_0;
ARCHITECTURE zynq_1_axi_bram_ctrl_0_0_arch OF zynq_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_MEMORY_DEPTH : INTEGER;
C_FAMILY : STRING;
C_BRAM_INST_MODE : STRING;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zynq_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_1_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "zynq_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zynq_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "zynq_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=3.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,C_MEMORY_DEPTH=1024,C_FAMILY=zynq,C_BRAM_INST_MODE=EXTERNAL,C_BRAM_ADDR_WIDTH=10,C_S_AXI_ADDR_WIDTH=12,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=12,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_MEMORY_DEPTH => 1024,
C_FAMILY => "zynq",
C_BRAM_INST_MODE => "EXTERNAL",
C_BRAM_ADDR_WIDTH => 10,
C_S_AXI_ADDR_WIDTH => 12,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zynq_1_axi_bram_ctrl_0_0_arch;
|
mit
|
f27ce3b7baf8ccb387188f14f53edf86
| 0.675335 | 3.056242 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/srl_fifo.vhd
| 1 | 11,966 |
-------------------------------------------------------------------------------
-- $Id: srl_fifo.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2013 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2001-05-11 First Version
-- KC 2001-06-20 Added Addr as an output port, for use as an occupancy
-- value
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
buffer_Full <= '1' when (addr_i = "1111") else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
Addr <= addr_i;
end process;
end architecture IMP;
|
mit
|
9c1751ee935fecd91794d020f26a98ac
| 0.436821 | 4.373538 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/wr_chnl.vhd
| 7 | 186,980 |
-------------------------------------------------------------------------------
-- wr_chnl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wr_chnl.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller write channel interfaces. Controls all
-- handshaking and data flow on the AXI write address (AW),
-- write data (W) and write response (B) channels.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/3/2011 v1.03a
-- ~~~~~~
-- Edits for scalability and support of 512 and 1024-bit data widths.
-- ^^^^^^
-- JLJ 2/10/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter.
-- ^^^^^^
-- JLJ 2/14/2011 v1.03a
-- ~~~~~~
-- Shift Hsiao ECC generate logic so not dependent on C_S_AXI_DATA_WIDTH.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update WE size based on 128-bit ECC configuration.
-- Update for usage of ecc_gen.vhd module directly from MIG.
-- Clean-up XST warnings.
-- ^^^^^^
-- JLJ 2/22/2011 v1.03a
-- ~~~~~~
-- Found issue with ECC decoding on read path. Remove MSB '0' usage
-- in syndrome calculation, since h_matrix is based on 32 + 7 = 39 bits.
-- ^^^^^^
-- JLJ 2/23/2011 v1.03a
-- ~~~~~~
-- Code clean-up.
-- Move all MIG functions to package body.
-- ^^^^^^
-- JLJ 2/28/2011 v1.03a
-- ~~~~~~
-- Fix mapping on BRAM_WE with bram_we_int for 128-bit w/ ECC.
-- ^^^^^^
-- JLJ 3/1/2011 v1.03a
-- ~~~~~~
-- Fix XST handling for DIV functions. Create seperate process when
-- divisor is not constant and a power of two.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- Fix double clock assertion of CE/UE error flags when asserted
-- during the RMW sequence.
-- ^^^^^^
-- JLJ 3/23/2011 v1.03a
-- ~~~~~~
-- Code clean-up.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Add code coverage on/off statements.
-- ^^^^^^
-- JLJ 4/8/2011 v1.03a
-- ~~~~~~
-- Modify back-to-back capability to remove combinatorial loop
-- on WREADY to AXI interface. Add internal constant, C_REG_WREADY.
-- Update axi_wready_int reset value (ensure it is '0').
--
-- Create new SM for C_REG_WREADY with dual port. Seperate assertion of BVALID
-- from WREADY. Create a FIFO to store AWID/BID values.
-- Use counter (with max of 8 ID values) to allow WREADY assertions
-- to be ahead of BVALID assertions.
-- Add sub module, SRL_FIFO.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Implement similar updates on WREADY for single port & ECC configurations.
-- Remove use of signal, axi_wready_sng with constant, C_REG_WREADY.
--
-- For single port operation with registered WREADY, provide BVALID counter
-- value to arbitration SM, add output signal, AW2Arb_BVALID_Cnt.
--
-- Create an additional SM for single port when C_REG_WREADY.
-- ^^^^^^
-- JLJ 4/14/2011 v1.03a
-- ~~~~~~
-- Remove attempt to create AXI write data pipeline full flag outside of SM
-- logic. Add corner case checks for BID FIFO/BVALID counter.
-- ^^^^^^
-- JLJ 4/15/2011 v1.03a
-- ~~~~~~
-- Clean up all code not related to C_REG_WREADY.
-- Goal to remove internal constant, C_REG_WREADY.
-- Work on size optimization. Implement signals to represent BVALID
-- counter values.
-- ^^^^^^
-- JLJ 4/20/2011 v1.03a
-- ~~~~~~
-- Code clean up. Remove unused signals.
-- Remove additional generate blocks with C_REG_WREADY.
-- ^^^^^^
-- JLJ 4/21/2011 v1.03a
-- ~~~~~~
-- Code clean up. Remove use of IF_IS_AXI4 constant.
-- Create new SM TYPE for each configuration.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Add check in data SM on back-to-back for BVALID counter max.
-- Clean up AXI_WREADY generate blocks.
-- ^^^^^^
-- JLJ 4/22/2011 v1.03a
-- ~~~~~~
-- Code clean up.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- Hard code C_USE_LUT6 constant.
-- ^^^^^^
-- JLJ 5/26/2011 v1.03a
-- ~~~~~~
-- Fix CR # 609695.
-- Modify usage of WLAST. Ensure that WLAST is qualified with
-- WVALID/WREADY assertions.
--
-- With CR # 609695, update else clause for narrow_burst_cnt_ld to
-- remove simulation warnings when axi_byte_div_curr_awsize = zero.
--
-- Catch code clean up with WLAST in data SM for axi_wr_burst_cmb
-- signal assertion.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.srl_fifo;
use work.wrap_brst;
use work.ua_narrow;
use work.checkbit_handler;
use work.checkbit_handler_64;
use work.correct_one_bit;
use work.correct_one_bit_64;
use work.ecc_gen;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wr_chnl is
generic (
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 2;
-- Adjust factor to BRAM address width based on data width (in bits)
C_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_SUPPORTS_NARROW : INTEGER := 1;
-- Support for narrow burst operations
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to "AXI4LITE" to optimize out burst transaction support
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0 -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
);
port (
-- AXI Global Signals
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
-- AXI Write Address Channel Signals (AW)
AXI_AWID : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_AWADDR : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWLEN : in std_logic_vector(7 downto 0);
-- Specifies the number of data transfers in the burst
-- "0000 0000" 1 data transfer
-- "0000 0001" 2 data transfers
-- ...
-- "1111 1111" 256 data transfers
AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- Specifies the max number of data bytes to transfer in each data beat
-- "000" 1 byte to transfer
-- "001" 2 bytes to transfer
-- "010" 3 bytes to transfer
-- ...
AXI_AWBURST : in std_logic_vector(1 downto 0);
-- Specifies burst type
-- "00" FIXED = Fixed burst address (handled as INCR)
-- "01" INCR = Increment burst address
-- "10" WRAP = Incrementing address burst that wraps to lower order address at boundary
-- "11" Reserved (not checked)
AXI_AWLOCK : in std_logic; -- Currently unused
AXI_AWCACHE : in std_logic_vector(3 downto 0); -- Currently unused
AXI_AWPROT : in std_logic_vector(2 downto 0); -- Currently unused
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic;
-- AXI Write Data Channel Signals (W)
AXI_WDATA : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0);
AXI_WSTRB : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0);
AXI_WLAST : in std_logic;
AXI_WVALID : in std_logic;
AXI_WREADY : out std_logic;
-- AXI Write Data Response Channel Signals (B)
AXI_BID : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0);
AXI_BRESP : out std_logic_vector(1 downto 0);
AXI_BVALID : out std_logic;
AXI_BREADY : in std_logic;
-- ECC Register Interface Signals
Enable_ECC : in std_logic;
BRAM_Addr_En : out std_logic := '0';
FaultInjectClr : out std_logic := '0';
CE_Failing_We : out std_logic := '0';
Sl_CE : out std_logic := '0';
Sl_UE : out std_logic := '0';
Active_Wr : out std_logic := '0';
FaultInjectData : in std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0);
FaultInjectECC : in std_logic_vector (C_ECC_WIDTH-1 downto 0);
-- Single Port Arbitration Signals
Arb2AW_Active : in std_logic;
AW2Arb_Busy : out std_logic := '0';
AW2Arb_Active_Clr : out std_logic := '0';
AW2Arb_BVALID_Cnt : out std_logic_vector (2 downto 0) := (others => '0');
Sng_BRAM_Addr_Rst : out std_logic := '0';
Sng_BRAM_Addr_Ld_En : out std_logic := '0';
Sng_BRAM_Addr_Ld : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
Sng_BRAM_Addr_Inc : out std_logic := '0';
Sng_BRAM_Addr : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
-- BRAM Write Port Interface Signals
BRAM_En : out std_logic := '0';
BRAM_WE : out std_logic_vector (C_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
BRAM_WrData : out std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0) := (others => '0');
BRAM_RdData : in std_logic_vector (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0)
);
end entity wr_chnl;
-------------------------------------------------------------------------------
architecture implementation of wr_chnl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- All functions defined in axi_bram_ctrl_funcs package.
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
constant RESP_OKAY : std_logic_vector (1 downto 0) := "00"; -- Normal access OK response
constant RESP_SLVERR : std_logic_vector (1 downto 0) := "10"; -- Slave error
-- For future support. constant RESP_EXOKAY : std_logic_vector (1 downto 0) := "01"; -- Exclusive access OK response
-- For future support. constant RESP_DECERR : std_logic_vector (1 downto 0) := "11"; -- Decode error
-- Set constants for AWLEN equal to a count of one or two beats.
constant AXI_AWLEN_ONE : std_logic_vector (7 downto 0) := (others => '0');
constant AXI_AWLEN_TWO : std_logic_vector (7 downto 0) := "00000001";
constant AXI_AWSIZE_ONE : std_logic_vector (2 downto 0) := "001";
-- Determine maximum size for narrow burst length counter
-- When C_AXI_DATA_WIDTH = 32, minimum narrow width burst is 8 bits
-- resulting in a count 3 downto 0 => so minimum counter width = 2 bits.
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst is 8 bits
-- resulting in a count 31 downto 0 => so minimum counter width = 5 bits.
constant C_NARROW_BURST_CNT_LEN : integer := log2 (C_AXI_DATA_WIDTH/8);
constant NARROW_CNT_MAX : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-- AXI Size Constants
-- constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
-- constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
-- constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
-- constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
-- constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
-- constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
-- constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
-- constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine max value of ARSIZE based on the AXI data width.
-- Use function in axi_bram_ctrl_funcs package.
constant C_AXI_SIZE_MAX : std_logic_vector (2 downto 0) := Create_Size_Max (C_AXI_DATA_WIDTH);
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
-- Move to full_axi module
-- constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_AXI_DATA_WIDTH/8);
-- Not used
-- constant C_BRAM_ADDR_ADJUST : integer := C_AXI_ADDR_WIDTH - C_BRAM_ADDR_ADJUST_FACTOR;
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
-- AXI Burst Types
-- AXI Spec 4.4
constant C_AXI_BURST_WRAP : std_logic_vector (1 downto 0) := "10";
constant C_AXI_BURST_INCR : std_logic_vector (1 downto 0) := "01";
constant C_AXI_BURST_FIXED : std_logic_vector (1 downto 0) := "00";
-- Internal ECC data width size.
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_AXI_DATA_WIDTH);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type WR_ADDR_SM_TYPE is ( IDLE,
LD_AWADDR
);
signal wr_addr_sm_cs, wr_addr_sm_ns : WR_ADDR_SM_TYPE;
signal aw_active_set : std_logic := '0';
signal aw_active_set_i : std_logic := '0';
signal aw_active_clr : std_logic := '0';
signal delay_aw_active_clr_cmb : std_logic := '0';
signal delay_aw_active_clr : std_logic := '0';
signal aw_active : std_logic := '0';
signal aw_active_d1 : std_logic := '0';
signal aw_active_re : std_logic := '0';
signal axi_awaddr_pipe : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal curr_awaddr_lsb : std_logic_vector (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0) := (others => '0');
signal awaddr_pipe_ld : std_logic := '0';
signal awaddr_pipe_ld_i : std_logic := '0';
signal awaddr_pipe_sel : std_logic := '0';
-- '0' indicates mux select from AXI
-- '1' indicates mux select from AW Addr Register
signal axi_awaddr_full : std_logic := '0';
signal axi_awid_pipe : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_awsize_pipe : std_logic_vector(2 downto 0) := (others => '0');
signal curr_awsize : std_logic_vector(2 downto 0) := (others => '0');
signal curr_awsize_reg : std_logic_vector (2 downto 0) := (others => '0');
-- Narrow Burst Signals
signal curr_narrow_burst_cmb : std_logic := '0';
signal curr_narrow_burst : std_logic := '0';
signal curr_narrow_burst_en : std_logic := '0';
signal narrow_burst_cnt_ld : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_reg : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_burst_cnt_ld_mod : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal narrow_addr_rst : std_logic := '0';
signal narrow_addr_ld_en : std_logic := '0';
signal narrow_addr_dec : std_logic := '0';
signal axi_awlen_pipe : std_logic_vector(7 downto 0) := (others => '0');
signal axi_awlen_pipe_1_or_2 : std_logic := '0';
signal curr_awlen : std_logic_vector(7 downto 0) := (others => '0');
signal curr_awlen_reg : std_logic_vector(7 downto 0) := (others => '0');
signal curr_awlen_reg_1_or_2 : std_logic := '0';
signal axi_awburst_pipe : std_logic_vector(1 downto 0) := (others => '0');
signal axi_awburst_pipe_fixed : std_logic := '0';
signal curr_awburst : std_logic_vector(1 downto 0) := (others => '0');
signal curr_wrap_burst : std_logic := '0';
signal curr_wrap_burst_reg : std_logic := '0';
signal curr_incr_burst : std_logic := '0';
signal curr_fixed_burst : std_logic := '0';
signal curr_fixed_burst_reg : std_logic := '0';
signal max_wrap_burst_mod : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_aresetn_d1 : std_logic := '0';
signal axi_aresetn_d2 : std_logic := '0';
signal axi_aresetn_re : std_logic := '0';
signal axi_aresetn_re_reg : std_logic := '0';
-- BRAM Address Counter
signal bram_addr_ld_en : std_logic := '0';
signal bram_addr_ld_en_i : std_logic := '0';
signal bram_addr_ld_en_mod : std_logic := '0';
signal bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_ld_wrap : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_addr_inc : std_logic := '0';
signal bram_addr_inc_mod : std_logic := '0';
signal bram_addr_inc_wrap_mod : std_logic := '0';
signal bram_addr_rst : std_logic := '0';
signal bram_addr_rst_cmb : std_logic := '0';
signal narrow_bram_addr_inc : std_logic := '0';
signal narrow_bram_addr_inc_d1 : std_logic := '0';
signal narrow_bram_addr_inc_re : std_logic := '0';
signal narrow_addr_int : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
signal curr_ua_narrow_wrap : std_logic := '0';
signal curr_ua_narrow_incr : std_logic := '0';
signal ua_narrow_load : std_logic_vector (C_NARROW_BURST_CNT_LEN-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- AXI Write Data Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type WR_DATA_SM_TYPE is ( IDLE,
W8_AWADDR,
-- W8_BREADY,
SNG_WR_DATA,
BRST_WR_DATA,
-- NEW_BRST_WR_DATA,
B2B_W8_WR_DATA --,
-- B2B_W8_BRESP,
-- W8_BRESP
);
signal wr_data_sm_cs, wr_data_sm_ns : WR_DATA_SM_TYPE;
type WR_DATA_SNG_SM_TYPE is ( IDLE,
SNG_WR_DATA,
BRST_WR_DATA );
signal wr_data_sng_sm_cs, wr_data_sng_sm_ns : WR_DATA_SNG_SM_TYPE;
type WR_DATA_ECC_SM_TYPE is ( IDLE,
RMW_RD_DATA,
RMW_CHK_DATA,
RMW_MOD_DATA,
RMW_WR_DATA );
signal wr_data_ecc_sm_cs, wr_data_ecc_sm_ns : WR_DATA_ECC_SM_TYPE;
-- Wr Data Buffer/Register
signal wrdata_reg_ld : std_logic := '0';
signal axi_wready_int : std_logic := '0';
signal axi_wready_int_mod : std_logic := '0';
signal axi_wdata_full_cmb : std_logic := '0';
signal axi_wdata_full : std_logic := '0';
signal axi_wdata_empty : std_logic := '0';
signal axi_wdata_full_reg : std_logic := '0';
-- WE Generator Signals
signal clr_bram_we_cmb : std_logic := '0';
signal clr_bram_we : std_logic := '0';
signal bram_we_ld : std_logic := '0';
signal axi_wr_burst_cmb : std_logic := '0';
signal axi_wr_burst : std_logic := '0';
signal wr_b2b_elgible : std_logic := '0';
-- CR # 609695 signal last_data_ack : std_logic := '0';
-- CR # 609695 signal last_data_ack_throttle : std_logic := '0';
signal last_data_ack_mod : std_logic := '0';
-- CR # 609695 signal w8_b2b_bresp : std_logic := '0';
signal axi_wlast_d1 : std_logic := '0';
signal axi_wlast_re : std_logic := '0';
-- Single Port Signals
-- Write busy flags only used in ECC configuration
-- when waiting for BVALID/BREADY handshake
signal wr_busy_cmb : std_logic := '0';
signal wr_busy_reg : std_logic := '0';
-- Only used by ECC register module.
signal active_wr_cmb : std_logic := '0';
signal active_wr_reg : std_logic := '0';
-------------------------------------------------------------------------------
-- AXI Write Response Channel Signals
-------------------------------------------------------------------------------
signal axi_bid_temp : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_bid_temp_full : std_logic := '0';
signal axi_bid_int : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal axi_bresp_int : std_logic_vector (1 downto 0) := (others => '0');
signal axi_bvalid_int : std_logic := '0';
signal axi_bvalid_set_cmb : std_logic := '0';
-------------------------------------------------------------------------------
-- Internal BRAM Signals
-------------------------------------------------------------------------------
signal reset_bram_we : std_logic := '0';
signal set_bram_we_cmb : std_logic := '0';
signal set_bram_we : std_logic := '0';
signal bram_we_int : std_logic_vector (C_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal bram_en_cmb : std_logic := '0';
signal bram_en_int : std_logic := '0';
signal bram_addr_int : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
signal bram_wrdata_int : std_logic_vector (C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- ECC Signals
-------------------------------------------------------------------------------
signal CorrectedRdData : std_logic_vector(0 to C_AXI_DATA_WIDTH-1);
signal RdModifyWr_Modify : std_logic := '0'; -- Modify cycle in read modify write sequence
signal RdModifyWr_Write : std_logic := '0'; -- Write cycle in read modify write sequence
signal WrData : std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal WrData_cmb : std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal UE_Q : std_logic := '0';
-------------------------------------------------------------------------------
-- BVALID Signals
-------------------------------------------------------------------------------
signal bvalid_cnt_inc : std_logic := '0';
signal bvalid_cnt_inc_d1 : std_logic := '0';
signal bvalid_cnt_dec : std_logic := '0';
signal bvalid_cnt : std_logic_vector (2 downto 0) := (others => '0');
signal bvalid_cnt_amax : std_logic := '0';
signal bvalid_cnt_max : std_logic := '0';
signal bvalid_cnt_non_zero : std_logic := '0';
-------------------------------------------------------------------------------
-- BID FIFO Signals
-------------------------------------------------------------------------------
signal bid_fifo_rst : std_logic := '0';
signal bid_fifo_ld_en : std_logic := '0';
signal bid_fifo_ld : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal bid_fifo_rd_en : std_logic := '0';
signal bid_fifo_rd : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
signal bid_fifo_not_empty : std_logic := '0';
signal bid_gets_fifo_load : std_logic := '0';
signal bid_gets_fifo_load_d1 : std_logic := '0';
signal first_fifo_bid : std_logic := '0';
signal b2b_fifo_bid : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
---------------------------------------------------------------------------
AXI_AWREADY <= axi_awready_int;
---------------------------------------------------------------------------
-- AXI Write Data Channel Output Signals
---------------------------------------------------------------------------
-- WREADY same signal assertion regardless of ECC or single port configuration.
AXI_WREADY <= axi_wready_int_mod;
---------------------------------------------------------------------------
-- AXI Write Response Channel Output Signals
---------------------------------------------------------------------------
AXI_BRESP <= axi_bresp_int;
AXI_BVALID <= axi_bvalid_int;
AXI_BID <= axi_bid_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_AW_PIPE_SNG
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AW_PIPE_SNG: if C_SINGLE_PORT_BRAM = 1 generate
begin
-- Unused AW pipeline (set default values)
awaddr_pipe_ld <= '0';
axi_awaddr_pipe <= AXI_AWADDR;
axi_awid_pipe <= AXI_AWID;
axi_awsize_pipe <= AXI_AWSIZE;
axi_awlen_pipe <= AXI_AWLEN;
axi_awburst_pipe <= AXI_AWBURST;
axi_awlen_pipe_1_or_2 <= '0';
axi_awburst_pipe_fixed <= '0';
axi_awaddr_full <= '0';
end generate GEN_AW_PIPE_SNG;
---------------------------------------------------------------------------
-- Generate: GEN_AW_PIPE_DUAL
-- Purpose: Only generate pipeline registers when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AW_PIPE_DUAL: if C_SINGLE_PORT_BRAM = 0 generate
begin
-----------------------------------------------------------------------
--
-- AXI Write Address Buffer/Register
-- (mimic behavior of address pipeline for AXI_AWID)
--
-----------------------------------------------------------------------
GEN_AWADDR: for i in C_AXI_ADDR_WIDTH-1 downto 0 generate
begin
REG_AWADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (awaddr_pipe_ld = '1') then
axi_awaddr_pipe (i) <= AXI_AWADDR (i);
else
axi_awaddr_pipe (i) <= axi_awaddr_pipe (i);
end if;
end if;
end process REG_AWADDR;
end generate GEN_AWADDR;
-----------------------------------------------------------------------
-- Register AWID
REG_AWID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (awaddr_pipe_ld = '1') then
axi_awid_pipe <= AXI_AWID;
else
axi_awid_pipe <= axi_awid_pipe;
end if;
end if;
end process REG_AWID;
---------------------------------------------------------------------------
-- In parallel to AWADDR pipeline and AWID
-- Use same control signals to capture AXI_AWSIZE, AXI_AWLEN & AXI_AWBURST.
-- Register AXI_AWSIZE, AXI_AWLEN & AXI_AWBURST
REG_AWCTRL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (awaddr_pipe_ld = '1') then
axi_awsize_pipe <= AXI_AWSIZE;
axi_awlen_pipe <= AXI_AWLEN;
axi_awburst_pipe <= AXI_AWBURST;
else
axi_awsize_pipe <= axi_awsize_pipe;
axi_awlen_pipe <= axi_awlen_pipe;
axi_awburst_pipe <= axi_awburst_pipe;
end if;
end if;
end process REG_AWCTRL;
---------------------------------------------------------------------------
-- Create signals that indicate value of AXI_AWLEN in pipeline stage
-- Used to decode length of burst when BRAM address can be loaded early
-- when pipeline is full.
--
-- Add early decode of AWBURST in pipeline.
REG_AWLEN_PIPE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (awaddr_pipe_ld = '1') then
-- Create merge to decode AWLEN of ONE or TWO
if (AXI_AWLEN = AXI_AWLEN_ONE) or (AXI_AWLEN = AXI_AWLEN_TWO) then
axi_awlen_pipe_1_or_2 <= '1';
else
axi_awlen_pipe_1_or_2 <= '0';
end if;
-- Early decode on value in pipeline of AWBURST
if (AXI_AWBURST = C_AXI_BURST_FIXED) then
axi_awburst_pipe_fixed <= '1';
else
axi_awburst_pipe_fixed <= '0';
end if;
else
axi_awlen_pipe_1_or_2 <= axi_awlen_pipe_1_or_2;
axi_awburst_pipe_fixed <= axi_awburst_pipe_fixed;
end if;
end if;
end process REG_AWLEN_PIPE;
---------------------------------------------------------------------------
-- Create full flag for AWADDR pipeline
-- Set when write address register is loaded.
-- Cleared when write address stored in register is loaded into BRAM
-- address counter.
REG_WRADDR_FULL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(bram_addr_ld_en = '1' and awaddr_pipe_sel = '1') then
axi_awaddr_full <= '0';
elsif (awaddr_pipe_ld = '1') then
axi_awaddr_full <= '1';
else
axi_awaddr_full <= axi_awaddr_full;
end if;
end if;
end process REG_WRADDR_FULL;
---------------------------------------------------------------------------
end generate GEN_AW_PIPE_DUAL;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL_ADDR_CNT
-- Purpose: Instantiate BRAM address counter unique for wr_chnl logic
-- only when controller configured in dual port mode.
---------------------------------------------------------------------------
GEN_DUAL_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 0) generate
begin
----------------------------------------------------------------------------
-- Replace I_ADDR_CNT module usage of pf_counter in proc_common library.
-- Only need to use lower 12-bits of address due to max AXI burst size
-- Since AXI guarantees bursts do not cross 4KB boundary, the counting part
-- of I_ADDR_CNT can be reduced to max 4KB.
--
-- Counter size is adjusted based on data width of BRAM.
-- For example, 32-bit data width BRAM, BRAM_Addr (1:0)
-- are fixed at "00". So, counter increments from
-- (C_AXI_ADDR_WIDTH - 1 : C_BRAM_ADDR_ADJUST).
----------------------------------------------------------------------------
I_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Reset usage differs from RD CHNL
if (bram_addr_rst = '1') then
bram_addr_int <= (others => '0');
elsif (bram_addr_ld_en_mod = '1') then
bram_addr_int <= bram_addr_ld;
elsif (bram_addr_inc_mod = '1') then
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process I_ADDR_CNT;
-- Set defaults to shared address counter
-- Only used in single port configurations
Sng_BRAM_Addr_Rst <= '0';
Sng_BRAM_Addr_Ld_En <= '0';
Sng_BRAM_Addr_Ld <= (others => '0');
Sng_BRAM_Addr_Inc <= '0';
end generate GEN_DUAL_ADDR_CNT;
---------------------------------------------------------------------------
-- Generate: GEN_SNG_ADDR_CNT
-- Purpose: When configured in single port BRAM mode, address counter
-- is shared with rd_chnl module. Assign output signals here
-- to counter instantiation at full_axi module level.
---------------------------------------------------------------------------
GEN_SNG_ADDR_CNT: if (C_SINGLE_PORT_BRAM = 1) generate
begin
Sng_BRAM_Addr_Rst <= bram_addr_rst;
Sng_BRAM_Addr_Ld_En <= bram_addr_ld_en_mod;
Sng_BRAM_Addr_Ld <= bram_addr_ld;
Sng_BRAM_Addr_Inc <= bram_addr_inc_mod;
bram_addr_int <= Sng_BRAM_Addr;
end generate GEN_SNG_ADDR_CNT;
---------------------------------------------------------------------------
--
-- Add BRAM counter reset for @ end of transfer
--
-- Create a unique BRAM address reset signal
-- If the write transaction is throttling on the AXI bus, then
-- the BRAM EN may get negated during the write transfer
--
-- Use combinatorial output from SM, bram_addr_rst_cmb, but ensure the
-- BRAM address is not reset while loading a new address.
bram_addr_rst <= (not (S_AXI_AResetn)) or (bram_addr_rst_cmb and
not (bram_addr_ld_en_mod) and not (bram_addr_inc_mod));
---------------------------------------------------------------------------
-- BRAM address counter load mux
--
-- Either load BRAM counter directly from AXI bus or from stored registered value
--
-- Added bram_addr_ld_wrap for loading on wrap burst types
-- Use registered signal to indicate current operation is a WRAP burst
--
-- Do not load bram_addr_ld_wrap when bram_addr_ld_en signal is asserted at beginning of write burst
-- BRAM address counter load. Due to condition when max_wrap_burst_mod remains asserted, due to BRAM address
-- counter not incrementing (at the end of the previous write burst).
-- bram_addr_ld <= bram_addr_ld_wrap when
-- (max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_ld_en = '0') else
-- axi_awaddr_pipe (C_BRAM_ADDR_SIZE-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
-- when (awaddr_pipe_sel = '1') else
-- AXI_AWADDR (C_BRAM_ADDR_SIZE-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
-- Replace C_BRAM_ADDR_SIZE w/ C_AXI_ADDR_WIDTH parameter usage
bram_addr_ld <= bram_addr_ld_wrap when
(max_wrap_burst_mod = '1' and curr_wrap_burst_reg = '1' and bram_addr_ld_en = '0') else
axi_awaddr_pipe (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
when (awaddr_pipe_sel = '1') else
AXI_AWADDR (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR);
---------------------------------------------------------------------------
-- On wrap burst max loads (simultaneous BRAM address increment is asserted).
-- Ensure that load has higher priority over increment.
-- Use registered signal to indicate current operation is a WRAP burst
-- bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or
-- (max_wrap_burst_mod = '1' and
-- curr_wrap_burst_reg = '1' and
-- bram_addr_inc_mod = '1'))
-- else '0';
-- Use duplicate version of bram_addr_ld_en in effort
-- to reduce fanout of signal routed to BRAM address counter
bram_addr_ld_en_mod <= '1' when (bram_addr_ld_en = '1' or
(max_wrap_burst_mod = '1' and
curr_wrap_burst_reg = '1' and
bram_addr_inc_wrap_mod = '1'))
else '0';
-- Create a special bram_addr_inc_mod for use in the bram_addr_ld_en_mod signal
-- logic. No need for the check if the current operation is NOT a fixed AND a wrap
-- burst. The transfer will be one or the other.
-- Found issue when narrow FIXED length burst is incorrectly
-- incrementing BRAM address counter
bram_addr_inc_wrap_mod <= bram_addr_inc when (curr_narrow_burst = '0')
else narrow_bram_addr_inc_re;
----------------------------------------------------------------------------
-- Handling for WRAP burst types
--
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Boundary is reached based on ARSIZE and ARLEN.
--
-- Goal is to minimize muxing on initial load of counter value.
-- On WRAP burst types, detect when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value set to '0'.
----------------------------------------------------------------------------
-- Detect valid WRAP burst types
curr_wrap_burst <= '1' when (curr_awburst = C_AXI_BURST_WRAP) else '0';
-- Detect INCR & FIXED burst type operations
curr_incr_burst <= '1' when (curr_awburst = C_AXI_BURST_INCR) else '0';
curr_fixed_burst <= '1' when (curr_awburst = C_AXI_BURST_FIXED) else '0';
----------------------------------------------------------------------------
-- Register curr_wrap_burst signal when BRAM address counter is initially
-- loaded
REG_CURR_WRAP_BRST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Add reset same as BRAM address counter
if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_rst = '1' and bram_addr_ld_en = '0') then
curr_wrap_burst_reg <= '0';
elsif (bram_addr_ld_en = '1') then
curr_wrap_burst_reg <= curr_wrap_burst;
else
curr_wrap_burst_reg <= curr_wrap_burst_reg;
end if;
end if;
end process REG_CURR_WRAP_BRST;
----------------------------------------------------------------------------
-- Register curr_fixed_burst signal when BRAM address counter is initially
-- loaded
REG_CURR_FIXED_BRST: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Add reset same as BRAM address counter
if (S_AXI_AResetn = C_RESET_ACTIVE) or (bram_addr_rst = '1' and bram_addr_ld_en = '0') then
curr_fixed_burst_reg <= '0';
elsif (bram_addr_ld_en = '1') then
curr_fixed_burst_reg <= curr_fixed_burst;
else
curr_fixed_burst_reg <= curr_fixed_burst_reg;
end if;
end if;
end process REG_CURR_FIXED_BRST;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Instance: I_WRAP_BRST
--
-- Description:
--
-- Instantiate WRAP_BRST module
-- Logic to generate the wrap around value to load into the BRAM address
-- counter on WRAP burst transactions.
-- WRAP value is based on current AWLEN, AWSIZE (for narrows) and
-- data width of BRAM module.
--
---------------------------------------------------------------------------
I_WRAP_BRST : entity work.wrap_brst
generic map (
C_AXI_ADDR_WIDTH => C_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk ,
S_AXI_AResetn => S_AXI_AResetn ,
curr_axlen => curr_awlen ,
curr_axsize => curr_awsize ,
curr_narrow_burst => curr_narrow_burst ,
narrow_bram_addr_inc_re => narrow_bram_addr_inc_re ,
bram_addr_ld_en => bram_addr_ld_en ,
bram_addr_ld => bram_addr_ld ,
bram_addr_int => bram_addr_int ,
bram_addr_ld_wrap => bram_addr_ld_wrap ,
max_wrap_burst_mod => max_wrap_burst_mod
);
---------------------------------------------------------------------------
-- Generate: GEN_WO_NARROW
-- Purpose: Create BRAM address increment signal when narrow bursts
-- are disabled.
---------------------------------------------------------------------------
GEN_WO_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 0) generate
begin
-- For non narrow burst operations, use bram_addr_inc from data SM.
-- Add in check that burst type is not FIXED, curr_fixed_burst_reg
bram_addr_inc_mod <= bram_addr_inc and not (curr_fixed_burst_reg);
-- The signal, curr_narrow_burst should always be set to '0' when narrow bursts
-- are disabled.
curr_narrow_burst <= '0';
narrow_bram_addr_inc_re <= '0';
end generate GEN_WO_NARROW;
---------------------------------------------------------------------------
-- Only instantiate NARROW_CNT and supporting logic when narrow transfers
-- are supported and utilized by masters in the AXI system.
-- The design parameter, C_S_AXI_SUPPORTS_NARROW will indicate this.
---------------------------------------------------------------------------
-- Generate: GEN_NARROW_CNT
-- Purpose: Instantiate narrow counter and logic when narrow
-- operation support is enabled.
-- And, only instantiate logic for narrow operations when
-- AXI bus protocol is not set for AXI-LITE.
---------------------------------------------------------------------------
GEN_NARROW_CNT: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-- Based on current operation being a narrow burst, hold off BRAM
-- address increment until narrow burst fits BRAM data width.
-- For non narrow burst operations, use bram_addr_inc from data SM.
-- Add in check that burst type is not FIXED, curr_fixed_burst_reg
bram_addr_inc_mod <= (bram_addr_inc and not (curr_fixed_burst_reg)) when (curr_narrow_burst = '0')
-- else narrow_bram_addr_inc_re;
-- Seeing incorrect BRAM address increment on narrow
-- fixed length burst operations.
-- Add this check for curr_fixed_burst_reg
else (narrow_bram_addr_inc_re and not (curr_fixed_burst_reg));
---------------------------------------------------------------------------
--
-- Generate seperate smaller counter for narrow burst operations
-- Replace I_NARROW_CNT module usage of pf_counter_top from proc_common library.
--
-- Counter size is adjusted based on size of data burst.
--
-- For example, 32-bit data width BRAM, minimum narrow width
-- burst is 8 bits resulting in a count 3 downto 0. So the
-- minimum counter width = 2 bits.
--
-- When C_AXI_DATA_WIDTH = 256, minimum narrow width burst
-- is 8 bits resulting in a count 31 downto 0. So the
-- minimum counter width = 5 bits.
--
-- Size of counter = C_NARROW_BURST_CNT_LEN
--
---------------------------------------------------------------------------
I_NARROW_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (narrow_addr_rst = '1') then
narrow_addr_int <= (others => '0');
-- Load narrow address counter
elsif (narrow_addr_ld_en = '1') then
narrow_addr_int <= narrow_burst_cnt_ld_mod;
-- Decrement ONLY (no increment functionality)
elsif (narrow_addr_dec = '1') then
narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0) <=
std_logic_vector (unsigned (narrow_addr_int (C_NARROW_BURST_CNT_LEN-1 downto 0)) - 1);
end if;
end if;
end process I_NARROW_CNT;
---------------------------------------------------------------------------
narrow_addr_rst <= not (S_AXI_AResetn);
-- Narrow burst counter load mux
-- Modify narrow burst count load value based on
-- unalignment of AXI address value
-- Account for INCR burst types at unaligned addresses
narrow_burst_cnt_ld_mod <= ua_narrow_load when (curr_ua_narrow_wrap = '1' or curr_ua_narrow_incr = '1') else
narrow_burst_cnt_ld when (bram_addr_ld_en = '1') else
narrow_burst_cnt_ld_reg;
narrow_addr_dec <= bram_addr_inc when (curr_narrow_burst = '1') else '0';
narrow_addr_ld_en <= (curr_narrow_burst_cmb and bram_addr_ld_en) or narrow_bram_addr_inc_re;
narrow_bram_addr_inc <= '1' when (narrow_addr_int = NARROW_CNT_MAX) and (curr_narrow_burst = '1')
-- Ensure that narrow address counter doesn't
-- flag max or get loaded to
-- reset narrow counter until AXI read data
-- bus has acknowledged current
-- data on the AXI bus. Use rd_adv_buf signal
-- to indicate the non throttle
-- condition on the AXI bus.
and (bram_addr_inc = '1')
else '0';
-- Detect rising edge of narrow_bram_addr_inc
REG_NARROW_BRAM_ADDR_INC: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_bram_addr_inc_d1 <= '0';
else
narrow_bram_addr_inc_d1 <= narrow_bram_addr_inc;
end if;
end if;
end process REG_NARROW_BRAM_ADDR_INC;
narrow_bram_addr_inc_re <= '1' when (narrow_bram_addr_inc = '1') and
(narrow_bram_addr_inc_d1 = '0')
else '0';
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT;
---------------------------------------------------------------------------
-- Generate: GEN_AWREADY
-- Purpose: AWREADY is only created here when in dual port BRAM mode.
---------------------------------------------------------------------------
GEN_AWREADY: if (C_SINGLE_PORT_BRAM = 0) generate
begin
-- v1.03a
----------------------------------------------------------------------------
-- AXI_AWREADY Output Register
-- Description: Keep AXI_AWREADY output asserted until AWADDR pipeline
-- is full. When a full condition is reached, negate
-- AWREADY as another AW address can not be accepted.
-- Add condition to keep AWReady asserted if loading current
--- AWADDR pipeline value into the BRAM address counter.
-- Indicated by assertion of bram_addr_ld_en & awaddr_pipe_sel.
--
----------------------------------------------------------------------------
REG_AWREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_awready_int <= '0';
-- Detect end of S_AXI_AResetn to assert AWREADY and accept
-- new AWADDR values
elsif (axi_aresetn_re_reg = '1') or (bram_addr_ld_en = '1' and awaddr_pipe_sel = '1') then
axi_awready_int <= '1';
elsif (awaddr_pipe_ld = '1') then
axi_awready_int <= '0';
else
axi_awready_int <= axi_awready_int;
end if;
end if;
end process REG_AWREADY;
----------------------------------------------------------------------------
-- Need to detect end of reset cycle to assert AWREADY on AXI bus
REG_ARESETN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
axi_aresetn_d1 <= S_AXI_AResetn;
axi_aresetn_d2 <= axi_aresetn_d1;
axi_aresetn_re_reg <= axi_aresetn_re;
end if;
end process REG_ARESETN;
-- Create combinatorial RE detect of S_AXI_AResetn
axi_aresetn_re <= '1' when (S_AXI_AResetn = '1' and axi_aresetn_d1 = '0') else '0';
end generate GEN_AWREADY;
----------------------------------------------------------------------------
-- Specify current AWSIZE signal
-- Address pipeline MUX
curr_awsize <= axi_awsize_pipe when (awaddr_pipe_sel = '1') else AXI_AWSIZE;
-- Register curr_awsize when bram_addr_ld_en = '1'
REG_AWSIZE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_awsize_reg <= (others => '0');
elsif (bram_addr_ld_en = '1') then
curr_awsize_reg <= curr_awsize;
else
curr_awsize_reg <= curr_awsize_reg;
end if;
end if;
end process REG_AWSIZE;
---------------------------------------------------------------------------
--
-- Generate: GEN_NARROW_EN
-- Purpose: Only instantiate logic to determine if current burst
-- is a narrow burst when narrow bursting logic is supported.
--
---------------------------------------------------------------------------
GEN_NARROW_EN: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
-----------------------------------------------------------------------
-- Determine "narrow" burst transfers
-- Compare the AWSIZE to the BRAM data width
-----------------------------------------------------------------------
-- v1.03a
-- Detect if current burst operation is of size /= to the full
-- AXI data bus width. If not, then the current operation is a
-- "narrow" burst.
curr_narrow_burst_cmb <= '1' when (curr_awsize /= C_AXI_SIZE_MAX) else '0';
---------------------------------------------------------------------------
curr_narrow_burst_en <= '1' when (bram_addr_ld_en = '1') and
(curr_awlen /= AXI_AWLEN_ONE) and
(curr_fixed_burst = '0')
else '0';
-- Register flag indicating the current operation
-- is a narrow write burst
NARROW_BURST_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
-- Need to reset this flag at end of narrow burst operation
-- Use handshaking signals on AXI
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Check for back to back narrow burst. If that is the case, then
-- do not clear curr_narrow_burst flag.
(axi_wlast_re = '1' and
curr_narrow_burst_en = '0'
-- If ECC is enabled, no clear to curr_narrow_burst when WLAST is asserted
-- this causes the BRAM address to incorrectly get asserted on the last
-- beat in the burst (due to delay in RMW logic)
and C_ECC = 0) then
curr_narrow_burst <= '0';
elsif (curr_narrow_burst_en = '1') then
curr_narrow_burst <= curr_narrow_burst_cmb;
end if;
end if;
end process NARROW_BURST_REG;
---------------------------------------------------------------------------
-- Detect RE of AXI_WLAST
-- Only used when narrow bursts are enabled.
WLAST_REG: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_wlast_d1 <= '0';
else
-- axi_wlast_d1 <= AXI_WLAST and axi_wready_int_mod;
-- CR # 609695
axi_wlast_d1 <= AXI_WLAST and axi_wready_int_mod and AXI_WVALID;
end if;
end if;
end process WLAST_REG;
-- axi_wlast_re <= (AXI_WLAST and axi_wready_int_mod) and not (axi_wlast_d1);
-- CR # 609695
axi_wlast_re <= (AXI_WLAST and axi_wready_int_mod and AXI_WVALID) and not (axi_wlast_d1);
end generate GEN_NARROW_EN;
---------------------------------------------------------------------------
-- Generate registered flag that active burst is a "narrow" burst
-- and load narrow burst counter
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_NARROW_CNT_LD
-- Purpose: Only instantiate logic to determine narrow burst counter
-- load value when narrow bursts are enabled.
--
---------------------------------------------------------------------------
GEN_NARROW_CNT_LD: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
signal curr_awsize_unsigned : unsigned (2 downto 0) := (others => '0');
signal axi_byte_div_curr_awsize : integer := 1;
begin
-- v1.03a
-- Create narrow burst counter load value based on current operation
-- "narrow" data width (indicated by value of AWSIZE).
curr_awsize_unsigned <= unsigned (curr_awsize);
-- XST does not support divisors that are not constants and powers of 2.
-- Create process to create a fixed value for divisor.
-- Replace this statement:
-- narrow_burst_cnt_ld <= std_logic_vector (
-- to_unsigned (
-- (C_AXI_DATA_WIDTH_BYTES / (2**(to_integer (curr_awsize_unsigned))) ) - 1,
-- C_NARROW_BURST_CNT_LEN));
-- -- With this new process and subsequent signal assignment:
-- DIV_AWSIZE: process (curr_awsize_unsigned)
-- begin
--
-- case (to_integer (curr_awsize_unsigned)) is
-- when 0 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 1;
-- when 1 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 2;
-- when 2 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 4;
-- when 3 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 8;
-- when 4 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 16;
-- when 5 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 32;
-- when 6 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 64;
-- when 7 => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 128;
-- --coverage off
-- when others => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES;
-- --coverage on
-- end case;
--
-- end process DIV_AWSIZE;
-- w/ CR # 609695
-- With this new process and subsequent signal assignment:
DIV_AWSIZE: process (curr_awsize_unsigned)
begin
case (curr_awsize_unsigned) is
when "000" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 1;
when "001" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 2;
when "010" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 4;
when "011" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 8;
when "100" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 16;
when "101" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 32;
when "110" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 64;
when "111" => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES / 128;
--coverage off
when others => axi_byte_div_curr_awsize <= C_AXI_DATA_WIDTH_BYTES;
--coverage on
end case;
end process DIV_AWSIZE;
---------------------------------------------------------------------------
-- Create narrow burst count load value.
--
-- Size is based on [C_NARROW_BURST_CNT_LEN-1 : 0]
-- For 32-bit BRAM, C_NARROW_BURST_CNT_LEN = 2.
-- For 64-bit BRAM, C_NARROW_BURST_CNT_LEN = 3.
-- For 128-bit BRAM, C_NARROW_BURST_CNT_LEN = 4. (etc.)
--
-- Signal, narrow_burst_cnt_ld signal is sized according to C_AXI_DATA_WIDTH.
-- Updated else clause for simulation warnings w/ CR # 609695
narrow_burst_cnt_ld <= std_logic_vector (
to_unsigned (
(axi_byte_div_curr_awsize) - 1,
C_NARROW_BURST_CNT_LEN))
when (axi_byte_div_curr_awsize > 0)
else std_logic_vector (to_unsigned (0, C_NARROW_BURST_CNT_LEN));
---------------------------------------------------------------------------
-- Register narrow_burst_cnt_ld
REG_NAR_BRST_CNT_LD: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
narrow_burst_cnt_ld_reg <= (others => '0');
elsif (bram_addr_ld_en = '1') then
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld;
else
narrow_burst_cnt_ld_reg <= narrow_burst_cnt_ld_reg;
end if;
end if;
end process REG_NAR_BRST_CNT_LD;
---------------------------------------------------------------------------
end generate GEN_NARROW_CNT_LD;
----------------------------------------------------------------------------
-- Specify current AWBURST signal
-- Input address pipeline MUX
curr_awburst <= axi_awburst_pipe when (awaddr_pipe_sel = '1') else AXI_AWBURST;
----------------------------------------------------------------------------
-- Specify current AWBURST signal
-- Input address pipeline MUX
curr_awlen <= axi_awlen_pipe when (awaddr_pipe_sel = '1') else AXI_AWLEN;
-- Duplicate early decode of AWLEN value to use in wr_b2b_elgible logic
REG_CURR_AWLEN: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
curr_awlen_reg_1_or_2 <= '0';
elsif (bram_addr_ld_en = '1') then
-- Create merge to decode AWLEN of ONE or TWO
if (curr_awlen = AXI_AWLEN_ONE) or (curr_awlen = AXI_AWLEN_TWO) then
curr_awlen_reg_1_or_2 <= '1';
else
curr_awlen_reg_1_or_2 <= '0';
end if;
else
curr_awlen_reg_1_or_2 <= curr_awlen_reg_1_or_2;
end if;
end if;
end process REG_CURR_AWLEN;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_UA_NARROW
-- Purpose: Only instantiate logic for burst narrow WRAP operations when
-- AXI bus protocol is not set for AXI-LITE and narrow
-- burst operations are supported.
--
---------------------------------------------------------------------------
GEN_UA_NARROW: if (C_S_AXI_SUPPORTS_NARROW = 1) generate
begin
---------------------------------------------------------------------------
-- New logic to detect unaligned address on a narrow WRAP burst transaction.
-- If this condition is met, then the narrow burst counter will be
-- initially loaded with an offset value corresponding to the unalignment
-- in the ARADDR value.
-- Create a sub module for all logic to determine the narrow burst counter
-- offset value on unaligned WRAP burst operations.
-- Module generates the following signals:
--
-- => curr_ua_narrow_wrap, to indicate the current
-- operation is an unaligned narrow WRAP burst.
--
-- => curr_ua_narrow_incr, to load narrow burst counter
-- for unaligned INCR burst operations.
--
-- => ua_narrow_load, narrow counter load value.
-- Sized, (C_NARROW_BURST_CNT_LEN-1 downto 0)
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Instance: I_UA_NARROW
--
-- Description:
--
-- Creates a narrow burst count load value when an operation
-- is an unaligned narrow WRAP or INCR burst type. Used by
-- I_NARROW_CNT module.
--
-- Logic is customized for each C_AXI_DATA_WIDTH.
---------------------------------------------------------------------------
I_UA_NARROW : entity work.ua_narrow
generic map (
C_AXI_DATA_WIDTH => C_AXI_DATA_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_NARROW_BURST_CNT_LEN => C_NARROW_BURST_CNT_LEN
)
port map (
curr_wrap_burst => curr_wrap_burst , -- in
curr_incr_burst => curr_incr_burst , -- in
bram_addr_ld_en => bram_addr_ld_en , -- in
curr_axlen => curr_awlen , -- in
curr_axsize => curr_awsize , -- in
curr_axaddr_lsb => curr_awaddr_lsb , -- in
curr_ua_narrow_wrap => curr_ua_narrow_wrap , -- out
curr_ua_narrow_incr => curr_ua_narrow_incr , -- out
ua_narrow_load => ua_narrow_load -- out
);
-- Use in all C_AXI_DATA_WIDTH generate statements
-- Only probe least significant BRAM address bits
-- C_BRAM_ADDR_ADJUST_FACTOR offset down to 0.
curr_awaddr_lsb <= axi_awaddr_pipe (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0)
when (awaddr_pipe_sel = '1') else
AXI_AWADDR (C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0);
end generate GEN_UA_NARROW;
---------------------------------------------------------------------------
--
-- Generate: GEN_AW_SNG
-- Purpose: If single port BRAM configuration, set all AW flags from
-- logic generated in sng_port_arb module.
--
---------------------------------------------------------------------------
GEN_AW_SNG: if (C_SINGLE_PORT_BRAM = 1) generate
begin
aw_active <= Arb2AW_Active;
bram_addr_ld_en <= aw_active_re;
AW2Arb_Active_Clr <= aw_active_clr;
AW2Arb_Busy <= wr_busy_reg;
AW2Arb_BVALID_Cnt <= bvalid_cnt;
end generate GEN_AW_SNG;
-- Rising edge detect of aw_active
-- For single port configurations, aw_active = Arb2AW_Active.
-- For dual port configurations, aw_active generated in ADDR SM.
RE_AW_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
aw_active_d1 <= '0';
else
aw_active_d1 <= aw_active;
end if;
end if;
end process RE_AW_ACT;
aw_active_re <= '1' when (aw_active = '1' and aw_active_d1 = '0') else '0';
---------------------------------------------------------------------------
--
-- Generate: GEN_AW_DUAL
-- Purpose: Generate AW control state machine logic only when AXI4
-- controller is configured for dual port mode. In dual port
-- mode, wr_chnl has full access over AW & port A of BRAM.
--
---------------------------------------------------------------------------
GEN_AW_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
AW2Arb_Active_Clr <= '0'; -- Only used in single port case
AW2Arb_Busy <= '0'; -- Only used in single port case
AW2Arb_BVALID_Cnt <= (others => '0');
----------------------------------------------------------------------------
REG_LAST_DATA_ACK: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
last_data_ack_mod <= '0';
else
-- last_data_ack_mod <= AXI_WLAST;
-- CR # 609695
last_data_ack_mod <= AXI_WLAST and AXI_WVALID and axi_wready_int_mod;
end if;
end if;
end process REG_LAST_DATA_ACK;
----------------------------------------------------------------------------
---------------------------------------------------------------------------
-- WR ADDR State Machine
--
-- Description: Central processing unit for AXI write address
-- channel interface handling and handshaking.
--
-- Outputs: awaddr_pipe_ld Combinatorial
-- awaddr_pipe_sel
-- bram_addr_ld_en
--
--
--
-- WR_ADDR_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_ADDR_SM_REG_PROCESS: Registered process of the state machine.
---------------------------------------------------------------------------
WR_ADDR_SM_CMB_PROCESS: process ( AXI_AWVALID,
bvalid_cnt_max,
axi_awaddr_full,
aw_active,
wr_b2b_elgible,
last_data_ack_mod,
wr_addr_sm_cs )
begin
-- assign default values for state machine outputs
wr_addr_sm_ns <= wr_addr_sm_cs;
awaddr_pipe_ld_i <= '0';
bram_addr_ld_en_i <= '0';
aw_active_set_i <= '0';
case wr_addr_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for pending operation in address pipeline that may
-- be elgible for back-to-back performance to BRAM.
-- Prevent loading BRAM address counter if BID FIFO can not
-- store the AWID value. Check the BVALID counter.
if (wr_b2b_elgible = '1') and (last_data_ack_mod = '1') and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
wr_addr_sm_ns <= IDLE;
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
aw_active_set_i <= '1';
-- Ensure AWVALID is recognized.
-- Address pipeline may be loaded, but BRAM counter
-- can not be loaded if at max of BID FIFO.
elsif (AXI_AWVALID = '1') then
-- If address pipeline is full
-- AWReady output is negated
-- If write address logic is ready for new operation
-- Load BRAM address counter and set aw_active = '1'
-- If address pipeline is already full to start next operation
-- load address counter from pipeline.
-- Prevent loading BRAM address counter if BID FIFO can not
-- store the AWID value. Check the BVALID counter.
-- Remain in this state
if (aw_active = '0') and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
wr_addr_sm_ns <= IDLE;
-- Stay in this state to capture AWVALID if asserted
-- in next clock cycle.
bram_addr_ld_en_i <= '1';
aw_active_set_i <= '1';
-- Address counter is currently busy.
-- No check on BVALID counter for address pipeline load.
-- Only the BRAM address counter is checked for BID FIFO capacity.
else
-- Check if AWADDR pipeline is not full and can be loaded
if (axi_awaddr_full = '0') then
wr_addr_sm_ns <= LD_AWADDR;
awaddr_pipe_ld_i <= '1';
end if;
end if; -- aw_active
-- Pending operation in pipeline that is waiting
-- until current operation is complete (aw_active = '0')
elsif (axi_awaddr_full = '1') and (aw_active = '0') and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
wr_addr_sm_ns <= IDLE;
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
aw_active_set_i <= '1';
end if; -- AWVALID
---------------------------- LD_AWADDR State ---------------------------
when LD_AWADDR =>
wr_addr_sm_ns <= IDLE;
if (wr_b2b_elgible = '1') and (last_data_ack_mod = '1') and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
-- Load BRAM address counter from pipelined value
bram_addr_ld_en_i <= '1';
aw_active_set_i <= '1';
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
wr_addr_sm_ns <= IDLE;
--coverage on
end case;
end process WR_ADDR_SM_CMB_PROCESS;
---------------------------------------------------------------------------
-- CR # 582705
-- Ensure combinatorial SM output signals do not get set before
-- the end of the reset (and ARREAADY can be set).
bram_addr_ld_en <= bram_addr_ld_en_i and axi_aresetn_d2;
aw_active_set <= aw_active_set_i and axi_aresetn_d2;
awaddr_pipe_ld <= awaddr_pipe_ld_i and axi_aresetn_d2;
WR_ADDR_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
-- CR # 582705
-- Ensure that ar_active does not get asserted (from SM) before
-- the end of reset and the ARREADY flag is set.
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
wr_addr_sm_cs <= IDLE;
else
wr_addr_sm_cs <= wr_addr_sm_ns;
end if;
end if;
end process WR_ADDR_SM_REG_PROCESS;
---------------------------------------------------------------------------
-- Asserting awaddr_pipe_sel outside of SM logic
-- The BRAM address counter will get loaded with value in AWADDR pipeline
-- when data is stored in the AWADDR pipeline.
awaddr_pipe_sel <= '1' when (axi_awaddr_full = '1') else '0';
---------------------------------------------------------------------------
-- Register for aw_active
REG_AW_ACT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- CR # 582705
-- if (S_AXI_AResetn = C_RESET_ACTIVE) then
if (axi_aresetn_d2 = C_RESET_ACTIVE) then
aw_active <= '0';
elsif (aw_active_set = '1') then
aw_active <= '1';
elsif (aw_active_clr = '1') then
aw_active <= '0';
else
aw_active <= aw_active;
end if;
end if;
end process REG_AW_ACT;
---------------------------------------------------------------------------
end generate GEN_AW_DUAL;
---------------------------------------------------------------------------
-- *** AXI Write Data Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- AXI WrData Buffer/Register
---------------------------------------------------------------------------
GEN_WRDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate
begin
REG_WRDATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (wrdata_reg_ld = '1') then
bram_wrdata_int (i) <= AXI_WDATA (i);
else
bram_wrdata_int (i) <= bram_wrdata_int (i);
end if;
end if;
end process REG_WRDATA;
end generate GEN_WRDATA;
---------------------------------------------------------------------------
-- Generate: GEN_WR_NO_ECC
-- Purpose: Generate BRAM WrData and WE signals based on AXI_WRDATA
-- and AXI_WSTRBs when C_ECC is disabled.
---------------------------------------------------------------------------
GEN_WR_NO_ECC: if C_ECC = 0 generate
begin
---------------------------------------------------------------------------
-- AXI WSTRB Buffer/Register
-- Use AXI write data channel data strobe signals to generate BRAM WE.
---------------------------------------------------------------------------
REG_BRAM_WE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Ensure we don't clear WE when loading subsequent WSTRB value
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(clr_bram_we = '1' and bram_we_ld = '0') then
bram_we_int <= (others => '0');
elsif (bram_we_ld = '1') then
bram_we_int <= AXI_WSTRB;
else
bram_we_int <= bram_we_int;
end if;
end if;
end process REG_BRAM_WE;
----------------------------------------------------------------------------
-- New logic to detect if pending operation in AWADDR pipeline is
-- elgible for back-to-back no "bubble" performance. And BRAM address
-- counter can be loaded upon last BRAM address presented for the current
-- operation.
-- This condition exists when the AWADDR pipeline is full and the pending
-- operation is a burst >= length of two data beats.
-- And not a FIXED burst type (must be INCR or WRAP type).
--
-- Narrow bursts are be neglible
--
-- Add check to complete current single and burst of two data bursts
-- prior to loading BRAM counter
wr_b2b_elgible <= '1' when (axi_awaddr_full = '1') and
-- Replace comparator logic here with register signal (pre pipeline stage
-- on axi_awlen_pipe value
-- Use merge in decode of ONE or TWO
(axi_awlen_pipe_1_or_2 /= '1') and
(axi_awburst_pipe_fixed /= '1') and
-- Use merge in decode of ONE or TWO
(curr_awlen_reg_1_or_2 /= '1')
else '0';
----------------------------------------------------------------------------
end generate GEN_WR_NO_ECC;
---------------------------------------------------------------------------
-- Generate: GEN_WR_ECC
-- Purpose: Generate BRAM WrData and WE signals based on AXI_WRDATA
-- and AXI_WSTRBs when C_ECC is enabled.
---------------------------------------------------------------------------
GEN_WR_ECC: if C_ECC = 1 generate
begin
wr_b2b_elgible <= '0';
---------------------------------------------------------------------------
-- AXI WSTRB Buffer/Register
-- Use AXI write data channel data strobe signals to generate BRAM WE.
---------------------------------------------------------------------------
REG_BRAM_WE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Ensure we don't clear WE when loading subsequent WSTRB value
if (S_AXI_AResetn = C_RESET_ACTIVE) or
(reset_bram_we = '1') then
bram_we_int <= (others => '0');
elsif (set_bram_we = '1') then
bram_we_int <= (others => '1');
else
bram_we_int <= bram_we_int;
end if;
end if;
end process REG_BRAM_WE;
end generate GEN_WR_ECC;
-----------------------------------------------------------------------
-- v1.03a
-----------------------------------------------------------------------
--
-- Implement WREADY to be a registered output. Used by all configurations.
-- This will disable the back-to-back streamlined WDATA
-- for write operations to BRAM.
--
-----------------------------------------------------------------------
REG_WREADY: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_wready_int_mod <= '0';
-- Keep AXI WREADY asserted unless write data register is full
-- Use combinatorial signal from SM.
elsif (axi_wdata_full_cmb = '1') then
axi_wready_int_mod <= '0';
else
axi_wready_int_mod <= '1';
end if;
end if;
end process REG_WREADY;
---------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Generate: GEN_WDATA_SM_ECC
-- Purpose: Create seperate SM for ECC read-modify-write logic.
-- Only used in single port BRAM mode. So, no address
-- pipelining. Must use aw_active from arbitration logic
-- to determine start of write to BRAM.
--
----------------------------------------------------------------------------
-- Test using same write data SM for single or dual port configuration.
-- The difference is the source of aw_active. In a single port configuration,
-- the aw_active is coming from the arbiter SM. In a dual port configuration,
-- the aw_active is coming from the write address SM in this module.
GEN_WDATA_SM_ECC: if C_ECC = 1 generate
begin
-- Unused in this SM configuration
bram_we_ld <= '0';
bram_addr_rst_cmb <= '0';
-- Output only used by ECC register module.
Active_Wr <= active_wr_reg;
---------------------------------------------------------------------------
--
-- WR DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking when ECC is enabled. SM will handle
-- each transaction as a read-modify-write to ensure
-- the correct ECC bits are stored in BRAM.
--
-- Dedicated to single port BRAM interface. Transaction
-- is not initiated until valid AWADDR is arbitration,
-- ie. aw_active will be asserted. SM can do early reads
-- while waiting for WVALID to be asserted.
--
-- Valid AWADDR recieve indicator comes from arbitration
-- logic (aw_active will be asserted).
--
-- Outputs: Name Type
--
-- aw_active_clr Not Registered
-- axi_wdata_full_reg Registered
-- wrdata_reg_ld Not Registered
-- bvalid_cnt_inc Not Registered
-- bram_addr_inc Not Registered
-- bram_en_int Registered
-- reset_bram_we Not Registered
-- set_bram_we Not Registered
--
--
-- WR_DATA_ECC_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_DATA_ECC_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
WR_DATA_ECC_SM_CMB_PROCESS: process ( AXI_WVALID,
AXI_WLAST,
aw_active,
wr_busy_reg,
axi_wdata_full_reg,
axi_wr_burst,
AXI_BREADY,
active_wr_reg,
wr_data_ecc_sm_cs )
begin
-- Assign default values for state machine outputs
wr_data_ecc_sm_ns <= wr_data_ecc_sm_cs;
aw_active_clr <= '0';
wr_busy_cmb <= wr_busy_reg;
bvalid_cnt_inc <= '0';
wrdata_reg_ld <= '0';
reset_bram_we <= '0';
set_bram_we_cmb <= '0';
bram_en_cmb <= '0';
bram_addr_inc <= '0';
axi_wdata_full_cmb <= axi_wdata_full_reg;
axi_wr_burst_cmb <= axi_wr_burst;
active_wr_cmb <= active_wr_reg;
case wr_data_ecc_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Prior to AWVALID assertion, WVALID may be asserted
-- and data accepted into WDATA register.
-- Catch this condition and ensure the register full flag is set.
-- Check that data pipeline is not already full.
if (AXI_WVALID = '1') and (axi_wdata_full_reg = '0') then
wrdata_reg_ld <= '1'; -- Load write data register
axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data
-- w/ CR # 609695
--
-- -- Set flag to check if single or not
-- if (AXI_WLAST = '1') then
-- axi_wr_burst_cmb <= '0';
-- else
-- axi_wr_burst_cmb <= '1';
-- end if;
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
end if;
-- Check if AWVALID is asserted & wins arbitration
if (aw_active = '1') then
active_wr_cmb <= '1'; -- Set flag that RMW SM is active
-- Controls mux select for BRAM and ECC register module
-- (Set to '1' wr_chnl or '0' for rd_chnl control)
bram_en_cmb <= '1'; -- Initiate BRAM read transfer
reset_bram_we <= '1'; -- Disable Port A write enables
-- Will proceed to read-modify-write if we get a
-- valid write address early (before WVALID)
wr_data_ecc_sm_ns <= RMW_RD_DATA;
end if; -- WVALID
------------------------- RMW_RD_DATA State -------------------------
when RMW_RD_DATA =>
-- Check if data to write is available in data pipeline
if (axi_wdata_full_reg = '1') then
wr_data_ecc_sm_ns <= RMW_CHK_DATA;
-- Else may have address, but not yet data from W channel
elsif (AXI_WVALID = '1') then
-- Ensure that WDATA pipeline is marked as full, so WREADY negates
axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data
wrdata_reg_ld <= '1'; -- Load write data register
-- w/ CR # 609695
--
-- -- Set flag to check if single or not
-- if (AXI_WLAST = '1') then
-- axi_wr_burst_cmb <= '0';
-- else
-- axi_wr_burst_cmb <= '1';
-- end if;
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
wr_data_ecc_sm_ns <= RMW_CHK_DATA;
else
-- Hold here and wait for write data
wr_data_ecc_sm_ns <= RMW_RD_DATA;
end if;
------------------------- RMW_CHK_DATA State -------------------------
when RMW_CHK_DATA =>
-- New state here to add register stage on calculating
-- checkbits for read data and then muxing/creating new
-- checkbits for write cycle.
-- Go immediately to MODIFY stage in RMW sequence
wr_data_ecc_sm_ns <= RMW_MOD_DATA;
set_bram_we_cmb <= '1'; -- Enable all WEs to BRAM
------------------------- RMW_MOD_DATA State -------------------------
when RMW_MOD_DATA =>
-- Modify clock cycle in RMW sequence
-- Only reach this state after a read AND we have data
-- in the write data pipeline to modify and subsequently write to BRAM.
bram_en_cmb <= '1'; -- Initiate BRAM write transfer
-- Can clear WDATA pipeline full condition flag
if (axi_wr_burst = '1') then
axi_wdata_full_cmb <= '0';
end if;
wr_data_ecc_sm_ns <= RMW_WR_DATA; -- Go to write data to BRAM
------------------------- RMW_WR_DATA State -------------------------
when RMW_WR_DATA =>
-- Check if last data beat in a burst (or the write is a single)
if (axi_wr_burst = '0') then
-- Can clear WDATA pipeline full condition flag now that
-- write data has gone out to BRAM (for single data transfers)
axi_wdata_full_cmb <= '0';
bvalid_cnt_inc <= '1'; -- Set flag to assert BVALID and increment counter
wr_data_ecc_sm_ns <= IDLE; -- Go back to IDLE, BVALID assertion is seperate
wr_busy_cmb <= '0'; -- Clear flag to arbiter
active_wr_cmb <= '0'; -- Clear flag (wr_chnl is done accessing BRAM)
-- Used for single port arbitration SM
axi_wr_burst_cmb <= '0';
aw_active_clr <= '1'; -- Clear aw_active flag
reset_bram_we <= '1'; -- Disable Port A write enables
else
-- Continue with read-modify-write sequence for write burst
-- If next data beat is available on AXI, capture the data
if (AXI_WVALID = '1') then
wrdata_reg_ld <= '1'; -- Load write data register
axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data
-- w/ CR # 609695
--
-- -- Set flag to check if single or not
-- if (AXI_WLAST = '1') then
-- axi_wr_burst_cmb <= '0';
-- else
-- axi_wr_burst_cmb <= '1';
-- end if;
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
end if;
-- After write cycle (in RMW) => Increment BRAM address counter
bram_addr_inc <= '1';
bram_en_cmb <= '1'; -- Initiate BRAM read transfer
reset_bram_we <= '1'; -- Disable Port A write enables
-- Will proceed to read-modify-write if we get a
-- valid write address early (before WVALID)
wr_data_ecc_sm_ns <= RMW_RD_DATA;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
wr_data_ecc_sm_ns <= IDLE;
--coverage on
end case;
end process WR_DATA_ECC_SM_CMB_PROCESS;
---------------------------------------------------------------------------
WR_DATA_ECC_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wr_data_ecc_sm_cs <= IDLE;
bram_en_int <= '0';
axi_wdata_full_reg <= '0';
wr_busy_reg <= '0';
active_wr_reg <= '0';
set_bram_we <= '0';
else
wr_data_ecc_sm_cs <= wr_data_ecc_sm_ns;
bram_en_int <= bram_en_cmb;
axi_wdata_full_reg <= axi_wdata_full_cmb;
wr_busy_reg <= wr_busy_cmb;
active_wr_reg <= active_wr_cmb;
set_bram_we <= set_bram_we_cmb;
end if;
end if;
end process WR_DATA_ECC_SM_REG_PROCESS;
---------------------------------------------------------------------------
end generate GEN_WDATA_SM_ECC;
-- v1.03a
----------------------------------------------------------------------------
--
-- Generate: GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY
-- Purpose: Create seperate SM use case of no ECC (no read-modify-write)
-- and single port BRAM configuration (no back to back operations
-- are supported). Must wait for aw_active from arbiter to indicate
-- control on BRAM interface.
--
----------------------------------------------------------------------------
GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY: if C_ECC = 0 and
C_SINGLE_PORT_BRAM = 1
generate
begin
-- Unused in this SM configuration
wr_busy_cmb <= '0'; -- Unused
wr_busy_reg <= '0'; -- Unused
active_wr_cmb <= '0'; -- Unused
active_wr_reg <= '0'; -- Unused
Active_Wr <= '0'; -- Unused
---------------------------------------------------------------------------
--
-- WR DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking.
--
-- Outputs: Name Type
-- aw_active_clr Not Registered
-- bvalid_cnt_inc Not Registered
-- wrdata_reg_ld Not Registered
-- bram_we_ld Not Registered
-- bram_en_int Registered
-- clr_bram_we Registered
-- bram_addr_inc Not Registered
-- wrdata_reg_ld Not Registered
--
-- Note:
--
-- On "narrow burst transfers" BRAM address only
-- gets incremented at BRAM data width.
-- On WRAP bursts, the BRAM address must wrap when
-- the max is reached
--
--
--
-- WR_DATA_SNG_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_DATA_SNG_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
WR_DATA_SNG_SM_CMB_PROCESS: process ( AXI_WVALID,
AXI_WLAST,
aw_active,
axi_wr_burst,
axi_wdata_full_reg,
wr_data_sng_sm_cs )
begin
-- assign default values for state machine outputs
wr_data_sng_sm_ns <= wr_data_sng_sm_cs;
aw_active_clr <= '0';
bvalid_cnt_inc <= '0';
axi_wr_burst_cmb <= axi_wr_burst;
wrdata_reg_ld <= '0';
bram_we_ld <= '0';
bram_en_cmb <= '0';
clr_bram_we_cmb <= '0';
bram_addr_inc <= '0';
bram_addr_rst_cmb <= '0';
axi_wdata_full_cmb <= axi_wdata_full_reg;
case wr_data_sng_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Prior to AWVALID assertion, WVALID may be asserted
-- and data accepted into WDATA register.
-- Catch this condition and ensure the register full flag is set.
-- Check that data pipeline is not already full.
--
-- Modify WE pipeline and mux to BRAM
-- as well. Since WE may be asserted early (when pipeline is loaded),
-- but not yet ready to go out to BRAM.
--
-- Only first data beat will be accepted early into data pipeline.
-- All remaining beats in a burst will only be accepted upon WVALID.
if (AXI_WVALID = '1') and (axi_wdata_full_reg = '0') then
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
end if;
-- Wait for WVALID and aw_active to initiate write transfer
if (aw_active = '1' and
(AXI_WVALID = '1' or axi_wdata_full_reg = '1')) then
-- If operation is a single, then it goes directly out to BRAM
-- WDATA register is never marked as FULL in this case.
-- If data pipeline is not previously loaded, do so now.
if (axi_wdata_full_reg = '0') then
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
end if;
-- Initiate BRAM write transfer
bram_en_cmb <= '1';
-- If data goes out to BRAM, mark data register as EMPTY
axi_wdata_full_cmb <= '0';
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
-- Check for singles, by checking WLAST assertion w/ WVALID
-- Only if write data pipeline is not yet filled, check WLAST
-- Otherwise, if pipeline is already full, use registered value of WLAST
-- to check for single vs. burst write operation.
if (AXI_WLAST = '1' and axi_wdata_full_reg = '0') or
(axi_wdata_full_reg = '1' and axi_wr_burst = '0') then
-- Single data write
wr_data_sng_sm_ns <= SNG_WR_DATA;
-- Set flag to assert BVALID and increment counter
bvalid_cnt_inc <= '1';
-- BRAM WE only asserted for single clock cycle
clr_bram_we_cmb <= '1';
else
-- Burst data write
wr_data_sng_sm_ns <= BRST_WR_DATA;
end if; -- WLAST
end if;
------------------------- SNG_WR_DATA State -------------------------
when SNG_WR_DATA =>
-- If WREADY is registered, then BVALID generation is seperate
-- from write data flow.
-- Go back to IDLE automatically
-- BVALID will get asserted seperately from W channel
wr_data_sng_sm_ns <= IDLE;
bram_addr_rst_cmb <= '1';
aw_active_clr <= '1';
-- Check for capture of next data beat (WREADY will be asserted)
if (AXI_WVALID = '1') then
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
axi_wdata_full_cmb <= '1'; -- Hold off accepting any new write data
axi_wr_burst_cmb <= not (AXI_WLAST); -- Set flag to check if single or not
else
axi_wdata_full_cmb <= '0'; -- If no next data, ensure data register is flagged EMPTY.
end if;
------------------------- BRST_WR_DATA State -------------------------
when BRST_WR_DATA =>
-- Reach this state at the 2nd data beat of a burst
-- AWADDR is already accepted
-- Continue to accept data from AXI write channel
-- and wait for assertion of WLAST
-- Check that WVALID remains asserted for burst
-- If negated, indicates throttling from AXI master
if (AXI_WVALID = '1') then
-- If WVALID is asserted for the 2nd and remaining
-- data beats of the transfer
-- Continue w/ BRAM write enable assertion & advance
-- write data register
-- Write data goes directly out to BRAM.
-- WDATA register is never marked as FULL in this case.
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
-- Initiate BRAM write transfer
bram_en_cmb <= '1';
-- Increment BRAM address counter
bram_addr_inc <= '1';
-- Check for last data beat in burst transfer
if (AXI_WLAST = '1') then
-- Last/single data write
wr_data_sng_sm_ns <= SNG_WR_DATA;
-- Set flag to assert BVALID and increment counter
bvalid_cnt_inc <= '1';
-- BRAM WE only asserted for single clock cycle
clr_bram_we_cmb <= '1';
end if; -- WLAST
-- Throttling
-- Suspend BRAM write & halt write data & WE register load
else
-- Negate write data register load
wrdata_reg_ld <= '0';
-- Negate WE register load
bram_we_ld <= '0';
-- Negate write to BRAM
bram_en_cmb <= '0';
-- Do not increment BRAM address counter
bram_addr_inc <= '0';
end if; -- WVALID
--coverage off
------------------------------ Default ----------------------------
when others =>
wr_data_sng_sm_ns <= IDLE;
--coverage on
end case;
end process WR_DATA_SNG_SM_CMB_PROCESS;
---------------------------------------------------------------------------
WR_DATA_SNG_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wr_data_sng_sm_cs <= IDLE;
bram_en_int <= '0';
clr_bram_we <= '0';
axi_wdata_full_reg <= '0';
else
wr_data_sng_sm_cs <= wr_data_sng_sm_ns;
bram_en_int <= bram_en_cmb;
clr_bram_we <= clr_bram_we_cmb;
axi_wdata_full_reg <= axi_wdata_full_cmb;
end if;
end if;
end process WR_DATA_SNG_SM_REG_PROCESS;
---------------------------------------------------------------------------
end generate GEN_WDATA_SM_NO_ECC_SNG_REG_WREADY;
----------------------------------------------------------------------------
--
-- Generate: GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY
--
-- Purpose: Create seperate SM for new logic to register out WREADY
-- signal. Behavior for back-to-back operations is different
-- than with combinatorial genearted WREADY output to AXI.
--
-- New SM design supports seperate WREADY and BVALID responses.
--
-- New logic here for axi_bvalid_int output register based
-- on counter design of BVALID.
--
----------------------------------------------------------------------------
GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY: if C_ECC = 0 and
C_SINGLE_PORT_BRAM = 0
generate
begin
-- Unused in this SM configuration
active_wr_cmb <= '0'; -- Unused
active_wr_reg <= '0'; -- Unused
Active_Wr <= '0'; -- Unused
wr_busy_cmb <= '0'; -- Unused
wr_busy_reg <= '0'; -- Unused
---------------------------------------------------------------------------
--
-- WR DATA State Machine
--
-- Description: Central processing unit for AXI write data
-- channel interface handling and AXI write data response
-- handshaking.
--
-- Outputs: Name Type
-- bvalid_cnt_inc Not Registered
-- aw_active_clr Not Registered
-- delay_aw_active_clr Registered
-- axi_wdata_full_reg Registered
-- bram_en_int Registered
-- wrdata_reg_ld Not Registered
-- bram_we_ld Not Registered
-- clr_bram_we Registered
-- bram_addr_inc
--
-- Note:
--
-- On "narrow burst transfers" BRAM address only
-- gets incremented at BRAM data width.
-- On WRAP bursts, the BRAM address must wrap when
-- the max is reached
--
-- Add check on BVALID counter max. Check with
-- AWVALID assertions (since AWID is connected to AWVALID).
--
--
-- WR_DATA_SM_CMB_PROCESS: Combinational process to determine next state.
-- WR_DATA_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
WR_DATA_SM_CMB_PROCESS: process ( AXI_WVALID,
AXI_WLAST,
bvalid_cnt_max,
bvalid_cnt_amax,
aw_active,
delay_aw_active_clr,
AXI_AWVALID,
axi_awready_int,
bram_addr_ld_en,
axi_awaddr_full,
awaddr_pipe_sel,
axi_wr_burst,
axi_wdata_full_reg,
wr_b2b_elgible,
wr_data_sm_cs )
begin
-- assign default values for state machine outputs
wr_data_sm_ns <= wr_data_sm_cs;
aw_active_clr <= '0';
delay_aw_active_clr_cmb <= delay_aw_active_clr;
bvalid_cnt_inc <= '0';
axi_wr_burst_cmb <= axi_wr_burst;
wrdata_reg_ld <= '0';
bram_we_ld <= '0';
bram_en_cmb <= '0';
clr_bram_we_cmb <= '0';
bram_addr_inc <= '0';
bram_addr_rst_cmb <= '0';
axi_wdata_full_cmb <= axi_wdata_full_reg;
case wr_data_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check valid write data on AXI write data channel
if (AXI_WVALID = '1') then
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
-- Add condition to check for simultaneous assertion
-- of AWVALID and AWREADY
if ((aw_active = '1') or (AXI_AWVALID = '1' and axi_awready_int = '1')) and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
-- Initiate BRAM write transfer
bram_en_cmb <= '1';
-- Check for singles, by checking WLAST assertion w/ WVALID
if (AXI_WLAST = '1') then
-- Single data write
wr_data_sm_ns <= SNG_WR_DATA;
-- Set flag to assert BVALID and increment counter
bvalid_cnt_inc <= '1';
-- Set flag to delay clear of AW active flag
delay_aw_active_clr_cmb <= '1';
-- BRAM WE only asserted for single clock cycle
clr_bram_we_cmb <= '1';
axi_wr_burst_cmb <= '0';
else
-- Burst data write
wr_data_sm_ns <= BRST_WR_DATA;
axi_wr_burst_cmb <= '1';
end if; -- WLAST
else
-- AWADDR not yet received
-- Go to wait for write address
wr_data_sm_ns <= W8_AWADDR;
-- Set flag that AXI write data pipe is full
-- and can not accept any more data beats
-- WREADY on AXI will negate in this condition.
axi_wdata_full_cmb <= '1';
-- Set flag for single/burst write operation
-- when AWADDR is not yet received
if (AXI_WLAST = '1') then
axi_wr_burst_cmb <= '0';
else
axi_wr_burst_cmb <= '1';
end if; -- WLAST
end if; -- aw_active
end if; -- WVALID
------------------------- W8_AWADDR State -------------------------
when W8_AWADDR =>
-- As we transition into this state, the write data pipeline
-- is already filled. axi_wdata_full_reg should be = '1'.
-- Disable any additional loads into write data register
-- Default value in SM is applied.
-- Wait for write address to be acknowledged
if (((aw_active = '1') or (AXI_AWVALID = '1' and axi_awready_int = '1')) or
-- Detect load of BRAM address counter from value stored in pipeline.
-- No need to wait until aw_active is asserted or address is captured from AXI bus.
-- As BRAM address is loaded from pipe and ready to be presented to BRAM.
-- Assert BRAM WE.
(bram_addr_ld_en = '1' and axi_awaddr_full = '1' and awaddr_pipe_sel = '1')) and
-- Ensure the BVALID counter does not roll over (max = 8 ID values)
(bvalid_cnt_max = '0') then
-- Initiate BRAM write transfer
bram_en_cmb <= '1';
-- Negate write data full condition
axi_wdata_full_cmb <= '0';
-- Check if single or burst operation
if (axi_wr_burst = '1') then
wr_data_sm_ns <= BRST_WR_DATA;
else
wr_data_sm_ns <= SNG_WR_DATA;
-- BRAM WE only asserted for single clock cycle
clr_bram_we_cmb <= '1';
-- Set flag to assert BVALID and increment counter
bvalid_cnt_inc <= '1';
delay_aw_active_clr_cmb <= '1';
end if;
else
-- Set flag that AXI write data pipe is full
-- and can not accept any more data beats
-- WREADY on AXI will negate in this condition.
axi_wdata_full_cmb <= '1';
end if;
------------------------- SNG_WR_DATA State -------------------------
when SNG_WR_DATA =>
-- No need to check for BVALID assertion here.
-- Move here under if clause on write response channel
-- acknowledging completion of write data.
-- If aw_active was not cleared prior to this state, then
-- clear the flag now.
if (delay_aw_active_clr = '1') then
delay_aw_active_clr_cmb <= '0';
aw_active_clr <= '1';
end if;
-- Add check here if while writing single data beat to BRAM,
-- a new AXI data beat is received (prior to the AWVALID assertion).
-- Ensure here that full flag is asserted for data pipeline state.
-- Check valid write data on AXI write data channel
if (AXI_WVALID = '1') then
-- Load write data register
wrdata_reg_ld <= '1';
-- Must also load WE register
bram_we_ld <= '1';
-- Set flag that AXI write data pipe is full
-- and can not accept any more data beats
-- WREADY on AXI will negate in this condition.
-- Ensure that axi_wdata_full_reg is asserted
-- to prevent early captures on next data burst (or single data
-- transfer)
-- This ensures that the data beats do not get skipped.
axi_wdata_full_cmb <= '1';
-- AWADDR not yet received
-- Go to wait for write address
wr_data_sm_ns <= W8_AWADDR;
-- Accept no more new write data after this first data beat
-- Pipeline is already full in this state. No need to assert
-- no_wdata_accept flag to '1'.
-- Set flag for single/burst write operation
-- when AWADDR is not yet received
if (AXI_WLAST = '1') then
axi_wr_burst_cmb <= '0';
else
axi_wr_burst_cmb <= '1';
end if; -- WLAST
else
-- No subsequent pending operation
-- Return to IDLE
wr_data_sm_ns <= IDLE;
bram_addr_rst_cmb <= '1';
end if;
------------------------- BRST_WR_DATA State -------------------------
when BRST_WR_DATA =>
-- Reach this state at the 2nd data beat of a burst
-- AWADDR is already accepted
-- Continue to accept data from AXI write channel
-- and wait for assertion of WLAST
-- Check that WVALID remains asserted for burst
-- If negated, indicates throttling from AXI master
if (AXI_WVALID = '1') then
-- If WVALID is asserted for the 2nd and remaining
-- data beats of the transfer
-- Continue w/ BRAM write enable assertion & advance
-- write data register
wrdata_reg_ld <= '1'; -- Load write data register
bram_we_ld <= '1'; -- Load WE register
bram_en_cmb <= '1'; -- Initiate BRAM write transfer
bram_addr_inc <= '1'; -- Increment BRAM address counter
-- Check for last data beat in burst transfer
if (AXI_WLAST = '1') then
-- Set flag to assert BVALID and increment counter
bvalid_cnt_inc <= '1';
-- The elgible signal will not be asserted for a subsequent
-- single data beat operation. Next operation is a burst.
-- And the AWADDR is loaded in the address pipeline.
-- Only if BVALID counter can handle next transfer,
-- proceed with back-to-back. Otherwise, go to IDLE
-- (after last data write).
if (wr_b2b_elgible = '1' and bvalid_cnt_amax = '0') then
-- Go to next operation and handle as a
-- back-to-back burst. No empty clock cycles.
-- Go to handle new burst for back to back condition
wr_data_sm_ns <= B2B_W8_WR_DATA;
axi_wr_burst_cmb <= '1';
-- No pending subsequent transfer (burst > 2 data beats)
-- to process
else
-- Last/single data write
wr_data_sm_ns <= SNG_WR_DATA;
-- Be sure to clear aw_active flag at end of write burst
-- But delay when the flag is cleared
delay_aw_active_clr_cmb <= '1';
end if;
end if; -- WLAST
-- Throttling
-- Suspend BRAM write & halt write data & WE register load
else
wrdata_reg_ld <= '0'; -- Negate write data register load
bram_we_ld <= '0'; -- Negate WE register load
bram_en_cmb <= '0'; -- Negate write to BRAM
bram_addr_inc <= '0'; -- Do not increment BRAM address counter
end if; -- WVALID
------------------------- B2B_W8_WR_DATA --------------------------
when B2B_W8_WR_DATA =>
-- Reach this state upon a back-to-back condition
-- when BVALID/BREADY handshake is received,
-- but WVALID is not yet asserted for subsequent transfer.
-- Check valid write data on AXI write data channel
if (AXI_WVALID = '1') then
-- Load write data register
wrdata_reg_ld <= '1';
-- Load WE register
bram_we_ld <= '1';
-- Initiate BRAM write transfer
bram_en_cmb <= '1';
-- Burst data write
wr_data_sm_ns <= BRST_WR_DATA;
axi_wr_burst_cmb <= '1';
-- Make modification to last_data_ack_mod signal
-- so that it is asserted when this state is reached
-- and the BRAM address counter gets loaded.
-- WVALID not yet asserted
else
wrdata_reg_ld <= '0'; -- Negate write data register load
bram_we_ld <= '0'; -- Negate WE register load
bram_en_cmb <= '0'; -- Negate write to BRAM
bram_addr_inc <= '0'; -- Do not increment BRAM address counter
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
wr_data_sm_ns <= IDLE;
--coverage on
end case;
end process WR_DATA_SM_CMB_PROCESS;
---------------------------------------------------------------------------
WR_DATA_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wr_data_sm_cs <= IDLE;
bram_en_int <= '0';
clr_bram_we <= '0';
delay_aw_active_clr <= '0';
axi_wdata_full_reg <= '0';
else
wr_data_sm_cs <= wr_data_sm_ns;
bram_en_int <= bram_en_cmb;
clr_bram_we <= clr_bram_we_cmb;
delay_aw_active_clr <= delay_aw_active_clr_cmb;
axi_wdata_full_reg <= axi_wdata_full_cmb;
end if;
end if;
end process WR_DATA_SM_REG_PROCESS;
---------------------------------------------------------------------------
end generate GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY;
---------------------------------------------------------------------------
WR_BURST_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_wr_burst <= '0';
else
axi_wr_burst <= axi_wr_burst_cmb;
end if;
end if;
end process WR_BURST_REG_PROCESS;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Write Response Channel Interface ***
---------------------------------------------------------------------------
-- v1.03a
---------------------------------------------------------------------------
--
--
-- New FIFO storage for BID, so AWID can be stored in
-- a FIFO and B response is seperated from W response.
--
-- Use registered WREADY & BID FIFO in single port configuration.
--
---------------------------------------------------------------------------
-- Instantiate FIFO to store BID values to be asserted back on B channel.
-- Only 8 entries deep, BVALID counter only allows W channel to be 8 ahead of
-- B channel.
--
-- If AWID is a single bit wide, sythesis optimizes the module, srl_fifo,
-- to a single SRL16E library module.
BID_FIFO: entity work.srl_fifo
generic map (
C_DATA_BITS => C_AXI_ID_WIDTH,
C_DEPTH => 8
)
port map (
Clk => S_AXI_AClk,
Reset => bid_fifo_rst,
FIFO_Write => bid_fifo_ld_en,
Data_In => bid_fifo_ld,
FIFO_Read => bid_fifo_rd_en,
Data_Out => bid_fifo_rd,
FIFO_Full => open,
Data_Exists => bid_fifo_not_empty,
Addr => open
);
bid_fifo_rst <= not (S_AXI_AResetn);
bid_fifo_ld_en <= bram_addr_ld_en;
bid_fifo_ld <= AXI_AWID when (awaddr_pipe_sel = '0') else axi_awid_pipe;
-- Read from FIFO when BVALID is to be asserted on bus, or in a back-to-back assertion
-- when a BID value is available in the FIFO.
bid_fifo_rd_en <= bid_fifo_not_empty and -- Only read if data is available.
((bid_gets_fifo_load_d1) or -- a) Do the FIFO read in the clock cycle
-- following the BID value directly
-- aserted on the B channel (from AWID or pipeline).
(first_fifo_bid) or -- b) Read from FIFO when BID is previously stored
-- but BVALID is not yet asserted on AXI.
(bvalid_cnt_dec)); -- c) Or read when next BID value is to be updated
-- on B channel (and exists waiting in FIFO).
-- 1) Special case (1st load in FIFO) (and single clock cycle turnaround needed on BID, from AWID).
-- If loading the FIFO and BVALID is to be asserted in the next clock cycle
-- Then capture this condition to read from FIFO in the subsequent clock cycle
-- (and clear the BID value stored in the FIFO).
bid_gets_fifo_load <= '1' when (bid_fifo_ld_en = '1') and
(first_fifo_bid = '1' or b2b_fifo_bid = '1') else '0';
first_fifo_bid <= '1' when ((bvalid_cnt_inc = '1') and (bvalid_cnt_non_zero = '0')) else '0';
-- 2) An additional special case.
-- When write data register is loaded for single (bvalid_cnt = "001", due to WLAST/WVALID)
-- But, AWID not yet received (FIFO is still empty).
-- If BID FIFO is still empty with the BVALID counter decrement, but simultaneously
-- is increment (same condition as first_fifo_bid).
b2b_fifo_bid <= '1' when (bvalid_cnt_inc = '1' and bvalid_cnt_dec = '1' and
bvalid_cnt = "001" and bid_fifo_not_empty = '0') else '0';
-- Output BID register to B AXI channel
REG_BID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_bid_int <= (others => '0');
-- If loading the FIFO and BVALID is to be asserted in the next clock cycle
-- Then output the AWID or pipelined value (the same BID that gets loaded into FIFO).
elsif (bid_gets_fifo_load = '1') then
axi_bid_int <= bid_fifo_ld;
-- If new value read from FIFO then ensure that value is updated on AXI.
elsif (bid_fifo_rd_en = '1') then
axi_bid_int <= bid_fifo_rd;
else
axi_bid_int <= axi_bid_int;
end if;
end if;
end process REG_BID;
-- Capture condition of BID output updated while the FIFO is also
-- getting updated. Read FIFO in the subsequent clock cycle to
-- clear the value stored in the FIFO.
REG_BID_LD: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bid_gets_fifo_load_d1 <= '0';
else
bid_gets_fifo_load_d1 <= bid_gets_fifo_load;
end if;
end if;
end process REG_BID_LD;
---------------------------------------------------------------------------
-- AXI_BRESP Output Register
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_BRESP
-- Purpose: Generate BRESP output signal when ECC is disabled.
-- Only allowable output is RESP_OKAY.
---------------------------------------------------------------------------
GEN_BRESP: if C_ECC = 0 generate
begin
REG_BRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_bresp_int <= (others => '0');
-- elsif (AXI_WLAST = '1') then
-- CR # 609695
elsif ((AXI_WLAST and AXI_WVALID and axi_wready_int_mod) = '1') then
-- AXI BRAM only supports OK response for normal operations
-- Exclusive operations not yet supported
axi_bresp_int <= RESP_OKAY;
else
axi_bresp_int <= axi_bresp_int;
end if;
end if;
end process REG_BRESP;
end generate GEN_BRESP;
---------------------------------------------------------------------------
-- Generate: GEN_BRESP_ECC
-- Purpose: Generate BRESP output signal when ECC is enabled
-- If no ECC error condition is detected during the RMW
-- sequence, then output will be RESP_OKAY. When an
-- uncorrectable error is detected, the output will RESP_SLVERR.
---------------------------------------------------------------------------
GEN_BRESP_ECC: if C_ECC = 1 generate
signal UE_Q_reg : std_logic := '0';
begin
REG_BRESP: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
axi_bresp_int <= (others => '0');
elsif (bvalid_cnt_inc_d1 = '1') then
--coverage off
-- Exclusive operations not yet supported
-- If no ECC errors occur, respond with OK
if (UE_Q = '1') or (UE_Q_reg = '1') then
axi_bresp_int <= RESP_SLVERR;
--coverage on
else
axi_bresp_int <= RESP_OKAY;
end if;
else
axi_bresp_int <= axi_bresp_int;
end if;
end if;
end process REG_BRESP;
-- Check if any error conditions occured during the write operation.
-- Capture condition for each write transfer.
REG_UE: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
-- Clear at end of current write (and ensure the flag is cleared
-- at the beginning of a write transfer)
if (S_AXI_AResetn = C_RESET_ACTIVE) or (aw_active_re = '1') or
(AXI_BREADY = '1' and axi_bvalid_int = '1') then
UE_Q_reg <= '0';
--coverage off
elsif (UE_Q = '1') then
UE_Q_reg <= '1';
--coverage on
else
UE_Q_reg <= UE_Q_reg;
end if;
end if;
end process REG_UE;
end generate GEN_BRESP_ECC;
-- v1.03a
---------------------------------------------------------------------------
-- Instantiate BVALID counter outside of specific SM generate block.
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- BVALID counter to track the # of required BVALID/BREADY handshakes
-- needed to occur on the AXI interface. Based on early and seperate
-- AWVALID/AWREADY and WVALID/WREADY handshake exchanges.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt <= (others => '0');
-- Ensure we only increment counter wyhen BREADY is not asserted
elsif (bvalid_cnt_inc = '1') and (bvalid_cnt_dec = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) + 1);
-- Ensure that we only decrement when SM is not incrementing
elsif (bvalid_cnt_dec = '1') and (bvalid_cnt_inc = '0') then
bvalid_cnt <= std_logic_vector (unsigned (bvalid_cnt (2 downto 0)) - 1);
else
bvalid_cnt <= bvalid_cnt;
end if;
end if;
end process REG_BVALID_CNT;
bvalid_cnt_dec <= '1' when (AXI_BREADY = '1' and
axi_bvalid_int = '1' and
bvalid_cnt_non_zero = '1') else '0';
bvalid_cnt_non_zero <= '1' when (bvalid_cnt /= "000") else '0';
bvalid_cnt_amax <= '1' when (bvalid_cnt = "110") else '0';
bvalid_cnt_max <= '1' when (bvalid_cnt = "111") else '0';
-- Replace BVALID output register
-- Assert BVALID as long as BVALID counter /= zero
REG_BVALID: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) or
-- Ensure that if we are also incrementing BVALID counter, the BVALID stays asserted.
(bvalid_cnt = "001" and bvalid_cnt_dec = '1' and bvalid_cnt_inc = '0') then
axi_bvalid_int <= '0';
elsif (bvalid_cnt_non_zero = '1') or (bvalid_cnt_inc = '1') then
axi_bvalid_int <= '1';
else
axi_bvalid_int <= '0';
end if;
end if;
end process REG_BVALID;
---------------------------------------------------------------------------
-- *** ECC Logic ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
--
-- Generate: GEN_ECC
-- Purpose: Generate BRAM ECC write data and check ECC on read operations.
-- Create signals to update ECC registers (lite_ecc_reg module interface).
--
---------------------------------------------------------------------------
GEN_ECC: if C_ECC = 1 generate
constant null7 : std_logic_vector(0 to 6) := "0000000"; -- Specific to 32-bit data width (AXI-Lite)
constant null8 : std_logic_vector(0 to 7) := "00000000"; -- Specific to 64-bit data width
-- constant C_USE_LUT6 : boolean := Family_To_LUT_Size (String_To_Family (C_FAMILY,false)) = 6;
-- Remove usage of C_FAMILY.
-- All architectures supporting AXI will support a LUT6.
-- Hard code this internal constant used in ECC algorithm.
constant C_USE_LUT6 : boolean := TRUE;
signal RdECC : std_logic_vector(C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Temp
signal WrECC : std_logic_vector(C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal WrECC_i : std_logic_vector(C_ECC_WIDTH-1 downto 0) := (others => '0');
signal AXI_WSTRB_Q : std_logic_vector((C_AXI_DATA_WIDTH/8 - 1) downto 0) := (others => '0');
signal Syndrome : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal Syndrome_4 : std_logic_vector (0 to 1) := (others => '0'); -- Specific to 32-bit ECC
signal Syndrome_6 : std_logic_vector (0 to 5) := (others => '0'); -- Specific to 32-bit ECC
signal Syndrome_7 : std_logic_vector (0 to 11) := (others => '0'); -- Specific to 64-bit ECC
signal syndrome_reg_i : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal syndrome_reg : std_logic_vector(0 to C_INT_ECC_WIDTH-1) := (others => '0'); -- Specific to BRAM data width
signal RdModifyWr_Read : std_logic := '0'; -- Read cycle in read modify write sequence
signal RdModifyWr_Read_i : std_logic := '0';
signal RdModifyWr_Check : std_logic := '0';
signal bram_din_a_i : std_logic_vector(0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) := (others => '0'); -- Set for port data width
signal UnCorrectedRdData : std_logic_vector(0 to C_AXI_DATA_WIDTH-1) := (others => '0');
signal CE_Q : std_logic := '0';
signal Sl_CE_i : std_logic := '0';
signal Sl_UE_i : std_logic := '0';
subtype syndrome_bits is std_logic_vector(0 to C_INT_ECC_WIDTH-1);
-- 0:6 for 32-bit ECC
-- 0:7 for 64-bit ECC
type correct_data_table_type is array (natural range 0 to C_AXI_DATA_WIDTH-1) of syndrome_bits;
type bool_array is array (natural range 0 to 6) of boolean;
constant inverted_bit : bool_array := (false,false,true,false,true,false,false);
-- v1.03a
constant CODE_WIDTH : integer := C_AXI_DATA_WIDTH + C_INT_ECC_WIDTH;
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
signal h_rows : std_logic_vector (CODE_WIDTH * ECC_WIDTH - 1 downto 0);
begin
-- Generate signal to advance BRAM read address pipeline to
-- capture address for ECC error conditions (in lite_ecc_reg module).
BRAM_Addr_En <= RdModifyWr_Read;
-- v1.03a
RdModifyWr_Read <= '1' when (wr_data_ecc_sm_cs = RMW_RD_DATA) else '0';
RdModifyWr_Modify <= '1' when (wr_data_ecc_sm_cs = RMW_MOD_DATA) else '0';
RdModifyWr_Write <= '1' when (wr_data_ecc_sm_cs = RMW_WR_DATA) else '0';
-----------------------------------------------------------------------
-- Remember write data one cycle to be available after read has been completed in a
-- read/modify write operation.
-- Save WSTRBs here in this register
REG_WSTRB : process (S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
AXI_WSTRB_Q <= (others => '0');
elsif (wrdata_reg_ld = '1') then
AXI_WSTRB_Q <= AXI_WSTRB;
end if;
end if;
end process REG_WSTRB;
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_WRDATA_CMB
-- Purpose: Replace manual signal assignment for WrData_cmb with
-- generate funtion.
--
-- Ensure correct byte swapping occurs with
-- CorrectedRdData (0 to C_AXI_DATA_WIDTH-1) assignment
-- to WrData_cmb (C_AXI_DATA_WIDTH-1 downto 0).
--
-- AXI_WSTRB_Q (C_AXI_DATA_WIDTH_BYTES-1 downto 0) matches
-- to WrData_cmb (C_AXI_DATA_WIDTH-1 downto 0).
--
------------------------------------------------------------------------
GEN_WRDATA_CMB: for i in C_AXI_DATA_WIDTH_BYTES-1 downto 0 generate
begin
WrData_cmb ( (((i+1)*8)-1) downto i*8 ) <= bram_wrdata_int ((((i+1)*8)-1) downto i*8) when
(RdModifyWr_Modify = '1' and AXI_WSTRB_Q(i) = '1')
else CorrectedRdData ( (C_AXI_DATA_WIDTH - ((i+1)*8)) to
(C_AXI_DATA_WIDTH - (i*8) - 1) );
end generate GEN_WRDATA_CMB;
REG_WRDATA : process (S_AXI_AClk) is
begin
-- Remove reset value to minimize resources & improve timing
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
WrData <= WrData_cmb;
end if;
end process REG_WRDATA;
------------------------------------------------------------------------
-- New assignment of ECC bits to BRAM write data outside generate
-- blocks. Same signal assignment regardless of ECC type.
BRAM_WrData ((C_AXI_DATA_WIDTH + C_ECC_WIDTH - 1) downto C_AXI_DATA_WIDTH)
<= WrECC_i xor FaultInjectECC;
------------------------------------------------------------------------
-- v1.03a
------------------------------------------------------------------------
-- Generate: GEN_HSIAO_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
-- Derived from MIG v3.7 Hsiao HDL.
------------------------------------------------------------------------
GEN_HSIAO_ECC: if C_ECC_TYPE = 1 generate
constant ECC_WIDTH : integer := C_INT_ECC_WIDTH;
type type_int0 is array (C_AXI_DATA_WIDTH - 1 downto 0) of std_logic_vector (ECC_WIDTH - 1 downto 0);
signal syndrome_ns : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal syndrome_r : std_logic_vector(ECC_WIDTH - 1 downto 0);
signal ecc_rddata_r : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
signal h_matrix : type_int0;
signal flip_bits : std_logic_vector(C_AXI_DATA_WIDTH - 1 downto 0);
begin
---------------------- Hsiao ECC Write Logic ----------------------
-- Instantiate ecc_gen_hsiao module, generated from MIG
ECC_GEN_HSIAO: entity work.ecc_gen
generic map (
code_width => CODE_WIDTH,
ecc_width => ECC_WIDTH,
data_width => C_AXI_DATA_WIDTH
)
port map (
-- Output
h_rows => h_rows (CODE_WIDTH * ECC_WIDTH - 1 downto 0)
);
-- Merge muxed rd/write data to gen
HSIAO_ECC: process (h_rows, WrData)
constant DQ_WIDTH : integer := CODE_WIDTH;
variable ecc_wrdata_tmp : std_logic_vector(DQ_WIDTH-1 downto C_AXI_DATA_WIDTH);
begin
-- Loop to generate all ECC bits
for k in 0 to ECC_WIDTH - 1 loop
ecc_wrdata_tmp (CODE_WIDTH - k - 1) := REDUCTION_XOR ( (WrData (C_AXI_DATA_WIDTH - 1 downto 0)
and h_rows (k * CODE_WIDTH + C_AXI_DATA_WIDTH - 1 downto k * CODE_WIDTH)));
end loop;
WrECC (C_INT_ECC_WIDTH-1 downto 0) <= ecc_wrdata_tmp (DQ_WIDTH-1 downto C_AXI_DATA_WIDTH);
end process HSIAO_ECC;
-----------------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: For 32-bit ECC implementations, assign unused
-- MSB of ECC output to BRAM with '0'.
-----------------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
begin
-- Account for 32-bit and MSB '0' of ECC bits
WrECC_i <= '0' & WrECC;
end generate GEN_ECC_32;
-----------------------------------------------------------------------
-- Generate: GEN_ECC_N
-- Purpose: For all non 32-bit ECC implementations, assign ECC
-- bits for BRAM output.
-----------------------------------------------------------------------
GEN_ECC_N: if C_AXI_DATA_WIDTH /= 32 generate
begin
WrECC_i <= WrECC;
end generate GEN_ECC_N;
---------------------- Hsiao ECC Read Logic -----------------------
GEN_RD_ECC: for m in 0 to ECC_WIDTH - 1 generate
begin
syndrome_ns (m) <= REDUCTION_XOR ( BRAM_RdData (CODE_WIDTH-1 downto 0)
and h_rows ((m*CODE_WIDTH)+CODE_WIDTH-1 downto (m*CODE_WIDTH)));
end generate GEN_RD_ECC;
-- Insert register stage for syndrome
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_r <= syndrome_ns;
end if;
end process REG_SYNDROME;
ecc_rddata_r <= UnCorrectedRdData;
-- Reconstruct H-matrix
H_COL: for n in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
H_BIT: for p in 0 to ECC_WIDTH - 1 generate
begin
h_matrix (n)(p) <= h_rows (p * CODE_WIDTH + n);
end generate H_BIT;
end generate H_COL;
GEN_FLIP_BIT: for r in 0 to C_AXI_DATA_WIDTH - 1 generate
begin
flip_bits (r) <= BOOLEAN_TO_STD_LOGIC (h_matrix (r) = syndrome_r);
end generate GEN_FLIP_BIT;
CorrectedRdData (0 to C_AXI_DATA_WIDTH-1) <= ecc_rddata_r (C_AXI_DATA_WIDTH-1 downto 0) xor
flip_bits (C_AXI_DATA_WIDTH-1 downto 0);
Sl_CE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
Sl_UE_i <= not (REDUCTION_NOR (syndrome_r (ECC_WIDTH-1 downto 0))) and not (REDUCTION_XOR (syndrome_r (ECC_WIDTH-1 downto 0)));
end generate GEN_HSIAO_ECC;
------------------------------------------------------------------------
-- Generate: GEN_HAMMING_ECC
-- Purpose: Determine type of ECC encoding. Hsiao or Hamming.
-- Add parameter/generate level.
------------------------------------------------------------------------
GEN_HAMMING_ECC: if C_ECC_TYPE = 0 generate
begin
-----------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: Assign ECC out data vector (N:0) unique for 32-bit BRAM.
-- Add extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 32-bit BRAM data widths.
-- ECC bits are in upper order bits.
-----------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
constant correct_data_table_32 : correct_data_table_type := (
0 => "1100001", 1 => "1010001", 2 => "0110001", 3 => "1110001",
4 => "1001001", 5 => "0101001", 6 => "1101001", 7 => "0011001",
8 => "1011001", 9 => "0111001", 10 => "1111001", 11 => "1000101",
12 => "0100101", 13 => "1100101", 14 => "0010101", 15 => "1010101",
16 => "0110101", 17 => "1110101", 18 => "0001101", 19 => "1001101",
20 => "0101101", 21 => "1101101", 22 => "0011101", 23 => "1011101",
24 => "0111101", 25 => "1111101", 26 => "1000011", 27 => "0100011",
28 => "1100011", 29 => "0010011", 30 => "1010011", 31 => "0110011"
);
signal syndrome_4_reg : std_logic_vector (0 to 1) := (others => '0'); -- Specific for 32-bit ECC
signal syndrome_6_reg : std_logic_vector (0 to 5) := (others => '0'); -- Specific for 32-bit ECC
begin
--------------------- Hamming 32-bit ECC Write Logic ------------------
-------------------------------------------------------------------------
-- Instance: CHK_HANDLER_WR_32
-- Description: Generate ECC bits for writing into BRAM.
-- WrData (N:0)
-------------------------------------------------------------------------
CHK_HANDLER_WR_32: entity work.checkbit_handler
generic map (
C_ENCODE => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
DataIn => WrData, -- [in std_logic_vector(0 to 31)]
CheckIn => null7, -- [in std_logic_vector(0 to 6)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 6)]
Syndrome => open, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => open, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => open, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => null7, -- [in std_logic_vector(0 to 6)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open ); -- [out std_logic]
-- v1.03a
-- Account for 32-bit and MSB '0' of ECC bits
WrECC_i <= '0' & WrECC;
--------------------- Hamming 32-bit ECC Read Logic -------------------
--------------------------------------------------------------------------
-- Instance: CHK_HANDLER_RD_32
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
--------------------------------------------------------------------------
CHK_HANDLER_RD_32: entity work.checkbit_handler
generic map (
C_ENCODE => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
-- DataIn (8:39)
-- CheckIn (1:7)
DataIn => bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH), -- [in std_logic_vector(0 to 31)]
CheckIn => bram_din_a_i(1 to C_INT_ECC_WIDTH), -- [in std_logic_vector(0 to 6)]
CheckOut => open, -- [out std_logic_vector(0 to 6)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 6)]
Syndrome_4 => Syndrome_4, -- [out std_logic_vector(0 to 1)]
Syndrome_6 => Syndrome_6, -- [out std_logic_vector(0 to 5)]
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 6)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
---------------------------------------------------------------------------
-- Insert register stage for syndrome
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_reg <= Syndrome;
syndrome_4_reg <= Syndrome_4;
syndrome_6_reg <= Syndrome_6;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Do last XOR on select syndrome bits outside of checkbit_handler (to match rd_chnl
-- w/ balanced pipeline stage) before correct_one_bit module.
syndrome_reg_i (0 to 3) <= syndrome_reg (0 to 3);
PARITY_CHK4: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 2)
port map (
InA => syndrome_4_reg (0 to 1), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (4) ); -- [out std_logic]
syndrome_reg_i (5) <= syndrome_reg (5);
PARITY_CHK6: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_6_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_reg_i (6) ); -- [out std_logic]
---------------------------------------------------------------------------
-- Generate: GEN_CORR_32
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_32: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
---------------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_32
-- Description: Generate ECC bits for checking data read from BRAM.
---------------------------------------------------------------------------
CORR_ONE_BIT_32: entity work.correct_one_bit
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_32 (i))
port map (
DIn => UnCorrectedRdData (i),
Syndrome => syndrome_reg_i,
DCorr => CorrectedRdData (i));
end generate GEN_CORR_32;
end generate GEN_ECC_32;
-----------------------------------------------------------------
-- Generate: GEN_ECC_64
-- Purpose: Assign ECC out data vector (N:0) unique for 64-bit BRAM.
-- No extra '0' at MSB of ECC vector for data2mem alignment
-- w/ 64-bit BRAM data widths.
-- ECC bits are in upper order bits.
-----------------------------------------------------------------
GEN_ECC_64: if C_AXI_DATA_WIDTH = 64 generate
constant correct_data_table_64 : correct_data_table_type := (
0 => "11000001", 1 => "10100001", 2 => "01100001", 3 => "11100001",
4 => "10010001", 5 => "01010001", 6 => "11010001", 7 => "00110001",
8 => "10110001", 9 => "01110001", 10 => "11110001", 11 => "10001001",
12 => "01001001", 13 => "11001001", 14 => "00101001", 15 => "10101001",
16 => "01101001", 17 => "11101001", 18 => "00011001", 19 => "10011001",
20 => "01011001", 21 => "11011001", 22 => "00111001", 23 => "10111001",
24 => "01111001", 25 => "11111001", 26 => "10000101", 27 => "01000101",
28 => "11000101", 29 => "00100101", 30 => "10100101", 31 => "01100101",
32 => "11100101", 33 => "00010101", 34 => "10010101", 35 => "01010101",
36 => "11010101", 37 => "00110101", 38 => "10110101", 39 => "01110101",
40 => "11110101", 41 => "00001101", 42 => "10001101", 43 => "01001101",
44 => "11001101", 45 => "00101101", 46 => "10101101", 47 => "01101101",
48 => "11101101", 49 => "00011101", 50 => "10011101", 51 => "01011101",
52 => "11011101", 53 => "00111101", 54 => "10111101", 55 => "01111101",
56 => "11111101", 57 => "10000011", 58 => "01000011", 59 => "11000011",
60 => "00100011", 61 => "10100011", 62 => "01100011", 63 => "11100011"
);
signal syndrome_7_reg : std_logic_vector (0 to 11) := (others => '0');
signal syndrome7_a : std_logic := '0';
signal syndrome7_b : std_logic := '0';
begin
--------------------- Hamming 64-bit ECC Write Logic ------------------
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_WR_64
-- Description: Generate ECC bits for writing into BRAM when configured
-- as 64-bit wide BRAM.
-- WrData (N:0)
-- Enable C_REG on encode path.
---------------------------------------------------------------------------
CHK_HANDLER_WR_64: entity work.checkbit_handler_64
generic map (
C_ENCODE => true, -- [boolean]
C_REG => true, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
Clk => S_AXI_AClk, -- [in std_logic]
DataIn => WrData_cmb, -- [in std_logic_vector(0 to 63)]
CheckIn => null8, -- [in std_logic_vector(0 to 7)]
CheckOut => WrECC, -- [out std_logic_vector(0 to 7)]
Syndrome => open, -- [out std_logic_vector(0 to 7)]
Syndrome_7 => open, -- [out std_logic_vector(0 to 11)]
Syndrome_Chk => null8, -- [in std_logic_vector(0 to 7)]
Enable_ECC => '1', -- [in std_logic]
UE_Q => '0', -- [in std_logic]
CE_Q => '0', -- [in std_logic]
UE => open, -- [out std_logic]
CE => open ); -- [out std_logic]
-- Note: (7:0) Old bit lane assignment
-- BRAM_WrData ((C_ECC_WIDTH - 1) downto 0)
-- v1.02a
-- WrECC is assigned to BRAM_WrData (71:64)
-- v1.03a
-- BRAM_WrData (71:64) assignment done outside of this
-- ECC type generate block.
WrECC_i <= WrECC;
--------------------- Hamming 64-bit ECC Read Logic -------------------
---------------------------------------------------------------------------
-- Instance: CHK_HANDLER_RD_64
-- Description: Generate ECC bits for checking data read from BRAM.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
CHK_HANDLER_RD_64: entity work.checkbit_handler_64
generic map (
C_ENCODE => false, -- [boolean]
C_REG => false, -- [boolean]
C_USE_LUT6 => C_USE_LUT6) -- [boolean]
port map (
Clk => S_AXI_AClk, -- [in std_logic]
-- DataIn (8:71)
-- CheckIn (0:7)
DataIn => bram_din_a_i (C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1), -- [in std_logic_vector(0 to 63)]
CheckIn => bram_din_a_i (0 to C_INT_ECC_WIDTH-1), -- [in std_logic_vector(0 to 7)]
CheckOut => open, -- [out std_logic_vector(0 to 7)]
Syndrome => Syndrome, -- [out std_logic_vector(0 to 7)]
Syndrome_7 => Syndrome_7, -- [out std_logic_vector(0 to 11)]
Syndrome_Chk => syndrome_reg_i, -- [in std_logic_vector(0 to 7)]
Enable_ECC => Enable_ECC, -- [in std_logic]
UE_Q => UE_Q, -- [in std_logic]
CE_Q => CE_Q, -- [in std_logic]
UE => Sl_UE_i, -- [out std_logic]
CE => Sl_CE_i ); -- [out std_logic]
---------------------------------------------------------------------------
-- Insert register stage for syndrome
REG_SYNDROME: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
syndrome_reg <= Syndrome;
syndrome_7_reg <= Syndrome_7;
end if;
end process REG_SYNDROME;
---------------------------------------------------------------------------
-- Move final XOR to registered side of syndrome bits.
-- Do last XOR on select syndrome bits after pipeline stage
-- before correct_one_bit_64 module.
syndrome_reg_i (0 to 6) <= syndrome_reg (0 to 6);
PARITY_CHK7_A: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome7_a ); -- [out std_logic]
PARITY_CHK7_B: entity work.parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => syndrome_7_reg (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome7_b ); -- [out std_logic]
syndrome_reg_i (7) <= syndrome7_a xor syndrome7_b;
---------------------------------------------------------------------------
-- Generate: GEN_CORRECT_DATA
-- Purpose: Generate corrected read data based on syndrome value.
-- All vectors oriented (0:N)
---------------------------------------------------------------------------
GEN_CORR_64: for i in 0 to C_AXI_DATA_WIDTH-1 generate
begin
---------------------------------------------------------------------------
-- Instance: CORR_ONE_BIT_64
-- Description: Generate ECC bits for checking data read from BRAM.
---------------------------------------------------------------------------
CORR_ONE_BIT_64: entity work.correct_one_bit_64
generic map (
C_USE_LUT6 => C_USE_LUT6,
Correct_Value => correct_data_table_64 (i))
port map (
DIn => UnCorrectedRdData (i),
Syndrome => syndrome_reg_i,
DCorr => CorrectedRdData (i));
end generate GEN_CORR_64;
end generate GEN_ECC_64;
end generate GEN_HAMMING_ECC;
-- Remember correctable/uncorrectable error from BRAM read
CORR_REG: process(S_AXI_AClk) is
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if RdModifyWr_Modify = '1' then -- Capture error signals
CE_Q <= Sl_CE_i;
UE_Q <= Sl_UE_i;
else
CE_Q <= '0';
UE_Q <= '0';
end if;
end if;
end process CORR_REG;
-- ECC register block gets registered UE or CE conditions to update
-- ECC registers/interrupt/flag outputs.
Sl_CE <= CE_Q;
Sl_UE <= UE_Q;
CE_Failing_We <= CE_Q;
FaultInjectClr <= '1' when (bvalid_cnt_inc_d1 = '1') else '0';
-----------------------------------------------------------------------
-- Add register delay on BVALID counter increment
-- Used to clear fault inject register.
REG_BVALID_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
bvalid_cnt_inc_d1 <= '0';
else
bvalid_cnt_inc_d1 <= bvalid_cnt_inc;
end if;
end if;
end process REG_BVALID_CNT;
-----------------------------------------------------------------------
-- Map BRAM_RdData (N:0) to bram_din_a_i (0:N)
-- Including read back ECC bits.
bram_din_a_i (0 to C_AXI_DATA_WIDTH+C_ECC_WIDTH-1) <=
BRAM_RdData (C_AXI_DATA_WIDTH+C_ECC_WIDTH-1 downto 0);
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- Generate: GEN_ECC_32
-- Purpose: For 32-bit ECC implementations, account for
-- extra bit in read data mapping on registered value.
-----------------------------------------------------------------------
GEN_ECC_32: if C_AXI_DATA_WIDTH = 32 generate
begin
-- Insert register stage for read data to correct
REG_CHK_DATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
UnCorrectedRdData <= bram_din_a_i(C_INT_ECC_WIDTH+1 to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH);
end if;
end process REG_CHK_DATA;
end generate GEN_ECC_32;
-----------------------------------------------------------------------
-- Generate: GEN_ECC_N
-- Purpose: For all non 32-bit ECC implementations, assign ECC
-- bits for BRAM output.
-----------------------------------------------------------------------
GEN_ECC_N: if C_AXI_DATA_WIDTH /= 32 generate
begin
-- Insert register stage for read data to correct
REG_CHK_DATA: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
UnCorrectedRdData <= bram_din_a_i(C_INT_ECC_WIDTH to C_INT_ECC_WIDTH+C_AXI_DATA_WIDTH-1);
end if;
end process REG_CHK_DATA;
end generate GEN_ECC_N;
end generate GEN_ECC;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Drive default output signals when ECC is diabled.
---------------------------------------------------------------------------
GEN_NO_ECC: if C_ECC = 0 generate
begin
BRAM_Addr_En <= '0';
FaultInjectClr <= '0';
CE_Failing_We <= '0';
Sl_CE <= '0';
Sl_UE <= '0';
end generate GEN_NO_ECC;
---------------------------------------------------------------------------
-- *** BRAM Interface Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WE
-- Purpose: BRAM WE generate process
-- One WE per 8-bits of BRAM data.
---------------------------------------------------------------------------
GEN_BRAM_WE: for i in C_AXI_DATA_WIDTH/8 + (C_ECC*(1+(C_AXI_DATA_WIDTH/128))) - 1 downto 0 generate
begin
BRAM_WE (i) <= bram_we_int (i);
end generate GEN_BRAM_WE;
---------------------------------------------------------------------------
BRAM_En <= bram_en_int;
---------------------------------------------------------------------------
-- BRAM Address Generate
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
--
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
--
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_WRDATA
-- Purpose: Generate BRAM Write Data.
---------------------------------------------------------------------------
GEN_BRAM_WRDATA: for i in C_AXI_DATA_WIDTH-1 downto 0 generate
begin
-- Check if ECC is enabled
-- If so, XOR the fault injection vector with the data
-- (post-pipeline) to avoid any timing issues on the data vector
-- from AXI.
-----------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Generate output write data when ECC is disabled.
-----------------------------------------------------------------------
GEN_NO_ECC : if C_ECC = 0 generate
begin
BRAM_WrData (i) <= bram_wrdata_int (i);
end generate GEN_NO_ECC;
-----------------------------------------------------------------------
-- Generate: GEN_NO_ECC
-- Purpose: Generate output write data when ECC is enable
-- (use fault vector)
-- (N:0)
-- for 32-bit (31:0) WrData while (ECC = [39:32])
-----------------------------------------------------------------------
GEN_W_ECC : if C_ECC = 1 generate
begin
BRAM_WrData (i) <= WrData (i) xor FaultInjectData (i);
end generate GEN_W_ECC;
end generate GEN_BRAM_WRDATA;
---------------------------------------------------------------------------
end architecture implementation;
|
mit
|
ed061ba39c5aec21e36c96d2dd0d71be
| 0.416168 | 4.795712 | false | false | false | false |
6769/VHDL
|
Lab_4/Part1/__report_code.vhd
| 1 | 6,572 |
--------------------------------------------------------------
------------------------------------------------------------
-- clock_second.vhd
------------------------------------------------------------
--------------------------------------------------------------
--Intertime clock
library ieee;
use ieee.numeric_bit.all;
entity clock_second is
port(clk:in bit ;
second:buffer bit);
end entity clock_second;
architecture Distribution of clock_second is
signal counter_for_osc_signal:unsigned(31 downto 0);
begin
process
begin
wait until clk'event and clk='1';
if counter_for_osc_signal < 25--*1000*1000
then
counter_for_osc_signal<=counter_for_osc_signal+1;
else counter_for_osc_signal<=(others=>'0');
second<=not second;
--here is the problem that second signal will result unflatten square wave,if using the commented mathod.
end if;
end process;
-- second<='1' when counter_for_osc_signal> 25*1000*1000 --High_percent_of_counter
-- else '0' ;
-- timing analysis here ...
end architecture Distribution;
--------------------------------------------------------------
------------------------------------------------------------
-- counter_max10.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
entity counter_max10 is
port(clk:in bit ;reset:in bit;limit:in bit;
carry:out bit;
CountedNumber:buffer unsigned(3 downto 0));
end entity counter_max10;
architecture behavior of counter_max10 is
begin
carry<=CountedNumber(3)and CountedNumber(0)and limit;--"1001"
process(clk,reset,limit)
begin
if(reset='0') then CountedNumber<=(others=>'0');
elsif (clk'event and clk='1' and limit='1') then
if(CountedNumber< 9) then CountedNumber<=CountedNumber+1;
else CountedNumber<="0000";
end if;
end if;
end process;
end architecture behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- Segment7Decoder.vhd
------------------------------------------------------------
--------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(7 downto 1) -- 7 bit decoded output.
);
end Segment7Decoder;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of Segment7Decoder is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
when "1010"=> segment7 <="0001000"; --'A'
when "1011"=> segment7 <="0000011"; --'b'
when "1100"=> segment7 <="0100111"; --'c'
when "1101"=> segment7 <="0100001"; --'d'
when "1110"=> segment7 <="0000110"; --'E'
when "1111"=> segment7 <="0001110"; --'f'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end Behavioral;
--------------------------------------------------------------
------------------------------------------------------------
-- Threebit_BCD_counter.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
entity Threebit_BCD_counter is
port( clk:in bit;reset:in bit;
Counter_Result:out unsigned(11 downto 0) );
end entity Threebit_BCD_counter;
architecture combination of Threebit_BCD_counter is
signal midcarry:bit_vector(2 downto 1);
signal mid_second:bit;
alias hex0:unsigned(3 downto 0) is Counter_Result(3 downto 0);
alias hex1:unsigned(3 downto 0) is Counter_Result(7 downto 4);
alias hex2:unsigned(3 downto 0) is Counter_Result(11 downto 8);
component counter_max10
port(clk:in bit ;reset:in bit;limit:in bit;
carry:out bit;
CountedNumber:buffer unsigned(3 downto 0));
end component;
component clock_second is
port(clk:in bit ;
second:buffer bit);
end component;
begin
High50MhzToSecond:clock_second port map(clk,mid_second);
hex0_lable:counter_max10 port map(mid_second,reset,'1',midcarry(1),hex0);
hex1_lable:counter_max10 port map(mid_second,reset,midcarry(1),midcarry(2),hex1 );
hex2_lable:counter_max10 port map(mid_second,reset,midcarry(2),open ,hex2 );
end architecture combination;
--------------------------------------------------------------
------------------------------------------------------------
-- View_output.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
entity View_output is
port(clk:in bit; reset:in bit;
hex0_out:out bit_vector(7 downto 0);
hex1_out:out bit_vector(7 downto 0);
hex2_out:out bit_vector(7 downto 0));
end entity View_output;
architecture combination_of_View of View_output is
--type
component Threebit_BCD_counter is
port( clk:in bit;reset:in bit;
Counter_Result:out unsigned(11 downto 0) );
end component;
component Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(7 downto 1) -- 7 bit decoded output.
);
end component;
signal mid_12bit_result:unsigned(11 downto 0);
alias mid_hex0:unsigned(3 downto 0) is mid_12bit_result(3 downto 0);
alias mid_hex1:unsigned(3 downto 0) is mid_12bit_result(7 downto 4);
alias mid_hex2:unsigned(3 downto 0) is mid_12bit_result(11 downto 8);
begin
Synthesis:Threebit_BCD_counter port map(clk,reset,mid_12bit_result);
hex0_out(0)<='1';
hex1_out(0)<='1';
hex2_out(0)<='1';
hex0_display:Segment7Decoder port map(bit_vector(mid_hex0),hex0_out(7 downto 1));
hex1_display:Segment7Decoder port map(bit_vector(mid_hex1),hex1_out(7 downto 1));
hex2_display:Segment7Decoder port map(bit_vector(mid_hex2),hex2_out(7 downto 1));
end architecture combination_of_View;
|
gpl-2.0
|
ccbbe9899c8e10c21596e63e8155886b
| 0.555082 | 3.787896 | false | false | false | false |
6769/VHDL
|
Lab_5/__FromSaru/lab50/__report_from_SaSa.vhd
| 1 | 8,126 |
--------------------------------------------------------------
------------------------------------------------------------
-- adder.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(addend1,addend2:in std_logic_vector(3 downto 0);
sum:out std_logic_vector(3 downto 0));
end adder;
architecture add of adder is
begin
sum<=addend1+addend2;
end add;
--------------------------------------------------------------
------------------------------------------------------------
-- comparator.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comparator is
port(point:in std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0);
eq:out bit);
end comparator;
architecture compare of comparator is
begin
--could be alternatived by MUX statements...3 lines...--
process(point,sum)
begin
if point=sum then
eq<='1';
else eq<='0';
end if;
end process;
end compare;
--------------------------------------------------------------
------------------------------------------------------------
-- control.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port(reset,rb,eq,d7,d711,d2312:in bit;
roll,win,lose,sp:out bit);
end control;
architecture con of control is
signal count:std_logic_vector(3 downto 0):="0000";
signal w,l:bit;
begin
process(reset,rb)
begin
if reset='0' then
sp<='1';
count<="0000";
elsif rb'event and rb='1' then
count<=count+1;
elsif rb'event and rb='0' and count="0001" then
sp<='0';
end if;
roll<=not rb;
end process;
process(count,eq,d7,d711,d2312)
begin
--if w='0' and l='0' then
if count="0000" then
w <='0';l <='0';
elsif count="0001" then
w <=d711;l <=d2312;
else
w <=eq;l <=d7;
end if;
--end if;
end process;
win<=w;
lose<=l;
end con;
--------------------------------------------------------------
------------------------------------------------------------
-- counter_1_6.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_1_6 is
port(clk_50m,roll:in bit;
out_count:inout std_logic_vector(3 downto 0));
end counter_1_6;
architecture count of counter_1_6 is
signal count:std_logic_vector(3 downto 0):="0000";
begin
process(clk_50m,roll,count)
begin
if roll='1' then
if clk_50m'event and clk_50m='0' then
if count>"0100" then
count<="0001";
else count<=count+1;
end if;
end if;
else out_count<=count;
end if;
end process;
end count;
--------------------------------------------------------------
------------------------------------------------------------
-- decoder_1_6.vhd
------------------------------------------------------------
--------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY decoder_1_6 IS
PORT(
m:IN STD_LOGIC_vector(3 downto 0);
led_vector:out bit_vector(7 DOWNTO 0));
END decoder_1_6;
ARCHITECTURE decoder_architecture OF decoder_1_6 IS
BEGIN
PROCESS(m)
BEGIN
CASE m IS
WHEN "0001" => led_vector<="11111001";--F9=>1
WHEN "0010" => led_vector<="10100100";--A4=>2
WHEN "0011" => led_vector<="10110000";--B0=>3
WHEN "0100" => led_vector<="10011001";--99=>4
WHEN "0101" => led_vector<="10010010";--92=>5
WHEN "0110" => led_vector<="10000010";--82=>6
WHEN others => led_vector<="11111111";--FF=>²»ÁÁ
END CASE;
END PROCESS;
END decoder_architecture;
--------------------------------------------------------------
------------------------------------------------------------
-- lab50.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lab50 is
port(reset,rb,clk_50m,clk_28m:in bit;
win,lose:out bit;
led1,led2:out bit_vector(7 downto 0));
end lab50;
architecture allmap of lab50 is
component counter_1_6 is
port(clk_50m,roll:in bit;
out_count:inout std_logic_vector(3 downto 0));
end component;
component decoder_1_6 IS
PORT(m:IN STD_LOGIC_vector(3 downto 0);
led_vector:out bit_vector(7 DOWNTO 0));
end component;
component adder is
port(addend1,addend2:in std_logic_vector(3 downto 0);
sum:out std_logic_vector(3 downto 0));
end component;
component point_register is
port(sp:in bit;
point:out std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0));
end component;
component comparator is
port(point:in std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0);
eq:out bit);
end component;
component test_logic is
port(sum:in std_logic_vector(3 downto 0);
d7,d711,d2312:out bit);
end component;
component control is
port(reset,rb,eq,d7,d711,d2312:in bit;
roll,win,lose,sp:out bit);
end component;
signal roll,eq,d7,d711,d2312,sp:bit;
signal count1,count2,sum,point:std_logic_vector(3 downto 0);
begin
decoder1:decoder_1_6 port map(m=>count1,led_vector=>led1);
decoder2:decoder_1_6 port map(m=>count2,led_vector=>led2);
counter1:counter_1_6 port map(clk_50m=>clk_50m,roll=>roll,out_count=>count1);
counter2:counter_1_6 port map(clk_50m=>clk_28m,roll=>roll,out_count=>count2);
add:adder port map(addend1=>count1,addend2=>count2,sum=>sum);
pr:point_register port map(sp=>sp,point=>point,sum=>sum);
compare:comparator port map(point=>point,sum=>sum,eq=>eq);
test:test_logic port map(sum=>sum,d7=>d7,d711=>d711,d2312=>d2312);
con:control port map(reset=>reset,rb=>rb,
eq=>eq,d7=>d7,d711=>d711,d2312=>d2312,
roll=>roll,win=>win,lose=>lose,sp=>sp);
end allmap;
--------------------------------------------------------------
------------------------------------------------------------
-- point_register.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity point_register is
--latch the last value--
port(sp:in bit;
point:out std_logic_vector(3 downto 0):="0000";
sum:in std_logic_vector(3 downto 0));
end point_register;
architecture point of point_register is
--signal count:bit;
begin
process(sp,sum)
begin
if sp='0' then
--count<='0';
elsif sp='1' then
--count<='1';
point<=sum;
end if;
end process;
end point;
--------------------------------------------------------------
------------------------------------------------------------
-- test_logic.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity test_logic is
port(sum:in std_logic_vector(3 downto 0);
d7,d711,d2312:out bit);
end test_logic;
architecture test of test_logic is
begin
process(sum)
begin
if sum="0111" then
d7<='1';
else d7<='0';
end if;
if sum="0111" or sum="1011" then
d711<='1';
else d711<='0';
end if;
if sum="0010" or sum="0011" or sum="1100" then
d2312<='1';
else d2312<='0';
end if;
end process;
end test;
|
gpl-2.0
|
105e53ce2a7ae529b8dc283d52cc2141
| 0.482033 | 3.836638 | false | false | false | false |
hanw/Open-Source-FPGA-Bitcoin-Miner
|
projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/golden_ticket_fifo/fifo_generator_v10_0/ramfifo/dmem.vhd
| 9 | 12,163 |
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|
gpl-3.0
|
00d3d916355e3d1c464e3b0f557cad5d
| 0.93102 | 1.900469 | false | false | false | false |
1995parham/FPGA-Homework
|
HW-3/src/p5/counter.vhd
| 1 | 893 |
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 28-03-2016
-- Module Name: p9.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
generic (N : integer := 4);
port (clk, reset : in std_logic;
count : out std_logic_vector (N - 1 downto 0));
end entity counter;
architecture behavioral of counter is
begin
process (clk, reset)
variable count_buff : std_logic_vector (N - 1 downto 0) := (others => '0');
begin
if clk'event and clk = '1' then
count <= count_buff;
count_buff := count_buff + '1';
end if;
if reset = '1' then
count_buff := (others => '0');
count <= count_buff;
end if;
end process;
end architecture behavioral;
|
gpl-3.0
|
5c16292d88885e44537f8d56d8c8f97c
| 0.533035 | 3.572 | false | false | false | false |
frankvanbever/MIPS_processor
|
testbenches/register_file_tb.vhd
| 1 | 3,946 |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:48:55 03/04/2013
-- Design Name:
-- Module Name: /home/frank/Dropbox/Workspaces/Workspace_xilinx/reg_file/register_file_tb.vhd
-- Project Name: reg_file
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: register_file
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY register_file_tb IS
END register_file_tb;
ARCHITECTURE behavior OF register_file_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT register_file
PORT(
clk : IN std_logic;
Read_reg_1 : IN std_logic_vector(25 downto 21);
Read_reg_2 : IN std_logic_vector(20 downto 16);
Write_reg : IN std_logic_vector(15 downto 11);
Write_data : IN std_logic_vector(31 downto 0);
Read_data_1 : OUT std_logic_vector(31 downto 0);
Read_data_2 : OUT std_logic_vector(31 downto 0);
write_enable : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal Read_reg_1 : std_logic_vector(25 downto 21) := (others => '0');
signal Read_reg_2 : std_logic_vector(20 downto 16) := (others => '0');
signal Write_reg : std_logic_vector(15 downto 11) := (others => '0');
signal Write_data : std_logic_vector(31 downto 0) := (others => '0');
signal write_enable : std_logic := '0';
--Outputs
signal Read_data_1 : std_logic_vector(31 downto 0);
signal Read_data_2 : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: register_file PORT MAP (
clk => clk,
Read_reg_1 => Read_reg_1,
Read_reg_2 => Read_reg_2,
Write_reg => Write_reg,
Write_data => Write_data,
Read_data_1 => Read_data_1,
Read_data_2 => Read_data_2,
write_enable => write_enable
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- set write enable to zero
write_enable <= '0';
-- test with zero
Read_reg_1 <= (others => '0');
Read_reg_2 <= (others => '0');
wait for clk_period*2;
assert Read_data_2 = X"00000000" report "Incorrect value at test with zero";
assert Read_data_1 = X"00000000" report "Incorrect value at test with zero";
wait for clk_period*10;
-- write a value into register one
write_enable <= '1';
Write_reg <= "00001";
Write_data <= X"00000002";
wait for clk_period*2;
write_enable <= '0';
Read_reg_1 <= "00001";
wait for clk_period;
assert Read_data_1 = X"00000002" report "Data is niet correct geschreven";
-- try to write a value into register 0
wait for clk_period*10;
write_enable <= '1';
Write_reg <= "00000";
Write_data <= X"10000000";
wait for clk_period;
write_enable <= '0';
Read_reg_1 <= "00000";
wait for clk_period;
assert Read_data_1 = X"00000000" report "Data is naar het 0 register geschreven";
wait;
end process;
END;
|
mit
|
9737725e31b604cb0bdba2daafc09301
| 0.622402 | 3.344068 | false | true | false | false |
6769/VHDL
|
Lab_3/Part01/__report_sum_up.vhd
| 1 | 2,612 |
--------------------------------------------------------------
------------------------------------------------------------
-- FSM_core.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
use ieee.std_logic_1164.all;
entity FSM_core is
port(X:in bit;
CLK:in bit;
reset:in bit;
stateout:out integer range 0 to 8;
Z:out bit);
end entity FSM_core;
architecture Behavior of FSM_core is
signal State,nextState:bit_vector(3 downto 0);
alias Q0:bit is State(0);
alias Q1:bit is State(1);
alias Q2:bit is State(2);
alias Q3:bit is State(3);
begin
stateout<=to_integer(unsigned(State));
Z<=(Q3 or Q2 )and not Q1 and not Q0;
--Q0`=x(q0'q1'+q0q2+q1q0')+x'(q3'q2'+q2q0')
nextState(0)<=(X and ((not Q0 and not Q2) or (Q0 and Q2)or (Q1 and not Q0)))or (not X and ((not Q3 and not Q2)or (Q2 and not Q0 )));
nextState(1)<=(x and ((Q1 and not Q0 and not Q2)or (not Q1 and Q0 and not Q2)))or(not x and ((not Q1 and Q0 and Q2)or (Q1 and not Q0 and Q2) )) ;
nextState(2)<=(X and ( (not Q1 and not Q0 and Q2) or (Q1 and Q0 and not Q2) ))or(not X and ( (not Q3 and not Q2) or (Q1 and not Q0 ) or (not Q1 and Q2) ));
nextState(3)<=not X and ( (Q3 and not Q2) or (Q1 and Q0 and Q2) );
process(CLK,reset)
begin
if reset='0' then State<="0000";
elsif CLK'event and CLK='1' then
State<=nextState;
end if;
end process;
end architecture Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- View_input.vhd
------------------------------------------------------------
--------------------------------------------------------------
entity View_input is
port (reset:in bit;
w: in bit;
clk:in bit;
z: out bit;
state8_0:out bit_vector(8 downto 0));--LED Red for showing State table
end entity View_input;
architecture match of View_input is
component FSM_core
port(
X: in bit;
CLK: in bit;
reset:in bit;
stateout:out integer range 0 to 8;
Z: out bit);
end component;
signal stateout:integer range 0 to 8;
begin
lable_1:fsm_core port map(w,clk,reset,stateout,z);
with stateout select --mux choice
state8_0 <= "000000001" when 0,
"000000010" when 1,
"000000100" when 2,
"000001000" when 3,
"000010000" when 4,
"000100000" when 5,
"001000000" when 6,
"010000000" when 7,
"100000000" when 8;
end architecture match;
|
gpl-2.0
|
594d27c18bc08dd2d62de1ca3a6f12d9
| 0.503063 | 3.357326 | false | false | false | false |
1995parham/FPGA-Homework
|
Project-Phase1/src/sequential/memory.vhd
| 2 | 1,369 |
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 30-03-2016
-- Module Name: memory.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity memory is
port (address : in std_logic_vector;
data_in : in std_logic_vector;
data_out : out std_logic_vector;
clk, rwbar, en, reset : in std_logic);
end entity memory;
architecture behavioral of memory is
type mem is array (natural range <>, natural range <>) of std_logic;
begin
process (clk)
constant memsize : integer := 2 ** address'length;
variable memory : mem (0 to memsize - 1, data_in'range);
begin
if clk'event and clk = '1' then
if reset = '1' then -- Reseting :D
for I in 0 to memsize - 1 loop
for J in data_in'range loop
memory(I, J) := '0';
end loop;
end loop;
elsif rwbar = '1' and en = '1' then -- Readiing :)
for i in data_out'range loop
data_out(i) <= memory (to_integer(unsigned(address)), i);
end loop;
elsif rwbar = '0' and en = '1' then -- Writing :)
for i in data_in'range loop
memory (to_integer(unsigned(address)), i) := data_in (i);
end loop;
end if;
end if;
end process;
end architecture behavioral;
|
gpl-3.0
|
c5affc7db54f041376ea477c440d410c
| 0.564646 | 3.397022 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/dist_mem_gen_v8_0/dist_mem_gen_v8_0.vhd
| 1 | 16,918 |
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66rduYq+9/uPKUw=
`protect end_protected
|
mit
|
85025dc368e1196dc85ed463a095941b
| 0.937995 | 1.883755 | false | false | false | false |
1995parham/FPGA-Homework
|
BCD/bcd_64_multiplier.vhd
| 1 | 1,368 |
library IEEE;
use IEEE.std_logic_1164.all;
entity bcd_sixty_four_multiplier is
port(
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
c: out std_logic_vector(63 downto 0)
);
end entity;
architecture struct of bcd_sixty_four_multiplier is
component bcd_eight_multiplier is
port (a: in std_logic_vector (31 downto 0);
b: in std_logic_vector (3 downto 0);
v: out std_logic_vector (35 downto 0));
end component;
component bcd_64_bit_adder is
port(
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
res: out std_logic_vector(63 downto 0)
);
end component;
type multipication_result is array (7 downto 0) of std_logic_vector(63 downto 0);
signal res: multipication_result := (others => (others => '0'));
signal intermediate: multipication_result := (others => (others => '0'));
begin
multiply_digit:
for i in 0 to 7 generate
digit_multiplier: bcd_eight_multiplier port map(a, b((i + 1) * 4 - 1 downto i * 4), res(i)((35 + i * 4) downto (0 + i * 4)));
end generate multiply_digit;
simple_adder: bcd_64_bit_adder port map(res(0), res(1), intermediate(0));
add_digit:
for i in 2 to 7 generate
adder: bcd_64_bit_adder port map(res(i), intermediate(i - 2), intermediate(i - 1));
end generate add_digit;
c <= intermediate(6);
end architecture;
|
gpl-3.0
|
fb0bf040a7a8d7640b37e7ccb16293ee
| 0.665936 | 3.060403 | false | false | false | false |
6769/VHDL
|
Lab_5/__FromSaru/lab50/counter_1_6.vhd
| 1 | 553 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter_1_6 is
port(clk_50m,roll:in bit;
out_count:inout std_logic_vector(3 downto 0));
end counter_1_6;
architecture count of counter_1_6 is
signal count:std_logic_vector(3 downto 0):="0000";
begin
process(clk_50m,roll,count)
begin
if roll='1' then
if clk_50m'event and clk_50m='0' then
if count>"0100" then
count<="0001";
else count<=count+1;
end if;
end if;
else out_count<=count;
end if;
end process;
end count;
|
gpl-2.0
|
0ae38d79139eb4333dfa18ed3eb20516
| 0.665461 | 2.895288 | false | false | false | false |
sorgelig/SAMCoupe_MIST
|
sid/sid_top.vhd
| 1 | 9,973 |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity sid_top is
generic (
g_filter_div : natural := 424; --for 96 MHz (221; -- for 50 MHz)
g_num_voices : natural := 3 );
port (
clock : in std_logic;
reset : in std_logic;
addr : in unsigned(7 downto 0);
wren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
comb_wave_l : in std_logic := '0';
comb_wave_r : in std_logic := '0';
start_iter : in std_logic;
sample_left : out signed(17 downto 0);
sample_right : out signed(17 downto 0);
active : out std_logic;
extfilter_en : in std_logic
);
end sid_top;
architecture structural of sid_top is
-- Voice index in pipe
signal voice_osc : unsigned(3 downto 0);
signal voice_wave : unsigned(3 downto 0);
signal voice_mul : unsigned(3 downto 0);
signal enable_osc : std_logic;
signal enable_wave : std_logic;
signal enable_mul : std_logic;
-- Oscillator parameters
signal freq : unsigned(15 downto 0);
signal test : std_logic;
signal sync : std_logic;
-- Wave map parameters
signal msb_other : std_logic;
signal comb_mode : std_logic;
signal ring_mod : std_logic;
signal wave_sel : std_logic_vector(3 downto 0);
signal sq_width : unsigned(11 downto 0);
-- ADSR parameters
signal gate : std_logic;
signal attack : std_logic_vector(3 downto 0);
signal decay : std_logic_vector(3 downto 0);
signal sustain : std_logic_vector(3 downto 0);
signal release : std_logic_vector(3 downto 0);
-- Filter enable
signal filter_en : std_logic;
-- globals
signal volume_l : unsigned(3 downto 0);
signal filter_co_l : unsigned(10 downto 0);
signal filter_res_l : unsigned(3 downto 0);
signal filter_hp_l : std_logic;
signal filter_bp_l : std_logic;
signal filter_lp_l : std_logic;
signal voice3_off_l : std_logic;
signal volume_r : unsigned(3 downto 0);
signal filter_co_r : unsigned(10 downto 0);
signal filter_res_r : unsigned(3 downto 0);
signal filter_hp_r : std_logic;
signal filter_bp_r : std_logic;
signal filter_lp_r : std_logic;
signal voice3_off_r : std_logic;
-- readback
signal osc3 : std_logic_vector(7 downto 0);
signal env3 : std_logic_vector(7 downto 0);
-- intermediate flags and signals
signal test_wave : std_logic;
signal osc_val : unsigned(23 downto 0);
signal carry_20 : std_logic;
signal enveloppe : unsigned(7 downto 0);
signal waveform : unsigned(11 downto 0);
signal valid_sum : std_logic;
signal valid_filt : std_logic;
signal valid_mix : std_logic;
signal filter_out_l: signed(17 downto 0) := (others => '0');
signal direct_out_l: signed(17 downto 0) := (others => '0');
signal high_pass_l : signed(17 downto 0) := (others => '0');
signal band_pass_l : signed(17 downto 0) := (others => '0');
signal low_pass_l : signed(17 downto 0) := (others => '0');
signal mixed_out_l : signed(17 downto 0) := (others => '0');
signal filter_out_r: signed(17 downto 0) := (others => '0');
signal direct_out_r: signed(17 downto 0) := (others => '0');
signal high_pass_r : signed(17 downto 0) := (others => '0');
signal band_pass_r : signed(17 downto 0) := (others => '0');
signal low_pass_r : signed(17 downto 0) := (others => '0');
signal mixed_out_r : signed(17 downto 0) := (others => '0');
begin
i_regs: entity work.sid_regs
port map
(
clock => clock,
reset => reset,
addr => addr,
wren => wren,
wdata => wdata,
rdata => rdata,
comb_wave_l => comb_wave_l,
comb_wave_r => comb_wave_r,
voice_osc => voice_osc,
voice_wave => voice_wave,
voice_adsr => voice_wave,
voice_mul => voice_mul,
-- Oscillator parameters
freq => freq,
test => test,
sync => sync,
-- Wave map parameters
comb_mode => comb_mode,
ring_mod => ring_mod,
wave_sel => wave_sel,
sq_width => sq_width,
-- ADSR parameters
gate => gate,
attack => attack,
decay => decay,
sustain => sustain,
release => release,
-- mixer parameters
filter_en => filter_en,
-- globals
volume_l => volume_l,
filter_co_l => filter_co_l,
filter_res_l=> filter_res_l,
filter_ex_l => open,
filter_hp_l => filter_hp_l,
filter_bp_l => filter_bp_l,
filter_lp_l => filter_lp_l,
voice3_off_l=> voice3_off_l,
volume_r => volume_r,
filter_co_r => filter_co_r,
filter_res_r=> filter_res_r,
filter_ex_r => open,
filter_hp_r => filter_hp_r,
filter_bp_r => filter_bp_r,
filter_lp_r => filter_lp_r,
voice3_off_r=> voice3_off_r,
-- readback
osc3 => osc3,
env3 => env3
);
i_ctrl: entity work.sid_ctrl
generic map
(
g_num_voices => g_num_voices
)
port map
(
clock => clock,
reset => reset,
start_iter => start_iter,
voice_osc => voice_osc,
enable_osc => enable_osc
);
osc: entity work.oscillator
generic map
(
g_num_voices
)
port map
(
clock => clock,
reset => reset,
voice_i => voice_osc,
voice_o => voice_wave,
enable_i => enable_osc,
enable_o => enable_wave,
freq => freq,
test => test,
sync => sync,
osc_val => osc_val,
test_o => test_wave,
carry_20 => carry_20,
msb_other => msb_other
);
wmap: entity work.wave_map
generic map
(
g_num_voices => g_num_voices,
g_sample_bits => 12
)
port map
(
clock => clock,
reset => reset,
test => test_wave,
osc_val => osc_val,
carry_20 => carry_20,
msb_other => msb_other,
voice_i => voice_wave,
enable_i => enable_wave,
comb_mode => comb_mode,
wave_sel => wave_sel,
ring_mod => ring_mod,
sq_width => sq_width,
voice_o => voice_mul,
enable_o => enable_mul,
wave_out => waveform
);
adsr: entity work.adsr_multi
generic map
(
g_num_voices => g_num_voices
)
port map
(
clock => clock,
reset => reset,
voice_i => voice_wave,
enable_i => enable_wave,
voice_o => open,
enable_o => open,
gate => gate,
attack => attack,
decay => decay,
sustain => sustain,
release => release,
env_state=> open, -- for testing only
env_out => enveloppe
);
sum: entity work.mult_acc(signed_wave)
port map
(
clock => clock,
reset => reset,
voice_i => voice_mul,
enable_i => enable_mul,
voice3_off_l=> voice3_off_l,
voice3_off_r=> voice3_off_r,
enveloppe => enveloppe,
waveform => waveform,
filter_en => filter_en,
osc3 => osc3,
env3 => env3,
valid_out => valid_sum,
filter_out_L => filter_out_L,
filter_out_R => filter_out_R,
direct_out_L => direct_out_L,
direct_out_R => direct_out_R
);
i_filt_left: entity work.sid_filter
generic map
(
g_divider => g_filter_div
)
port map
(
clock => clock,
reset => reset,
enable => extfilter_en,
filt_co => filter_co_l,
filt_res => filter_res_l,
valid_in => valid_sum,
input => filter_out_L,
high_pass => high_pass_L,
band_pass => band_pass_L,
low_pass => low_pass_L,
error_out => open,
valid_out => valid_filt
);
mix: entity work.sid_mixer
port map
(
clock => clock,
reset => reset,
valid_in => valid_filt,
direct_out => direct_out_L,
high_pass => high_pass_L,
band_pass => band_pass_L,
low_pass => low_pass_L,
filter_hp => filter_hp_l,
filter_bp => filter_bp_l,
filter_lp => filter_lp_l,
volume => volume_l,
mixed_out => mixed_out_L,
valid_out => open
);
i_filt_right: entity work.sid_filter
generic map
(
g_divider => g_filter_div
)
port map
(
clock => clock,
reset => reset,
enable => extfilter_en,
filt_co => filter_co_r,
filt_res => filter_res_r,
valid_in => valid_sum,
input => filter_out_R,
high_pass => high_pass_R,
band_pass => band_pass_R,
low_pass => low_pass_R,
error_out => open,
valid_out => open
);
mix_right: entity work.sid_mixer
port map
(
clock => clock,
reset => reset,
valid_in => valid_filt,
direct_out => direct_out_R,
high_pass => high_pass_R,
band_pass => band_pass_R,
low_pass => low_pass_R,
filter_hp => filter_hp_r,
filter_bp => filter_bp_r,
filter_lp => filter_lp_r,
volume => volume_r,
mixed_out => mixed_out_R,
valid_out => open
);
sample_left <= mixed_out_L;
sample_right <= mixed_out_R;
active <= '1' when volume_l /="0000" or volume_r /="0000" else '0';
end structural;
|
gpl-2.0
|
51de0a1f06eb7f1b7325f6107d34fe80
| 0.52963 | 3.060141 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/sng_port_arb.vhd
| 7 | 17,789 |
-------------------------------------------------------------------------------
-- sng_port_arb.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: sng_port_arb.vhd
--
-- Description: This file is the top level arbiter for full AXI4 mode
-- when configured in a single port mode to BRAM.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add input signal, AW2Arb_BVALID_Cnt, from wr_chnl. For configurations
-- when WREADY is to be a registered output. With a seperate FIFO for BID,
-- ensure arbitration does not get more than 8 ahead of BID responses. A
-- value of 8 is the max of the BVALID counter.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
------------------------------------------------------------------------------
entity sng_port_arb is
generic (
C_S_AXI_ADDR_WIDTH : integer := 32
-- Width of AXI address bus (in bits)
);
port (
-- *** AXI Clock and Reset ***
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
-- *** AXI Write Address Channel Signals (AW) ***
AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_AWVALID : in std_logic;
AXI_AWREADY : out std_logic := '0';
-- *** AXI Read Address Channel Signals (AR) ***
AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
AXI_ARVALID : in std_logic;
AXI_ARREADY : out std_logic := '0';
-- *** Write Channel Interface Signals ***
Arb2AW_Active : out std_logic := '0';
AW2Arb_Busy : in std_logic;
AW2Arb_Active_Clr : in std_logic;
AW2Arb_BVALID_Cnt : in std_logic_vector (2 downto 0);
-- *** Read Channel Interface Signals ***
Arb2AR_Active : out std_logic := '0';
AR2Arb_Active_Clr : in std_logic
);
end entity sng_port_arb;
-------------------------------------------------------------------------------
architecture implementation of sng_port_arb is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_RESET_ACTIVE : std_logic := '0';
constant ARB_WR : std_logic := '0';
constant ARB_RD : std_logic := '1';
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Write & Read Address Channel Signals
-------------------------------------------------------------------------------
-- State machine type declarations
type ARB_SM_TYPE is ( IDLE,
RD_DATA,
WR_DATA
);
signal arb_sm_cs, arb_sm_ns : ARB_SM_TYPE;
signal axi_awready_cmb : std_logic := '0';
signal axi_awready_int : std_logic := '0';
signal axi_arready_cmb : std_logic := '0';
signal axi_arready_int : std_logic := '0';
signal last_arb_won_cmb : std_logic := '0';
signal last_arb_won : std_logic := '0';
signal aw_active_cmb : std_logic := '0';
signal aw_active : std_logic := '0';
signal ar_active_cmb : std_logic := '0';
signal ar_active : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** AXI Output Signals ***
---------------------------------------------------------------------------
-- AXI Write Address Channel Output Signals
AXI_AWREADY <= axi_awready_int;
-- AXI Read Address Channel Output Signals
AXI_ARREADY <= axi_arready_int;
---------------------------------------------------------------------------
-- *** AXI Write Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** AXI Read Address Channel Interface ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- *** Internal Arbitration Interface ***
---------------------------------------------------------------------------
Arb2AW_Active <= aw_active;
Arb2AR_Active <= ar_active;
---------------------------------------------------------------------------
-- Main Arb State Machine
--
-- Description: Main arbitration logic when AXI BRAM controller
-- configured in a single port BRAM mode.
-- Module is instantiated when C_SINGLE_PORT_BRAM = 1.
--
-- Outputs: last_arb_won Registered
-- aw_active Registered
-- ar_active Registered
-- axi_awready_int Registered
-- axi_arready_int Registered
--
--
-- ARB_SM_CMB_PROCESS: Combinational process to determine next state.
-- ARB_SM_REG_PROCESS: Registered process of the state machine.
--
---------------------------------------------------------------------------
ARB_SM_CMB_PROCESS: process ( AXI_AWVALID,
AXI_ARVALID,
AW2Arb_BVALID_Cnt,
AW2Arb_Busy,
AW2Arb_Active_Clr,
AR2Arb_Active_Clr,
last_arb_won,
aw_active,
ar_active,
arb_sm_cs )
begin
-- assign default values for state machine outputs
arb_sm_ns <= arb_sm_cs;
axi_awready_cmb <= '0';
axi_arready_cmb <= '0';
last_arb_won_cmb <= last_arb_won;
aw_active_cmb <= aw_active;
ar_active_cmb <= ar_active;
case arb_sm_cs is
---------------------------- IDLE State ---------------------------
when IDLE =>
-- Check for valid read operation
-- Reads take priority over AW traffic (if both asserted)
-- 4/11
-- if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or
-- ((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- 4/11
-- Add BVALID counter to AW arbitration.
-- Since this is arbitration to read, no need for BVALID counter.
if ((AXI_ARVALID = '1') and (AXI_AWVALID = '1') and (last_arb_won = ARB_WR)) or -- and
--(AW2Arb_BVALID_Cnt /= "111")) or
((AXI_ARVALID = '1') and (AXI_AWVALID = '0')) then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Write operations are lower priority than reads
-- when an AXI master asserted both operations simultaneously.
-- 4/11 elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
elsif (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
end if;
------------------------- WR_DATA State -------------------------
when WR_DATA =>
-- Wait for write operation to complete
if (AW2Arb_Active_Clr = '1') then
aw_active_cmb <= '0';
-- Check early for pending read (to save clock cycle
-- in transitioning back to IDLE)
if (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
-- Note: if timing paths occur b/w wr_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a read operation.
else
arb_sm_ns <= IDLE;
end if;
end if;
---------------------------- RD_DATA State ---------------------------
when RD_DATA =>
-- Wait for read operation to complete
if (AR2Arb_Active_Clr = '1') then
ar_active_cmb <= '0';
-- Check early for pending write operation (to save clock cycle
-- in transitioning back to IDLE)
-- 4/11 if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') then
if (AXI_AWVALID = '1') and (AW2Arb_Busy = '0') and
(AW2Arb_BVALID_Cnt /= "111") then
-- Write wins arbitration
arb_sm_ns <= WR_DATA;
axi_awready_cmb <= '1';
last_arb_won_cmb <= ARB_WR;
aw_active_cmb <= '1';
-- Note: if timing paths occur b/w rd_chnl data SM
-- and here, remove this clause to check for early
-- arbitration on a write operation.
-- Check early for a pending back-to-back read operation
elsif (AXI_AWVALID = '0') and (AXI_ARVALID = '1') then
-- Read wins arbitration
arb_sm_ns <= RD_DATA;
axi_arready_cmb <= '1';
last_arb_won_cmb <= ARB_RD;
ar_active_cmb <= '1';
else
arb_sm_ns <= IDLE;
end if;
end if;
--coverage off
------------------------------ Default ----------------------------
when others =>
arb_sm_ns <= IDLE;
--coverage on
end case;
end process ARB_SM_CMB_PROCESS;
---------------------------------------------------------------------------
ARB_SM_REG_PROCESS: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1' ) then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
arb_sm_cs <= IDLE;
last_arb_won <= ARB_WR;
aw_active <= '0';
ar_active <= '0';
axi_awready_int <='0';
axi_arready_int <='0';
else
arb_sm_cs <= arb_sm_ns;
last_arb_won <= last_arb_won_cmb;
aw_active <= aw_active_cmb;
ar_active <= ar_active_cmb;
axi_awready_int <= axi_awready_cmb;
axi_arready_int <= axi_arready_cmb;
end if;
end if;
end process ARB_SM_REG_PROCESS;
---------------------------------------------------------------------------
end architecture implementation;
|
mit
|
5b87229994003b29e8eaddcb1d55b050
| 0.394795 | 5.150261 | false | false | false | false |
sbates130272/capi-textswap
|
rtl/proc_memcpy.vhd
| 1 | 2,651 |
--------------------------------------------------------------------------------
--
-- Copyright 2015 PMC-Sierra, Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License"); you
-- may not use this file except in compliance with the License. You may
-- obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0 Unless required by
-- applicable law or agreed to in writing, software distributed under the
-- License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-- CONDITIONS OF ANY KIND, either express or implied. See the License for
-- the specific language governing permissions and limitations under the
-- License.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company: PMC-Sierra, Inc.
-- Engineer: Logan Gunthorpe
--
-- Description:
-- Copy input data to output.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library capi;
entity proc_memcpy is
port (
clk : in std_logic;
en : in std_logic;
idata : in std_logic_vector(0 to 511);
ivalid : in std_logic;
idone : in std_logic;
iready : out std_logic;
odata : out std_logic_vector(0 to 511);
ovalid : out std_logic;
odirty : out std_logic;
oready : in std_logic;
odone : out std_logic;
len : in unsigned(0 to 31)
);
end entity proc_memcpy;
architecture main of proc_memcpy is
signal fifo_rst : std_logic;
signal fifo_write : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
begin
fifo_rst <= not en;
fifo_write <= ivalid and not fifo_full;
iready <= not fifo_full;
odirty <= '0';
FIFO: entity capi.sync_fifo_fwft
generic map (
WRITE_SLACK => 2,
DATA_BITS => idata'length,
ADDR_BITS => 3)
port map (
clk => clk,
rst => fifo_rst,
write => fifo_write,
write_data => idata,
full => fifo_full,
read => oready,
read_valid => ovalid,
read_data => odata,
empty => fifo_empty);
DONE_P: process (clk) is
begin
if rising_edge(clk) then
odone <= fifo_empty and not ivalid and en and idone;
end if;
end process DONE_P;
end architecture main;
|
apache-2.0
|
0697c09a115ca85f652b278770ee869f
| 0.50132 | 4.262058 | false | false | false | false |
sorgelig/SAMCoupe_MIST
|
t80/T80.vhd
| 1 | 34,338 |
--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup.
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
-- Z80 compatible microprocessor core
--
-- Version : 0247
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
-- 0210 : Fixed wait and halt
-- 0211 : Fixed Refresh addition and IM 1
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
-- 0237 : Changed 8080 I/O address output, added IntE output
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
);
end T80;
architecture rtl of T80 is
constant aNone : std_logic_vector(2 downto 0) := "111";
constant aBC : std_logic_vector(2 downto 0) := "000";
constant aDE : std_logic_vector(2 downto 0) := "001";
constant aXY : std_logic_vector(2 downto 0) := "010";
constant aIOA : std_logic_vector(2 downto 0) := "100";
constant aSP : std_logic_vector(2 downto 0) := "101";
constant aZI : std_logic_vector(2 downto 0) := "110";
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal WZ : std_logic_vector(15 downto 0); -- MEMPTR register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_RXDD : std_logic;
signal I_INRC : std_logic;
signal SetWZ : std_logic_vector(1 downto 0);
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
signal DOR : std_logic_vector(127 downto 0);
begin
REG <= DOR & std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC when Alternate = '0'
else DOR(127 downto 112) & DOR(47 downto 0) & DOR(63 downto 48) & DOR(111 downto 64) &
std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC;
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetWZ => SetWZ,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
WZ => WZ,
XY_State=> XY_State,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
variable n : std_logic_vector(7 downto 0);
variable ioq : std_logic_vector(8 downto 0);
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
WZ <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
I_RXDD <= '0';
elsif rising_edge(CLK_n) then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= WZ(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(WZ(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= WZ;
PC <= unsigned(WZ);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= WZ(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(WZ(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= WZ;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
WZ <= (ACC & DI_Reg) + "1";
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
if SetWZ = "01" then
WZ <= RegBusC + "1";
end if;
if SetWZ = "10" then
WZ(7 downto 0) <= RegBusC(7 downto 0) + "1";
WZ(15 downto 8) <= ACC;
end if;
end if;
when aDE =>
A <= RegBusC;
if SetWZ = "10" then
WZ(7 downto 0) <= RegBusC(7 downto 0) + "1";
WZ(15 downto 8) <= ACC;
end if;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(WZ) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= WZ(7 downto 0);
if SetWZ = "10" then
WZ(7 downto 0) <= WZ(7 downto 0) + "1";
WZ(15 downto 8) <= ACC;
end if;
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
if SetWZ = "11" then
WZ <= std_logic_vector(ID16);
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if (TState = 2 and I_BTR = '1' and IR(0) = '1') or (TState = 1 and I_BTR = '1' and IR(0) = '0') then
ioq := ('0' & DI_Reg) + ('0' & std_logic_vector(ID16(7 downto 0)));
F(Flag_N) <= DI_Reg(7);
F(Flag_C) <= ioq(8);
F(Flag_H) <= ioq(8);
ioq := (ioq and x"7") xor ('0'&BusA);
F(Flag_P) <= not (ioq(0) xor ioq(1) xor ioq(2) xor ioq(3) xor ioq(4) xor ioq(5) xor ioq(6) xor ioq(7));
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
WZ <= std_logic_vector(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
WZ <= (others =>'0');
WZ(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
WZ <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if MCycle = "011" and TState = 4 and No_BTR = '0' then
if I_BT = '1' or I_BC = '1' then
WZ <= std_logic_vector(PC)-"1";
end if;
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
WZ(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
WZ(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
F(Flag_S) <= I(7);
if I = x"00" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_Y) <= I(5);
F(Flag_H) <= '0';
F(Flag_X) <= I(3);
F(Flag_N) <= '0';
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
F(Flag_S) <= R(7);
if R = x"00" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_Y) <= R(5);
F(Flag_H) <= '0';
F(Flag_X) <= R(3);
F(Flag_N) <= '0';
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
F(Flag_X) <= DI_Reg(3);
F(Flag_Y) <= DI_Reg(5);
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 and Auto_Wait_t1 = '0' then
-- Keep D0 from M3 for RLD/RRD (Sorgelig)
I_RXDD <= I_RLD or I_RRD;
if I_RXDD='0' then
DO <= BusB;
end if;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if TState = 1 and I_BC = '1' then
n := ALU_Q - ("0000000" & F_Out(Flag_H));
F(Flag_X) <= n(3);
F(Flag_Y) <= n(1);
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if rising_edge(CLK_n) then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0' and Auto_Wait_t1 = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0),
DOR => DOR);
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if rising_edge(CLK_n) then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusA <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif rising_edge(CLK_n) then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif rising_edge(CLK_n) then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif rising_edge(CLK_n) then
if CEN = '1' then
Auto_Wait_t2 <= Auto_Wait_t1;
if T_Res = '1' then
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
else
Auto_Wait_t1 <= Auto_Wait or IORQ_i;
end if;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or (MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or No_BTR = '1' or (MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif IntE_FF1 = '1' and INT_n='0' and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if (Auto_Wait = '1' and Auto_Wait_t2 = '0') nor
(IOWait = 1 and IORQ_i = '1' and Auto_Wait_t1 = '0') then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
|
gpl-2.0
|
d0e12b82a313f6eb0ef4ab1f53d718d8
| 0.509406 | 2.934872 | false | false | false | false |
6769/VHDL
|
Lab_6/TheFinalCodeVersion/__report_formats.vhd
| 1 | 14,126 |
--------------------------------------------------------------
------------------------------------------------------------
-- Addsub.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity Addsub_Unit is
Generic (n : Integer := 16);
port(
a,b: in std_logic_vector(n-1 downto 0);
select_add_sub: in std_logic;
result: buffer std_logic_vector(n-1 downto 0)
);
end entity Addsub_Unit;
architecture Behavior of Addsub_Unit is
begin
process(select_add_sub,a,b)
begin
case select_add_sub is
when '0'=>
result<=a+b;
when '1'=>
result<=a-b;
when others=>
result<=(others=>'Z');
end case;
end process;
end architecture Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- Control_unit.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity Control_unit is
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--multiplexer
Riout:out std_logic_vector(0 to n_of_reg-1);
Gout,DINout:out std_logic;
--Register Data in
Rin:out std_logic_vector(0 to n_of_reg-1);
Ain,Gin:out std_logic;
--ALU control_unit
AddSub:out std_logic;
--Counter state
Tstep_Q:in std_logic_vector(1 downto 0);
Clear:out std_logic;
--singular control signal
Run,Resetn:in std_logic;
Done:buffer std_logic
);
end entity Control_unit;
architecture behavior of Control_unit is
--declare component
--
--
component dec3to8 --InstructionSet decoder to multiplexers
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end component;
--declare signals
--
--
subtype regwidth is std_logic_vector(15 downto 0);
--InstructionSet
signal IR:std_logic_vector(1 to 9);
signal I,X,Y:std_LOGIC_vector(1 to 3);
signal Xreg,Yreg:std_logic_vector(0 to 7);
begin
Clear<= (not Resetn) or Done;
--InstructionFormat I..X..Y..
process(IRset,Run)
begin
if(Run='1' )then
IR<=IRset;
end if;
end process;
I <= IR(1 to 3); --IR 1,2,3
X <= IR(4 to 6);
Y <= IR(7 to 9);
--InstructionDecoder to MUX
decX : dec3to8 port map(X, '1', Xreg);--IR 4,5,6
decY : dec3to8 port map(Y, '1', Yreg);--IR 7,8,9
controlsignals:
process (Tstep_Q, I, Xreg, Yreg)--,Run)
begin
--specify initial values
Done<='0';
--to multiplexer
DINout<='0';
Gout<='0';
Riout<=(others =>'0');
--to register
Rin<=(others =>'0');
Ain<='0';
Gin<='0';
IRin<='0';
AddSub<='Z';
--if(Run='1')then
case Tstep_Q is
when "00" => -- store DIN in IR as long as Tstep_Q = 0
IRin <= '1';
when "01" => -- define signals in time step T1
case I is
when "000"=>--MV Rx,Ry;
Riout<=Yreg;
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "001"=>--MVi Rx,imd;
DINout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "010"=>--Add Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when "011"=>--Sub Rx,Ry; Rxout,Ain;
Riout<=Xreg;
Ain<='1';
when others=>null;
end case;
when "10" => -- define signals in time step T2
case I is
when "010"=>--Add Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='0';
Gin<='1';
when "011"=>--Sub Rx,Ry; Ryout,Gin;
Riout<=Yreg;
AddSub<='1';
Gin<='1';
when others=>null;
end case;
when "11" => -- define signals in time step T3
case I is
when "010"=>--Add Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when "011"=>--Sub Rx,Ry; Gout,Rxin;
Gout<='1';
Rin(to_integer(unsigned(X)))<='1';
Done<='1';
when others=>null;
end case;
end case;
--end if;
end process;
end architecture behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- dec3to8.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dec3to8 is
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end dec3to8;
architecture Behavior of dec3to8 is
begin
process (W, En)
begin
if En = '1' then
case W is
when "000" => Y <= "10000000";
when "001" => Y <= "01000000";
when "010" => Y <= "00100000";
when "011" => Y <= "00010000";
when "100" => Y <= "00001000";
when "101" => Y <= "00000100";
when "110" => Y <= "00000010";
when "111" => Y <= "00000001";
when others=> null;
end case;
else
Y <= "00000000";
end if;
end process;
end Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- multiplexers.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity multiplexers is
generic(
N:integer:=2;--number of register;
n_multi:integer:=16 --bus width
);
port(
DataIn,reg_G:in std_logic_vector(n_multi-1 downto 0);
reg0: in std_logic_vector(n_multi-1 downto 0);
reg1: in std_logic_vector(n_multi-1 downto 0);
control_reg:in std_logic_vector( 0 to N-1);
control_GDi:in std_logic_vector(1 downto 0);
out_to_bus: buffer std_logic_vector(n_multi-1 downto 0)
);
end entity multiplexers;
architecture choice of multiplexers is
signal mid_choice:std_logic_vector(N+2-1 downto 0);
begin
mid_choice<=control_reg&control_GDi;--0~7|G|Din--
-- out_to_bus<= DataIn when control_GDi(0)='1'
-- else reg_G when control_GDi(1)='1'
-- else reg0 when control_reg(0)='1'
-- else reg1 when control_reg(1)='1'
-- ;--else (others=>'Z');
process(mid_choice,reg0,reg1,reg_G,DataIn)
begin
case mid_choice is
when "1000"=>
out_to_bus<=reg0;
when "0100"=>
out_to_bus<=reg1;
when "0010"=>
out_to_bus<=reg_G;
when others=>
--when "0001"=>
out_to_bus<=DataIn;
--when others=>
end case;
end process;
end architecture choice;
--------------------------------------------------------------
------------------------------------------------------------
-- regn.vhd
------------------------------------------------------------
--------------------------------------------------------------
Library ieee;
Use ieee.std_logic_1164.All;
Entity regn Is
Generic (n : Integer := 16);
Port (
R : In STD_LOGIC_VECTOR(n - 1 Downto 0);
Rin, Clock : In STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR(n - 1 Downto 0)
);
End regn;
Architecture Behavior Of regn Is
Begin
Process (Clock)
Begin
If Clock'EVENT And Clock = '1' Then
If Rin = '1' Then
Q <= R;
End If;
End If;
End Process;
End Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- upcount.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity upcount is
port (
Clear, Clock : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(1 downto 0)
);
end upcount;
architecture Behavior of upcount is
signal Count : STD_LOGIC_VECTOR(1 downto 0);
begin
process (Clock)
begin
if (Clock'EVENT and Clock = '1') then
if Clear = '1' then
Count <= "00";
else
Count <= Count + 1;
end if;
end if;
end process;
Q <= Count;
end Behavior;
--------------------------------------------------------------
------------------------------------------------------------
-- View.vhd
------------------------------------------------------------
--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity View is
port (
DIN : in STD_LOGIC_VECTOR(15 downto 0);
Resetn, Clock, Run : in STD_LOGIC;
Done : out STD_LOGIC;
BusWires : buffer STD_LOGIC_VECTOR(15 downto 0)
);
end View;
architecture Behavior of View is
--declare component
--
--
component dec3to8 --InstructionSet decoder to multiplexers
port (
W : in STD_LOGIC_VECTOR(2 downto 0);
En : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(0 to 7)
);
end component;
component regn --usual register
Generic (n : Integer := 16);
Port (
R : In STD_LOGIC_VECTOR(n - 1 Downto 0);
Rin, Clock : In STD_LOGIC;
Q : Buffer STD_LOGIC_VECTOR(n - 1 Downto 0)
);
end component;
component upcount
port (
Clear, Clock : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
component Addsub_Unit
Generic (n : Integer := 16);
port(
a,b: in std_logic_vector(n-1 downto 0);
select_add_sub: in std_logic;
result: buffer std_logic_vector(n-1 downto 0)
);
end component;
component multiplexers
generic(
N:integer:=2;--number of register;
n_multi:integer:=16 --bus width
);
port(
DataIn,reg_G:in std_logic_vector(n_multi-1 downto 0);
reg0: in std_logic_vector(n_multi-1 downto 0);
reg1: in std_logic_vector(n_multi-1 downto 0);
control_reg:in std_logic_vector( 0 to N-1);
control_GDi:in std_logic_vector(1 downto 0);
out_to_bus: buffer std_logic_vector(n_multi-1 downto 0)
);
end component;
component Control_unit
generic(
--the number of universal register
n_of_reg:integer:=8
);
port(
--IR control_unit
IRset:in std_logic_vector(0 to 8);--instruction length =9 bits
IRin:out std_logic;
--multiplexer
Riout:out std_logic_vector(0 to n_of_reg-1);
Gout,DINout:out std_logic;
--Register Data in
Rin:out std_logic_vector(0 to n_of_reg-1);
Ain,Gin:out std_logic;
--ALU control_unit
AddSub:out std_logic;
--Counter state
Tstep_Q:in std_logic_vector(1 downto 0);
Clear:out std_logic;
--singular control signal
Run,Resetn:in std_logic;
Done:buffer std_logic
);
end component;
--declare signals
--
--
subtype regwidth is std_logic_vector(15 downto 0);
signal R0,R1,A,G:regwidth;
---------------------------------
--Control_unit output
---------------------------------
--IR control_unit
signal IRset: std_logic_vector(0 to 8);--instruction length =9 bits
signal IRin: std_logic;
--multiplexer
signal Riout: std_logic_vector(0 to 7);
signal Gout,DINout: std_logic;
--Register Data in
signal Rin: std_logic_vector(0 to 7);
signal Ain,Gin: std_logic;
--ALU control_unit
signal AddSub: std_logic;
--Counter state
signal Tstep_Q: std_logic_vector(1 downto 0);
signal Clear: std_logic;
--singular control signal
--signal Run,Resetn: std_logic;
--signal Done: std_logic;
-------------------------------------
signal ALU_result:std_logic_vector(15 downto 0);
begin
Tstep : upcount port map(Clear, Clock , Tstep_Q);
-- Din, RinControl,Clk,ROut
reg_0 : regn port map(BusWires, Rin(0), Clock, R0);
reg_1 : regn port map(BusWires, Rin(1), Clock, R1);
reg_A : regn port map(BusWires, Ain, Clock, A );
reg_G : regn port map(ALU_result, Gin, Clock, G );
reg_IR: regn generic map(9) port map(DIN(15 downto 7),IRin,Clock,IRset);
ALU_Unit:
Addsub_Unit port map(A, BusWires,AddSub, ALU_result);
--instantiate other registers and the adder/subtracter unit
Multiplexer_Unit:
multiplexers generic map(N=>2,n_multi=>16) port map(DIN,G,R0,R1,Riout(0 to 1) ,Gout&DINout,BusWires);
--define the bus
--Control_unit
--------------------
Control_unit_label:Control_unit port map(
IRset,--instruction length =9 bits
IRin,
--multiplexer
Riout,
Gout,DINout,
--Register Data in
Rin,
Ain,Gin,
--ALU control_unit
AddSub,
--Counter state
Tstep_Q,
Clear,
--singular control signal
Run,Resetn,
Done
);
--------------------
end architecture Behavior;
|
gpl-2.0
|
1343339723c03821ab9d52a811645ead
| 0.471117 | 3.793233 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/VGA/ipcore_dir/blk_mem_gen_v7_3.vhd
| 2 | 5,677 |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v7_3.vhd when simulating
-- the core, blk_mem_gen_v7_3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v7_3 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END blk_mem_gen_v7_3;
ARCHITECTURE blk_mem_gen_v7_3_a OF blk_mem_gen_v7_3 IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_gen_v7_3
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_gen_v7_3 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 4,
c_addrb_width => 4,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16,
c_read_depth_b => 16,
c_read_width_a => 16,
c_read_width_b => 16,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16,
c_write_depth_b => 16,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 16,
c_write_width_b => 16,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v7_3
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END blk_mem_gen_v7_3_a;
|
mit
|
e98bf0f24aeed25d1ac774d8d575253a
| 0.532147 | 3.802411 | false | false | false | false |
6769/VHDL
|
Lab_6/TheFinalCodeVersion/multiplexers.vhd
| 2 | 1,349 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity multiplexers is
generic(
N:integer:=2;--number of register;
n_multi:integer:=16 --bus width
);
port(
DataIn,reg_G:in std_logic_vector(n_multi-1 downto 0);
reg0: in std_logic_vector(n_multi-1 downto 0);
reg1: in std_logic_vector(n_multi-1 downto 0);
control_reg:in std_logic_vector( 0 to N-1);
control_GDi:in std_logic_vector(1 downto 0);
out_to_bus: buffer std_logic_vector(n_multi-1 downto 0)
);
end entity multiplexers;
architecture choice of multiplexers is
signal mid_choice:std_logic_vector(N+2-1 downto 0);
begin
mid_choice<=control_reg&control_GDi;--0~7|G|Din--
-- out_to_bus<= DataIn when control_GDi(0)='1'
-- else reg_G when control_GDi(1)='1'
-- else reg0 when control_reg(0)='1'
-- else reg1 when control_reg(1)='1'
-- ;--else (others=>'Z');
process(mid_choice,reg0,reg1,reg_G,DataIn)
begin
case mid_choice is
when "1000"=>
out_to_bus<=reg0;
when "0100"=>
out_to_bus<=reg1;
when "0010"=>
out_to_bus<=reg_G;
when others=>
--when "0001"=>
out_to_bus<=DataIn;
--when others=>
end case;
end process;
end architecture choice;
|
gpl-2.0
|
c51f6690fbf0ab7244761ae87aadefcf
| 0.587102 | 3.052036 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/VGA/ipcore_dir/fifo_mem/example_design/fifo_mem_exdes.vhd
| 2 | 4,972 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_mem_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fifo_mem_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END fifo_mem_exdes;
ARCHITECTURE xilinx OF fifo_mem_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT fifo_mem IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : fifo_mem
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
|
mit
|
7db73d42cff191122253c494fe26a3fa
| 0.557321 | 4.629423 | false | false | false | false |
sorgelig/SAMCoupe_MIST
|
sid/my_math_pkg.vhd
| 6 | 4,097 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package my_math_pkg is
function sum_limit(i1, i2 : signed) return signed;
function sub_limit(i1, i2 : signed) return signed;
function sum_limit(i1, i2 : unsigned) return unsigned;
function extend(x : signed; len : natural) return signed;
function extend(x : unsigned; len : natural) return unsigned;
function left_align(x : signed; len : natural) return signed;
function left_scale(x : signed; sh : natural) return signed;
-- function shift_right(x : signed; positions: natural) return signed;
end;
package body my_math_pkg is
function sum_limit(i1, i2 : signed) return signed is
variable o : signed(i1'range);
begin
assert i1'length = i2'length
report "i1 and i2 should have the same length!"
severity failure;
o := i1 + i2;
if (i1(i1'left) = i2(i2'left)) and (o(o'left) /= i1(i1'left)) then
if i1(i1'left)='1' then
o := to_signed(-(2**(o'length-1)), o'length);
else
o := to_signed(2**(o'length-1) - 1, o'length);
end if;
end if;
return o;
end function;
function sub_limit(i1, i2 : signed) return signed is
variable o : signed(i1'range);
begin
assert i1'length = i2'length
report "i1 and i2 should have the same length!"
severity failure;
o := i1 - i2;
if (i1(i1'left) /= i2(i2'left)) and (o(o'left) /= i1(i1'left)) then
if i1(i1'left)='1' then
o := to_signed(-(2**(o'length-1)), o'length);
else
o := to_signed(2**(o'length-1) - 1, o'length);
end if;
end if;
return o;
end function;
function sum_limit(i1, i2 : unsigned) return unsigned is
variable o : unsigned(i1'length downto 0);
begin
o := ('0' & i1) + i2;
if o(o'left)='1' then
o := (others => '1');
end if;
return o(i1'length-1 downto 0);
end function;
function extend(x : signed; len : natural) return signed is
variable ret : signed(len-1 downto 0);
alias a : signed(x'length-1 downto 0) is x;
begin
ret := (others => x(x'left));
ret(a'range) := a;
return ret;
end function extend;
function extend(x : unsigned; len : natural) return unsigned is
variable ret : unsigned(len-1 downto 0);
alias a : unsigned(x'length-1 downto 0) is x;
begin
ret := (others => '0');
ret(a'range) := a;
return ret;
end function extend;
function left_align(x : signed; len : natural) return signed is
variable ret : signed(len-1 downto 0);
begin
ret := (others => '0');
ret(len-1 downto len-x'length) := x;
return ret;
end function left_align;
function left_scale(x : signed; sh : natural) return signed is
alias a : signed(x'length-1 downto 0) is x;
variable ret : signed(x'length-(1+sh) downto 0);
variable top : signed(sh downto 0);
begin
if sh=0 then
return x;
end if;
top := a(a'high downto a'high-sh);
if (top = -1) or (top = 0) then -- can shift without getting punished!
ret := a(ret'range);
elsif a(a'high)='1' then -- negative and can't shift, so max neg:
ret := (others => '0');
ret(ret'high) := '1';
else -- positive and can't shift, so max pos
ret := (others => '1');
ret(ret'high) := '0';
end if;
return ret;
end function left_scale;
-- function shift_right(x : signed; positions: natural) return signed is
-- alias a : signed(x'length-1 downto 0) is x;
-- variable ret : signed(x'length-1 downto 0);
-- begin
-- ret := (others => x(x'left));
-- ret(a'left-positions downto 0) := a(a'left downto positions);
-- return ret;
-- end function shift_right;
end;
|
gpl-2.0
|
6e9bb8fc18b717b3f7bd5fd269b23d34
| 0.545277 | 3.486809 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/full_axi.vhd
| 7 | 43,438 |
-------------------------------------------------------------------------------
-- full_axi.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: full_axi.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller when configured in a full AXI4 mode.
-- The rd_chnl and wr_chnl modules are instantiated.
-- The ECC AXI-Lite register module is instantiated, if enabled.
-- When single port BRAM mode is selected, the arbitration logic
-- is instantiated (and connected to each wr_chnl & rd_chnl).
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen_hsiao.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen_hsiao.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- Remove library version # dependency. Replace with work library.
-- ^^^^^^
-- JLJ 2/15/2011 v1.03a
-- ~~~~~~
-- Initial integration of Hsiao ECC algorithm.
-- Add C_ECC_TYPE top level parameter and mappings on instantiated modules.
-- ^^^^^^
-- JLJ 2/18/2011 v1.03a
-- ~~~~~~
-- Update WE & BRAM data sizes based on 128-bit ECC configuration.
-- Plus XST clean-up.
-- ^^^^^^
-- JLJ 3/31/2011 v1.03a
-- ~~~~~~
-- Add coverage tags.
-- ^^^^^^
-- JLJ 4/11/2011 v1.03a
-- ~~~~~~
-- Add signal, AW2Arb_BVALID_Cnt, between wr_chnl and sng_port_arb modules.
-- ^^^^^^
-- JLJ 4/20/2011 v1.03a
-- ~~~~~~
-- Add default values for Arb2AW_Active & Arb2AR_Active when dual port mode.
-- ^^^^^^
-- JLJ 5/6/2011 v1.03a
-- ~~~~~~
-- Remove usage of C_FAMILY.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
use work.lite_ecc_reg;
use work.sng_port_arb;
use work.wr_chnl;
use work.rd_chnl;
------------------------------------------------------------------------------
entity full_axi is
generic (
-- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_ECC_WIDTH : integer := 8;
-- Width of ECC data vector
C_ECC_TYPE : integer := 0; -- v1.03a
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
C_ECC_ONOFF_RESET_VALUE : integer := 1;
-- By default, ECC checking is on (can disable ECC @ reset by setting this to 0)
-- Hard coded parameters at top level.
-- Note: Kept in design for future enhancement.
C_ENABLE_AXI_CTRL_REG_IF : integer := 0;
-- By default the ECC AXI-Lite register interface is enabled
C_CE_FAILING_REGISTERS : integer := 0;
-- Enable CE (correctable error) failing registers
C_UE_FAILING_REGISTERS : integer := 0;
-- Enable UE (uncorrectable error) failing registers
C_ECC_STATUS_REGISTERS : integer := 0;
-- Enable ECC status registers
C_ECC_ONOFF_REGISTER : integer := 0;
-- Enable ECC on/off control register
C_CE_COUNTER_WIDTH : integer := 0
-- Selects CE counter width/threshold to assert ECC_Interrupt
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
ECC_Interrupt : out std_logic := '0';
ECC_UE : out std_logic := '0';
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
S_AXI_AWLOCK : in std_logic;
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
S_AXI_WLAST : in std_logic;
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
S_AXI_ARLOCK : in std_logic;
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
-- AXI Read Data Channel Signals (R)
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RLAST : out std_logic;
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Clock and Reset
-- TBD
-- S_AXI_CTRL_ACLK : in std_logic;
-- S_AXI_CTRL_ARESETN : in std_logic;
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID : in std_logic;
S_AXI_CTRL_AWREADY : out std_logic;
S_AXI_CTRL_AWADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_WVALID : in std_logic;
S_AXI_CTRL_WREADY : out std_logic;
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_BVALID : out std_logic;
S_AXI_CTRL_BREADY : in std_logic;
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
S_AXI_CTRL_ARVALID : in std_logic;
S_AXI_CTRL_ARREADY : out std_logic;
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
S_AXI_CTRL_RRESP : out std_logic_vector(1 downto 0);
S_AXI_CTRL_RVALID : out std_logic;
S_AXI_CTRL_RREADY : in std_logic;
-- BRAM Interface Signals (Port A)
BRAM_En_A : out std_logic;
BRAM_WE_A : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_A : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_A : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_A : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- BRAM Interface Signals (Port B)
BRAM_En_B : out std_logic;
BRAM_WE_B : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_Addr_B : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
BRAM_WrData_B : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
BRAM_RdData_B : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity full_axi;
-------------------------------------------------------------------------------
architecture implementation of full_axi is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant C_INT_ECC_WIDTH : integer := Int_ECC_Size (C_S_AXI_DATA_WIDTH);
-- Modify C_BRAM_ADDR_SIZE to be adjusted for BRAM data width
-- When BRAM data width = 32 bits, BRAM_Addr (1:0) = "00"
-- When BRAM data width = 64 bits, BRAM_Addr (2:0) = "000"
-- When BRAM data width = 128 bits, BRAM_Addr (3:0) = "0000"
-- When BRAM data width = 256 bits, BRAM_Addr (4:0) = "00000"
constant C_BRAM_ADDR_ADJUST_FACTOR : integer := log2 (C_S_AXI_DATA_WIDTH/8);
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
-- Internal AXI Signals
signal S_AXI_AWREADY_i : std_logic := '0';
signal S_AXI_ARREADY_i : std_logic := '0';
-- Internal BRAM Signals
signal BRAM_Addr_A_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_Addr_B_i : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal BRAM_En_A_i : std_logic := '0';
signal BRAM_En_B_i : std_logic := '0';
signal BRAM_WE_A_i : std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal BRAM_RdData_i : std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*(8+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
-- Internal ECC Signals
signal Enable_ECC : std_logic := '0';
signal FaultInjectClr : std_logic := '0'; -- Clear for Fault Inject Registers
signal CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Wr_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
--signal UE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
--signal CE_CounterReg_Inc : std_logic := '0'; -- Increment CE Counter Register
signal Wr_Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Wr_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal Rd_CE_Failing_We : std_logic := '0'; -- WE for CE Failing Registers
signal Rd_Sl_CE : std_logic := '0'; -- Correctable Error Flag
signal Rd_Sl_UE : std_logic := '0'; -- Uncorrectable Error Flag
signal FaultInjectData : std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
signal FaultInjectECC : std_logic_vector (C_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal FaultInjectECC_i : std_logic_vector (C_INT_ECC_WIDTH-1 downto 0) := (others => '0'); -- Specific to BRAM data width
signal Active_Wr : std_logic := '0';
signal BRAM_Addr_En : std_logic := '0';
signal Wr_BRAM_Addr_En : std_logic := '0';
signal Rd_BRAM_Addr_En : std_logic := '0';
-- Internal Arbitration Signals
signal Arb2AW_Active : std_logic := '0';
signal AW2Arb_Busy : std_logic := '0';
signal AW2Arb_Active_Clr : std_logic := '0';
signal AW2Arb_BVALID_Cnt : std_logic_vector (2 downto 0) := (others => '0');
signal Arb2AR_Active : std_logic := '0';
signal AR2Arb_Active_Clr : std_logic := '0';
signal WrChnl_BRAM_Addr_Rst : std_logic := '0';
signal WrChnl_BRAM_Addr_Ld_En : std_logic := '0';
signal WrChnl_BRAM_Addr_Inc : std_logic := '0';
signal WrChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal RdChnl_BRAM_Addr_Ld_En : std_logic := '0';
signal RdChnl_BRAM_Addr_Inc : std_logic := '0';
signal RdChnl_BRAM_Addr_Ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal bram_addr_int : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- *** BRAM Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: ADDR_SNG_PORT
-- Purpose: OR the BRAM_Addr outputs from each wr_chnl & rd_chnl
-- Only one write or read will be active at a time.
-- Ensure that ecah channel address is driven to '0' when not in use.
---------------------------------------------------------------------------
ADDR_SNG_PORT: if C_SINGLE_PORT_BRAM = 1 generate
signal sng_bram_addr_rst : std_logic := '0';
signal sng_bram_addr_ld_en : std_logic := '0';
signal sng_bram_addr_ld : std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) := (others => '0');
signal sng_bram_addr_inc : std_logic := '0';
begin
-- BRAM_Addr_A <= BRAM_Addr_A_i or BRAM_Addr_B_i;
-- BRAM_Addr_A <= BRAM_Addr_A_i when (Arb2AW_Active = '1') else BRAM_Addr_B_i;
-- BRAM_Addr_A <= BRAM_Addr_A_i when (Active_Wr = '1') else BRAM_Addr_B_i;
-- Insert mux on address counter control signals
sng_bram_addr_rst <= WrChnl_BRAM_Addr_Rst;
sng_bram_addr_ld_en <= WrChnl_BRAM_Addr_Ld_En or RdChnl_BRAM_Addr_Ld_En;
sng_bram_addr_ld <= RdChnl_BRAM_Addr_Ld when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Ld;
sng_bram_addr_inc <= RdChnl_BRAM_Addr_Inc when (Arb2AR_Active = '1') else WrChnl_BRAM_Addr_Inc;
I_ADDR_CNT: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (sng_bram_addr_rst = '1') then
bram_addr_int <= (others => '0');
elsif (sng_bram_addr_ld_en = '1') then
bram_addr_int <= sng_bram_addr_ld;
elsif (sng_bram_addr_inc = '1') then
bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12) <=
bram_addr_int (C_S_AXI_ADDR_WIDTH-1 downto 12);
bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR) <=
std_logic_vector (unsigned (bram_addr_int (11 downto C_BRAM_ADDR_ADJUST_FACTOR)) + 1);
end if;
end if;
end process I_ADDR_CNT;
BRAM_Addr_B <= (others => '0');
BRAM_En_A <= BRAM_En_A_i or BRAM_En_B_i;
-- BRAM_En_A <= BRAM_En_A_i when (Arb2AW_Active = '1') else BRAM_En_B_i;
BRAM_En_B <= '0';
BRAM_RdData_i <= BRAM_RdData_A; -- Assign read data port A
BRAM_WE_A <= BRAM_WE_A_i when (Arb2AW_Active = '1') else (others => '0');
-- v1.03a
-- Early register on WrData and WSTRB in wr_chnl. (Previous value was always cleared).
---------------------------------------------------------------------------
-- Generate: GEN_L_BRAM_ADDR
-- Purpose: Generate zeros on lower order address bits adjustable
-- based on BRAM data width.
---------------------------------------------------------------------------
GEN_L_BRAM_ADDR: for i in C_BRAM_ADDR_ADJUST_FACTOR-1 downto 0 generate
begin
BRAM_Addr_A (i) <= '0';
end generate GEN_L_BRAM_ADDR;
---------------------------------------------------------------------------
-- Generate: GEN_BRAM_ADDR
-- Purpose: Assign BRAM address output from address counter.
---------------------------------------------------------------------------
GEN_BRAM_ADDR: for i in C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR generate
begin
BRAM_Addr_A (i) <= bram_addr_int (i);
end generate GEN_BRAM_ADDR;
end generate ADDR_SNG_PORT;
---------------------------------------------------------------------------
-- Generate: ADDR_DUAL_PORT
-- Purpose: Assign each BRAM address when in a dual port controller
-- configuration.
---------------------------------------------------------------------------
ADDR_DUAL_PORT: if C_SINGLE_PORT_BRAM = 0 generate
begin
BRAM_Addr_A <= BRAM_Addr_A_i;
BRAM_Addr_B <= BRAM_Addr_B_i;
BRAM_En_A <= BRAM_En_A_i;
BRAM_En_B <= BRAM_En_B_i;
BRAM_WE_A <= BRAM_WE_A_i;
BRAM_RdData_i <= BRAM_RdData_B; -- Assign read data port B
end generate ADDR_DUAL_PORT;
BRAM_WrData_B <= (others => '0');
BRAM_WE_B <= (others => '0');
---------------------------------------------------------------------------
-- *** AXI-Lite ECC Register Output Signals ***
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Generate: GEN_NO_REGS
-- Purpose: Generate default values if ECC registers are disabled (or when
-- ECC is disabled).
-- Include both AXI-Lite default signal values & internal
-- core signal values.
---------------------------------------------------------------------------
GEN_NO_REGS: if (C_ECC = 0) generate
begin
S_AXI_CTRL_AWREADY <= '0';
S_AXI_CTRL_WREADY <= '0';
S_AXI_CTRL_BRESP <= (others => '0');
S_AXI_CTRL_BVALID <= '0';
S_AXI_CTRL_ARREADY <= '0';
S_AXI_CTRL_RDATA <= (others => '0');
S_AXI_CTRL_RRESP <= (others => '0');
S_AXI_CTRL_RVALID <= '0';
-- No fault injection
FaultInjectData <= (others => '0');
FaultInjectECC <= (others => '0');
-- Interrupt only enabled when ECC status/interrupt registers enabled
ECC_Interrupt <= '0';
ECC_UE <= '0';
Enable_ECC <= '0';
end generate GEN_NO_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_REGS
-- Purpose: Generate ECC register module when ECC is enabled and
-- ECC registers are enabled.
---------------------------------------------------------------------------
-- GEN_REGS: if (C_ECC = 1 and C_ENABLE_AXI_CTRL_REG_IF = 1) generate
-- For future implementation.
GEN_REGS: if (C_ECC = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_LITE_ECC_REG : entity work.lite_ecc_reg
generic map (
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
C_ECC_WIDTH => C_INT_ECC_WIDTH , -- ECC width specific to data width
C_FAULT_INJECT => C_FAULT_INJECT ,
C_CE_FAILING_REGISTERS => C_CE_FAILING_REGISTERS ,
C_UE_FAILING_REGISTERS => C_UE_FAILING_REGISTERS ,
C_ECC_STATUS_REGISTERS => C_ECC_STATUS_REGISTERS ,
C_ECC_ONOFF_REGISTER => C_ECC_ONOFF_REGISTER ,
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE ,
C_CE_COUNTER_WIDTH => C_CE_COUNTER_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
-- TBD
-- S_AXI_CTRL_AClk => S_AXI_CTRL_AClk , -- AXI-Lite clock
-- S_AXI_CTRL_AResetn => S_AXI_CTRL_AResetn ,
Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
-- Add AXI-Lite ECC Register Ports
AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
Enable_ECC => Enable_ECC ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => CE_Failing_We ,
CE_CounterReg_Inc => CE_Failing_We ,
Sl_CE => Sl_CE ,
Sl_UE => Sl_UE ,
BRAM_Addr_A => BRAM_Addr_A_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_B => BRAM_Addr_B_i (C_S_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR) , -- v1.03a
BRAM_Addr_En => BRAM_Addr_En ,
Active_Wr => Active_Wr ,
-- BRAM_RdData_A => BRAM_RdData_A (C_S_AXI_DATA_WIDTH-1 downto 0) ,
-- BRAM_RdData_B => BRAM_RdData_B (C_S_AXI_DATA_WIDTH-1 downto 0) ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC_i
);
BRAM_Addr_En <= Wr_BRAM_Addr_En or Rd_BRAM_Addr_En;
-- v1.03a
-- Add coverage tags for Wr_CE_Failing_We.
-- No testing on forcing errors with RMW and AXI write transfers.
--coverage off
CE_Failing_We <= Wr_CE_Failing_We or Rd_CE_Failing_We;
Sl_CE <= Wr_Sl_CE or Rd_Sl_CE;
Sl_UE <= Wr_Sl_UE or Rd_Sl_UE;
--coverage on
-------------------------------------------------------------------
-- Generate: GEN_32
-- Purpose: Add MSB '0' on ECC vector as only 7-bits wide in 32-bit.
-------------------------------------------------------------------
GEN_32: if C_S_AXI_DATA_WIDTH = 32 generate
begin
FaultInjectECC <= '0' & FaultInjectECC_i;
end generate GEN_32;
-------------------------------------------------------------------
-- Generate: GEN_NON_32
-- Purpose: Data widths match at 8-bits for ECC on 64-bit data.
-- And 9-bits for 128-bit data.
-------------------------------------------------------------------
GEN_NON_32: if C_S_AXI_DATA_WIDTH /= 32 generate
begin
FaultInjectECC <= FaultInjectECC_i;
end generate GEN_NON_32;
end generate GEN_REGS;
---------------------------------------------------------------------------
-- Generate: GEN_ARB
-- Purpose: Generate arbitration module when AXI4 is configured in
-- single port mode.
---------------------------------------------------------------------------
GEN_ARB: if (C_SINGLE_PORT_BRAM = 1) generate
begin
---------------------------------------------------------------------------
-- Instance: I_LITE_ECC_REG
-- Description: This module is for the AXI-Lite ECC registers.
--
-- Responsible for all AXI-Lite communication to the
-- ECC register bank. Provides user interface signals
-- to rest of AXI BRAM controller IP core for ECC functionality
-- and control.
-- Manages AXI-Lite write address (AW) and read address (AR),
-- write data (W), write response (B), and read data (R) channels.
---------------------------------------------------------------------------
I_SNG_PORT : entity work.sng_port_arb
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
S_AXI_AClk => S_AXI_AClk , -- AXI clock
S_AXI_AResetn => S_AXI_AResetn ,
AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY ,
AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY ,
Arb2AW_Active => Arb2AW_Active ,
AW2Arb_Busy => AW2Arb_Busy ,
AW2Arb_Active_Clr => AW2Arb_Active_Clr ,
AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt ,
Arb2AR_Active => Arb2AR_Active ,
AR2Arb_Active_Clr => AR2Arb_Active_Clr
);
end generate GEN_ARB;
---------------------------------------------------------------------------
-- Generate: GEN_DUAL
-- Purpose: Dual mode. AWREADY and ARREADY are generated from each
-- wr_chnl and rd_chnl module.
---------------------------------------------------------------------------
GEN_DUAL: if (C_SINGLE_PORT_BRAM = 0) generate
begin
S_AXI_AWREADY <= S_AXI_AWREADY_i;
S_AXI_ARREADY <= S_AXI_ARREADY_i;
Arb2AW_Active <= '0';
Arb2AR_Active <= '0';
end generate GEN_DUAL;
---------------------------------------------------------------------------
-- Instance: I_WR_CHNL
--
-- Description:
-- BRAM controller write channel logic. Controls AXI bus handshaking and
-- data flow on the write address (AW), write data (W) and
-- write response (B) channels.
--
-- BRAM signals are marked as output from Wr Chnl for future implementation
-- of merging Wr/Rd channel outputs to a single port of the BRAM module.
--
---------------------------------------------------------------------------
I_WR_CHNL : entity work.wr_chnl
generic map (
-- C_FAMILY => C_FAMILY ,
C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH ,
C_ECC_TYPE => C_ECC_TYPE -- v1.03a
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
AXI_AWID => S_AXI_AWID ,
AXI_AWADDR => S_AXI_AWADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_AWLEN => S_AXI_AWLEN ,
AXI_AWSIZE => S_AXI_AWSIZE ,
AXI_AWBURST => S_AXI_AWBURST ,
AXI_AWLOCK => S_AXI_AWLOCK ,
AXI_AWCACHE => S_AXI_AWCACHE ,
AXI_AWPROT => S_AXI_AWPROT ,
AXI_AWVALID => S_AXI_AWVALID ,
AXI_AWREADY => S_AXI_AWREADY_i ,
AXI_WDATA => S_AXI_WDATA ,
AXI_WSTRB => S_AXI_WSTRB ,
AXI_WLAST => S_AXI_WLAST ,
AXI_WVALID => S_AXI_WVALID ,
AXI_WREADY => S_AXI_WREADY ,
AXI_BID => S_AXI_BID ,
AXI_BRESP => S_AXI_BRESP ,
AXI_BVALID => S_AXI_BVALID ,
AXI_BREADY => S_AXI_BREADY ,
-- Arb Ports
Arb2AW_Active => Arb2AW_Active ,
AW2Arb_Busy => AW2Arb_Busy ,
AW2Arb_Active_Clr => AW2Arb_Active_Clr ,
AW2Arb_BVALID_Cnt => AW2Arb_BVALID_Cnt ,
Sng_BRAM_Addr_Rst => WrChnl_BRAM_Addr_Rst ,
Sng_BRAM_Addr_Ld_En => WrChnl_BRAM_Addr_Ld_En ,
Sng_BRAM_Addr_Ld => WrChnl_BRAM_Addr_Ld ,
Sng_BRAM_Addr_Inc => WrChnl_BRAM_Addr_Inc ,
Sng_BRAM_Addr => bram_addr_int ,
-- ECC Ports
Enable_ECC => Enable_ECC ,
BRAM_Addr_En => Wr_BRAM_Addr_En ,
FaultInjectClr => FaultInjectClr ,
CE_Failing_We => Wr_CE_Failing_We ,
Sl_CE => Wr_Sl_CE ,
Sl_UE => Wr_Sl_UE ,
Active_Wr => Active_Wr ,
FaultInjectData => FaultInjectData ,
FaultInjectECC => FaultInjectECC ,
BRAM_En => BRAM_En_A_i ,
-- BRAM_WE => BRAM_WE_A ,
-- 4/13
BRAM_WE => BRAM_WE_A_i ,
BRAM_WrData => BRAM_WrData_A ,
BRAM_RdData => BRAM_RdData_A ,
BRAM_Addr => BRAM_Addr_A_i
);
---------------------------------------------------------------------------
-- Instance: I_RD_CHNL
--
-- Description:
-- BRAM controller read channel logic. Controls all handshaking and data
-- flow on read address (AR) and read data (R) AXI channels.
--
-- BRAM signals are marked as Rd Chnl signals for future implementation
-- of merging Rd/Wr BRAM signals to a single BRAM port.
--
---------------------------------------------------------------------------
I_RD_CHNL : entity work.rd_chnl
generic map (
-- C_FAMILY => C_FAMILY ,
C_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
C_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_BRAM_ADDR_ADJUST_FACTOR => C_BRAM_ADDR_ADJUST_FACTOR ,
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
C_S_AXI_SUPPORTS_NARROW => C_S_AXI_SUPPORTS_NARROW_BURST ,
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
C_ECC => C_ECC ,
C_ECC_WIDTH => C_ECC_WIDTH ,
C_ECC_TYPE => C_ECC_TYPE -- v1.03a
)
port map (
S_AXI_AClk => S_AXI_ACLK ,
S_AXI_AResetn => S_AXI_ARESETN ,
AXI_ARID => S_AXI_ARID ,
AXI_ARADDR => S_AXI_ARADDR (C_S_AXI_ADDR_WIDTH-1 downto 0),
AXI_ARLEN => S_AXI_ARLEN ,
AXI_ARSIZE => S_AXI_ARSIZE ,
AXI_ARBURST => S_AXI_ARBURST ,
AXI_ARLOCK => S_AXI_ARLOCK ,
AXI_ARCACHE => S_AXI_ARCACHE ,
AXI_ARPROT => S_AXI_ARPROT ,
AXI_ARVALID => S_AXI_ARVALID ,
AXI_ARREADY => S_AXI_ARREADY_i ,
AXI_RID => S_AXI_RID ,
AXI_RDATA => S_AXI_RDATA ,
AXI_RRESP => S_AXI_RRESP ,
AXI_RLAST => S_AXI_RLAST ,
AXI_RVALID => S_AXI_RVALID ,
AXI_RREADY => S_AXI_RREADY ,
-- Arb Ports
Arb2AR_Active => Arb2AR_Active ,
AR2Arb_Active_Clr => AR2Arb_Active_Clr ,
Sng_BRAM_Addr_Ld_En => RdChnl_BRAM_Addr_Ld_En ,
Sng_BRAM_Addr_Ld => RdChnl_BRAM_Addr_Ld ,
Sng_BRAM_Addr_Inc => RdChnl_BRAM_Addr_Inc ,
Sng_BRAM_Addr => bram_addr_int ,
-- ECC Ports
Enable_ECC => Enable_ECC ,
BRAM_Addr_En => Rd_BRAM_Addr_En ,
CE_Failing_We => Rd_CE_Failing_We ,
Sl_CE => Rd_Sl_CE ,
Sl_UE => Rd_Sl_UE ,
BRAM_En => BRAM_En_B_i ,
BRAM_Addr => BRAM_Addr_B_i ,
BRAM_RdData => BRAM_RdData_i
);
end architecture implementation;
|
mit
|
2d9f44cec713d5501818d8abe16fc253
| 0.435402 | 4.117346 | false | false | false | false |
meaepeppe/FIR_ISA
|
VHDL/Reg_n.vhd
| 1 | 521 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY Reg_n IS
GENERIC(Nb: INTEGER :=9);
PORT(
CLK, RST_n, EN: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR(Nb-1 DOWNTO 0);
DOUT: OUT STD_LOGIC_VECTOR(Nb-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE beh_reg OF Reg_n IS
BEGIN
PROCESS(CLK, RST_n)
BEGIN
IF RST_n = '0' THEN
DOUT <= (OTHERS => '0');
ELSIF CLK'EVENT AND CLK = '1' THEN
IF EN = '1' THEN
DOUT <= DIN;
END IF;
END IF;
END PROCESS;
END beh_reg;
|
gpl-3.0
|
f13d2d3ede0710561a23e9fd7c188015
| 0.604607 | 2.553922 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/dist_mem_gen_v8_0/dist_mem_comps.vhd
| 1 | 16,444 |
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WA==
`protect end_protected
|
mit
|
03d3f7a208ecaf2dcf696a2603a48834
| 0.938032 | 1.88578 | false | false | false | false |
1995parham/FPGA-Homework
|
HW-1/src/p4-4/p4-4.vhd
| 1 | 1,076 |
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 03-03-2016
-- Module Name: p4-4.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity carry_look_ahead_adder is
generic (N : natural := 4);
port (a, b : in std_logic_vector(N - 1 downto 0);
s : out std_logic_vector(N - 1 downto 0);
cin : in std_logic;
cout : out std_logic);
end entity carry_look_ahead_adder;
architecture structural of carry_look_ahead_adder is
signal P, G : std_logic_vector(N - 1 downto 0);
signal C : std_logic_vector(N downto 0);
begin
C(0) <= cin;
cout <= C(N);
carry: for I in 1 to N generate
C(I) <= G(I - 1) or (P(I - 1) and C(I - 1));
end generate carry;
p_and_g: for I in 0 to N - 1 generate
P(I) <= a(I) xor b(I);
G(I) <= a(I) and b(I);
end generate p_and_g;
sum: for I in 0 to N - 1 generate
s(I) <= a(I) xor b(I) xor C(I);
end generate sum;
end architecture structural;
|
gpl-3.0
|
d1473b7d0f9d6cc694eed6ca8d9c6dae
| 0.530669 | 2.956044 | false | false | false | false |
6769/VHDL
|
Lab_4/Part2/IndependentSimulated/H24_Min60_Sec60_v2.vhd
| 1 | 3,413 |
library ieee;
use ieee.numeric_bit.all;
entity H24_Min60_Sec60_v2 is
port(Clk,Ldn,Reset:in bit;
Din :in unsigned(16 downto 1);
Qout:out unsigned(23 downto 0));
end entity H24_Min60_Sec60_v2;
architecture Behavior of H24_Min60_Sec60_v2 is
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 downto 0) is Q(3 downto 0);
alias Second_hig:unsigned(3 downto 0) is Q(7 downto 4);
alias Min_low: unsigned(3 downto 0) is Q(11 downto 8);
alias Min_hig: unsigned(3 downto 0) is Q(15 downto 12);
alias Hour_low: unsigned(3 downto 0) is Q(19 downto 16);
alias Hour_hig: unsigned(3 downto 0) is Q(23 downto 20);
--internal logic
-- signal second_count,min_count:integer range 0 to 59;--(63 downto 0);
-- signal hour_count: integer range 0 to 23;--(31 downto 0);
--signal carry_from_second,carry_from_min:bit;
constant CLs:unsigned(3 downto 0):="0000";
begin
Qout<=Q;
process(Clk,Ldn,Reset)
begin
if(Reset='0') then --min_count<=to_integer(Din(6 downto 1));hour_count<=to_integer(Din(13 downto 9));
Q<=(others=>'0');
elsif(Ldn='0' and Reset='1') then
Min_low <=Din(4 downto 1);
Min_hig <=Din(8 downto 5);
Hour_low<=Din(12 downto 9);
Hour_hig<=Din(16 downto 13);-- Q<=(others=>'0');
elsif(Clk'event and Clk='1') then
if(Second_low=9) then Second_low<=CLs;
if(Second_hig=5) then Second_hig<=CLs;
if(Min_low=9) then Min_low<=CLs;
if(Min_hig=5) then Min_hig<=CLs;
if(Hour_hig<2)then --09:59:59,19:59:59
if(Hour_low=9) then Hour_low<=CLs;Hour_hig<=Hour_hig+1;
else Hour_low<=Hour_low+1;
end if;
else --Hour_hig==2
if(Hour_low=3) then Hour_low<=CLs;Hour_hig<=CLs;
else Hour_low<=Hour_low+1;
end if;
end if;
else Min_hig<=Min_hig+1;
end if;
else Min_low<=Min_low+1;
end if;
else Second_hig<=Second_hig+1;
end if;
else Second_low<=Second_low+1;
end if;
-------------------------------------------old design,too much latchs...--------------------------
-- if(second_count=59) then second_count<=0;
-- if(min_count=59) then min_count<=0;
-- if(hour_count=23) then hour_count<=0;
-- else hour_count<=hour_count+1;
-- end if;
-- --carry_from_min<='1';
-- else min_count<=min_count+1;
-- end if;
-- --carry_from_second<='1';
-- else second_count<=second_count+1;
-- end if;
end if;
end process;
-- Second_low<=to_unsigned(second_count mod 10,4);
-- Second_hig<=to_unsigned(second_count/10,4);
-- Min_low<=to_unsigned(min_count mod 10,4);
-- Min_hig<=to_unsigned(min_count/10,4);
-- Hour_low<=to_unsigned(hour_count mod 10,4);
-- Hour_hig<=to_unsigned(hour_count/10,4);
end architecture Behavior;
|
gpl-2.0
|
e2be0b6f10dfd3348765f065c0f6c8b6
| 0.489013 | 3.646368 | false | false | false | false |
1995parham/FPGA-Homework
|
BCD/bcd_adder.vhd
| 1 | 1,731 |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bcd_adder is
port(
a: in std_logic_vector(3 downto 0);
b: in std_logic_vector(3 downto 0);
res: out std_logic_vector(3 downto 0);
cout: out std_logic_vector(3 downto 0)
);
end entity;
architecture struct of bcd_adder is
component n_bit_adder
generic(N: integer);
port(
a: in std_logic_vector(N - 1 downto 0);
b: in std_logic_vector(N - 1 downto 0);
cin: in std_logic;
res: out std_logic_vector(N - 1 downto 0);
cout: out std_logic
);
end component;
signal not_aligned_res: std_logic_vector(3 downto 0);
signal forced_aligned_res: std_logic_vector(3 downto 0);
signal cout_plus_1: std_logic_vector(3 downto 0);
signal fully_fake_signal_1: std_logic;
signal fully_fake_signal_2: std_logic;
signal readable_cout: std_logic;
begin
simple_adder: n_bit_adder generic map(4)
port map(a(3 downto 0), b, '0', not_aligned_res, readable_cout);
shifting_adder: n_bit_adder generic map(4)
port map(not_aligned_res, "0110", '0', forced_aligned_res, fully_fake_signal_1);
res <= forced_aligned_res when to_integer(unsigned(not_aligned_res)) > 9 else
forced_aligned_res when readable_cout = '1' else
not_aligned_res when readable_cout = '0' else
not_aligned_res when to_integer(unsigned(not_aligned_res)) < 10 else
"XXXX";
cout <= cout_plus_1 when to_integer(unsigned(not_aligned_res)) > 9 else
cout_plus_1 when readable_cout = '1' else
"XXXX";
end architecture;
|
gpl-3.0
|
1496af7e4f2217a184a8b5d7ef4820c0
| 0.601386 | 3.45509 | false | false | false | false |
Project-Bonfire/EHA
|
Test/credit_based/TB_Package_32_bit_credit_based_NI.vhd
| 3 | 16,691 |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function CX_GEN(current_address, network_size : integer) return integer;
procedure NI_control(network_size, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time;
signal clk: in std_logic;
-- NI configuration
signal reserved_address : in std_logic_vector(29 downto 0);
signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O
signal counter_address : in std_logic_vector(29 downto 0);
signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register
signal self_diagnosis_address : in std_logic_vector(29 downto 0);
-- NI signals
signal enable: out std_logic;
signal write_byte_enable: out std_logic_vector(3 downto 0);
signal address: out std_logic_vector(31 downto 2);
signal data_write: out std_logic_vector(31 downto 0);
signal data_read: in std_logic_vector(31 downto 0);
signal test: out std_logic_vector(31 downto 0));
end TB_Package;
package body TB_Package is
constant Header_type : std_logic_vector := "001";
constant Body_type : std_logic_vector := "010";
constant Tail_type : std_logic_vector := "100";
function CX_GEN(current_address, network_size : integer) return integer is
variable X, Y : integer := 0;
variable CN, CE, CW, CS : std_logic := '0';
variable CX : std_logic_vector(3 downto 0);
begin
X := current_address mod network_size;
Y := current_address / network_size;
if X /= 0 then
CW := '1';
end if;
if X /= network_size-1 then
CE := '1';
end if;
if Y /= 0 then
CN := '1';
end if;
if Y /= network_size-1 then
CS := '1';
end if;
CX := CS&CW&CE&CN;
return to_integer(unsigned(CX));
end CX_GEN;
procedure NI_control(network_size, frame_length, current_address, initial_delay, min_packet_size, max_packet_size: in integer;
finish_time: in time;
signal clk: in std_logic;
-- NI configuration
signal reserved_address : in std_logic_vector(29 downto 0);
signal flag_address : in std_logic_vector(29 downto 0) ; -- reserved address for the memory mapped I/O
signal counter_address : in std_logic_vector(29 downto 0);
signal reconfiguration_address : in std_logic_vector(29 downto 0); -- reserved address for reconfiguration register
signal self_diagnosis_address : in std_logic_vector(29 downto 0);
-- NI signals
signal enable: out std_logic;
signal write_byte_enable: out std_logic_vector(3 downto 0);
signal address: out std_logic_vector(31 downto 2);
signal data_write: out std_logic_vector(31 downto 0);
signal data_read: in std_logic_vector(31 downto 0);
signal test: out std_logic_vector(31 downto 0)) is
-- variables for random functions
constant DATA_WIDTH : integer := 32;
variable seed1 :positive := current_address+1;
variable seed2 :positive := current_address+1;
variable rand : real ;
--file handling variables
variable SEND_LINEVARIABLE : line;
file SEND_FILE : text;
variable RECEIVED_LINEVARIABLE : line;
file RECEIVED_FILE : text;
variable DIAGNOSIS_LINEVARIABLE : line;
file DIAGNOSIS_FILE : text;
-- receiving variables
variable receive_source_node, receive_destination_node, receive_packet_id, receive_counter, receive_packet_length: integer;
variable diagnosis_source_node, diagnosis_destination_node, diagnosis_packet_id, diagnosis_counter, diagnosis_packet_length: integer;
-- sending variables
variable send_destination_node, send_counter, send_id_counter: integer:= 0;
variable send_packet_length: integer:= 8;
type state_type is (Idle, Header_flit, Body_flit, Tail_flit);
variable state : state_type;
variable frame_starting_delay : integer:= 0;
variable frame_counter: integer:= 0;
variable diagnosis : std_logic := '0';
variable diagnosis_data: std_logic_vector(24 downto 0);
variable first_packet : boolean := True;
begin
file_open(DIAGNOSIS_FILE,"diagnosis.txt",WRITE_MODE);
file_open(RECEIVED_FILE,"received.txt",WRITE_MODE);
file_open(SEND_FILE,"sent.txt",WRITE_MODE);
enable <= '1';
state := Idle;
send_packet_length := min_packet_size;
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size-1)))/100);
wait until clk'event and clk ='0';
address <= reconfiguration_address;
wait until clk'event and clk ='0';
write_byte_enable <= "1111";
data_write <= "00000000000000000000" & std_logic_vector(to_unsigned(CX_GEN(current_address, network_size), 4)) & std_logic_vector(to_unsigned(60, 8));
wait until clk'event and clk ='0';
write_byte_enable <= "0000";
data_write <= (others =>'0');
while true loop
-- read the flag status
address <= flag_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
--flag register is organized like this:
-- .-------------------------------------------------.
-- | N2P_empty | P2N_full | self_diagnosis_flag | ...|
-- '-------------------------------------------------'
if data_read(29) = '1' then -- self diagnosis data is ready!
-- read the received self diagnosis data status
address <= self_diagnosis_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
test <= data_read;
write(DIAGNOSIS_LINEVARIABLE, string'("Self diagnosis of SHMU Node:"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
if data_read(0) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("Local input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if data_read(1) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("South input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if data_read(2) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("West input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if data_read(3) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("East input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if data_read(4) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("North input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
write(DIAGNOSIS_LINEVARIABLE, string'("--------------------------------"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
wait until clk'event and clk ='0';
elsif data_read(31) = '0' then -- N2P is not empty, can receive flit
-- read the received data status
address <= counter_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
-- read the received data status
address <= reserved_address;
write_byte_enable <= "0000";
wait until clk'event and clk ='0';
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001") then -- got header flit
receive_destination_node := to_integer(unsigned(data_read(14 downto 1)));
receive_source_node := to_integer(unsigned(data_read(28 downto 15)));
receive_counter := 1;
diagnosis := '0';
diagnosis_data := (others => '0');
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010") then -- got body flit
if receive_counter = 1 then
receive_packet_length := to_integer(unsigned(data_read(28 downto 15)));
receive_packet_id := to_integer(unsigned(data_read(14 downto 1)));
end if;
receive_counter := receive_counter+1;
if data_read(28 downto 13) = "0100011001000100" then
diagnosis := '1';
diagnosis_data(11 downto 0) := data_read(12 downto 1);
end if;
end if;
if (data_read(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100") then -- got tail flit
receive_counter := receive_counter+1;
if diagnosis = '0' then
write(RECEIVED_LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(receive_source_node) & " to: " & integer'image(receive_destination_node) & " length: "& integer'image(receive_packet_length) & " actual length: "& integer'image(receive_counter) & " id: "& integer'image(receive_packet_id));
writeline(RECEIVED_FILE, RECEIVED_LINEVARIABLE);
else
diagnosis_data(24 downto 12) := data_read(28 downto 16);
write(DIAGNOSIS_LINEVARIABLE, "Packet received at " & time'image(now) & " From: " & integer'image(receive_source_node) & " to: " & integer'image(receive_destination_node) & " length: "& integer'image(receive_packet_length) & " actual length: "& integer'image(receive_counter) & " id: "& integer'image(receive_packet_id) & " diagnosis: " );
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
write(DIAGNOSIS_LINEVARIABLE, to_bitvector(diagnosis_data));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
if diagnosis_data(0) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("Local input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if diagnosis_data(1) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("South input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if diagnosis_data(2) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("West input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if diagnosis_data(3) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("East input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
if diagnosis_data(4) = '1' then
write(DIAGNOSIS_LINEVARIABLE, string'("North input is link broken!"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
write(DIAGNOSIS_LINEVARIABLE, string'("--------------------------------"));
writeline(DIAGNOSIS_FILE, DIAGNOSIS_LINEVARIABLE);
end if;
end if;
elsif data_read(30) = '0' then -- P2N is not full, can send flit
if frame_counter >= frame_starting_delay then
if state = Idle and now < finish_time then
if frame_counter < frame_starting_delay+1 then
state := Header_flit;
send_counter := send_counter+1;
-- generating the destination address
uniform(seed1, seed2, rand);
send_destination_node := integer(rand*real((network_size**2)-1));
while (send_destination_node = current_address) loop
uniform(seed1, seed2, rand);
send_destination_node := integer(rand*real((network_size**2)-1));
end loop;
--generating the packet length
uniform(seed1, seed2, rand);
send_packet_length := integer((integer(rand*100.0)*frame_length)/300);
if (send_packet_length < min_packet_size) then
send_packet_length:=min_packet_size;
end if;
if (send_packet_length > max_packet_size) then
send_packet_length:=max_packet_size;
end if;
-- this is the header flit
address <= reserved_address;
write_byte_enable <= "1111";
data_write <= "0000" & std_logic_vector(to_unsigned(0, 14)) & std_logic_vector(to_unsigned(send_destination_node, 14));
write(SEND_LINEVARIABLE, "Packet generated at " & time'image(now) & " From " & integer'image(current_address) & " to " & integer'image(send_destination_node) & " with length: "& integer'image(send_packet_length) & " id: " & integer'image(send_id_counter));
writeline(SEND_FILE, SEND_LINEVARIABLE);
else
state := Idle;
end if;
elsif state = Header_flit then
-- first body flit
address <= reserved_address;
write_byte_enable <= "1111";
if first_packet = True then
data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14));
else
data_write <= "0000" & std_logic_vector(to_unsigned(send_packet_length, 14)) & std_logic_vector(to_unsigned(send_id_counter, 14));
end if;
send_counter := send_counter+1;
state := Body_flit;
elsif state = Body_flit then
-- rest of body flits
address <= reserved_address;
write_byte_enable <= "1111";
uniform(seed1, seed2, rand);
data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28));
send_counter := send_counter+1;
if send_counter = send_packet_length-1 then
state := Tail_flit;
else
state := Body_flit;
end if;
elsif state = Tail_flit then
-- tail flit
address <= reserved_address;
write_byte_enable <= "1111";
if first_packet = True then
data_write <= "0000" & "0000000000000000000000000000";
first_packet := False;
else
uniform(seed1, seed2, rand);
data_write <= "0000" & std_logic_vector(to_unsigned(integer(rand*1000.0), 28));
end if;
send_counter := 0;
state := Idle;
send_id_counter := send_id_counter + 1;
if send_id_counter = 16384 then
send_id_counter := 0;
end if;
end if;
end if;
frame_counter := frame_counter + 1;
if frame_counter = frame_length then
frame_counter := 0;
uniform(seed1, seed2, rand);
frame_starting_delay := integer(((integer(rand*100.0)*(frame_length - max_packet_size)))/100);
end if;
wait until clk'event and clk ='0';
end if;
end loop;
file_close(SEND_FILE);
file_close(RECEIVED_FILE);
file_close(DIAGNOSIS_FILE);
end NI_control;
end TB_Package;
|
gpl-3.0
|
7c231adf9e0cede953fa1170425f422c
| 0.54125 | 4.437915 | false | false | false | false |
zzhou007/161lab
|
newlab5/cpu_components.vhd
| 1 | 10,440 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity generic_register is
generic (
SIZE : natural := 4
);
port (
clk : in std_logic;
rst : in std_logic;
write_en : in std_logic;
data_in : in std_logic_vector(SIZE-1 downto 0);
data_out : out std_logic_vector(SIZE-1 downto 0)
);
end generic_register;
architecture Behavioral of generic_register is
begin
process (clk, rst)
begin
if rst = '1' then
data_out <= (others => '0');
elsif rising_edge(clk) then
if write_en = '1' then
data_out <= data_in;
end if;
end if;
end process;
end Behavioral;
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_2_1 is
generic(
SIZE : natural := 4
);
port (
select_in : in std_logic;
data_0_in : in std_logic_vector(SIZE-1 downto 0);
data_1_in : in std_logic_vector(SIZE-1 downto 0);
data_out : out std_logic_vector(SIZE-1 downto 0)
);
end mux_2_1;
architecture Behavioral of mux_2_1 is
begin
process (select_in, data_0_in, data_1_in)
begin
case select_in is
when '0' => data_out <= data_0_in;
when '1' => data_out <= data_1_in;
when others => data_out <= (others => '0');
end case;
end process;
end Behavioral;
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity cpu_registers is
port (
clk : in std_logic;
rst : in std_logic;
reg_write : in std_logic;
read_register_1 : in std_logic_vector(4 downto 0);
read_register_2 : in std_logic_vector(4 downto 0);
write_register : in std_logic_vector(4 downto 0);
write_data : in std_logic_vector(31 downto 0);
read_data_1 : out std_logic_vector(31 downto 0);
read_data_2 : out std_logic_vector(31 downto 0)
);
end cpu_registers;
architecture Behavioral of cpu_registers is
type REG_BUFF is array(0 to 31) of std_logic_vector(31 downto 0);
signal registers : REG_BUFF;
begin
process (rst, read_register_1, read_register_2)
begin
if rst = '1' then
read_data_1 <= (others => '0');
read_data_2 <= (others => '0');
else
read_data_1 <= registers(conv_integer(read_register_1));
read_data_2 <= registers(conv_integer(read_register_2));
end if;
end process;
process (rst, clk)
begin
if rst = '1' then
for i in 31 downto 0 loop
registers(i) <= (others => '0');
end loop;
elsif rising_edge(clk) then
if reg_write = '1' then
registers(conv_integer(write_register)) <= write_data;
end if;
end if;
end process;
end Behavioral;
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.cpu_constant_library.all;
entity alu is
port (
alu_control_in : in std_logic_vector(3 downto 0);
channel_a_in : in std_logic_vector(31 downto 0);
channel_b_in : in std_logic_vector(31 downto 0);
zero_out : out std_logic;
alu_result_out : out std_logic_vector(31 downto 0)
);
end alu;
architecture Behavioral of alu is
signal result_s : std_logic_vector(31 downto 0);
begin
process (alu_control_in, channel_a_in, channel_b_in)
begin
case alu_control_in is
--AND
when "0000" => result_s <= channel_a_in and channel_b_in;
--OR
when "0001" => result_s <= channel_a_in or channel_b_in;
--ADD
when "0010" => result_s <= channel_a_in + channel_b_in;
--SUB
when "0110" => result_s <= channel_a_in - channel_b_in;
--SLT
when "0111" => if channel_a_in < channel_b_in then
result_s <= (others => '1');
else
result_s <= (others => '0');
end if;
--NOR
when "1100" => result_s <= channel_a_in nor channel_b_in;
when others => result_s <= (others => '0');
end case;
end process;
alu_result_out <= result_s;
zero_out <= '1' when result_s = 0 else '0';
end Behavioral;
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
entity memory is
generic (
COE_FILE_NAME : string := "init.coe"
);
port (
clk : in std_logic;
rst : in std_logic;
instr_read_address : in std_logic_vector(7 downto 0);
instr_instruction : out std_logic_vector(31 downto 0);
data_mem_write : in std_logic;
data_address : in std_logic_vector(7 downto 0);
data_write_data : in std_logic_vector(31 downto 0);
data_read_data : out std_logic_vector(31 downto 0)
);
end memory;
architecture Behavioral of memory is
type MEMORY_BUFFER is array(255 downto 0) of std_logic_vector(31 downto 0);
signal buff : MEMORY_BUFFER;
begin
process (rst, clk, instr_read_address, data_mem_write, data_address, data_write_data, buff)
file coe_file : text;
variable coe_line : line;
variable coe_str : bit_vector(31 downto 0);
variable coe_status: file_open_status;
begin
if rst = '1' then
file_open(coe_status, coe_file, COE_FILE_NAME, read_mode);
if coe_status = OPEN_OK then
for i in 0 to 255 loop
if not endfile(coe_file) then
readline(coe_file, coe_line);
read(coe_line, coe_str);
buff(i) <= to_StdLogicVector(coe_str);
else
buff(i) <= (others => '0');
end if;
end loop;
file_close(coe_file);
else
report "Could not open COE file" severity warning;
for i in 0 to 255 loop
buff(i) <= (others => '0');
end loop;
end if;
instr_instruction <= (others => '0');
data_read_data <= (others => '0');
else
if rising_edge(clk) and data_mem_write = '1' then
buff(conv_integer(data_address)) <= data_write_data;
end if;
instr_instruction <= buff(conv_integer(instr_read_address));
data_read_data <= buff(conv_integer(data_address));
end if;
end process;
end Behavioral;
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.cpu_constant_library.all;
entity alu_control is
port (
alu_op : in std_logic_vector(1 downto 0);
instruction_5_0 : in std_logic_vector(5 downto 0);
alu_out : out std_logic_vector(3 downto 0)
);
end alu_control;
architecture Behavioral of alu_control is
begin
process (alu_op, instruction_5_0)
begin
if alu_op = "00" then -- LW or SW
alu_out <= ALU_ADD;
elsif alu_op = "01" then -- branch
alu_out <= ALU_SUBTRACT;
else -- R_Type
case instruction_5_0 is
when FUNCT_AND => alu_out <= ALU_AND;
when FUNCT_OR => alu_out <= ALU_OR;
when FUNCT_ADD => alu_out <= ALU_ADD;
when FUNCT_SUBTRACT => alu_out <= ALU_SUBTRACT;
when FUNCT_LESS_THAN => alu_out <= ALU_LESS_THAN;
when FUNCT_NOR => alu_out <= ALU_NOR;
when others => alu_out <= (others => '0');
end case;
end if;
end process;
end Behavioral;
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
-- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- -----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.cpu_constant_library.all;
entity control_unit is
port (
instr_op : in std_logic_vector(5 downto 0);
reg_dst : out std_logic;
branch : out std_logic;
mem_read : out std_logic;
mem_to_reg : out std_logic;
alu_op : out std_logic_vector(1 downto 0);
mem_write : out std_logic;
alu_src : out std_logic;
reg_write : out std_logic
);
end control_unit;
architecture Behavioral of control_unit is
begin
process (instr_op)
begin
reg_dst <= '0';
branch <= '0';
mem_read <= '0';
mem_to_reg <= '0';
alu_op <= (others => '0');
mem_write <= '0';
alu_src <= '0';
reg_write <= '0';
case instr_op is
when OPCODE_R_TYPE => reg_dst <= '1';
reg_write <= '1';
alu_op <= "10";
when OPCODE_ADDI => alu_src <= '1';
reg_write <= '1';
when OPCODE_LOAD_WORD => alu_src <= '1';
mem_to_reg <= '1';
reg_write <= '1';
mem_read <= '1';
when OPCODE_STORE_WORD => alu_src <= '1';
mem_write <= '1';
when OPCODE_BRANCH_EQ => branch <= '1';
alu_op <= "01";
when others =>
end case;
end process;
end Behavioral;
|
gpl-2.0
|
5c3c410dca14595bc1b38fe4492cbc99
| 0.461494 | 3.613707 | false | false | false | false |
Project-Bonfire/EHA
|
RTL/Router/credit_based/RTL/New_SHMU_on_Node/With_checkers/plasma.vhd
| 3 | 15,291 |
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0);
Reconfig_command : out std_logic
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
constant reserved_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant reserved_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant reserved_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = reserved_address) or (ram_address_late = reserved_flag_address)
or (ram_address_late = reserved_counter_address)) then
cpu_data_r <= ram_data_r_ni;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
u2_ram: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r);
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address, SHMU_address => 0)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
end; --architecture logic
|
gpl-3.0
|
e2a5b597e343fb5726732a75b5e7c9d4
| 0.531816 | 3.547796 | false | false | false | false |
sorgelig/SAMCoupe_MIST
|
sid/sid_ctrl.vhd
| 6 | 1,641 |
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sid_ctrl is
generic (
g_num_voices : natural := 8 );
port (
clock : in std_logic;
reset : in std_logic;
start_iter : in std_logic;
voice_osc : out unsigned(3 downto 0);
enable_osc : out std_logic );
end sid_ctrl;
architecture gideon of sid_ctrl is
signal voice_cnt : unsigned(3 downto 0);
signal enable : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
voice_cnt <= X"0";
enable <= '0';
elsif start_iter='1' then
voice_cnt <= X"0";
enable <= '1';
elsif voice_cnt = g_num_voices-1 then
voice_cnt <= X"0";
enable <= '0';
elsif enable='1' then
voice_cnt <= voice_cnt + 1;
enable <= '1';
end if;
end if;
end process;
voice_osc <= voice_cnt;
enable_osc <= enable;
end gideon;
|
gpl-2.0
|
c506fb495154eaf647bc95a2cf9cf56b
| 0.441804 | 4.229381 | false | false | false | false |
sunoc/vhdl-lz4-variation
|
z_old/sha1/sha_schedule.vhd
| 1 | 8,197 |
-----------------------------------------------------------------------------------
--! @file sha_schedule.vhd
--! @brief SHA-1/2 Prepare the Message Schedule Module.
--! SHA-1/2 用スケジュールモジュール.
--! @version 0.9.0
--! @date 2012/11/20
--! @author Ichiro Kawazome <[email protected]>
-----------------------------------------------------------------------------------
--
-- Copyright (C) 2012 Ichiro Kawazome
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------------
--! @brief SHA_SCHEDULE :
--! SHA-1/2用スケジュールモジュール.
-----------------------------------------------------------------------------------
entity SHA_SCHEDULE is
generic (
WORD_BITS : --! @brief SHA-1/2 WORD BITS :
--! １ワードのビット数を指定する.
--! * SHA-1/SHA-256の場合は32を設定する.
--! * SHA-512の場合は64を設定する.
integer := 32;
WORDS : --! @brief SHA-1/2 WORD SIZE :
--! １クロックで処理するワード数を指定する.
integer := 1;
INPUT_NUM : --! @brief INPUT END NUMBER :
integer := 16;
CALC_NUM : --! @brief CALC END NUMBER :
--! SHA-1では80, SHA-2では64
integer := 80;
END_NUM : --! @brief END OF NUMBER :
--! 最後のスケジューリング番号を指定する.
--! SHA-1では80, SHA-2では64
integer := 80
);
port (
-------------------------------------------------------------------------------
-- クロック&リセット信号
-------------------------------------------------------------------------------
CLK : --! @brief CLOCK :
--! クロック信号
in std_logic;
RST : --! @brief ASYNCRONOUSE RESET :
--! 非同期リセット信号.アクティブハイ.
in std_logic;
CLR : --! @brief SYNCRONOUSE RESET :
--! 同期リセット信号.アクティブハイ.
in std_logic;
-------------------------------------------------------------------------------
-- 入力側 I/F
-------------------------------------------------------------------------------
I_DONE : --! @brief INPUT MESSAGE DONE :
in std_logic;
I_VAL : --! @brief INPUT MESSAGE VALID :
in std_logic;
I_RDY : --! @brief INPUT MESSAGE READY :
out std_logic;
-------------------------------------------------------------------------------
-- 出力側 I/F
-------------------------------------------------------------------------------
O_INPUT : --! @brief INPUT MESSAGE PHASE :
out std_logic;
O_LAST : --! @brief LAST WORD OF MESSAGE :
out std_logic;
O_DONE : --! @brief MESSAGE DONE :
out std_logic;
O_NUM : --! @brief OUTPUT MESSAGE NUMBER :
out integer range 0 to END_NUM-1;
O_VAL : --! @brief OUTPUT MESSAGE VALID :
out std_logic;
O_RDY : --! @brief OUTPUT MESSAGE READY :
in std_logic
);
end SHA_SCHEDULE;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture RTL of SHA_SCHEDULE is
-------------------------------------------------------------------------------
-- 各種内部信号.
-------------------------------------------------------------------------------
signal state_count : integer range 0 to END_NUM-1;
signal input_state : boolean;
signal calc_state : boolean;
signal gap_state : boolean;
signal last_state : boolean;
signal done_pending : boolean;
begin
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
I_RDY <= '1' when (input_state and O_RDY = '1') else '0';
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
process (CLK, RST) begin
if (RST = '1') then
state_count <= 0;
elsif (CLK'event and CLK = '1') then
if (CLR = '1' or last_state) then
state_count <= 0;
elsif (input_state and I_VAL = '1' and O_RDY = '1') or
(calc_state and O_RDY = '1') or
(gap_state ) then
state_count <= state_count + WORDS;
end if;
end if;
end process;
input_state <= (state_count < INPUT_NUM);
calc_state <= (state_count >= INPUT_NUM and state_count < CALC_NUM);
gap_state <= (state_count >= CALC_NUM);
last_state <= (state_count = END_NUM-WORDS);
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
process (CLK, RST) begin
if (RST = '1') then
done_pending <= FALSE;
elsif (CLK'event and CLK = '1') then
if (CLR = '1') then
done_pending <= FALSE;
elsif (input_state and I_VAL = '1' and I_DONE = '1') then
done_pending <= TRUE;
elsif (last_state) then
done_pending <= FALSE;
end if;
end if;
end process;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
O_VAL <= '1' when (input_state and I_VAL = '1') or (calc_state) else '0';
O_NUM <= state_count;
O_INPUT <= '1' when (input_state) else '0';
O_LAST <= '1' when (state_count = CALC_NUM-WORDS) else '0';
O_DONE <= '1' when (last_state and done_pending) else '0';
end RTL;
|
gpl-3.0
|
b71311b222fd598b1c30b30589abbc69
| 0.388346 | 5.088501 | false | false | false | false |
sunoc/vhdl-lz4-variation
|
z_old/sha1/sha1_proc.vhd
| 1 | 20,326 |
-----------------------------------------------------------------------------------
--! @file sha1_proc.vhd
--! @brief SHA-1 Processing Module :
--! SHA-1用計算モジュール.
--! @version 0.9.0
--! @date 2012/12/20
--! @author Ichiro Kawazome <[email protected]>
-----------------------------------------------------------------------------------
--
-- Copyright (C) 2012 Ichiro Kawazome
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library IKWZM_SECURE_HASH;
use IKWZM_SECURE_HASH.SHA1.WORD_BITS;
use IKWZM_SECURE_HASH.SHA1.HASH_BITS;
-----------------------------------------------------------------------------------
--! @brief SHA1_PROC :
--! SHA-1用計算モジュール.
-----------------------------------------------------------------------------------
entity SHA1_PROC is
generic (
WORDS : --! @brief OUTPUT WORD SIZE :
--! 出力側のワード数を指定する(1ワードは32bit).
integer := 1;
PIPELINE : --! @brief PIPELINE MODE :
--! パイプラインモードを指定する.
--! * PIPELINE=1: K[t]+W[t]を一度レジスタで叩いてから演算する.
--! 少しだけ動作周波数が上がる可能性がある.
--! スループットは変わらないが、レイテンシーが１クロック遅
--! くなる.
integer := 1;
BLOCK_GAP : --! @brief BLOCK GAP CYCLE :
--! １ブロック(16word)処理する毎に挿入するギャップのサイクル
--! 数を指定する.
--! サイクル数分だけスループットが落ちるが、動作周波数が上が
--! る可能性がある.
integer := 0
);
port (
-------------------------------------------------------------------------------
-- クロック&リセット信号
-------------------------------------------------------------------------------
CLK : --! @brief CLOCK :
--! クロック信号
in std_logic;
RST : --! @brief ASYNCRONOUSE RESET :
--! 非同期リセット信号.アクティブハイ.
in std_logic;
CLR : --! @brief SYNCRONOUSE RESET :
--! 同期リセット信号.アクティブハイ.
in std_logic;
-------------------------------------------------------------------------------
-- 入力側 I/F
-------------------------------------------------------------------------------
M_DATA : --! @brief INPUT MESSAGE DATA :
in std_logic_vector(WORD_BITS*WORDS-1 downto 0);
M_DONE : --! @brief INPUT MESSAGE DONE :
in std_logic;
M_VAL : --! @brief INPUT MESSAGE VALID :
in std_logic;
M_RDY : --! @brief INPUT MESSAGE READY :
out std_logic;
-------------------------------------------------------------------------------
-- 出力側 I/F
-------------------------------------------------------------------------------
O_DATA : --! @brief OUTPUT WORD DATA :
out std_logic_vector(HASH_BITS-1 downto 0);
O_VAL : --! @brief OUTPUT WORD VALID :
out std_logic;
O_RDY : --! @brief OUTPUT WORD READY :
in std_logic
);
end SHA1_PROC;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library IKWZM_SECURE_HASH;
use IKWZM_SECURE_HASH.SHA1.all;
architecture RTL of SHA1_PROC is
-------------------------------------------------------------------------------
-- カウンタ(NUM)の最大値
-------------------------------------------------------------------------------
constant END_NUM : integer := ROUNDS + WORDS*BLOCK_GAP;
subtype NUM_TYPE is integer range 0 to END_NUM-1;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
type NUM_SEL_TYPE is (NUM_00_19, NUM_20_39, NUM_40_59, NUM_60_79);
type NUM_SEL_VECTOR is array (INTEGER range <>) of NUM_SEL_TYPE;
-------------------------------------------------------------------------------
-- スケジュール用の信号
-------------------------------------------------------------------------------
signal s_num : NUM_TYPE;
signal s_done : std_logic;
signal s_last : std_logic;
signal s_input : std_logic;
signal s_valid : std_logic;
signal s_ready : std_logic;
-------------------------------------------------------------------------------
-- W[t]
-------------------------------------------------------------------------------
signal w_num_sel : NUM_SEL_VECTOR(0 to WORDS-1);
signal w_done : std_logic;
signal w_last : std_logic;
signal w_valid : std_logic;
signal w_reg : WORD_VECTOR(0 to 15 );
signal w : WORD_VECTOR(0 to WORDS);
-------------------------------------------------------------------------------
-- W[t]+K[t]
-------------------------------------------------------------------------------
signal p_num_sel : NUM_SEL_VECTOR(0 to WORDS-1);
signal p_valid : std_logic;
signal p_done : std_logic;
signal p_last : std_logic;
signal p : WORD_VECTOR(0 to WORDS-1);
-------------------------------------------------------------------------------
-- a,b,c,d,e
-------------------------------------------------------------------------------
signal a : WORD_VECTOR(0 to WORDS);
signal b : WORD_VECTOR(0 to WORDS);
signal c : WORD_VECTOR(0 to WORDS);
signal d : WORD_VECTOR(0 to WORDS);
signal e : WORD_VECTOR(0 to WORDS);
signal a_reg : WORD_TYPE;
signal b_reg : WORD_TYPE;
signal c_reg : WORD_TYPE;
signal d_reg : WORD_TYPE;
signal e_reg : WORD_TYPE;
-------------------------------------------------------------------------------
-- H0,H1,H2,H3,H4
-------------------------------------------------------------------------------
signal h0 : WORD_TYPE;
signal h1 : WORD_TYPE;
signal h2 : WORD_TYPE;
signal h3 : WORD_TYPE;
signal h4 : WORD_TYPE;
-------------------------------------------------------------------------------
-- K[t]
-------------------------------------------------------------------------------
signal k : WORD_VECTOR(0 to WORDS);
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
signal o_last : std_logic;
signal o_done : std_logic;
signal o_valid : std_logic;
begin
-------------------------------------------------------------------------------
-- スケジューラ
-------------------------------------------------------------------------------
SCHEDULE: SHA_SCHEDULE
generic map (
WORD_BITS => WORD_BITS , --
WORDS => WORDS , --
INPUT_NUM => 16 , --
CALC_NUM => ROUNDS , --
END_NUM => END_NUM --
)
port map (
CLK => CLK , -- In :
RST => RST , -- In :
CLR => CLR , -- In :
I_DONE => M_DONE , -- In :
I_VAL => M_VAL , -- In :
I_RDY => M_RDY , -- Out :
O_NUM => s_num , -- Out :
O_INPUT => s_input , -- Out :
O_LAST => s_last , -- Out :
O_DONE => s_done , -- Out :
O_VAL => s_valid , -- Out :
O_RDY => s_ready -- In :
);
process (CLK, RST) begin
if (RST = '1') then s_ready <= '1';
elsif (CLK'event and CLK = '1') then
if (CLR = '1') then s_ready <= '1';
elsif (o_done = '1') then s_ready <= '1';
elsif (s_done = '1') then s_ready <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- W[t]の生成
-------------------------------------------------------------------------------
process (CLK, RST)
variable w_work : WORD_VECTOR(0 to 15 + WORDS);
begin
if (RST = '1') then
w_reg <= (others => WORD_NULL);
w_valid <= '0';
w_done <= '0';
w_last <= '0';
w_num_sel <= (others => NUM_00_19);
elsif (CLK'event and CLK = '1') then
if (CLR = '1') then
w_reg <= (others => WORD_NULL);
w_valid <= '0';
w_done <= '0';
w_last <= '0';
w_num_sel <= (others => NUM_00_19);
else
if (s_valid = '1') then
w_work(0 to 15) := w_reg(0 to 15);
for i in 0 to WORDS-1 loop
if (s_input = '1') then
w_work(16+i) := M_DATA(WORD_BITS*(i+1)-1 downto WORD_BITS*i);
else
w_work(16+i) := RotL(w_work(16+i-3 ) xor
w_work(16+i-8 ) xor
w_work(16+i-14) xor
w_work(16+i-16), 1);
end if;
end loop;
w_reg <= w_work(WORDS to WORDS+15);
end if;
w_valid <= s_valid;
w_done <= s_done;
w_last <= s_last;
for i in 0 to WORDS-1 loop
if ( 0 <= s_num + i and s_num + i < 20) then
w_num_sel(i) <= NUM_00_19;
elsif (20 <= s_num + i and s_num + i < 40) then
w_num_sel(i) <= NUM_20_39;
elsif (40 <= s_num + i and s_num + i < 60) then
w_num_sel(i) <= NUM_40_59;
else
w_num_sel(i) <= NUM_60_79;
end if;
end loop;
end if;
end if;
end process;
W_GEN: for i in 0 to WORDS-1 generate
w(i) <= w_reg(16-WORDS+i);
end generate;
-------------------------------------------------------------------------------
-- K[t]の生成
-------------------------------------------------------------------------------
K_GEN: for i in 0 to WORDS-1 generate
k(i) <= K0 when (w_num_sel(i) = NUM_00_19) else
K1 when (w_num_sel(i) = NUM_20_39) else
K2 when (w_num_sel(i) = NUM_40_59) else
K3;
end generate;
-------------------------------------------------------------------------------
-- K[t]+W[t]の生成
-------------------------------------------------------------------------------
P_TRUE: if (PIPELINE > 0) generate
process (CLK, RST) begin
if (RST = '1') then
p_num_sel <= (others => NUM_00_19);
p_valid <= '0';
p_done <= '0';
p_last <= '0';
p <= (others => WORD_NULL);
elsif (CLK'event and CLK = '1') then
if (CLR = '1') then
p_num_sel <= (others => NUM_00_19);
p_valid <= '0';
p_done <= '0';
p_last <= '0';
p <= (others => WORD_NULL);
else
p_num_sel <= w_num_sel;
p_valid <= w_valid;
p_done <= w_done;
p_last <= w_last;
for i in 0 to WORDS-1 loop
p(i) <= std_logic_vector(unsigned(k(i))+unsigned(w(i)));
end loop;
end if;
end if;
end process;
end generate;
P_FALSE: if (PIPELINE = 0) generate
p_num_sel <= w_num_sel;
p_valid <= w_valid;
p_last <= w_last;
p_done <= w_done;
P_GEN: for i in 0 to WORDS-1 generate
p(i) <= std_logic_vector(unsigned(k(i))+unsigned(w(i)));
end generate;
end generate;
-------------------------------------------------------------------------------
-- a,b,c,d,e の計算
-------------------------------------------------------------------------------
a(0) <= a_reg;
b(0) <= b_reg;
c(0) <= c_reg;
d(0) <= d_reg;
e(0) <= e_reg;
CALC: for i in 0 to WORDS-1 generate
signal a0 : unsigned(WORD_BITS-1 downto 0);
signal a1 : unsigned(WORD_BITS-1 downto 0);
signal a2 : unsigned(WORD_BITS-1 downto 0);
signal a3 : unsigned(WORD_BITS-1 downto 0);
begin
a0 <= unsigned(RotL(a(i),5));
a1 <= unsigned(Ch (b(i),c(i),d(i))) when (p_num_sel(i) = NUM_00_19) else
unsigned(Parity(b(i),c(i),d(i))) when (p_num_sel(i) = NUM_20_39) else
unsigned(Maj (b(i),c(i),d(i))) when (p_num_sel(i) = NUM_40_59) else
unsigned(Parity(b(i),c(i),d(i)));
a2 <= unsigned(e(i));
a3 <= unsigned(p(i));
a(i+1) <= std_logic_vector(a0+a1+a2+a3);
b(i+1) <= a(i);
c(i+1) <= RotL(B(i),30);
d(i+1) <= c(i);
e(i+1) <= d(i);
end generate;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
process (CLK, RST)
variable h0_next : WORD_TYPE;
variable h1_next : WORD_TYPE;
variable h2_next : WORD_TYPE;
variable h3_next : WORD_TYPE;
variable h4_next : WORD_TYPE;
begin
if (RST = '1') then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
a_reg <= H0_INIT;
b_reg <= H1_INIT;
c_reg <= H2_INIT;
d_reg <= H3_INIT;
e_reg <= H4_INIT;
elsif (CLK'event and CLK = '1') then
if (CLR = '1') then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
a_reg <= H0_INIT;
b_reg <= H1_INIT;
c_reg <= H2_INIT;
d_reg <= H3_INIT;
e_reg <= H4_INIT;
elsif (o_done = '1') then
h0 <= H0_INIT;
h1 <= H1_INIT;
h2 <= H2_INIT;
h3 <= H3_INIT;
h4 <= H4_INIT;
a_reg <= H0_INIT;
b_reg <= H1_INIT;
c_reg <= H2_INIT;
d_reg <= H3_INIT;
e_reg <= H4_INIT;
elsif (p_last = '1' and BLOCK_GAP = 0) then
h0_next := std_logic_vector(unsigned(h0) + unsigned(a(WORDS)));
h1_next := std_logic_vector(unsigned(h1) + unsigned(b(WORDS)));
h2_next := std_logic_vector(unsigned(h2) + unsigned(c(WORDS)));
h3_next := std_logic_vector(unsigned(h3) + unsigned(d(WORDS)));
h4_next := std_logic_vector(unsigned(h4) + unsigned(e(WORDS)));
a_reg <= h0_next;
b_reg <= h1_next;
c_reg <= h2_next;
d_reg <= h3_next;
e_reg <= h4_next;
h0 <= h0_next;
h1 <= h1_next;
h2 <= h2_next;
h3 <= h3_next;
h4 <= h4_next;
elsif (o_last = '1' and BLOCK_GAP > 0) then
h0_next := std_logic_vector(unsigned(h0) + unsigned(a_reg));
h1_next := std_logic_vector(unsigned(h1) + unsigned(b_reg));
h2_next := std_logic_vector(unsigned(h2) + unsigned(c_reg));
h3_next := std_logic_vector(unsigned(h3) + unsigned(d_reg));
h4_next := std_logic_vector(unsigned(h4) + unsigned(e_reg));
h0 <= h0_next;
h1 <= h1_next;
h2 <= h2_next;
h3 <= h3_next;
h4 <= h4_next;
a_reg <= h0_next;
b_reg <= h1_next;
c_reg <= h2_next;
d_reg <= h3_next;
e_reg <= h4_next;
elsif (p_valid = '1') then
a_reg <= a(a'high);
b_reg <= b(b'high);
c_reg <= c(c'high);
d_reg <= d(d'high);
e_reg <= e(e'high);
end if;
end if;
end process;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
process (CLK, RST) begin
if (RST = '1') then
o_last <= '0';
o_valid <= '0';
elsif (CLK'event and CLK = '1') then
if (CLR = '1') then
o_last <= '0';
o_valid <= '0';
else
o_last <= p_last;
if (o_done = '1') then
o_valid <= '0';
elsif (p_done = '1') then
o_valid <= '1';
end if;
end if;
end if;
end process;
O_DATA <= h0 & h1 & h2 & h3 & h4;
O_VAL <= o_valid;
o_done <= '1' when (o_valid = '1' and O_RDY = '1') else '0';
end RTL;
|
gpl-3.0
|
de749898f5cc982283883212a1b2a617
| 0.341249 | 4.142319 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/CPU/MEM_WB.vhd
| 1 | 2,245 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:28:10 11/21/2013
-- Design Name:
-- Module Name: MEM_WB - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MEM_WB is
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
WriteIn : in STD_LOGIC;
MemtoRegInput : in STD_LOGIC;
MemtoRegOutput : out STD_LOGIC;
RegWriteInput: in STD_LOGIC;
RegWriteOutput: out STD_LOGIC;
AluResultInput : in STD_LOGIC_VECTOR (15 downto 0);
AluResultOutput : out STD_LOGIC_VECTOR (15 downto 0);
MemResultInput: in STD_LOGIC_VECTOR (15 downto 0);
MemResultOutput: out STD_LOGIC_VECTOR (15 downto 0);
RegReadInput1 : in STD_LOGIC_VECTOR (3 downto 0);
RegReadInput2 : in STD_LOGIC_VECTOR (3 downto 0);
RegWriteToInput : in STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput1 : out STD_LOGIC_VECTOR (3 downto 0);
RegReadOutput2 : out STD_LOGIC_VECTOR (3 downto 0);
RegWriteToOutput : out STD_LOGIC_VECTOR (3 downto 0);
retinput: in std_logic;
retoutput: out std_logic
);
end MEM_WB;
architecture Behavioral of MEM_WB is
begin
process (rst, clk, WriteIn)
begin
if (rst = '0') then
MemtoRegOutput <= '0';
RegWriteOutput <= '0';
retoutput <= '0';
elsif (clk'event and clk = '1') then
if (WriteIn = '1') then
MemtoRegOutput <= MemtoRegInput;
RegWriteOutput <= RegWriteInput;
AluResultOutput <= AluResultInput;
MemResultOutput <= MemResultInput;
RegReadOutput1 <= RegReadInput1;
RegReadOutput2 <= RegReadInput2;
RegWriteToOutput <= RegWriteToInput;
retoutput <= retinput;
end if;
end if;
end process;
end Behavioral;
|
mit
|
7eb42b3190e099b7894ecf63e61a8da0
| 0.638753 | 3.603531 | false | false | false | false |
frankvanbever/MIPS_processor
|
data_memory.vhd
| 1 | 3,669 |
-- Frank Vanbever 06/03/13
-------------------------------------------------------------------------------
--! @file
--! @brief Data Memory implementation for a MIPS processor
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
--! Data memory implementation for a MIPS processor. Allows storage for 64 words currently.
-------------------------------------------------------------------------------
entity data_memory is
port(
-- input signals
clk : in std_logic; -- clock
-- control signals
--! Write enable signal. Warning: mutually exclusive with MemRead!
MemWrite : in std_logic;
--! Read enable signal. Warning: mutually exclusive with MemWrite!
MemRead : in std_logic;
-- input vectors
--! Adress from which the value should be read or to which it should be
--! written
adress : in std_logic_vector(31 downto 0);
--! Data to be written at the given adress in write mode
write_data : in std_logic_vector(31 downto 0);
--! Data to be read from the given adress in read mode
read_data : out std_logic_vector(31 downto 0)
);
end data_memory;
-------------------------------------------------------------------------------
--! @brief The architecture of the data memory is based on an array of 64
--! 32-bit words
--! @detailed MemWrite and MemRead are mutually exclusive, only one can be 1 at
--! a time. This is a problem that needs to be adressed.
-------------------------------------------------------------------------------
architecture behavioral of data_memory is
subtype word is std_logic_vector(31 downto 0);
type memory_array is array (0 to 63) of word;
shared variable dataMem : memory_array :=
(X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000",
X"00000000");
begin --behavioral
---------------------------------------------------------------
--! process that governs reading from or writing to the memory.
--! reads or writes values accordingly.
---------------------------------------------------------------
data_mem_proc : process(MemRead,MemWrite,write_data,adress)
begin
-- trick to avoid undefined address error(should give no problems,only delays the read/write untill adress is defined well)
if(conv_integer(adress)<63)then
if (MemRead = '1') and (MemWrite = '0') then
read_data <= dataMem(conv_integer(adress));
elsif (MemRead = '0') and (MemWrite = '1') then
dataMem(conv_integer(adress)) := write_data;
end if;
end if;
end process;
end behavioral;
|
mit
|
21d9a0e88e5dbc9b655218c991255158
| 0.545108 | 4.131757 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/CPU/RiskChecker.vhd
| 1 | 1,593 |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:33:18 11/21/2013
-- Design Name:
-- Module Name: RiskChecker - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.Common.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RiskChecker is
Port(
PCWrite : out STD_LOGIC;
IFIDWrite : out STD_LOGIC;
ControlRst : out STD_LOGIC;
IDEX_MemWrite : in STD_LOGIC;
IDEX_W : in Int4;
IFID_R1 : in Int4;
IFID_R2 : in Int4;
op : in Int5;
forwardBEQZ: out std_logic_vector(1 downto 0);
EXMEM_W : in Int4
);
end RiskChecker;
architecture Behavioral of RiskChecker is
begin
-- TODO
PCWrite <= '1';
IFIDWrite <= '1';
ControlRst <= '1';
process(op, IDEX_W, IFID_R1)
begin
forwardBEQZ <= "00";
if ((op = "11010" or op = "11011") and IDEX_W /= Zero_reg and IDEX_W = IFID_R1) then
forwardBEQZ <= "01";
elsif ((op = "11010" or op = "11011") and EXMEM_W /= Zero_reg and EXMEM_W = IFID_R1) then
forwardBEQZ <= "10";
end if;
end process;
end Behavioral;
|
mit
|
74c10d74ae772fc37941c61aca4d1789
| 0.595731 | 3.291322 | false | false | false | false |
fupolarbear/THU-Class-CO-makecomputer
|
src/VGA/ipcore_dir/fifo_mem/simulation/fifo_mem_tb.vhd
| 2 | 4,517 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: fifo_mem_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY fifo_mem_tb IS
END ENTITY;
ARCHITECTURE fifo_mem_tb_ARCH OF fifo_mem_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
fifo_mem_synth_inst:ENTITY work.fifo_mem_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
mit
|
7684f078cea6d5020a1dd181e1427490
| 0.615231 | 4.581136 | false | false | false | false |
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/checkbit_handler_64.vhd
| 7 | 78,226 |
-------------------------------------------------------------------------------
-- checkbit_handler_64.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: checkbit_handler_64.vhd
--
-- Description: Generates the ECC checkbits for the input vector of
-- 64-bit data widths.
--
-- VHDL-Standard: VHDL'93/02
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
--
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity checkbit_handler_64 is
generic (
C_ENCODE : boolean := true;
C_REG : boolean := false;
C_USE_LUT6 : boolean := true);
port (
Clk : in std_logic;
DataIn : in std_logic_vector (63 downto 0);
CheckIn : in std_logic_vector (7 downto 0);
CheckOut : out std_logic_vector (7 downto 0);
Syndrome : out std_logic_vector (7 downto 0);
Syndrome_7 : out std_logic_vector (11 downto 0);
Syndrome_Chk : in std_logic_vector (0 to 7);
Enable_ECC : in std_logic;
UE_Q : in std_logic;
CE_Q : in std_logic;
UE : out std_logic;
CE : out std_logic
);
end entity checkbit_handler_64;
library unisim;
use unisim.vcomponents.all;
-- library axi_bram_ctrl_v1_02_a;
-- use axi_bram_ctrl_v1_02_a.all;
architecture IMP of checkbit_handler_64 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
component XOR18 is
generic (
C_USE_LUT6 : boolean);
port (
InA : in std_logic_vector(0 to 17);
res : out std_logic);
end component XOR18;
component Parity is
generic (
C_USE_LUT6 : boolean;
C_SIZE : integer);
port (
InA : in std_logic_vector(0 to C_SIZE - 1);
Res : out std_logic);
end component Parity;
-- component ParityEnable
-- generic (
-- C_USE_LUT6 : boolean;
-- C_SIZE : integer);
-- port (
-- InA : in std_logic_vector(0 to C_SIZE - 1);
-- Enable : in std_logic;
-- Res : out std_logic);
-- end component ParityEnable;
signal data_chk0 : std_logic_vector(0 to 34);
signal data_chk1 : std_logic_vector(0 to 34);
signal data_chk2 : std_logic_vector(0 to 34);
signal data_chk3 : std_logic_vector(0 to 30);
signal data_chk4 : std_logic_vector(0 to 30);
signal data_chk5 : std_logic_vector(0 to 30);
signal data_chk6 : std_logic_vector(0 to 6);
signal data_chk6_xor : std_logic;
-- signal data_chk7_a : std_logic_vector(0 to 17);
-- signal data_chk7_b : std_logic_vector(0 to 17);
-- signal data_chk7_i : std_logic;
-- signal data_chk7_xor : std_logic;
-- signal data_chk7_i_xor : std_logic;
-- signal data_chk7_a_xor : std_logic;
-- signal data_chk7_b_xor : std_logic;
begin -- architecture IMP
-- Add bits for 64-bit ECC
-- 0 <= 0 1 3 4 6 8 10 11 13 17 19 21 23 25 26 28 30
-- 32 34 36 38 40 42 44 46 48 50 52 54 56 57 59 61 63
data_chk0 <= DataIn(0) & DataIn(1) & DataIn(3) & DataIn(4) & DataIn(6) & DataIn(8) & DataIn(10) &
DataIn(11) & DataIn(13) & DataIn(15) & DataIn(17) & DataIn(19) & DataIn(21) &
DataIn(23) & DataIn(25) & DataIn(26) & DataIn(28) & DataIn(30) &
DataIn(32) & DataIn(34) & DataIn(36) & DataIn(38) & DataIn(40) &
DataIn(42) & DataIn(44) & DataIn(46) & DataIn(48) & DataIn(50) &
DataIn(52) & DataIn(54) & DataIn(56) & DataIn(57) & DataIn(59) &
DataIn(61) & DataIn(63) ;
-- 18 + 17 = 35
---------------------------------------------------------------------------
-- 1 <= 0 2 3 5 6 9 10 12 13 16 17 20 21 24 25 27 28 31
-- 32 35 36 39 40 43 44 47 48 51 52 55 56 58 59 62 63
data_chk1 <= DataIn(0) & DataIn(2) & DataIn(3) & DataIn(5) & DataIn(6) & DataIn(9) & DataIn(10) &
DataIn(12) & DataIn(13) & DataIn(16) & DataIn(17) & DataIn(20) & DataIn(21) &
DataIn(24) & DataIn(25) & DataIn(27) & DataIn(28) & DataIn(31) &
DataIn(32) & DataIn(35) & DataIn(36) & DataIn(39) & DataIn(40) &
DataIn(43) & DataIn(44) & DataIn(47) & DataIn(48) & DataIn(51) &
DataIn(52) & DataIn(55) & DataIn(56) & DataIn(58) & DataIn(59) &
DataIn(62) & DataIn(63) ;
-- 18 + 17 = 35
---------------------------------------------------------------------------
-- 2 <= 1 2 3 7 8 9 10 14 15 16 17 22 23 24 25 29 30 31
-- 32 37 38 39 40 45 46 47 48 53 54 55 56 60 61 62 63
data_chk2 <= DataIn(1) & DataIn(2) & DataIn(3) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) & DataIn(29) & DataIn(30) & DataIn(31) &
DataIn(32) & DataIn(37) & DataIn(38) & DataIn(39) & DataIn(40) & DataIn(45) &
DataIn(46) & DataIn(47) & DataIn(48) & DataIn(53) & DataIn(54) & DataIn(55) &
DataIn(56) & DataIn(60) & DataIn(61) & DataIn(62) & DataIn(63) ;
-- 18 + 17 = 35
---------------------------------------------------------------------------
-- 3 <= 4 5 6 7 8 9 10 18 19 20 21 22 23 24 25
-- 33 34 35 36 37 38 39 40 49 50 51 52 53 54 55 56
data_chk3 <= DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) & DataIn(8) & DataIn(9) & DataIn(10) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) &
DataIn(33) & DataIn(34) & DataIn(35) & DataIn(36) & DataIn(37) & DataIn(38) & DataIn(39) &
DataIn(40) & DataIn(49) & DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) &
DataIn(55) & DataIn(56) ;
-- 15 + 16 = 31
---------------------------------------------------------------------------
-- 4 <= 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
-- 41-56
data_chk4 <= DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) & DataIn(15) & DataIn(16) & DataIn(17) &
DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) & DataIn(22) & DataIn(23) & DataIn(24) &
DataIn(25) &
DataIn(41) & DataIn(42) & DataIn(43) & DataIn(44) & DataIn(45) & DataIn(46) & DataIn(47) &
DataIn(48) & DataIn(49) & DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) &
DataIn(55) & DataIn(56) ;
-- 15 + 16 = 31
---------------------------------------------------------------------------
-- 5 <= 26 - 31
-- 32 - 56
data_chk5 <= DataIn(26) & DataIn(27) & DataIn(28) & DataIn(29) & DataIn(30) & DataIn(31) &
DataIn(32) & DataIn(33) & DataIn(34) & DataIn(35) & DataIn(36) & DataIn(37) &
DataIn(38) & DataIn(39) & DataIn(40) & DataIn(41) & DataIn(42) & DataIn(43) &
DataIn(44) & DataIn(45) & DataIn(46) & DataIn(47) & DataIn(48) & DataIn(49) &
DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) & DataIn(55) &
DataIn(56) ;
-- 18 + 13 = 31
---------------------------------------------------------------------------
-- New additional checkbit for 64-bit data
-- 6 <= 57 - 63
data_chk6 <= DataIn(57) & DataIn(58) & DataIn(59) & DataIn(60) & DataIn(61) & DataIn(62) &
DataIn(63) ;
-- Encode bits for writing data
Encode_Bits : if (C_ENCODE) generate
-- signal data_chk0_i : std_logic_vector(0 to 17);
-- signal data_chk0_xor : std_logic;
-- signal data_chk0_i_xor : std_logic;
-- signal data_chk1_i : std_logic_vector(0 to 17);
-- signal data_chk1_xor : std_logic;
-- signal data_chk1_i_xor : std_logic;
-- signal data_chk2_i : std_logic_vector(0 to 17);
-- signal data_chk2_xor : std_logic;
-- signal data_chk2_i_xor : std_logic;
-- signal data_chk3_i : std_logic_vector(0 to 17);
-- signal data_chk3_xor : std_logic;
-- signal data_chk3_i_xor : std_logic;
-- signal data_chk4_i : std_logic_vector(0 to 17);
-- signal data_chk4_xor : std_logic;
-- signal data_chk4_i_xor : std_logic;
-- signal data_chk5_i : std_logic_vector(0 to 17);
-- signal data_chk5_xor : std_logic;
-- signal data_chk5_i_xor : std_logic;
-- signal data_chk6_i : std_logic;
-- signal data_chk0_xor_reg : std_logic;
-- signal data_chk0_i_xor_reg : std_logic;
-- signal data_chk1_xor_reg : std_logic;
-- signal data_chk1_i_xor_reg : std_logic;
-- signal data_chk2_xor_reg : std_logic;
-- signal data_chk2_i_xor_reg : std_logic;
-- signal data_chk3_xor_reg : std_logic;
-- signal data_chk3_i_xor_reg : std_logic;
-- signal data_chk4_xor_reg : std_logic;
-- signal data_chk4_i_xor_reg : std_logic;
-- signal data_chk5_xor_reg : std_logic;
-- signal data_chk5_i_xor_reg : std_logic;
-- signal data_chk6_i_reg : std_logic;
-- signal data_chk7_a_xor_reg : std_logic;
-- signal data_chk7_b_xor_reg : std_logic;
-- Checkbit (0)
signal data_chk0_a : std_logic_vector (0 to 5);
signal data_chk0_b : std_logic_vector (0 to 5);
signal data_chk0_c : std_logic_vector (0 to 5);
signal data_chk0_d : std_logic_vector (0 to 5);
signal data_chk0_e : std_logic_vector (0 to 5);
signal data_chk0_f : std_logic_vector (0 to 4);
signal data_chk0_a_xor : std_logic;
signal data_chk0_b_xor : std_logic;
signal data_chk0_c_xor : std_logic;
signal data_chk0_d_xor : std_logic;
signal data_chk0_e_xor : std_logic;
signal data_chk0_f_xor : std_logic;
signal data_chk0_a_xor_reg : std_logic;
signal data_chk0_b_xor_reg : std_logic;
signal data_chk0_c_xor_reg : std_logic;
signal data_chk0_d_xor_reg : std_logic;
signal data_chk0_e_xor_reg : std_logic;
signal data_chk0_f_xor_reg : std_logic;
-- Checkbit (1)
signal data_chk1_a : std_logic_vector (0 to 5);
signal data_chk1_b : std_logic_vector (0 to 5);
signal data_chk1_c : std_logic_vector (0 to 5);
signal data_chk1_d : std_logic_vector (0 to 5);
signal data_chk1_e : std_logic_vector (0 to 5);
signal data_chk1_f : std_logic_vector (0 to 4);
signal data_chk1_a_xor : std_logic;
signal data_chk1_b_xor : std_logic;
signal data_chk1_c_xor : std_logic;
signal data_chk1_d_xor : std_logic;
signal data_chk1_e_xor : std_logic;
signal data_chk1_f_xor : std_logic;
signal data_chk1_a_xor_reg : std_logic;
signal data_chk1_b_xor_reg : std_logic;
signal data_chk1_c_xor_reg : std_logic;
signal data_chk1_d_xor_reg : std_logic;
signal data_chk1_e_xor_reg : std_logic;
signal data_chk1_f_xor_reg : std_logic;
-- Checkbit (2)
signal data_chk2_a : std_logic_vector (0 to 5);
signal data_chk2_b : std_logic_vector (0 to 5);
signal data_chk2_c : std_logic_vector (0 to 5);
signal data_chk2_d : std_logic_vector (0 to 5);
signal data_chk2_e : std_logic_vector (0 to 5);
signal data_chk2_f : std_logic_vector (0 to 4);
signal data_chk2_a_xor : std_logic;
signal data_chk2_b_xor : std_logic;
signal data_chk2_c_xor : std_logic;
signal data_chk2_d_xor : std_logic;
signal data_chk2_e_xor : std_logic;
signal data_chk2_f_xor : std_logic;
signal data_chk2_a_xor_reg : std_logic;
signal data_chk2_b_xor_reg : std_logic;
signal data_chk2_c_xor_reg : std_logic;
signal data_chk2_d_xor_reg : std_logic;
signal data_chk2_e_xor_reg : std_logic;
signal data_chk2_f_xor_reg : std_logic;
-- Checkbit (3)
signal data_chk3_a : std_logic_vector (0 to 5);
signal data_chk3_b : std_logic_vector (0 to 5);
signal data_chk3_c : std_logic_vector (0 to 5);
signal data_chk3_d : std_logic_vector (0 to 5);
signal data_chk3_e : std_logic_vector (0 to 5);
signal data_chk3_a_xor : std_logic;
signal data_chk3_b_xor : std_logic;
signal data_chk3_c_xor : std_logic;
signal data_chk3_d_xor : std_logic;
signal data_chk3_e_xor : std_logic;
signal data_chk3_f_xor : std_logic;
signal data_chk3_a_xor_reg : std_logic;
signal data_chk3_b_xor_reg : std_logic;
signal data_chk3_c_xor_reg : std_logic;
signal data_chk3_d_xor_reg : std_logic;
signal data_chk3_e_xor_reg : std_logic;
signal data_chk3_f_xor_reg : std_logic;
-- Checkbit (4)
signal data_chk4_a : std_logic_vector (0 to 5);
signal data_chk4_b : std_logic_vector (0 to 5);
signal data_chk4_c : std_logic_vector (0 to 5);
signal data_chk4_d : std_logic_vector (0 to 5);
signal data_chk4_e : std_logic_vector (0 to 5);
signal data_chk4_a_xor : std_logic;
signal data_chk4_b_xor : std_logic;
signal data_chk4_c_xor : std_logic;
signal data_chk4_d_xor : std_logic;
signal data_chk4_e_xor : std_logic;
signal data_chk4_f_xor : std_logic;
signal data_chk4_a_xor_reg : std_logic;
signal data_chk4_b_xor_reg : std_logic;
signal data_chk4_c_xor_reg : std_logic;
signal data_chk4_d_xor_reg : std_logic;
signal data_chk4_e_xor_reg : std_logic;
signal data_chk4_f_xor_reg : std_logic;
-- Checkbit (5)
signal data_chk5_a : std_logic_vector (0 to 5);
signal data_chk5_b : std_logic_vector (0 to 5);
signal data_chk5_c : std_logic_vector (0 to 5);
signal data_chk5_d : std_logic_vector (0 to 5);
signal data_chk5_e : std_logic_vector (0 to 5);
signal data_chk5_a_xor : std_logic;
signal data_chk5_b_xor : std_logic;
signal data_chk5_c_xor : std_logic;
signal data_chk5_d_xor : std_logic;
signal data_chk5_e_xor : std_logic;
signal data_chk5_f_xor : std_logic;
signal data_chk5_a_xor_reg : std_logic;
signal data_chk5_b_xor_reg : std_logic;
signal data_chk5_c_xor_reg : std_logic;
signal data_chk5_d_xor_reg : std_logic;
signal data_chk5_e_xor_reg : std_logic;
signal data_chk5_f_xor_reg : std_logic;
-- Checkbit (6)
signal data_chk6_a : std_logic;
signal data_chk6_b : std_logic;
signal data_chk6_a_reg : std_logic;
signal data_chk6_b_reg : std_logic;
-- Checkbit (7)
signal data_chk7_a : std_logic_vector (0 to 5);
signal data_chk7_b : std_logic_vector (0 to 5);
signal data_chk7_c : std_logic_vector (0 to 5);
signal data_chk7_d : std_logic_vector (0 to 5);
signal data_chk7_e : std_logic_vector (0 to 5);
signal data_chk7_f : std_logic_vector (0 to 4);
signal data_chk7_a_xor : std_logic;
signal data_chk7_b_xor : std_logic;
signal data_chk7_c_xor : std_logic;
signal data_chk7_d_xor : std_logic;
signal data_chk7_e_xor : std_logic;
signal data_chk7_f_xor : std_logic;
signal data_chk7_a_xor_reg : std_logic;
signal data_chk7_b_xor_reg : std_logic;
signal data_chk7_c_xor_reg : std_logic;
signal data_chk7_d_xor_reg : std_logic;
signal data_chk7_e_xor_reg : std_logic;
signal data_chk7_f_xor_reg : std_logic;
begin
-----------------------------------------------------------------------------
-- For timing improvements, if check bit XOR logic
-- needs to be pipelined. Add register level here
-- after 1st LUT level.
REG_BITS : if (C_REG) generate
begin
REG_CHK: process (Clk)
begin
if (Clk'event and Clk = '1' ) then
-- Checkbit (0)
-- data_chk0_xor_reg <= data_chk0_xor;
-- data_chk0_i_xor_reg <= data_chk0_i_xor;
data_chk0_a_xor_reg <= data_chk0_a_xor;
data_chk0_b_xor_reg <= data_chk0_b_xor;
data_chk0_c_xor_reg <= data_chk0_c_xor;
data_chk0_d_xor_reg <= data_chk0_d_xor;
data_chk0_e_xor_reg <= data_chk0_e_xor;
data_chk0_f_xor_reg <= data_chk0_f_xor;
-- Checkbit (1)
-- data_chk1_xor_reg <= data_chk1_xor;
-- data_chk1_i_xor_reg <= data_chk1_i_xor;
data_chk1_a_xor_reg <= data_chk1_a_xor;
data_chk1_b_xor_reg <= data_chk1_b_xor;
data_chk1_c_xor_reg <= data_chk1_c_xor;
data_chk1_d_xor_reg <= data_chk1_d_xor;
data_chk1_e_xor_reg <= data_chk1_e_xor;
data_chk1_f_xor_reg <= data_chk1_f_xor;
-- Checkbit (2)
-- data_chk2_xor_reg <= data_chk2_xor;
-- data_chk2_i_xor_reg <= data_chk2_i_xor;
data_chk2_a_xor_reg <= data_chk2_a_xor;
data_chk2_b_xor_reg <= data_chk2_b_xor;
data_chk2_c_xor_reg <= data_chk2_c_xor;
data_chk2_d_xor_reg <= data_chk2_d_xor;
data_chk2_e_xor_reg <= data_chk2_e_xor;
data_chk2_f_xor_reg <= data_chk2_f_xor;
-- Checkbit (3)
-- data_chk3_xor_reg <= data_chk3_xor;
-- data_chk3_i_xor_reg <= data_chk3_i_xor;
data_chk3_a_xor_reg <= data_chk3_a_xor;
data_chk3_b_xor_reg <= data_chk3_b_xor;
data_chk3_c_xor_reg <= data_chk3_c_xor;
data_chk3_d_xor_reg <= data_chk3_d_xor;
data_chk3_e_xor_reg <= data_chk3_e_xor;
data_chk3_f_xor_reg <= data_chk3_f_xor;
-- Checkbit (4)
-- data_chk4_xor_reg <= data_chk4_xor;
-- data_chk4_i_xor_reg <= data_chk4_i_xor;
data_chk4_a_xor_reg <= data_chk4_a_xor;
data_chk4_b_xor_reg <= data_chk4_b_xor;
data_chk4_c_xor_reg <= data_chk4_c_xor;
data_chk4_d_xor_reg <= data_chk4_d_xor;
data_chk4_e_xor_reg <= data_chk4_e_xor;
data_chk4_f_xor_reg <= data_chk4_f_xor;
-- Checkbit (5)
-- data_chk5_xor_reg <= data_chk5_xor;
-- data_chk5_i_xor_reg <= data_chk5_i_xor;
data_chk5_a_xor_reg <= data_chk5_a_xor;
data_chk5_b_xor_reg <= data_chk5_b_xor;
data_chk5_c_xor_reg <= data_chk5_c_xor;
data_chk5_d_xor_reg <= data_chk5_d_xor;
data_chk5_e_xor_reg <= data_chk5_e_xor;
data_chk5_f_xor_reg <= data_chk5_f_xor;
-- Checkbit (6)
-- data_chk6_i_reg <= data_chk6_i;
data_chk6_a_reg <= data_chk6_a;
data_chk6_b_reg <= data_chk6_b;
-- Checkbit (7)
-- data_chk7_a_xor_reg <= data_chk7_a_xor;
-- data_chk7_b_xor_reg <= data_chk7_b_xor;
data_chk7_a_xor_reg <= data_chk7_a_xor;
data_chk7_b_xor_reg <= data_chk7_b_xor;
data_chk7_c_xor_reg <= data_chk7_c_xor;
data_chk7_d_xor_reg <= data_chk7_d_xor;
data_chk7_e_xor_reg <= data_chk7_e_xor;
data_chk7_f_xor_reg <= data_chk7_f_xor;
end if;
end process REG_CHK;
-- Perform the last XOR after the register stage
-- CheckOut(0) <= data_chk0_xor_reg xor data_chk0_i_xor_reg;
CheckOut(0) <= data_chk0_a_xor_reg xor
data_chk0_b_xor_reg xor
data_chk0_c_xor_reg xor
data_chk0_d_xor_reg xor
data_chk0_e_xor_reg xor
data_chk0_f_xor_reg;
-- CheckOut(1) <= data_chk1_xor_reg xor data_chk1_i_xor_reg;
CheckOut(1) <= data_chk1_a_xor_reg xor
data_chk1_b_xor_reg xor
data_chk1_c_xor_reg xor
data_chk1_d_xor_reg xor
data_chk1_e_xor_reg xor
data_chk1_f_xor_reg;
-- CheckOut(2) <= data_chk2_xor_reg xor data_chk2_i_xor_reg;
CheckOut(2) <= data_chk2_a_xor_reg xor
data_chk2_b_xor_reg xor
data_chk2_c_xor_reg xor
data_chk2_d_xor_reg xor
data_chk2_e_xor_reg xor
data_chk2_f_xor_reg;
-- CheckOut(3) <= data_chk3_xor_reg xor data_chk3_i_xor_reg;
CheckOut(3) <= data_chk3_a_xor_reg xor
data_chk3_b_xor_reg xor
data_chk3_c_xor_reg xor
data_chk3_d_xor_reg xor
data_chk3_e_xor_reg xor
data_chk3_f_xor_reg;
-- CheckOut(4) <= data_chk4_xor_reg xor data_chk4_i_xor_reg;
CheckOut(4) <= data_chk4_a_xor_reg xor
data_chk4_b_xor_reg xor
data_chk4_c_xor_reg xor
data_chk4_d_xor_reg xor
data_chk4_e_xor_reg xor
data_chk4_f_xor_reg;
-- CheckOut(5) <= data_chk5_xor_reg xor data_chk5_i_xor_reg;
CheckOut(5) <= data_chk5_a_xor_reg xor
data_chk5_b_xor_reg xor
data_chk5_c_xor_reg xor
data_chk5_d_xor_reg xor
data_chk5_e_xor_reg xor
data_chk5_f_xor_reg;
-- CheckOut(6) <= data_chk6_i_reg;
CheckOut(6) <= data_chk6_a_reg xor data_chk6_b_reg;
-- CheckOut(7) <= data_chk7_a_xor_reg xor data_chk7_b_xor_reg;
CheckOut(7) <= data_chk7_a_xor_reg xor
data_chk7_b_xor_reg xor
data_chk7_c_xor_reg xor
data_chk7_d_xor_reg xor
data_chk7_e_xor_reg xor
data_chk7_f_xor_reg;
end generate REG_BITS;
NO_REG_BITS: if (not C_REG) generate
begin
-- CheckOut(0) <= data_chk0_xor xor data_chk0_i_xor;
CheckOut(0) <= data_chk0_a_xor xor
data_chk0_b_xor xor
data_chk0_c_xor xor
data_chk0_d_xor xor
data_chk0_e_xor xor
data_chk0_f_xor;
-- CheckOut(1) <= data_chk1_xor xor data_chk1_i_xor;
CheckOut(1) <= data_chk1_a_xor xor
data_chk1_b_xor xor
data_chk1_c_xor xor
data_chk1_d_xor xor
data_chk1_e_xor xor
data_chk1_f_xor;
-- CheckOut(2) <= data_chk2_xor xor data_chk2_i_xor;
CheckOut(2) <= data_chk2_a_xor xor
data_chk2_b_xor xor
data_chk2_c_xor xor
data_chk2_d_xor xor
data_chk2_e_xor xor
data_chk2_f_xor;
-- CheckOut(3) <= data_chk3_xor xor data_chk3_i_xor;
CheckOut(3) <= data_chk3_a_xor xor
data_chk3_b_xor xor
data_chk3_c_xor xor
data_chk3_d_xor xor
data_chk3_e_xor xor
data_chk3_f_xor;
-- CheckOut(4) <= data_chk4_xor xor data_chk4_i_xor;
CheckOut(4) <= data_chk4_a_xor xor
data_chk4_b_xor xor
data_chk4_c_xor xor
data_chk4_d_xor xor
data_chk4_e_xor xor
data_chk4_f_xor;
-- CheckOut(5) <= data_chk5_xor xor data_chk5_i_xor;
CheckOut(5) <= data_chk5_a_xor xor
data_chk5_b_xor xor
data_chk5_c_xor xor
data_chk5_d_xor xor
data_chk5_e_xor xor
data_chk5_f_xor;
-- CheckOut(6) <= data_chk6_i;
CheckOut(6) <= data_chk6_a xor data_chk6_b;
-- CheckOut(7) <= data_chk7_a_xor xor data_chk7_b_xor;
CheckOut(7) <= data_chk7_a_xor xor
data_chk7_b_xor xor
data_chk7_c_xor xor
data_chk7_d_xor xor
data_chk7_e_xor xor
data_chk7_f_xor;
end generate NO_REG_BITS;
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Checkbit 0 built up using 2x XOR18
-------------------------------------------------------------------------------
-- XOR18_I0_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk0 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk0_xor); -- [out std_logic]
--
-- data_chk0_i <= data_chk0 (18 to 34) & '0';
--
-- XOR18_I0_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk0_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk0_i_xor); -- [out std_logic]
--
-- -- CheckOut(0) <= data_chk0_xor xor data_chk0_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk0_a <= data_chk0 (0 to 5);
data_chk0_b <= data_chk0 (6 to 11);
data_chk0_c <= data_chk0 (12 to 17);
data_chk0_d <= data_chk0 (18 to 23);
data_chk0_e <= data_chk0 (24 to 29);
data_chk0_f <= data_chk0 (30 to 34);
PARITY_CHK0_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_a_xor ); -- [out std_logic]
PARITY_CHK0_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_b_xor ); -- [out std_logic]
PARITY_CHK0_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_c_xor ); -- [out std_logic]
PARITY_CHK0_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_d_xor ); -- [out std_logic]
PARITY_CHK0_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_e_xor ); -- [out std_logic]
PARITY_CHK0_F : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk0_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk0_f_xor ); -- [out std_logic]
-------------------------------------------------------------------------------
-- Checkbit 1 built up using 2x XOR18
-------------------------------------------------------------------------------
-- XOR18_I1_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk1 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk1_xor); -- [out std_logic]
--
-- data_chk1_i <= data_chk1 (18 to 34) & '0';
--
-- XOR18_I1_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk1_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk1_i_xor); -- [out std_logic]
--
-- -- CheckOut(1) <= data_chk1_xor xor data_chk1_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk1_a <= data_chk1 (0 to 5);
data_chk1_b <= data_chk1 (6 to 11);
data_chk1_c <= data_chk1 (12 to 17);
data_chk1_d <= data_chk1 (18 to 23);
data_chk1_e <= data_chk1 (24 to 29);
data_chk1_f <= data_chk1 (30 to 34);
PARITY_chk1_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_a_xor ); -- [out std_logic]
PARITY_chk1_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_b_xor ); -- [out std_logic]
PARITY_chk1_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_c_xor ); -- [out std_logic]
PARITY_chk1_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_d_xor ); -- [out std_logic]
PARITY_chk1_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_e_xor ); -- [out std_logic]
PARITY_chk1_F : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk1_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk1_f_xor ); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 2 built up using 2x XOR18
------------------------------------------------------------------------------------------------
-- XOR18_I2_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk2 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk2_xor); -- [out std_logic]
--
-- data_chk2_i <= data_chk2 (18 to 34) & '0';
--
-- XOR18_I2_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk2_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk2_i_xor); -- [out std_logic]
--
-- -- CheckOut(2) <= data_chk2_xor xor data_chk2_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk2_a <= data_chk2 (0 to 5);
data_chk2_b <= data_chk2 (6 to 11);
data_chk2_c <= data_chk2 (12 to 17);
data_chk2_d <= data_chk2 (18 to 23);
data_chk2_e <= data_chk2 (24 to 29);
data_chk2_f <= data_chk2 (30 to 34);
PARITY_chk2_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_a_xor ); -- [out std_logic]
PARITY_chk2_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_b_xor ); -- [out std_logic]
PARITY_chk2_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_c_xor ); -- [out std_logic]
PARITY_chk2_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_d_xor ); -- [out std_logic]
PARITY_chk2_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_e_xor ); -- [out std_logic]
PARITY_chk2_F : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk2_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk2_f_xor ); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 3 built up using 2x XOR18
------------------------------------------------------------------------------------------------
-- XOR18_I3_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk3 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk3_xor); -- [out std_logic]
--
-- data_chk3_i <= data_chk3 (18 to 30) & "00000";
--
-- XOR18_I3_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk3_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk3_i_xor); -- [out std_logic]
--
-- -- CheckOut(3) <= data_chk3_xor xor data_chk3_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk3_a <= data_chk3 (0 to 5);
data_chk3_b <= data_chk3 (6 to 11);
data_chk3_c <= data_chk3 (12 to 17);
data_chk3_d <= data_chk3 (18 to 23);
data_chk3_e <= data_chk3 (24 to 29);
data_chk3_f_xor <= data_chk3 (30);
PARITY_chk3_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk3_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk3_a_xor ); -- [out std_logic]
PARITY_chk3_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk3_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk3_b_xor ); -- [out std_logic]
PARITY_chk3_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk3_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk3_c_xor ); -- [out std_logic]
PARITY_chk3_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk3_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk3_d_xor ); -- [out std_logic]
PARITY_chk3_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk3_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk3_e_xor ); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 4 built up using 2x XOR18
------------------------------------------------------------------------------------------------
-- XOR18_I4_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk4 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk4_xor); -- [out std_logic]
--
-- data_chk4_i <= data_chk4 (18 to 30) & "00000";
--
-- XOR18_I4_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk4_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk4_i_xor); -- [out std_logic]
--
-- -- CheckOut(4) <= data_chk4_xor xor data_chk4_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk4_a <= data_chk4 (0 to 5);
data_chk4_b <= data_chk4 (6 to 11);
data_chk4_c <= data_chk4 (12 to 17);
data_chk4_d <= data_chk4 (18 to 23);
data_chk4_e <= data_chk4 (24 to 29);
data_chk4_f_xor <= data_chk4 (30);
PARITY_chk4_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk4_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk4_a_xor ); -- [out std_logic]
PARITY_chk4_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk4_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk4_b_xor ); -- [out std_logic]
PARITY_chk4_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk4_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk4_c_xor ); -- [out std_logic]
PARITY_chk4_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk4_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk4_d_xor ); -- [out std_logic]
PARITY_chk4_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk4_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk4_e_xor ); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 5 built up using 2x XOR18
------------------------------------------------------------------------------------------------
-- XOR18_I5_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk5 (0 to 17), -- [in std_logic_vector(0 to 17)]
-- res => data_chk5_xor); -- [out std_logic]
--
-- data_chk5_i <= data_chk5 (18 to 30) & "00000";
--
-- XOR18_I5_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk5_i, -- [in std_logic_vector(0 to 17)]
-- res => data_chk5_i_xor); -- [out std_logic]
--
-- -- CheckOut(5) <= data_chk5_xor xor data_chk5_i_xor;
-- Push register stage to earlier in ECC XOR logic stages (when enabled, C_REG)
data_chk5_a <= data_chk5 (0 to 5);
data_chk5_b <= data_chk5 (6 to 11);
data_chk5_c <= data_chk5 (12 to 17);
data_chk5_d <= data_chk5 (18 to 23);
data_chk5_e <= data_chk5 (24 to 29);
data_chk5_f_xor <= data_chk5 (30);
PARITY_chk5_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk5_a_xor ); -- [out std_logic]
PARITY_chk5_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk5_b_xor ); -- [out std_logic]
PARITY_chk5_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk5_c_xor ); -- [out std_logic]
PARITY_chk5_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk5_d_xor ); -- [out std_logic]
PARITY_chk5_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk5_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk5_e_xor ); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 1 LUT6 + 1 XOR
------------------------------------------------------------------------------------------------
Parity_chk6_I : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk6 (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk6_xor); -- [out std_logic]
-- data_chk6_i <= data_chk6_xor xor data_chk6(6);
-- Push register stage to 1st ECC XOR logic stage (when enabled, C_REG)
data_chk6_a <= data_chk6_xor;
data_chk6_b <= data_chk6(6);
-- CheckOut(6) <= data_chk6_xor xor data_chk6(6);
-- CheckOut(6) <= data_chk6_i;
-- Overall checkbit
-- New checkbit (7) for 64-bit ECC
-- 7 <= 0 1 2 4 5 7 10 11 12 14 17 18 21 23 24 26 27 29
-- 32 33 36 38 39 41 44 46 47 50 51 53 56 57 58 60 63
------------------------------------------------------------------------------------------------
-- Checkbit 6 built up from 2x XOR18
------------------------------------------------------------------------------------------------
-- data_chk7_a <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7) & DataIn(10) &
-- DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18) & DataIn(21) &
-- DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29) ;
--
-- data_chk7_b <= DataIn(32) & DataIn(33) & DataIn(36) & DataIn(38) & DataIn(39) &
-- DataIn(41) & DataIn(44) & DataIn(46) & DataIn(47) & DataIn(50) &
-- DataIn(51) & DataIn(53) & DataIn(56) & DataIn(57) & DataIn(58) &
-- DataIn(60) & DataIn(63) & '0';
--
-- XOR18_I7_A : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk7_a, -- [in std_logic_vector(0 to 17)]
-- res => data_chk7_a_xor); -- [out std_logic]
--
--
-- XOR18_I7_B : XOR18
-- generic map (
-- C_USE_LUT6 => C_USE_LUT6) -- [boolean]
-- port map (
-- InA => data_chk7_b, -- [in std_logic_vector(0 to 17)]
-- res => data_chk7_b_xor); -- [out std_logic]
-- Move register stage to earlier in LUT XOR logic when enabled (for C_ENCODE only)
-- Break up data_chk7_a & data_chk7_b into the following 6-input LUT XOR combinations.
data_chk7_a <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(4) & DataIn(5) & DataIn(7);
data_chk7_b <= DataIn(10) & DataIn(11) & DataIn(12) & DataIn(14) & DataIn(17) & DataIn(18);
data_chk7_c <= DataIn(21) & DataIn(23) & DataIn(24) & DataIn(26) & DataIn(27) & DataIn(29);
data_chk7_d <= DataIn(32) & DataIn(33) & DataIn(36) & DataIn(38) & DataIn(39) & DataIn(41);
data_chk7_e <= DataIn(44) & DataIn(46) & DataIn(47) & DataIn(50) & DataIn(51) & DataIn(53);
data_chk7_f <= DataIn(56) & DataIn(57) & DataIn(58) & DataIn(60) & DataIn(63);
PARITY_CHK7_A : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7_a (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_a_xor ); -- [out std_logic]
PARITY_CHK7_B : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7_b (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_b_xor ); -- [out std_logic]
PARITY_CHK7_C : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7_c (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_c_xor ); -- [out std_logic]
PARITY_CHK7_D : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7_d (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_d_xor ); -- [out std_logic]
PARITY_CHK7_E : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7_e (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_e_xor ); -- [out std_logic]
PARITY_CHK7_F : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk7_f (0 to 4), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => data_chk7_f_xor ); -- [out std_logic]
-- Merge all data bits
-- CheckOut(7) <= data_chk7_xor xor data_chk7_i_xor;
-- data_chk7_i <= data_chk7_a_xor xor data_chk7_b_xor;
-- CheckOut(7) <= data_chk7_i;
end generate Encode_Bits;
--------------------------------------------------------------------------------------------------
-- Decode bits to get syndrome and UE/CE signals
--------------------------------------------------------------------------------------------------
Decode_Bits : if (not C_ENCODE) generate
signal syndrome_i : std_logic_vector(0 to 7) := (others => '0');
-- Unused signal syndrome_int_7 : std_logic;
signal chk0_1 : std_logic_vector(0 to 6);
signal chk1_1 : std_logic_vector(0 to 6);
signal chk2_1 : std_logic_vector(0 to 6);
signal data_chk3_i : std_logic_vector(0 to 31);
signal chk3_1 : std_logic_vector(0 to 3);
signal data_chk4_i : std_logic_vector(0 to 31);
signal chk4_1 : std_logic_vector(0 to 3);
signal data_chk5_i : std_logic_vector(0 to 31);
signal chk5_1 : std_logic_vector(0 to 3);
signal data_chk6_i : std_logic_vector(0 to 7);
signal data_chk7 : std_logic_vector(0 to 71);
signal chk7_1 : std_logic_vector(0 to 11);
-- signal syndrome7_a : std_logic;
-- signal syndrome7_b : std_logic;
signal syndrome_0_to_2 : std_logic_vector(0 to 2);
signal syndrome_3_to_6 : std_logic_vector(3 to 6);
signal syndrome_3_to_6_multi : std_logic;
signal syndrome_3_to_6_zero : std_logic;
signal ue_i_0 : std_logic;
signal ue_i_1 : std_logic;
begin
------------------------------------------------------------------------------------------------
-- Syndrome bit 0 built up from 5 LUT6, 1 LUT5 and 1 7-bit XOR
------------------------------------------------------------------------------------------------
-- chk0_1(3) <= CheckIn(0);
chk0_1(6) <= CheckIn(0); -- 64-bit ECC
Parity_chk0_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(0)); -- [out std_logic]
Parity_chk0_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(1)); -- [out std_logic]
Parity_chk0_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(2)); -- [out std_logic]
-- Checkbit 0
-- 18-bit for 32-bit data
-- 35-bit for 64-bit data
Parity_chk0_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(18 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(3)); -- [out std_logic]
Parity_chk0_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk0(24 to 29), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(4)); -- [out std_logic]
Parity_chk0_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk0(30 to 34), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk0_1(5)); -- [out std_logic]
-- Parity_chk0_7 : ParityEnable
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
-- port map (
-- InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Enable => Enable_ECC, -- [in std_logic]
-- Res => syndrome_i(0)); -- [out std_logic]
Parity_chk0_7 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => chk0_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(0)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 1 built up from 5 LUT6, 1 LUT5 and 1 7-bit XOR
------------------------------------------------------------------------------------------------
-- chk1_1(3) <= CheckIn(1);
chk1_1(6) <= CheckIn(1); -- 64-bit ECC
Parity_chk1_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(0)); -- [out std_logic]
Parity_chk1_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(1)); -- [out std_logic]
Parity_chk1_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(2)); -- [out std_logic]
-- Checkbit 1
-- 18-bit for 32-bit data
-- 35-bit for 64-bit data
Parity_chk1_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(18 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(3)); -- [out std_logic]
Parity_chk1_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk1(24 to 29), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(4)); -- [out std_logic]
Parity_chk1_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk1(30 to 34), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk1_1(5)); -- [out std_logic]
-- Parity_chk1_7 : ParityEnable
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
-- port map (
-- InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Enable => Enable_ECC, -- [in std_logic]
-- Res => syndrome_i(1)); -- [out std_logic]
Parity_chk1_7 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => chk1_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(1)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 2 built up from 5 LUT6, 1 LUT5 and 1 7-bit XOR
------------------------------------------------------------------------------------------------
-- chk2_1(3) <= CheckIn(2);
chk2_1(6) <= CheckIn(2); -- 64-bit ECC
Parity_chk2_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(0)); -- [out std_logic]
Parity_chk2_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(1)); -- [out std_logic]
Parity_chk2_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(2)); -- [out std_logic]
-- Checkbit 2
-- 18-bit for 32-bit data
-- 35-bit for 64-bit data
Parity_chk2_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(18 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(3)); -- [out std_logic]
Parity_chk2_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk2(24 to 29), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(4)); -- [out std_logic]
Parity_chk2_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 5)
port map (
InA => data_chk2(30 to 34), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk2_1(5)); -- [out std_logic]
-- Parity_chk2_7 : ParityEnable
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
-- port map (
-- InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Enable => Enable_ECC, -- [in std_logic]
-- Res => syndrome_i(2)); -- [out std_logic]
Parity_chk2_7 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => chk2_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(2)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 3 built up from 4 LUT8 and 1 LUT4
------------------------------------------------------------------------------------------------
data_chk3_i <= data_chk3 & CheckIn(3);
Parity_chk3_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(0)); -- [out std_logic]
Parity_chk3_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(1)); -- [out std_logic]
-- 15-bit for 32-bit ECC
-- 31-bit for 64-bit ECC
Parity_chk3_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(16 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(2)); -- [out std_logic]
Parity_chk3_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk3_i(24 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk3_1(3)); -- [out std_logic]
-- Parity_chk3_5 : ParityEnable
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
-- port map (
-- InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Enable => Enable_ECC, -- [in std_logic]
-- Res => syndrome_i(3)); -- [out std_logic]
Parity_chk3_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk3_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(3)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 4 built up from 4 LUT8 and 1 LUT4
------------------------------------------------------------------------------------------------
data_chk4_i <= data_chk4 & CheckIn(4);
-- 15-bit for 32-bit ECC
-- 31-bit for 64-bit ECC
Parity_chk4_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(0)); -- [out std_logic]
Parity_chk4_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(1)); -- [out std_logic]
Parity_chk4_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(16 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(2)); -- [out std_logic]
Parity_chk4_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk4_i(24 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk4_1(3)); -- [out std_logic]
Parity_chk4_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk4_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(4)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 5 built up from 4 LUT8 and 1 LUT4
------------------------------------------------------------------------------------------------
data_chk5_i <= data_chk5 & CheckIn(5);
-- 15-bit for 32-bit ECC
-- 31-bit for 64-bit ECC
Parity_chk5_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk5_i(0 to 7), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk5_1(0)); -- [out std_logic]
Parity_chk5_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk5_i(8 to 15), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk5_1(1)); -- [out std_logic]
Parity_chk5_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk5_i(16 to 23), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk5_1(2)); -- [out std_logic]
Parity_chk5_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk5_i(24 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk5_1(3)); -- [out std_logic]
Parity_chk5_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 4)
port map (
InA => chk5_1, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(5)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 6 built up from 1 LUT8
------------------------------------------------------------------------------------------------
data_chk6_i <= data_chk6 & CheckIn(6);
Parity_chk6_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 8)
port map (
InA => data_chk6_i, -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => syndrome_i(6)); -- [out std_logic]
------------------------------------------------------------------------------------------------
-- Syndrome bit 7 built up from 3 LUT7 and 8 LUT6 and 1 LUT3 (12 total) + 2 LUT6 + 1 2-bit XOR
------------------------------------------------------------------------------------------------
-- 32-bit ECC uses DataIn(0:31) and Checkin (0 to 6)
-- 64-bit ECC will use DataIn(0:63) and Checkin (0 to 7)
data_chk7 <= DataIn(0) & DataIn(1) & DataIn(2) & DataIn(3) & DataIn(4) & DataIn(5) & DataIn(6) & DataIn(7) &
DataIn(8) & DataIn(9) & DataIn(10) & DataIn(11) & DataIn(12) & DataIn(13) & DataIn(14) &
DataIn(15) & DataIn(16) & DataIn(17) & DataIn(18) & DataIn(19) & DataIn(20) & DataIn(21) &
DataIn(22) & DataIn(23) & DataIn(24) & DataIn(25) & DataIn(26) & DataIn(27) & DataIn(28) &
DataIn(29) & DataIn(30) & DataIn(31) &
DataIn(32) & DataIn(33) & DataIn(34) & DataIn(35) & DataIn(36) & DataIn(37) &
DataIn(38) & DataIn(39) & DataIn(40) & DataIn(41) & DataIn(42) & DataIn(43) &
DataIn(44) & DataIn(45) & DataIn(46) & DataIn(47) & DataIn(48) & DataIn(49) &
DataIn(50) & DataIn(51) & DataIn(52) & DataIn(53) & DataIn(54) & DataIn(55) &
DataIn(56) & DataIn(57) & DataIn(58) & DataIn(59) & DataIn(60) & DataIn(61) &
DataIn(62) & DataIn(63) &
CheckIn(6) & CheckIn(5) & CheckIn(4) & CheckIn(3) & CheckIn(2) &
CheckIn(1) & CheckIn(0) & CheckIn(7);
Parity_chk7_1 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(0)); -- [out std_logic]
Parity_chk7_2 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(1)); -- [out std_logic]
Parity_chk7_3 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(12 to 17), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(2)); -- [out std_logic]
Parity_chk7_4 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk7(18 to 24), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(3)); -- [out std_logic]
Parity_chk7_5 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk7(25 to 31), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(4)); -- [out std_logic]
Parity_chk7_6 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 7)
port map (
InA => data_chk7(32 to 38), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(5)); -- [out std_logic]
Parity_chk7_7 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(39 to 44), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(6)); -- [out std_logic]
Parity_chk7_8 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(45 to 50), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(7)); -- [out std_logic]
Parity_chk7_9 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(51 to 56), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(8)); -- [out std_logic]
Parity_chk7_10 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(57 to 62), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(9)); -- [out std_logic]
Parity_chk7_11 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
port map (
InA => data_chk7(63 to 68), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(10)); -- [out std_logic]
Parity_chk7_12 : Parity
generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 3)
port map (
InA => data_chk7(69 to 71), -- [in std_logic_vector(0 to C_SIZE - 1)]
Res => chk7_1(11)); -- [out std_logic]
-- Unused
-- Parity_chk7_13 : Parity
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
-- port map (
-- InA => chk7_1 (0 to 5), -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Res => syndrome7_a); -- [out std_logic]
--
--
-- Parity_chk7_14 : Parity
-- generic map (C_USE_LUT6 => C_USE_LUT6, C_SIZE => 6)
-- port map (
-- InA => chk7_1 (6 to 11), -- [in std_logic_vector(0 to C_SIZE - 1)]
-- Res => syndrome7_b); -- [out std_logic]
-- Unused syndrome_i(7) <= syndrome7_a xor syndrome7_b;
-- Unused syndrome_i (7) <= syndrome7_a;
-- syndrome_i (7) is not used here. Final XOR stage is done outside this module with Syndrome_7 vector output.
-- Clean up this statement.
syndrome_i (7) <= '0';
-- Unused syndrome_int_7 <= syndrome7_a xor syndrome7_b;
-- Unused Syndrome_7_b <= syndrome7_b;
Syndrome <= syndrome_i;
-- Bring out seperate output to do final XOR stage on Syndrome (7) after
-- the pipeline stage.
Syndrome_7 <= chk7_1 (0 to 11);
---------------------------------------------------------------------------
-- With final syndrome registered outside this module for pipeline balancing
-- Use registered syndrome to generate any error flags.
-- Use input signal, Syndrome_Chk which is the registered Syndrome used to
-- correct any single bit errors.
syndrome_0_to_2 <= Syndrome_Chk(0) & Syndrome_Chk(1) & Syndrome_Chk(2);
-- syndrome_3_to_6 <= syndrome_i(3) & syndrome_i(4) & syndrome_i(5) & syndrome_i(6);
syndrome_3_to_6 <= Syndrome_Chk(3) & Syndrome_Chk(4) & Syndrome_Chk(5) & Syndrome_Chk(6);
syndrome_3_to_6_zero <= '1' when syndrome_3_to_6 = "0000" else '0';
-- Syndrome bits (3:6) can indicate a double bit error if
-- Syndrome (6) = '1' AND any bits of Syndrome(3:5) are equal to a '1'.
syndrome_3_to_6_multi <= '1' when (syndrome_3_to_6 = "1111" or -- 15
syndrome_3_to_6 = "1101" or -- 13
syndrome_3_to_6 = "1011" or -- 11
syndrome_3_to_6 = "1001" or -- 9
syndrome_3_to_6 = "0111" or -- 7
syndrome_3_to_6 = "0101" or -- 5
syndrome_3_to_6 = "0011") -- 3
else '0';
-- A single bit error is detectable if
-- Syndrome (7) = '1' and a double bit error is not detectable in Syndrome (3:6)
-- CE <= Enable_ECC and (syndrome_i(7) or CE_Q) when (syndrome_3_to_6_multi = '0')
-- CE <= Enable_ECC and (syndrome_int_7 or CE_Q) when (syndrome_3_to_6_multi = '0')
-- CE <= Enable_ECC and (Syndrome_Chk(7) or CE_Q) when (syndrome_3_to_6_multi = '0')
-- else CE_Q and Enable_ECC;
-- Ensure that CE flag is only asserted for a single clock cycle (and does not keep
-- registered output value)
CE <= (Enable_ECC and Syndrome_Chk(7)) when (syndrome_3_to_6_multi = '0') else '0';
-- Uncorrectable error if Syndrome(7) = '0' and any other bits are = '1'.
-- ue_i_0 <= Enable_ECC when (syndrome_3_to_6_zero = '0') or (syndrome_i(0 to 2) /= "000")
-- else UE_Q and Enable_ECC;
-- ue_i_0 <= Enable_ECC when (syndrome_3_to_6_zero = '0') or (syndrome_0_to_2 /= "000")
-- else UE_Q and Enable_ECC;
--
-- ue_i_1 <= Enable_ECC and (syndrome_3_to_6_multi or UE_Q);
-- Similar edit from CE flag. Ensure that UE flags are only asserted for a single
-- clock cycle. The flags are registered outside this module for detection in
-- register module.
ue_i_0 <= Enable_ECC when (syndrome_3_to_6_zero = '0') or (syndrome_0_to_2 /= "000") else '0';
ue_i_1 <= Enable_ECC and (syndrome_3_to_6_multi);
Use_LUT6: if (C_USE_LUT6) generate
UE_MUXF7 : MUXF7
port map (
I0 => ue_i_0,
I1 => ue_i_1,
-- S => syndrome_i(7),
-- S => syndrome_int_7,
S => Syndrome_Chk(7),
O => UE );
end generate Use_LUT6;
Use_RTL: if (not C_USE_LUT6) generate
-- bit 6 in 32-bit ECC
-- bit 7 in 64-bit ECC
-- UE <= ue_i_1 when syndrome_i(7) = '1' else ue_i_0;
-- UE <= ue_i_1 when syndrome_int_7 = '1' else ue_i_0;
UE <= ue_i_1 when Syndrome_Chk(7) = '1' else ue_i_0;
end generate Use_RTL;
end generate Decode_Bits;
end architecture IMP;
|
mit
|
a172eaf0e28e8a62d1be459e9267a301
| 0.453187 | 3.3299 | false | false | false | false |
zzhou007/161lab
|
lab6/BinaryCAM_Cell.vhd
| 1 | 1,214 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCAM_Cell is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
cell_search_bit : in STD_LOGIC;
cell_dont_care_bit : in STD_LOGIC;
cell_match_bit_in : in STD_LOGIC ;
cell_match_bit_out : out STD_LOGIC);
end BCAM_Cell;
architecture Behavioral of BCAM_Cell is
signal FF: STD_LOGIC;
begin
process(clk, rst, we, cell_search_bit, cell_dont_care_bit, cell_match_bit_in)
begin
--reset data most important
if rst = '1' then
FF <= '0';
cell_match_bit_out <= '0';
-- write data from search
elsif we = '1' then
FF <= cell_search_bit;
cell_match_bit_out <= '0';
--search
--previous result is wrong therefore nothing matches
elsif cell_match_bit_in = '0' then
cell_match_bit_out <= '0';
--previous result matches
elsif cell_match_bit_in = '1' then
--check current cell if match
if FF = cell_search_bit then
cell_match_bit_out <= '1';
else
--current cell doesnt match
cell_match_bit_out <= '0';
end if;
end if;
end process;
end Behavioral ;
|
gpl-2.0
|
661a70246b35bc5aec3c8ea6508c7578
| 0.616969 | 2.982801 | false | false | false | false |
6769/VHDL
|
Lab_5/Modelsim/DiceGame_controller.vhd
| 1 | 1,568 |
library ieee ;
use ieee.numeric_bit.all;
entity DiceGame_controller is
port(Rb, Reset, CLK: in bit;
Sum: in integer range 2 to 12;
Roll, Win, Lose: out bit);
end DiceGame_controller;
architecture DiceGameControl of DiceGame_controller is
signal State, Nextstate: integer range 0 to 5:=0;
signal Point: integer range 2 to 12;
signal Sp: bit;
begin
process(Rb, State)
begin
--Sp <= '0'; Roll <= '0'; Win <= '0'; Lose <= '0';
case State is
when 0 =>
if Rb = '1' then Nextstate <= 1;
else Nextstate<=0;
end if;
when 1 =>
if Sum = 7 or Sum = 11 then Nextstate <= 2;
elsif Sum = 2 or Sum = 3 or Sum =12 then Nextstate <= 3;
else Nextstate <= 4;--Sp <= '1' ;
end if;
when 2 =>
--Win <= '1';
--if Reset = '1' then Nextstate <= 0; end if;
when 3 =>
--Lose <= '1';
--if Reset = '1' then Nextstate <= 0; end if;
when 4 =>
if Rb = '1' then Nextstate <= 5; end if;
when 5 =>
if Sum = Point then Nextstate <= 2;
elsif Sum = 7 then Nextstate <= 3;
else Nextstate <= 4;
end if;
end case;
end process;
process(CLK)
begin
if CLK'event and CLK = '1' then
if Sp = '1' then Point <= Sum; end if;
if Reset='1' then State<=0;
else State <= Nextstate;
end if;
end if;
end process;
Win<='1' when State=2 and Rb='0'
else '0';
Lose<='1' when State=3 and Rb='0'
else '0';
Roll<=Rb;
Sp <= '1' when State=1 else '0';
end DiceGameControl;
|
gpl-2.0
|
34f1285636933b8210eaefc74e400a64
| 0.537628 | 3.37931 | false | false | false | false |
sorgelig/SAMCoupe_MIST
|
t80/T80pa.vhd
| 1 | 6,393 |
--
-- Z80 compatible microprocessor core, preudo-asynchronous top level (by Sorgelig)
--
-- Copyright (c) 2001-2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- File history :
--
-- v1.0: convert to preudo-asynchronous model with original Z80 timings.
--
-- v2.0: rewritten for more precise timings.
-- support for both CEN_n and CEN_p set to 1. Effective clock will be CLK/2.
--
-- v2.1: Output Address 0 during non-bus MCycle (fix ZX contention)
--
-- v2.2: Interrupt acknowledge cycle has been corrected
-- WAIT_n is broken in T80.vhd. Simulate correct WAIT_n locally.
--
-- v2.3: Output last used Address during non-bus MCycle seems more correct.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80pa is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CEN_p : in std_logic;
CEN_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
);
end T80pa;
architecture rtl of T80pa is
signal IntCycle_n : std_logic;
signal IntCycleD_n : std_logic_vector(1 downto 0);
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal BUSAK : std_logic;
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal CEN_pol : std_logic;
signal A_int : std_logic_vector(15 downto 0);
signal A_last : std_logic_vector(15 downto 0);
begin
A <= A_int when NoRead = '0' or Write = '1' else A_last;
BUSAK_n <= BUSAK;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1
)
port map(
CEN => CEN_p and not CEN_pol,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => '1',
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK,
CLK_n => CLK,
A => A_int,
DInst => DI, -- valid at beginning of T3
DI => DI_Reg, -- latched at middle of T3
DO => DO,
REG => REG,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n
);
process(CLK)
begin
if rising_edge(CLK) then
if RESET_n = '0' then
WR_n <= '1';
RD_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
CEN_pol <= '0';
elsif CEN_p = '1' and CEN_pol = '0' then
CEN_pol <= '1';
if MCycle = "001" then
if TState = "010" then
IORQ_n <= '1';
MREQ_n <= '1';
RD_n <= '1';
end if;
else
if TState = "001" and IORQ = '1' then
WR_n <= not Write;
RD_n <= Write;
IORQ_n <= '0';
end if;
end if;
elsif CEN_n = '1' and CEN_pol = '1' then
if TState = "010" then
CEN_pol <= not WAIT_n;
else
CEN_pol <= '0';
end if;
if TState = "011" and BUSAK = '1' then
DI_Reg <= DI;
end if;
if MCycle = "001" then
if TState = "001" then
IntCycleD_n <= IntCycleD_n(0) & IntCycle_n;
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycleD_n(1);
A_last <= A_int;
end if;
if TState = "011" then
IntCycleD_n <= "11";
RD_n <= '1';
MREQ_n <= '0';
end if;
if TState = "100" then
MREQ_n <= '1';
end if;
else
if NoRead = '0' and IORQ = '0' then
if TState = "001" then
RD_n <= Write;
MREQ_n <= '0';
A_last <= A_int;
end if;
end if;
if TState = "010" then
WR_n <= not Write;
end if;
if TState = "011" then
WR_n <= '1';
RD_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
end if;
end if;
end if;
end if;
end process;
end;
|
gpl-2.0
|
6b09d532251d2c12b99bc9460107762b
| 0.585797 | 2.983201 | false | false | false | false |
sbates130272/capi-textswap
|
rtl/list_bits_set.vhd
| 1 | 5,062 |
--------------------------------------------------------------------------------
--
-- Copyright 2015 PMC-Sierra, Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License"); you
-- may not use this file except in compliance with the License. You may
-- obtain a copy of the License at
-- http://www.apache.org/licenses/LICENSE-2.0 Unless required by
-- applicable law or agreed to in writing, software distributed under the
-- License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
-- CONDITIONS OF ANY KIND, either express or implied. See the License for
-- the specific language governing permissions and limitations under the
-- License.
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company: PMC-Sierra, Inc.
-- Engineer: Logan Gunthorpe
--
-- Description
-- -----------
-- Given a stream of sparse words this block will produce a stream of
-- indexeses indictating where the bits are set. An input fifo is
-- included in this block seeing the output may require multiple
-- clock cycles given a single input.
--
-- Each word takes a minimum of 1 cycle to process. If N bits
-- are set in a word then N cycles are required. The output
-- of the block is registered.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library capi;
use capi.misc.all;
entity list_bits_set is
generic (
DATA_WIDTH : positive := 32;
INPUT_FIFO_ADDR_BITS : positive := 6);
port (
clk : in std_logic;
en : in std_logic := '1';
clear : in std_logic := '0';
empty : out std_logic;
-- Input
din : in std_logic_vector(DATA_WIDTH-1 downto 0);
din_vld : in std_logic;
full : out std_logic;
-- Output
word : out unsigned(31 downto 0);
bit_idx : out unsigned(log2_ceil(DATA_WIDTH)-1 downto 0);
vld : out std_logic
);
end entity list_bits_set;
architecture main of list_bits_set is
signal fifo_read : std_logic;
signal fifo_valid : std_logic;
signal fifo_write : std_logic;
signal fifo_full : std_logic;
signal fifo_data : std_logic_vector(din'range);
signal fifo_empty : std_logic;
signal current : std_logic_vector(din'range) := (others=>'0');
signal current_valid : std_logic := '0';
signal bit_idx_i : unsigned(log2_ceil(DATA_WIDTH)-1 downto 0);
signal vld_i : std_logic;
signal mult_set : std_logic;
signal word_i : unsigned(31 downto 0);
begin
-- purpose: Buffer the input seeing the output takes one cycle
-- per set bit.
INPUT_FIFO : entity capi.sync_fifo_fwft
generic map (
DATA_BITS => din'length,
ADDR_BITS => INPUT_FIFO_ADDR_BITS,
WRITE_SLACK => 10)
port map (
clk => clk,
write => fifo_write,
write_data => din,
full => fifo_full,
read => fifo_read,
read_data => fifo_data,
read_valid => fifo_valid,
empty => fifo_empty);
fifo_write <= din_vld;
full <= fifo_full;
-- purpose: Get the index of the least-significant set bit and whether
-- one or more bits are set.
BITS_SET_I : entity work.bits_set
generic map (
width => din'length,
step => 8)
port map (
d => current,
frst => bit_idx_i,
one_set => vld_i,
mult_set => mult_set);
--purpose: Retrieve the next word from the FIFO or clear one of
-- the set bits.
fifo_read <= en and (not current_valid or not mult_set);
NEXT_DATA : process (clk) is
begin
if rising_edge(clk) then
if fifo_read = '1' then
current <= fifo_data;
current_valid <= fifo_valid;
elsif en = '1' then
current(to_integer(bit_idx_i)) <= '0';
end if;
end if;
end process NEXT_DATA;
-- purpose: Count the words
WORD_COUNT : process (clk) is
begin
if rising_edge(clk) then
if clear = '1' then
word_i <= (others => '1');
elsif fifo_read = '1' and fifo_valid = '1' then
word_i <= word_i + 1;
end if;
end if;
end process WORD_COUNT;
-- purpose: register the outputs
REG_OUTPUT: process (clk) is
begin
if rising_edge(clk) and en = '1' then
bit_idx <= bit_idx_i;
vld <= vld_i and current_valid;
word <= word_i;
empty <= fifo_empty and not current_valid;
end if;
end process REG_OUTPUT;
end architecture;
|
apache-2.0
|
082d0d0ea49386b62a124c7a7220683a
| 0.518175 | 4.043131 | false | false | false | false |
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