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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1,274 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,275 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2_4 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__and2_4 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | 0 |
1,276 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out_X , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out_X , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,278 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2 (
X,
A,
B
);
output X;
input A;
input B;
wire and0_out_X;
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__and2 (
X,
A,
B
); |
output X;
input A;
input B;
wire and0_out_X;
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule | 0 |
1,279 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out_X;
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__and2 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out_X;
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule | 0 |
1,280 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2_0 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and2_0 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,281 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2_0 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__and2_0 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | 0 |
1,282 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,283 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2_1 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__and2_1 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | 0 |
1,284 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn_0 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__einvn_0 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
); |
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,285 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn_0 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule | module sky130_fd_sc_hd__einvn_0 (
Z ,
A ,
TE_B
); |
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule | 0 |
1,286 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__einvn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
); |
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,287 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule | module sky130_fd_sc_hd__einvn_4 (
Z ,
A ,
TE_B
); |
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule | 0 |
1,288 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__einvn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
); |
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,289 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn_1 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule | module sky130_fd_sc_hd__einvn_1 (
Z ,
A ,
TE_B
); |
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule | 0 |
1,290 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule | module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
); |
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule | 0 |
1,292 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
notif0 notif00 (Z , A, TE_B );
endmodule | module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B
); |
output Z ;
input A ;
input TE_B;
notif0 notif00 (Z , A, TE_B );
endmodule | 0 |
1,293 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
notif0 notif00 (Z , A, TE_B );
endmodule | module sky130_fd_sc_hd__einvn (
Z ,
A ,
TE_B
); |
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
notif0 notif00 (Z , A, TE_B );
endmodule | 0 |
1,294 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__einvn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
); |
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,295 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule | module sky130_fd_sc_hd__einvn_2 (
Z ,
A ,
TE_B
); |
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule | 0 |
1,296 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__einvn_8 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
); |
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,297 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__einvn_8 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule | module sky130_fd_sc_hd__einvn_8 (
Z ,
A ,
TE_B
); |
output Z ;
input A ;
input TE_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__einvn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule | 0 |
1,298 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__probe_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__probe_p (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
); |
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,300 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__probe_p (
X,
A
);
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__probe_p (
X,
A
); |
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,301 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__probe_p (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__probe_p (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,302 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__probe_p_8 (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
);
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
sky130_fd_sc_hd__probe_p base (
.X(X),
.A(A),
.VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
endmodule | module sky130_fd_sc_hd__probe_p_8 (
X ,
A ,
VGND,
VNB ,
VPB ,
VPWR
); |
output X ;
input A ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
sky130_fd_sc_hd__probe_p base (
.X(X),
.A(A),
.VGND(VGND),
.VNB(VNB),
.VPB(VPB),
.VPWR(VPWR)
);
endmodule | 0 |
1,303 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__probe_p_8 (
X,
A
);
output X;
input A;
supply0 VGND;
supply0 VNB ;
supply1 VPB ;
supply1 VPWR;
sky130_fd_sc_hd__probe_p base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__probe_p_8 (
X,
A
); |
output X;
input A;
supply0 VGND;
supply0 VNB ;
supply1 VPB ;
supply1 VPWR;
sky130_fd_sc_hd__probe_p base (
.X(X),
.A(A)
);
endmodule | 0 |
1,304 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__inv_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,305 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_1 (
Y,
A
);
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | module sky130_fd_sc_hd__inv_1 (
Y,
A
); |
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | 0 |
1,306 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,307 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_2 (
Y,
A
);
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | module sky130_fd_sc_hd__inv_2 (
Y,
A
); |
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | 0 |
1,308 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_6 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__inv_6 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,309 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_6 (
Y,
A
);
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | module sky130_fd_sc_hd__inv_6 (
Y,
A
); |
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | 0 |
1,310 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__inv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,311 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_16 (
Y,
A
);
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | module sky130_fd_sc_hd__inv_16 (
Y,
A
); |
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | 0 |
1,312 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__inv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,313 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_4 (
Y,
A
);
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | module sky130_fd_sc_hd__inv_4 (
Y,
A
); |
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | 0 |
1,314 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__inv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,315 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_8 (
Y,
A
);
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | module sky130_fd_sc_hd__inv_8 (
Y,
A
); |
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | 0 |
1,316 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_12 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__inv_12 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,317 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv_12 (
Y,
A
);
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | module sky130_fd_sc_hd__inv_12 (
Y,
A
); |
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__inv base (
.Y(Y),
.A(A)
);
endmodule | 0 |
1,318 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
1,320 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv (
Y,
A
);
output Y;
input A;
wire not0_out_Y;
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule | module sky130_fd_sc_hd__inv (
Y,
A
); |
output Y;
input A;
wire not0_out_Y;
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule | 0 |
1,321 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__inv (
Y,
A
);
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out_Y;
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule | module sky130_fd_sc_hd__inv (
Y,
A
); |
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out_Y;
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule | 0 |
1,322 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
); |
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,323 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule | module sky130_fd_sc_hd__fa_2 (
COUT,
SUM ,
A ,
B ,
CIN
); |
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule | 0 |
1,324 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fa_4 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__fa_4 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
); |
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,325 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fa_4 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule | module sky130_fd_sc_hd__fa_4 (
COUT,
SUM ,
A ,
B ,
CIN
); |
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule | 0 |
1,326 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
); |
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,327 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule | module sky130_fd_sc_hd__fa_1 (
COUT,
SUM ,
A ,
B ,
CIN
); |
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule | 0 |
1,328 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule | module sky130_fd_sc_hd__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
); |
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule | 0 |
1,330 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule | module sky130_fd_sc_hd__fa (
COUT,
SUM ,
A ,
B ,
CIN
); |
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule | 0 |
1,331 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule | module sky130_fd_sc_hd__fa (
COUT,
SUM ,
A ,
B ,
CIN
); |
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT;
wire or2_out_SUM ;
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT, and1_out, and0_out);
buf buf0 (COUT , or1_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out);
buf buf1 (SUM , or2_out_SUM );
endmodule | 0 |
1,332 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tapvpwrvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tapvpwrvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__tapvpwrvgnd_1 (
VPWR,
VGND,
VPB ,
VNB
); |
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tapvpwrvgnd base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,333 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tapvpwrvgnd_1 ();
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tapvpwrvgnd base ();
endmodule | module sky130_fd_sc_hd__tapvpwrvgnd_1 (); |
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tapvpwrvgnd base ();
endmodule | 0 |
1,334 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule | module sky130_fd_sc_hd__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
); |
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule | 0 |
1,336 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tapvpwrvgnd ();
endmodule | module sky130_fd_sc_hd__tapvpwrvgnd (); |
endmodule | 0 |
1,337 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tapvpwrvgnd ();
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule | module sky130_fd_sc_hd__tapvpwrvgnd (); |
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule | 0 |
1,338 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__dlygate4sd3 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,340 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd3 (
X,
A
);
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__dlygate4sd3 (
X,
A
); |
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,341 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd3 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__dlygate4sd3 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,342 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd3_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd3 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlygate4sd3_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd3 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,343 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd3_1 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd3 base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__dlygate4sd3_1 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd3 base (
.X(X),
.A(A)
);
endmodule | 0 |
1,344 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2b_2 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__or2b_2 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,345 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2b_2 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule | module sky130_fd_sc_hd__or2b_2 (
X ,
A ,
B_N
); |
output X ;
input A ;
input B_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule | 0 |
1,346 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2b_4 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__or2b_4 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,347 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2b_4 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule | module sky130_fd_sc_hd__or2b_4 (
X ,
A ,
B_N
); |
output X ;
input A ;
input B_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule | 0 |
1,348 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2b_1 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__or2b_1 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,349 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2b_1 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule | module sky130_fd_sc_hd__or2b_1 (
X ,
A ,
B_N
); |
output X ;
input A ;
input B_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule | 0 |
1,350 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
not not0 (not0_out , B_N );
or or0 (or0_out_X , not0_out, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,352 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2b (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
wire not0_out ;
wire or0_out_X;
not not0 (not0_out , B_N );
or or0 (or0_out_X, not0_out, A );
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__or2b (
X ,
A ,
B_N
); |
output X ;
input A ;
input B_N;
wire not0_out ;
wire or0_out_X;
not not0 (not0_out , B_N );
or or0 (or0_out_X, not0_out, A );
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,353 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2b (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire or0_out_X;
not not0 (not0_out , B_N );
or or0 (or0_out_X, not0_out, A );
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__or2b (
X ,
A ,
B_N
); |
output X ;
input A ;
input B_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire or0_out_X;
not not0 (not0_out , B_N );
or or0 (or0_out_X, not0_out, A );
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,354 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xnor3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__xnor3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,355 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xnor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | module sky130_fd_sc_hd__xnor3_1 (
X,
A,
B,
C
); |
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | 0 |
1,356 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xnor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__xnor3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,357 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xnor3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | module sky130_fd_sc_hd__xnor3_4 (
X,
A,
B,
C
); |
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | 0 |
1,358 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xnor3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__xnor3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,359 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xnor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | module sky130_fd_sc_hd__xnor3_2 (
X,
A,
B,
C
); |
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule | 0 |
1,360 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire xnor0_out_X ;
wire pwrgood_pp0_out_X;
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,362 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
wire xnor0_out_X;
xnor xnor0 (xnor0_out_X, A, B, C );
buf buf0 (X , xnor0_out_X );
endmodule | module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C
); |
output X;
input A;
input B;
input C;
wire xnor0_out_X;
xnor xnor0 (xnor0_out_X, A, B, C );
buf buf0 (X , xnor0_out_X );
endmodule | 0 |
1,363 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire xnor0_out_X;
xnor xnor0 (xnor0_out_X, A, B, C );
buf buf0 (X , xnor0_out_X );
endmodule | module sky130_fd_sc_hd__xnor3 (
X,
A,
B,
C
); |
output X;
input A;
input B;
input C;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire xnor0_out_X;
xnor xnor0 (xnor0_out_X, A, B, C );
buf buf0 (X , xnor0_out_X );
endmodule | 0 |
1,364 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxtp_4 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dfxtp_4 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,365 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxtp_4 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule | module sky130_fd_sc_hd__dfxtp_4 (
Q ,
CLK,
D
); |
output Q ;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule | 0 |
1,366 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxtp_2 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dfxtp_2 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,367 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxtp_2 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule | module sky130_fd_sc_hd__dfxtp_2 (
Q ,
CLK,
D
); |
output Q ;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule | 0 |
1,368 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,369 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,370 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxtp (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
wire buf_Q;
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dfxtp (
Q ,
CLK,
D
); |
output Q ;
input CLK;
input D ;
wire buf_Q;
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,371 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxtp (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dfxtp (
Q ,
CLK,
D
); |
output Q ;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,372 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxtp_1 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dfxtp_1 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,373 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxtp_1 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule | module sky130_fd_sc_hd__dfxtp_1 (
Q ,
CLK,
D
); |
output Q ;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule | 0 |
1,374 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,375 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule | module sky130_fd_sc_hd__dlrtp_2 (
Q ,
RESET_B,
D ,
GATE
); |
output Q ;
input RESET_B;
input D ;
input GATE ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule | 0 |
1,376 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,377 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule | module sky130_fd_sc_hd__dlrtp_4 (
Q ,
RESET_B,
D ,
GATE
); |
output Q ;
input RESET_B;
input D ;
input GATE ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule | 0 |
1,378 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET;
wire buf_Q;
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET;
wire buf_Q;
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,379 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,380 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
wire RESET;
wire buf_Q;
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE
); |
output Q ;
input RESET_B;
input D ;
input GATE ;
wire RESET;
wire buf_Q;
not not0 (RESET , RESET_B );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,381 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dlrtp (
Q ,
RESET_B,
D ,
GATE
); |
output Q ;
input RESET_B;
input D ;
input GATE ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire GATE_delayed ;
wire RESET_delayed ;
wire RESET_B_delayed;
wire buf_Q ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,382 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlrtp_1 (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
Subsets and Splits