Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
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1,054 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
not not0 (not0_out_Y , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
1,056 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__bufinv (
Y,
A
);
output Y;
input A;
wire not0_out_Y;
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule | module sky130_fd_sc_hd__bufinv (
Y,
A
); |
output Y;
input A;
wire not0_out_Y;
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule | 0 |
1,057 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__bufinv (
Y,
A
);
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out_Y;
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule | module sky130_fd_sc_hd__bufinv (
Y,
A
); |
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out_Y;
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule | 0 |
1,058 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
); |
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | 0 |
1,059 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
X,
A
);
output X;
input A;
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 (
X,
A
); |
output X;
input A;
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule | 0 |
1,060 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
wire pwrgood0_out_A;
wire buf0_out_X ;
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, VPWRIN, VGND );
buf buf0 (buf0_out_X , pwrgood0_out_A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
); |
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
wire pwrgood0_out_A;
wire buf0_out_X ;
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, VPWRIN, VGND );
buf buf0 (buf0_out_X , pwrgood0_out_A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
endmodule | 0 |
1,062 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
X,
A
);
output X;
input A;
buf buf0 (X , A );
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
X,
A
); |
output X;
input A;
buf buf0 (X , A );
endmodule | 0 |
1,063 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
buf buf0 (X , A );
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
buf buf0 (X , A );
endmodule | 0 |
1,064 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
); |
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | 0 |
1,065 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
X,
A
);
output X;
input A;
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 (
X,
A
); |
output X;
input A;
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule | 0 |
1,066 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
X ,
A ,
VPWRIN,
VPWR ,
VGND ,
VPB
); |
output X ;
input A ;
input VPWRIN;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A),
.VPWRIN(VPWRIN),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | 0 |
1,067 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
X,
A
);
output X;
input A;
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 (
X,
A
); |
output X;
input A;
wire VPWRIN;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap base (
.X(X),
.A(A)
);
endmodule | 0 |
1,068 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__clkdlybuf4s25 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,070 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s25 (
X,
A
);
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__clkdlybuf4s25 (
X,
A
); |
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,071 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s25 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__clkdlybuf4s25 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,072 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s25_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__clkdlybuf4s25_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,073 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s25_1 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__clkdlybuf4s25_1 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A)
);
endmodule | 0 |
1,074 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s25_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__clkdlybuf4s25_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,075 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s25_2 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__clkdlybuf4s25_2 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s25 base (
.X(X),
.A(A)
);
endmodule | 0 |
1,076 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,078 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, C1, B1, and0_out, D1);
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
); |
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, C1, B1, and0_out, D1);
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,079 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, C1, B1, and0_out, D1);
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__a2111o (
X ,
A1,
A2,
B1,
C1,
D1
); |
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, C1, B1, and0_out, D1);
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,080 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a2111o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,081 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111o_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | module sky130_fd_sc_hd__a2111o_2 (
X ,
A1,
A2,
B1,
C1,
D1
); |
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | 0 |
1,082 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a2111o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,083 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111o_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | module sky130_fd_sc_hd__a2111o_1 (
X ,
A1,
A2,
B1,
C1,
D1
); |
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | 0 |
1,084 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111o_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a2111o_4 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,085 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111o_4 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | module sky130_fd_sc_hd__a2111o_4 (
X ,
A1,
A2,
B1,
C1,
D1
); |
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | 0 |
1,086 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xor2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__xor2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,087 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xor2_4 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__xor2_4 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | 0 |
1,088 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,089 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__xor2_1 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | 0 |
1,090 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,092 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xor2 (
X,
A,
B
);
output X;
input A;
input B;
wire xor0_out_X;
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule | module sky130_fd_sc_hd__xor2 (
X,
A,
B
); |
output X;
input A;
input B;
wire xor0_out_X;
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule | 0 |
1,093 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xor2 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire xor0_out_X;
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule | module sky130_fd_sc_hd__xor2 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire xor0_out_X;
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule | 0 |
1,094 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xor2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__xor2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,095 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__xor2_2 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__xor2_2 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | 0 |
1,096 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3b_2 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and3b_2 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,097 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3b_2 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule | module sky130_fd_sc_hd__and3b_2 (
X ,
A_N,
B ,
C
); |
output X ;
input A_N;
input B ;
input C ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule | 0 |
1,098 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__and3b (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X , C, not0_out, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,100 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3b (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__and3b (
X ,
A_N,
B ,
C
); |
output X ;
input A_N;
input B ;
input C ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule | 0 |
1,101 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3b (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__and3b (
X ,
A_N,
B ,
C
); |
output X ;
input A_N;
input B ;
input C ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule | 0 |
1,102 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,103 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3b_4 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule | module sky130_fd_sc_hd__and3b_4 (
X ,
A_N,
B ,
C
); |
output X ;
input A_N;
input B ;
input C ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule | 0 |
1,104 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3b_1 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and3b_1 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,105 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and3b_1 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule | module sky130_fd_sc_hd__and3b_1 (
X ,
A_N,
B ,
C
); |
output X ;
input A_N;
input B ;
input C ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule | 0 |
1,106 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
wire pwrgood0_out_A;
wire buf0_out_X ;
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood0_out_A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
); |
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
wire pwrgood0_out_A;
wire buf0_out_X ;
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood0_out_A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
endmodule | 0 |
1,108 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
X,
A
);
output X;
input A;
buf buf0 (X , A );
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
X,
A
); |
output X;
input A;
buf buf0 (X , A );
endmodule | 0 |
1,109 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
buf buf0 (X , A );
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
buf buf0 (X , A );
endmodule | 0 |
1,110 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A),
.LOWLVPWR(LOWLVPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
); |
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A),
.LOWLVPWR(LOWLVPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | 0 |
1,111 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
X,
A
);
output X;
input A;
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
X,
A
); |
output X;
input A;
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A)
);
endmodule | 0 |
1,112 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A),
.LOWLVPWR(LOWLVPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
); |
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A),
.LOWLVPWR(LOWLVPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | 0 |
1,113 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
X,
A
);
output X;
input A;
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 (
X,
A
); |
output X;
input A;
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A)
);
endmodule | 0 |
1,114 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A),
.LOWLVPWR(LOWLVPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
); |
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A),
.LOWLVPWR(LOWLVPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule | 0 |
1,115 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
X,
A
);
output X;
input A;
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 (
X,
A
); |
output X;
input A;
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A)
);
endmodule | 0 |
1,116 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule | module sky130_fd_sc_hd__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
); |
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule | 0 |
1,118 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tapvgnd2 ();
endmodule | module sky130_fd_sc_hd__tapvgnd2 (); |
endmodule | 0 |
1,119 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tapvgnd2 ();
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule | module sky130_fd_sc_hd__tapvgnd2 (); |
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule | 0 |
1,120 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tapvgnd2_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__tapvgnd2_1 (
VPWR,
VGND,
VPB ,
VNB
); |
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,121 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tapvgnd2_1 ();
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tapvgnd2 base ();
endmodule | module sky130_fd_sc_hd__tapvgnd2_1 (); |
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tapvgnd2 base ();
endmodule | 0 |
1,122 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a31o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a31o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,123 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a31o_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__a31o_1 (
X ,
A1,
A2,
A3,
B1
); |
output X ;
input A1;
input A2;
input A3;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule | 0 |
1,124 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,126 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a31o (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__a31o (
X ,
A1,
A2,
A3,
B1
); |
output X ;
input A1;
input A2;
input A3;
input B1;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,127 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a31o (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__a31o (
X ,
A1,
A2,
A3,
B1
); |
output X ;
input A1;
input A2;
input A3;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,128 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a31o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a31o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,129 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a31o_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__a31o_2 (
X ,
A1,
A2,
A3,
B1
); |
output X ;
input A1;
input A2;
input A3;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule | 0 |
1,130 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a31o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a31o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,131 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a31o_4 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__a31o_4 (
X ,
A1,
A2,
A3,
B1
); |
output X ;
input A1;
input A2;
input A3;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule | 0 |
1,132 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire nor0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire nor0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,134 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and4bb (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
wire nor0_out ;
wire and0_out_X;
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X, nor0_out, C, D );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__and4bb (
X ,
A_N,
B_N,
C ,
D
); |
output X ;
input A_N;
input B_N;
input C ;
input D ;
wire nor0_out ;
wire and0_out_X;
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X, nor0_out, C, D );
buf buf0 (X , and0_out_X );
endmodule | 0 |
1,135 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and4bb (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire nor0_out ;
wire and0_out_X;
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X, nor0_out, C, D );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__and4bb (
X ,
A_N,
B_N,
C ,
D
); |
output X ;
input A_N;
input B_N;
input C ;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire nor0_out ;
wire and0_out_X;
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X, nor0_out, C, D );
buf buf0 (X , and0_out_X );
endmodule | 0 |
1,136 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and4bb_4 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and4bb_4 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,137 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and4bb_4 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule | module sky130_fd_sc_hd__and4bb_4 (
X ,
A_N,
B_N,
C ,
D
); |
output X ;
input A_N;
input B_N;
input C ;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule | 0 |
1,138 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and4bb_1 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and4bb_1 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,139 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and4bb_1 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule | module sky130_fd_sc_hd__and4bb_1 (
X ,
A_N,
B_N,
C ,
D
); |
output X ;
input A_N;
input B_N;
input C ;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule | 0 |
1,140 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and4bb_2 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and4bb_2 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,141 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and4bb_2 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule | module sky130_fd_sc_hd__and4bb_2 (
X ,
A_N,
B_N,
C ,
D
); |
output X ;
input A_N;
input B_N;
input C ;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule | 0 |
1,142 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,143 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxbp_2 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule | module sky130_fd_sc_hd__dfxbp_2 (
Q ,
Q_N,
CLK,
D
); |
output Q ;
output Q_N;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule | 0 |
1,144 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,145 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxbp_1 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule | module sky130_fd_sc_hd__dfxbp_1 (
Q ,
Q_N,
CLK,
D
); |
output Q ;
output Q_N;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule | 0 |
1,146 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | 0 |
1,147 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | 0 |
1,148 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
wire buf_Q;
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N,
CLK,
D
); |
output Q ;
output Q_N;
input CLK;
input D ;
wire buf_Q;
sky130_fd_sc_hd__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | 0 |
1,149 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dfxbp (
Q ,
Q_N,
CLK,
D
); |
output Q ;
output Q_N;
input CLK;
input D ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | 0 |
1,150 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,151 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE)
);
endmodule | module sky130_fd_sc_hd__dlxbp_1 (
Q ,
Q_N ,
D ,
GATE
); |
output Q ;
output Q_N ;
input D ;
input GATE;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlxbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE(GATE)
);
endmodule | 0 |
1,152 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | 0 |
1,153 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule | module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule | 0 |
1,154 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
wire buf_Q;
sky130_fd_sc_hd__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE
); |
output Q ;
output Q_N ;
input D ;
input GATE;
wire buf_Q;
sky130_fd_sc_hd__udp_dlatch$P `UNIT_DELAY dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule | 0 |
1,155 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule | module sky130_fd_sc_hd__dlxbp (
Q ,
Q_N ,
D ,
GATE
); |
output Q ;
output Q_N ;
input D ;
input GATE;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule | 0 |
1,156 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,157 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule | module sky130_fd_sc_hd__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
); |
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule | 0 |
1,158 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET;
wire SET ;
wire buf_Q;
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET;
wire SET ;
wire buf_Q;
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule | 0 |
1,159 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule | 0 |
1,160 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
wire RESET;
wire SET ;
wire buf_Q;
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
); |
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
wire RESET;
wire SET ;
wire buf_Q;
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_hd__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule | 0 |
1,161 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule | module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
); |
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule | 0 |
1,162 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,163 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | 0 |
Subsets and Splits