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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
944 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux2_8 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__mux2_8 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
945 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux2_8 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule | module sky130_fd_sc_hd__mux2_8 (
X ,
A0,
A1,
S
); |
output X ;
input A0;
input A1;
input S ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule | 0 |
946 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux2_4 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__mux2_4 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
947 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__mux2_4 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule | module sky130_fd_sc_hd__mux2_4 (
X ,
A0,
A1,
S
); |
output X ;
input A0;
input A1;
input S ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule | 0 |
948 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__nor2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
949 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__nor2_2 (
Y,
A,
B
); |
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | 0 |
950 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__nor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
951 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__nor2_1 (
Y,
A,
B
); |
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | 0 |
952 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
954 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
wire nor0_out_Y;
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__nor2 (
Y,
A,
B
); |
output Y;
input A;
input B;
wire nor0_out_Y;
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
955 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire nor0_out_Y;
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__nor2 (
Y,
A,
B
); |
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire nor0_out_Y;
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
956 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__nor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
957 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__nor2_4 (
Y,
A,
B
); |
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | 0 |
958 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__nor2_8 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
959 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor2_8 (
Y,
A,
B
);
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__nor2_8 (
Y,
A,
B
); |
output Y;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule | 0 |
960 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
962 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
wire nor0_out ;
wire nor1_out_X;
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule | module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
wire nor0_out ;
wire nor1_out_X;
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule | 0 |
963 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire nor0_out ;
wire nor1_out_X;
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule | module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire nor0_out ;
wire nor1_out_X;
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X, B1_N, nor0_out );
buf buf0 (X , nor1_out_X );
endmodule | 0 |
964 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
965 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | module sky130_fd_sc_hd__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | 0 |
966 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
967 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | module sky130_fd_sc_hd__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | 0 |
968 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
969 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | module sky130_fd_sc_hd__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | 0 |
970 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a41oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a41oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
971 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a41oi_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__a41oi_1 (
Y ,
A1,
A2,
A3,
A4,
B1
); |
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | 0 |
972 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a41oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a41oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
973 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a41oi_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__a41oi_4 (
Y ,
A1,
A2,
A3,
A4,
B1
); |
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | 0 |
974 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a41oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a41oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
975 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a41oi_2 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__a41oi_2 (
Y ,
A1,
A2,
A3,
A4,
B1
); |
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | 0 |
976 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
978 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
); |
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
979 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
); |
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
980 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__or2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
981 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__or2_1 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | 0 |
982 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__or2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
983 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2_4 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__or2_4 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | 0 |
984 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
or or0 (or0_out_X , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
or or0 (or0_out_X , B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
986 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2 (
X,
A,
B
);
output X;
input A;
input B;
wire or0_out_X;
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__or2 (
X,
A,
B
); |
output X;
input A;
input B;
wire or0_out_X;
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule | 0 |
987 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire or0_out_X;
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__or2 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire or0_out_X;
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule | 0 |
988 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2_0 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__or2_0 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
989 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2_0 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__or2_0 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | 0 |
990 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__or2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
991 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or2_2 (
X,
A,
B
);
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | module sky130_fd_sc_hd__or2_2 (
X,
A,
B
); |
output X;
input A;
input B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule | 0 |
992 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | 0 |
994 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd2 (
X,
A
);
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__dlygate4sd2 (
X,
A
); |
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
995 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd2 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__dlygate4sd2 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
996 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd2_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd2 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlygate4sd2_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd2 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
997 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd2_1 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd2 base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__dlygate4sd2_1 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd2 base (
.X(X),
.A(A)
);
endmodule | 0 |
998 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__o41ai (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
1,000 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule | module sky130_fd_sc_hd__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
); |
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule | 0 |
1,001 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule | module sky130_fd_sc_hd__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
); |
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule | 0 |
1,002 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o41ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o41ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,003 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o41ai_2 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__o41ai_2 (
Y ,
A1,
A2,
A3,
A4,
B1
); |
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | 0 |
1,004 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o41ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o41ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,005 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o41ai_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__o41ai_1 (
Y ,
A1,
A2,
A3,
A4,
B1
); |
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | 0 |
1,006 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o41ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o41ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,007 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o41ai_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__o41ai_4 (
Y ,
A1,
A2,
A3,
A4,
B1
); |
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule | 0 |
1,008 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2b_2 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and2b_2 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,009 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2b_2 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule | module sky130_fd_sc_hd__and2b_2 (
X ,
A_N,
B
); |
output X ;
input A_N;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule | 0 |
1,010 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2b_4 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and2b_4 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,011 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2b_4 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule | module sky130_fd_sc_hd__and2b_4 (
X ,
A_N,
B
); |
output X ;
input A_N;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule | 0 |
1,012 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,014 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2b (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__and2b (
X ,
A_N,
B
); |
output X ;
input A_N;
input B ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule | 0 |
1,015 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2b (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__and2b (
X ,
A_N,
B
); |
output X ;
input A_N;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule | 0 |
1,016 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2b_1 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__and2b_1 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,017 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__and2b_1 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule | module sky130_fd_sc_hd__and2b_1 (
X ,
A_N,
B
); |
output X ;
input A_N;
input B ;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule | 0 |
1,018 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a311o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a311o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,019 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a311o_2 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | module sky130_fd_sc_hd__a311o_2 (
X ,
A1,
A2,
A3,
B1,
C1
); |
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | 0 |
1,020 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a311o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a311o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,021 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a311o_1 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | module sky130_fd_sc_hd__a311o_1 (
X ,
A1,
A2,
A3,
B1,
C1
); |
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | 0 |
1,022 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a311o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a311o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,023 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a311o_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | module sky130_fd_sc_hd__a311o_4 (
X ,
A1,
A2,
A3,
B1,
C1
); |
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | 0 |
1,024 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,026 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__a311o (
X ,
A1,
A2,
A3,
B1,
C1
); |
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,027 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a311o (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__a311o (
X ,
A1,
A2,
A3,
B1,
C1
); |
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire or0_out_X;
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, C1, B1);
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,028 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
1,030 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
); |
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
1,031 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__a2111oi (
Y ,
A1,
A2,
B1,
C1,
D1
); |
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire nor0_out_Y;
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, C1, D1, and0_out);
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
1,032 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111oi_0 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a2111oi_0 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,033 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111oi_0 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | module sky130_fd_sc_hd__a2111oi_0 (
Y ,
A1,
A2,
B1,
C1,
D1
); |
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | 0 |
1,034 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a2111oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,035 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111oi_1 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | module sky130_fd_sc_hd__a2111oi_1 (
Y ,
A1,
A2,
B1,
C1,
D1
); |
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | 0 |
1,036 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a2111oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,037 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111oi_4 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | module sky130_fd_sc_hd__a2111oi_4 (
Y ,
A1,
A2,
B1,
C1,
D1
); |
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | 0 |
1,038 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a2111oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,039 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a2111oi_2 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | module sky130_fd_sc_hd__a2111oi_2 (
Y ,
A1,
A2,
B1,
C1,
D1
); |
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule | 0 |
1,040 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or3b_4 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__or3b_4 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,041 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or3b_4 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule | module sky130_fd_sc_hd__or3b_4 (
X ,
A ,
B ,
C_N
); |
output X ;
input A ;
input B ;
input C_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule | 0 |
1,042 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or3b_2 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__or3b_2 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,043 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or3b_2 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule | module sky130_fd_sc_hd__or3b_2 (
X ,
A ,
B ,
C_N
); |
output X ;
input A ;
input B ;
input C_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule | 0 |
1,044 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,046 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
wire not0_out ;
wire or0_out_X;
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N
); |
output X ;
input A ;
input B ;
input C_N;
wire not0_out ;
wire or0_out_X;
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,047 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire or0_out_X;
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N
); |
output X ;
input A ;
input B ;
input C_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire or0_out_X;
not not0 (not0_out , C_N );
or or0 (or0_out_X, B, A, not0_out );
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,048 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,049 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule | module sky130_fd_sc_hd__or3b_1 (
X ,
A ,
B ,
C_N
); |
output X ;
input A ;
input B ;
input C_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule | 0 |
1,050 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__bufinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__bufinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,051 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__bufinv_8 (
Y,
A
);
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A)
);
endmodule | module sky130_fd_sc_hd__bufinv_8 (
Y,
A
); |
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A)
);
endmodule | 0 |
1,052 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__bufinv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__bufinv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,053 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__bufinv_16 (
Y,
A
);
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A)
);
endmodule | module sky130_fd_sc_hd__bufinv_16 (
Y,
A
); |
output Y;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__bufinv base (
.Y(Y),
.A(A)
);
endmodule | 0 |
Subsets and Splits