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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1,820 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd1_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlygate4sd1_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,821 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd1_1 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__dlygate4sd1_1 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule | 0 |
1,822 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,824 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
);
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
); |
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,825 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__dlygate4sd1 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,826 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
1,828 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ai (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule | module sky130_fd_sc_hd__o21ai (
Y ,
A1,
A2,
B1
); |
output Y ;
input A1;
input A2;
input B1;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule | 0 |
1,829 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ai (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule | module sky130_fd_sc_hd__o21ai (
Y ,
A1,
A2,
B1
); |
output Y ;
input A1;
input A2;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule | 0 |
1,830 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o21ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,831 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ai_2 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__o21ai_2 (
Y ,
A1,
A2,
B1
); |
output Y ;
input A1;
input A2;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule | 0 |
1,832 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o21ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,833 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ai_1 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__o21ai_1 (
Y ,
A1,
A2,
B1
); |
output Y ;
input A1;
input A2;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule | 0 |
1,834 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o21ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,835 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ai_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__o21ai_4 (
Y ,
A1,
A2,
B1
); |
output Y ;
input A1;
input A2;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule | 0 |
1,836 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ai_0 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o21ai_0 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,837 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o21ai_0 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule | module sky130_fd_sc_hd__o21ai_0 (
Y ,
A1,
A2,
B1
); |
output Y ;
input A1;
input A2;
input B1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule | 0 |
1,838 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tap_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__tap_2 (
VPWR,
VGND,
VPB ,
VNB
); |
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,839 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tap_2 ();
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tap base ();
endmodule | module sky130_fd_sc_hd__tap_2 (); |
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tap base ();
endmodule | 0 |
1,840 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tap (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule | module sky130_fd_sc_hd__tap (
VPWR,
VGND,
VPB ,
VNB
); |
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule | 0 |
1,842 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tap ();
endmodule | module sky130_fd_sc_hd__tap (); |
endmodule | 0 |
1,843 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tap ();
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule | module sky130_fd_sc_hd__tap (); |
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule | 0 |
1,844 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tap_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__tap_1 (
VPWR,
VGND,
VPB ,
VNB
); |
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,845 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__tap_1 ();
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tap base ();
endmodule | module sky130_fd_sc_hd__tap_1 (); |
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__tap base ();
endmodule | 0 |
1,846 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s50_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__clkdlybuf4s50_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,847 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s50_2 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__clkdlybuf4s50_2 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A)
);
endmodule | 0 |
1,848 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s50_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__clkdlybuf4s50_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,849 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s50_1 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__clkdlybuf4s50_1 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkdlybuf4s50 base (
.X(X),
.A(A)
);
endmodule | 0 |
1,850 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s50 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__clkdlybuf4s50 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,852 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s50 (
X,
A
);
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__clkdlybuf4s50 (
X,
A
); |
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,853 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkdlybuf4s50 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__clkdlybuf4s50 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,854 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,855 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | module sky130_fd_sc_hd__a21bo_1 (
X ,
A1 ,
A2 ,
B1_N
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | 0 |
1,856 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,857 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | module sky130_fd_sc_hd__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | 0 |
1,858 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,860 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
wire nand0_out ;
wire nand1_out_X;
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule | module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
wire nand0_out ;
wire nand1_out_X;
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule | 0 |
1,861 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire nand0_out ;
wire nand1_out_X;
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule | module sky130_fd_sc_hd__a21bo (
X ,
A1 ,
A2 ,
B1_N
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire nand0_out ;
wire nand1_out_X;
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X, B1_N, nand0_out);
buf buf0 (X , nand1_out_X );
endmodule | 0 |
1,862 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,863 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | module sky130_fd_sc_hd__a21bo_4 (
X ,
A1 ,
A2 ,
B1_N
); |
output X ;
input A1 ;
input A2 ;
input B1_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule | 0 |
1,864 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,866 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a22o (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
wire and0_out ;
wire and1_out ;
wire or0_out_X;
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__a22o (
X ,
A1,
A2,
B1,
B2
); |
output X ;
input A1;
input A2;
input B1;
input B2;
wire and0_out ;
wire and1_out ;
wire or0_out_X;
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,867 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a22o (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire and1_out ;
wire or0_out_X;
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule | module sky130_fd_sc_hd__a22o (
X ,
A1,
A2,
B1,
B2
); |
output X ;
input A1;
input A2;
input B1;
input B2;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire and0_out ;
wire and1_out ;
wire or0_out_X;
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule | 0 |
1,868 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a22o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a22o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,869 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a22o_2 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule | module sky130_fd_sc_hd__a22o_2 (
X ,
A1,
A2,
B1,
B2
); |
output X ;
input A1;
input A2;
input B1;
input B2;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule | 0 |
1,870 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a22o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a22o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,871 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a22o_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule | module sky130_fd_sc_hd__a22o_1 (
X ,
A1,
A2,
B1,
B2
); |
output X ;
input A1;
input A2;
input B1;
input B2;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule | 0 |
1,872 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a22o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__a22o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,873 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__a22o_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule | module sky130_fd_sc_hd__a22o_4 (
X ,
A1,
A2,
B1,
B2
); |
output X ;
input A1;
input A2;
input B1;
input B2;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule | 0 |
1,874 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxtp_1 (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dlxtp_1 (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,875 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxtp_1 (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule | module sky130_fd_sc_hd__dlxtp_1 (
Q ,
D ,
GATE
); |
output Q ;
input D ;
input GATE;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule | 0 |
1,876 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D, GATE, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,877 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule | module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule | 0 |
1,878 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
wire buf_Q;
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE
); |
output Q ;
input D ;
input GATE;
wire buf_Q;
sky130_fd_sc_hd__udp_dlatch$P dlatch0 (buf_Q , D, GATE );
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,879 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule | module sky130_fd_sc_hd__dlxtp (
Q ,
D ,
GATE
); |
output Q ;
input D ;
input GATE;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule | 0 |
1,880 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,881 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule | module sky130_fd_sc_hd__nor4b_1 (
Y ,
A ,
B ,
C ,
D_N
); |
output Y ;
input A ;
input B ;
input C ;
input D_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule | 0 |
1,882 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__nor4b (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire not0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y , A, B, C, not0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
1,884 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
wire not0_out ;
wire nor0_out_Y;
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__nor4b (
Y ,
A ,
B ,
C ,
D_N
); |
output Y ;
input A ;
input B ;
input C ;
input D_N;
wire not0_out ;
wire nor0_out_Y;
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
1,885 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire nor0_out_Y;
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule | module sky130_fd_sc_hd__nor4b (
Y ,
A ,
B ,
C ,
D_N
); |
output Y ;
input A ;
input B ;
input C ;
input D_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire nor0_out_Y;
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule | 0 |
1,886 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,887 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule | module sky130_fd_sc_hd__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N
); |
output Y ;
input A ;
input B ;
input C ;
input D_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule | 0 |
1,888 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,889 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule | module sky130_fd_sc_hd__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N
); |
output Y ;
input A ;
input B ;
input C ;
input D_N;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule | 0 |
1,890 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o311ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o311ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,891 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o311ai_4 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | module sky130_fd_sc_hd__o311ai_4 (
Y ,
A1,
A2,
A3,
B1,
C1
); |
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | 0 |
1,892 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | module sky130_fd_sc_hd__o311ai (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule | 0 |
1,894 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule | module sky130_fd_sc_hd__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
); |
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule | 0 |
1,895 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule | module sky130_fd_sc_hd__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
); |
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire or0_out ;
wire nand0_out_Y;
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule | 0 |
1,896 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o311ai_0 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o311ai_0 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,897 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o311ai_0 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | module sky130_fd_sc_hd__o311ai_0 (
Y ,
A1,
A2,
A3,
B1,
C1
); |
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | 0 |
1,898 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o311ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o311ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,899 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o311ai_1 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | module sky130_fd_sc_hd__o311ai_1 (
Y ,
A1,
A2,
A3,
B1,
C1
); |
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | 0 |
1,900 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o311ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__o311ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
); |
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,901 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__o311ai_2 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | module sky130_fd_sc_hd__o311ai_2 (
Y ,
A1,
A2,
A3,
B1,
C1
); |
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule | 0 |
1,902 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,903 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B)
);
endmodule | module sky130_fd_sc_hd__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B
); |
output Q ;
input CLK_N ;
input D ;
input RESET_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B)
);
endmodule | 0 |
1,904 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q ;
wire RESET ;
wire intclk;
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q ;
wire RESET ;
wire intclk;
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,905 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
); |
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,906 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
wire buf_Q ;
wire RESET ;
wire intclk;
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
); |
output Q ;
input CLK_N ;
input D ;
input RESET_B;
wire buf_Q ;
wire RESET ;
wire intclk;
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_hd__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,907 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
); |
output Q ;
input CLK_N ;
input D ;
input RESET_B;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,908 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__clkbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,909 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf_16 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__clkbuf_16 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule | 0 |
1,910 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__clkbuf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,911 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf_1 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__clkbuf_1 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule | 0 |
1,912 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__clkbuf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,913 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf_4 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__clkbuf_4 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule | 0 |
1,914 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | module sky130_fd_sc_hd__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule | 0 |
1,916 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf (
X,
A
);
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__clkbuf (
X,
A
); |
output X;
input A;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,917 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | module sky130_fd_sc_hd__clkbuf (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
wire buf0_out_X;
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule | 0 |
1,918 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__clkbuf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,919 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf_2 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__clkbuf_2 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule | 0 |
1,920 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__clkbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
); |
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,921 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__clkbuf_8 (
X,
A
);
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule | module sky130_fd_sc_hd__clkbuf_8 (
X,
A
); |
output X;
input A;
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__clkbuf base (
.X(X),
.A(A)
);
endmodule | 0 |
1,922 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
X ,
SLEEP,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
X ,
SLEEP,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
); |
output X ;
input SLEEP;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule | 0 |
1,923 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule | module sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 (
X ,
SLEEP,
A
); |
output X ;
input SLEEP;
input A ;
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_isobufsrckapwr base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule | 0 |
1,924 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire not0_out ;
wire and0_out_X ;
wire pwrgood0_out_X ;
wire pwrgood1_out_x2;
not not0 (not0_out , SLEEP );
and and0 (and0_out_X , not0_out, A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X , and0_out_X, VPWR, VGND, SLEEP);
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (pwrgood1_out_x2, pwrgood0_out_X, KAPWR, VGND );
buf buf0 (X , pwrgood1_out_x2 );
endmodule | module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
); |
output X ;
input SLEEP;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
wire not0_out ;
wire and0_out_X ;
wire pwrgood0_out_X ;
wire pwrgood1_out_x2;
not not0 (not0_out , SLEEP );
and and0 (and0_out_X , not0_out, A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S pwrgood0 (pwrgood0_out_X , and0_out_X, VPWR, VGND, SLEEP);
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (pwrgood1_out_x2, pwrgood0_out_X, KAPWR, VGND );
buf buf0 (X , pwrgood1_out_x2 );
endmodule | 0 |
1,926 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A
); |
output X ;
input SLEEP;
input A ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule | 0 |
1,927 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule | module sky130_fd_sc_hd__lpflow_isobufsrckapwr (
X ,
SLEEP,
A
); |
output X ;
input SLEEP;
input A ;
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
wire not0_out ;
wire and0_out_X;
not not0 (not0_out , SLEEP );
and and0 (and0_out_X, not0_out, A );
buf buf0 (X , and0_out_X );
endmodule | 0 |
1,928 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
wire mux_out;
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
wire mux_out;
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule | 0 |
1,929 | data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v | 518,791,335 | sky130_fd_sc_hd.v | v | 102,455 | 130 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/518791335/verilog_model/sky130_fd_sc_hd.v:4976: Can't resolve module reference: 'sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N'\n sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);\n ^~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 267,285 | module | module sky130_fd_sc_hd__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | module sky130_fd_sc_hd__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
); |
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule | 0 |
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