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2,042 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized12
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | 8 |
2,043 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized13
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | 8 |
2,044 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized14
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | 8 |
2,045 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized15
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized15 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized15
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized15 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | 8 |
2,046 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized16
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized16 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized16
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized16 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | 8 |
2,047 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized17
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized17 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized17
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized17 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | 8 |
2,048 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized18
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized18 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized18
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized18 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | 8 |
2,049 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized19
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized19 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized19
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized19 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | 8 |
2,050 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized2
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,051 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized20
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized20 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized20
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized20 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | 8 |
2,052 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized21
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized21 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized21
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized21 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | 8 |
2,053 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized22
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized22 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized22
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized22 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ));
endmodule | 8 |
2,054 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized23
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized23 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized23
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized23 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | 8 |
2,055 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized24
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized24 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized24
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized24 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | 8 |
2,056 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized25
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized25 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized25
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized25 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | 8 |
2,057 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized26
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized26 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized26
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized26 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | 8 |
2,058 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized27
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized27 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized27
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized27 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | 8 |
2,059 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized28
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized28 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized28
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized28 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | 8 |
2,060 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized29
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized29 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized29
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized29 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | 8 |
2,061 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized3
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,062 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized30
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized30 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized30
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized30 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ));
endmodule | 8 |
2,063 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized31
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized31 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized31
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized31 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,064 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized32
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized32 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized32
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized32 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,065 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized33
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized33 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized33
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized33 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,066 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized34
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized34 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized34
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized34 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,067 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized35
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized35 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized35
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized35 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,068 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized36
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized36 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized36
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized36 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,069 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized37
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized37 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized37
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized37 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,070 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized38
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized38 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized38
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized38 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,071 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized39
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized39 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized39
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized39 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,072 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized4
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,073 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized40
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized40 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized40
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized40 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,074 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized41
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized41 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized41
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized41 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,075 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized42
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized42 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized42
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized42 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,076 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized43
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized43 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized43
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized43 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,077 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized44
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized44 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized44
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized44 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,078 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized45
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized45 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized45
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized45 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,079 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized46
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized46 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized46
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized46 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,080 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized5
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,081 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized6
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out));
endmodule | 8 |
2,082 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized7
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | 8 |
2,083 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized8
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | 8 |
2,084 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized9
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9 \prim_noinit.ram
(.ADDRBWRADDR(ADDRBWRADDR),
.E(E),
.S_DCLK_O(S_DCLK_O),
.doutb_array(doutb_array),
.ena_array(ena_array),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[11] (\i_intcap.CAP_ADDR_O_reg[11] ),
.out(out),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ));
endmodule | 8 |
2,085 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,086 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,087 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized1
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,088 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized10
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,089 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized11
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,090 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized12
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,091 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized13
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,092 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized14
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,093 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized15
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized15
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,094 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized16
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized16
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,095 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized17
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized17
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,096 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized18
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized18
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,097 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized19
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized19
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,098 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized2
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,099 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized20
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized20
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,100 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized21
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized21
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,101 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized22
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized22
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][25] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][26] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,102 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized23
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized23
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,103 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized24
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized24
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,104 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized25
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized25
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,105 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized26
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized26
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,106 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized27
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized27
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,107 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized28
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized28
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,108 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized29
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized29
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,109 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized3
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,110 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized30
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized30
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][34] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][35] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,111 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized31
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized31
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,112 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized32
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized32
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,113 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized33
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized33
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,114 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized34
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized34
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,115 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized35
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized35
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,116 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized36
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized36
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,117 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized37
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized37
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,118 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized38
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized38
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][43] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][44] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,119 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized39
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized39
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,120 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized4
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,121 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized40
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized40
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,122 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized41
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized41
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,123 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized42
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized42
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,124 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized43
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized43
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,125 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized44
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized44
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,126 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized45
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized45
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,127 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized46
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg);
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized46
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
CAP_TRIGGER_O_reg); |
output [7:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]CAP_TRIGGER_O_reg;
wire [11:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire S_DCLK_O;
wire [7:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,CAP_TRIGGER_O_reg}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,128 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized5
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,129 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP);
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized6
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
DIADI,
DIPADIP); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
wire [11:0]ADDRBWRADDR;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,DIADI}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,DIPADIP}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,130 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized7
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,131 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized8
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,132 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] );
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized9
(doutb_array,
out,
S_DCLK_O,
ena_array,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[11] ,
ADDRBWRADDR,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ); |
output [8:0]doutb_array;
input out;
input S_DCLK_O;
input [0:0]ena_array;
input [0:0]enb_array;
input [0:0]E;
input [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
input [11:0]ADDRBWRADDR;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
wire [11:0]ADDRBWRADDR;
wire [0:0]E;
wire S_DCLK_O;
wire [8:0]doutb_array;
wire [0:0]ena_array;
wire [0:0]enb_array;
wire [11:0]\i_intcap.CAP_ADDR_O_reg[11] ;
wire out;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:8]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:1]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* CLOCK_DOMAINS = "INDEPENDENT" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(9),
.READ_WIDTH_B(9),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(9),
.WRITE_WIDTH_B(9))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\i_intcap.CAP_ADDR_O_reg[11] ,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,ADDRBWRADDR,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(out),
.CLKBWRCLK(S_DCLK_O),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\shifted_data_in_reg[8][16] }),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,\shifted_data_in_reg[8][17] }),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:8],doutb_array[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:1],doutb_array[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena_array),
.ENBWREN(enb_array),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(E),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule | 8 |
2,133 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(D,
out,
S_DCLK_O,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[14] ,
Q,
ADDRBWRADDR,
DIADI,
DIPADIP,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ,
\read_addr_reg[11]_rep ,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ,
CAP_TRIGGER_O_reg,
CAP_WR_EN_O_reg);
output [52:0]D;
input out;
input S_DCLK_O;
input [7:0]enb_array;
input [0:0]E;
input [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
input [14:0]Q;
input [0:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
input [10:0]\read_addr_reg[11]_rep ;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
input [7:0]CAP_TRIGGER_O_reg;
input CAP_WR_EN_O_reg;
wire [0:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire CAP_WR_EN_O_reg;
wire [52:0]D;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire [14:0]Q;
wire S_DCLK_O;
wire [7:0]enb_array;
wire [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
wire out;
wire [10:0]\read_addr_reg[11]_rep ;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.CAP_WR_EN_O_reg(CAP_WR_EN_O_reg),
.D(D),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.Q(Q),
.S_DCLK_O(S_DCLK_O),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[14] (\i_intcap.CAP_ADDR_O_reg[14] ),
.out(out),
.\read_addr_reg[11]_rep (\read_addr_reg[11]_rep ),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(D,
out,
S_DCLK_O,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[14] ,
Q,
ADDRBWRADDR,
DIADI,
DIPADIP,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ,
\read_addr_reg[11]_rep ,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ,
CAP_TRIGGER_O_reg,
CAP_WR_EN_O_reg); |
output [52:0]D;
input out;
input S_DCLK_O;
input [7:0]enb_array;
input [0:0]E;
input [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
input [14:0]Q;
input [0:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
input [10:0]\read_addr_reg[11]_rep ;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
input [7:0]CAP_TRIGGER_O_reg;
input CAP_WR_EN_O_reg;
wire [0:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire CAP_WR_EN_O_reg;
wire [52:0]D;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire [14:0]Q;
wire S_DCLK_O;
wire [7:0]enb_array;
wire [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
wire out;
wire [10:0]\read_addr_reg[11]_rep ;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.CAP_WR_EN_O_reg(CAP_WR_EN_O_reg),
.D(D),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.Q(Q),
.S_DCLK_O(S_DCLK_O),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[14] (\i_intcap.CAP_ADDR_O_reg[14] ),
.out(out),
.\read_addr_reg[11]_rep (\read_addr_reg[11]_rep ),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,134 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
(D,
out,
S_DCLK_O,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[14] ,
Q,
ADDRBWRADDR,
DIADI,
DIPADIP,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ,
\read_addr_reg[11]_rep ,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ,
CAP_TRIGGER_O_reg,
CAP_WR_EN_O_reg);
output [52:0]D;
input out;
input S_DCLK_O;
input [7:0]enb_array;
input [0:0]E;
input [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
input [14:0]Q;
input [0:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
input [10:0]\read_addr_reg[11]_rep ;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
input [7:0]CAP_TRIGGER_O_reg;
input CAP_WR_EN_O_reg;
wire [0:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire CAP_WR_EN_O_reg;
wire [52:0]D;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire [14:0]Q;
wire S_DCLK_O;
wire [7:0]enb_array;
wire [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
wire out;
wire [10:0]\read_addr_reg[11]_rep ;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.CAP_WR_EN_O_reg(CAP_WR_EN_O_reg),
.D(D),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.Q(Q),
.S_DCLK_O(S_DCLK_O),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[14] (\i_intcap.CAP_ADDR_O_reg[14] ),
.out(out),
.\read_addr_reg[11]_rep (\read_addr_reg[11]_rep ),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
(D,
out,
S_DCLK_O,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[14] ,
Q,
ADDRBWRADDR,
DIADI,
DIPADIP,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ,
\read_addr_reg[11]_rep ,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ,
CAP_TRIGGER_O_reg,
CAP_WR_EN_O_reg); |
output [52:0]D;
input out;
input S_DCLK_O;
input [7:0]enb_array;
input [0:0]E;
input [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
input [14:0]Q;
input [0:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
input [10:0]\read_addr_reg[11]_rep ;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
input [7:0]CAP_TRIGGER_O_reg;
input CAP_WR_EN_O_reg;
wire [0:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire CAP_WR_EN_O_reg;
wire [52:0]D;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire [14:0]Q;
wire S_DCLK_O;
wire [7:0]enb_array;
wire [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
wire out;
wire [10:0]\read_addr_reg[11]_rep ;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.CAP_WR_EN_O_reg(CAP_WR_EN_O_reg),
.D(D),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.Q(Q),
.S_DCLK_O(S_DCLK_O),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[14] (\i_intcap.CAP_ADDR_O_reg[14] ),
.out(out),
.\read_addr_reg[11]_rep (\read_addr_reg[11]_rep ),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,135 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
(D,
out,
S_DCLK_O,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[14] ,
Q,
ADDRBWRADDR,
DIADI,
DIPADIP,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ,
\read_addr_reg[11]_rep ,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ,
CAP_TRIGGER_O_reg,
CAP_WR_EN_O_reg);
output [52:0]D;
input out;
input S_DCLK_O;
input [7:0]enb_array;
input [0:0]E;
input [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
input [14:0]Q;
input [0:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
input [10:0]\read_addr_reg[11]_rep ;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
input [7:0]CAP_TRIGGER_O_reg;
input CAP_WR_EN_O_reg;
wire [0:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire CAP_WR_EN_O_reg;
wire [52:0]D;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire [14:0]Q;
wire S_DCLK_O;
wire [7:0]enb_array;
wire [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
wire out;
wire [10:0]\read_addr_reg[11]_rep ;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.CAP_WR_EN_O_reg(CAP_WR_EN_O_reg),
.D(D),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.Q(Q),
.S_DCLK_O(S_DCLK_O),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[14] (\i_intcap.CAP_ADDR_O_reg[14] ),
.out(out),
.\read_addr_reg[11]_rep (\read_addr_reg[11]_rep ),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
(D,
out,
S_DCLK_O,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[14] ,
Q,
ADDRBWRADDR,
DIADI,
DIPADIP,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ,
\read_addr_reg[11]_rep ,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ,
CAP_TRIGGER_O_reg,
CAP_WR_EN_O_reg); |
output [52:0]D;
input out;
input S_DCLK_O;
input [7:0]enb_array;
input [0:0]E;
input [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
input [14:0]Q;
input [0:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
input [10:0]\read_addr_reg[11]_rep ;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
input [7:0]CAP_TRIGGER_O_reg;
input CAP_WR_EN_O_reg;
wire [0:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire CAP_WR_EN_O_reg;
wire [52:0]D;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire [14:0]Q;
wire S_DCLK_O;
wire [7:0]enb_array;
wire [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
wire out;
wire [10:0]\read_addr_reg[11]_rep ;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.CAP_WR_EN_O_reg(CAP_WR_EN_O_reg),
.D(D),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.Q(Q),
.S_DCLK_O(S_DCLK_O),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[14] (\i_intcap.CAP_ADDR_O_reg[14] ),
.out(out),
.\read_addr_reg[11]_rep (\read_addr_reg[11]_rep ),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,136 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter
(CLK,
CFG_CLK,
RESET,
SCNT_RESET,
CNT_CTRL,
CNT_LOAD_IN,
CNT_LOAD_EN,
CNT_LOAD_DOUT,
COUNTER_MATCH);
input CLK;
input CFG_CLK;
input [1:0]RESET;
input SCNT_RESET;
input [1:0]CNT_CTRL;
input CNT_LOAD_IN;
input CNT_LOAD_EN;
output CNT_LOAD_DOUT;
output COUNTER_MATCH;
wire CFG_CLK;
wire CLK;
wire [1:0]CNT_CTRL;
wire CNT_LOAD_DOUT;
wire CNT_LOAD_EN;
wire CNT_LOAD_IN;
wire COUNTER_MATCH;
wire [1:0]RESET;
wire SCNT_RESET;
wire [15:0]counter;
wire [16:1]counter0;
wire \counter[0]_i_1_n_0 ;
wire \counter[10]_i_1_n_0 ;
wire \counter[11]_i_1_n_0 ;
wire \counter[12]_i_1_n_0 ;
wire \counter[12]_i_3_n_0 ;
wire \counter[12]_i_4_n_0 ;
wire \counter[12]_i_5_n_0 ;
wire \counter[12]_i_6_n_0 ;
wire \counter[13]_i_1_n_0 ;
wire \counter[14]_i_1_n_0 ;
wire \counter[15]_i_1_n_0 ;
wire \counter[16]_i_1_n_0 ;
wire \counter[16]_i_2_n_0 ;
wire \counter[16]_i_3_n_0 ;
wire \counter[16]_i_5_n_0 ;
wire \counter[16]_i_6_n_0 ;
wire \counter[16]_i_7_n_0 ;
wire \counter[16]_i_8_n_0 ;
wire \counter[1]_i_1_n_0 ;
wire \counter[2]_i_1_n_0 ;
wire \counter[3]_i_1_n_0 ;
wire \counter[4]_i_1_n_0 ;
wire \counter[4]_i_3_n_0 ;
wire \counter[4]_i_4_n_0 ;
wire \counter[4]_i_5_n_0 ;
wire \counter[4]_i_6_n_0 ;
wire \counter[5]_i_1_n_0 ;
wire \counter[6]_i_1_n_0 ;
wire \counter[7]_i_1_n_0 ;
wire \counter[8]_i_1_n_0 ;
wire \counter[8]_i_3_n_0 ;
wire \counter[8]_i_4_n_0 ;
wire \counter[8]_i_5_n_0 ;
wire \counter[8]_i_6_n_0 ;
wire \counter[9]_i_1_n_0 ;
wire [16:1]counter_load_i;
wire \counter_load_i_reg[17]_srl15_n_0 ;
wire \counter_reg[12]_i_2_n_0 ;
wire \counter_reg[12]_i_2_n_1 ;
wire \counter_reg[12]_i_2_n_2 ;
wire \counter_reg[12]_i_2_n_3 ;
wire \counter_reg[16]_i_4_n_1 ;
wire \counter_reg[16]_i_4_n_2 ;
wire \counter_reg[16]_i_4_n_3 ;
wire \counter_reg[4]_i_2_n_0 ;
wire \counter_reg[4]_i_2_n_1 ;
wire \counter_reg[4]_i_2_n_2 ;
wire \counter_reg[4]_i_2_n_3 ;
wire \counter_reg[8]_i_2_n_0 ;
wire \counter_reg[8]_i_2_n_1 ;
wire \counter_reg[8]_i_2_n_2 ;
wire \counter_reg[8]_i_2_n_3 ;
wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;
LUT4 #(
.INIT(16'hAACF))
\counter[0]_i_1
(.I0(CNT_LOAD_DOUT),
.I1(COUNTER_MATCH),
.I2(counter[0]),
.I3(\counter[16]_i_3_n_0 ),
.O(\counter[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[10]_i_1
(.I0(counter_load_i[10]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[10]),
.I3(COUNTER_MATCH),
.O(\counter[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[11]_i_1
(.I0(counter_load_i[11]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[11]),
.I3(COUNTER_MATCH),
.O(\counter[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[12]_i_1
(.I0(counter_load_i[12]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[12]),
.I3(COUNTER_MATCH),
.O(\counter[12]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_3
(.I0(counter[12]),
.O(\counter[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_4
(.I0(counter[11]),
.O(\counter[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_5
(.I0(counter[10]),
.O(\counter[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_6
(.I0(counter[9]),
.O(\counter[12]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[13]_i_1
(.I0(counter_load_i[13]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[13]),
.I3(COUNTER_MATCH),
.O(\counter[13]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[14]_i_1
(.I0(counter_load_i[14]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[14]),
.I3(COUNTER_MATCH),
.O(\counter[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[15]_i_1
(.I0(counter_load_i[15]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[15]),
.I3(COUNTER_MATCH),
.O(\counter[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFEFEE))
\counter[16]_i_1
(.I0(CNT_CTRL[0]),
.I1(SCNT_RESET),
.I2(RESET[0]),
.I3(RESET[1]),
.I4(CNT_CTRL[1]),
.O(\counter[16]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[16]_i_2
(.I0(counter_load_i[16]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[16]),
.I3(COUNTER_MATCH),
.O(\counter[16]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFAE))
\counter[16]_i_3
(.I0(CNT_CTRL[0]),
.I1(RESET[1]),
.I2(RESET[0]),
.I3(SCNT_RESET),
.O(\counter[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_5
(.I0(COUNTER_MATCH),
.O(\counter[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_6
(.I0(counter[15]),
.O(\counter[16]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_7
(.I0(counter[14]),
.O(\counter[16]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_8
(.I0(counter[13]),
.O(\counter[16]_i_8_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[1]_i_1
(.I0(counter_load_i[1]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[1]),
.I3(COUNTER_MATCH),
.O(\counter[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[2]_i_1
(.I0(counter_load_i[2]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[2]),
.I3(COUNTER_MATCH),
.O(\counter[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[3]_i_1
(.I0(counter_load_i[3]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[3]),
.I3(COUNTER_MATCH),
.O(\counter[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[4]_i_1
(.I0(counter_load_i[4]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[4]),
.I3(COUNTER_MATCH),
.O(\counter[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_3
(.I0(counter[4]),
.O(\counter[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_4
(.I0(counter[3]),
.O(\counter[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_5
(.I0(counter[2]),
.O(\counter[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_6
(.I0(counter[1]),
.O(\counter[4]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[5]_i_1
(.I0(counter_load_i[5]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[5]),
.I3(COUNTER_MATCH),
.O(\counter[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[6]_i_1
(.I0(counter_load_i[6]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[6]),
.I3(COUNTER_MATCH),
.O(\counter[6]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[7]_i_1
(.I0(counter_load_i[7]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[7]),
.I3(COUNTER_MATCH),
.O(\counter[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[8]_i_1
(.I0(counter_load_i[8]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[8]),
.I3(COUNTER_MATCH),
.O(\counter[8]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_3
(.I0(counter[8]),
.O(\counter[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_4
(.I0(counter[7]),
.O(\counter[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_5
(.I0(counter[6]),
.O(\counter[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_6
(.I0(counter[5]),
.O(\counter[8]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[9]_i_1
(.I0(counter_load_i[9]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[9]),
.I3(COUNTER_MATCH),
.O(\counter[9]_i_1_n_0 ));
FDRE \counter_load_i_reg[0]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[1]),
.Q(CNT_LOAD_DOUT),
.R(1'b0));
FDRE \counter_load_i_reg[10]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[11]),
.Q(counter_load_i[10]),
.R(1'b0));
FDRE \counter_load_i_reg[11]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[12]),
.Q(counter_load_i[11]),
.R(1'b0));
FDRE \counter_load_i_reg[12]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[13]),
.Q(counter_load_i[12]),
.R(1'b0));
FDRE \counter_load_i_reg[13]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[14]),
.Q(counter_load_i[13]),
.R(1'b0));
FDRE \counter_load_i_reg[14]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[15]),
.Q(counter_load_i[14]),
.R(1'b0));
FDRE \counter_load_i_reg[15]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[16]),
.Q(counter_load_i[15]),
.R(1'b0));
FDRE \counter_load_i_reg[16]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(\counter_load_i_reg[17]_srl15_n_0 ),
.Q(counter_load_i[16]),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[3].U_COUNTER /\counter_load_i_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[3].U_COUNTER /\counter_load_i_reg[17]_srl15 " *)
SRL16E \counter_load_i_reg[17]_srl15
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(CNT_LOAD_EN),
.CLK(CFG_CLK),
.D(CNT_LOAD_IN),
.Q(\counter_load_i_reg[17]_srl15_n_0 ));
FDRE \counter_load_i_reg[1]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[2]),
.Q(counter_load_i[1]),
.R(1'b0));
FDRE \counter_load_i_reg[2]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[3]),
.Q(counter_load_i[2]),
.R(1'b0));
FDRE \counter_load_i_reg[3]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[4]),
.Q(counter_load_i[3]),
.R(1'b0));
FDRE \counter_load_i_reg[4]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[5]),
.Q(counter_load_i[4]),
.R(1'b0));
FDRE \counter_load_i_reg[5]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[6]),
.Q(counter_load_i[5]),
.R(1'b0));
FDRE \counter_load_i_reg[6]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[7]),
.Q(counter_load_i[6]),
.R(1'b0));
FDRE \counter_load_i_reg[7]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[8]),
.Q(counter_load_i[7]),
.R(1'b0));
FDRE \counter_load_i_reg[8]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[9]),
.Q(counter_load_i[8]),
.R(1'b0));
FDRE \counter_load_i_reg[9]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[10]),
.Q(counter_load_i[9]),
.R(1'b0));
FDRE \counter_reg[0]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[0]_i_1_n_0 ),
.Q(counter[0]),
.R(1'b0));
FDRE \counter_reg[10]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[10]_i_1_n_0 ),
.Q(counter[10]),
.R(1'b0));
FDRE \counter_reg[11]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[11]_i_1_n_0 ),
.Q(counter[11]),
.R(1'b0));
FDRE \counter_reg[12]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[12]_i_1_n_0 ),
.Q(counter[12]),
.R(1'b0));
CARRY4 \counter_reg[12]_i_2
(.CI(\counter_reg[8]_i_2_n_0 ),
.CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[12:9]),
.S({\counter[12]_i_3_n_0 ,\counter[12]_i_4_n_0 ,\counter[12]_i_5_n_0 ,\counter[12]_i_6_n_0 }));
FDRE \counter_reg[13]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[13]_i_1_n_0 ),
.Q(counter[13]),
.R(1'b0));
FDRE \counter_reg[14]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[14]_i_1_n_0 ),
.Q(counter[14]),
.R(1'b0));
FDRE \counter_reg[15]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[15]_i_1_n_0 ),
.Q(counter[15]),
.R(1'b0));
FDRE \counter_reg[16]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[16]_i_2_n_0 ),
.Q(COUNTER_MATCH),
.R(1'b0));
CARRY4 \counter_reg[16]_i_4
(.CI(\counter_reg[12]_i_2_n_0 ),
.CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[16:13]),
.S({\counter[16]_i_5_n_0 ,\counter[16]_i_6_n_0 ,\counter[16]_i_7_n_0 ,\counter[16]_i_8_n_0 }));
FDRE \counter_reg[1]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[1]_i_1_n_0 ),
.Q(counter[1]),
.R(1'b0));
FDRE \counter_reg[2]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[2]_i_1_n_0 ),
.Q(counter[2]),
.R(1'b0));
FDRE \counter_reg[3]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[3]_i_1_n_0 ),
.Q(counter[3]),
.R(1'b0));
FDRE \counter_reg[4]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[4]_i_1_n_0 ),
.Q(counter[4]),
.R(1'b0));
CARRY4 \counter_reg[4]_i_2
(.CI(1'b0),
.CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
.CYINIT(counter[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[4:1]),
.S({\counter[4]_i_3_n_0 ,\counter[4]_i_4_n_0 ,\counter[4]_i_5_n_0 ,\counter[4]_i_6_n_0 }));
FDRE \counter_reg[5]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[5]_i_1_n_0 ),
.Q(counter[5]),
.R(1'b0));
FDRE \counter_reg[6]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[6]_i_1_n_0 ),
.Q(counter[6]),
.R(1'b0));
FDRE \counter_reg[7]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[7]_i_1_n_0 ),
.Q(counter[7]),
.R(1'b0));
FDRE \counter_reg[8]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[8]_i_1_n_0 ),
.Q(counter[8]),
.R(1'b0));
CARRY4 \counter_reg[8]_i_2
(.CI(\counter_reg[4]_i_2_n_0 ),
.CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[8:5]),
.S({\counter[8]_i_3_n_0 ,\counter[8]_i_4_n_0 ,\counter[8]_i_5_n_0 ,\counter[8]_i_6_n_0 }));
FDRE \counter_reg[9]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[9]_i_1_n_0 ),
.Q(counter[9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter
(CLK,
CFG_CLK,
RESET,
SCNT_RESET,
CNT_CTRL,
CNT_LOAD_IN,
CNT_LOAD_EN,
CNT_LOAD_DOUT,
COUNTER_MATCH); |
input CLK;
input CFG_CLK;
input [1:0]RESET;
input SCNT_RESET;
input [1:0]CNT_CTRL;
input CNT_LOAD_IN;
input CNT_LOAD_EN;
output CNT_LOAD_DOUT;
output COUNTER_MATCH;
wire CFG_CLK;
wire CLK;
wire [1:0]CNT_CTRL;
wire CNT_LOAD_DOUT;
wire CNT_LOAD_EN;
wire CNT_LOAD_IN;
wire COUNTER_MATCH;
wire [1:0]RESET;
wire SCNT_RESET;
wire [15:0]counter;
wire [16:1]counter0;
wire \counter[0]_i_1_n_0 ;
wire \counter[10]_i_1_n_0 ;
wire \counter[11]_i_1_n_0 ;
wire \counter[12]_i_1_n_0 ;
wire \counter[12]_i_3_n_0 ;
wire \counter[12]_i_4_n_0 ;
wire \counter[12]_i_5_n_0 ;
wire \counter[12]_i_6_n_0 ;
wire \counter[13]_i_1_n_0 ;
wire \counter[14]_i_1_n_0 ;
wire \counter[15]_i_1_n_0 ;
wire \counter[16]_i_1_n_0 ;
wire \counter[16]_i_2_n_0 ;
wire \counter[16]_i_3_n_0 ;
wire \counter[16]_i_5_n_0 ;
wire \counter[16]_i_6_n_0 ;
wire \counter[16]_i_7_n_0 ;
wire \counter[16]_i_8_n_0 ;
wire \counter[1]_i_1_n_0 ;
wire \counter[2]_i_1_n_0 ;
wire \counter[3]_i_1_n_0 ;
wire \counter[4]_i_1_n_0 ;
wire \counter[4]_i_3_n_0 ;
wire \counter[4]_i_4_n_0 ;
wire \counter[4]_i_5_n_0 ;
wire \counter[4]_i_6_n_0 ;
wire \counter[5]_i_1_n_0 ;
wire \counter[6]_i_1_n_0 ;
wire \counter[7]_i_1_n_0 ;
wire \counter[8]_i_1_n_0 ;
wire \counter[8]_i_3_n_0 ;
wire \counter[8]_i_4_n_0 ;
wire \counter[8]_i_5_n_0 ;
wire \counter[8]_i_6_n_0 ;
wire \counter[9]_i_1_n_0 ;
wire [16:1]counter_load_i;
wire \counter_load_i_reg[17]_srl15_n_0 ;
wire \counter_reg[12]_i_2_n_0 ;
wire \counter_reg[12]_i_2_n_1 ;
wire \counter_reg[12]_i_2_n_2 ;
wire \counter_reg[12]_i_2_n_3 ;
wire \counter_reg[16]_i_4_n_1 ;
wire \counter_reg[16]_i_4_n_2 ;
wire \counter_reg[16]_i_4_n_3 ;
wire \counter_reg[4]_i_2_n_0 ;
wire \counter_reg[4]_i_2_n_1 ;
wire \counter_reg[4]_i_2_n_2 ;
wire \counter_reg[4]_i_2_n_3 ;
wire \counter_reg[8]_i_2_n_0 ;
wire \counter_reg[8]_i_2_n_1 ;
wire \counter_reg[8]_i_2_n_2 ;
wire \counter_reg[8]_i_2_n_3 ;
wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;
LUT4 #(
.INIT(16'hAACF))
\counter[0]_i_1
(.I0(CNT_LOAD_DOUT),
.I1(COUNTER_MATCH),
.I2(counter[0]),
.I3(\counter[16]_i_3_n_0 ),
.O(\counter[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[10]_i_1
(.I0(counter_load_i[10]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[10]),
.I3(COUNTER_MATCH),
.O(\counter[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[11]_i_1
(.I0(counter_load_i[11]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[11]),
.I3(COUNTER_MATCH),
.O(\counter[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[12]_i_1
(.I0(counter_load_i[12]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[12]),
.I3(COUNTER_MATCH),
.O(\counter[12]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_3
(.I0(counter[12]),
.O(\counter[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_4
(.I0(counter[11]),
.O(\counter[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_5
(.I0(counter[10]),
.O(\counter[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_6
(.I0(counter[9]),
.O(\counter[12]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[13]_i_1
(.I0(counter_load_i[13]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[13]),
.I3(COUNTER_MATCH),
.O(\counter[13]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[14]_i_1
(.I0(counter_load_i[14]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[14]),
.I3(COUNTER_MATCH),
.O(\counter[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[15]_i_1
(.I0(counter_load_i[15]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[15]),
.I3(COUNTER_MATCH),
.O(\counter[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFEFEE))
\counter[16]_i_1
(.I0(CNT_CTRL[0]),
.I1(SCNT_RESET),
.I2(RESET[0]),
.I3(RESET[1]),
.I4(CNT_CTRL[1]),
.O(\counter[16]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[16]_i_2
(.I0(counter_load_i[16]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[16]),
.I3(COUNTER_MATCH),
.O(\counter[16]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFAE))
\counter[16]_i_3
(.I0(CNT_CTRL[0]),
.I1(RESET[1]),
.I2(RESET[0]),
.I3(SCNT_RESET),
.O(\counter[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_5
(.I0(COUNTER_MATCH),
.O(\counter[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_6
(.I0(counter[15]),
.O(\counter[16]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_7
(.I0(counter[14]),
.O(\counter[16]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_8
(.I0(counter[13]),
.O(\counter[16]_i_8_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[1]_i_1
(.I0(counter_load_i[1]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[1]),
.I3(COUNTER_MATCH),
.O(\counter[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[2]_i_1
(.I0(counter_load_i[2]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[2]),
.I3(COUNTER_MATCH),
.O(\counter[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[3]_i_1
(.I0(counter_load_i[3]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[3]),
.I3(COUNTER_MATCH),
.O(\counter[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[4]_i_1
(.I0(counter_load_i[4]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[4]),
.I3(COUNTER_MATCH),
.O(\counter[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_3
(.I0(counter[4]),
.O(\counter[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_4
(.I0(counter[3]),
.O(\counter[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_5
(.I0(counter[2]),
.O(\counter[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_6
(.I0(counter[1]),
.O(\counter[4]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[5]_i_1
(.I0(counter_load_i[5]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[5]),
.I3(COUNTER_MATCH),
.O(\counter[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[6]_i_1
(.I0(counter_load_i[6]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[6]),
.I3(COUNTER_MATCH),
.O(\counter[6]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[7]_i_1
(.I0(counter_load_i[7]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[7]),
.I3(COUNTER_MATCH),
.O(\counter[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[8]_i_1
(.I0(counter_load_i[8]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[8]),
.I3(COUNTER_MATCH),
.O(\counter[8]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_3
(.I0(counter[8]),
.O(\counter[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_4
(.I0(counter[7]),
.O(\counter[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_5
(.I0(counter[6]),
.O(\counter[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_6
(.I0(counter[5]),
.O(\counter[8]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[9]_i_1
(.I0(counter_load_i[9]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[9]),
.I3(COUNTER_MATCH),
.O(\counter[9]_i_1_n_0 ));
FDRE \counter_load_i_reg[0]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[1]),
.Q(CNT_LOAD_DOUT),
.R(1'b0));
FDRE \counter_load_i_reg[10]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[11]),
.Q(counter_load_i[10]),
.R(1'b0));
FDRE \counter_load_i_reg[11]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[12]),
.Q(counter_load_i[11]),
.R(1'b0));
FDRE \counter_load_i_reg[12]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[13]),
.Q(counter_load_i[12]),
.R(1'b0));
FDRE \counter_load_i_reg[13]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[14]),
.Q(counter_load_i[13]),
.R(1'b0));
FDRE \counter_load_i_reg[14]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[15]),
.Q(counter_load_i[14]),
.R(1'b0));
FDRE \counter_load_i_reg[15]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[16]),
.Q(counter_load_i[15]),
.R(1'b0));
FDRE \counter_load_i_reg[16]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(\counter_load_i_reg[17]_srl15_n_0 ),
.Q(counter_load_i[16]),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[3].U_COUNTER /\counter_load_i_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[3].U_COUNTER /\counter_load_i_reg[17]_srl15 " *)
SRL16E \counter_load_i_reg[17]_srl15
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(CNT_LOAD_EN),
.CLK(CFG_CLK),
.D(CNT_LOAD_IN),
.Q(\counter_load_i_reg[17]_srl15_n_0 ));
FDRE \counter_load_i_reg[1]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[2]),
.Q(counter_load_i[1]),
.R(1'b0));
FDRE \counter_load_i_reg[2]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[3]),
.Q(counter_load_i[2]),
.R(1'b0));
FDRE \counter_load_i_reg[3]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[4]),
.Q(counter_load_i[3]),
.R(1'b0));
FDRE \counter_load_i_reg[4]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[5]),
.Q(counter_load_i[4]),
.R(1'b0));
FDRE \counter_load_i_reg[5]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[6]),
.Q(counter_load_i[5]),
.R(1'b0));
FDRE \counter_load_i_reg[6]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[7]),
.Q(counter_load_i[6]),
.R(1'b0));
FDRE \counter_load_i_reg[7]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[8]),
.Q(counter_load_i[7]),
.R(1'b0));
FDRE \counter_load_i_reg[8]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[9]),
.Q(counter_load_i[8]),
.R(1'b0));
FDRE \counter_load_i_reg[9]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[10]),
.Q(counter_load_i[9]),
.R(1'b0));
FDRE \counter_reg[0]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[0]_i_1_n_0 ),
.Q(counter[0]),
.R(1'b0));
FDRE \counter_reg[10]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[10]_i_1_n_0 ),
.Q(counter[10]),
.R(1'b0));
FDRE \counter_reg[11]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[11]_i_1_n_0 ),
.Q(counter[11]),
.R(1'b0));
FDRE \counter_reg[12]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[12]_i_1_n_0 ),
.Q(counter[12]),
.R(1'b0));
CARRY4 \counter_reg[12]_i_2
(.CI(\counter_reg[8]_i_2_n_0 ),
.CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[12:9]),
.S({\counter[12]_i_3_n_0 ,\counter[12]_i_4_n_0 ,\counter[12]_i_5_n_0 ,\counter[12]_i_6_n_0 }));
FDRE \counter_reg[13]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[13]_i_1_n_0 ),
.Q(counter[13]),
.R(1'b0));
FDRE \counter_reg[14]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[14]_i_1_n_0 ),
.Q(counter[14]),
.R(1'b0));
FDRE \counter_reg[15]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[15]_i_1_n_0 ),
.Q(counter[15]),
.R(1'b0));
FDRE \counter_reg[16]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[16]_i_2_n_0 ),
.Q(COUNTER_MATCH),
.R(1'b0));
CARRY4 \counter_reg[16]_i_4
(.CI(\counter_reg[12]_i_2_n_0 ),
.CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[16:13]),
.S({\counter[16]_i_5_n_0 ,\counter[16]_i_6_n_0 ,\counter[16]_i_7_n_0 ,\counter[16]_i_8_n_0 }));
FDRE \counter_reg[1]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[1]_i_1_n_0 ),
.Q(counter[1]),
.R(1'b0));
FDRE \counter_reg[2]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[2]_i_1_n_0 ),
.Q(counter[2]),
.R(1'b0));
FDRE \counter_reg[3]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[3]_i_1_n_0 ),
.Q(counter[3]),
.R(1'b0));
FDRE \counter_reg[4]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[4]_i_1_n_0 ),
.Q(counter[4]),
.R(1'b0));
CARRY4 \counter_reg[4]_i_2
(.CI(1'b0),
.CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
.CYINIT(counter[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[4:1]),
.S({\counter[4]_i_3_n_0 ,\counter[4]_i_4_n_0 ,\counter[4]_i_5_n_0 ,\counter[4]_i_6_n_0 }));
FDRE \counter_reg[5]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[5]_i_1_n_0 ),
.Q(counter[5]),
.R(1'b0));
FDRE \counter_reg[6]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[6]_i_1_n_0 ),
.Q(counter[6]),
.R(1'b0));
FDRE \counter_reg[7]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[7]_i_1_n_0 ),
.Q(counter[7]),
.R(1'b0));
FDRE \counter_reg[8]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[8]_i_1_n_0 ),
.Q(counter[8]),
.R(1'b0));
CARRY4 \counter_reg[8]_i_2
(.CI(\counter_reg[4]_i_2_n_0 ),
.CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[8:5]),
.S({\counter[8]_i_3_n_0 ,\counter[8]_i_4_n_0 ,\counter[8]_i_5_n_0 ,\counter[8]_i_6_n_0 }));
FDRE \counter_reg[9]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[9]_i_1_n_0 ),
.Q(counter[9]),
.R(1'b0));
endmodule | 8 |
2,137 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__4
(CLK,
CFG_CLK,
RESET,
SCNT_RESET,
CNT_CTRL,
CNT_LOAD_IN,
CNT_LOAD_EN,
CNT_LOAD_DOUT,
COUNTER_MATCH);
input CLK;
input CFG_CLK;
input [1:0]RESET;
input SCNT_RESET;
input [1:0]CNT_CTRL;
input CNT_LOAD_IN;
input CNT_LOAD_EN;
output CNT_LOAD_DOUT;
output COUNTER_MATCH;
wire CFG_CLK;
wire CLK;
wire [1:0]CNT_CTRL;
wire CNT_LOAD_DOUT;
wire CNT_LOAD_EN;
wire CNT_LOAD_IN;
wire COUNTER_MATCH;
wire [1:0]RESET;
wire SCNT_RESET;
wire [15:0]counter;
wire [16:1]counter0;
wire \counter[0]_i_1_n_0 ;
wire \counter[10]_i_1_n_0 ;
wire \counter[11]_i_1_n_0 ;
wire \counter[12]_i_1_n_0 ;
wire \counter[12]_i_3_n_0 ;
wire \counter[12]_i_4_n_0 ;
wire \counter[12]_i_5_n_0 ;
wire \counter[12]_i_6_n_0 ;
wire \counter[13]_i_1_n_0 ;
wire \counter[14]_i_1_n_0 ;
wire \counter[15]_i_1_n_0 ;
wire \counter[16]_i_1_n_0 ;
wire \counter[16]_i_2_n_0 ;
wire \counter[16]_i_3_n_0 ;
wire \counter[16]_i_5_n_0 ;
wire \counter[16]_i_6_n_0 ;
wire \counter[16]_i_7_n_0 ;
wire \counter[16]_i_8_n_0 ;
wire \counter[1]_i_1_n_0 ;
wire \counter[2]_i_1_n_0 ;
wire \counter[3]_i_1_n_0 ;
wire \counter[4]_i_1_n_0 ;
wire \counter[4]_i_3_n_0 ;
wire \counter[4]_i_4_n_0 ;
wire \counter[4]_i_5_n_0 ;
wire \counter[4]_i_6_n_0 ;
wire \counter[5]_i_1_n_0 ;
wire \counter[6]_i_1_n_0 ;
wire \counter[7]_i_1_n_0 ;
wire \counter[8]_i_1_n_0 ;
wire \counter[8]_i_3_n_0 ;
wire \counter[8]_i_4_n_0 ;
wire \counter[8]_i_5_n_0 ;
wire \counter[8]_i_6_n_0 ;
wire \counter[9]_i_1_n_0 ;
wire [16:1]counter_load_i;
wire \counter_load_i_reg[17]_srl15_n_0 ;
wire \counter_reg[12]_i_2_n_0 ;
wire \counter_reg[12]_i_2_n_1 ;
wire \counter_reg[12]_i_2_n_2 ;
wire \counter_reg[12]_i_2_n_3 ;
wire \counter_reg[16]_i_4_n_1 ;
wire \counter_reg[16]_i_4_n_2 ;
wire \counter_reg[16]_i_4_n_3 ;
wire \counter_reg[4]_i_2_n_0 ;
wire \counter_reg[4]_i_2_n_1 ;
wire \counter_reg[4]_i_2_n_2 ;
wire \counter_reg[4]_i_2_n_3 ;
wire \counter_reg[8]_i_2_n_0 ;
wire \counter_reg[8]_i_2_n_1 ;
wire \counter_reg[8]_i_2_n_2 ;
wire \counter_reg[8]_i_2_n_3 ;
wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;
LUT4 #(
.INIT(16'hAACF))
\counter[0]_i_1
(.I0(CNT_LOAD_DOUT),
.I1(COUNTER_MATCH),
.I2(counter[0]),
.I3(\counter[16]_i_3_n_0 ),
.O(\counter[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[10]_i_1
(.I0(counter_load_i[10]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[10]),
.I3(COUNTER_MATCH),
.O(\counter[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[11]_i_1
(.I0(counter_load_i[11]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[11]),
.I3(COUNTER_MATCH),
.O(\counter[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[12]_i_1
(.I0(counter_load_i[12]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[12]),
.I3(COUNTER_MATCH),
.O(\counter[12]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_3
(.I0(counter[12]),
.O(\counter[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_4
(.I0(counter[11]),
.O(\counter[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_5
(.I0(counter[10]),
.O(\counter[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_6
(.I0(counter[9]),
.O(\counter[12]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[13]_i_1
(.I0(counter_load_i[13]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[13]),
.I3(COUNTER_MATCH),
.O(\counter[13]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[14]_i_1
(.I0(counter_load_i[14]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[14]),
.I3(COUNTER_MATCH),
.O(\counter[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[15]_i_1
(.I0(counter_load_i[15]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[15]),
.I3(COUNTER_MATCH),
.O(\counter[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFEFEE))
\counter[16]_i_1
(.I0(CNT_CTRL[0]),
.I1(SCNT_RESET),
.I2(RESET[0]),
.I3(RESET[1]),
.I4(CNT_CTRL[1]),
.O(\counter[16]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[16]_i_2
(.I0(counter_load_i[16]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[16]),
.I3(COUNTER_MATCH),
.O(\counter[16]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFAE))
\counter[16]_i_3
(.I0(CNT_CTRL[0]),
.I1(RESET[1]),
.I2(RESET[0]),
.I3(SCNT_RESET),
.O(\counter[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_5
(.I0(COUNTER_MATCH),
.O(\counter[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_6
(.I0(counter[15]),
.O(\counter[16]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_7
(.I0(counter[14]),
.O(\counter[16]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_8
(.I0(counter[13]),
.O(\counter[16]_i_8_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[1]_i_1
(.I0(counter_load_i[1]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[1]),
.I3(COUNTER_MATCH),
.O(\counter[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[2]_i_1
(.I0(counter_load_i[2]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[2]),
.I3(COUNTER_MATCH),
.O(\counter[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[3]_i_1
(.I0(counter_load_i[3]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[3]),
.I3(COUNTER_MATCH),
.O(\counter[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[4]_i_1
(.I0(counter_load_i[4]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[4]),
.I3(COUNTER_MATCH),
.O(\counter[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_3
(.I0(counter[4]),
.O(\counter[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_4
(.I0(counter[3]),
.O(\counter[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_5
(.I0(counter[2]),
.O(\counter[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_6
(.I0(counter[1]),
.O(\counter[4]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[5]_i_1
(.I0(counter_load_i[5]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[5]),
.I3(COUNTER_MATCH),
.O(\counter[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[6]_i_1
(.I0(counter_load_i[6]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[6]),
.I3(COUNTER_MATCH),
.O(\counter[6]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[7]_i_1
(.I0(counter_load_i[7]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[7]),
.I3(COUNTER_MATCH),
.O(\counter[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[8]_i_1
(.I0(counter_load_i[8]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[8]),
.I3(COUNTER_MATCH),
.O(\counter[8]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_3
(.I0(counter[8]),
.O(\counter[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_4
(.I0(counter[7]),
.O(\counter[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_5
(.I0(counter[6]),
.O(\counter[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_6
(.I0(counter[5]),
.O(\counter[8]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[9]_i_1
(.I0(counter_load_i[9]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[9]),
.I3(COUNTER_MATCH),
.O(\counter[9]_i_1_n_0 ));
FDRE \counter_load_i_reg[0]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[1]),
.Q(CNT_LOAD_DOUT),
.R(1'b0));
FDRE \counter_load_i_reg[10]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[11]),
.Q(counter_load_i[10]),
.R(1'b0));
FDRE \counter_load_i_reg[11]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[12]),
.Q(counter_load_i[11]),
.R(1'b0));
FDRE \counter_load_i_reg[12]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[13]),
.Q(counter_load_i[12]),
.R(1'b0));
FDRE \counter_load_i_reg[13]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[14]),
.Q(counter_load_i[13]),
.R(1'b0));
FDRE \counter_load_i_reg[14]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[15]),
.Q(counter_load_i[14]),
.R(1'b0));
FDRE \counter_load_i_reg[15]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[16]),
.Q(counter_load_i[15]),
.R(1'b0));
FDRE \counter_load_i_reg[16]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(\counter_load_i_reg[17]_srl15_n_0 ),
.Q(counter_load_i[16]),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[0].U_COUNTER /\counter_load_i_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[0].U_COUNTER /\counter_load_i_reg[17]_srl15 " *)
SRL16E \counter_load_i_reg[17]_srl15
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(CNT_LOAD_EN),
.CLK(CFG_CLK),
.D(CNT_LOAD_IN),
.Q(\counter_load_i_reg[17]_srl15_n_0 ));
FDRE \counter_load_i_reg[1]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[2]),
.Q(counter_load_i[1]),
.R(1'b0));
FDRE \counter_load_i_reg[2]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[3]),
.Q(counter_load_i[2]),
.R(1'b0));
FDRE \counter_load_i_reg[3]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[4]),
.Q(counter_load_i[3]),
.R(1'b0));
FDRE \counter_load_i_reg[4]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[5]),
.Q(counter_load_i[4]),
.R(1'b0));
FDRE \counter_load_i_reg[5]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[6]),
.Q(counter_load_i[5]),
.R(1'b0));
FDRE \counter_load_i_reg[6]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[7]),
.Q(counter_load_i[6]),
.R(1'b0));
FDRE \counter_load_i_reg[7]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[8]),
.Q(counter_load_i[7]),
.R(1'b0));
FDRE \counter_load_i_reg[8]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[9]),
.Q(counter_load_i[8]),
.R(1'b0));
FDRE \counter_load_i_reg[9]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[10]),
.Q(counter_load_i[9]),
.R(1'b0));
FDRE \counter_reg[0]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[0]_i_1_n_0 ),
.Q(counter[0]),
.R(1'b0));
FDRE \counter_reg[10]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[10]_i_1_n_0 ),
.Q(counter[10]),
.R(1'b0));
FDRE \counter_reg[11]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[11]_i_1_n_0 ),
.Q(counter[11]),
.R(1'b0));
FDRE \counter_reg[12]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[12]_i_1_n_0 ),
.Q(counter[12]),
.R(1'b0));
CARRY4 \counter_reg[12]_i_2
(.CI(\counter_reg[8]_i_2_n_0 ),
.CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[12:9]),
.S({\counter[12]_i_3_n_0 ,\counter[12]_i_4_n_0 ,\counter[12]_i_5_n_0 ,\counter[12]_i_6_n_0 }));
FDRE \counter_reg[13]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[13]_i_1_n_0 ),
.Q(counter[13]),
.R(1'b0));
FDRE \counter_reg[14]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[14]_i_1_n_0 ),
.Q(counter[14]),
.R(1'b0));
FDRE \counter_reg[15]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[15]_i_1_n_0 ),
.Q(counter[15]),
.R(1'b0));
FDRE \counter_reg[16]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[16]_i_2_n_0 ),
.Q(COUNTER_MATCH),
.R(1'b0));
CARRY4 \counter_reg[16]_i_4
(.CI(\counter_reg[12]_i_2_n_0 ),
.CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[16:13]),
.S({\counter[16]_i_5_n_0 ,\counter[16]_i_6_n_0 ,\counter[16]_i_7_n_0 ,\counter[16]_i_8_n_0 }));
FDRE \counter_reg[1]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[1]_i_1_n_0 ),
.Q(counter[1]),
.R(1'b0));
FDRE \counter_reg[2]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[2]_i_1_n_0 ),
.Q(counter[2]),
.R(1'b0));
FDRE \counter_reg[3]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[3]_i_1_n_0 ),
.Q(counter[3]),
.R(1'b0));
FDRE \counter_reg[4]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[4]_i_1_n_0 ),
.Q(counter[4]),
.R(1'b0));
CARRY4 \counter_reg[4]_i_2
(.CI(1'b0),
.CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
.CYINIT(counter[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[4:1]),
.S({\counter[4]_i_3_n_0 ,\counter[4]_i_4_n_0 ,\counter[4]_i_5_n_0 ,\counter[4]_i_6_n_0 }));
FDRE \counter_reg[5]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[5]_i_1_n_0 ),
.Q(counter[5]),
.R(1'b0));
FDRE \counter_reg[6]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[6]_i_1_n_0 ),
.Q(counter[6]),
.R(1'b0));
FDRE \counter_reg[7]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[7]_i_1_n_0 ),
.Q(counter[7]),
.R(1'b0));
FDRE \counter_reg[8]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[8]_i_1_n_0 ),
.Q(counter[8]),
.R(1'b0));
CARRY4 \counter_reg[8]_i_2
(.CI(\counter_reg[4]_i_2_n_0 ),
.CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[8:5]),
.S({\counter[8]_i_3_n_0 ,\counter[8]_i_4_n_0 ,\counter[8]_i_5_n_0 ,\counter[8]_i_6_n_0 }));
FDRE \counter_reg[9]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[9]_i_1_n_0 ),
.Q(counter[9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__4
(CLK,
CFG_CLK,
RESET,
SCNT_RESET,
CNT_CTRL,
CNT_LOAD_IN,
CNT_LOAD_EN,
CNT_LOAD_DOUT,
COUNTER_MATCH); |
input CLK;
input CFG_CLK;
input [1:0]RESET;
input SCNT_RESET;
input [1:0]CNT_CTRL;
input CNT_LOAD_IN;
input CNT_LOAD_EN;
output CNT_LOAD_DOUT;
output COUNTER_MATCH;
wire CFG_CLK;
wire CLK;
wire [1:0]CNT_CTRL;
wire CNT_LOAD_DOUT;
wire CNT_LOAD_EN;
wire CNT_LOAD_IN;
wire COUNTER_MATCH;
wire [1:0]RESET;
wire SCNT_RESET;
wire [15:0]counter;
wire [16:1]counter0;
wire \counter[0]_i_1_n_0 ;
wire \counter[10]_i_1_n_0 ;
wire \counter[11]_i_1_n_0 ;
wire \counter[12]_i_1_n_0 ;
wire \counter[12]_i_3_n_0 ;
wire \counter[12]_i_4_n_0 ;
wire \counter[12]_i_5_n_0 ;
wire \counter[12]_i_6_n_0 ;
wire \counter[13]_i_1_n_0 ;
wire \counter[14]_i_1_n_0 ;
wire \counter[15]_i_1_n_0 ;
wire \counter[16]_i_1_n_0 ;
wire \counter[16]_i_2_n_0 ;
wire \counter[16]_i_3_n_0 ;
wire \counter[16]_i_5_n_0 ;
wire \counter[16]_i_6_n_0 ;
wire \counter[16]_i_7_n_0 ;
wire \counter[16]_i_8_n_0 ;
wire \counter[1]_i_1_n_0 ;
wire \counter[2]_i_1_n_0 ;
wire \counter[3]_i_1_n_0 ;
wire \counter[4]_i_1_n_0 ;
wire \counter[4]_i_3_n_0 ;
wire \counter[4]_i_4_n_0 ;
wire \counter[4]_i_5_n_0 ;
wire \counter[4]_i_6_n_0 ;
wire \counter[5]_i_1_n_0 ;
wire \counter[6]_i_1_n_0 ;
wire \counter[7]_i_1_n_0 ;
wire \counter[8]_i_1_n_0 ;
wire \counter[8]_i_3_n_0 ;
wire \counter[8]_i_4_n_0 ;
wire \counter[8]_i_5_n_0 ;
wire \counter[8]_i_6_n_0 ;
wire \counter[9]_i_1_n_0 ;
wire [16:1]counter_load_i;
wire \counter_load_i_reg[17]_srl15_n_0 ;
wire \counter_reg[12]_i_2_n_0 ;
wire \counter_reg[12]_i_2_n_1 ;
wire \counter_reg[12]_i_2_n_2 ;
wire \counter_reg[12]_i_2_n_3 ;
wire \counter_reg[16]_i_4_n_1 ;
wire \counter_reg[16]_i_4_n_2 ;
wire \counter_reg[16]_i_4_n_3 ;
wire \counter_reg[4]_i_2_n_0 ;
wire \counter_reg[4]_i_2_n_1 ;
wire \counter_reg[4]_i_2_n_2 ;
wire \counter_reg[4]_i_2_n_3 ;
wire \counter_reg[8]_i_2_n_0 ;
wire \counter_reg[8]_i_2_n_1 ;
wire \counter_reg[8]_i_2_n_2 ;
wire \counter_reg[8]_i_2_n_3 ;
wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;
LUT4 #(
.INIT(16'hAACF))
\counter[0]_i_1
(.I0(CNT_LOAD_DOUT),
.I1(COUNTER_MATCH),
.I2(counter[0]),
.I3(\counter[16]_i_3_n_0 ),
.O(\counter[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[10]_i_1
(.I0(counter_load_i[10]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[10]),
.I3(COUNTER_MATCH),
.O(\counter[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[11]_i_1
(.I0(counter_load_i[11]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[11]),
.I3(COUNTER_MATCH),
.O(\counter[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[12]_i_1
(.I0(counter_load_i[12]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[12]),
.I3(COUNTER_MATCH),
.O(\counter[12]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_3
(.I0(counter[12]),
.O(\counter[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_4
(.I0(counter[11]),
.O(\counter[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_5
(.I0(counter[10]),
.O(\counter[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_6
(.I0(counter[9]),
.O(\counter[12]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[13]_i_1
(.I0(counter_load_i[13]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[13]),
.I3(COUNTER_MATCH),
.O(\counter[13]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[14]_i_1
(.I0(counter_load_i[14]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[14]),
.I3(COUNTER_MATCH),
.O(\counter[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[15]_i_1
(.I0(counter_load_i[15]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[15]),
.I3(COUNTER_MATCH),
.O(\counter[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFEFEE))
\counter[16]_i_1
(.I0(CNT_CTRL[0]),
.I1(SCNT_RESET),
.I2(RESET[0]),
.I3(RESET[1]),
.I4(CNT_CTRL[1]),
.O(\counter[16]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[16]_i_2
(.I0(counter_load_i[16]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[16]),
.I3(COUNTER_MATCH),
.O(\counter[16]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFAE))
\counter[16]_i_3
(.I0(CNT_CTRL[0]),
.I1(RESET[1]),
.I2(RESET[0]),
.I3(SCNT_RESET),
.O(\counter[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_5
(.I0(COUNTER_MATCH),
.O(\counter[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_6
(.I0(counter[15]),
.O(\counter[16]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_7
(.I0(counter[14]),
.O(\counter[16]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_8
(.I0(counter[13]),
.O(\counter[16]_i_8_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[1]_i_1
(.I0(counter_load_i[1]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[1]),
.I3(COUNTER_MATCH),
.O(\counter[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[2]_i_1
(.I0(counter_load_i[2]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[2]),
.I3(COUNTER_MATCH),
.O(\counter[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[3]_i_1
(.I0(counter_load_i[3]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[3]),
.I3(COUNTER_MATCH),
.O(\counter[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[4]_i_1
(.I0(counter_load_i[4]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[4]),
.I3(COUNTER_MATCH),
.O(\counter[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_3
(.I0(counter[4]),
.O(\counter[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_4
(.I0(counter[3]),
.O(\counter[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_5
(.I0(counter[2]),
.O(\counter[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_6
(.I0(counter[1]),
.O(\counter[4]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[5]_i_1
(.I0(counter_load_i[5]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[5]),
.I3(COUNTER_MATCH),
.O(\counter[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[6]_i_1
(.I0(counter_load_i[6]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[6]),
.I3(COUNTER_MATCH),
.O(\counter[6]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[7]_i_1
(.I0(counter_load_i[7]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[7]),
.I3(COUNTER_MATCH),
.O(\counter[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[8]_i_1
(.I0(counter_load_i[8]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[8]),
.I3(COUNTER_MATCH),
.O(\counter[8]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_3
(.I0(counter[8]),
.O(\counter[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_4
(.I0(counter[7]),
.O(\counter[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_5
(.I0(counter[6]),
.O(\counter[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_6
(.I0(counter[5]),
.O(\counter[8]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[9]_i_1
(.I0(counter_load_i[9]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[9]),
.I3(COUNTER_MATCH),
.O(\counter[9]_i_1_n_0 ));
FDRE \counter_load_i_reg[0]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[1]),
.Q(CNT_LOAD_DOUT),
.R(1'b0));
FDRE \counter_load_i_reg[10]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[11]),
.Q(counter_load_i[10]),
.R(1'b0));
FDRE \counter_load_i_reg[11]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[12]),
.Q(counter_load_i[11]),
.R(1'b0));
FDRE \counter_load_i_reg[12]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[13]),
.Q(counter_load_i[12]),
.R(1'b0));
FDRE \counter_load_i_reg[13]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[14]),
.Q(counter_load_i[13]),
.R(1'b0));
FDRE \counter_load_i_reg[14]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[15]),
.Q(counter_load_i[14]),
.R(1'b0));
FDRE \counter_load_i_reg[15]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[16]),
.Q(counter_load_i[15]),
.R(1'b0));
FDRE \counter_load_i_reg[16]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(\counter_load_i_reg[17]_srl15_n_0 ),
.Q(counter_load_i[16]),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[0].U_COUNTER /\counter_load_i_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[0].U_COUNTER /\counter_load_i_reg[17]_srl15 " *)
SRL16E \counter_load_i_reg[17]_srl15
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(CNT_LOAD_EN),
.CLK(CFG_CLK),
.D(CNT_LOAD_IN),
.Q(\counter_load_i_reg[17]_srl15_n_0 ));
FDRE \counter_load_i_reg[1]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[2]),
.Q(counter_load_i[1]),
.R(1'b0));
FDRE \counter_load_i_reg[2]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[3]),
.Q(counter_load_i[2]),
.R(1'b0));
FDRE \counter_load_i_reg[3]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[4]),
.Q(counter_load_i[3]),
.R(1'b0));
FDRE \counter_load_i_reg[4]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[5]),
.Q(counter_load_i[4]),
.R(1'b0));
FDRE \counter_load_i_reg[5]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[6]),
.Q(counter_load_i[5]),
.R(1'b0));
FDRE \counter_load_i_reg[6]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[7]),
.Q(counter_load_i[6]),
.R(1'b0));
FDRE \counter_load_i_reg[7]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[8]),
.Q(counter_load_i[7]),
.R(1'b0));
FDRE \counter_load_i_reg[8]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[9]),
.Q(counter_load_i[8]),
.R(1'b0));
FDRE \counter_load_i_reg[9]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[10]),
.Q(counter_load_i[9]),
.R(1'b0));
FDRE \counter_reg[0]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[0]_i_1_n_0 ),
.Q(counter[0]),
.R(1'b0));
FDRE \counter_reg[10]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[10]_i_1_n_0 ),
.Q(counter[10]),
.R(1'b0));
FDRE \counter_reg[11]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[11]_i_1_n_0 ),
.Q(counter[11]),
.R(1'b0));
FDRE \counter_reg[12]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[12]_i_1_n_0 ),
.Q(counter[12]),
.R(1'b0));
CARRY4 \counter_reg[12]_i_2
(.CI(\counter_reg[8]_i_2_n_0 ),
.CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[12:9]),
.S({\counter[12]_i_3_n_0 ,\counter[12]_i_4_n_0 ,\counter[12]_i_5_n_0 ,\counter[12]_i_6_n_0 }));
FDRE \counter_reg[13]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[13]_i_1_n_0 ),
.Q(counter[13]),
.R(1'b0));
FDRE \counter_reg[14]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[14]_i_1_n_0 ),
.Q(counter[14]),
.R(1'b0));
FDRE \counter_reg[15]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[15]_i_1_n_0 ),
.Q(counter[15]),
.R(1'b0));
FDRE \counter_reg[16]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[16]_i_2_n_0 ),
.Q(COUNTER_MATCH),
.R(1'b0));
CARRY4 \counter_reg[16]_i_4
(.CI(\counter_reg[12]_i_2_n_0 ),
.CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[16:13]),
.S({\counter[16]_i_5_n_0 ,\counter[16]_i_6_n_0 ,\counter[16]_i_7_n_0 ,\counter[16]_i_8_n_0 }));
FDRE \counter_reg[1]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[1]_i_1_n_0 ),
.Q(counter[1]),
.R(1'b0));
FDRE \counter_reg[2]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[2]_i_1_n_0 ),
.Q(counter[2]),
.R(1'b0));
FDRE \counter_reg[3]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[3]_i_1_n_0 ),
.Q(counter[3]),
.R(1'b0));
FDRE \counter_reg[4]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[4]_i_1_n_0 ),
.Q(counter[4]),
.R(1'b0));
CARRY4 \counter_reg[4]_i_2
(.CI(1'b0),
.CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
.CYINIT(counter[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[4:1]),
.S({\counter[4]_i_3_n_0 ,\counter[4]_i_4_n_0 ,\counter[4]_i_5_n_0 ,\counter[4]_i_6_n_0 }));
FDRE \counter_reg[5]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[5]_i_1_n_0 ),
.Q(counter[5]),
.R(1'b0));
FDRE \counter_reg[6]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[6]_i_1_n_0 ),
.Q(counter[6]),
.R(1'b0));
FDRE \counter_reg[7]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[7]_i_1_n_0 ),
.Q(counter[7]),
.R(1'b0));
FDRE \counter_reg[8]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[8]_i_1_n_0 ),
.Q(counter[8]),
.R(1'b0));
CARRY4 \counter_reg[8]_i_2
(.CI(\counter_reg[4]_i_2_n_0 ),
.CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[8:5]),
.S({\counter[8]_i_3_n_0 ,\counter[8]_i_4_n_0 ,\counter[8]_i_5_n_0 ,\counter[8]_i_6_n_0 }));
FDRE \counter_reg[9]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[9]_i_1_n_0 ),
.Q(counter[9]),
.R(1'b0));
endmodule | 8 |
2,138 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__5
(CLK,
CFG_CLK,
RESET,
SCNT_RESET,
CNT_CTRL,
CNT_LOAD_IN,
CNT_LOAD_EN,
CNT_LOAD_DOUT,
COUNTER_MATCH);
input CLK;
input CFG_CLK;
input [1:0]RESET;
input SCNT_RESET;
input [1:0]CNT_CTRL;
input CNT_LOAD_IN;
input CNT_LOAD_EN;
output CNT_LOAD_DOUT;
output COUNTER_MATCH;
wire CFG_CLK;
wire CLK;
wire [1:0]CNT_CTRL;
wire CNT_LOAD_DOUT;
wire CNT_LOAD_EN;
wire CNT_LOAD_IN;
wire COUNTER_MATCH;
wire [1:0]RESET;
wire SCNT_RESET;
wire [15:0]counter;
wire [16:1]counter0;
wire \counter[0]_i_1_n_0 ;
wire \counter[10]_i_1_n_0 ;
wire \counter[11]_i_1_n_0 ;
wire \counter[12]_i_1_n_0 ;
wire \counter[12]_i_3_n_0 ;
wire \counter[12]_i_4_n_0 ;
wire \counter[12]_i_5_n_0 ;
wire \counter[12]_i_6_n_0 ;
wire \counter[13]_i_1_n_0 ;
wire \counter[14]_i_1_n_0 ;
wire \counter[15]_i_1_n_0 ;
wire \counter[16]_i_1_n_0 ;
wire \counter[16]_i_2_n_0 ;
wire \counter[16]_i_3_n_0 ;
wire \counter[16]_i_5_n_0 ;
wire \counter[16]_i_6_n_0 ;
wire \counter[16]_i_7_n_0 ;
wire \counter[16]_i_8_n_0 ;
wire \counter[1]_i_1_n_0 ;
wire \counter[2]_i_1_n_0 ;
wire \counter[3]_i_1_n_0 ;
wire \counter[4]_i_1_n_0 ;
wire \counter[4]_i_3_n_0 ;
wire \counter[4]_i_4_n_0 ;
wire \counter[4]_i_5_n_0 ;
wire \counter[4]_i_6_n_0 ;
wire \counter[5]_i_1_n_0 ;
wire \counter[6]_i_1_n_0 ;
wire \counter[7]_i_1_n_0 ;
wire \counter[8]_i_1_n_0 ;
wire \counter[8]_i_3_n_0 ;
wire \counter[8]_i_4_n_0 ;
wire \counter[8]_i_5_n_0 ;
wire \counter[8]_i_6_n_0 ;
wire \counter[9]_i_1_n_0 ;
wire [16:1]counter_load_i;
wire \counter_load_i_reg[17]_srl15_n_0 ;
wire \counter_reg[12]_i_2_n_0 ;
wire \counter_reg[12]_i_2_n_1 ;
wire \counter_reg[12]_i_2_n_2 ;
wire \counter_reg[12]_i_2_n_3 ;
wire \counter_reg[16]_i_4_n_1 ;
wire \counter_reg[16]_i_4_n_2 ;
wire \counter_reg[16]_i_4_n_3 ;
wire \counter_reg[4]_i_2_n_0 ;
wire \counter_reg[4]_i_2_n_1 ;
wire \counter_reg[4]_i_2_n_2 ;
wire \counter_reg[4]_i_2_n_3 ;
wire \counter_reg[8]_i_2_n_0 ;
wire \counter_reg[8]_i_2_n_1 ;
wire \counter_reg[8]_i_2_n_2 ;
wire \counter_reg[8]_i_2_n_3 ;
wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;
LUT4 #(
.INIT(16'hAACF))
\counter[0]_i_1
(.I0(CNT_LOAD_DOUT),
.I1(COUNTER_MATCH),
.I2(counter[0]),
.I3(\counter[16]_i_3_n_0 ),
.O(\counter[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[10]_i_1
(.I0(counter_load_i[10]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[10]),
.I3(COUNTER_MATCH),
.O(\counter[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[11]_i_1
(.I0(counter_load_i[11]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[11]),
.I3(COUNTER_MATCH),
.O(\counter[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[12]_i_1
(.I0(counter_load_i[12]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[12]),
.I3(COUNTER_MATCH),
.O(\counter[12]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_3
(.I0(counter[12]),
.O(\counter[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_4
(.I0(counter[11]),
.O(\counter[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_5
(.I0(counter[10]),
.O(\counter[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_6
(.I0(counter[9]),
.O(\counter[12]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[13]_i_1
(.I0(counter_load_i[13]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[13]),
.I3(COUNTER_MATCH),
.O(\counter[13]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[14]_i_1
(.I0(counter_load_i[14]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[14]),
.I3(COUNTER_MATCH),
.O(\counter[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[15]_i_1
(.I0(counter_load_i[15]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[15]),
.I3(COUNTER_MATCH),
.O(\counter[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFEFEE))
\counter[16]_i_1
(.I0(CNT_CTRL[0]),
.I1(SCNT_RESET),
.I2(RESET[0]),
.I3(RESET[1]),
.I4(CNT_CTRL[1]),
.O(\counter[16]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[16]_i_2
(.I0(counter_load_i[16]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[16]),
.I3(COUNTER_MATCH),
.O(\counter[16]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFAE))
\counter[16]_i_3
(.I0(CNT_CTRL[0]),
.I1(RESET[1]),
.I2(RESET[0]),
.I3(SCNT_RESET),
.O(\counter[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_5
(.I0(COUNTER_MATCH),
.O(\counter[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_6
(.I0(counter[15]),
.O(\counter[16]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_7
(.I0(counter[14]),
.O(\counter[16]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_8
(.I0(counter[13]),
.O(\counter[16]_i_8_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[1]_i_1
(.I0(counter_load_i[1]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[1]),
.I3(COUNTER_MATCH),
.O(\counter[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[2]_i_1
(.I0(counter_load_i[2]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[2]),
.I3(COUNTER_MATCH),
.O(\counter[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[3]_i_1
(.I0(counter_load_i[3]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[3]),
.I3(COUNTER_MATCH),
.O(\counter[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[4]_i_1
(.I0(counter_load_i[4]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[4]),
.I3(COUNTER_MATCH),
.O(\counter[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_3
(.I0(counter[4]),
.O(\counter[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_4
(.I0(counter[3]),
.O(\counter[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_5
(.I0(counter[2]),
.O(\counter[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_6
(.I0(counter[1]),
.O(\counter[4]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[5]_i_1
(.I0(counter_load_i[5]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[5]),
.I3(COUNTER_MATCH),
.O(\counter[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[6]_i_1
(.I0(counter_load_i[6]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[6]),
.I3(COUNTER_MATCH),
.O(\counter[6]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[7]_i_1
(.I0(counter_load_i[7]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[7]),
.I3(COUNTER_MATCH),
.O(\counter[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[8]_i_1
(.I0(counter_load_i[8]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[8]),
.I3(COUNTER_MATCH),
.O(\counter[8]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_3
(.I0(counter[8]),
.O(\counter[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_4
(.I0(counter[7]),
.O(\counter[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_5
(.I0(counter[6]),
.O(\counter[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_6
(.I0(counter[5]),
.O(\counter[8]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[9]_i_1
(.I0(counter_load_i[9]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[9]),
.I3(COUNTER_MATCH),
.O(\counter[9]_i_1_n_0 ));
FDRE \counter_load_i_reg[0]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[1]),
.Q(CNT_LOAD_DOUT),
.R(1'b0));
FDRE \counter_load_i_reg[10]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[11]),
.Q(counter_load_i[10]),
.R(1'b0));
FDRE \counter_load_i_reg[11]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[12]),
.Q(counter_load_i[11]),
.R(1'b0));
FDRE \counter_load_i_reg[12]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[13]),
.Q(counter_load_i[12]),
.R(1'b0));
FDRE \counter_load_i_reg[13]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[14]),
.Q(counter_load_i[13]),
.R(1'b0));
FDRE \counter_load_i_reg[14]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[15]),
.Q(counter_load_i[14]),
.R(1'b0));
FDRE \counter_load_i_reg[15]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[16]),
.Q(counter_load_i[15]),
.R(1'b0));
FDRE \counter_load_i_reg[16]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(\counter_load_i_reg[17]_srl15_n_0 ),
.Q(counter_load_i[16]),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[1].U_COUNTER /\counter_load_i_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[1].U_COUNTER /\counter_load_i_reg[17]_srl15 " *)
SRL16E \counter_load_i_reg[17]_srl15
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(CNT_LOAD_EN),
.CLK(CFG_CLK),
.D(CNT_LOAD_IN),
.Q(\counter_load_i_reg[17]_srl15_n_0 ));
FDRE \counter_load_i_reg[1]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[2]),
.Q(counter_load_i[1]),
.R(1'b0));
FDRE \counter_load_i_reg[2]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[3]),
.Q(counter_load_i[2]),
.R(1'b0));
FDRE \counter_load_i_reg[3]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[4]),
.Q(counter_load_i[3]),
.R(1'b0));
FDRE \counter_load_i_reg[4]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[5]),
.Q(counter_load_i[4]),
.R(1'b0));
FDRE \counter_load_i_reg[5]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[6]),
.Q(counter_load_i[5]),
.R(1'b0));
FDRE \counter_load_i_reg[6]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[7]),
.Q(counter_load_i[6]),
.R(1'b0));
FDRE \counter_load_i_reg[7]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[8]),
.Q(counter_load_i[7]),
.R(1'b0));
FDRE \counter_load_i_reg[8]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[9]),
.Q(counter_load_i[8]),
.R(1'b0));
FDRE \counter_load_i_reg[9]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[10]),
.Q(counter_load_i[9]),
.R(1'b0));
FDRE \counter_reg[0]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[0]_i_1_n_0 ),
.Q(counter[0]),
.R(1'b0));
FDRE \counter_reg[10]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[10]_i_1_n_0 ),
.Q(counter[10]),
.R(1'b0));
FDRE \counter_reg[11]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[11]_i_1_n_0 ),
.Q(counter[11]),
.R(1'b0));
FDRE \counter_reg[12]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[12]_i_1_n_0 ),
.Q(counter[12]),
.R(1'b0));
CARRY4 \counter_reg[12]_i_2
(.CI(\counter_reg[8]_i_2_n_0 ),
.CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[12:9]),
.S({\counter[12]_i_3_n_0 ,\counter[12]_i_4_n_0 ,\counter[12]_i_5_n_0 ,\counter[12]_i_6_n_0 }));
FDRE \counter_reg[13]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[13]_i_1_n_0 ),
.Q(counter[13]),
.R(1'b0));
FDRE \counter_reg[14]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[14]_i_1_n_0 ),
.Q(counter[14]),
.R(1'b0));
FDRE \counter_reg[15]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[15]_i_1_n_0 ),
.Q(counter[15]),
.R(1'b0));
FDRE \counter_reg[16]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[16]_i_2_n_0 ),
.Q(COUNTER_MATCH),
.R(1'b0));
CARRY4 \counter_reg[16]_i_4
(.CI(\counter_reg[12]_i_2_n_0 ),
.CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[16:13]),
.S({\counter[16]_i_5_n_0 ,\counter[16]_i_6_n_0 ,\counter[16]_i_7_n_0 ,\counter[16]_i_8_n_0 }));
FDRE \counter_reg[1]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[1]_i_1_n_0 ),
.Q(counter[1]),
.R(1'b0));
FDRE \counter_reg[2]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[2]_i_1_n_0 ),
.Q(counter[2]),
.R(1'b0));
FDRE \counter_reg[3]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[3]_i_1_n_0 ),
.Q(counter[3]),
.R(1'b0));
FDRE \counter_reg[4]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[4]_i_1_n_0 ),
.Q(counter[4]),
.R(1'b0));
CARRY4 \counter_reg[4]_i_2
(.CI(1'b0),
.CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
.CYINIT(counter[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[4:1]),
.S({\counter[4]_i_3_n_0 ,\counter[4]_i_4_n_0 ,\counter[4]_i_5_n_0 ,\counter[4]_i_6_n_0 }));
FDRE \counter_reg[5]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[5]_i_1_n_0 ),
.Q(counter[5]),
.R(1'b0));
FDRE \counter_reg[6]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[6]_i_1_n_0 ),
.Q(counter[6]),
.R(1'b0));
FDRE \counter_reg[7]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[7]_i_1_n_0 ),
.Q(counter[7]),
.R(1'b0));
FDRE \counter_reg[8]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[8]_i_1_n_0 ),
.Q(counter[8]),
.R(1'b0));
CARRY4 \counter_reg[8]_i_2
(.CI(\counter_reg[4]_i_2_n_0 ),
.CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[8:5]),
.S({\counter[8]_i_3_n_0 ,\counter[8]_i_4_n_0 ,\counter[8]_i_5_n_0 ,\counter[8]_i_6_n_0 }));
FDRE \counter_reg[9]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[9]_i_1_n_0 ),
.Q(counter[9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__5
(CLK,
CFG_CLK,
RESET,
SCNT_RESET,
CNT_CTRL,
CNT_LOAD_IN,
CNT_LOAD_EN,
CNT_LOAD_DOUT,
COUNTER_MATCH); |
input CLK;
input CFG_CLK;
input [1:0]RESET;
input SCNT_RESET;
input [1:0]CNT_CTRL;
input CNT_LOAD_IN;
input CNT_LOAD_EN;
output CNT_LOAD_DOUT;
output COUNTER_MATCH;
wire CFG_CLK;
wire CLK;
wire [1:0]CNT_CTRL;
wire CNT_LOAD_DOUT;
wire CNT_LOAD_EN;
wire CNT_LOAD_IN;
wire COUNTER_MATCH;
wire [1:0]RESET;
wire SCNT_RESET;
wire [15:0]counter;
wire [16:1]counter0;
wire \counter[0]_i_1_n_0 ;
wire \counter[10]_i_1_n_0 ;
wire \counter[11]_i_1_n_0 ;
wire \counter[12]_i_1_n_0 ;
wire \counter[12]_i_3_n_0 ;
wire \counter[12]_i_4_n_0 ;
wire \counter[12]_i_5_n_0 ;
wire \counter[12]_i_6_n_0 ;
wire \counter[13]_i_1_n_0 ;
wire \counter[14]_i_1_n_0 ;
wire \counter[15]_i_1_n_0 ;
wire \counter[16]_i_1_n_0 ;
wire \counter[16]_i_2_n_0 ;
wire \counter[16]_i_3_n_0 ;
wire \counter[16]_i_5_n_0 ;
wire \counter[16]_i_6_n_0 ;
wire \counter[16]_i_7_n_0 ;
wire \counter[16]_i_8_n_0 ;
wire \counter[1]_i_1_n_0 ;
wire \counter[2]_i_1_n_0 ;
wire \counter[3]_i_1_n_0 ;
wire \counter[4]_i_1_n_0 ;
wire \counter[4]_i_3_n_0 ;
wire \counter[4]_i_4_n_0 ;
wire \counter[4]_i_5_n_0 ;
wire \counter[4]_i_6_n_0 ;
wire \counter[5]_i_1_n_0 ;
wire \counter[6]_i_1_n_0 ;
wire \counter[7]_i_1_n_0 ;
wire \counter[8]_i_1_n_0 ;
wire \counter[8]_i_3_n_0 ;
wire \counter[8]_i_4_n_0 ;
wire \counter[8]_i_5_n_0 ;
wire \counter[8]_i_6_n_0 ;
wire \counter[9]_i_1_n_0 ;
wire [16:1]counter_load_i;
wire \counter_load_i_reg[17]_srl15_n_0 ;
wire \counter_reg[12]_i_2_n_0 ;
wire \counter_reg[12]_i_2_n_1 ;
wire \counter_reg[12]_i_2_n_2 ;
wire \counter_reg[12]_i_2_n_3 ;
wire \counter_reg[16]_i_4_n_1 ;
wire \counter_reg[16]_i_4_n_2 ;
wire \counter_reg[16]_i_4_n_3 ;
wire \counter_reg[4]_i_2_n_0 ;
wire \counter_reg[4]_i_2_n_1 ;
wire \counter_reg[4]_i_2_n_2 ;
wire \counter_reg[4]_i_2_n_3 ;
wire \counter_reg[8]_i_2_n_0 ;
wire \counter_reg[8]_i_2_n_1 ;
wire \counter_reg[8]_i_2_n_2 ;
wire \counter_reg[8]_i_2_n_3 ;
wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;
LUT4 #(
.INIT(16'hAACF))
\counter[0]_i_1
(.I0(CNT_LOAD_DOUT),
.I1(COUNTER_MATCH),
.I2(counter[0]),
.I3(\counter[16]_i_3_n_0 ),
.O(\counter[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[10]_i_1
(.I0(counter_load_i[10]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[10]),
.I3(COUNTER_MATCH),
.O(\counter[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[11]_i_1
(.I0(counter_load_i[11]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[11]),
.I3(COUNTER_MATCH),
.O(\counter[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[12]_i_1
(.I0(counter_load_i[12]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[12]),
.I3(COUNTER_MATCH),
.O(\counter[12]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_3
(.I0(counter[12]),
.O(\counter[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_4
(.I0(counter[11]),
.O(\counter[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_5
(.I0(counter[10]),
.O(\counter[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_6
(.I0(counter[9]),
.O(\counter[12]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[13]_i_1
(.I0(counter_load_i[13]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[13]),
.I3(COUNTER_MATCH),
.O(\counter[13]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[14]_i_1
(.I0(counter_load_i[14]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[14]),
.I3(COUNTER_MATCH),
.O(\counter[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[15]_i_1
(.I0(counter_load_i[15]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[15]),
.I3(COUNTER_MATCH),
.O(\counter[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFEFEE))
\counter[16]_i_1
(.I0(CNT_CTRL[0]),
.I1(SCNT_RESET),
.I2(RESET[0]),
.I3(RESET[1]),
.I4(CNT_CTRL[1]),
.O(\counter[16]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[16]_i_2
(.I0(counter_load_i[16]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[16]),
.I3(COUNTER_MATCH),
.O(\counter[16]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFAE))
\counter[16]_i_3
(.I0(CNT_CTRL[0]),
.I1(RESET[1]),
.I2(RESET[0]),
.I3(SCNT_RESET),
.O(\counter[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_5
(.I0(COUNTER_MATCH),
.O(\counter[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_6
(.I0(counter[15]),
.O(\counter[16]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_7
(.I0(counter[14]),
.O(\counter[16]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_8
(.I0(counter[13]),
.O(\counter[16]_i_8_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[1]_i_1
(.I0(counter_load_i[1]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[1]),
.I3(COUNTER_MATCH),
.O(\counter[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[2]_i_1
(.I0(counter_load_i[2]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[2]),
.I3(COUNTER_MATCH),
.O(\counter[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[3]_i_1
(.I0(counter_load_i[3]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[3]),
.I3(COUNTER_MATCH),
.O(\counter[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[4]_i_1
(.I0(counter_load_i[4]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[4]),
.I3(COUNTER_MATCH),
.O(\counter[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_3
(.I0(counter[4]),
.O(\counter[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_4
(.I0(counter[3]),
.O(\counter[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_5
(.I0(counter[2]),
.O(\counter[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_6
(.I0(counter[1]),
.O(\counter[4]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[5]_i_1
(.I0(counter_load_i[5]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[5]),
.I3(COUNTER_MATCH),
.O(\counter[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[6]_i_1
(.I0(counter_load_i[6]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[6]),
.I3(COUNTER_MATCH),
.O(\counter[6]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[7]_i_1
(.I0(counter_load_i[7]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[7]),
.I3(COUNTER_MATCH),
.O(\counter[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[8]_i_1
(.I0(counter_load_i[8]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[8]),
.I3(COUNTER_MATCH),
.O(\counter[8]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_3
(.I0(counter[8]),
.O(\counter[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_4
(.I0(counter[7]),
.O(\counter[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_5
(.I0(counter[6]),
.O(\counter[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_6
(.I0(counter[5]),
.O(\counter[8]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[9]_i_1
(.I0(counter_load_i[9]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[9]),
.I3(COUNTER_MATCH),
.O(\counter[9]_i_1_n_0 ));
FDRE \counter_load_i_reg[0]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[1]),
.Q(CNT_LOAD_DOUT),
.R(1'b0));
FDRE \counter_load_i_reg[10]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[11]),
.Q(counter_load_i[10]),
.R(1'b0));
FDRE \counter_load_i_reg[11]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[12]),
.Q(counter_load_i[11]),
.R(1'b0));
FDRE \counter_load_i_reg[12]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[13]),
.Q(counter_load_i[12]),
.R(1'b0));
FDRE \counter_load_i_reg[13]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[14]),
.Q(counter_load_i[13]),
.R(1'b0));
FDRE \counter_load_i_reg[14]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[15]),
.Q(counter_load_i[14]),
.R(1'b0));
FDRE \counter_load_i_reg[15]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[16]),
.Q(counter_load_i[15]),
.R(1'b0));
FDRE \counter_load_i_reg[16]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(\counter_load_i_reg[17]_srl15_n_0 ),
.Q(counter_load_i[16]),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[1].U_COUNTER /\counter_load_i_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[1].U_COUNTER /\counter_load_i_reg[17]_srl15 " *)
SRL16E \counter_load_i_reg[17]_srl15
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(CNT_LOAD_EN),
.CLK(CFG_CLK),
.D(CNT_LOAD_IN),
.Q(\counter_load_i_reg[17]_srl15_n_0 ));
FDRE \counter_load_i_reg[1]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[2]),
.Q(counter_load_i[1]),
.R(1'b0));
FDRE \counter_load_i_reg[2]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[3]),
.Q(counter_load_i[2]),
.R(1'b0));
FDRE \counter_load_i_reg[3]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[4]),
.Q(counter_load_i[3]),
.R(1'b0));
FDRE \counter_load_i_reg[4]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[5]),
.Q(counter_load_i[4]),
.R(1'b0));
FDRE \counter_load_i_reg[5]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[6]),
.Q(counter_load_i[5]),
.R(1'b0));
FDRE \counter_load_i_reg[6]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[7]),
.Q(counter_load_i[6]),
.R(1'b0));
FDRE \counter_load_i_reg[7]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[8]),
.Q(counter_load_i[7]),
.R(1'b0));
FDRE \counter_load_i_reg[8]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[9]),
.Q(counter_load_i[8]),
.R(1'b0));
FDRE \counter_load_i_reg[9]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[10]),
.Q(counter_load_i[9]),
.R(1'b0));
FDRE \counter_reg[0]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[0]_i_1_n_0 ),
.Q(counter[0]),
.R(1'b0));
FDRE \counter_reg[10]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[10]_i_1_n_0 ),
.Q(counter[10]),
.R(1'b0));
FDRE \counter_reg[11]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[11]_i_1_n_0 ),
.Q(counter[11]),
.R(1'b0));
FDRE \counter_reg[12]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[12]_i_1_n_0 ),
.Q(counter[12]),
.R(1'b0));
CARRY4 \counter_reg[12]_i_2
(.CI(\counter_reg[8]_i_2_n_0 ),
.CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[12:9]),
.S({\counter[12]_i_3_n_0 ,\counter[12]_i_4_n_0 ,\counter[12]_i_5_n_0 ,\counter[12]_i_6_n_0 }));
FDRE \counter_reg[13]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[13]_i_1_n_0 ),
.Q(counter[13]),
.R(1'b0));
FDRE \counter_reg[14]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[14]_i_1_n_0 ),
.Q(counter[14]),
.R(1'b0));
FDRE \counter_reg[15]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[15]_i_1_n_0 ),
.Q(counter[15]),
.R(1'b0));
FDRE \counter_reg[16]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[16]_i_2_n_0 ),
.Q(COUNTER_MATCH),
.R(1'b0));
CARRY4 \counter_reg[16]_i_4
(.CI(\counter_reg[12]_i_2_n_0 ),
.CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[16:13]),
.S({\counter[16]_i_5_n_0 ,\counter[16]_i_6_n_0 ,\counter[16]_i_7_n_0 ,\counter[16]_i_8_n_0 }));
FDRE \counter_reg[1]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[1]_i_1_n_0 ),
.Q(counter[1]),
.R(1'b0));
FDRE \counter_reg[2]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[2]_i_1_n_0 ),
.Q(counter[2]),
.R(1'b0));
FDRE \counter_reg[3]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[3]_i_1_n_0 ),
.Q(counter[3]),
.R(1'b0));
FDRE \counter_reg[4]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[4]_i_1_n_0 ),
.Q(counter[4]),
.R(1'b0));
CARRY4 \counter_reg[4]_i_2
(.CI(1'b0),
.CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
.CYINIT(counter[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[4:1]),
.S({\counter[4]_i_3_n_0 ,\counter[4]_i_4_n_0 ,\counter[4]_i_5_n_0 ,\counter[4]_i_6_n_0 }));
FDRE \counter_reg[5]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[5]_i_1_n_0 ),
.Q(counter[5]),
.R(1'b0));
FDRE \counter_reg[6]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[6]_i_1_n_0 ),
.Q(counter[6]),
.R(1'b0));
FDRE \counter_reg[7]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[7]_i_1_n_0 ),
.Q(counter[7]),
.R(1'b0));
FDRE \counter_reg[8]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[8]_i_1_n_0 ),
.Q(counter[8]),
.R(1'b0));
CARRY4 \counter_reg[8]_i_2
(.CI(\counter_reg[4]_i_2_n_0 ),
.CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[8:5]),
.S({\counter[8]_i_3_n_0 ,\counter[8]_i_4_n_0 ,\counter[8]_i_5_n_0 ,\counter[8]_i_6_n_0 }));
FDRE \counter_reg[9]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[9]_i_1_n_0 ),
.Q(counter[9]),
.R(1'b0));
endmodule | 8 |
2,139 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__6
(CLK,
CFG_CLK,
RESET,
SCNT_RESET,
CNT_CTRL,
CNT_LOAD_IN,
CNT_LOAD_EN,
CNT_LOAD_DOUT,
COUNTER_MATCH);
input CLK;
input CFG_CLK;
input [1:0]RESET;
input SCNT_RESET;
input [1:0]CNT_CTRL;
input CNT_LOAD_IN;
input CNT_LOAD_EN;
output CNT_LOAD_DOUT;
output COUNTER_MATCH;
wire CFG_CLK;
wire CLK;
wire [1:0]CNT_CTRL;
wire CNT_LOAD_DOUT;
wire CNT_LOAD_EN;
wire CNT_LOAD_IN;
wire COUNTER_MATCH;
wire [1:0]RESET;
wire SCNT_RESET;
wire [15:0]counter;
wire [16:1]counter0;
wire \counter[0]_i_1_n_0 ;
wire \counter[10]_i_1_n_0 ;
wire \counter[11]_i_1_n_0 ;
wire \counter[12]_i_1_n_0 ;
wire \counter[12]_i_3_n_0 ;
wire \counter[12]_i_4_n_0 ;
wire \counter[12]_i_5_n_0 ;
wire \counter[12]_i_6_n_0 ;
wire \counter[13]_i_1_n_0 ;
wire \counter[14]_i_1_n_0 ;
wire \counter[15]_i_1_n_0 ;
wire \counter[16]_i_1_n_0 ;
wire \counter[16]_i_2_n_0 ;
wire \counter[16]_i_3_n_0 ;
wire \counter[16]_i_5_n_0 ;
wire \counter[16]_i_6_n_0 ;
wire \counter[16]_i_7_n_0 ;
wire \counter[16]_i_8_n_0 ;
wire \counter[1]_i_1_n_0 ;
wire \counter[2]_i_1_n_0 ;
wire \counter[3]_i_1_n_0 ;
wire \counter[4]_i_1_n_0 ;
wire \counter[4]_i_3_n_0 ;
wire \counter[4]_i_4_n_0 ;
wire \counter[4]_i_5_n_0 ;
wire \counter[4]_i_6_n_0 ;
wire \counter[5]_i_1_n_0 ;
wire \counter[6]_i_1_n_0 ;
wire \counter[7]_i_1_n_0 ;
wire \counter[8]_i_1_n_0 ;
wire \counter[8]_i_3_n_0 ;
wire \counter[8]_i_4_n_0 ;
wire \counter[8]_i_5_n_0 ;
wire \counter[8]_i_6_n_0 ;
wire \counter[9]_i_1_n_0 ;
wire [16:1]counter_load_i;
wire \counter_load_i_reg[17]_srl15_n_0 ;
wire \counter_reg[12]_i_2_n_0 ;
wire \counter_reg[12]_i_2_n_1 ;
wire \counter_reg[12]_i_2_n_2 ;
wire \counter_reg[12]_i_2_n_3 ;
wire \counter_reg[16]_i_4_n_1 ;
wire \counter_reg[16]_i_4_n_2 ;
wire \counter_reg[16]_i_4_n_3 ;
wire \counter_reg[4]_i_2_n_0 ;
wire \counter_reg[4]_i_2_n_1 ;
wire \counter_reg[4]_i_2_n_2 ;
wire \counter_reg[4]_i_2_n_3 ;
wire \counter_reg[8]_i_2_n_0 ;
wire \counter_reg[8]_i_2_n_1 ;
wire \counter_reg[8]_i_2_n_2 ;
wire \counter_reg[8]_i_2_n_3 ;
wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;
LUT4 #(
.INIT(16'hAACF))
\counter[0]_i_1
(.I0(CNT_LOAD_DOUT),
.I1(COUNTER_MATCH),
.I2(counter[0]),
.I3(\counter[16]_i_3_n_0 ),
.O(\counter[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[10]_i_1
(.I0(counter_load_i[10]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[10]),
.I3(COUNTER_MATCH),
.O(\counter[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[11]_i_1
(.I0(counter_load_i[11]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[11]),
.I3(COUNTER_MATCH),
.O(\counter[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[12]_i_1
(.I0(counter_load_i[12]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[12]),
.I3(COUNTER_MATCH),
.O(\counter[12]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_3
(.I0(counter[12]),
.O(\counter[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_4
(.I0(counter[11]),
.O(\counter[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_5
(.I0(counter[10]),
.O(\counter[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_6
(.I0(counter[9]),
.O(\counter[12]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[13]_i_1
(.I0(counter_load_i[13]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[13]),
.I3(COUNTER_MATCH),
.O(\counter[13]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[14]_i_1
(.I0(counter_load_i[14]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[14]),
.I3(COUNTER_MATCH),
.O(\counter[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[15]_i_1
(.I0(counter_load_i[15]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[15]),
.I3(COUNTER_MATCH),
.O(\counter[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFEFEE))
\counter[16]_i_1
(.I0(CNT_CTRL[0]),
.I1(SCNT_RESET),
.I2(RESET[0]),
.I3(RESET[1]),
.I4(CNT_CTRL[1]),
.O(\counter[16]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[16]_i_2
(.I0(counter_load_i[16]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[16]),
.I3(COUNTER_MATCH),
.O(\counter[16]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFAE))
\counter[16]_i_3
(.I0(CNT_CTRL[0]),
.I1(RESET[1]),
.I2(RESET[0]),
.I3(SCNT_RESET),
.O(\counter[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_5
(.I0(COUNTER_MATCH),
.O(\counter[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_6
(.I0(counter[15]),
.O(\counter[16]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_7
(.I0(counter[14]),
.O(\counter[16]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_8
(.I0(counter[13]),
.O(\counter[16]_i_8_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[1]_i_1
(.I0(counter_load_i[1]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[1]),
.I3(COUNTER_MATCH),
.O(\counter[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[2]_i_1
(.I0(counter_load_i[2]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[2]),
.I3(COUNTER_MATCH),
.O(\counter[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[3]_i_1
(.I0(counter_load_i[3]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[3]),
.I3(COUNTER_MATCH),
.O(\counter[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[4]_i_1
(.I0(counter_load_i[4]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[4]),
.I3(COUNTER_MATCH),
.O(\counter[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_3
(.I0(counter[4]),
.O(\counter[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_4
(.I0(counter[3]),
.O(\counter[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_5
(.I0(counter[2]),
.O(\counter[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_6
(.I0(counter[1]),
.O(\counter[4]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[5]_i_1
(.I0(counter_load_i[5]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[5]),
.I3(COUNTER_MATCH),
.O(\counter[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[6]_i_1
(.I0(counter_load_i[6]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[6]),
.I3(COUNTER_MATCH),
.O(\counter[6]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[7]_i_1
(.I0(counter_load_i[7]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[7]),
.I3(COUNTER_MATCH),
.O(\counter[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[8]_i_1
(.I0(counter_load_i[8]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[8]),
.I3(COUNTER_MATCH),
.O(\counter[8]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_3
(.I0(counter[8]),
.O(\counter[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_4
(.I0(counter[7]),
.O(\counter[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_5
(.I0(counter[6]),
.O(\counter[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_6
(.I0(counter[5]),
.O(\counter[8]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[9]_i_1
(.I0(counter_load_i[9]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[9]),
.I3(COUNTER_MATCH),
.O(\counter[9]_i_1_n_0 ));
FDRE \counter_load_i_reg[0]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[1]),
.Q(CNT_LOAD_DOUT),
.R(1'b0));
FDRE \counter_load_i_reg[10]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[11]),
.Q(counter_load_i[10]),
.R(1'b0));
FDRE \counter_load_i_reg[11]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[12]),
.Q(counter_load_i[11]),
.R(1'b0));
FDRE \counter_load_i_reg[12]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[13]),
.Q(counter_load_i[12]),
.R(1'b0));
FDRE \counter_load_i_reg[13]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[14]),
.Q(counter_load_i[13]),
.R(1'b0));
FDRE \counter_load_i_reg[14]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[15]),
.Q(counter_load_i[14]),
.R(1'b0));
FDRE \counter_load_i_reg[15]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[16]),
.Q(counter_load_i[15]),
.R(1'b0));
FDRE \counter_load_i_reg[16]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(\counter_load_i_reg[17]_srl15_n_0 ),
.Q(counter_load_i[16]),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[2].U_COUNTER /\counter_load_i_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[2].U_COUNTER /\counter_load_i_reg[17]_srl15 " *)
SRL16E \counter_load_i_reg[17]_srl15
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(CNT_LOAD_EN),
.CLK(CFG_CLK),
.D(CNT_LOAD_IN),
.Q(\counter_load_i_reg[17]_srl15_n_0 ));
FDRE \counter_load_i_reg[1]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[2]),
.Q(counter_load_i[1]),
.R(1'b0));
FDRE \counter_load_i_reg[2]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[3]),
.Q(counter_load_i[2]),
.R(1'b0));
FDRE \counter_load_i_reg[3]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[4]),
.Q(counter_load_i[3]),
.R(1'b0));
FDRE \counter_load_i_reg[4]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[5]),
.Q(counter_load_i[4]),
.R(1'b0));
FDRE \counter_load_i_reg[5]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[6]),
.Q(counter_load_i[5]),
.R(1'b0));
FDRE \counter_load_i_reg[6]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[7]),
.Q(counter_load_i[6]),
.R(1'b0));
FDRE \counter_load_i_reg[7]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[8]),
.Q(counter_load_i[7]),
.R(1'b0));
FDRE \counter_load_i_reg[8]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[9]),
.Q(counter_load_i[8]),
.R(1'b0));
FDRE \counter_load_i_reg[9]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[10]),
.Q(counter_load_i[9]),
.R(1'b0));
FDRE \counter_reg[0]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[0]_i_1_n_0 ),
.Q(counter[0]),
.R(1'b0));
FDRE \counter_reg[10]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[10]_i_1_n_0 ),
.Q(counter[10]),
.R(1'b0));
FDRE \counter_reg[11]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[11]_i_1_n_0 ),
.Q(counter[11]),
.R(1'b0));
FDRE \counter_reg[12]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[12]_i_1_n_0 ),
.Q(counter[12]),
.R(1'b0));
CARRY4 \counter_reg[12]_i_2
(.CI(\counter_reg[8]_i_2_n_0 ),
.CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[12:9]),
.S({\counter[12]_i_3_n_0 ,\counter[12]_i_4_n_0 ,\counter[12]_i_5_n_0 ,\counter[12]_i_6_n_0 }));
FDRE \counter_reg[13]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[13]_i_1_n_0 ),
.Q(counter[13]),
.R(1'b0));
FDRE \counter_reg[14]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[14]_i_1_n_0 ),
.Q(counter[14]),
.R(1'b0));
FDRE \counter_reg[15]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[15]_i_1_n_0 ),
.Q(counter[15]),
.R(1'b0));
FDRE \counter_reg[16]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[16]_i_2_n_0 ),
.Q(COUNTER_MATCH),
.R(1'b0));
CARRY4 \counter_reg[16]_i_4
(.CI(\counter_reg[12]_i_2_n_0 ),
.CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[16:13]),
.S({\counter[16]_i_5_n_0 ,\counter[16]_i_6_n_0 ,\counter[16]_i_7_n_0 ,\counter[16]_i_8_n_0 }));
FDRE \counter_reg[1]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[1]_i_1_n_0 ),
.Q(counter[1]),
.R(1'b0));
FDRE \counter_reg[2]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[2]_i_1_n_0 ),
.Q(counter[2]),
.R(1'b0));
FDRE \counter_reg[3]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[3]_i_1_n_0 ),
.Q(counter[3]),
.R(1'b0));
FDRE \counter_reg[4]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[4]_i_1_n_0 ),
.Q(counter[4]),
.R(1'b0));
CARRY4 \counter_reg[4]_i_2
(.CI(1'b0),
.CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
.CYINIT(counter[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[4:1]),
.S({\counter[4]_i_3_n_0 ,\counter[4]_i_4_n_0 ,\counter[4]_i_5_n_0 ,\counter[4]_i_6_n_0 }));
FDRE \counter_reg[5]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[5]_i_1_n_0 ),
.Q(counter[5]),
.R(1'b0));
FDRE \counter_reg[6]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[6]_i_1_n_0 ),
.Q(counter[6]),
.R(1'b0));
FDRE \counter_reg[7]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[7]_i_1_n_0 ),
.Q(counter[7]),
.R(1'b0));
FDRE \counter_reg[8]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[8]_i_1_n_0 ),
.Q(counter[8]),
.R(1'b0));
CARRY4 \counter_reg[8]_i_2
(.CI(\counter_reg[4]_i_2_n_0 ),
.CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[8:5]),
.S({\counter[8]_i_3_n_0 ,\counter[8]_i_4_n_0 ,\counter[8]_i_5_n_0 ,\counter[8]_i_6_n_0 }));
FDRE \counter_reg[9]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[9]_i_1_n_0 ),
.Q(counter[9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__6
(CLK,
CFG_CLK,
RESET,
SCNT_RESET,
CNT_CTRL,
CNT_LOAD_IN,
CNT_LOAD_EN,
CNT_LOAD_DOUT,
COUNTER_MATCH); |
input CLK;
input CFG_CLK;
input [1:0]RESET;
input SCNT_RESET;
input [1:0]CNT_CTRL;
input CNT_LOAD_IN;
input CNT_LOAD_EN;
output CNT_LOAD_DOUT;
output COUNTER_MATCH;
wire CFG_CLK;
wire CLK;
wire [1:0]CNT_CTRL;
wire CNT_LOAD_DOUT;
wire CNT_LOAD_EN;
wire CNT_LOAD_IN;
wire COUNTER_MATCH;
wire [1:0]RESET;
wire SCNT_RESET;
wire [15:0]counter;
wire [16:1]counter0;
wire \counter[0]_i_1_n_0 ;
wire \counter[10]_i_1_n_0 ;
wire \counter[11]_i_1_n_0 ;
wire \counter[12]_i_1_n_0 ;
wire \counter[12]_i_3_n_0 ;
wire \counter[12]_i_4_n_0 ;
wire \counter[12]_i_5_n_0 ;
wire \counter[12]_i_6_n_0 ;
wire \counter[13]_i_1_n_0 ;
wire \counter[14]_i_1_n_0 ;
wire \counter[15]_i_1_n_0 ;
wire \counter[16]_i_1_n_0 ;
wire \counter[16]_i_2_n_0 ;
wire \counter[16]_i_3_n_0 ;
wire \counter[16]_i_5_n_0 ;
wire \counter[16]_i_6_n_0 ;
wire \counter[16]_i_7_n_0 ;
wire \counter[16]_i_8_n_0 ;
wire \counter[1]_i_1_n_0 ;
wire \counter[2]_i_1_n_0 ;
wire \counter[3]_i_1_n_0 ;
wire \counter[4]_i_1_n_0 ;
wire \counter[4]_i_3_n_0 ;
wire \counter[4]_i_4_n_0 ;
wire \counter[4]_i_5_n_0 ;
wire \counter[4]_i_6_n_0 ;
wire \counter[5]_i_1_n_0 ;
wire \counter[6]_i_1_n_0 ;
wire \counter[7]_i_1_n_0 ;
wire \counter[8]_i_1_n_0 ;
wire \counter[8]_i_3_n_0 ;
wire \counter[8]_i_4_n_0 ;
wire \counter[8]_i_5_n_0 ;
wire \counter[8]_i_6_n_0 ;
wire \counter[9]_i_1_n_0 ;
wire [16:1]counter_load_i;
wire \counter_load_i_reg[17]_srl15_n_0 ;
wire \counter_reg[12]_i_2_n_0 ;
wire \counter_reg[12]_i_2_n_1 ;
wire \counter_reg[12]_i_2_n_2 ;
wire \counter_reg[12]_i_2_n_3 ;
wire \counter_reg[16]_i_4_n_1 ;
wire \counter_reg[16]_i_4_n_2 ;
wire \counter_reg[16]_i_4_n_3 ;
wire \counter_reg[4]_i_2_n_0 ;
wire \counter_reg[4]_i_2_n_1 ;
wire \counter_reg[4]_i_2_n_2 ;
wire \counter_reg[4]_i_2_n_3 ;
wire \counter_reg[8]_i_2_n_0 ;
wire \counter_reg[8]_i_2_n_1 ;
wire \counter_reg[8]_i_2_n_2 ;
wire \counter_reg[8]_i_2_n_3 ;
wire [3:3]\NLW_counter_reg[16]_i_4_CO_UNCONNECTED ;
LUT4 #(
.INIT(16'hAACF))
\counter[0]_i_1
(.I0(CNT_LOAD_DOUT),
.I1(COUNTER_MATCH),
.I2(counter[0]),
.I3(\counter[16]_i_3_n_0 ),
.O(\counter[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[10]_i_1
(.I0(counter_load_i[10]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[10]),
.I3(COUNTER_MATCH),
.O(\counter[10]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[11]_i_1
(.I0(counter_load_i[11]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[11]),
.I3(COUNTER_MATCH),
.O(\counter[11]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[12]_i_1
(.I0(counter_load_i[12]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[12]),
.I3(COUNTER_MATCH),
.O(\counter[12]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_3
(.I0(counter[12]),
.O(\counter[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_4
(.I0(counter[11]),
.O(\counter[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_5
(.I0(counter[10]),
.O(\counter[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[12]_i_6
(.I0(counter[9]),
.O(\counter[12]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[13]_i_1
(.I0(counter_load_i[13]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[13]),
.I3(COUNTER_MATCH),
.O(\counter[13]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[14]_i_1
(.I0(counter_load_i[14]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[14]),
.I3(COUNTER_MATCH),
.O(\counter[14]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[15]_i_1
(.I0(counter_load_i[15]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[15]),
.I3(COUNTER_MATCH),
.O(\counter[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFFEFEE))
\counter[16]_i_1
(.I0(CNT_CTRL[0]),
.I1(SCNT_RESET),
.I2(RESET[0]),
.I3(RESET[1]),
.I4(CNT_CTRL[1]),
.O(\counter[16]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[16]_i_2
(.I0(counter_load_i[16]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[16]),
.I3(COUNTER_MATCH),
.O(\counter[16]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFAE))
\counter[16]_i_3
(.I0(CNT_CTRL[0]),
.I1(RESET[1]),
.I2(RESET[0]),
.I3(SCNT_RESET),
.O(\counter[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_5
(.I0(COUNTER_MATCH),
.O(\counter[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_6
(.I0(counter[15]),
.O(\counter[16]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_7
(.I0(counter[14]),
.O(\counter[16]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[16]_i_8
(.I0(counter[13]),
.O(\counter[16]_i_8_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[1]_i_1
(.I0(counter_load_i[1]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[1]),
.I3(COUNTER_MATCH),
.O(\counter[1]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[2]_i_1
(.I0(counter_load_i[2]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[2]),
.I3(COUNTER_MATCH),
.O(\counter[2]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[3]_i_1
(.I0(counter_load_i[3]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[3]),
.I3(COUNTER_MATCH),
.O(\counter[3]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[4]_i_1
(.I0(counter_load_i[4]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[4]),
.I3(COUNTER_MATCH),
.O(\counter[4]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_3
(.I0(counter[4]),
.O(\counter[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_4
(.I0(counter[3]),
.O(\counter[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_5
(.I0(counter[2]),
.O(\counter[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[4]_i_6
(.I0(counter[1]),
.O(\counter[4]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[5]_i_1
(.I0(counter_load_i[5]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[5]),
.I3(COUNTER_MATCH),
.O(\counter[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[6]_i_1
(.I0(counter_load_i[6]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[6]),
.I3(COUNTER_MATCH),
.O(\counter[6]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[7]_i_1
(.I0(counter_load_i[7]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[7]),
.I3(COUNTER_MATCH),
.O(\counter[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[8]_i_1
(.I0(counter_load_i[8]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[8]),
.I3(COUNTER_MATCH),
.O(\counter[8]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_3
(.I0(counter[8]),
.O(\counter[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_4
(.I0(counter[7]),
.O(\counter[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_5
(.I0(counter[6]),
.O(\counter[8]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\counter[8]_i_6
(.I0(counter[5]),
.O(\counter[8]_i_6_n_0 ));
LUT4 #(
.INIT(16'h88B8))
\counter[9]_i_1
(.I0(counter_load_i[9]),
.I1(\counter[16]_i_3_n_0 ),
.I2(counter0[9]),
.I3(COUNTER_MATCH),
.O(\counter[9]_i_1_n_0 ));
FDRE \counter_load_i_reg[0]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[1]),
.Q(CNT_LOAD_DOUT),
.R(1'b0));
FDRE \counter_load_i_reg[10]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[11]),
.Q(counter_load_i[10]),
.R(1'b0));
FDRE \counter_load_i_reg[11]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[12]),
.Q(counter_load_i[11]),
.R(1'b0));
FDRE \counter_load_i_reg[12]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[13]),
.Q(counter_load_i[12]),
.R(1'b0));
FDRE \counter_load_i_reg[13]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[14]),
.Q(counter_load_i[13]),
.R(1'b0));
FDRE \counter_load_i_reg[14]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[15]),
.Q(counter_load_i[14]),
.R(1'b0));
FDRE \counter_load_i_reg[15]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[16]),
.Q(counter_load_i[15]),
.R(1'b0));
FDRE \counter_load_i_reg[16]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(\counter_load_i_reg[17]_srl15_n_0 ),
.Q(counter_load_i[16]),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[2].U_COUNTER /\counter_load_i_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[2].U_COUNTER /\counter_load_i_reg[17]_srl15 " *)
SRL16E \counter_load_i_reg[17]_srl15
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(CNT_LOAD_EN),
.CLK(CFG_CLK),
.D(CNT_LOAD_IN),
.Q(\counter_load_i_reg[17]_srl15_n_0 ));
FDRE \counter_load_i_reg[1]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[2]),
.Q(counter_load_i[1]),
.R(1'b0));
FDRE \counter_load_i_reg[2]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[3]),
.Q(counter_load_i[2]),
.R(1'b0));
FDRE \counter_load_i_reg[3]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[4]),
.Q(counter_load_i[3]),
.R(1'b0));
FDRE \counter_load_i_reg[4]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[5]),
.Q(counter_load_i[4]),
.R(1'b0));
FDRE \counter_load_i_reg[5]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[6]),
.Q(counter_load_i[5]),
.R(1'b0));
FDRE \counter_load_i_reg[6]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[7]),
.Q(counter_load_i[6]),
.R(1'b0));
FDRE \counter_load_i_reg[7]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[8]),
.Q(counter_load_i[7]),
.R(1'b0));
FDRE \counter_load_i_reg[8]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[9]),
.Q(counter_load_i[8]),
.R(1'b0));
FDRE \counter_load_i_reg[9]
(.C(CFG_CLK),
.CE(CNT_LOAD_EN),
.D(counter_load_i[10]),
.Q(counter_load_i[9]),
.R(1'b0));
FDRE \counter_reg[0]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[0]_i_1_n_0 ),
.Q(counter[0]),
.R(1'b0));
FDRE \counter_reg[10]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[10]_i_1_n_0 ),
.Q(counter[10]),
.R(1'b0));
FDRE \counter_reg[11]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[11]_i_1_n_0 ),
.Q(counter[11]),
.R(1'b0));
FDRE \counter_reg[12]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[12]_i_1_n_0 ),
.Q(counter[12]),
.R(1'b0));
CARRY4 \counter_reg[12]_i_2
(.CI(\counter_reg[8]_i_2_n_0 ),
.CO({\counter_reg[12]_i_2_n_0 ,\counter_reg[12]_i_2_n_1 ,\counter_reg[12]_i_2_n_2 ,\counter_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[12:9]),
.S({\counter[12]_i_3_n_0 ,\counter[12]_i_4_n_0 ,\counter[12]_i_5_n_0 ,\counter[12]_i_6_n_0 }));
FDRE \counter_reg[13]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[13]_i_1_n_0 ),
.Q(counter[13]),
.R(1'b0));
FDRE \counter_reg[14]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[14]_i_1_n_0 ),
.Q(counter[14]),
.R(1'b0));
FDRE \counter_reg[15]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[15]_i_1_n_0 ),
.Q(counter[15]),
.R(1'b0));
FDRE \counter_reg[16]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[16]_i_2_n_0 ),
.Q(COUNTER_MATCH),
.R(1'b0));
CARRY4 \counter_reg[16]_i_4
(.CI(\counter_reg[12]_i_2_n_0 ),
.CO({\NLW_counter_reg[16]_i_4_CO_UNCONNECTED [3],\counter_reg[16]_i_4_n_1 ,\counter_reg[16]_i_4_n_2 ,\counter_reg[16]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[16:13]),
.S({\counter[16]_i_5_n_0 ,\counter[16]_i_6_n_0 ,\counter[16]_i_7_n_0 ,\counter[16]_i_8_n_0 }));
FDRE \counter_reg[1]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[1]_i_1_n_0 ),
.Q(counter[1]),
.R(1'b0));
FDRE \counter_reg[2]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[2]_i_1_n_0 ),
.Q(counter[2]),
.R(1'b0));
FDRE \counter_reg[3]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[3]_i_1_n_0 ),
.Q(counter[3]),
.R(1'b0));
FDRE \counter_reg[4]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[4]_i_1_n_0 ),
.Q(counter[4]),
.R(1'b0));
CARRY4 \counter_reg[4]_i_2
(.CI(1'b0),
.CO({\counter_reg[4]_i_2_n_0 ,\counter_reg[4]_i_2_n_1 ,\counter_reg[4]_i_2_n_2 ,\counter_reg[4]_i_2_n_3 }),
.CYINIT(counter[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[4:1]),
.S({\counter[4]_i_3_n_0 ,\counter[4]_i_4_n_0 ,\counter[4]_i_5_n_0 ,\counter[4]_i_6_n_0 }));
FDRE \counter_reg[5]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[5]_i_1_n_0 ),
.Q(counter[5]),
.R(1'b0));
FDRE \counter_reg[6]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[6]_i_1_n_0 ),
.Q(counter[6]),
.R(1'b0));
FDRE \counter_reg[7]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[7]_i_1_n_0 ),
.Q(counter[7]),
.R(1'b0));
FDRE \counter_reg[8]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[8]_i_1_n_0 ),
.Q(counter[8]),
.R(1'b0));
CARRY4 \counter_reg[8]_i_2
(.CI(\counter_reg[4]_i_2_n_0 ),
.CO({\counter_reg[8]_i_2_n_0 ,\counter_reg[8]_i_2_n_1 ,\counter_reg[8]_i_2_n_2 ,\counter_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(counter0[8:5]),
.S({\counter[8]_i_3_n_0 ,\counter[8]_i_4_n_0 ,\counter[8]_i_5_n_0 ,\counter[8]_i_6_n_0 }));
FDRE \counter_reg[9]
(.C(CLK),
.CE(\counter[16]_i_1_n_0 ),
.D(\counter[9]_i_1_n_0 ),
.Q(counter[9]),
.R(1'b0));
endmodule | 8 |
2,140 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila
(clk,
clk_nobuf,
clkdiv_out,
sl_iport0,
sl_oport0,
trig_in,
trig_in_ack,
trig_out,
trig_out_ack,
probe0,
probe1,
probe2,
probe3,
probe4,
probe5,
probe6,
probe7,
probe8,
probe9,
probe10,
probe11,
probe12,
probe13,
probe14,
probe15,
probe16,
probe17,
probe18,
probe19,
probe20,
probe21,
probe22,
probe23,
probe24,
probe25,
probe26,
probe27,
probe28,
probe29,
probe30,
probe31,
probe32,
probe33,
probe34,
probe35,
probe36,
probe37,
probe38,
probe39,
probe40,
probe41,
probe42,
probe43,
probe44,
probe45,
probe46,
probe47,
probe48,
probe49,
probe50,
probe51,
probe52,
probe53,
probe54,
probe55,
probe56,
probe57,
probe58,
probe59,
probe60,
probe61,
probe62,
probe63,
probe64,
probe65,
probe66,
probe67,
probe68,
probe69,
probe70,
probe71,
probe72,
probe73,
probe74,
probe75,
probe76,
probe77,
probe78,
probe79,
probe80,
probe81,
probe82,
probe83,
probe84,
probe85,
probe86,
probe87,
probe88,
probe89,
probe90,
probe91,
probe92,
probe93,
probe94,
probe95,
probe96,
probe97,
probe98,
probe99,
probe100,
probe101,
probe102,
probe103,
probe104,
probe105,
probe106,
probe107,
probe108,
probe109,
probe110,
probe111,
probe112,
probe113,
probe114,
probe115,
probe116,
probe117,
probe118,
probe119,
probe120,
probe121,
probe122,
probe123,
probe124,
probe125,
probe126,
probe127,
probe128,
probe129,
probe130,
probe131,
probe132,
probe133,
probe134,
probe135,
probe136,
probe137,
probe138,
probe139,
probe140,
probe141,
probe142,
probe143,
probe144,
probe145,
probe146,
probe147,
probe148,
probe149,
probe150,
probe151,
probe152,
probe153,
probe154,
probe155,
probe156,
probe157,
probe158,
probe159,
probe160,
probe161,
probe162,
probe163,
probe164,
probe165,
probe166,
probe167,
probe168,
probe169,
probe170,
probe171,
probe172,
probe173,
probe174,
probe175,
probe176,
probe177,
probe178,
probe179,
probe180,
probe181,
probe182,
probe183,
probe184,
probe185,
probe186,
probe187,
probe188,
probe189,
probe190,
probe191,
probe192,
probe193,
probe194,
probe195,
probe196,
probe197,
probe198,
probe199,
probe200,
probe201,
probe202,
probe203,
probe204,
probe205,
probe206,
probe207,
probe208,
probe209,
probe210,
probe211,
probe212,
probe213,
probe214,
probe215,
probe216,
probe217,
probe218,
probe219,
probe220,
probe221,
probe222,
probe223,
probe224,
probe225,
probe226,
probe227,
probe228,
probe229,
probe230,
probe231,
probe232,
probe233,
probe234,
probe235,
probe236,
probe237,
probe238,
probe239,
probe240,
probe241,
probe242,
probe243,
probe244,
probe245,
probe246,
probe247,
probe248,
probe249,
probe250,
probe251,
probe252,
probe253,
probe254,
probe255,
probe256,
probe257,
probe258,
probe259,
probe260,
probe261,
probe262,
probe263,
probe264,
probe265,
probe266,
probe267,
probe268,
probe269,
probe270,
probe271,
probe272,
probe273,
probe274,
probe275,
probe276,
probe277,
probe278,
probe279,
probe280,
probe281,
probe282,
probe283,
probe284,
probe285,
probe286,
probe287,
probe288,
probe289,
probe290,
probe291,
probe292,
probe293,
probe294,
probe295,
probe296,
probe297,
probe298,
probe299,
probe300,
probe301,
probe302,
probe303,
probe304,
probe305,
probe306,
probe307,
probe308,
probe309,
probe310,
probe311,
probe312,
probe313,
probe314,
probe315,
probe316,
probe317,
probe318,
probe319,
probe320,
probe321,
probe322,
probe323,
probe324,
probe325,
probe326,
probe327,
probe328,
probe329,
probe330,
probe331,
probe332,
probe333,
probe334,
probe335,
probe336,
probe337,
probe338,
probe339,
probe340,
probe341,
probe342,
probe343,
probe344,
probe345,
probe346,
probe347,
probe348,
probe349,
probe350,
probe351,
probe352,
probe353,
probe354,
probe355,
probe356,
probe357,
probe358,
probe359,
probe360,
probe361,
probe362,
probe363,
probe364,
probe365,
probe366,
probe367,
probe368,
probe369,
probe370,
probe371,
probe372,
probe373,
probe374,
probe375,
probe376,
probe377,
probe378,
probe379,
probe380,
probe381,
probe382,
probe383,
probe384,
probe385,
probe386,
probe387,
probe388,
probe389,
probe390,
probe391,
probe392,
probe393,
probe394,
probe395,
probe396,
probe397,
probe398,
probe399,
probe400,
probe401,
probe402,
probe403,
probe404,
probe405,
probe406,
probe407,
probe408,
probe409,
probe410,
probe411,
probe412,
probe413,
probe414,
probe415,
probe416,
probe417,
probe418,
probe419,
probe420,
probe421,
probe422,
probe423,
probe424,
probe425,
probe426,
probe427,
probe428,
probe429,
probe430,
probe431,
probe432,
probe433,
probe434,
probe435,
probe436,
probe437,
probe438,
probe439,
probe440,
probe441,
probe442,
probe443,
probe444,
probe445,
probe446,
probe447,
probe448,
probe449,
probe450,
probe451,
probe452,
probe453,
probe454,
probe455,
probe456,
probe457,
probe458,
probe459,
probe460,
probe461,
probe462,
probe463,
probe464,
probe465,
probe466,
probe467,
probe468,
probe469,
probe470,
probe471,
probe472,
probe473,
probe474,
probe475,
probe476,
probe477,
probe478,
probe479,
probe480,
probe481,
probe482,
probe483,
probe484,
probe485,
probe486,
probe487,
probe488,
probe489,
probe490,
probe491,
probe492,
probe493,
probe494,
probe495,
probe496,
probe497,
probe498,
probe499,
probe500,
probe501,
probe502,
probe503,
probe504,
probe505,
probe506,
probe507,
probe508,
probe509,
probe510,
probe511,
probe512,
probe513,
probe514,
probe515,
probe516,
probe517,
probe518,
probe519,
probe520,
probe521,
probe522,
probe523,
probe524,
probe525,
probe526,
probe527,
probe528,
probe529,
probe530,
probe531,
probe532,
probe533,
probe534,
probe535,
probe536,
probe537,
probe538,
probe539,
probe540,
probe541,
probe542,
probe543,
probe544,
probe545,
probe546,
probe547,
probe548,
probe549,
probe550,
probe551,
probe552,
probe553,
probe554,
probe555,
probe556,
probe557,
probe558,
probe559,
probe560,
probe561,
probe562,
probe563,
probe564,
probe565,
probe566,
probe567,
probe568,
probe569,
probe570,
probe571,
probe572,
probe573,
probe574,
probe575,
probe576,
probe577,
probe578,
probe579,
probe580,
probe581,
probe582,
probe583,
probe584,
probe585,
probe586,
probe587,
probe588,
probe589,
probe590,
probe591,
probe592,
probe593,
probe594,
probe595,
probe596,
probe597,
probe598,
probe599,
probe600,
probe601,
probe602,
probe603,
probe604,
probe605,
probe606,
probe607,
probe608,
probe609,
probe610,
probe611,
probe612,
probe613,
probe614,
probe615,
probe616,
probe617,
probe618,
probe619,
probe620,
probe621,
probe622,
probe623,
probe624,
probe625,
probe626,
probe627,
probe628,
probe629,
probe630,
probe631,
probe632,
probe633,
probe634,
probe635,
probe636,
probe637,
probe638,
probe639,
probe640,
probe641,
probe642,
probe643,
probe644,
probe645,
probe646,
probe647,
probe648,
probe649,
probe650,
probe651,
probe652,
probe653,
probe654,
probe655,
probe656,
probe657,
probe658,
probe659,
probe660,
probe661,
probe662,
probe663,
probe664,
probe665,
probe666,
probe667,
probe668,
probe669,
probe670,
probe671,
probe672,
probe673,
probe674,
probe675,
probe676,
probe677,
probe678,
probe679,
probe680,
probe681,
probe682,
probe683,
probe684,
probe685,
probe686,
probe687,
probe688,
probe689,
probe690,
probe691,
probe692,
probe693,
probe694,
probe695,
probe696,
probe697,
probe698,
probe699,
probe700,
probe701,
probe702,
probe703,
probe704,
probe705,
probe706,
probe707,
probe708,
probe709,
probe710,
probe711,
probe712,
probe713,
probe714,
probe715,
probe716,
probe717,
probe718,
probe719,
probe720,
probe721,
probe722,
probe723,
probe724,
probe725,
probe726,
probe727,
probe728,
probe729,
probe730,
probe731,
probe732,
probe733,
probe734,
probe735,
probe736,
probe737,
probe738,
probe739,
probe740,
probe741,
probe742,
probe743,
probe744,
probe745,
probe746,
probe747,
probe748,
probe749,
probe750,
probe751,
probe752,
probe753,
probe754,
probe755,
probe756,
probe757,
probe758,
probe759,
probe760,
probe761,
probe762,
probe763,
probe764,
probe765,
probe766,
probe767,
probe768,
probe769,
probe770,
probe771,
probe772,
probe773,
probe774,
probe775,
probe776,
probe777,
probe778,
probe779,
probe780,
probe781,
probe782,
probe783,
probe784,
probe785,
probe786,
probe787,
probe788,
probe789,
probe790,
probe791,
probe792,
probe793,
probe794,
probe795,
probe796,
probe797,
probe798,
probe799,
probe800,
probe801,
probe802,
probe803,
probe804,
probe805,
probe806,
probe807,
probe808,
probe809,
probe810,
probe811,
probe812,
probe813,
probe814,
probe815,
probe816,
probe817,
probe818,
probe819,
probe820,
probe821,
probe822,
probe823,
probe824,
probe825,
probe826,
probe827,
probe828,
probe829,
probe830,
probe831,
probe832,
probe833,
probe834,
probe835,
probe836,
probe837,
probe838,
probe839,
probe840,
probe841,
probe842,
probe843,
probe844,
probe845,
probe846,
probe847,
probe848,
probe849,
probe850,
probe851,
probe852,
probe853,
probe854,
probe855,
probe856,
probe857,
probe858,
probe859,
probe860,
probe861,
probe862,
probe863,
probe864,
probe865,
probe866,
probe867,
probe868,
probe869,
probe870,
probe871,
probe872,
probe873,
probe874,
probe875,
probe876,
probe877,
probe878,
probe879,
probe880,
probe881,
probe882,
probe883,
probe884,
probe885,
probe886,
probe887,
probe888,
probe889,
probe890,
probe891,
probe892,
probe893,
probe894,
probe895,
probe896,
probe897,
probe898,
probe899,
probe900,
probe901,
probe902,
probe903,
probe904,
probe905,
probe906,
probe907,
probe908,
probe909,
probe910,
probe911,
probe912,
probe913,
probe914,
probe915,
probe916,
probe917,
probe918,
probe919,
probe920,
probe921,
probe922,
probe923,
probe924,
probe925,
probe926,
probe927,
probe928,
probe929,
probe930,
probe931,
probe932,
probe933,
probe934,
probe935,
probe936,
probe937,
probe938,
probe939,
probe940,
probe941,
probe942,
probe943,
probe944,
probe945,
probe946,
probe947,
probe948,
probe949,
probe950,
probe951,
probe952,
probe953,
probe954,
probe955,
probe956,
probe957,
probe958,
probe959,
probe960,
probe961,
probe962,
probe963,
probe964,
probe965,
probe966,
probe967,
probe968,
probe969,
probe970,
probe971,
probe972,
probe973,
probe974,
probe975,
probe976,
probe977,
probe978,
probe979,
probe980,
probe981,
probe982,
probe983,
probe984,
probe985,
probe986,
probe987,
probe988,
probe989,
probe990,
probe991,
probe992,
probe993,
probe994,
probe995,
probe996,
probe997,
probe998,
probe999,
probe1000,
probe1001,
probe1002,
probe1003,
probe1004,
probe1005,
probe1006,
probe1007,
probe1008,
probe1009,
probe1010,
probe1011,
probe1012,
probe1013,
probe1014,
probe1015,
probe1016,
probe1017,
probe1018,
probe1019,
probe1020,
probe1021,
probe1022,
probe1023);
input clk;
input clk_nobuf;
output clkdiv_out;
(* dont_touch = "true" *) input [36:0]sl_iport0;
(* dont_touch = "true" *) output [16:0]sl_oport0;
input trig_in;
output trig_in_ack;
output trig_out;
input trig_out_ack;
input [0:0]probe0;
input [0:0]probe1;
input [15:0]probe2;
input [15:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [12:0]probe6;
input [0:0]probe7;
input [1:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [0:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [0:0]probe19;
input [0:0]probe20;
input [0:0]probe21;
input [0:0]probe22;
input [0:0]probe23;
input [0:0]probe24;
input [0:0]probe25;
input [0:0]probe26;
input [0:0]probe27;
input [0:0]probe28;
input [0:0]probe29;
input [0:0]probe30;
input [0:0]probe31;
input [0:0]probe32;
input [0:0]probe33;
input [0:0]probe34;
input [0:0]probe35;
input [0:0]probe36;
input [0:0]probe37;
input [0:0]probe38;
input [0:0]probe39;
input [0:0]probe40;
input [0:0]probe41;
input [0:0]probe42;
input [0:0]probe43;
input [0:0]probe44;
input [0:0]probe45;
input [0:0]probe46;
input [0:0]probe47;
input [0:0]probe48;
input [0:0]probe49;
input [0:0]probe50;
input [0:0]probe51;
input [0:0]probe52;
input [0:0]probe53;
input [0:0]probe54;
input [0:0]probe55;
input [0:0]probe56;
input [0:0]probe57;
input [0:0]probe58;
input [0:0]probe59;
input [0:0]probe60;
input [0:0]probe61;
input [0:0]probe62;
input [0:0]probe63;
input [0:0]probe64;
input [0:0]probe65;
input [0:0]probe66;
input [0:0]probe67;
input [0:0]probe68;
input [0:0]probe69;
input [0:0]probe70;
input [0:0]probe71;
input [0:0]probe72;
input [0:0]probe73;
input [0:0]probe74;
input [0:0]probe75;
input [0:0]probe76;
input [0:0]probe77;
input [0:0]probe78;
input [0:0]probe79;
input [0:0]probe80;
input [0:0]probe81;
input [0:0]probe82;
input [0:0]probe83;
input [0:0]probe84;
input [0:0]probe85;
input [0:0]probe86;
input [0:0]probe87;
input [0:0]probe88;
input [0:0]probe89;
input [0:0]probe90;
input [0:0]probe91;
input [0:0]probe92;
input [0:0]probe93;
input [0:0]probe94;
input [0:0]probe95;
input [0:0]probe96;
input [0:0]probe97;
input [0:0]probe98;
input [0:0]probe99;
input [0:0]probe100;
input [0:0]probe101;
input [0:0]probe102;
input [0:0]probe103;
input [0:0]probe104;
input [0:0]probe105;
input [0:0]probe106;
input [0:0]probe107;
input [0:0]probe108;
input [0:0]probe109;
input [0:0]probe110;
input [0:0]probe111;
input [0:0]probe112;
input [0:0]probe113;
input [0:0]probe114;
input [0:0]probe115;
input [0:0]probe116;
input [0:0]probe117;
input [0:0]probe118;
input [0:0]probe119;
input [0:0]probe120;
input [0:0]probe121;
input [0:0]probe122;
input [0:0]probe123;
input [0:0]probe124;
input [0:0]probe125;
input [0:0]probe126;
input [0:0]probe127;
input [0:0]probe128;
input [0:0]probe129;
input [0:0]probe130;
input [0:0]probe131;
input [0:0]probe132;
input [0:0]probe133;
input [0:0]probe134;
input [0:0]probe135;
input [0:0]probe136;
input [0:0]probe137;
input [0:0]probe138;
input [0:0]probe139;
input [0:0]probe140;
input [0:0]probe141;
input [0:0]probe142;
input [0:0]probe143;
input [0:0]probe144;
input [0:0]probe145;
input [0:0]probe146;
input [0:0]probe147;
input [0:0]probe148;
input [0:0]probe149;
input [0:0]probe150;
input [0:0]probe151;
input [0:0]probe152;
input [0:0]probe153;
input [0:0]probe154;
input [0:0]probe155;
input [0:0]probe156;
input [0:0]probe157;
input [0:0]probe158;
input [0:0]probe159;
input [0:0]probe160;
input [0:0]probe161;
input [0:0]probe162;
input [0:0]probe163;
input [0:0]probe164;
input [0:0]probe165;
input [0:0]probe166;
input [0:0]probe167;
input [0:0]probe168;
input [0:0]probe169;
input [0:0]probe170;
input [0:0]probe171;
input [0:0]probe172;
input [0:0]probe173;
input [0:0]probe174;
input [0:0]probe175;
input [0:0]probe176;
input [0:0]probe177;
input [0:0]probe178;
input [0:0]probe179;
input [0:0]probe180;
input [0:0]probe181;
input [0:0]probe182;
input [0:0]probe183;
input [0:0]probe184;
input [0:0]probe185;
input [0:0]probe186;
input [0:0]probe187;
input [0:0]probe188;
input [0:0]probe189;
input [0:0]probe190;
input [0:0]probe191;
input [0:0]probe192;
input [0:0]probe193;
input [0:0]probe194;
input [0:0]probe195;
input [0:0]probe196;
input [0:0]probe197;
input [0:0]probe198;
input [0:0]probe199;
input [0:0]probe200;
input [0:0]probe201;
input [0:0]probe202;
input [0:0]probe203;
input [0:0]probe204;
input [0:0]probe205;
input [0:0]probe206;
input [0:0]probe207;
input [0:0]probe208;
input [0:0]probe209;
input [0:0]probe210;
input [0:0]probe211;
input [0:0]probe212;
input [0:0]probe213;
input [0:0]probe214;
input [0:0]probe215;
input [0:0]probe216;
input [0:0]probe217;
input [0:0]probe218;
input [0:0]probe219;
input [0:0]probe220;
input [0:0]probe221;
input [0:0]probe222;
input [0:0]probe223;
input [0:0]probe224;
input [0:0]probe225;
input [0:0]probe226;
input [0:0]probe227;
input [0:0]probe228;
input [0:0]probe229;
input [0:0]probe230;
input [0:0]probe231;
input [0:0]probe232;
input [0:0]probe233;
input [0:0]probe234;
input [0:0]probe235;
input [0:0]probe236;
input [0:0]probe237;
input [0:0]probe238;
input [0:0]probe239;
input [0:0]probe240;
input [0:0]probe241;
input [0:0]probe242;
input [0:0]probe243;
input [0:0]probe244;
input [0:0]probe245;
input [0:0]probe246;
input [0:0]probe247;
input [0:0]probe248;
input [0:0]probe249;
input [0:0]probe250;
input [0:0]probe251;
input [0:0]probe252;
input [0:0]probe253;
input [0:0]probe254;
input [0:0]probe255;
input [0:0]probe256;
input [0:0]probe257;
input [0:0]probe258;
input [0:0]probe259;
input [0:0]probe260;
input [0:0]probe261;
input [0:0]probe262;
input [0:0]probe263;
input [0:0]probe264;
input [0:0]probe265;
input [0:0]probe266;
input [0:0]probe267;
input [0:0]probe268;
input [0:0]probe269;
input [0:0]probe270;
input [0:0]probe271;
input [0:0]probe272;
input [0:0]probe273;
input [0:0]probe274;
input [0:0]probe275;
input [0:0]probe276;
input [0:0]probe277;
input [0:0]probe278;
input [0:0]probe279;
input [0:0]probe280;
input [0:0]probe281;
input [0:0]probe282;
input [0:0]probe283;
input [0:0]probe284;
input [0:0]probe285;
input [0:0]probe286;
input [0:0]probe287;
input [0:0]probe288;
input [0:0]probe289;
input [0:0]probe290;
input [0:0]probe291;
input [0:0]probe292;
input [0:0]probe293;
input [0:0]probe294;
input [0:0]probe295;
input [0:0]probe296;
input [0:0]probe297;
input [0:0]probe298;
input [0:0]probe299;
input [0:0]probe300;
input [0:0]probe301;
input [0:0]probe302;
input [0:0]probe303;
input [0:0]probe304;
input [0:0]probe305;
input [0:0]probe306;
input [0:0]probe307;
input [0:0]probe308;
input [0:0]probe309;
input [0:0]probe310;
input [0:0]probe311;
input [0:0]probe312;
input [0:0]probe313;
input [0:0]probe314;
input [0:0]probe315;
input [0:0]probe316;
input [0:0]probe317;
input [0:0]probe318;
input [0:0]probe319;
input [0:0]probe320;
input [0:0]probe321;
input [0:0]probe322;
input [0:0]probe323;
input [0:0]probe324;
input [0:0]probe325;
input [0:0]probe326;
input [0:0]probe327;
input [0:0]probe328;
input [0:0]probe329;
input [0:0]probe330;
input [0:0]probe331;
input [0:0]probe332;
input [0:0]probe333;
input [0:0]probe334;
input [0:0]probe335;
input [0:0]probe336;
input [0:0]probe337;
input [0:0]probe338;
input [0:0]probe339;
input [0:0]probe340;
input [0:0]probe341;
input [0:0]probe342;
input [0:0]probe343;
input [0:0]probe344;
input [0:0]probe345;
input [0:0]probe346;
input [0:0]probe347;
input [0:0]probe348;
input [0:0]probe349;
input [0:0]probe350;
input [0:0]probe351;
input [0:0]probe352;
input [0:0]probe353;
input [0:0]probe354;
input [0:0]probe355;
input [0:0]probe356;
input [0:0]probe357;
input [0:0]probe358;
input [0:0]probe359;
input [0:0]probe360;
input [0:0]probe361;
input [0:0]probe362;
input [0:0]probe363;
input [0:0]probe364;
input [0:0]probe365;
input [0:0]probe366;
input [0:0]probe367;
input [0:0]probe368;
input [0:0]probe369;
input [0:0]probe370;
input [0:0]probe371;
input [0:0]probe372;
input [0:0]probe373;
input [0:0]probe374;
input [0:0]probe375;
input [0:0]probe376;
input [0:0]probe377;
input [0:0]probe378;
input [0:0]probe379;
input [0:0]probe380;
input [0:0]probe381;
input [0:0]probe382;
input [0:0]probe383;
input [0:0]probe384;
input [0:0]probe385;
input [0:0]probe386;
input [0:0]probe387;
input [0:0]probe388;
input [0:0]probe389;
input [0:0]probe390;
input [0:0]probe391;
input [0:0]probe392;
input [0:0]probe393;
input [0:0]probe394;
input [0:0]probe395;
input [0:0]probe396;
input [0:0]probe397;
input [0:0]probe398;
input [0:0]probe399;
input [0:0]probe400;
input [0:0]probe401;
input [0:0]probe402;
input [0:0]probe403;
input [0:0]probe404;
input [0:0]probe405;
input [0:0]probe406;
input [0:0]probe407;
input [0:0]probe408;
input [0:0]probe409;
input [0:0]probe410;
input [0:0]probe411;
input [0:0]probe412;
input [0:0]probe413;
input [0:0]probe414;
input [0:0]probe415;
input [0:0]probe416;
input [0:0]probe417;
input [0:0]probe418;
input [0:0]probe419;
input [0:0]probe420;
input [0:0]probe421;
input [0:0]probe422;
input [0:0]probe423;
input [0:0]probe424;
input [0:0]probe425;
input [0:0]probe426;
input [0:0]probe427;
input [0:0]probe428;
input [0:0]probe429;
input [0:0]probe430;
input [0:0]probe431;
input [0:0]probe432;
input [0:0]probe433;
input [0:0]probe434;
input [0:0]probe435;
input [0:0]probe436;
input [0:0]probe437;
input [0:0]probe438;
input [0:0]probe439;
input [0:0]probe440;
input [0:0]probe441;
input [0:0]probe442;
input [0:0]probe443;
input [0:0]probe444;
input [0:0]probe445;
input [0:0]probe446;
input [0:0]probe447;
input [0:0]probe448;
input [0:0]probe449;
input [0:0]probe450;
input [0:0]probe451;
input [0:0]probe452;
input [0:0]probe453;
input [0:0]probe454;
input [0:0]probe455;
input [0:0]probe456;
input [0:0]probe457;
input [0:0]probe458;
input [0:0]probe459;
input [0:0]probe460;
input [0:0]probe461;
input [0:0]probe462;
input [0:0]probe463;
input [0:0]probe464;
input [0:0]probe465;
input [0:0]probe466;
input [0:0]probe467;
input [0:0]probe468;
input [0:0]probe469;
input [0:0]probe470;
input [0:0]probe471;
input [0:0]probe472;
input [0:0]probe473;
input [0:0]probe474;
input [0:0]probe475;
input [0:0]probe476;
input [0:0]probe477;
input [0:0]probe478;
input [0:0]probe479;
input [0:0]probe480;
input [0:0]probe481;
input [0:0]probe482;
input [0:0]probe483;
input [0:0]probe484;
input [0:0]probe485;
input [0:0]probe486;
input [0:0]probe487;
input [0:0]probe488;
input [0:0]probe489;
input [0:0]probe490;
input [0:0]probe491;
input [0:0]probe492;
input [0:0]probe493;
input [0:0]probe494;
input [0:0]probe495;
input [0:0]probe496;
input [0:0]probe497;
input [0:0]probe498;
input [0:0]probe499;
input [0:0]probe500;
input [0:0]probe501;
input [0:0]probe502;
input [0:0]probe503;
input [0:0]probe504;
input [0:0]probe505;
input [0:0]probe506;
input [0:0]probe507;
input [0:0]probe508;
input [0:0]probe509;
input [0:0]probe510;
input [0:0]probe511;
input [0:0]probe512;
input [0:0]probe513;
input [0:0]probe514;
input [0:0]probe515;
input [0:0]probe516;
input [0:0]probe517;
input [0:0]probe518;
input [0:0]probe519;
input [0:0]probe520;
input [0:0]probe521;
input [0:0]probe522;
input [0:0]probe523;
input [0:0]probe524;
input [0:0]probe525;
input [0:0]probe526;
input [0:0]probe527;
input [0:0]probe528;
input [0:0]probe529;
input [0:0]probe530;
input [0:0]probe531;
input [0:0]probe532;
input [0:0]probe533;
input [0:0]probe534;
input [0:0]probe535;
input [0:0]probe536;
input [0:0]probe537;
input [0:0]probe538;
input [0:0]probe539;
input [0:0]probe540;
input [0:0]probe541;
input [0:0]probe542;
input [0:0]probe543;
input [0:0]probe544;
input [0:0]probe545;
input [0:0]probe546;
input [0:0]probe547;
input [0:0]probe548;
input [0:0]probe549;
input [0:0]probe550;
input [0:0]probe551;
input [0:0]probe552;
input [0:0]probe553;
input [0:0]probe554;
input [0:0]probe555;
input [0:0]probe556;
input [0:0]probe557;
input [0:0]probe558;
input [0:0]probe559;
input [0:0]probe560;
input [0:0]probe561;
input [0:0]probe562;
input [0:0]probe563;
input [0:0]probe564;
input [0:0]probe565;
input [0:0]probe566;
input [0:0]probe567;
input [0:0]probe568;
input [0:0]probe569;
input [0:0]probe570;
input [0:0]probe571;
input [0:0]probe572;
input [0:0]probe573;
input [0:0]probe574;
input [0:0]probe575;
input [0:0]probe576;
input [0:0]probe577;
input [0:0]probe578;
input [0:0]probe579;
input [0:0]probe580;
input [0:0]probe581;
input [0:0]probe582;
input [0:0]probe583;
input [0:0]probe584;
input [0:0]probe585;
input [0:0]probe586;
input [0:0]probe587;
input [0:0]probe588;
input [0:0]probe589;
input [0:0]probe590;
input [0:0]probe591;
input [0:0]probe592;
input [0:0]probe593;
input [0:0]probe594;
input [0:0]probe595;
input [0:0]probe596;
input [0:0]probe597;
input [0:0]probe598;
input [0:0]probe599;
input [0:0]probe600;
input [0:0]probe601;
input [0:0]probe602;
input [0:0]probe603;
input [0:0]probe604;
input [0:0]probe605;
input [0:0]probe606;
input [0:0]probe607;
input [0:0]probe608;
input [0:0]probe609;
input [0:0]probe610;
input [0:0]probe611;
input [0:0]probe612;
input [0:0]probe613;
input [0:0]probe614;
input [0:0]probe615;
input [0:0]probe616;
input [0:0]probe617;
input [0:0]probe618;
input [0:0]probe619;
input [0:0]probe620;
input [0:0]probe621;
input [0:0]probe622;
input [0:0]probe623;
input [0:0]probe624;
input [0:0]probe625;
input [0:0]probe626;
input [0:0]probe627;
input [0:0]probe628;
input [0:0]probe629;
input [0:0]probe630;
input [0:0]probe631;
input [0:0]probe632;
input [0:0]probe633;
input [0:0]probe634;
input [0:0]probe635;
input [0:0]probe636;
input [0:0]probe637;
input [0:0]probe638;
input [0:0]probe639;
input [0:0]probe640;
input [0:0]probe641;
input [0:0]probe642;
input [0:0]probe643;
input [0:0]probe644;
input [0:0]probe645;
input [0:0]probe646;
input [0:0]probe647;
input [0:0]probe648;
input [0:0]probe649;
input [0:0]probe650;
input [0:0]probe651;
input [0:0]probe652;
input [0:0]probe653;
input [0:0]probe654;
input [0:0]probe655;
input [0:0]probe656;
input [0:0]probe657;
input [0:0]probe658;
input [0:0]probe659;
input [0:0]probe660;
input [0:0]probe661;
input [0:0]probe662;
input [0:0]probe663;
input [0:0]probe664;
input [0:0]probe665;
input [0:0]probe666;
input [0:0]probe667;
input [0:0]probe668;
input [0:0]probe669;
input [0:0]probe670;
input [0:0]probe671;
input [0:0]probe672;
input [0:0]probe673;
input [0:0]probe674;
input [0:0]probe675;
input [0:0]probe676;
input [0:0]probe677;
input [0:0]probe678;
input [0:0]probe679;
input [0:0]probe680;
input [0:0]probe681;
input [0:0]probe682;
input [0:0]probe683;
input [0:0]probe684;
input [0:0]probe685;
input [0:0]probe686;
input [0:0]probe687;
input [0:0]probe688;
input [0:0]probe689;
input [0:0]probe690;
input [0:0]probe691;
input [0:0]probe692;
input [0:0]probe693;
input [0:0]probe694;
input [0:0]probe695;
input [0:0]probe696;
input [0:0]probe697;
input [0:0]probe698;
input [0:0]probe699;
input [0:0]probe700;
input [0:0]probe701;
input [0:0]probe702;
input [0:0]probe703;
input [0:0]probe704;
input [0:0]probe705;
input [0:0]probe706;
input [0:0]probe707;
input [0:0]probe708;
input [0:0]probe709;
input [0:0]probe710;
input [0:0]probe711;
input [0:0]probe712;
input [0:0]probe713;
input [0:0]probe714;
input [0:0]probe715;
input [0:0]probe716;
input [0:0]probe717;
input [0:0]probe718;
input [0:0]probe719;
input [0:0]probe720;
input [0:0]probe721;
input [0:0]probe722;
input [0:0]probe723;
input [0:0]probe724;
input [0:0]probe725;
input [0:0]probe726;
input [0:0]probe727;
input [0:0]probe728;
input [0:0]probe729;
input [0:0]probe730;
input [0:0]probe731;
input [0:0]probe732;
input [0:0]probe733;
input [0:0]probe734;
input [0:0]probe735;
input [0:0]probe736;
input [0:0]probe737;
input [0:0]probe738;
input [0:0]probe739;
input [0:0]probe740;
input [0:0]probe741;
input [0:0]probe742;
input [0:0]probe743;
input [0:0]probe744;
input [0:0]probe745;
input [0:0]probe746;
input [0:0]probe747;
input [0:0]probe748;
input [0:0]probe749;
input [0:0]probe750;
input [0:0]probe751;
input [0:0]probe752;
input [0:0]probe753;
input [0:0]probe754;
input [0:0]probe755;
input [0:0]probe756;
input [0:0]probe757;
input [0:0]probe758;
input [0:0]probe759;
input [0:0]probe760;
input [0:0]probe761;
input [0:0]probe762;
input [0:0]probe763;
input [0:0]probe764;
input [0:0]probe765;
input [0:0]probe766;
input [0:0]probe767;
input [0:0]probe768;
input [0:0]probe769;
input [0:0]probe770;
input [0:0]probe771;
input [0:0]probe772;
input [0:0]probe773;
input [0:0]probe774;
input [0:0]probe775;
input [0:0]probe776;
input [0:0]probe777;
input [0:0]probe778;
input [0:0]probe779;
input [0:0]probe780;
input [0:0]probe781;
input [0:0]probe782;
input [0:0]probe783;
input [0:0]probe784;
input [0:0]probe785;
input [0:0]probe786;
input [0:0]probe787;
input [0:0]probe788;
input [0:0]probe789;
input [0:0]probe790;
input [0:0]probe791;
input [0:0]probe792;
input [0:0]probe793;
input [0:0]probe794;
input [0:0]probe795;
input [0:0]probe796;
input [0:0]probe797;
input [0:0]probe798;
input [0:0]probe799;
input [0:0]probe800;
input [0:0]probe801;
input [0:0]probe802;
input [0:0]probe803;
input [0:0]probe804;
input [0:0]probe805;
input [0:0]probe806;
input [0:0]probe807;
input [0:0]probe808;
input [0:0]probe809;
input [0:0]probe810;
input [0:0]probe811;
input [0:0]probe812;
input [0:0]probe813;
input [0:0]probe814;
input [0:0]probe815;
input [0:0]probe816;
input [0:0]probe817;
input [0:0]probe818;
input [0:0]probe819;
input [0:0]probe820;
input [0:0]probe821;
input [0:0]probe822;
input [0:0]probe823;
input [0:0]probe824;
input [0:0]probe825;
input [0:0]probe826;
input [0:0]probe827;
input [0:0]probe828;
input [0:0]probe829;
input [0:0]probe830;
input [0:0]probe831;
input [0:0]probe832;
input [0:0]probe833;
input [0:0]probe834;
input [0:0]probe835;
input [0:0]probe836;
input [0:0]probe837;
input [0:0]probe838;
input [0:0]probe839;
input [0:0]probe840;
input [0:0]probe841;
input [0:0]probe842;
input [0:0]probe843;
input [0:0]probe844;
input [0:0]probe845;
input [0:0]probe846;
input [0:0]probe847;
input [0:0]probe848;
input [0:0]probe849;
input [0:0]probe850;
input [0:0]probe851;
input [0:0]probe852;
input [0:0]probe853;
input [0:0]probe854;
input [0:0]probe855;
input [0:0]probe856;
input [0:0]probe857;
input [0:0]probe858;
input [0:0]probe859;
input [0:0]probe860;
input [0:0]probe861;
input [0:0]probe862;
input [0:0]probe863;
input [0:0]probe864;
input [0:0]probe865;
input [0:0]probe866;
input [0:0]probe867;
input [0:0]probe868;
input [0:0]probe869;
input [0:0]probe870;
input [0:0]probe871;
input [0:0]probe872;
input [0:0]probe873;
input [0:0]probe874;
input [0:0]probe875;
input [0:0]probe876;
input [0:0]probe877;
input [0:0]probe878;
input [0:0]probe879;
input [0:0]probe880;
input [0:0]probe881;
input [0:0]probe882;
input [0:0]probe883;
input [0:0]probe884;
input [0:0]probe885;
input [0:0]probe886;
input [0:0]probe887;
input [0:0]probe888;
input [0:0]probe889;
input [0:0]probe890;
input [0:0]probe891;
input [0:0]probe892;
input [0:0]probe893;
input [0:0]probe894;
input [0:0]probe895;
input [0:0]probe896;
input [0:0]probe897;
input [0:0]probe898;
input [0:0]probe899;
input [0:0]probe900;
input [0:0]probe901;
input [0:0]probe902;
input [0:0]probe903;
input [0:0]probe904;
input [0:0]probe905;
input [0:0]probe906;
input [0:0]probe907;
input [0:0]probe908;
input [0:0]probe909;
input [0:0]probe910;
input [0:0]probe911;
input [0:0]probe912;
input [0:0]probe913;
input [0:0]probe914;
input [0:0]probe915;
input [0:0]probe916;
input [0:0]probe917;
input [0:0]probe918;
input [0:0]probe919;
input [0:0]probe920;
input [0:0]probe921;
input [0:0]probe922;
input [0:0]probe923;
input [0:0]probe924;
input [0:0]probe925;
input [0:0]probe926;
input [0:0]probe927;
input [0:0]probe928;
input [0:0]probe929;
input [0:0]probe930;
input [0:0]probe931;
input [0:0]probe932;
input [0:0]probe933;
input [0:0]probe934;
input [0:0]probe935;
input [0:0]probe936;
input [0:0]probe937;
input [0:0]probe938;
input [0:0]probe939;
input [0:0]probe940;
input [0:0]probe941;
input [0:0]probe942;
input [0:0]probe943;
input [0:0]probe944;
input [0:0]probe945;
input [0:0]probe946;
input [0:0]probe947;
input [0:0]probe948;
input [0:0]probe949;
input [0:0]probe950;
input [0:0]probe951;
input [0:0]probe952;
input [0:0]probe953;
input [0:0]probe954;
input [0:0]probe955;
input [0:0]probe956;
input [0:0]probe957;
input [0:0]probe958;
input [0:0]probe959;
input [0:0]probe960;
input [0:0]probe961;
input [0:0]probe962;
input [0:0]probe963;
input [0:0]probe964;
input [0:0]probe965;
input [0:0]probe966;
input [0:0]probe967;
input [0:0]probe968;
input [0:0]probe969;
input [0:0]probe970;
input [0:0]probe971;
input [0:0]probe972;
input [0:0]probe973;
input [0:0]probe974;
input [0:0]probe975;
input [0:0]probe976;
input [0:0]probe977;
input [0:0]probe978;
input [0:0]probe979;
input [0:0]probe980;
input [0:0]probe981;
input [0:0]probe982;
input [0:0]probe983;
input [0:0]probe984;
input [0:0]probe985;
input [0:0]probe986;
input [0:0]probe987;
input [0:0]probe988;
input [0:0]probe989;
input [0:0]probe990;
input [0:0]probe991;
input [0:0]probe992;
input [0:0]probe993;
input [0:0]probe994;
input [0:0]probe995;
input [0:0]probe996;
input [0:0]probe997;
input [0:0]probe998;
input [0:0]probe999;
input [0:0]probe1000;
input [0:0]probe1001;
input [0:0]probe1002;
input [0:0]probe1003;
input [0:0]probe1004;
input [0:0]probe1005;
input [0:0]probe1006;
input [0:0]probe1007;
input [0:0]probe1008;
input [0:0]probe1009;
input [0:0]probe1010;
input [0:0]probe1011;
input [0:0]probe1012;
input [0:0]probe1013;
input [0:0]probe1014;
input [0:0]probe1015;
input [0:0]probe1016;
input [0:0]probe1017;
input [0:0]probe1018;
input [0:0]probe1019;
input [0:0]probe1020;
input [0:0]probe1021;
input [0:0]probe1022;
input [0:0]probe1023;
wire \<const0> ;
(* RTL_KEEP = "true" *) wire clk1x;
(* DONT_TOUCH *) wire dummy;
wire [0:0]probe0;
wire [0:0]probe1;
wire [15:0]probe2;
wire [15:0]probe3;
wire [0:0]probe4;
wire [0:0]probe5;
wire [12:0]probe6;
wire [0:0]probe7;
wire [1:0]probe8;
(* DONT_TOUCH *) wire [36:0]sl_iport0;
(* DONT_TOUCH *) wire [16:0]sl_oport0;
assign clk1x = clk;
assign clkdiv_out = \<const0> ;
assign trig_in_ack = \<const0> ;
assign trig_out = \<const0> ;
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(dummy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_core ila_core_inst
(.DUMMY_I(dummy),
.SL_IPORT_I(sl_iport0),
.SL_OPORT_O(sl_oport0),
.out(clk1x),
.probe0(probe0),
.probe1(probe1),
.probe2(probe2),
.probe3(probe3),
.probe4(probe4),
.probe5(probe5),
.probe6(probe6),
.probe7(probe7),
.probe8(probe8));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila
(clk,
clk_nobuf,
clkdiv_out,
sl_iport0,
sl_oport0,
trig_in,
trig_in_ack,
trig_out,
trig_out_ack,
probe0,
probe1,
probe2,
probe3,
probe4,
probe5,
probe6,
probe7,
probe8,
probe9,
probe10,
probe11,
probe12,
probe13,
probe14,
probe15,
probe16,
probe17,
probe18,
probe19,
probe20,
probe21,
probe22,
probe23,
probe24,
probe25,
probe26,
probe27,
probe28,
probe29,
probe30,
probe31,
probe32,
probe33,
probe34,
probe35,
probe36,
probe37,
probe38,
probe39,
probe40,
probe41,
probe42,
probe43,
probe44,
probe45,
probe46,
probe47,
probe48,
probe49,
probe50,
probe51,
probe52,
probe53,
probe54,
probe55,
probe56,
probe57,
probe58,
probe59,
probe60,
probe61,
probe62,
probe63,
probe64,
probe65,
probe66,
probe67,
probe68,
probe69,
probe70,
probe71,
probe72,
probe73,
probe74,
probe75,
probe76,
probe77,
probe78,
probe79,
probe80,
probe81,
probe82,
probe83,
probe84,
probe85,
probe86,
probe87,
probe88,
probe89,
probe90,
probe91,
probe92,
probe93,
probe94,
probe95,
probe96,
probe97,
probe98,
probe99,
probe100,
probe101,
probe102,
probe103,
probe104,
probe105,
probe106,
probe107,
probe108,
probe109,
probe110,
probe111,
probe112,
probe113,
probe114,
probe115,
probe116,
probe117,
probe118,
probe119,
probe120,
probe121,
probe122,
probe123,
probe124,
probe125,
probe126,
probe127,
probe128,
probe129,
probe130,
probe131,
probe132,
probe133,
probe134,
probe135,
probe136,
probe137,
probe138,
probe139,
probe140,
probe141,
probe142,
probe143,
probe144,
probe145,
probe146,
probe147,
probe148,
probe149,
probe150,
probe151,
probe152,
probe153,
probe154,
probe155,
probe156,
probe157,
probe158,
probe159,
probe160,
probe161,
probe162,
probe163,
probe164,
probe165,
probe166,
probe167,
probe168,
probe169,
probe170,
probe171,
probe172,
probe173,
probe174,
probe175,
probe176,
probe177,
probe178,
probe179,
probe180,
probe181,
probe182,
probe183,
probe184,
probe185,
probe186,
probe187,
probe188,
probe189,
probe190,
probe191,
probe192,
probe193,
probe194,
probe195,
probe196,
probe197,
probe198,
probe199,
probe200,
probe201,
probe202,
probe203,
probe204,
probe205,
probe206,
probe207,
probe208,
probe209,
probe210,
probe211,
probe212,
probe213,
probe214,
probe215,
probe216,
probe217,
probe218,
probe219,
probe220,
probe221,
probe222,
probe223,
probe224,
probe225,
probe226,
probe227,
probe228,
probe229,
probe230,
probe231,
probe232,
probe233,
probe234,
probe235,
probe236,
probe237,
probe238,
probe239,
probe240,
probe241,
probe242,
probe243,
probe244,
probe245,
probe246,
probe247,
probe248,
probe249,
probe250,
probe251,
probe252,
probe253,
probe254,
probe255,
probe256,
probe257,
probe258,
probe259,
probe260,
probe261,
probe262,
probe263,
probe264,
probe265,
probe266,
probe267,
probe268,
probe269,
probe270,
probe271,
probe272,
probe273,
probe274,
probe275,
probe276,
probe277,
probe278,
probe279,
probe280,
probe281,
probe282,
probe283,
probe284,
probe285,
probe286,
probe287,
probe288,
probe289,
probe290,
probe291,
probe292,
probe293,
probe294,
probe295,
probe296,
probe297,
probe298,
probe299,
probe300,
probe301,
probe302,
probe303,
probe304,
probe305,
probe306,
probe307,
probe308,
probe309,
probe310,
probe311,
probe312,
probe313,
probe314,
probe315,
probe316,
probe317,
probe318,
probe319,
probe320,
probe321,
probe322,
probe323,
probe324,
probe325,
probe326,
probe327,
probe328,
probe329,
probe330,
probe331,
probe332,
probe333,
probe334,
probe335,
probe336,
probe337,
probe338,
probe339,
probe340,
probe341,
probe342,
probe343,
probe344,
probe345,
probe346,
probe347,
probe348,
probe349,
probe350,
probe351,
probe352,
probe353,
probe354,
probe355,
probe356,
probe357,
probe358,
probe359,
probe360,
probe361,
probe362,
probe363,
probe364,
probe365,
probe366,
probe367,
probe368,
probe369,
probe370,
probe371,
probe372,
probe373,
probe374,
probe375,
probe376,
probe377,
probe378,
probe379,
probe380,
probe381,
probe382,
probe383,
probe384,
probe385,
probe386,
probe387,
probe388,
probe389,
probe390,
probe391,
probe392,
probe393,
probe394,
probe395,
probe396,
probe397,
probe398,
probe399,
probe400,
probe401,
probe402,
probe403,
probe404,
probe405,
probe406,
probe407,
probe408,
probe409,
probe410,
probe411,
probe412,
probe413,
probe414,
probe415,
probe416,
probe417,
probe418,
probe419,
probe420,
probe421,
probe422,
probe423,
probe424,
probe425,
probe426,
probe427,
probe428,
probe429,
probe430,
probe431,
probe432,
probe433,
probe434,
probe435,
probe436,
probe437,
probe438,
probe439,
probe440,
probe441,
probe442,
probe443,
probe444,
probe445,
probe446,
probe447,
probe448,
probe449,
probe450,
probe451,
probe452,
probe453,
probe454,
probe455,
probe456,
probe457,
probe458,
probe459,
probe460,
probe461,
probe462,
probe463,
probe464,
probe465,
probe466,
probe467,
probe468,
probe469,
probe470,
probe471,
probe472,
probe473,
probe474,
probe475,
probe476,
probe477,
probe478,
probe479,
probe480,
probe481,
probe482,
probe483,
probe484,
probe485,
probe486,
probe487,
probe488,
probe489,
probe490,
probe491,
probe492,
probe493,
probe494,
probe495,
probe496,
probe497,
probe498,
probe499,
probe500,
probe501,
probe502,
probe503,
probe504,
probe505,
probe506,
probe507,
probe508,
probe509,
probe510,
probe511,
probe512,
probe513,
probe514,
probe515,
probe516,
probe517,
probe518,
probe519,
probe520,
probe521,
probe522,
probe523,
probe524,
probe525,
probe526,
probe527,
probe528,
probe529,
probe530,
probe531,
probe532,
probe533,
probe534,
probe535,
probe536,
probe537,
probe538,
probe539,
probe540,
probe541,
probe542,
probe543,
probe544,
probe545,
probe546,
probe547,
probe548,
probe549,
probe550,
probe551,
probe552,
probe553,
probe554,
probe555,
probe556,
probe557,
probe558,
probe559,
probe560,
probe561,
probe562,
probe563,
probe564,
probe565,
probe566,
probe567,
probe568,
probe569,
probe570,
probe571,
probe572,
probe573,
probe574,
probe575,
probe576,
probe577,
probe578,
probe579,
probe580,
probe581,
probe582,
probe583,
probe584,
probe585,
probe586,
probe587,
probe588,
probe589,
probe590,
probe591,
probe592,
probe593,
probe594,
probe595,
probe596,
probe597,
probe598,
probe599,
probe600,
probe601,
probe602,
probe603,
probe604,
probe605,
probe606,
probe607,
probe608,
probe609,
probe610,
probe611,
probe612,
probe613,
probe614,
probe615,
probe616,
probe617,
probe618,
probe619,
probe620,
probe621,
probe622,
probe623,
probe624,
probe625,
probe626,
probe627,
probe628,
probe629,
probe630,
probe631,
probe632,
probe633,
probe634,
probe635,
probe636,
probe637,
probe638,
probe639,
probe640,
probe641,
probe642,
probe643,
probe644,
probe645,
probe646,
probe647,
probe648,
probe649,
probe650,
probe651,
probe652,
probe653,
probe654,
probe655,
probe656,
probe657,
probe658,
probe659,
probe660,
probe661,
probe662,
probe663,
probe664,
probe665,
probe666,
probe667,
probe668,
probe669,
probe670,
probe671,
probe672,
probe673,
probe674,
probe675,
probe676,
probe677,
probe678,
probe679,
probe680,
probe681,
probe682,
probe683,
probe684,
probe685,
probe686,
probe687,
probe688,
probe689,
probe690,
probe691,
probe692,
probe693,
probe694,
probe695,
probe696,
probe697,
probe698,
probe699,
probe700,
probe701,
probe702,
probe703,
probe704,
probe705,
probe706,
probe707,
probe708,
probe709,
probe710,
probe711,
probe712,
probe713,
probe714,
probe715,
probe716,
probe717,
probe718,
probe719,
probe720,
probe721,
probe722,
probe723,
probe724,
probe725,
probe726,
probe727,
probe728,
probe729,
probe730,
probe731,
probe732,
probe733,
probe734,
probe735,
probe736,
probe737,
probe738,
probe739,
probe740,
probe741,
probe742,
probe743,
probe744,
probe745,
probe746,
probe747,
probe748,
probe749,
probe750,
probe751,
probe752,
probe753,
probe754,
probe755,
probe756,
probe757,
probe758,
probe759,
probe760,
probe761,
probe762,
probe763,
probe764,
probe765,
probe766,
probe767,
probe768,
probe769,
probe770,
probe771,
probe772,
probe773,
probe774,
probe775,
probe776,
probe777,
probe778,
probe779,
probe780,
probe781,
probe782,
probe783,
probe784,
probe785,
probe786,
probe787,
probe788,
probe789,
probe790,
probe791,
probe792,
probe793,
probe794,
probe795,
probe796,
probe797,
probe798,
probe799,
probe800,
probe801,
probe802,
probe803,
probe804,
probe805,
probe806,
probe807,
probe808,
probe809,
probe810,
probe811,
probe812,
probe813,
probe814,
probe815,
probe816,
probe817,
probe818,
probe819,
probe820,
probe821,
probe822,
probe823,
probe824,
probe825,
probe826,
probe827,
probe828,
probe829,
probe830,
probe831,
probe832,
probe833,
probe834,
probe835,
probe836,
probe837,
probe838,
probe839,
probe840,
probe841,
probe842,
probe843,
probe844,
probe845,
probe846,
probe847,
probe848,
probe849,
probe850,
probe851,
probe852,
probe853,
probe854,
probe855,
probe856,
probe857,
probe858,
probe859,
probe860,
probe861,
probe862,
probe863,
probe864,
probe865,
probe866,
probe867,
probe868,
probe869,
probe870,
probe871,
probe872,
probe873,
probe874,
probe875,
probe876,
probe877,
probe878,
probe879,
probe880,
probe881,
probe882,
probe883,
probe884,
probe885,
probe886,
probe887,
probe888,
probe889,
probe890,
probe891,
probe892,
probe893,
probe894,
probe895,
probe896,
probe897,
probe898,
probe899,
probe900,
probe901,
probe902,
probe903,
probe904,
probe905,
probe906,
probe907,
probe908,
probe909,
probe910,
probe911,
probe912,
probe913,
probe914,
probe915,
probe916,
probe917,
probe918,
probe919,
probe920,
probe921,
probe922,
probe923,
probe924,
probe925,
probe926,
probe927,
probe928,
probe929,
probe930,
probe931,
probe932,
probe933,
probe934,
probe935,
probe936,
probe937,
probe938,
probe939,
probe940,
probe941,
probe942,
probe943,
probe944,
probe945,
probe946,
probe947,
probe948,
probe949,
probe950,
probe951,
probe952,
probe953,
probe954,
probe955,
probe956,
probe957,
probe958,
probe959,
probe960,
probe961,
probe962,
probe963,
probe964,
probe965,
probe966,
probe967,
probe968,
probe969,
probe970,
probe971,
probe972,
probe973,
probe974,
probe975,
probe976,
probe977,
probe978,
probe979,
probe980,
probe981,
probe982,
probe983,
probe984,
probe985,
probe986,
probe987,
probe988,
probe989,
probe990,
probe991,
probe992,
probe993,
probe994,
probe995,
probe996,
probe997,
probe998,
probe999,
probe1000,
probe1001,
probe1002,
probe1003,
probe1004,
probe1005,
probe1006,
probe1007,
probe1008,
probe1009,
probe1010,
probe1011,
probe1012,
probe1013,
probe1014,
probe1015,
probe1016,
probe1017,
probe1018,
probe1019,
probe1020,
probe1021,
probe1022,
probe1023); |
input clk;
input clk_nobuf;
output clkdiv_out;
(* dont_touch = "true" *) input [36:0]sl_iport0;
(* dont_touch = "true" *) output [16:0]sl_oport0;
input trig_in;
output trig_in_ack;
output trig_out;
input trig_out_ack;
input [0:0]probe0;
input [0:0]probe1;
input [15:0]probe2;
input [15:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [12:0]probe6;
input [0:0]probe7;
input [1:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [0:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [0:0]probe19;
input [0:0]probe20;
input [0:0]probe21;
input [0:0]probe22;
input [0:0]probe23;
input [0:0]probe24;
input [0:0]probe25;
input [0:0]probe26;
input [0:0]probe27;
input [0:0]probe28;
input [0:0]probe29;
input [0:0]probe30;
input [0:0]probe31;
input [0:0]probe32;
input [0:0]probe33;
input [0:0]probe34;
input [0:0]probe35;
input [0:0]probe36;
input [0:0]probe37;
input [0:0]probe38;
input [0:0]probe39;
input [0:0]probe40;
input [0:0]probe41;
input [0:0]probe42;
input [0:0]probe43;
input [0:0]probe44;
input [0:0]probe45;
input [0:0]probe46;
input [0:0]probe47;
input [0:0]probe48;
input [0:0]probe49;
input [0:0]probe50;
input [0:0]probe51;
input [0:0]probe52;
input [0:0]probe53;
input [0:0]probe54;
input [0:0]probe55;
input [0:0]probe56;
input [0:0]probe57;
input [0:0]probe58;
input [0:0]probe59;
input [0:0]probe60;
input [0:0]probe61;
input [0:0]probe62;
input [0:0]probe63;
input [0:0]probe64;
input [0:0]probe65;
input [0:0]probe66;
input [0:0]probe67;
input [0:0]probe68;
input [0:0]probe69;
input [0:0]probe70;
input [0:0]probe71;
input [0:0]probe72;
input [0:0]probe73;
input [0:0]probe74;
input [0:0]probe75;
input [0:0]probe76;
input [0:0]probe77;
input [0:0]probe78;
input [0:0]probe79;
input [0:0]probe80;
input [0:0]probe81;
input [0:0]probe82;
input [0:0]probe83;
input [0:0]probe84;
input [0:0]probe85;
input [0:0]probe86;
input [0:0]probe87;
input [0:0]probe88;
input [0:0]probe89;
input [0:0]probe90;
input [0:0]probe91;
input [0:0]probe92;
input [0:0]probe93;
input [0:0]probe94;
input [0:0]probe95;
input [0:0]probe96;
input [0:0]probe97;
input [0:0]probe98;
input [0:0]probe99;
input [0:0]probe100;
input [0:0]probe101;
input [0:0]probe102;
input [0:0]probe103;
input [0:0]probe104;
input [0:0]probe105;
input [0:0]probe106;
input [0:0]probe107;
input [0:0]probe108;
input [0:0]probe109;
input [0:0]probe110;
input [0:0]probe111;
input [0:0]probe112;
input [0:0]probe113;
input [0:0]probe114;
input [0:0]probe115;
input [0:0]probe116;
input [0:0]probe117;
input [0:0]probe118;
input [0:0]probe119;
input [0:0]probe120;
input [0:0]probe121;
input [0:0]probe122;
input [0:0]probe123;
input [0:0]probe124;
input [0:0]probe125;
input [0:0]probe126;
input [0:0]probe127;
input [0:0]probe128;
input [0:0]probe129;
input [0:0]probe130;
input [0:0]probe131;
input [0:0]probe132;
input [0:0]probe133;
input [0:0]probe134;
input [0:0]probe135;
input [0:0]probe136;
input [0:0]probe137;
input [0:0]probe138;
input [0:0]probe139;
input [0:0]probe140;
input [0:0]probe141;
input [0:0]probe142;
input [0:0]probe143;
input [0:0]probe144;
input [0:0]probe145;
input [0:0]probe146;
input [0:0]probe147;
input [0:0]probe148;
input [0:0]probe149;
input [0:0]probe150;
input [0:0]probe151;
input [0:0]probe152;
input [0:0]probe153;
input [0:0]probe154;
input [0:0]probe155;
input [0:0]probe156;
input [0:0]probe157;
input [0:0]probe158;
input [0:0]probe159;
input [0:0]probe160;
input [0:0]probe161;
input [0:0]probe162;
input [0:0]probe163;
input [0:0]probe164;
input [0:0]probe165;
input [0:0]probe166;
input [0:0]probe167;
input [0:0]probe168;
input [0:0]probe169;
input [0:0]probe170;
input [0:0]probe171;
input [0:0]probe172;
input [0:0]probe173;
input [0:0]probe174;
input [0:0]probe175;
input [0:0]probe176;
input [0:0]probe177;
input [0:0]probe178;
input [0:0]probe179;
input [0:0]probe180;
input [0:0]probe181;
input [0:0]probe182;
input [0:0]probe183;
input [0:0]probe184;
input [0:0]probe185;
input [0:0]probe186;
input [0:0]probe187;
input [0:0]probe188;
input [0:0]probe189;
input [0:0]probe190;
input [0:0]probe191;
input [0:0]probe192;
input [0:0]probe193;
input [0:0]probe194;
input [0:0]probe195;
input [0:0]probe196;
input [0:0]probe197;
input [0:0]probe198;
input [0:0]probe199;
input [0:0]probe200;
input [0:0]probe201;
input [0:0]probe202;
input [0:0]probe203;
input [0:0]probe204;
input [0:0]probe205;
input [0:0]probe206;
input [0:0]probe207;
input [0:0]probe208;
input [0:0]probe209;
input [0:0]probe210;
input [0:0]probe211;
input [0:0]probe212;
input [0:0]probe213;
input [0:0]probe214;
input [0:0]probe215;
input [0:0]probe216;
input [0:0]probe217;
input [0:0]probe218;
input [0:0]probe219;
input [0:0]probe220;
input [0:0]probe221;
input [0:0]probe222;
input [0:0]probe223;
input [0:0]probe224;
input [0:0]probe225;
input [0:0]probe226;
input [0:0]probe227;
input [0:0]probe228;
input [0:0]probe229;
input [0:0]probe230;
input [0:0]probe231;
input [0:0]probe232;
input [0:0]probe233;
input [0:0]probe234;
input [0:0]probe235;
input [0:0]probe236;
input [0:0]probe237;
input [0:0]probe238;
input [0:0]probe239;
input [0:0]probe240;
input [0:0]probe241;
input [0:0]probe242;
input [0:0]probe243;
input [0:0]probe244;
input [0:0]probe245;
input [0:0]probe246;
input [0:0]probe247;
input [0:0]probe248;
input [0:0]probe249;
input [0:0]probe250;
input [0:0]probe251;
input [0:0]probe252;
input [0:0]probe253;
input [0:0]probe254;
input [0:0]probe255;
input [0:0]probe256;
input [0:0]probe257;
input [0:0]probe258;
input [0:0]probe259;
input [0:0]probe260;
input [0:0]probe261;
input [0:0]probe262;
input [0:0]probe263;
input [0:0]probe264;
input [0:0]probe265;
input [0:0]probe266;
input [0:0]probe267;
input [0:0]probe268;
input [0:0]probe269;
input [0:0]probe270;
input [0:0]probe271;
input [0:0]probe272;
input [0:0]probe273;
input [0:0]probe274;
input [0:0]probe275;
input [0:0]probe276;
input [0:0]probe277;
input [0:0]probe278;
input [0:0]probe279;
input [0:0]probe280;
input [0:0]probe281;
input [0:0]probe282;
input [0:0]probe283;
input [0:0]probe284;
input [0:0]probe285;
input [0:0]probe286;
input [0:0]probe287;
input [0:0]probe288;
input [0:0]probe289;
input [0:0]probe290;
input [0:0]probe291;
input [0:0]probe292;
input [0:0]probe293;
input [0:0]probe294;
input [0:0]probe295;
input [0:0]probe296;
input [0:0]probe297;
input [0:0]probe298;
input [0:0]probe299;
input [0:0]probe300;
input [0:0]probe301;
input [0:0]probe302;
input [0:0]probe303;
input [0:0]probe304;
input [0:0]probe305;
input [0:0]probe306;
input [0:0]probe307;
input [0:0]probe308;
input [0:0]probe309;
input [0:0]probe310;
input [0:0]probe311;
input [0:0]probe312;
input [0:0]probe313;
input [0:0]probe314;
input [0:0]probe315;
input [0:0]probe316;
input [0:0]probe317;
input [0:0]probe318;
input [0:0]probe319;
input [0:0]probe320;
input [0:0]probe321;
input [0:0]probe322;
input [0:0]probe323;
input [0:0]probe324;
input [0:0]probe325;
input [0:0]probe326;
input [0:0]probe327;
input [0:0]probe328;
input [0:0]probe329;
input [0:0]probe330;
input [0:0]probe331;
input [0:0]probe332;
input [0:0]probe333;
input [0:0]probe334;
input [0:0]probe335;
input [0:0]probe336;
input [0:0]probe337;
input [0:0]probe338;
input [0:0]probe339;
input [0:0]probe340;
input [0:0]probe341;
input [0:0]probe342;
input [0:0]probe343;
input [0:0]probe344;
input [0:0]probe345;
input [0:0]probe346;
input [0:0]probe347;
input [0:0]probe348;
input [0:0]probe349;
input [0:0]probe350;
input [0:0]probe351;
input [0:0]probe352;
input [0:0]probe353;
input [0:0]probe354;
input [0:0]probe355;
input [0:0]probe356;
input [0:0]probe357;
input [0:0]probe358;
input [0:0]probe359;
input [0:0]probe360;
input [0:0]probe361;
input [0:0]probe362;
input [0:0]probe363;
input [0:0]probe364;
input [0:0]probe365;
input [0:0]probe366;
input [0:0]probe367;
input [0:0]probe368;
input [0:0]probe369;
input [0:0]probe370;
input [0:0]probe371;
input [0:0]probe372;
input [0:0]probe373;
input [0:0]probe374;
input [0:0]probe375;
input [0:0]probe376;
input [0:0]probe377;
input [0:0]probe378;
input [0:0]probe379;
input [0:0]probe380;
input [0:0]probe381;
input [0:0]probe382;
input [0:0]probe383;
input [0:0]probe384;
input [0:0]probe385;
input [0:0]probe386;
input [0:0]probe387;
input [0:0]probe388;
input [0:0]probe389;
input [0:0]probe390;
input [0:0]probe391;
input [0:0]probe392;
input [0:0]probe393;
input [0:0]probe394;
input [0:0]probe395;
input [0:0]probe396;
input [0:0]probe397;
input [0:0]probe398;
input [0:0]probe399;
input [0:0]probe400;
input [0:0]probe401;
input [0:0]probe402;
input [0:0]probe403;
input [0:0]probe404;
input [0:0]probe405;
input [0:0]probe406;
input [0:0]probe407;
input [0:0]probe408;
input [0:0]probe409;
input [0:0]probe410;
input [0:0]probe411;
input [0:0]probe412;
input [0:0]probe413;
input [0:0]probe414;
input [0:0]probe415;
input [0:0]probe416;
input [0:0]probe417;
input [0:0]probe418;
input [0:0]probe419;
input [0:0]probe420;
input [0:0]probe421;
input [0:0]probe422;
input [0:0]probe423;
input [0:0]probe424;
input [0:0]probe425;
input [0:0]probe426;
input [0:0]probe427;
input [0:0]probe428;
input [0:0]probe429;
input [0:0]probe430;
input [0:0]probe431;
input [0:0]probe432;
input [0:0]probe433;
input [0:0]probe434;
input [0:0]probe435;
input [0:0]probe436;
input [0:0]probe437;
input [0:0]probe438;
input [0:0]probe439;
input [0:0]probe440;
input [0:0]probe441;
input [0:0]probe442;
input [0:0]probe443;
input [0:0]probe444;
input [0:0]probe445;
input [0:0]probe446;
input [0:0]probe447;
input [0:0]probe448;
input [0:0]probe449;
input [0:0]probe450;
input [0:0]probe451;
input [0:0]probe452;
input [0:0]probe453;
input [0:0]probe454;
input [0:0]probe455;
input [0:0]probe456;
input [0:0]probe457;
input [0:0]probe458;
input [0:0]probe459;
input [0:0]probe460;
input [0:0]probe461;
input [0:0]probe462;
input [0:0]probe463;
input [0:0]probe464;
input [0:0]probe465;
input [0:0]probe466;
input [0:0]probe467;
input [0:0]probe468;
input [0:0]probe469;
input [0:0]probe470;
input [0:0]probe471;
input [0:0]probe472;
input [0:0]probe473;
input [0:0]probe474;
input [0:0]probe475;
input [0:0]probe476;
input [0:0]probe477;
input [0:0]probe478;
input [0:0]probe479;
input [0:0]probe480;
input [0:0]probe481;
input [0:0]probe482;
input [0:0]probe483;
input [0:0]probe484;
input [0:0]probe485;
input [0:0]probe486;
input [0:0]probe487;
input [0:0]probe488;
input [0:0]probe489;
input [0:0]probe490;
input [0:0]probe491;
input [0:0]probe492;
input [0:0]probe493;
input [0:0]probe494;
input [0:0]probe495;
input [0:0]probe496;
input [0:0]probe497;
input [0:0]probe498;
input [0:0]probe499;
input [0:0]probe500;
input [0:0]probe501;
input [0:0]probe502;
input [0:0]probe503;
input [0:0]probe504;
input [0:0]probe505;
input [0:0]probe506;
input [0:0]probe507;
input [0:0]probe508;
input [0:0]probe509;
input [0:0]probe510;
input [0:0]probe511;
input [0:0]probe512;
input [0:0]probe513;
input [0:0]probe514;
input [0:0]probe515;
input [0:0]probe516;
input [0:0]probe517;
input [0:0]probe518;
input [0:0]probe519;
input [0:0]probe520;
input [0:0]probe521;
input [0:0]probe522;
input [0:0]probe523;
input [0:0]probe524;
input [0:0]probe525;
input [0:0]probe526;
input [0:0]probe527;
input [0:0]probe528;
input [0:0]probe529;
input [0:0]probe530;
input [0:0]probe531;
input [0:0]probe532;
input [0:0]probe533;
input [0:0]probe534;
input [0:0]probe535;
input [0:0]probe536;
input [0:0]probe537;
input [0:0]probe538;
input [0:0]probe539;
input [0:0]probe540;
input [0:0]probe541;
input [0:0]probe542;
input [0:0]probe543;
input [0:0]probe544;
input [0:0]probe545;
input [0:0]probe546;
input [0:0]probe547;
input [0:0]probe548;
input [0:0]probe549;
input [0:0]probe550;
input [0:0]probe551;
input [0:0]probe552;
input [0:0]probe553;
input [0:0]probe554;
input [0:0]probe555;
input [0:0]probe556;
input [0:0]probe557;
input [0:0]probe558;
input [0:0]probe559;
input [0:0]probe560;
input [0:0]probe561;
input [0:0]probe562;
input [0:0]probe563;
input [0:0]probe564;
input [0:0]probe565;
input [0:0]probe566;
input [0:0]probe567;
input [0:0]probe568;
input [0:0]probe569;
input [0:0]probe570;
input [0:0]probe571;
input [0:0]probe572;
input [0:0]probe573;
input [0:0]probe574;
input [0:0]probe575;
input [0:0]probe576;
input [0:0]probe577;
input [0:0]probe578;
input [0:0]probe579;
input [0:0]probe580;
input [0:0]probe581;
input [0:0]probe582;
input [0:0]probe583;
input [0:0]probe584;
input [0:0]probe585;
input [0:0]probe586;
input [0:0]probe587;
input [0:0]probe588;
input [0:0]probe589;
input [0:0]probe590;
input [0:0]probe591;
input [0:0]probe592;
input [0:0]probe593;
input [0:0]probe594;
input [0:0]probe595;
input [0:0]probe596;
input [0:0]probe597;
input [0:0]probe598;
input [0:0]probe599;
input [0:0]probe600;
input [0:0]probe601;
input [0:0]probe602;
input [0:0]probe603;
input [0:0]probe604;
input [0:0]probe605;
input [0:0]probe606;
input [0:0]probe607;
input [0:0]probe608;
input [0:0]probe609;
input [0:0]probe610;
input [0:0]probe611;
input [0:0]probe612;
input [0:0]probe613;
input [0:0]probe614;
input [0:0]probe615;
input [0:0]probe616;
input [0:0]probe617;
input [0:0]probe618;
input [0:0]probe619;
input [0:0]probe620;
input [0:0]probe621;
input [0:0]probe622;
input [0:0]probe623;
input [0:0]probe624;
input [0:0]probe625;
input [0:0]probe626;
input [0:0]probe627;
input [0:0]probe628;
input [0:0]probe629;
input [0:0]probe630;
input [0:0]probe631;
input [0:0]probe632;
input [0:0]probe633;
input [0:0]probe634;
input [0:0]probe635;
input [0:0]probe636;
input [0:0]probe637;
input [0:0]probe638;
input [0:0]probe639;
input [0:0]probe640;
input [0:0]probe641;
input [0:0]probe642;
input [0:0]probe643;
input [0:0]probe644;
input [0:0]probe645;
input [0:0]probe646;
input [0:0]probe647;
input [0:0]probe648;
input [0:0]probe649;
input [0:0]probe650;
input [0:0]probe651;
input [0:0]probe652;
input [0:0]probe653;
input [0:0]probe654;
input [0:0]probe655;
input [0:0]probe656;
input [0:0]probe657;
input [0:0]probe658;
input [0:0]probe659;
input [0:0]probe660;
input [0:0]probe661;
input [0:0]probe662;
input [0:0]probe663;
input [0:0]probe664;
input [0:0]probe665;
input [0:0]probe666;
input [0:0]probe667;
input [0:0]probe668;
input [0:0]probe669;
input [0:0]probe670;
input [0:0]probe671;
input [0:0]probe672;
input [0:0]probe673;
input [0:0]probe674;
input [0:0]probe675;
input [0:0]probe676;
input [0:0]probe677;
input [0:0]probe678;
input [0:0]probe679;
input [0:0]probe680;
input [0:0]probe681;
input [0:0]probe682;
input [0:0]probe683;
input [0:0]probe684;
input [0:0]probe685;
input [0:0]probe686;
input [0:0]probe687;
input [0:0]probe688;
input [0:0]probe689;
input [0:0]probe690;
input [0:0]probe691;
input [0:0]probe692;
input [0:0]probe693;
input [0:0]probe694;
input [0:0]probe695;
input [0:0]probe696;
input [0:0]probe697;
input [0:0]probe698;
input [0:0]probe699;
input [0:0]probe700;
input [0:0]probe701;
input [0:0]probe702;
input [0:0]probe703;
input [0:0]probe704;
input [0:0]probe705;
input [0:0]probe706;
input [0:0]probe707;
input [0:0]probe708;
input [0:0]probe709;
input [0:0]probe710;
input [0:0]probe711;
input [0:0]probe712;
input [0:0]probe713;
input [0:0]probe714;
input [0:0]probe715;
input [0:0]probe716;
input [0:0]probe717;
input [0:0]probe718;
input [0:0]probe719;
input [0:0]probe720;
input [0:0]probe721;
input [0:0]probe722;
input [0:0]probe723;
input [0:0]probe724;
input [0:0]probe725;
input [0:0]probe726;
input [0:0]probe727;
input [0:0]probe728;
input [0:0]probe729;
input [0:0]probe730;
input [0:0]probe731;
input [0:0]probe732;
input [0:0]probe733;
input [0:0]probe734;
input [0:0]probe735;
input [0:0]probe736;
input [0:0]probe737;
input [0:0]probe738;
input [0:0]probe739;
input [0:0]probe740;
input [0:0]probe741;
input [0:0]probe742;
input [0:0]probe743;
input [0:0]probe744;
input [0:0]probe745;
input [0:0]probe746;
input [0:0]probe747;
input [0:0]probe748;
input [0:0]probe749;
input [0:0]probe750;
input [0:0]probe751;
input [0:0]probe752;
input [0:0]probe753;
input [0:0]probe754;
input [0:0]probe755;
input [0:0]probe756;
input [0:0]probe757;
input [0:0]probe758;
input [0:0]probe759;
input [0:0]probe760;
input [0:0]probe761;
input [0:0]probe762;
input [0:0]probe763;
input [0:0]probe764;
input [0:0]probe765;
input [0:0]probe766;
input [0:0]probe767;
input [0:0]probe768;
input [0:0]probe769;
input [0:0]probe770;
input [0:0]probe771;
input [0:0]probe772;
input [0:0]probe773;
input [0:0]probe774;
input [0:0]probe775;
input [0:0]probe776;
input [0:0]probe777;
input [0:0]probe778;
input [0:0]probe779;
input [0:0]probe780;
input [0:0]probe781;
input [0:0]probe782;
input [0:0]probe783;
input [0:0]probe784;
input [0:0]probe785;
input [0:0]probe786;
input [0:0]probe787;
input [0:0]probe788;
input [0:0]probe789;
input [0:0]probe790;
input [0:0]probe791;
input [0:0]probe792;
input [0:0]probe793;
input [0:0]probe794;
input [0:0]probe795;
input [0:0]probe796;
input [0:0]probe797;
input [0:0]probe798;
input [0:0]probe799;
input [0:0]probe800;
input [0:0]probe801;
input [0:0]probe802;
input [0:0]probe803;
input [0:0]probe804;
input [0:0]probe805;
input [0:0]probe806;
input [0:0]probe807;
input [0:0]probe808;
input [0:0]probe809;
input [0:0]probe810;
input [0:0]probe811;
input [0:0]probe812;
input [0:0]probe813;
input [0:0]probe814;
input [0:0]probe815;
input [0:0]probe816;
input [0:0]probe817;
input [0:0]probe818;
input [0:0]probe819;
input [0:0]probe820;
input [0:0]probe821;
input [0:0]probe822;
input [0:0]probe823;
input [0:0]probe824;
input [0:0]probe825;
input [0:0]probe826;
input [0:0]probe827;
input [0:0]probe828;
input [0:0]probe829;
input [0:0]probe830;
input [0:0]probe831;
input [0:0]probe832;
input [0:0]probe833;
input [0:0]probe834;
input [0:0]probe835;
input [0:0]probe836;
input [0:0]probe837;
input [0:0]probe838;
input [0:0]probe839;
input [0:0]probe840;
input [0:0]probe841;
input [0:0]probe842;
input [0:0]probe843;
input [0:0]probe844;
input [0:0]probe845;
input [0:0]probe846;
input [0:0]probe847;
input [0:0]probe848;
input [0:0]probe849;
input [0:0]probe850;
input [0:0]probe851;
input [0:0]probe852;
input [0:0]probe853;
input [0:0]probe854;
input [0:0]probe855;
input [0:0]probe856;
input [0:0]probe857;
input [0:0]probe858;
input [0:0]probe859;
input [0:0]probe860;
input [0:0]probe861;
input [0:0]probe862;
input [0:0]probe863;
input [0:0]probe864;
input [0:0]probe865;
input [0:0]probe866;
input [0:0]probe867;
input [0:0]probe868;
input [0:0]probe869;
input [0:0]probe870;
input [0:0]probe871;
input [0:0]probe872;
input [0:0]probe873;
input [0:0]probe874;
input [0:0]probe875;
input [0:0]probe876;
input [0:0]probe877;
input [0:0]probe878;
input [0:0]probe879;
input [0:0]probe880;
input [0:0]probe881;
input [0:0]probe882;
input [0:0]probe883;
input [0:0]probe884;
input [0:0]probe885;
input [0:0]probe886;
input [0:0]probe887;
input [0:0]probe888;
input [0:0]probe889;
input [0:0]probe890;
input [0:0]probe891;
input [0:0]probe892;
input [0:0]probe893;
input [0:0]probe894;
input [0:0]probe895;
input [0:0]probe896;
input [0:0]probe897;
input [0:0]probe898;
input [0:0]probe899;
input [0:0]probe900;
input [0:0]probe901;
input [0:0]probe902;
input [0:0]probe903;
input [0:0]probe904;
input [0:0]probe905;
input [0:0]probe906;
input [0:0]probe907;
input [0:0]probe908;
input [0:0]probe909;
input [0:0]probe910;
input [0:0]probe911;
input [0:0]probe912;
input [0:0]probe913;
input [0:0]probe914;
input [0:0]probe915;
input [0:0]probe916;
input [0:0]probe917;
input [0:0]probe918;
input [0:0]probe919;
input [0:0]probe920;
input [0:0]probe921;
input [0:0]probe922;
input [0:0]probe923;
input [0:0]probe924;
input [0:0]probe925;
input [0:0]probe926;
input [0:0]probe927;
input [0:0]probe928;
input [0:0]probe929;
input [0:0]probe930;
input [0:0]probe931;
input [0:0]probe932;
input [0:0]probe933;
input [0:0]probe934;
input [0:0]probe935;
input [0:0]probe936;
input [0:0]probe937;
input [0:0]probe938;
input [0:0]probe939;
input [0:0]probe940;
input [0:0]probe941;
input [0:0]probe942;
input [0:0]probe943;
input [0:0]probe944;
input [0:0]probe945;
input [0:0]probe946;
input [0:0]probe947;
input [0:0]probe948;
input [0:0]probe949;
input [0:0]probe950;
input [0:0]probe951;
input [0:0]probe952;
input [0:0]probe953;
input [0:0]probe954;
input [0:0]probe955;
input [0:0]probe956;
input [0:0]probe957;
input [0:0]probe958;
input [0:0]probe959;
input [0:0]probe960;
input [0:0]probe961;
input [0:0]probe962;
input [0:0]probe963;
input [0:0]probe964;
input [0:0]probe965;
input [0:0]probe966;
input [0:0]probe967;
input [0:0]probe968;
input [0:0]probe969;
input [0:0]probe970;
input [0:0]probe971;
input [0:0]probe972;
input [0:0]probe973;
input [0:0]probe974;
input [0:0]probe975;
input [0:0]probe976;
input [0:0]probe977;
input [0:0]probe978;
input [0:0]probe979;
input [0:0]probe980;
input [0:0]probe981;
input [0:0]probe982;
input [0:0]probe983;
input [0:0]probe984;
input [0:0]probe985;
input [0:0]probe986;
input [0:0]probe987;
input [0:0]probe988;
input [0:0]probe989;
input [0:0]probe990;
input [0:0]probe991;
input [0:0]probe992;
input [0:0]probe993;
input [0:0]probe994;
input [0:0]probe995;
input [0:0]probe996;
input [0:0]probe997;
input [0:0]probe998;
input [0:0]probe999;
input [0:0]probe1000;
input [0:0]probe1001;
input [0:0]probe1002;
input [0:0]probe1003;
input [0:0]probe1004;
input [0:0]probe1005;
input [0:0]probe1006;
input [0:0]probe1007;
input [0:0]probe1008;
input [0:0]probe1009;
input [0:0]probe1010;
input [0:0]probe1011;
input [0:0]probe1012;
input [0:0]probe1013;
input [0:0]probe1014;
input [0:0]probe1015;
input [0:0]probe1016;
input [0:0]probe1017;
input [0:0]probe1018;
input [0:0]probe1019;
input [0:0]probe1020;
input [0:0]probe1021;
input [0:0]probe1022;
input [0:0]probe1023;
wire \<const0> ;
(* RTL_KEEP = "true" *) wire clk1x;
(* DONT_TOUCH *) wire dummy;
wire [0:0]probe0;
wire [0:0]probe1;
wire [15:0]probe2;
wire [15:0]probe3;
wire [0:0]probe4;
wire [0:0]probe5;
wire [12:0]probe6;
wire [0:0]probe7;
wire [1:0]probe8;
(* DONT_TOUCH *) wire [36:0]sl_iport0;
(* DONT_TOUCH *) wire [16:0]sl_oport0;
assign clk1x = clk;
assign clkdiv_out = \<const0> ;
assign trig_in_ack = \<const0> ;
assign trig_out = \<const0> ;
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(dummy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_core ila_core_inst
(.DUMMY_I(dummy),
.SL_IPORT_I(sl_iport0),
.SL_OPORT_O(sl_oport0),
.out(clk1x),
.probe0(probe0),
.probe1(probe1),
.probe2(probe2),
.probe3(probe3),
.probe4(probe4),
.probe5(probe5),
.probe6(probe6),
.probe7(probe7),
.probe8(probe8));
endmodule | 8 |
2,141 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_adv_trigger_sequencer
(trig_out_fsm,
capture_fsm,
flag0_temp,
flag1_temp,
flag2_temp,
flag3_temp,
\SEQUENCER_STATE_O_reg[11]_0 ,
\SEQUENCER_STATE_O_reg[11]_1 ,
\SEQUENCER_STATE_O_reg[11]_2 ,
\current_state_reg[0]_0 ,
CNT_CTRL,
trigger_reg_0,
A,
\CFG_DATA_O_reg[7] ,
SEQUENCER_STATE_O,
COUNTER_EQ,
toggle_rd,
S_DCLK_O,
bram_rd_en,
E,
bram_en,
CAP_DONE_O_reg,
out,
cap_done,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,
O_reg,
basic_trigger,
en_adv_trigger,
Q,
dout_reg1_reg,
\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ,
p_2_out,
\BRAM_DATA_reg[15] ,
ADDRA,
\BRAM_DATA_reg[23] ,
dout_reg1_reg_0);
output trig_out_fsm;
output capture_fsm;
output flag0_temp;
output flag1_temp;
output flag2_temp;
output flag3_temp;
output \SEQUENCER_STATE_O_reg[11]_0 ;
output \SEQUENCER_STATE_O_reg[11]_1 ;
output \SEQUENCER_STATE_O_reg[11]_2 ;
output \current_state_reg[0]_0 ;
output [7:0]CNT_CTRL;
output trigger_reg_0;
output [0:0]A;
output [23:0]\CFG_DATA_O_reg[7] ;
output [15:0]SEQUENCER_STATE_O;
input [3:0]COUNTER_EQ;
input toggle_rd;
input S_DCLK_O;
input bram_rd_en;
input [0:0]E;
input bram_en;
input CAP_DONE_O_reg;
input out;
input cap_done;
input \I_YESLUT6.I_YES_OREG.O_reg_reg ;
input \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
input O_reg;
input basic_trigger;
input en_adv_trigger;
input [1:0]Q;
input dout_reg1_reg;
input \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ;
input [0:0]p_2_out;
input [15:0]\BRAM_DATA_reg[15] ;
input [1:0]ADDRA;
input [7:0]\BRAM_DATA_reg[23] ;
input dout_reg1_reg_0;
wire [0:0]A;
wire [1:0]ADDRA;
wire [15:0]\BRAM_DATA_reg[15] ;
wire [7:0]\BRAM_DATA_reg[23] ;
wire CAPTURE_O_i_1_n_0;
wire CAP_DONE_O_reg;
wire [23:0]CFG_BRAM_RD_DATA0;
wire \CFG_BRAM_RD_DATA[23]_i_1_n_0 ;
wire [23:0]\CFG_DATA_O_reg[7] ;
wire [7:0]CNT_CTRL;
wire [3:0]COUNTER_EQ;
wire [0:0]E;
wire FLAG0_O010_out;
wire FLAG0_O18_out;
wire FLAG0_O_i_1_n_0;
wire FLAG1_O0;
wire FLAG1_O1__0;
wire FLAG1_O_i_1_n_0;
wire FLAG2_O0;
wire FLAG2_O1__0;
wire FLAG2_O_i_1_n_0;
wire FLAG3_O0;
wire FLAG3_O1__0;
wire FLAG3_O_i_1_n_0;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ;
wire O_reg;
wire [1:0]Q;
wire [15:0]SEQUENCER_STATE_O;
wire \SEQUENCER_STATE_O[10]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[11]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[12]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[13]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[14]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[15]_i_2_n_0 ;
wire \SEQUENCER_STATE_O[7]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[8]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[9]_i_1_n_0 ;
wire \SEQUENCER_STATE_O_reg[11]_0 ;
wire \SEQUENCER_STATE_O_reg[11]_1 ;
wire \SEQUENCER_STATE_O_reg[11]_2 ;
wire S_DCLK_O;
wire basic_trigger;
wire \bram_addr[6]_i_1_n_0 ;
wire \bram_addr[6]_i_3_n_0 ;
wire [6:0]bram_addr_reg;
wire bram_en;
wire bram_en_1;
wire \bram_rd_addr[6]_i_2_n_0 ;
wire [6:0]bram_rd_addr_reg;
wire bram_rd_en;
wire bram_rd_en_0;
wire bram_rd_we;
wire bram_we;
wire cap_done;
wire capture_fsm;
wire [1:0]cntcmpsel;
wire \current_state_reg[0]_0 ;
wire dout_reg1_reg;
wire dout_reg1_reg_0;
wire [18:0]douta;
wire en_adv_trigger;
wire flag0_temp;
wire flag1_temp;
wire flag2_temp;
wire flag3_temp;
wire fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_n_1;
wire fsm_mem_data_reg_r1_0_63_0_2_n_2;
wire fsm_mem_data_reg_r1_0_63_12_14_n_0;
wire fsm_mem_data_reg_r1_0_63_12_14_n_1;
wire fsm_mem_data_reg_r1_0_63_12_14_n_2;
wire fsm_mem_data_reg_r1_0_63_15_17_n_0;
wire fsm_mem_data_reg_r1_0_63_15_17_n_1;
wire fsm_mem_data_reg_r1_0_63_15_17_n_2;
wire fsm_mem_data_reg_r1_0_63_18_20_n_0;
wire fsm_mem_data_reg_r1_0_63_18_20_n_1;
wire fsm_mem_data_reg_r1_0_63_18_20_n_2;
wire fsm_mem_data_reg_r1_0_63_21_23_n_0;
wire fsm_mem_data_reg_r1_0_63_21_23_n_1;
wire fsm_mem_data_reg_r1_0_63_21_23_n_2;
wire fsm_mem_data_reg_r1_0_63_3_5_n_0;
wire fsm_mem_data_reg_r1_0_63_3_5_n_1;
wire fsm_mem_data_reg_r1_0_63_3_5_n_2;
wire fsm_mem_data_reg_r1_0_63_6_8_n_0;
wire fsm_mem_data_reg_r1_0_63_6_8_n_1;
wire fsm_mem_data_reg_r1_0_63_6_8_n_2;
wire fsm_mem_data_reg_r1_0_63_9_11_n_0;
wire fsm_mem_data_reg_r1_0_63_9_11_n_1;
wire fsm_mem_data_reg_r1_0_63_9_11_n_2;
wire fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0;
wire fsm_mem_data_reg_r1_64_127_0_2_n_0;
wire fsm_mem_data_reg_r1_64_127_0_2_n_1;
wire fsm_mem_data_reg_r1_64_127_0_2_n_2;
wire fsm_mem_data_reg_r1_64_127_12_14_n_0;
wire fsm_mem_data_reg_r1_64_127_12_14_n_1;
wire fsm_mem_data_reg_r1_64_127_12_14_n_2;
wire fsm_mem_data_reg_r1_64_127_15_17_n_0;
wire fsm_mem_data_reg_r1_64_127_15_17_n_1;
wire fsm_mem_data_reg_r1_64_127_15_17_n_2;
wire fsm_mem_data_reg_r1_64_127_18_20_n_0;
wire fsm_mem_data_reg_r1_64_127_18_20_n_1;
wire fsm_mem_data_reg_r1_64_127_18_20_n_2;
wire fsm_mem_data_reg_r1_64_127_21_23_n_0;
wire fsm_mem_data_reg_r1_64_127_21_23_n_1;
wire fsm_mem_data_reg_r1_64_127_21_23_n_2;
wire fsm_mem_data_reg_r1_64_127_3_5_n_0;
wire fsm_mem_data_reg_r1_64_127_3_5_n_1;
wire fsm_mem_data_reg_r1_64_127_3_5_n_2;
wire fsm_mem_data_reg_r1_64_127_6_8_n_0;
wire fsm_mem_data_reg_r1_64_127_6_8_n_1;
wire fsm_mem_data_reg_r1_64_127_6_8_n_2;
wire fsm_mem_data_reg_r1_64_127_9_11_n_0;
wire fsm_mem_data_reg_r1_64_127_9_11_n_1;
wire fsm_mem_data_reg_r1_64_127_9_11_n_2;
wire fsm_mem_data_reg_r2_0_63_0_2_n_0;
wire fsm_mem_data_reg_r2_0_63_0_2_n_1;
wire fsm_mem_data_reg_r2_0_63_0_2_n_2;
wire fsm_mem_data_reg_r2_0_63_12_14_n_0;
wire fsm_mem_data_reg_r2_0_63_12_14_n_1;
wire fsm_mem_data_reg_r2_0_63_12_14_n_2;
wire fsm_mem_data_reg_r2_0_63_15_17_n_0;
wire fsm_mem_data_reg_r2_0_63_15_17_n_1;
wire fsm_mem_data_reg_r2_0_63_15_17_n_2;
wire fsm_mem_data_reg_r2_0_63_18_20_n_0;
wire fsm_mem_data_reg_r2_0_63_18_20_n_1;
wire fsm_mem_data_reg_r2_0_63_18_20_n_2;
wire fsm_mem_data_reg_r2_0_63_21_23_n_0;
wire fsm_mem_data_reg_r2_0_63_21_23_n_1;
wire fsm_mem_data_reg_r2_0_63_21_23_n_2;
wire fsm_mem_data_reg_r2_0_63_3_5_n_0;
wire fsm_mem_data_reg_r2_0_63_3_5_n_1;
wire fsm_mem_data_reg_r2_0_63_3_5_n_2;
wire fsm_mem_data_reg_r2_0_63_6_8_n_0;
wire fsm_mem_data_reg_r2_0_63_6_8_n_1;
wire fsm_mem_data_reg_r2_0_63_6_8_n_2;
wire fsm_mem_data_reg_r2_0_63_9_11_n_0;
wire fsm_mem_data_reg_r2_0_63_9_11_n_1;
wire fsm_mem_data_reg_r2_0_63_9_11_n_2;
wire fsm_mem_data_reg_r2_64_127_0_2_n_0;
wire fsm_mem_data_reg_r2_64_127_0_2_n_1;
wire fsm_mem_data_reg_r2_64_127_0_2_n_2;
wire fsm_mem_data_reg_r2_64_127_12_14_n_0;
wire fsm_mem_data_reg_r2_64_127_12_14_n_1;
wire fsm_mem_data_reg_r2_64_127_12_14_n_2;
wire fsm_mem_data_reg_r2_64_127_15_17_n_0;
wire fsm_mem_data_reg_r2_64_127_15_17_n_1;
wire fsm_mem_data_reg_r2_64_127_15_17_n_2;
wire fsm_mem_data_reg_r2_64_127_18_20_n_0;
wire fsm_mem_data_reg_r2_64_127_18_20_n_1;
wire fsm_mem_data_reg_r2_64_127_18_20_n_2;
wire fsm_mem_data_reg_r2_64_127_21_23_n_0;
wire fsm_mem_data_reg_r2_64_127_21_23_n_1;
wire fsm_mem_data_reg_r2_64_127_21_23_n_2;
wire fsm_mem_data_reg_r2_64_127_3_5_n_0;
wire fsm_mem_data_reg_r2_64_127_3_5_n_1;
wire fsm_mem_data_reg_r2_64_127_3_5_n_2;
wire fsm_mem_data_reg_r2_64_127_6_8_n_0;
wire fsm_mem_data_reg_r2_64_127_6_8_n_1;
wire fsm_mem_data_reg_r2_64_127_6_8_n_2;
wire fsm_mem_data_reg_r2_64_127_9_11_n_0;
wire fsm_mem_data_reg_r2_64_127_9_11_n_1;
wire fsm_mem_data_reg_r2_64_127_9_11_n_2;
wire out;
wire [6:0]p_0_in;
wire [6:0]p_0_in__0;
wire [0:0]p_2_out;
wire [0:0]p_34_out__0;
wire toggle_rd;
wire trig_out_fsm;
wire trigger_reg_0;
wire NLW_fsm_mem_data_reg_r1_0_63_0_2_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_12_14_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_15_17_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_18_20_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_21_23_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_3_5_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_6_8_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_9_11_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_0_2_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_12_14_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_15_17_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_18_20_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_21_23_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_3_5_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_6_8_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_9_11_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_0_2_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_12_14_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_15_17_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_18_20_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_21_23_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_3_5_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_6_8_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_9_11_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_0_2_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_12_14_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_15_17_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_18_20_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_21_23_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_3_5_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_6_8_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_9_11_DOD_UNCONNECTED;
LUT5 #(
.INIT(32'hC8C00800))
CAPTURE_O_i_1
(.I0(douta[18]),
.I1(dout_reg1_reg),
.I2(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
.I3(O_reg),
.I4(capture_fsm),
.O(CAPTURE_O_i_1_n_0));
LUT6 #(
.INIT(64'h1011100000000000))
CAPTURE_O_i_2
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_18_20_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_18_20_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[18]));
FDRE CAPTURE_O_reg
(.C(out),
.CE(1'b1),
.D(CAPTURE_O_i_1_n_0),
.Q(capture_fsm),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[0]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_0_2_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_0_2_n_0),
.O(CFG_BRAM_RD_DATA0[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[10]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_9_11_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_9_11_n_1),
.O(CFG_BRAM_RD_DATA0[10]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[11]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_9_11_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_9_11_n_2),
.O(CFG_BRAM_RD_DATA0[11]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[12]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_12_14_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_12_14_n_0),
.O(CFG_BRAM_RD_DATA0[12]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[13]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_12_14_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_12_14_n_1),
.O(CFG_BRAM_RD_DATA0[13]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[14]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_12_14_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_12_14_n_2),
.O(CFG_BRAM_RD_DATA0[14]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[15]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_15_17_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_15_17_n_0),
.O(CFG_BRAM_RD_DATA0[15]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[16]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_15_17_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_15_17_n_1),
.O(CFG_BRAM_RD_DATA0[16]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[17]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_15_17_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_15_17_n_2),
.O(CFG_BRAM_RD_DATA0[17]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[18]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_18_20_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_18_20_n_0),
.O(CFG_BRAM_RD_DATA0[18]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[19]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_18_20_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_18_20_n_1),
.O(CFG_BRAM_RD_DATA0[19]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[1]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_0_2_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_0_2_n_1),
.O(CFG_BRAM_RD_DATA0[1]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[20]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_18_20_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_18_20_n_2),
.O(CFG_BRAM_RD_DATA0[20]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[21]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_21_23_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_21_23_n_0),
.O(CFG_BRAM_RD_DATA0[21]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[22]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_21_23_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_21_23_n_1),
.O(CFG_BRAM_RD_DATA0[22]));
LUT2 #(
.INIT(4'h2))
\CFG_BRAM_RD_DATA[23]_i_1
(.I0(bram_rd_en_0),
.I1(bram_rd_we),
.O(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[23]_i_2
(.I0(fsm_mem_data_reg_r2_64_127_21_23_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_21_23_n_2),
.O(CFG_BRAM_RD_DATA0[23]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[2]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_0_2_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_0_2_n_2),
.O(CFG_BRAM_RD_DATA0[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[3]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_3_5_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_3_5_n_0),
.O(CFG_BRAM_RD_DATA0[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[4]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_3_5_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_3_5_n_1),
.O(CFG_BRAM_RD_DATA0[4]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[5]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_3_5_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_3_5_n_2),
.O(CFG_BRAM_RD_DATA0[5]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[6]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_6_8_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_6_8_n_0),
.O(CFG_BRAM_RD_DATA0[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[7]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_6_8_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_6_8_n_1),
.O(CFG_BRAM_RD_DATA0[7]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[8]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_6_8_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_6_8_n_2),
.O(CFG_BRAM_RD_DATA0[8]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[9]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_9_11_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_9_11_n_0),
.O(CFG_BRAM_RD_DATA0[9]));
FDRE \CFG_BRAM_RD_DATA_reg[0]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[0]),
.Q(\CFG_DATA_O_reg[7] [0]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[10]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[10]),
.Q(\CFG_DATA_O_reg[7] [10]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[11]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[11]),
.Q(\CFG_DATA_O_reg[7] [11]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[12]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[12]),
.Q(\CFG_DATA_O_reg[7] [12]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[13]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[13]),
.Q(\CFG_DATA_O_reg[7] [13]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[14]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[14]),
.Q(\CFG_DATA_O_reg[7] [14]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[15]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[15]),
.Q(\CFG_DATA_O_reg[7] [15]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[16]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[16]),
.Q(\CFG_DATA_O_reg[7] [16]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[17]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[17]),
.Q(\CFG_DATA_O_reg[7] [17]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[18]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[18]),
.Q(\CFG_DATA_O_reg[7] [18]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[19]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[19]),
.Q(\CFG_DATA_O_reg[7] [19]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[1]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[1]),
.Q(\CFG_DATA_O_reg[7] [1]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[20]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[20]),
.Q(\CFG_DATA_O_reg[7] [20]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[21]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[21]),
.Q(\CFG_DATA_O_reg[7] [21]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[22]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[22]),
.Q(\CFG_DATA_O_reg[7] [22]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[23]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[23]),
.Q(\CFG_DATA_O_reg[7] [23]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[2]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[2]),
.Q(\CFG_DATA_O_reg[7] [2]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[3]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[3]),
.Q(\CFG_DATA_O_reg[7] [3]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[4]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[4]),
.Q(\CFG_DATA_O_reg[7] [4]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[5]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[5]),
.Q(\CFG_DATA_O_reg[7] [5]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[6]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[6]),
.Q(\CFG_DATA_O_reg[7] [6]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[7]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[7]),
.Q(\CFG_DATA_O_reg[7] [7]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[8]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[8]),
.Q(\CFG_DATA_O_reg[7] [8]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[9]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[9]),
.Q(\CFG_DATA_O_reg[7] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'hFFFF4500))
FLAG0_O_i_1
(.I0(FLAG0_O18_out),
.I1(Q[0]),
.I2(Q[1]),
.I3(flag0_temp),
.I4(FLAG0_O010_out),
.O(FLAG0_O_i_1_n_0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG0_O_i_2
(.I0(fsm_mem_data_reg_r1_0_63_18_20_n_2),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_18_20_n_2),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG0_O18_out));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG0_O_i_3
(.I0(fsm_mem_data_reg_r1_0_63_12_14_n_2),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_12_14_n_2),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG0_O010_out));
FDRE FLAG0_O_reg
(.C(out),
.CE(1'b1),
.D(FLAG0_O_i_1_n_0),
.Q(flag0_temp),
.R(1'b0));
LUT5 #(
.INIT(32'hFFFF4500))
FLAG1_O_i_1
(.I0(FLAG1_O1__0),
.I1(Q[0]),
.I2(Q[1]),
.I3(flag1_temp),
.I4(FLAG1_O0),
.O(FLAG1_O_i_1_n_0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG1_O_i_2
(.I0(fsm_mem_data_reg_r1_0_63_21_23_n_0),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_21_23_n_0),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG1_O1__0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG1_O_i_3
(.I0(fsm_mem_data_reg_r1_0_63_15_17_n_0),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_15_17_n_0),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG1_O0));
FDRE FLAG1_O_reg
(.C(out),
.CE(1'b1),
.D(FLAG1_O_i_1_n_0),
.Q(flag1_temp),
.R(1'b0));
LUT5 #(
.INIT(32'hFFFF4500))
FLAG2_O_i_1
(.I0(FLAG2_O1__0),
.I1(Q[0]),
.I2(Q[1]),
.I3(flag2_temp),
.I4(FLAG2_O0),
.O(FLAG2_O_i_1_n_0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG2_O_i_2
(.I0(fsm_mem_data_reg_r1_0_63_21_23_n_1),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_21_23_n_1),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG2_O1__0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG2_O_i_3
(.I0(fsm_mem_data_reg_r1_0_63_15_17_n_1),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_15_17_n_1),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG2_O0));
FDRE FLAG2_O_reg
(.C(out),
.CE(1'b1),
.D(FLAG2_O_i_1_n_0),
.Q(flag2_temp),
.R(1'b0));
LUT5 #(
.INIT(32'hFFFF4500))
FLAG3_O_i_1
(.I0(FLAG3_O1__0),
.I1(Q[0]),
.I2(Q[1]),
.I3(flag3_temp),
.I4(FLAG3_O0),
.O(FLAG3_O_i_1_n_0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG3_O_i_2
(.I0(fsm_mem_data_reg_r1_0_63_21_23_n_2),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_21_23_n_2),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG3_O1__0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG3_O_i_3
(.I0(fsm_mem_data_reg_r1_0_63_15_17_n_2),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_15_17_n_2),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG3_O0));
FDRE FLAG3_O_reg
(.C(out),
.CE(1'b1),
.D(FLAG3_O_i_1_n_0),
.Q(flag3_temp),
.R(1'b0));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[0].U_COUNTER_i_2
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_3_5_n_2),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_3_5_n_2),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[1]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[0].U_COUNTER_i_3
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_3_5_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_3_5_n_1),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[0]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[1].U_COUNTER_i_1
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_6_8_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_6_8_n_1),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[3]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[1].U_COUNTER_i_2
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_6_8_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_6_8_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[2]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[2].U_COUNTER_i_1
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_9_11_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_9_11_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[5]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[2].U_COUNTER_i_2
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_6_8_n_2),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_6_8_n_2),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[4]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[3].U_COUNTER_i_1
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_9_11_n_2),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_9_11_n_2),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[7]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[3].U_COUNTER_i_2
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_9_11_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_9_11_n_1),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[6]));
LUT3 #(
.INIT(8'hE2))
\I_YESLUT6.U_SRL32_D_i_2
(.I0(basic_trigger),
.I1(en_adv_trigger),
.I2(trig_out_fsm),
.O(A));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h04))
\SEQUENCER_STATE_O[10]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_0 ),
.I1(\SEQUENCER_STATE_O_reg[11]_1 ),
.I2(\SEQUENCER_STATE_O_reg[11]_2 ),
.O(\SEQUENCER_STATE_O[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h08))
\SEQUENCER_STATE_O[11]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_0 ),
.I1(\SEQUENCER_STATE_O_reg[11]_1 ),
.I2(\SEQUENCER_STATE_O_reg[11]_2 ),
.O(\SEQUENCER_STATE_O[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h02))
\SEQUENCER_STATE_O[12]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_2 ),
.I1(\SEQUENCER_STATE_O_reg[11]_0 ),
.I2(\SEQUENCER_STATE_O_reg[11]_1 ),
.O(\SEQUENCER_STATE_O[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h20))
\SEQUENCER_STATE_O[13]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_2 ),
.I1(\SEQUENCER_STATE_O_reg[11]_1 ),
.I2(\SEQUENCER_STATE_O_reg[11]_0 ),
.O(\SEQUENCER_STATE_O[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h20))
\SEQUENCER_STATE_O[14]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_2 ),
.I1(\SEQUENCER_STATE_O_reg[11]_0 ),
.I2(\SEQUENCER_STATE_O_reg[11]_1 ),
.O(\SEQUENCER_STATE_O[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h80))
\SEQUENCER_STATE_O[15]_i_2
(.I0(\SEQUENCER_STATE_O_reg[11]_2 ),
.I1(\SEQUENCER_STATE_O_reg[11]_0 ),
.I2(\SEQUENCER_STATE_O_reg[11]_1 ),
.O(\SEQUENCER_STATE_O[15]_i_2_n_0 ));
LUT3 #(
.INIT(8'h08))
\SEQUENCER_STATE_O[7]_i_1
(.I0(\current_state_reg[0]_0 ),
.I1(dout_reg1_reg),
.I2(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
.O(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h01))
\SEQUENCER_STATE_O[8]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_0 ),
.I1(\SEQUENCER_STATE_O_reg[11]_1 ),
.I2(\SEQUENCER_STATE_O_reg[11]_2 ),
.O(\SEQUENCER_STATE_O[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h04))
\SEQUENCER_STATE_O[9]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_1 ),
.I1(\SEQUENCER_STATE_O_reg[11]_0 ),
.I2(\SEQUENCER_STATE_O_reg[11]_2 ),
.O(\SEQUENCER_STATE_O[9]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[0]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[8]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[0]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[10]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[10]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[10]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[11]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[11]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[11]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[12]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[12]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[12]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[13]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[13]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[13]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[14]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[14]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[14]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[15]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[15]_i_2_n_0 ),
.Q(SEQUENCER_STATE_O[15]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[1]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[9]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[1]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[2]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[10]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[2]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[3]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[11]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[3]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[4]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[12]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[4]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[5]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[13]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[5]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[6]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[14]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[6]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[7]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[15]_i_2_n_0 ),
.Q(SEQUENCER_STATE_O[7]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[8]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[8]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[8]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[9]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[9]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[9]),
.R(dout_reg1_reg_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT1 #(
.INIT(2'h1))
\bram_addr[0]_i_1
(.I0(bram_addr_reg[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h6))
\bram_addr[1]_i_1
(.I0(bram_addr_reg[0]),
.I1(bram_addr_reg[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\bram_addr[2]_i_1
(.I0(bram_addr_reg[0]),
.I1(bram_addr_reg[1]),
.I2(bram_addr_reg[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h7F80))
\bram_addr[3]_i_1
(.I0(bram_addr_reg[1]),
.I1(bram_addr_reg[0]),
.I2(bram_addr_reg[2]),
.I3(bram_addr_reg[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\bram_addr[4]_i_1
(.I0(bram_addr_reg[2]),
.I1(bram_addr_reg[0]),
.I2(bram_addr_reg[1]),
.I3(bram_addr_reg[3]),
.I4(bram_addr_reg[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\bram_addr[5]_i_1
(.I0(bram_addr_reg[3]),
.I1(bram_addr_reg[1]),
.I2(bram_addr_reg[0]),
.I3(bram_addr_reg[2]),
.I4(bram_addr_reg[4]),
.I5(bram_addr_reg[5]),
.O(p_0_in__0[5]));
LUT2 #(
.INIT(4'h8))
\bram_addr[6]_i_1
(.I0(bram_en_1),
.I1(bram_we),
.O(\bram_addr[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'h78))
\bram_addr[6]_i_2
(.I0(\bram_addr[6]_i_3_n_0 ),
.I1(bram_addr_reg[5]),
.I2(bram_addr_reg[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h80000000))
\bram_addr[6]_i_3
(.I0(bram_addr_reg[4]),
.I1(bram_addr_reg[2]),
.I2(bram_addr_reg[0]),
.I3(bram_addr_reg[1]),
.I4(bram_addr_reg[3]),
.O(\bram_addr[6]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[0]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[0]),
.Q(bram_addr_reg[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[1]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[1]),
.Q(bram_addr_reg[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[2]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[2]),
.Q(bram_addr_reg[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[3]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[3]),
.Q(bram_addr_reg[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[4]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[4]),
.Q(bram_addr_reg[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[5]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[5]),
.Q(bram_addr_reg[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[6]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[6]),
.Q(bram_addr_reg[6]),
.R(1'b0));
FDRE bram_en_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(bram_en),
.Q(bram_en_1),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT1 #(
.INIT(2'h1))
\bram_rd_addr[0]_i_1
(.I0(bram_rd_addr_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h6))
\bram_rd_addr[1]_i_1
(.I0(bram_rd_addr_reg[0]),
.I1(bram_rd_addr_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h78))
\bram_rd_addr[2]_i_1
(.I0(bram_rd_addr_reg[0]),
.I1(bram_rd_addr_reg[1]),
.I2(bram_rd_addr_reg[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h7F80))
\bram_rd_addr[3]_i_1
(.I0(bram_rd_addr_reg[1]),
.I1(bram_rd_addr_reg[0]),
.I2(bram_rd_addr_reg[2]),
.I3(bram_rd_addr_reg[3]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\bram_rd_addr[4]_i_1
(.I0(bram_rd_addr_reg[2]),
.I1(bram_rd_addr_reg[0]),
.I2(bram_rd_addr_reg[1]),
.I3(bram_rd_addr_reg[3]),
.I4(bram_rd_addr_reg[4]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\bram_rd_addr[5]_i_1
(.I0(bram_rd_addr_reg[3]),
.I1(bram_rd_addr_reg[1]),
.I2(bram_rd_addr_reg[0]),
.I3(bram_rd_addr_reg[2]),
.I4(bram_rd_addr_reg[4]),
.I5(bram_rd_addr_reg[5]),
.O(p_0_in[5]));
LUT3 #(
.INIT(8'h78))
\bram_rd_addr[6]_i_1
(.I0(\bram_rd_addr[6]_i_2_n_0 ),
.I1(bram_rd_addr_reg[5]),
.I2(bram_rd_addr_reg[6]),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h80000000))
\bram_rd_addr[6]_i_2
(.I0(bram_rd_addr_reg[4]),
.I1(bram_rd_addr_reg[2]),
.I2(bram_rd_addr_reg[0]),
.I3(bram_rd_addr_reg[1]),
.I4(bram_rd_addr_reg[3]),
.O(\bram_rd_addr[6]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[0]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[0]),
.Q(bram_rd_addr_reg[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[1]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[1]),
.Q(bram_rd_addr_reg[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[2]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[2]),
.Q(bram_rd_addr_reg[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[3]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[3]),
.Q(bram_rd_addr_reg[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[4]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[4]),
.Q(bram_rd_addr_reg[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[5]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[5]),
.Q(bram_rd_addr_reg[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[6]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[6]),
.Q(bram_rd_addr_reg[6]),
.R(1'b0));
FDRE bram_rd_en_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(bram_rd_en),
.Q(bram_rd_en_0),
.R(1'b0));
FDRE bram_rd_we_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(toggle_rd),
.Q(bram_rd_we),
.R(1'b0));
FDRE bram_we_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(E),
.Q(bram_we),
.R(1'b0));
LUT6 #(
.INIT(64'h1011100000000000))
\cntcmpsel[0]_i_1
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_12_14_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_12_14_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[12]));
LUT6 #(
.INIT(64'h1011100000000000))
\cntcmpsel[1]_i_3
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_12_14_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_12_14_n_1),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[13]));
FDRE \cntcmpsel_reg[0]
(.C(out),
.CE(p_2_out),
.D(douta[12]),
.Q(cntcmpsel[0]),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
FDRE \cntcmpsel_reg[1]
(.C(out),
.CE(p_2_out),
.D(douta[13]),
.Q(cntcmpsel[1]),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
LUT6 #(
.INIT(64'h1011100000000000))
\current_state[0]_i_1__47
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_0_2_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_0_2_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[0]));
LUT6 #(
.INIT(64'h1011100000000000))
\current_state[1]_i_1__47
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_0_2_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_0_2_n_1),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[1]));
LUT6 #(
.INIT(64'h1011100000000000))
\current_state[2]_i_1__47
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_0_2_n_2),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_0_2_n_2),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[2]));
LUT6 #(
.INIT(64'h1011100000000000))
\current_state[3]_i_1__47
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_3_5_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_3_5_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[3]));
FDRE \current_state_reg[0]
(.C(out),
.CE(p_2_out),
.D(douta[0]),
.Q(\SEQUENCER_STATE_O_reg[11]_0 ),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
FDRE \current_state_reg[1]
(.C(out),
.CE(p_2_out),
.D(douta[1]),
.Q(\SEQUENCER_STATE_O_reg[11]_1 ),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
FDRE \current_state_reg[2]
(.C(out),
.CE(p_2_out),
.D(douta[2]),
.Q(\SEQUENCER_STATE_O_reg[11]_2 ),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
FDRE \current_state_reg[3]
(.C(out),
.CE(p_2_out),
.D(douta[3]),
.Q(\current_state_reg[0]_0 ),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_0_2
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [0]),
.DIB(\BRAM_DATA_reg[15] [1]),
.DIC(\BRAM_DATA_reg[15] [2]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_0_2_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_0_2_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_0_2_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_0_2_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
LUT3 #(
.INIT(8'h08))
fsm_mem_data_reg_r1_0_63_0_2_i_1
(.I0(bram_we),
.I1(bram_en_1),
.I2(bram_addr_reg[6]),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_12_14
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [12]),
.DIB(\BRAM_DATA_reg[15] [13]),
.DIC(\BRAM_DATA_reg[15] [14]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_12_14_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_12_14_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_12_14_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_12_14_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_15_17
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [15]),
.DIB(\BRAM_DATA_reg[23] [0]),
.DIC(\BRAM_DATA_reg[23] [1]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_15_17_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_15_17_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_15_17_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_15_17_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_18_20
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [2]),
.DIB(\BRAM_DATA_reg[23] [3]),
.DIC(\BRAM_DATA_reg[23] [4]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_18_20_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_18_20_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_18_20_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_18_20_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_21_23
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [5]),
.DIB(\BRAM_DATA_reg[23] [6]),
.DIC(\BRAM_DATA_reg[23] [7]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_21_23_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_21_23_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_21_23_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_21_23_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_3_5
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [3]),
.DIB(\BRAM_DATA_reg[15] [4]),
.DIC(\BRAM_DATA_reg[15] [5]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_3_5_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_3_5_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_3_5_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_3_5_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_6_8
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [6]),
.DIB(\BRAM_DATA_reg[15] [7]),
.DIC(\BRAM_DATA_reg[15] [8]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_6_8_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_6_8_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_6_8_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_6_8_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_9_11
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [9]),
.DIB(\BRAM_DATA_reg[15] [10]),
.DIC(\BRAM_DATA_reg[15] [11]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_9_11_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_9_11_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_9_11_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_9_11_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_0_2
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [0]),
.DIB(\BRAM_DATA_reg[15] [1]),
.DIC(\BRAM_DATA_reg[15] [2]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_0_2_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_0_2_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_0_2_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_0_2_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
LUT3 #(
.INIT(8'h80))
fsm_mem_data_reg_r1_64_127_0_2_i_1
(.I0(bram_we),
.I1(bram_en_1),
.I2(bram_addr_reg[6]),
.O(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_12_14
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [12]),
.DIB(\BRAM_DATA_reg[15] [13]),
.DIC(\BRAM_DATA_reg[15] [14]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_12_14_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_12_14_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_12_14_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_12_14_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_15_17
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [15]),
.DIB(\BRAM_DATA_reg[23] [0]),
.DIC(\BRAM_DATA_reg[23] [1]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_15_17_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_15_17_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_15_17_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_15_17_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_18_20
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [2]),
.DIB(\BRAM_DATA_reg[23] [3]),
.DIC(\BRAM_DATA_reg[23] [4]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_18_20_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_18_20_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_18_20_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_18_20_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_21_23
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [5]),
.DIB(\BRAM_DATA_reg[23] [6]),
.DIC(\BRAM_DATA_reg[23] [7]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_21_23_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_21_23_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_21_23_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_21_23_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_3_5
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [3]),
.DIB(\BRAM_DATA_reg[15] [4]),
.DIC(\BRAM_DATA_reg[15] [5]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_3_5_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_3_5_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_3_5_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_3_5_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_6_8
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [6]),
.DIB(\BRAM_DATA_reg[15] [7]),
.DIC(\BRAM_DATA_reg[15] [8]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_6_8_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_6_8_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_6_8_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_6_8_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_9_11
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [9]),
.DIB(\BRAM_DATA_reg[15] [10]),
.DIC(\BRAM_DATA_reg[15] [11]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_9_11_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_9_11_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_9_11_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_9_11_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_0_2
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [0]),
.DIB(\BRAM_DATA_reg[15] [1]),
.DIC(\BRAM_DATA_reg[15] [2]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_0_2_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_0_2_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_0_2_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_0_2_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_12_14
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [12]),
.DIB(\BRAM_DATA_reg[15] [13]),
.DIC(\BRAM_DATA_reg[15] [14]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_12_14_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_12_14_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_12_14_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_12_14_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_15_17
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [15]),
.DIB(\BRAM_DATA_reg[23] [0]),
.DIC(\BRAM_DATA_reg[23] [1]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_15_17_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_15_17_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_15_17_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_15_17_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_18_20
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [2]),
.DIB(\BRAM_DATA_reg[23] [3]),
.DIC(\BRAM_DATA_reg[23] [4]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_18_20_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_18_20_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_18_20_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_18_20_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_21_23
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [5]),
.DIB(\BRAM_DATA_reg[23] [6]),
.DIC(\BRAM_DATA_reg[23] [7]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_21_23_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_21_23_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_21_23_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_21_23_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_3_5
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [3]),
.DIB(\BRAM_DATA_reg[15] [4]),
.DIC(\BRAM_DATA_reg[15] [5]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_3_5_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_3_5_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_3_5_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_3_5_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_6_8
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [6]),
.DIB(\BRAM_DATA_reg[15] [7]),
.DIC(\BRAM_DATA_reg[15] [8]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_6_8_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_6_8_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_6_8_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_6_8_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_9_11
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [9]),
.DIB(\BRAM_DATA_reg[15] [10]),
.DIC(\BRAM_DATA_reg[15] [11]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_9_11_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_9_11_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_9_11_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_9_11_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_0_2
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [0]),
.DIB(\BRAM_DATA_reg[15] [1]),
.DIC(\BRAM_DATA_reg[15] [2]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_0_2_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_0_2_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_0_2_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_0_2_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_12_14
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [12]),
.DIB(\BRAM_DATA_reg[15] [13]),
.DIC(\BRAM_DATA_reg[15] [14]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_12_14_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_12_14_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_12_14_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_12_14_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_15_17
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [15]),
.DIB(\BRAM_DATA_reg[23] [0]),
.DIC(\BRAM_DATA_reg[23] [1]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_15_17_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_15_17_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_15_17_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_15_17_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_18_20
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [2]),
.DIB(\BRAM_DATA_reg[23] [3]),
.DIC(\BRAM_DATA_reg[23] [4]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_18_20_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_18_20_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_18_20_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_18_20_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_21_23
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [5]),
.DIB(\BRAM_DATA_reg[23] [6]),
.DIC(\BRAM_DATA_reg[23] [7]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_21_23_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_21_23_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_21_23_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_21_23_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_3_5
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [3]),
.DIB(\BRAM_DATA_reg[15] [4]),
.DIC(\BRAM_DATA_reg[15] [5]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_3_5_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_3_5_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_3_5_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_3_5_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_6_8
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [6]),
.DIB(\BRAM_DATA_reg[15] [7]),
.DIC(\BRAM_DATA_reg[15] [8]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_6_8_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_6_8_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_6_8_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_6_8_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_9_11
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [9]),
.DIB(\BRAM_DATA_reg[15] [10]),
.DIC(\BRAM_DATA_reg[15] [11]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_9_11_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_9_11_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_9_11_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_9_11_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
p_34_out
(.I0(COUNTER_EQ[3]),
.I1(COUNTER_EQ[1]),
.I2(cntcmpsel[0]),
.I3(COUNTER_EQ[2]),
.I4(cntcmpsel[1]),
.I5(COUNTER_EQ[0]),
.O(p_34_out__0));
LUT5 #(
.INIT(32'hBBBFFFBF))
trigger_i_2
(.I0(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
.I1(O_reg),
.I2(fsm_mem_data_reg_r1_0_63_18_20_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_64_127_18_20_n_1),
.O(trigger_reg_0));
FDRE trigger_reg
(.C(out),
.CE(1'b1),
.D(CAP_DONE_O_reg),
.Q(trig_out_fsm),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_adv_trigger_sequencer
(trig_out_fsm,
capture_fsm,
flag0_temp,
flag1_temp,
flag2_temp,
flag3_temp,
\SEQUENCER_STATE_O_reg[11]_0 ,
\SEQUENCER_STATE_O_reg[11]_1 ,
\SEQUENCER_STATE_O_reg[11]_2 ,
\current_state_reg[0]_0 ,
CNT_CTRL,
trigger_reg_0,
A,
\CFG_DATA_O_reg[7] ,
SEQUENCER_STATE_O,
COUNTER_EQ,
toggle_rd,
S_DCLK_O,
bram_rd_en,
E,
bram_en,
CAP_DONE_O_reg,
out,
cap_done,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ,
O_reg,
basic_trigger,
en_adv_trigger,
Q,
dout_reg1_reg,
\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ,
p_2_out,
\BRAM_DATA_reg[15] ,
ADDRA,
\BRAM_DATA_reg[23] ,
dout_reg1_reg_0); |
output trig_out_fsm;
output capture_fsm;
output flag0_temp;
output flag1_temp;
output flag2_temp;
output flag3_temp;
output \SEQUENCER_STATE_O_reg[11]_0 ;
output \SEQUENCER_STATE_O_reg[11]_1 ;
output \SEQUENCER_STATE_O_reg[11]_2 ;
output \current_state_reg[0]_0 ;
output [7:0]CNT_CTRL;
output trigger_reg_0;
output [0:0]A;
output [23:0]\CFG_DATA_O_reg[7] ;
output [15:0]SEQUENCER_STATE_O;
input [3:0]COUNTER_EQ;
input toggle_rd;
input S_DCLK_O;
input bram_rd_en;
input [0:0]E;
input bram_en;
input CAP_DONE_O_reg;
input out;
input cap_done;
input \I_YESLUT6.I_YES_OREG.O_reg_reg ;
input \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
input O_reg;
input basic_trigger;
input en_adv_trigger;
input [1:0]Q;
input dout_reg1_reg;
input \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ;
input [0:0]p_2_out;
input [15:0]\BRAM_DATA_reg[15] ;
input [1:0]ADDRA;
input [7:0]\BRAM_DATA_reg[23] ;
input dout_reg1_reg_0;
wire [0:0]A;
wire [1:0]ADDRA;
wire [15:0]\BRAM_DATA_reg[15] ;
wire [7:0]\BRAM_DATA_reg[23] ;
wire CAPTURE_O_i_1_n_0;
wire CAP_DONE_O_reg;
wire [23:0]CFG_BRAM_RD_DATA0;
wire \CFG_BRAM_RD_DATA[23]_i_1_n_0 ;
wire [23:0]\CFG_DATA_O_reg[7] ;
wire [7:0]CNT_CTRL;
wire [3:0]COUNTER_EQ;
wire [0:0]E;
wire FLAG0_O010_out;
wire FLAG0_O18_out;
wire FLAG0_O_i_1_n_0;
wire FLAG1_O0;
wire FLAG1_O1__0;
wire FLAG1_O_i_1_n_0;
wire FLAG2_O0;
wire FLAG2_O1__0;
wire FLAG2_O_i_1_n_0;
wire FLAG3_O0;
wire FLAG3_O1__0;
wire FLAG3_O_i_1_n_0;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg_0 ;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg_1 ;
wire O_reg;
wire [1:0]Q;
wire [15:0]SEQUENCER_STATE_O;
wire \SEQUENCER_STATE_O[10]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[11]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[12]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[13]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[14]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[15]_i_2_n_0 ;
wire \SEQUENCER_STATE_O[7]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[8]_i_1_n_0 ;
wire \SEQUENCER_STATE_O[9]_i_1_n_0 ;
wire \SEQUENCER_STATE_O_reg[11]_0 ;
wire \SEQUENCER_STATE_O_reg[11]_1 ;
wire \SEQUENCER_STATE_O_reg[11]_2 ;
wire S_DCLK_O;
wire basic_trigger;
wire \bram_addr[6]_i_1_n_0 ;
wire \bram_addr[6]_i_3_n_0 ;
wire [6:0]bram_addr_reg;
wire bram_en;
wire bram_en_1;
wire \bram_rd_addr[6]_i_2_n_0 ;
wire [6:0]bram_rd_addr_reg;
wire bram_rd_en;
wire bram_rd_en_0;
wire bram_rd_we;
wire bram_we;
wire cap_done;
wire capture_fsm;
wire [1:0]cntcmpsel;
wire \current_state_reg[0]_0 ;
wire dout_reg1_reg;
wire dout_reg1_reg_0;
wire [18:0]douta;
wire en_adv_trigger;
wire flag0_temp;
wire flag1_temp;
wire flag2_temp;
wire flag3_temp;
wire fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_n_1;
wire fsm_mem_data_reg_r1_0_63_0_2_n_2;
wire fsm_mem_data_reg_r1_0_63_12_14_n_0;
wire fsm_mem_data_reg_r1_0_63_12_14_n_1;
wire fsm_mem_data_reg_r1_0_63_12_14_n_2;
wire fsm_mem_data_reg_r1_0_63_15_17_n_0;
wire fsm_mem_data_reg_r1_0_63_15_17_n_1;
wire fsm_mem_data_reg_r1_0_63_15_17_n_2;
wire fsm_mem_data_reg_r1_0_63_18_20_n_0;
wire fsm_mem_data_reg_r1_0_63_18_20_n_1;
wire fsm_mem_data_reg_r1_0_63_18_20_n_2;
wire fsm_mem_data_reg_r1_0_63_21_23_n_0;
wire fsm_mem_data_reg_r1_0_63_21_23_n_1;
wire fsm_mem_data_reg_r1_0_63_21_23_n_2;
wire fsm_mem_data_reg_r1_0_63_3_5_n_0;
wire fsm_mem_data_reg_r1_0_63_3_5_n_1;
wire fsm_mem_data_reg_r1_0_63_3_5_n_2;
wire fsm_mem_data_reg_r1_0_63_6_8_n_0;
wire fsm_mem_data_reg_r1_0_63_6_8_n_1;
wire fsm_mem_data_reg_r1_0_63_6_8_n_2;
wire fsm_mem_data_reg_r1_0_63_9_11_n_0;
wire fsm_mem_data_reg_r1_0_63_9_11_n_1;
wire fsm_mem_data_reg_r1_0_63_9_11_n_2;
wire fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0;
wire fsm_mem_data_reg_r1_64_127_0_2_n_0;
wire fsm_mem_data_reg_r1_64_127_0_2_n_1;
wire fsm_mem_data_reg_r1_64_127_0_2_n_2;
wire fsm_mem_data_reg_r1_64_127_12_14_n_0;
wire fsm_mem_data_reg_r1_64_127_12_14_n_1;
wire fsm_mem_data_reg_r1_64_127_12_14_n_2;
wire fsm_mem_data_reg_r1_64_127_15_17_n_0;
wire fsm_mem_data_reg_r1_64_127_15_17_n_1;
wire fsm_mem_data_reg_r1_64_127_15_17_n_2;
wire fsm_mem_data_reg_r1_64_127_18_20_n_0;
wire fsm_mem_data_reg_r1_64_127_18_20_n_1;
wire fsm_mem_data_reg_r1_64_127_18_20_n_2;
wire fsm_mem_data_reg_r1_64_127_21_23_n_0;
wire fsm_mem_data_reg_r1_64_127_21_23_n_1;
wire fsm_mem_data_reg_r1_64_127_21_23_n_2;
wire fsm_mem_data_reg_r1_64_127_3_5_n_0;
wire fsm_mem_data_reg_r1_64_127_3_5_n_1;
wire fsm_mem_data_reg_r1_64_127_3_5_n_2;
wire fsm_mem_data_reg_r1_64_127_6_8_n_0;
wire fsm_mem_data_reg_r1_64_127_6_8_n_1;
wire fsm_mem_data_reg_r1_64_127_6_8_n_2;
wire fsm_mem_data_reg_r1_64_127_9_11_n_0;
wire fsm_mem_data_reg_r1_64_127_9_11_n_1;
wire fsm_mem_data_reg_r1_64_127_9_11_n_2;
wire fsm_mem_data_reg_r2_0_63_0_2_n_0;
wire fsm_mem_data_reg_r2_0_63_0_2_n_1;
wire fsm_mem_data_reg_r2_0_63_0_2_n_2;
wire fsm_mem_data_reg_r2_0_63_12_14_n_0;
wire fsm_mem_data_reg_r2_0_63_12_14_n_1;
wire fsm_mem_data_reg_r2_0_63_12_14_n_2;
wire fsm_mem_data_reg_r2_0_63_15_17_n_0;
wire fsm_mem_data_reg_r2_0_63_15_17_n_1;
wire fsm_mem_data_reg_r2_0_63_15_17_n_2;
wire fsm_mem_data_reg_r2_0_63_18_20_n_0;
wire fsm_mem_data_reg_r2_0_63_18_20_n_1;
wire fsm_mem_data_reg_r2_0_63_18_20_n_2;
wire fsm_mem_data_reg_r2_0_63_21_23_n_0;
wire fsm_mem_data_reg_r2_0_63_21_23_n_1;
wire fsm_mem_data_reg_r2_0_63_21_23_n_2;
wire fsm_mem_data_reg_r2_0_63_3_5_n_0;
wire fsm_mem_data_reg_r2_0_63_3_5_n_1;
wire fsm_mem_data_reg_r2_0_63_3_5_n_2;
wire fsm_mem_data_reg_r2_0_63_6_8_n_0;
wire fsm_mem_data_reg_r2_0_63_6_8_n_1;
wire fsm_mem_data_reg_r2_0_63_6_8_n_2;
wire fsm_mem_data_reg_r2_0_63_9_11_n_0;
wire fsm_mem_data_reg_r2_0_63_9_11_n_1;
wire fsm_mem_data_reg_r2_0_63_9_11_n_2;
wire fsm_mem_data_reg_r2_64_127_0_2_n_0;
wire fsm_mem_data_reg_r2_64_127_0_2_n_1;
wire fsm_mem_data_reg_r2_64_127_0_2_n_2;
wire fsm_mem_data_reg_r2_64_127_12_14_n_0;
wire fsm_mem_data_reg_r2_64_127_12_14_n_1;
wire fsm_mem_data_reg_r2_64_127_12_14_n_2;
wire fsm_mem_data_reg_r2_64_127_15_17_n_0;
wire fsm_mem_data_reg_r2_64_127_15_17_n_1;
wire fsm_mem_data_reg_r2_64_127_15_17_n_2;
wire fsm_mem_data_reg_r2_64_127_18_20_n_0;
wire fsm_mem_data_reg_r2_64_127_18_20_n_1;
wire fsm_mem_data_reg_r2_64_127_18_20_n_2;
wire fsm_mem_data_reg_r2_64_127_21_23_n_0;
wire fsm_mem_data_reg_r2_64_127_21_23_n_1;
wire fsm_mem_data_reg_r2_64_127_21_23_n_2;
wire fsm_mem_data_reg_r2_64_127_3_5_n_0;
wire fsm_mem_data_reg_r2_64_127_3_5_n_1;
wire fsm_mem_data_reg_r2_64_127_3_5_n_2;
wire fsm_mem_data_reg_r2_64_127_6_8_n_0;
wire fsm_mem_data_reg_r2_64_127_6_8_n_1;
wire fsm_mem_data_reg_r2_64_127_6_8_n_2;
wire fsm_mem_data_reg_r2_64_127_9_11_n_0;
wire fsm_mem_data_reg_r2_64_127_9_11_n_1;
wire fsm_mem_data_reg_r2_64_127_9_11_n_2;
wire out;
wire [6:0]p_0_in;
wire [6:0]p_0_in__0;
wire [0:0]p_2_out;
wire [0:0]p_34_out__0;
wire toggle_rd;
wire trig_out_fsm;
wire trigger_reg_0;
wire NLW_fsm_mem_data_reg_r1_0_63_0_2_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_12_14_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_15_17_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_18_20_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_21_23_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_3_5_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_6_8_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_0_63_9_11_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_0_2_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_12_14_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_15_17_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_18_20_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_21_23_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_3_5_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_6_8_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r1_64_127_9_11_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_0_2_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_12_14_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_15_17_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_18_20_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_21_23_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_3_5_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_6_8_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_0_63_9_11_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_0_2_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_12_14_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_15_17_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_18_20_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_21_23_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_3_5_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_6_8_DOD_UNCONNECTED;
wire NLW_fsm_mem_data_reg_r2_64_127_9_11_DOD_UNCONNECTED;
LUT5 #(
.INIT(32'hC8C00800))
CAPTURE_O_i_1
(.I0(douta[18]),
.I1(dout_reg1_reg),
.I2(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
.I3(O_reg),
.I4(capture_fsm),
.O(CAPTURE_O_i_1_n_0));
LUT6 #(
.INIT(64'h1011100000000000))
CAPTURE_O_i_2
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_18_20_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_18_20_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[18]));
FDRE CAPTURE_O_reg
(.C(out),
.CE(1'b1),
.D(CAPTURE_O_i_1_n_0),
.Q(capture_fsm),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[0]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_0_2_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_0_2_n_0),
.O(CFG_BRAM_RD_DATA0[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[10]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_9_11_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_9_11_n_1),
.O(CFG_BRAM_RD_DATA0[10]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[11]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_9_11_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_9_11_n_2),
.O(CFG_BRAM_RD_DATA0[11]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[12]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_12_14_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_12_14_n_0),
.O(CFG_BRAM_RD_DATA0[12]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[13]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_12_14_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_12_14_n_1),
.O(CFG_BRAM_RD_DATA0[13]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[14]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_12_14_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_12_14_n_2),
.O(CFG_BRAM_RD_DATA0[14]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[15]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_15_17_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_15_17_n_0),
.O(CFG_BRAM_RD_DATA0[15]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[16]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_15_17_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_15_17_n_1),
.O(CFG_BRAM_RD_DATA0[16]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[17]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_15_17_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_15_17_n_2),
.O(CFG_BRAM_RD_DATA0[17]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[18]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_18_20_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_18_20_n_0),
.O(CFG_BRAM_RD_DATA0[18]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[19]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_18_20_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_18_20_n_1),
.O(CFG_BRAM_RD_DATA0[19]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[1]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_0_2_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_0_2_n_1),
.O(CFG_BRAM_RD_DATA0[1]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[20]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_18_20_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_18_20_n_2),
.O(CFG_BRAM_RD_DATA0[20]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[21]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_21_23_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_21_23_n_0),
.O(CFG_BRAM_RD_DATA0[21]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[22]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_21_23_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_21_23_n_1),
.O(CFG_BRAM_RD_DATA0[22]));
LUT2 #(
.INIT(4'h2))
\CFG_BRAM_RD_DATA[23]_i_1
(.I0(bram_rd_en_0),
.I1(bram_rd_we),
.O(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[23]_i_2
(.I0(fsm_mem_data_reg_r2_64_127_21_23_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_21_23_n_2),
.O(CFG_BRAM_RD_DATA0[23]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[2]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_0_2_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_0_2_n_2),
.O(CFG_BRAM_RD_DATA0[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[3]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_3_5_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_3_5_n_0),
.O(CFG_BRAM_RD_DATA0[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[4]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_3_5_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_3_5_n_1),
.O(CFG_BRAM_RD_DATA0[4]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[5]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_3_5_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_3_5_n_2),
.O(CFG_BRAM_RD_DATA0[5]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[6]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_6_8_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_6_8_n_0),
.O(CFG_BRAM_RD_DATA0[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[7]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_6_8_n_1),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_6_8_n_1),
.O(CFG_BRAM_RD_DATA0[7]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[8]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_6_8_n_2),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_6_8_n_2),
.O(CFG_BRAM_RD_DATA0[8]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\CFG_BRAM_RD_DATA[9]_i_1
(.I0(fsm_mem_data_reg_r2_64_127_9_11_n_0),
.I1(bram_rd_addr_reg[6]),
.I2(fsm_mem_data_reg_r2_0_63_9_11_n_0),
.O(CFG_BRAM_RD_DATA0[9]));
FDRE \CFG_BRAM_RD_DATA_reg[0]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[0]),
.Q(\CFG_DATA_O_reg[7] [0]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[10]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[10]),
.Q(\CFG_DATA_O_reg[7] [10]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[11]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[11]),
.Q(\CFG_DATA_O_reg[7] [11]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[12]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[12]),
.Q(\CFG_DATA_O_reg[7] [12]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[13]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[13]),
.Q(\CFG_DATA_O_reg[7] [13]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[14]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[14]),
.Q(\CFG_DATA_O_reg[7] [14]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[15]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[15]),
.Q(\CFG_DATA_O_reg[7] [15]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[16]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[16]),
.Q(\CFG_DATA_O_reg[7] [16]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[17]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[17]),
.Q(\CFG_DATA_O_reg[7] [17]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[18]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[18]),
.Q(\CFG_DATA_O_reg[7] [18]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[19]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[19]),
.Q(\CFG_DATA_O_reg[7] [19]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[1]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[1]),
.Q(\CFG_DATA_O_reg[7] [1]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[20]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[20]),
.Q(\CFG_DATA_O_reg[7] [20]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[21]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[21]),
.Q(\CFG_DATA_O_reg[7] [21]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[22]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[22]),
.Q(\CFG_DATA_O_reg[7] [22]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[23]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[23]),
.Q(\CFG_DATA_O_reg[7] [23]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[2]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[2]),
.Q(\CFG_DATA_O_reg[7] [2]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[3]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[3]),
.Q(\CFG_DATA_O_reg[7] [3]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[4]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[4]),
.Q(\CFG_DATA_O_reg[7] [4]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[5]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[5]),
.Q(\CFG_DATA_O_reg[7] [5]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[6]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[6]),
.Q(\CFG_DATA_O_reg[7] [6]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[7]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[7]),
.Q(\CFG_DATA_O_reg[7] [7]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[8]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[8]),
.Q(\CFG_DATA_O_reg[7] [8]),
.R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[9]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(CFG_BRAM_RD_DATA0[9]),
.Q(\CFG_DATA_O_reg[7] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'hFFFF4500))
FLAG0_O_i_1
(.I0(FLAG0_O18_out),
.I1(Q[0]),
.I2(Q[1]),
.I3(flag0_temp),
.I4(FLAG0_O010_out),
.O(FLAG0_O_i_1_n_0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG0_O_i_2
(.I0(fsm_mem_data_reg_r1_0_63_18_20_n_2),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_18_20_n_2),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG0_O18_out));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG0_O_i_3
(.I0(fsm_mem_data_reg_r1_0_63_12_14_n_2),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_12_14_n_2),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG0_O010_out));
FDRE FLAG0_O_reg
(.C(out),
.CE(1'b1),
.D(FLAG0_O_i_1_n_0),
.Q(flag0_temp),
.R(1'b0));
LUT5 #(
.INIT(32'hFFFF4500))
FLAG1_O_i_1
(.I0(FLAG1_O1__0),
.I1(Q[0]),
.I2(Q[1]),
.I3(flag1_temp),
.I4(FLAG1_O0),
.O(FLAG1_O_i_1_n_0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG1_O_i_2
(.I0(fsm_mem_data_reg_r1_0_63_21_23_n_0),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_21_23_n_0),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG1_O1__0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG1_O_i_3
(.I0(fsm_mem_data_reg_r1_0_63_15_17_n_0),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_15_17_n_0),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG1_O0));
FDRE FLAG1_O_reg
(.C(out),
.CE(1'b1),
.D(FLAG1_O_i_1_n_0),
.Q(flag1_temp),
.R(1'b0));
LUT5 #(
.INIT(32'hFFFF4500))
FLAG2_O_i_1
(.I0(FLAG2_O1__0),
.I1(Q[0]),
.I2(Q[1]),
.I3(flag2_temp),
.I4(FLAG2_O0),
.O(FLAG2_O_i_1_n_0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG2_O_i_2
(.I0(fsm_mem_data_reg_r1_0_63_21_23_n_1),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_21_23_n_1),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG2_O1__0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG2_O_i_3
(.I0(fsm_mem_data_reg_r1_0_63_15_17_n_1),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_15_17_n_1),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG2_O0));
FDRE FLAG2_O_reg
(.C(out),
.CE(1'b1),
.D(FLAG2_O_i_1_n_0),
.Q(flag2_temp),
.R(1'b0));
LUT5 #(
.INIT(32'hFFFF4500))
FLAG3_O_i_1
(.I0(FLAG3_O1__0),
.I1(Q[0]),
.I2(Q[1]),
.I3(flag3_temp),
.I4(FLAG3_O0),
.O(FLAG3_O_i_1_n_0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG3_O_i_2
(.I0(fsm_mem_data_reg_r1_0_63_21_23_n_2),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_21_23_n_2),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG3_O1__0));
LUT6 #(
.INIT(64'h000000E200000000))
FLAG3_O_i_3
(.I0(fsm_mem_data_reg_r1_0_63_15_17_n_2),
.I1(\current_state_reg[0]_0 ),
.I2(fsm_mem_data_reg_r1_64_127_15_17_n_2),
.I3(cap_done),
.I4(trig_out_fsm),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(FLAG3_O0));
FDRE FLAG3_O_reg
(.C(out),
.CE(1'b1),
.D(FLAG3_O_i_1_n_0),
.Q(flag3_temp),
.R(1'b0));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[0].U_COUNTER_i_2
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_3_5_n_2),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_3_5_n_2),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[1]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[0].U_COUNTER_i_3
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_3_5_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_3_5_n_1),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[0]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[1].U_COUNTER_i_1
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_6_8_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_6_8_n_1),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[3]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[1].U_COUNTER_i_2
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_6_8_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_6_8_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[2]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[2].U_COUNTER_i_1
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_9_11_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_9_11_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[5]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[2].U_COUNTER_i_2
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_6_8_n_2),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_6_8_n_2),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[4]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[3].U_COUNTER_i_1
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_9_11_n_2),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_9_11_n_2),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[7]));
LUT6 #(
.INIT(64'h1011100000000000))
\G_COUNTER[3].U_COUNTER_i_2
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_9_11_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_9_11_n_1),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(CNT_CTRL[6]));
LUT3 #(
.INIT(8'hE2))
\I_YESLUT6.U_SRL32_D_i_2
(.I0(basic_trigger),
.I1(en_adv_trigger),
.I2(trig_out_fsm),
.O(A));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h04))
\SEQUENCER_STATE_O[10]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_0 ),
.I1(\SEQUENCER_STATE_O_reg[11]_1 ),
.I2(\SEQUENCER_STATE_O_reg[11]_2 ),
.O(\SEQUENCER_STATE_O[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h08))
\SEQUENCER_STATE_O[11]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_0 ),
.I1(\SEQUENCER_STATE_O_reg[11]_1 ),
.I2(\SEQUENCER_STATE_O_reg[11]_2 ),
.O(\SEQUENCER_STATE_O[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h02))
\SEQUENCER_STATE_O[12]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_2 ),
.I1(\SEQUENCER_STATE_O_reg[11]_0 ),
.I2(\SEQUENCER_STATE_O_reg[11]_1 ),
.O(\SEQUENCER_STATE_O[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h20))
\SEQUENCER_STATE_O[13]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_2 ),
.I1(\SEQUENCER_STATE_O_reg[11]_1 ),
.I2(\SEQUENCER_STATE_O_reg[11]_0 ),
.O(\SEQUENCER_STATE_O[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h20))
\SEQUENCER_STATE_O[14]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_2 ),
.I1(\SEQUENCER_STATE_O_reg[11]_0 ),
.I2(\SEQUENCER_STATE_O_reg[11]_1 ),
.O(\SEQUENCER_STATE_O[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h80))
\SEQUENCER_STATE_O[15]_i_2
(.I0(\SEQUENCER_STATE_O_reg[11]_2 ),
.I1(\SEQUENCER_STATE_O_reg[11]_0 ),
.I2(\SEQUENCER_STATE_O_reg[11]_1 ),
.O(\SEQUENCER_STATE_O[15]_i_2_n_0 ));
LUT3 #(
.INIT(8'h08))
\SEQUENCER_STATE_O[7]_i_1
(.I0(\current_state_reg[0]_0 ),
.I1(dout_reg1_reg),
.I2(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
.O(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h01))
\SEQUENCER_STATE_O[8]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_0 ),
.I1(\SEQUENCER_STATE_O_reg[11]_1 ),
.I2(\SEQUENCER_STATE_O_reg[11]_2 ),
.O(\SEQUENCER_STATE_O[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h04))
\SEQUENCER_STATE_O[9]_i_1
(.I0(\SEQUENCER_STATE_O_reg[11]_1 ),
.I1(\SEQUENCER_STATE_O_reg[11]_0 ),
.I2(\SEQUENCER_STATE_O_reg[11]_2 ),
.O(\SEQUENCER_STATE_O[9]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[0]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[8]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[0]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[10]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[10]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[10]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[11]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[11]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[11]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[12]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[12]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[12]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[13]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[13]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[13]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[14]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[14]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[14]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[15]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[15]_i_2_n_0 ),
.Q(SEQUENCER_STATE_O[15]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[1]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[9]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[1]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[2]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[10]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[2]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[3]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[11]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[3]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[4]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[12]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[4]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[5]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[13]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[5]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[6]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[14]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[6]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[7]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[15]_i_2_n_0 ),
.Q(SEQUENCER_STATE_O[7]),
.R(\SEQUENCER_STATE_O[7]_i_1_n_0 ));
FDRE \SEQUENCER_STATE_O_reg[8]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[8]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[8]),
.R(dout_reg1_reg_0));
FDRE \SEQUENCER_STATE_O_reg[9]
(.C(out),
.CE(p_2_out),
.D(\SEQUENCER_STATE_O[9]_i_1_n_0 ),
.Q(SEQUENCER_STATE_O[9]),
.R(dout_reg1_reg_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT1 #(
.INIT(2'h1))
\bram_addr[0]_i_1
(.I0(bram_addr_reg[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h6))
\bram_addr[1]_i_1
(.I0(bram_addr_reg[0]),
.I1(bram_addr_reg[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\bram_addr[2]_i_1
(.I0(bram_addr_reg[0]),
.I1(bram_addr_reg[1]),
.I2(bram_addr_reg[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h7F80))
\bram_addr[3]_i_1
(.I0(bram_addr_reg[1]),
.I1(bram_addr_reg[0]),
.I2(bram_addr_reg[2]),
.I3(bram_addr_reg[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\bram_addr[4]_i_1
(.I0(bram_addr_reg[2]),
.I1(bram_addr_reg[0]),
.I2(bram_addr_reg[1]),
.I3(bram_addr_reg[3]),
.I4(bram_addr_reg[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\bram_addr[5]_i_1
(.I0(bram_addr_reg[3]),
.I1(bram_addr_reg[1]),
.I2(bram_addr_reg[0]),
.I3(bram_addr_reg[2]),
.I4(bram_addr_reg[4]),
.I5(bram_addr_reg[5]),
.O(p_0_in__0[5]));
LUT2 #(
.INIT(4'h8))
\bram_addr[6]_i_1
(.I0(bram_en_1),
.I1(bram_we),
.O(\bram_addr[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'h78))
\bram_addr[6]_i_2
(.I0(\bram_addr[6]_i_3_n_0 ),
.I1(bram_addr_reg[5]),
.I2(bram_addr_reg[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h80000000))
\bram_addr[6]_i_3
(.I0(bram_addr_reg[4]),
.I1(bram_addr_reg[2]),
.I2(bram_addr_reg[0]),
.I3(bram_addr_reg[1]),
.I4(bram_addr_reg[3]),
.O(\bram_addr[6]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[0]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[0]),
.Q(bram_addr_reg[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[1]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[1]),
.Q(bram_addr_reg[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[2]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[2]),
.Q(bram_addr_reg[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[3]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[3]),
.Q(bram_addr_reg[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[4]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[4]),
.Q(bram_addr_reg[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[5]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[5]),
.Q(bram_addr_reg[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_addr_reg[6]
(.C(S_DCLK_O),
.CE(\bram_addr[6]_i_1_n_0 ),
.D(p_0_in__0[6]),
.Q(bram_addr_reg[6]),
.R(1'b0));
FDRE bram_en_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(bram_en),
.Q(bram_en_1),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT1 #(
.INIT(2'h1))
\bram_rd_addr[0]_i_1
(.I0(bram_rd_addr_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h6))
\bram_rd_addr[1]_i_1
(.I0(bram_rd_addr_reg[0]),
.I1(bram_rd_addr_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'h78))
\bram_rd_addr[2]_i_1
(.I0(bram_rd_addr_reg[0]),
.I1(bram_rd_addr_reg[1]),
.I2(bram_rd_addr_reg[2]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h7F80))
\bram_rd_addr[3]_i_1
(.I0(bram_rd_addr_reg[1]),
.I1(bram_rd_addr_reg[0]),
.I2(bram_rd_addr_reg[2]),
.I3(bram_rd_addr_reg[3]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\bram_rd_addr[4]_i_1
(.I0(bram_rd_addr_reg[2]),
.I1(bram_rd_addr_reg[0]),
.I2(bram_rd_addr_reg[1]),
.I3(bram_rd_addr_reg[3]),
.I4(bram_rd_addr_reg[4]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\bram_rd_addr[5]_i_1
(.I0(bram_rd_addr_reg[3]),
.I1(bram_rd_addr_reg[1]),
.I2(bram_rd_addr_reg[0]),
.I3(bram_rd_addr_reg[2]),
.I4(bram_rd_addr_reg[4]),
.I5(bram_rd_addr_reg[5]),
.O(p_0_in[5]));
LUT3 #(
.INIT(8'h78))
\bram_rd_addr[6]_i_1
(.I0(\bram_rd_addr[6]_i_2_n_0 ),
.I1(bram_rd_addr_reg[5]),
.I2(bram_rd_addr_reg[6]),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h80000000))
\bram_rd_addr[6]_i_2
(.I0(bram_rd_addr_reg[4]),
.I1(bram_rd_addr_reg[2]),
.I2(bram_rd_addr_reg[0]),
.I3(bram_rd_addr_reg[1]),
.I4(bram_rd_addr_reg[3]),
.O(\bram_rd_addr[6]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[0]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[0]),
.Q(bram_rd_addr_reg[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[1]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[1]),
.Q(bram_rd_addr_reg[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[2]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[2]),
.Q(bram_rd_addr_reg[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[3]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[3]),
.Q(bram_rd_addr_reg[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[4]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[4]),
.Q(bram_rd_addr_reg[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[5]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[5]),
.Q(bram_rd_addr_reg[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bram_rd_addr_reg[6]
(.C(S_DCLK_O),
.CE(\CFG_BRAM_RD_DATA[23]_i_1_n_0 ),
.D(p_0_in[6]),
.Q(bram_rd_addr_reg[6]),
.R(1'b0));
FDRE bram_rd_en_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(bram_rd_en),
.Q(bram_rd_en_0),
.R(1'b0));
FDRE bram_rd_we_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(toggle_rd),
.Q(bram_rd_we),
.R(1'b0));
FDRE bram_we_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(E),
.Q(bram_we),
.R(1'b0));
LUT6 #(
.INIT(64'h1011100000000000))
\cntcmpsel[0]_i_1
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_12_14_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_12_14_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[12]));
LUT6 #(
.INIT(64'h1011100000000000))
\cntcmpsel[1]_i_3
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_12_14_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_12_14_n_1),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[13]));
FDRE \cntcmpsel_reg[0]
(.C(out),
.CE(p_2_out),
.D(douta[12]),
.Q(cntcmpsel[0]),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
FDRE \cntcmpsel_reg[1]
(.C(out),
.CE(p_2_out),
.D(douta[13]),
.Q(cntcmpsel[1]),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
LUT6 #(
.INIT(64'h1011100000000000))
\current_state[0]_i_1__47
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_0_2_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_0_2_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[0]));
LUT6 #(
.INIT(64'h1011100000000000))
\current_state[1]_i_1__47
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_0_2_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_0_2_n_1),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[1]));
LUT6 #(
.INIT(64'h1011100000000000))
\current_state[2]_i_1__47
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_0_2_n_2),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_0_2_n_2),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[2]));
LUT6 #(
.INIT(64'h1011100000000000))
\current_state[3]_i_1__47
(.I0(trig_out_fsm),
.I1(cap_done),
.I2(fsm_mem_data_reg_r1_64_127_3_5_n_0),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_0_63_3_5_n_0),
.I5(\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.O(douta[3]));
FDRE \current_state_reg[0]
(.C(out),
.CE(p_2_out),
.D(douta[0]),
.Q(\SEQUENCER_STATE_O_reg[11]_0 ),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
FDRE \current_state_reg[1]
(.C(out),
.CE(p_2_out),
.D(douta[1]),
.Q(\SEQUENCER_STATE_O_reg[11]_1 ),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
FDRE \current_state_reg[2]
(.C(out),
.CE(p_2_out),
.D(douta[2]),
.Q(\SEQUENCER_STATE_O_reg[11]_2 ),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
FDRE \current_state_reg[3]
(.C(out),
.CE(p_2_out),
.D(douta[3]),
.Q(\current_state_reg[0]_0 ),
.R(\I_YESLUT6.I_YES_OREG.O_reg_reg_1 ));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_0_2
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [0]),
.DIB(\BRAM_DATA_reg[15] [1]),
.DIC(\BRAM_DATA_reg[15] [2]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_0_2_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_0_2_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_0_2_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_0_2_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
LUT3 #(
.INIT(8'h08))
fsm_mem_data_reg_r1_0_63_0_2_i_1
(.I0(bram_we),
.I1(bram_en_1),
.I2(bram_addr_reg[6]),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_12_14
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [12]),
.DIB(\BRAM_DATA_reg[15] [13]),
.DIC(\BRAM_DATA_reg[15] [14]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_12_14_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_12_14_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_12_14_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_12_14_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_15_17
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [15]),
.DIB(\BRAM_DATA_reg[23] [0]),
.DIC(\BRAM_DATA_reg[23] [1]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_15_17_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_15_17_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_15_17_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_15_17_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_18_20
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [2]),
.DIB(\BRAM_DATA_reg[23] [3]),
.DIC(\BRAM_DATA_reg[23] [4]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_18_20_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_18_20_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_18_20_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_18_20_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_21_23
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [5]),
.DIB(\BRAM_DATA_reg[23] [6]),
.DIC(\BRAM_DATA_reg[23] [7]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_21_23_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_21_23_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_21_23_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_21_23_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_3_5
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [3]),
.DIB(\BRAM_DATA_reg[15] [4]),
.DIC(\BRAM_DATA_reg[15] [5]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_3_5_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_3_5_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_3_5_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_3_5_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_6_8
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [6]),
.DIB(\BRAM_DATA_reg[15] [7]),
.DIC(\BRAM_DATA_reg[15] [8]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_6_8_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_6_8_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_6_8_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_6_8_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_0_63_9_11
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [9]),
.DIB(\BRAM_DATA_reg[15] [10]),
.DIC(\BRAM_DATA_reg[15] [11]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_0_63_9_11_n_0),
.DOB(fsm_mem_data_reg_r1_0_63_9_11_n_1),
.DOC(fsm_mem_data_reg_r1_0_63_9_11_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_0_63_9_11_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_0_2
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [0]),
.DIB(\BRAM_DATA_reg[15] [1]),
.DIC(\BRAM_DATA_reg[15] [2]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_0_2_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_0_2_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_0_2_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_0_2_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
LUT3 #(
.INIT(8'h80))
fsm_mem_data_reg_r1_64_127_0_2_i_1
(.I0(bram_we),
.I1(bram_en_1),
.I2(bram_addr_reg[6]),
.O(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_12_14
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [12]),
.DIB(\BRAM_DATA_reg[15] [13]),
.DIC(\BRAM_DATA_reg[15] [14]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_12_14_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_12_14_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_12_14_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_12_14_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_15_17
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [15]),
.DIB(\BRAM_DATA_reg[23] [0]),
.DIC(\BRAM_DATA_reg[23] [1]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_15_17_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_15_17_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_15_17_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_15_17_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_18_20
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [2]),
.DIB(\BRAM_DATA_reg[23] [3]),
.DIC(\BRAM_DATA_reg[23] [4]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_18_20_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_18_20_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_18_20_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_18_20_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_21_23
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [5]),
.DIB(\BRAM_DATA_reg[23] [6]),
.DIC(\BRAM_DATA_reg[23] [7]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_21_23_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_21_23_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_21_23_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_21_23_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_3_5
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [3]),
.DIB(\BRAM_DATA_reg[15] [4]),
.DIC(\BRAM_DATA_reg[15] [5]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_3_5_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_3_5_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_3_5_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_3_5_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_6_8
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [6]),
.DIB(\BRAM_DATA_reg[15] [7]),
.DIC(\BRAM_DATA_reg[15] [8]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_6_8_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_6_8_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_6_8_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_6_8_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r1_64_127_9_11
(.ADDRA({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRB({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRC({\SEQUENCER_STATE_O_reg[11]_2 ,\SEQUENCER_STATE_O_reg[11]_1 ,\SEQUENCER_STATE_O_reg[11]_0 ,ADDRA,p_34_out__0}),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [9]),
.DIB(\BRAM_DATA_reg[15] [10]),
.DIC(\BRAM_DATA_reg[15] [11]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r1_64_127_9_11_n_0),
.DOB(fsm_mem_data_reg_r1_64_127_9_11_n_1),
.DOC(fsm_mem_data_reg_r1_64_127_9_11_n_2),
.DOD(NLW_fsm_mem_data_reg_r1_64_127_9_11_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_0_2
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [0]),
.DIB(\BRAM_DATA_reg[15] [1]),
.DIC(\BRAM_DATA_reg[15] [2]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_0_2_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_0_2_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_0_2_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_0_2_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_12_14
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [12]),
.DIB(\BRAM_DATA_reg[15] [13]),
.DIC(\BRAM_DATA_reg[15] [14]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_12_14_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_12_14_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_12_14_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_12_14_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_15_17
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [15]),
.DIB(\BRAM_DATA_reg[23] [0]),
.DIC(\BRAM_DATA_reg[23] [1]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_15_17_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_15_17_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_15_17_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_15_17_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_18_20
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [2]),
.DIB(\BRAM_DATA_reg[23] [3]),
.DIC(\BRAM_DATA_reg[23] [4]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_18_20_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_18_20_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_18_20_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_18_20_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_21_23
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [5]),
.DIB(\BRAM_DATA_reg[23] [6]),
.DIC(\BRAM_DATA_reg[23] [7]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_21_23_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_21_23_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_21_23_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_21_23_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_3_5
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [3]),
.DIB(\BRAM_DATA_reg[15] [4]),
.DIC(\BRAM_DATA_reg[15] [5]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_3_5_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_3_5_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_3_5_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_3_5_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_6_8
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [6]),
.DIB(\BRAM_DATA_reg[15] [7]),
.DIC(\BRAM_DATA_reg[15] [8]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_6_8_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_6_8_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_6_8_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_6_8_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_0_63_9_11
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [9]),
.DIB(\BRAM_DATA_reg[15] [10]),
.DIC(\BRAM_DATA_reg[15] [11]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_0_63_9_11_n_0),
.DOB(fsm_mem_data_reg_r2_0_63_9_11_n_1),
.DOC(fsm_mem_data_reg_r2_0_63_9_11_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_0_63_9_11_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_0_2
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [0]),
.DIB(\BRAM_DATA_reg[15] [1]),
.DIC(\BRAM_DATA_reg[15] [2]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_0_2_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_0_2_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_0_2_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_0_2_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_12_14
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [12]),
.DIB(\BRAM_DATA_reg[15] [13]),
.DIC(\BRAM_DATA_reg[15] [14]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_12_14_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_12_14_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_12_14_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_12_14_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_15_17
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [15]),
.DIB(\BRAM_DATA_reg[23] [0]),
.DIC(\BRAM_DATA_reg[23] [1]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_15_17_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_15_17_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_15_17_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_15_17_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_18_20
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [2]),
.DIB(\BRAM_DATA_reg[23] [3]),
.DIC(\BRAM_DATA_reg[23] [4]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_18_20_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_18_20_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_18_20_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_18_20_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_21_23
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[23] [5]),
.DIB(\BRAM_DATA_reg[23] [6]),
.DIC(\BRAM_DATA_reg[23] [7]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_21_23_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_21_23_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_21_23_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_21_23_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_3_5
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [3]),
.DIB(\BRAM_DATA_reg[15] [4]),
.DIC(\BRAM_DATA_reg[15] [5]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_3_5_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_3_5_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_3_5_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_3_5_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_6_8
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [6]),
.DIB(\BRAM_DATA_reg[15] [7]),
.DIC(\BRAM_DATA_reg[15] [8]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_6_8_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_6_8_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_6_8_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_6_8_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM64M fsm_mem_data_reg_r2_64_127_9_11
(.ADDRA(bram_rd_addr_reg[5:0]),
.ADDRB(bram_rd_addr_reg[5:0]),
.ADDRC(bram_rd_addr_reg[5:0]),
.ADDRD(bram_addr_reg[5:0]),
.DIA(\BRAM_DATA_reg[15] [9]),
.DIB(\BRAM_DATA_reg[15] [10]),
.DIC(\BRAM_DATA_reg[15] [11]),
.DID(1'b0),
.DOA(fsm_mem_data_reg_r2_64_127_9_11_n_0),
.DOB(fsm_mem_data_reg_r2_64_127_9_11_n_1),
.DOC(fsm_mem_data_reg_r2_64_127_9_11_n_2),
.DOD(NLW_fsm_mem_data_reg_r2_64_127_9_11_DOD_UNCONNECTED),
.WCLK(S_DCLK_O),
.WE(fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
p_34_out
(.I0(COUNTER_EQ[3]),
.I1(COUNTER_EQ[1]),
.I2(cntcmpsel[0]),
.I3(COUNTER_EQ[2]),
.I4(cntcmpsel[1]),
.I5(COUNTER_EQ[0]),
.O(p_34_out__0));
LUT5 #(
.INIT(32'hBBBFFFBF))
trigger_i_2
(.I0(\I_YESLUT6.I_YES_OREG.O_reg_reg_0 ),
.I1(O_reg),
.I2(fsm_mem_data_reg_r1_0_63_18_20_n_1),
.I3(\current_state_reg[0]_0 ),
.I4(fsm_mem_data_reg_r1_64_127_18_20_n_1),
.O(trigger_reg_0));
FDRE trigger_reg
(.C(out),
.CE(1'b1),
.D(CAP_DONE_O_reg),
.Q(trig_out_fsm),
.R(1'b0));
endmodule | 8 |
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