Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
2,142 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_addrgen
(u_wcnt_lcmp_q,
\iscnt_reg[0] ,
wcnt_hcmp,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
\iscnt_reg[0]_0 ,
\xsdb_reg_reg[14] ,
DOUT_O,
u_wcnt_lcmp_q_0,
SRL_Q_O,
u_wcnt_hcmp_q,
E,
S_DCLK_O,
A,
scnt_cmp_temp,
out,
wcnt_lcmp_temp,
wcnt_hcmp_temp,
Q,
D,
\reset_out_reg[0] );
output [0:0]u_wcnt_lcmp_q;
output [0:0]\iscnt_reg[0] ;
output wcnt_hcmp;
output [14:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
output \iscnt_reg[0]_0 ;
output [14:0]\xsdb_reg_reg[14] ;
output DOUT_O;
output u_wcnt_lcmp_q_0;
output SRL_Q_O;
output u_wcnt_hcmp_q;
input [0:0]E;
input S_DCLK_O;
input [3:0]A;
input scnt_cmp_temp;
input out;
input wcnt_lcmp_temp;
input wcnt_hcmp_temp;
input [0:0]Q;
input [0:0]D;
input [0:0]\reset_out_reg[0] ;
wire [3:0]A;
wire [0:0]D;
(* async_reg = "true" *) wire [14:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
(* async_reg = "true" *) wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
wire DOUT_O;
wire [0:0]E;
wire [0:0]Q;
wire SRL_Q_O;
wire S_DCLK_O;
wire [14:0]cap_addr_next;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [16:16]cfg_data_vec;
wire cmp_reset;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[10] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[11] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[12] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[13] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[14] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[15] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[1] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[2] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[3] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[4] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[5] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[6] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[7] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[8] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[9] ;
(* DONT_TOUCH *) (* async_reg = "true" *) wire [14:0]icap_addr;
(* DONT_TOUCH *) (* async_reg = "true" *) wire icap_wr_en;
wire [0:0]\iscnt_reg[0] ;
wire \iscnt_reg[0]_0 ;
wire out;
wire [0:0]\reset_out_reg[0] ;
wire scnt_ce;
wire scnt_cmp_temp;
wire u_wcnt_hcmp_q;
wire [0:0]u_wcnt_lcmp_q;
wire u_wcnt_lcmp_q_0;
wire [14:0]wcnt;
wire wcnt_hcmp;
wire wcnt_hcmp_temp;
wire wcnt_lcmp_temp;
wire [14:0]\xsdb_reg_reg[14] ;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE CAP_WR_EN_O_reg
(.C(out),
.CE(1'b1),
.D(icap_wr_en),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
.R(Q));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6 U_CMPRESET
(.A({u_wcnt_lcmp_q,A}),
.E(E),
.S_DCLK_O(S_DCLK_O),
.cfg_data_0(cfg_data_0),
.cfg_data_1(cfg_data_1),
.cmp_reset(cmp_reset),
.u_scnt_cmp_q(\iscnt_reg[0] ));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[0]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[0]),
.Q(\xsdb_reg_reg[14] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[10]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[10]),
.Q(\xsdb_reg_reg[14] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[11]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[11]),
.Q(\xsdb_reg_reg[14] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[12]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[12]),
.Q(\xsdb_reg_reg[14] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[13]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[13]),
.Q(\xsdb_reg_reg[14] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[14]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[14]),
.Q(\xsdb_reg_reg[14] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[1]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[1]),
.Q(\xsdb_reg_reg[14] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[2]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[2]),
.Q(\xsdb_reg_reg[14] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[3]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[3]),
.Q(\xsdb_reg_reg[14] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[4]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[4]),
.Q(\xsdb_reg_reg[14] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[5]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[5]),
.Q(\xsdb_reg_reg[14] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[6]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[6]),
.Q(\xsdb_reg_reg[14] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[7]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[7]),
.Q(\xsdb_reg_reg[14] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[8]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[8]),
.Q(\xsdb_reg_reg[14] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[9]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[9]),
.Q(\xsdb_reg_reg[14] [9]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[0]
(.C(out),
.CE(1'b1),
.D(icap_addr[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[10]
(.C(out),
.CE(1'b1),
.D(icap_addr[10]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [10]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[11]
(.C(out),
.CE(1'b1),
.D(icap_addr[11]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [11]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[12]
(.C(out),
.CE(1'b1),
.D(icap_addr[12]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [12]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[13]
(.C(out),
.CE(1'b1),
.D(icap_addr[13]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [13]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[14]
(.C(out),
.CE(1'b1),
.D(icap_addr[14]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [14]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[1]
(.C(out),
.CE(1'b1),
.D(icap_addr[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[2]
(.C(out),
.CE(1'b1),
.D(icap_addr[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[3]
(.C(out),
.CE(1'b1),
.D(icap_addr[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[4]
(.C(out),
.CE(1'b1),
.D(icap_addr[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[5]
(.C(out),
.CE(1'b1),
.D(icap_addr[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[6]
(.C(out),
.CE(1'b1),
.D(icap_addr[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[7]
(.C(out),
.CE(1'b1),
.D(icap_addr[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[8]
(.C(out),
.CE(1'b1),
.D(icap_addr[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[9]
(.C(out),
.CE(1'b1),
.D(icap_addr[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[0]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[0]),
.Q(icap_addr[0]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[10]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[10]),
.Q(icap_addr[10]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[11]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[11]),
.Q(icap_addr[11]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[12]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[12]),
.Q(icap_addr[12]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[13]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[13]),
.Q(icap_addr[13]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[14]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[14]),
.Q(icap_addr[14]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[1]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[1]),
.Q(icap_addr[1]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[2]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[2]),
.Q(icap_addr[2]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[3]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[3]),
.Q(icap_addr[3]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[4]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[4]),
.Q(icap_addr[4]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[5]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[5]),
.Q(icap_addr[5]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[6]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[6]),
.Q(icap_addr[6]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[7]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[7]),
.Q(icap_addr[7]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[8]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[8]),
.Q(icap_addr[8]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[9]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[9]),
.Q(icap_addr[9]),
.R(Q));
FDRE \i_o_to_64k.cfg_data_vec_reg[10]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[9] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[10] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[11]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[10] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[11] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[12]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[11] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[12] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[13]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[12] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[13] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[14]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[13] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[14] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[15]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[14] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[15] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[16]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[15] ),
.Q(cfg_data_vec),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[1]
(.C(S_DCLK_O),
.CE(E),
.D(D),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[1] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[2]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[1] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[2] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[3]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[2] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[3] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[4]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[3] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[4] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[5]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[4] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[5] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[6]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[5] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[6] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[7]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[6] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[7] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[8]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[7] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[8] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[9]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[8] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[9] ),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/i_o_to_64k.u_selx " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\i_o_to_64k.u_selx
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_vec),
.Q(cfg_data_0));
(* ASYNC_REG *)
FDRE icap_wr_en_reg
(.C(out),
.CE(1'b1),
.D(scnt_ce),
.Q(icap_wr_en),
.R(Q));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_sample_counter u_cap_sample_counter
(.A({u_wcnt_lcmp_q,A}),
.D(cap_addr_next),
.DOUT_O(DOUT_O),
.E(E),
.Q({\i_o_to_64k.cfg_data_vec_reg_n_0_[15] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[14] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[13] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[12] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[11] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[10] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[9] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[8] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[7] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[6] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[5] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[4] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[3] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[2] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[1] }),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.cfg_data_1(cfg_data_1),
.cmp_reset(cmp_reset),
.\iscnt_reg[0]_0 (\iscnt_reg[0] ),
.\iscnt_reg[0]_1 (\iscnt_reg[0]_0 ),
.\iwcnt_reg[14] (wcnt),
.out(out),
.scnt_ce(scnt_ce),
.scnt_cmp_temp(scnt_cmp_temp));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_window_counter u_cap_window_counter
(.A(A),
.D(wcnt),
.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (SRL_Q_O),
.Q(Q),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.cmp_reset(cmp_reset),
.out(out),
.u_wcnt_hcmp_q_0(u_wcnt_hcmp_q),
.u_wcnt_lcmp_q_0(u_wcnt_lcmp_q),
.u_wcnt_lcmp_q_1(u_wcnt_lcmp_q_0),
.wcnt_hcmp(wcnt_hcmp),
.wcnt_hcmp_temp(wcnt_hcmp_temp),
.wcnt_lcmp_temp(wcnt_lcmp_temp));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_addrgen
(u_wcnt_lcmp_q,
\iscnt_reg[0] ,
wcnt_hcmp,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
\iscnt_reg[0]_0 ,
\xsdb_reg_reg[14] ,
DOUT_O,
u_wcnt_lcmp_q_0,
SRL_Q_O,
u_wcnt_hcmp_q,
E,
S_DCLK_O,
A,
scnt_cmp_temp,
out,
wcnt_lcmp_temp,
wcnt_hcmp_temp,
Q,
D,
\reset_out_reg[0] ); |
output [0:0]u_wcnt_lcmp_q;
output [0:0]\iscnt_reg[0] ;
output wcnt_hcmp;
output [14:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
output \iscnt_reg[0]_0 ;
output [14:0]\xsdb_reg_reg[14] ;
output DOUT_O;
output u_wcnt_lcmp_q_0;
output SRL_Q_O;
output u_wcnt_hcmp_q;
input [0:0]E;
input S_DCLK_O;
input [3:0]A;
input scnt_cmp_temp;
input out;
input wcnt_lcmp_temp;
input wcnt_hcmp_temp;
input [0:0]Q;
input [0:0]D;
input [0:0]\reset_out_reg[0] ;
wire [3:0]A;
wire [0:0]D;
(* async_reg = "true" *) wire [14:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
(* async_reg = "true" *) wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
wire DOUT_O;
wire [0:0]E;
wire [0:0]Q;
wire SRL_Q_O;
wire S_DCLK_O;
wire [14:0]cap_addr_next;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [16:16]cfg_data_vec;
wire cmp_reset;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[10] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[11] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[12] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[13] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[14] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[15] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[1] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[2] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[3] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[4] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[5] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[6] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[7] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[8] ;
wire \i_o_to_64k.cfg_data_vec_reg_n_0_[9] ;
(* DONT_TOUCH *) (* async_reg = "true" *) wire [14:0]icap_addr;
(* DONT_TOUCH *) (* async_reg = "true" *) wire icap_wr_en;
wire [0:0]\iscnt_reg[0] ;
wire \iscnt_reg[0]_0 ;
wire out;
wire [0:0]\reset_out_reg[0] ;
wire scnt_ce;
wire scnt_cmp_temp;
wire u_wcnt_hcmp_q;
wire [0:0]u_wcnt_lcmp_q;
wire u_wcnt_lcmp_q_0;
wire [14:0]wcnt;
wire wcnt_hcmp;
wire wcnt_hcmp_temp;
wire wcnt_lcmp_temp;
wire [14:0]\xsdb_reg_reg[14] ;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE CAP_WR_EN_O_reg
(.C(out),
.CE(1'b1),
.D(icap_wr_en),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
.R(Q));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6 U_CMPRESET
(.A({u_wcnt_lcmp_q,A}),
.E(E),
.S_DCLK_O(S_DCLK_O),
.cfg_data_0(cfg_data_0),
.cfg_data_1(cfg_data_1),
.cmp_reset(cmp_reset),
.u_scnt_cmp_q(\iscnt_reg[0] ));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[0]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[0]),
.Q(\xsdb_reg_reg[14] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[10]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[10]),
.Q(\xsdb_reg_reg[14] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[11]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[11]),
.Q(\xsdb_reg_reg[14] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[12]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[12]),
.Q(\xsdb_reg_reg[14] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[13]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[13]),
.Q(\xsdb_reg_reg[14] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[14]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[14]),
.Q(\xsdb_reg_reg[14] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[1]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[1]),
.Q(\xsdb_reg_reg[14] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[2]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[2]),
.Q(\xsdb_reg_reg[14] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[3]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[3]),
.Q(\xsdb_reg_reg[14] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[4]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[4]),
.Q(\xsdb_reg_reg[14] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[5]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[5]),
.Q(\xsdb_reg_reg[14] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[6]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[6]),
.Q(\xsdb_reg_reg[14] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[7]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[7]),
.Q(\xsdb_reg_reg[14] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[8]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[8]),
.Q(\xsdb_reg_reg[14] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\captured_samples_reg[9]
(.C(out),
.CE(\reset_out_reg[0] ),
.D(wcnt[9]),
.Q(\xsdb_reg_reg[14] [9]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[0]
(.C(out),
.CE(1'b1),
.D(icap_addr[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[10]
(.C(out),
.CE(1'b1),
.D(icap_addr[10]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [10]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[11]
(.C(out),
.CE(1'b1),
.D(icap_addr[11]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [11]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[12]
(.C(out),
.CE(1'b1),
.D(icap_addr[12]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [12]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[13]
(.C(out),
.CE(1'b1),
.D(icap_addr[13]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [13]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[14]
(.C(out),
.CE(1'b1),
.D(icap_addr[14]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [14]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[1]
(.C(out),
.CE(1'b1),
.D(icap_addr[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[2]
(.C(out),
.CE(1'b1),
.D(icap_addr[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[3]
(.C(out),
.CE(1'b1),
.D(icap_addr[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[4]
(.C(out),
.CE(1'b1),
.D(icap_addr[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[5]
(.C(out),
.CE(1'b1),
.D(icap_addr[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[6]
(.C(out),
.CE(1'b1),
.D(icap_addr[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[7]
(.C(out),
.CE(1'b1),
.D(icap_addr[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[8]
(.C(out),
.CE(1'b1),
.D(icap_addr[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.R(Q));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \i_intcap.CAP_ADDR_O_reg[9]
(.C(out),
.CE(1'b1),
.D(icap_addr[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[0]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[0]),
.Q(icap_addr[0]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[10]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[10]),
.Q(icap_addr[10]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[11]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[11]),
.Q(icap_addr[11]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[12]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[12]),
.Q(icap_addr[12]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[13]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[13]),
.Q(icap_addr[13]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[14]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[14]),
.Q(icap_addr[14]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[1]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[1]),
.Q(icap_addr[1]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[2]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[2]),
.Q(icap_addr[2]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[3]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[3]),
.Q(icap_addr[3]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[4]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[4]),
.Q(icap_addr[4]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[5]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[5]),
.Q(icap_addr[5]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[6]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[6]),
.Q(icap_addr[6]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[7]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[7]),
.Q(icap_addr[7]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[8]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[8]),
.Q(icap_addr[8]),
.R(Q));
(* ASYNC_REG *)
FDRE \i_intcap.icap_addr_reg[9]
(.C(out),
.CE(1'b1),
.D(cap_addr_next[9]),
.Q(icap_addr[9]),
.R(Q));
FDRE \i_o_to_64k.cfg_data_vec_reg[10]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[9] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[10] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[11]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[10] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[11] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[12]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[11] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[12] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[13]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[12] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[13] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[14]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[13] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[14] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[15]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[14] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[15] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[16]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[15] ),
.Q(cfg_data_vec),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[1]
(.C(S_DCLK_O),
.CE(E),
.D(D),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[1] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[2]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[1] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[2] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[3]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[2] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[3] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[4]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[3] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[4] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[5]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[4] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[5] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[6]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[5] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[6] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[7]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[6] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[7] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[8]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[7] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[8] ),
.R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[9]
(.C(S_DCLK_O),
.CE(E),
.D(\i_o_to_64k.cfg_data_vec_reg_n_0_[8] ),
.Q(\i_o_to_64k.cfg_data_vec_reg_n_0_[9] ),
.R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/i_o_to_64k.u_selx " *)
SRL16E #(
.INIT(16'h0000),
.IS_CLK_INVERTED(1'b0))
\i_o_to_64k.u_selx
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(E),
.CLK(S_DCLK_O),
.D(cfg_data_vec),
.Q(cfg_data_0));
(* ASYNC_REG *)
FDRE icap_wr_en_reg
(.C(out),
.CE(1'b1),
.D(scnt_ce),
.Q(icap_wr_en),
.R(Q));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_sample_counter u_cap_sample_counter
(.A({u_wcnt_lcmp_q,A}),
.D(cap_addr_next),
.DOUT_O(DOUT_O),
.E(E),
.Q({\i_o_to_64k.cfg_data_vec_reg_n_0_[15] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[14] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[13] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[12] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[11] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[10] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[9] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[8] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[7] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[6] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[5] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[4] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[3] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[2] ,\i_o_to_64k.cfg_data_vec_reg_n_0_[1] }),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.cfg_data_1(cfg_data_1),
.cmp_reset(cmp_reset),
.\iscnt_reg[0]_0 (\iscnt_reg[0] ),
.\iscnt_reg[0]_1 (\iscnt_reg[0]_0 ),
.\iwcnt_reg[14] (wcnt),
.out(out),
.scnt_ce(scnt_ce),
.scnt_cmp_temp(scnt_cmp_temp));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_window_counter u_cap_window_counter
(.A(A),
.D(wcnt),
.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (SRL_Q_O),
.Q(Q),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.cmp_reset(cmp_reset),
.out(out),
.u_wcnt_hcmp_q_0(u_wcnt_hcmp_q),
.u_wcnt_lcmp_q_0(u_wcnt_lcmp_q),
.u_wcnt_lcmp_q_1(u_wcnt_lcmp_q_0),
.wcnt_hcmp(wcnt_hcmp),
.wcnt_hcmp_temp(wcnt_hcmp_temp),
.wcnt_lcmp_temp(wcnt_lcmp_temp));
endmodule | 8 |
2,143 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_ctrl_legacy
(O_reg,
\xsdb_reg_reg[0] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
D,
TRIGGERED_SL_I,
scnt_reset,
cap_done,
\current_state_reg[0] ,
\current_state_reg[0]_0 ,
p_2_out,
trigger_reg,
\xsdb_reg_reg[14] ,
DOUT_O,
u_wcnt_lcmp_q,
u_wcnt_hcmp_q,
E,
capture_ctrl_config_serial_output,
A,
S_DCLK_O,
scnt_cmp_temp,
out,
wcnt_lcmp_temp,
wcnt_hcmp_temp,
capture_qual_ctrl_1,
capture_strg_qual,
capture_fsm,
Q,
dout_reg1_reg,
trig_out_fsm,
en_adv_trigger,
basic_trigger,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
\reset_out_reg[0] );
output O_reg;
output \xsdb_reg_reg[0] ;
output [14:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
output [0:0]D;
output TRIGGERED_SL_I;
output scnt_reset;
output cap_done;
output \current_state_reg[0] ;
output \current_state_reg[0]_0 ;
output [0:0]p_2_out;
output trigger_reg;
output [14:0]\xsdb_reg_reg[14] ;
output DOUT_O;
output u_wcnt_lcmp_q;
output u_wcnt_hcmp_q;
input [0:0]E;
input capture_ctrl_config_serial_output;
input [0:0]A;
input S_DCLK_O;
input scnt_cmp_temp;
input out;
input wcnt_lcmp_temp;
input wcnt_hcmp_temp;
input [1:0]capture_qual_ctrl_1;
input capture_strg_qual;
input capture_fsm;
input [1:0]Q;
input dout_reg1_reg;
input trig_out_fsm;
input en_adv_trigger;
input basic_trigger;
input \I_YESLUT6.I_YES_OREG.O_reg_reg ;
input [0:0]\reset_out_reg[0] ;
wire [0:0]A;
wire [0:0]D;
wire [14:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
wire DOUT_O;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire O_reg;
wire [1:0]Q;
wire S_DCLK_O;
wire TRIGGERED_SL_I;
wire U_CDONE_n_1;
wire basic_trigger;
wire cap_done;
wire capture_ctrl_config_serial_output;
wire capture_fsm;
wire capture_i;
wire [1:0]capture_qual_ctrl_1;
wire capture_strg_qual;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire \current_state_reg[0] ;
wire \current_state_reg[0]_0 ;
wire dout_reg1_reg;
wire en_adv_trigger;
wire itrigger_in;
(* async_reg = "true" *) wire itrigger_out;
(* async_reg = "true" *) wire n_0_0;
wire out;
wire [0:0]p_2_out;
wire [0:0]\reset_out_reg[0] ;
wire scnt_cmp;
wire scnt_cmp_temp;
wire scnt_reset;
wire trig_out_fsm;
wire trigger_reg;
wire u_wcnt_hcmp_q;
wire u_wcnt_lcmp_q;
wire wcnt_hcmp;
wire wcnt_hcmp_temp;
wire wcnt_lcmp;
wire wcnt_lcmp_temp;
wire \xsdb_reg_reg[0] ;
wire [14:0]\xsdb_reg_reg[14] ;
LUT4 #(
.INIT(16'hFDAD))
A0
(.I0(capture_qual_ctrl_1[0]),
.I1(capture_strg_qual),
.I2(capture_qual_ctrl_1[1]),
.I3(capture_fsm),
.O(capture_i));
FDRE #(
.INIT(1'b0))
CAP_DONE_O_reg
(.C(out),
.CE(1'b1),
.D(U_CDONE_n_1),
.Q(cap_done),
.R(1'b0));
FDRE CAP_TRIGGER_O_reg
(.C(out),
.CE(1'b1),
.D(n_0_0),
.Q(TRIGGERED_SL_I),
.R(Q[0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6__parameterized0 U_CDONE
(.A({wcnt_lcmp,capture_i,A,O_reg,\xsdb_reg_reg[0] }),
.CAP_DONE_O_reg(U_CDONE_n_1),
.D(D),
.E(E),
.Q(Q),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.cap_done(cap_done),
.out(out),
.wcnt_hcmp(wcnt_hcmp));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7 U_NS0
(.A({scnt_cmp,capture_i,A,O_reg}),
.D(cfg_data_1),
.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg_0 (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.Q(Q[0]),
.S_DCLK_O(S_DCLK_O),
.cap_done(cap_done),
.cfg_data_0(cfg_data_0),
.dout_reg1_reg(dout_reg1_reg),
.out(out),
.p_2_out(p_2_out),
.trig_out_fsm(trig_out_fsm),
.trigger_reg(trigger_reg),
.u_wcnt_lcmp_q(wcnt_lcmp),
.wcnt_hcmp(wcnt_hcmp),
.\xsdb_reg_reg[0] (\xsdb_reg_reg[0] ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7_183 U_NS1
(.A({scnt_cmp,capture_i,A}),
.E(E),
.Q(Q[0]),
.S_DCLK_O(S_DCLK_O),
.basic_trigger(basic_trigger),
.capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
.cfg_data_0(cfg_data_0),
.\current_state_reg[0] (\current_state_reg[0] ),
.\current_state_reg[0]_0 (\current_state_reg[0]_0 ),
.dout_reg1_reg(dout_reg1_reg),
.en_adv_trigger(en_adv_trigger),
.itrigger_in(itrigger_in),
.out(out),
.trig_out_fsm(trig_out_fsm),
.u_wcnt_lcmp_q({wcnt_lcmp,\xsdb_reg_reg[0] }),
.wcnt_hcmp(wcnt_hcmp),
.\xsdb_reg_reg[1] (O_reg));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(itrigger_out),
.O(n_0_0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
itrigger_out_reg
(.C(out),
.CE(1'b1),
.D(itrigger_in),
.Q(itrigger_out),
.R(Q[0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_addrgen u_cap_addrgen
(.A({capture_i,A,O_reg,\xsdb_reg_reg[0] }),
.D(cfg_data_1),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
.DOUT_O(DOUT_O),
.E(E),
.Q(Q[0]),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.\iscnt_reg[0] (scnt_cmp),
.\iscnt_reg[0]_0 (scnt_reset),
.out(out),
.\reset_out_reg[0] (\reset_out_reg[0] ),
.scnt_cmp_temp(scnt_cmp_temp),
.u_wcnt_hcmp_q(u_wcnt_hcmp_q),
.u_wcnt_lcmp_q(wcnt_lcmp),
.u_wcnt_lcmp_q_0(u_wcnt_lcmp_q),
.wcnt_hcmp(wcnt_hcmp),
.wcnt_hcmp_temp(wcnt_hcmp_temp),
.wcnt_lcmp_temp(wcnt_lcmp_temp),
.\xsdb_reg_reg[14] (\xsdb_reg_reg[14] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_ctrl_legacy
(O_reg,
\xsdb_reg_reg[0] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
D,
TRIGGERED_SL_I,
scnt_reset,
cap_done,
\current_state_reg[0] ,
\current_state_reg[0]_0 ,
p_2_out,
trigger_reg,
\xsdb_reg_reg[14] ,
DOUT_O,
u_wcnt_lcmp_q,
u_wcnt_hcmp_q,
E,
capture_ctrl_config_serial_output,
A,
S_DCLK_O,
scnt_cmp_temp,
out,
wcnt_lcmp_temp,
wcnt_hcmp_temp,
capture_qual_ctrl_1,
capture_strg_qual,
capture_fsm,
Q,
dout_reg1_reg,
trig_out_fsm,
en_adv_trigger,
basic_trigger,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
\reset_out_reg[0] ); |
output O_reg;
output \xsdb_reg_reg[0] ;
output [14:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
output [0:0]D;
output TRIGGERED_SL_I;
output scnt_reset;
output cap_done;
output \current_state_reg[0] ;
output \current_state_reg[0]_0 ;
output [0:0]p_2_out;
output trigger_reg;
output [14:0]\xsdb_reg_reg[14] ;
output DOUT_O;
output u_wcnt_lcmp_q;
output u_wcnt_hcmp_q;
input [0:0]E;
input capture_ctrl_config_serial_output;
input [0:0]A;
input S_DCLK_O;
input scnt_cmp_temp;
input out;
input wcnt_lcmp_temp;
input wcnt_hcmp_temp;
input [1:0]capture_qual_ctrl_1;
input capture_strg_qual;
input capture_fsm;
input [1:0]Q;
input dout_reg1_reg;
input trig_out_fsm;
input en_adv_trigger;
input basic_trigger;
input \I_YESLUT6.I_YES_OREG.O_reg_reg ;
input [0:0]\reset_out_reg[0] ;
wire [0:0]A;
wire [0:0]D;
wire [14:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
wire DOUT_O;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire O_reg;
wire [1:0]Q;
wire S_DCLK_O;
wire TRIGGERED_SL_I;
wire U_CDONE_n_1;
wire basic_trigger;
wire cap_done;
wire capture_ctrl_config_serial_output;
wire capture_fsm;
wire capture_i;
wire [1:0]capture_qual_ctrl_1;
wire capture_strg_qual;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire \current_state_reg[0] ;
wire \current_state_reg[0]_0 ;
wire dout_reg1_reg;
wire en_adv_trigger;
wire itrigger_in;
(* async_reg = "true" *) wire itrigger_out;
(* async_reg = "true" *) wire n_0_0;
wire out;
wire [0:0]p_2_out;
wire [0:0]\reset_out_reg[0] ;
wire scnt_cmp;
wire scnt_cmp_temp;
wire scnt_reset;
wire trig_out_fsm;
wire trigger_reg;
wire u_wcnt_hcmp_q;
wire u_wcnt_lcmp_q;
wire wcnt_hcmp;
wire wcnt_hcmp_temp;
wire wcnt_lcmp;
wire wcnt_lcmp_temp;
wire \xsdb_reg_reg[0] ;
wire [14:0]\xsdb_reg_reg[14] ;
LUT4 #(
.INIT(16'hFDAD))
A0
(.I0(capture_qual_ctrl_1[0]),
.I1(capture_strg_qual),
.I2(capture_qual_ctrl_1[1]),
.I3(capture_fsm),
.O(capture_i));
FDRE #(
.INIT(1'b0))
CAP_DONE_O_reg
(.C(out),
.CE(1'b1),
.D(U_CDONE_n_1),
.Q(cap_done),
.R(1'b0));
FDRE CAP_TRIGGER_O_reg
(.C(out),
.CE(1'b1),
.D(n_0_0),
.Q(TRIGGERED_SL_I),
.R(Q[0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6__parameterized0 U_CDONE
(.A({wcnt_lcmp,capture_i,A,O_reg,\xsdb_reg_reg[0] }),
.CAP_DONE_O_reg(U_CDONE_n_1),
.D(D),
.E(E),
.Q(Q),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.cap_done(cap_done),
.out(out),
.wcnt_hcmp(wcnt_hcmp));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7 U_NS0
(.A({scnt_cmp,capture_i,A,O_reg}),
.D(cfg_data_1),
.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg_0 (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.Q(Q[0]),
.S_DCLK_O(S_DCLK_O),
.cap_done(cap_done),
.cfg_data_0(cfg_data_0),
.dout_reg1_reg(dout_reg1_reg),
.out(out),
.p_2_out(p_2_out),
.trig_out_fsm(trig_out_fsm),
.trigger_reg(trigger_reg),
.u_wcnt_lcmp_q(wcnt_lcmp),
.wcnt_hcmp(wcnt_hcmp),
.\xsdb_reg_reg[0] (\xsdb_reg_reg[0] ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut7_183 U_NS1
(.A({scnt_cmp,capture_i,A}),
.E(E),
.Q(Q[0]),
.S_DCLK_O(S_DCLK_O),
.basic_trigger(basic_trigger),
.capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
.cfg_data_0(cfg_data_0),
.\current_state_reg[0] (\current_state_reg[0] ),
.\current_state_reg[0]_0 (\current_state_reg[0]_0 ),
.dout_reg1_reg(dout_reg1_reg),
.en_adv_trigger(en_adv_trigger),
.itrigger_in(itrigger_in),
.out(out),
.trig_out_fsm(trig_out_fsm),
.u_wcnt_lcmp_q({wcnt_lcmp,\xsdb_reg_reg[0] }),
.wcnt_hcmp(wcnt_hcmp),
.\xsdb_reg_reg[1] (O_reg));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(itrigger_out),
.O(n_0_0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
itrigger_out_reg
(.C(out),
.CE(1'b1),
.D(itrigger_in),
.Q(itrigger_out),
.R(Q[0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_addrgen u_cap_addrgen
(.A({capture_i,A,O_reg,\xsdb_reg_reg[0] }),
.D(cfg_data_1),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ),
.DOUT_O(DOUT_O),
.E(E),
.Q(Q[0]),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.\iscnt_reg[0] (scnt_cmp),
.\iscnt_reg[0]_0 (scnt_reset),
.out(out),
.\reset_out_reg[0] (\reset_out_reg[0] ),
.scnt_cmp_temp(scnt_cmp_temp),
.u_wcnt_hcmp_q(u_wcnt_hcmp_q),
.u_wcnt_lcmp_q(wcnt_lcmp),
.u_wcnt_lcmp_q_0(u_wcnt_lcmp_q),
.wcnt_hcmp(wcnt_hcmp),
.wcnt_hcmp_temp(wcnt_hcmp_temp),
.wcnt_lcmp_temp(wcnt_lcmp_temp),
.\xsdb_reg_reg[14] (\xsdb_reg_reg[14] ));
endmodule | 8 |
2,144 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_sample_counter
(scnt_ce,
\iscnt_reg[0]_0 ,
\iscnt_reg[0]_1 ,
D,
SRL_Q_O,
DOUT_O,
E,
cfg_data_1,
A,
S_DCLK_O,
cmp_reset,
scnt_cmp_temp,
out,
\iwcnt_reg[14] ,
Q);
output scnt_ce;
output [0:0]\iscnt_reg[0]_0 ;
output \iscnt_reg[0]_1 ;
output [14:0]D;
output SRL_Q_O;
output DOUT_O;
input [0:0]E;
input cfg_data_1;
input [4:0]A;
input S_DCLK_O;
input cmp_reset;
input scnt_cmp_temp;
input out;
input [14:0]\iwcnt_reg[14] ;
input [14:0]Q;
wire [4:0]A;
wire [14:0]D;
wire DOUT_O;
wire [0:0]E;
wire [14:0]Q;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_1_0;
wire cfg_data_2;
wire cmp_reset;
wire \iscnt[0]_i_2_n_0 ;
wire \iscnt[0]_i_3_n_0 ;
wire \iscnt[0]_i_4_n_0 ;
wire \iscnt[0]_i_5_n_0 ;
wire \iscnt[12]_i_2_n_0 ;
wire \iscnt[12]_i_3_n_0 ;
wire \iscnt[12]_i_4_n_0 ;
wire \iscnt[4]_i_2_n_0 ;
wire \iscnt[4]_i_3_n_0 ;
wire \iscnt[4]_i_4_n_0 ;
wire \iscnt[4]_i_5_n_0 ;
wire \iscnt[8]_i_2_n_0 ;
wire \iscnt[8]_i_3_n_0 ;
wire \iscnt[8]_i_4_n_0 ;
wire \iscnt[8]_i_5_n_0 ;
wire [0:0]\iscnt_reg[0]_0 ;
wire \iscnt_reg[0]_1 ;
wire \iscnt_reg[0]_i_1_n_0 ;
wire \iscnt_reg[0]_i_1_n_1 ;
wire \iscnt_reg[0]_i_1_n_2 ;
wire \iscnt_reg[0]_i_1_n_3 ;
wire \iscnt_reg[0]_i_1_n_4 ;
wire \iscnt_reg[0]_i_1_n_5 ;
wire \iscnt_reg[0]_i_1_n_6 ;
wire \iscnt_reg[0]_i_1_n_7 ;
wire \iscnt_reg[12]_i_1_n_2 ;
wire \iscnt_reg[12]_i_1_n_3 ;
wire \iscnt_reg[12]_i_1_n_5 ;
wire \iscnt_reg[12]_i_1_n_6 ;
wire \iscnt_reg[12]_i_1_n_7 ;
wire \iscnt_reg[4]_i_1_n_0 ;
wire \iscnt_reg[4]_i_1_n_1 ;
wire \iscnt_reg[4]_i_1_n_2 ;
wire \iscnt_reg[4]_i_1_n_3 ;
wire \iscnt_reg[4]_i_1_n_4 ;
wire \iscnt_reg[4]_i_1_n_5 ;
wire \iscnt_reg[4]_i_1_n_6 ;
wire \iscnt_reg[4]_i_1_n_7 ;
wire \iscnt_reg[8]_i_1_n_0 ;
wire \iscnt_reg[8]_i_1_n_1 ;
wire \iscnt_reg[8]_i_1_n_2 ;
wire \iscnt_reg[8]_i_1_n_3 ;
wire \iscnt_reg[8]_i_1_n_4 ;
wire \iscnt_reg[8]_i_1_n_5 ;
wire \iscnt_reg[8]_i_1_n_6 ;
wire \iscnt_reg[8]_i_1_n_7 ;
wire [14:0]\iwcnt_reg[14] ;
wire out;
wire [14:0]scnt;
wire scnt_ce;
wire scnt_cmp_ce;
wire scnt_cmp_temp;
wire [3:2]\NLW_iscnt_reg[12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_iscnt_reg[12]_i_1_O_UNCONNECTED ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4_190 U_SCE
(.A(A[3:0]),
.E(E),
.S_DCLK_O(S_DCLK_O),
.cfg_data_0(cfg_data_0),
.cfg_data_1(cfg_data_1),
.\iscnt_reg[14] (scnt_ce));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_191 U_SCMPCE
(.A({\iscnt_reg[0]_0 ,A[3:0]}),
.E(E),
.S_DCLK_O(S_DCLK_O),
.cfg_data_0(cfg_data_0),
.cfg_data_1_0(cfg_data_1_0),
.scnt_cmp_ce(scnt_cmp_ce));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6_192 U_SCRST
(.A(A),
.E(E),
.SRL_D_I(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.cfg_data_1_0(cfg_data_1_0),
.\iscnt_reg[0] (\iscnt_reg[0]_1 ),
.u_scnt_cmp_q(\iscnt_reg[0]_0 ));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[0]_i_1
(.I0(scnt[0]),
.I1(\iwcnt_reg[14] [0]),
.I2(Q[0]),
.O(D[0]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[10]_i_1
(.I0(scnt[10]),
.I1(\iwcnt_reg[14] [10]),
.I2(Q[10]),
.O(D[10]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[11]_i_1
(.I0(scnt[11]),
.I1(\iwcnt_reg[14] [11]),
.I2(Q[11]),
.O(D[11]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[12]_i_1
(.I0(scnt[12]),
.I1(\iwcnt_reg[14] [12]),
.I2(Q[12]),
.O(D[12]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[13]_i_1
(.I0(scnt[13]),
.I1(\iwcnt_reg[14] [13]),
.I2(Q[13]),
.O(D[13]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[14]_i_1
(.I0(scnt[14]),
.I1(\iwcnt_reg[14] [14]),
.I2(Q[14]),
.O(D[14]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[1]_i_1
(.I0(scnt[1]),
.I1(\iwcnt_reg[14] [1]),
.I2(Q[1]),
.O(D[1]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[2]_i_1
(.I0(scnt[2]),
.I1(\iwcnt_reg[14] [2]),
.I2(Q[2]),
.O(D[2]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[3]_i_1
(.I0(scnt[3]),
.I1(\iwcnt_reg[14] [3]),
.I2(Q[3]),
.O(D[3]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[4]_i_1
(.I0(scnt[4]),
.I1(\iwcnt_reg[14] [4]),
.I2(Q[4]),
.O(D[4]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[5]_i_1
(.I0(scnt[5]),
.I1(\iwcnt_reg[14] [5]),
.I2(Q[5]),
.O(D[5]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[6]_i_1
(.I0(scnt[6]),
.I1(\iwcnt_reg[14] [6]),
.I2(Q[6]),
.O(D[6]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[7]_i_1
(.I0(scnt[7]),
.I1(\iwcnt_reg[14] [7]),
.I2(Q[7]),
.O(D[7]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[8]_i_1
(.I0(scnt[8]),
.I1(\iwcnt_reg[14] [8]),
.I2(Q[8]),
.O(D[8]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[9]_i_1
(.I0(scnt[9]),
.I1(\iwcnt_reg[14] [9]),
.I2(Q[9]),
.O(D[9]));
LUT1 #(
.INIT(2'h2))
\iscnt[0]_i_2
(.I0(scnt[3]),
.O(\iscnt[0]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[0]_i_3
(.I0(scnt[2]),
.O(\iscnt[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[0]_i_4
(.I0(scnt[1]),
.O(\iscnt[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\iscnt[0]_i_5
(.I0(scnt[0]),
.O(\iscnt[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[12]_i_2
(.I0(scnt[14]),
.O(\iscnt[12]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[12]_i_3
(.I0(scnt[13]),
.O(\iscnt[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[12]_i_4
(.I0(scnt[12]),
.O(\iscnt[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[4]_i_2
(.I0(scnt[7]),
.O(\iscnt[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[4]_i_3
(.I0(scnt[6]),
.O(\iscnt[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[4]_i_4
(.I0(scnt[5]),
.O(\iscnt[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[4]_i_5
(.I0(scnt[4]),
.O(\iscnt[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[8]_i_2
(.I0(scnt[11]),
.O(\iscnt[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[8]_i_3
(.I0(scnt[10]),
.O(\iscnt[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[8]_i_4
(.I0(scnt[9]),
.O(\iscnt[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[8]_i_5
(.I0(scnt[8]),
.O(\iscnt[8]_i_5_n_0 ));
FDRE \iscnt_reg[0]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[0]_i_1_n_7 ),
.Q(scnt[0]),
.R(\iscnt_reg[0]_1 ));
CARRY4 \iscnt_reg[0]_i_1
(.CI(1'b0),
.CO({\iscnt_reg[0]_i_1_n_0 ,\iscnt_reg[0]_i_1_n_1 ,\iscnt_reg[0]_i_1_n_2 ,\iscnt_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\iscnt_reg[0]_i_1_n_4 ,\iscnt_reg[0]_i_1_n_5 ,\iscnt_reg[0]_i_1_n_6 ,\iscnt_reg[0]_i_1_n_7 }),
.S({\iscnt[0]_i_2_n_0 ,\iscnt[0]_i_3_n_0 ,\iscnt[0]_i_4_n_0 ,\iscnt[0]_i_5_n_0 }));
FDRE \iscnt_reg[10]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[8]_i_1_n_5 ),
.Q(scnt[10]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[11]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[8]_i_1_n_4 ),
.Q(scnt[11]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[12]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[12]_i_1_n_7 ),
.Q(scnt[12]),
.R(\iscnt_reg[0]_1 ));
CARRY4 \iscnt_reg[12]_i_1
(.CI(\iscnt_reg[8]_i_1_n_0 ),
.CO({\NLW_iscnt_reg[12]_i_1_CO_UNCONNECTED [3:2],\iscnt_reg[12]_i_1_n_2 ,\iscnt_reg[12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_iscnt_reg[12]_i_1_O_UNCONNECTED [3],\iscnt_reg[12]_i_1_n_5 ,\iscnt_reg[12]_i_1_n_6 ,\iscnt_reg[12]_i_1_n_7 }),
.S({1'b0,\iscnt[12]_i_2_n_0 ,\iscnt[12]_i_3_n_0 ,\iscnt[12]_i_4_n_0 }));
FDRE \iscnt_reg[13]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[12]_i_1_n_6 ),
.Q(scnt[13]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[14]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[12]_i_1_n_5 ),
.Q(scnt[14]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[1]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[0]_i_1_n_6 ),
.Q(scnt[1]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[2]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[0]_i_1_n_5 ),
.Q(scnt[2]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[3]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[0]_i_1_n_4 ),
.Q(scnt[3]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[4]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[4]_i_1_n_7 ),
.Q(scnt[4]),
.R(\iscnt_reg[0]_1 ));
CARRY4 \iscnt_reg[4]_i_1
(.CI(\iscnt_reg[0]_i_1_n_0 ),
.CO({\iscnt_reg[4]_i_1_n_0 ,\iscnt_reg[4]_i_1_n_1 ,\iscnt_reg[4]_i_1_n_2 ,\iscnt_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\iscnt_reg[4]_i_1_n_4 ,\iscnt_reg[4]_i_1_n_5 ,\iscnt_reg[4]_i_1_n_6 ,\iscnt_reg[4]_i_1_n_7 }),
.S({\iscnt[4]_i_2_n_0 ,\iscnt[4]_i_3_n_0 ,\iscnt[4]_i_4_n_0 ,\iscnt[4]_i_5_n_0 }));
FDRE \iscnt_reg[5]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[4]_i_1_n_6 ),
.Q(scnt[5]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[6]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[4]_i_1_n_5 ),
.Q(scnt[6]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[7]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[4]_i_1_n_4 ),
.Q(scnt[7]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[8]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[8]_i_1_n_7 ),
.Q(scnt[8]),
.R(\iscnt_reg[0]_1 ));
CARRY4 \iscnt_reg[8]_i_1
(.CI(\iscnt_reg[4]_i_1_n_0 ),
.CO({\iscnt_reg[8]_i_1_n_0 ,\iscnt_reg[8]_i_1_n_1 ,\iscnt_reg[8]_i_1_n_2 ,\iscnt_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\iscnt_reg[8]_i_1_n_4 ,\iscnt_reg[8]_i_1_n_5 ,\iscnt_reg[8]_i_1_n_6 ,\iscnt_reg[8]_i_1_n_7 }),
.S({\iscnt[8]_i_2_n_0 ,\iscnt[8]_i_3_n_0 ,\iscnt[8]_i_4_n_0 ,\iscnt[8]_i_5_n_0 }));
FDRE \iscnt_reg[9]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[8]_i_1_n_6 ),
.Q(scnt[9]),
.R(\iscnt_reg[0]_1 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_193 u_scnt_cmp
(.D(scnt),
.DOUT_O(DOUT_O),
.E(E),
.SRL_D_I(cfg_data_2),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O),
.out(out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
u_scnt_cmp_q
(.C(out),
.CE(scnt_cmp_ce),
.D(scnt_cmp_temp),
.Q(\iscnt_reg[0]_0 ),
.R(cmp_reset));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_sample_counter
(scnt_ce,
\iscnt_reg[0]_0 ,
\iscnt_reg[0]_1 ,
D,
SRL_Q_O,
DOUT_O,
E,
cfg_data_1,
A,
S_DCLK_O,
cmp_reset,
scnt_cmp_temp,
out,
\iwcnt_reg[14] ,
Q); |
output scnt_ce;
output [0:0]\iscnt_reg[0]_0 ;
output \iscnt_reg[0]_1 ;
output [14:0]D;
output SRL_Q_O;
output DOUT_O;
input [0:0]E;
input cfg_data_1;
input [4:0]A;
input S_DCLK_O;
input cmp_reset;
input scnt_cmp_temp;
input out;
input [14:0]\iwcnt_reg[14] ;
input [14:0]Q;
wire [4:0]A;
wire [14:0]D;
wire DOUT_O;
wire [0:0]E;
wire [14:0]Q;
wire SRL_Q_O;
wire S_DCLK_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_1_0;
wire cfg_data_2;
wire cmp_reset;
wire \iscnt[0]_i_2_n_0 ;
wire \iscnt[0]_i_3_n_0 ;
wire \iscnt[0]_i_4_n_0 ;
wire \iscnt[0]_i_5_n_0 ;
wire \iscnt[12]_i_2_n_0 ;
wire \iscnt[12]_i_3_n_0 ;
wire \iscnt[12]_i_4_n_0 ;
wire \iscnt[4]_i_2_n_0 ;
wire \iscnt[4]_i_3_n_0 ;
wire \iscnt[4]_i_4_n_0 ;
wire \iscnt[4]_i_5_n_0 ;
wire \iscnt[8]_i_2_n_0 ;
wire \iscnt[8]_i_3_n_0 ;
wire \iscnt[8]_i_4_n_0 ;
wire \iscnt[8]_i_5_n_0 ;
wire [0:0]\iscnt_reg[0]_0 ;
wire \iscnt_reg[0]_1 ;
wire \iscnt_reg[0]_i_1_n_0 ;
wire \iscnt_reg[0]_i_1_n_1 ;
wire \iscnt_reg[0]_i_1_n_2 ;
wire \iscnt_reg[0]_i_1_n_3 ;
wire \iscnt_reg[0]_i_1_n_4 ;
wire \iscnt_reg[0]_i_1_n_5 ;
wire \iscnt_reg[0]_i_1_n_6 ;
wire \iscnt_reg[0]_i_1_n_7 ;
wire \iscnt_reg[12]_i_1_n_2 ;
wire \iscnt_reg[12]_i_1_n_3 ;
wire \iscnt_reg[12]_i_1_n_5 ;
wire \iscnt_reg[12]_i_1_n_6 ;
wire \iscnt_reg[12]_i_1_n_7 ;
wire \iscnt_reg[4]_i_1_n_0 ;
wire \iscnt_reg[4]_i_1_n_1 ;
wire \iscnt_reg[4]_i_1_n_2 ;
wire \iscnt_reg[4]_i_1_n_3 ;
wire \iscnt_reg[4]_i_1_n_4 ;
wire \iscnt_reg[4]_i_1_n_5 ;
wire \iscnt_reg[4]_i_1_n_6 ;
wire \iscnt_reg[4]_i_1_n_7 ;
wire \iscnt_reg[8]_i_1_n_0 ;
wire \iscnt_reg[8]_i_1_n_1 ;
wire \iscnt_reg[8]_i_1_n_2 ;
wire \iscnt_reg[8]_i_1_n_3 ;
wire \iscnt_reg[8]_i_1_n_4 ;
wire \iscnt_reg[8]_i_1_n_5 ;
wire \iscnt_reg[8]_i_1_n_6 ;
wire \iscnt_reg[8]_i_1_n_7 ;
wire [14:0]\iwcnt_reg[14] ;
wire out;
wire [14:0]scnt;
wire scnt_ce;
wire scnt_cmp_ce;
wire scnt_cmp_temp;
wire [3:2]\NLW_iscnt_reg[12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_iscnt_reg[12]_i_1_O_UNCONNECTED ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4_190 U_SCE
(.A(A[3:0]),
.E(E),
.S_DCLK_O(S_DCLK_O),
.cfg_data_0(cfg_data_0),
.cfg_data_1(cfg_data_1),
.\iscnt_reg[14] (scnt_ce));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_191 U_SCMPCE
(.A({\iscnt_reg[0]_0 ,A[3:0]}),
.E(E),
.S_DCLK_O(S_DCLK_O),
.cfg_data_0(cfg_data_0),
.cfg_data_1_0(cfg_data_1_0),
.scnt_cmp_ce(scnt_cmp_ce));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut6_192 U_SCRST
(.A(A),
.E(E),
.SRL_D_I(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.cfg_data_1_0(cfg_data_1_0),
.\iscnt_reg[0] (\iscnt_reg[0]_1 ),
.u_scnt_cmp_q(\iscnt_reg[0]_0 ));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[0]_i_1
(.I0(scnt[0]),
.I1(\iwcnt_reg[14] [0]),
.I2(Q[0]),
.O(D[0]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[10]_i_1
(.I0(scnt[10]),
.I1(\iwcnt_reg[14] [10]),
.I2(Q[10]),
.O(D[10]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[11]_i_1
(.I0(scnt[11]),
.I1(\iwcnt_reg[14] [11]),
.I2(Q[11]),
.O(D[11]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[12]_i_1
(.I0(scnt[12]),
.I1(\iwcnt_reg[14] [12]),
.I2(Q[12]),
.O(D[12]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[13]_i_1
(.I0(scnt[13]),
.I1(\iwcnt_reg[14] [13]),
.I2(Q[13]),
.O(D[13]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[14]_i_1
(.I0(scnt[14]),
.I1(\iwcnt_reg[14] [14]),
.I2(Q[14]),
.O(D[14]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[1]_i_1
(.I0(scnt[1]),
.I1(\iwcnt_reg[14] [1]),
.I2(Q[1]),
.O(D[1]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[2]_i_1
(.I0(scnt[2]),
.I1(\iwcnt_reg[14] [2]),
.I2(Q[2]),
.O(D[2]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[3]_i_1
(.I0(scnt[3]),
.I1(\iwcnt_reg[14] [3]),
.I2(Q[3]),
.O(D[3]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[4]_i_1
(.I0(scnt[4]),
.I1(\iwcnt_reg[14] [4]),
.I2(Q[4]),
.O(D[4]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[5]_i_1
(.I0(scnt[5]),
.I1(\iwcnt_reg[14] [5]),
.I2(Q[5]),
.O(D[5]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[6]_i_1
(.I0(scnt[6]),
.I1(\iwcnt_reg[14] [6]),
.I2(Q[6]),
.O(D[6]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[7]_i_1
(.I0(scnt[7]),
.I1(\iwcnt_reg[14] [7]),
.I2(Q[7]),
.O(D[7]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[8]_i_1
(.I0(scnt[8]),
.I1(\iwcnt_reg[14] [8]),
.I2(Q[8]),
.O(D[8]));
LUT3 #(
.INIT(8'hAC))
\i_intcap.icap_addr[9]_i_1
(.I0(scnt[9]),
.I1(\iwcnt_reg[14] [9]),
.I2(Q[9]),
.O(D[9]));
LUT1 #(
.INIT(2'h2))
\iscnt[0]_i_2
(.I0(scnt[3]),
.O(\iscnt[0]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[0]_i_3
(.I0(scnt[2]),
.O(\iscnt[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[0]_i_4
(.I0(scnt[1]),
.O(\iscnt[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\iscnt[0]_i_5
(.I0(scnt[0]),
.O(\iscnt[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[12]_i_2
(.I0(scnt[14]),
.O(\iscnt[12]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[12]_i_3
(.I0(scnt[13]),
.O(\iscnt[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[12]_i_4
(.I0(scnt[12]),
.O(\iscnt[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[4]_i_2
(.I0(scnt[7]),
.O(\iscnt[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[4]_i_3
(.I0(scnt[6]),
.O(\iscnt[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[4]_i_4
(.I0(scnt[5]),
.O(\iscnt[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[4]_i_5
(.I0(scnt[4]),
.O(\iscnt[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[8]_i_2
(.I0(scnt[11]),
.O(\iscnt[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[8]_i_3
(.I0(scnt[10]),
.O(\iscnt[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[8]_i_4
(.I0(scnt[9]),
.O(\iscnt[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iscnt[8]_i_5
(.I0(scnt[8]),
.O(\iscnt[8]_i_5_n_0 ));
FDRE \iscnt_reg[0]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[0]_i_1_n_7 ),
.Q(scnt[0]),
.R(\iscnt_reg[0]_1 ));
CARRY4 \iscnt_reg[0]_i_1
(.CI(1'b0),
.CO({\iscnt_reg[0]_i_1_n_0 ,\iscnt_reg[0]_i_1_n_1 ,\iscnt_reg[0]_i_1_n_2 ,\iscnt_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\iscnt_reg[0]_i_1_n_4 ,\iscnt_reg[0]_i_1_n_5 ,\iscnt_reg[0]_i_1_n_6 ,\iscnt_reg[0]_i_1_n_7 }),
.S({\iscnt[0]_i_2_n_0 ,\iscnt[0]_i_3_n_0 ,\iscnt[0]_i_4_n_0 ,\iscnt[0]_i_5_n_0 }));
FDRE \iscnt_reg[10]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[8]_i_1_n_5 ),
.Q(scnt[10]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[11]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[8]_i_1_n_4 ),
.Q(scnt[11]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[12]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[12]_i_1_n_7 ),
.Q(scnt[12]),
.R(\iscnt_reg[0]_1 ));
CARRY4 \iscnt_reg[12]_i_1
(.CI(\iscnt_reg[8]_i_1_n_0 ),
.CO({\NLW_iscnt_reg[12]_i_1_CO_UNCONNECTED [3:2],\iscnt_reg[12]_i_1_n_2 ,\iscnt_reg[12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_iscnt_reg[12]_i_1_O_UNCONNECTED [3],\iscnt_reg[12]_i_1_n_5 ,\iscnt_reg[12]_i_1_n_6 ,\iscnt_reg[12]_i_1_n_7 }),
.S({1'b0,\iscnt[12]_i_2_n_0 ,\iscnt[12]_i_3_n_0 ,\iscnt[12]_i_4_n_0 }));
FDRE \iscnt_reg[13]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[12]_i_1_n_6 ),
.Q(scnt[13]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[14]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[12]_i_1_n_5 ),
.Q(scnt[14]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[1]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[0]_i_1_n_6 ),
.Q(scnt[1]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[2]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[0]_i_1_n_5 ),
.Q(scnt[2]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[3]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[0]_i_1_n_4 ),
.Q(scnt[3]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[4]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[4]_i_1_n_7 ),
.Q(scnt[4]),
.R(\iscnt_reg[0]_1 ));
CARRY4 \iscnt_reg[4]_i_1
(.CI(\iscnt_reg[0]_i_1_n_0 ),
.CO({\iscnt_reg[4]_i_1_n_0 ,\iscnt_reg[4]_i_1_n_1 ,\iscnt_reg[4]_i_1_n_2 ,\iscnt_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\iscnt_reg[4]_i_1_n_4 ,\iscnt_reg[4]_i_1_n_5 ,\iscnt_reg[4]_i_1_n_6 ,\iscnt_reg[4]_i_1_n_7 }),
.S({\iscnt[4]_i_2_n_0 ,\iscnt[4]_i_3_n_0 ,\iscnt[4]_i_4_n_0 ,\iscnt[4]_i_5_n_0 }));
FDRE \iscnt_reg[5]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[4]_i_1_n_6 ),
.Q(scnt[5]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[6]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[4]_i_1_n_5 ),
.Q(scnt[6]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[7]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[4]_i_1_n_4 ),
.Q(scnt[7]),
.R(\iscnt_reg[0]_1 ));
FDRE \iscnt_reg[8]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[8]_i_1_n_7 ),
.Q(scnt[8]),
.R(\iscnt_reg[0]_1 ));
CARRY4 \iscnt_reg[8]_i_1
(.CI(\iscnt_reg[4]_i_1_n_0 ),
.CO({\iscnt_reg[8]_i_1_n_0 ,\iscnt_reg[8]_i_1_n_1 ,\iscnt_reg[8]_i_1_n_2 ,\iscnt_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\iscnt_reg[8]_i_1_n_4 ,\iscnt_reg[8]_i_1_n_5 ,\iscnt_reg[8]_i_1_n_6 ,\iscnt_reg[8]_i_1_n_7 }),
.S({\iscnt[8]_i_2_n_0 ,\iscnt[8]_i_3_n_0 ,\iscnt[8]_i_4_n_0 ,\iscnt[8]_i_5_n_0 }));
FDRE \iscnt_reg[9]
(.C(out),
.CE(scnt_ce),
.D(\iscnt_reg[8]_i_1_n_6 ),
.Q(scnt[9]),
.R(\iscnt_reg[0]_1 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_193 u_scnt_cmp
(.D(scnt),
.DOUT_O(DOUT_O),
.E(E),
.SRL_D_I(cfg_data_2),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O),
.out(out));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
u_scnt_cmp_q
(.C(out),
.CE(scnt_cmp_ce),
.D(scnt_cmp_temp),
.Q(\iscnt_reg[0]_0 ),
.R(cmp_reset));
endmodule | 8 |
2,145 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_window_counter
(u_wcnt_lcmp_q_0,
wcnt_hcmp,
D,
u_wcnt_lcmp_q_1,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
u_wcnt_hcmp_q_0,
E,
SRL_Q_O,
A,
S_DCLK_O,
cmp_reset,
wcnt_lcmp_temp,
out,
wcnt_hcmp_temp,
Q);
output [0:0]u_wcnt_lcmp_q_0;
output wcnt_hcmp;
output [14:0]D;
output u_wcnt_lcmp_q_1;
output \I_YESLUT6.I_YES_OREG.O_reg_reg ;
output u_wcnt_hcmp_q_0;
input [0:0]E;
input SRL_Q_O;
input [3:0]A;
input S_DCLK_O;
input cmp_reset;
input wcnt_lcmp_temp;
input out;
input wcnt_hcmp_temp;
input [0:0]Q;
wire [3:0]A;
wire [14:0]D;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [0:0]Q;
wire SRL_Q_O;
wire S_DCLK_O;
wire [29:1]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in ;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire cfg_data_3;
wire cmp_reset;
wire \iwcnt[0]_i_2_n_0 ;
wire \iwcnt[0]_i_3_n_0 ;
wire \iwcnt[0]_i_4_n_0 ;
wire \iwcnt[0]_i_5_n_0 ;
wire \iwcnt[12]_i_2_n_0 ;
wire \iwcnt[12]_i_3_n_0 ;
wire \iwcnt[12]_i_4_n_0 ;
wire \iwcnt[4]_i_2_n_0 ;
wire \iwcnt[4]_i_3_n_0 ;
wire \iwcnt[4]_i_4_n_0 ;
wire \iwcnt[4]_i_5_n_0 ;
wire \iwcnt[8]_i_2_n_0 ;
wire \iwcnt[8]_i_3_n_0 ;
wire \iwcnt[8]_i_4_n_0 ;
wire \iwcnt[8]_i_5_n_0 ;
wire \iwcnt_reg[0]_i_1_n_0 ;
wire \iwcnt_reg[0]_i_1_n_1 ;
wire \iwcnt_reg[0]_i_1_n_2 ;
wire \iwcnt_reg[0]_i_1_n_3 ;
wire \iwcnt_reg[0]_i_1_n_4 ;
wire \iwcnt_reg[0]_i_1_n_5 ;
wire \iwcnt_reg[0]_i_1_n_6 ;
wire \iwcnt_reg[0]_i_1_n_7 ;
wire \iwcnt_reg[12]_i_1_n_2 ;
wire \iwcnt_reg[12]_i_1_n_3 ;
wire \iwcnt_reg[12]_i_1_n_5 ;
wire \iwcnt_reg[12]_i_1_n_6 ;
wire \iwcnt_reg[12]_i_1_n_7 ;
wire \iwcnt_reg[4]_i_1_n_0 ;
wire \iwcnt_reg[4]_i_1_n_1 ;
wire \iwcnt_reg[4]_i_1_n_2 ;
wire \iwcnt_reg[4]_i_1_n_3 ;
wire \iwcnt_reg[4]_i_1_n_4 ;
wire \iwcnt_reg[4]_i_1_n_5 ;
wire \iwcnt_reg[4]_i_1_n_6 ;
wire \iwcnt_reg[4]_i_1_n_7 ;
wire \iwcnt_reg[8]_i_1_n_0 ;
wire \iwcnt_reg[8]_i_1_n_1 ;
wire \iwcnt_reg[8]_i_1_n_2 ;
wire \iwcnt_reg[8]_i_1_n_3 ;
wire \iwcnt_reg[8]_i_1_n_4 ;
wire \iwcnt_reg[8]_i_1_n_5 ;
wire \iwcnt_reg[8]_i_1_n_6 ;
wire \iwcnt_reg[8]_i_1_n_7 ;
wire out;
wire u_wcnt_hcmp_q_0;
wire [0:0]u_wcnt_lcmp_q_0;
wire u_wcnt_lcmp_q_1;
wire wcnt_ce;
wire wcnt_hcmp;
wire wcnt_hcmp_ce;
wire wcnt_hcmp_temp;
wire wcnt_lcmp_ce;
wire wcnt_lcmp_temp;
wire [3:2]\NLW_iwcnt_reg[12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_iwcnt_reg[12]_i_1_O_UNCONNECTED ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4 U_WCE
(.A(A),
.E(E),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O),
.cfg_data_0(cfg_data_0),
.wcnt_ce(wcnt_ce));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5 U_WHCMPCE
(.A({wcnt_hcmp,A}),
.E(E),
.SRL_D_I(cfg_data_3),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.wcnt_hcmp_ce(wcnt_hcmp_ce));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_184 U_WLCMPCE
(.A({u_wcnt_lcmp_q_0,A}),
.E(E),
.SRL_D_I(cfg_data_1),
.S_DCLK_O(S_DCLK_O),
.cfg_data_0(cfg_data_0),
.wcnt_lcmp_ce(wcnt_lcmp_ce));
LUT1 #(
.INIT(2'h2))
\iwcnt[0]_i_2
(.I0(D[3]),
.O(\iwcnt[0]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[0]_i_3
(.I0(D[2]),
.O(\iwcnt[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[0]_i_4
(.I0(D[1]),
.O(\iwcnt[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\iwcnt[0]_i_5
(.I0(D[0]),
.O(\iwcnt[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[12]_i_2
(.I0(D[14]),
.O(\iwcnt[12]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[12]_i_3
(.I0(D[13]),
.O(\iwcnt[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[12]_i_4
(.I0(D[12]),
.O(\iwcnt[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[4]_i_2
(.I0(D[7]),
.O(\iwcnt[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[4]_i_3
(.I0(D[6]),
.O(\iwcnt[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[4]_i_4
(.I0(D[5]),
.O(\iwcnt[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[4]_i_5
(.I0(D[4]),
.O(\iwcnt[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[8]_i_2
(.I0(D[11]),
.O(\iwcnt[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[8]_i_3
(.I0(D[10]),
.O(\iwcnt[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[8]_i_4
(.I0(D[9]),
.O(\iwcnt[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[8]_i_5
(.I0(D[8]),
.O(\iwcnt[8]_i_5_n_0 ));
FDRE \iwcnt_reg[0]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[0]_i_1_n_7 ),
.Q(D[0]),
.R(Q));
CARRY4 \iwcnt_reg[0]_i_1
(.CI(1'b0),
.CO({\iwcnt_reg[0]_i_1_n_0 ,\iwcnt_reg[0]_i_1_n_1 ,\iwcnt_reg[0]_i_1_n_2 ,\iwcnt_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\iwcnt_reg[0]_i_1_n_4 ,\iwcnt_reg[0]_i_1_n_5 ,\iwcnt_reg[0]_i_1_n_6 ,\iwcnt_reg[0]_i_1_n_7 }),
.S({\iwcnt[0]_i_2_n_0 ,\iwcnt[0]_i_3_n_0 ,\iwcnt[0]_i_4_n_0 ,\iwcnt[0]_i_5_n_0 }));
FDRE \iwcnt_reg[10]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[8]_i_1_n_5 ),
.Q(D[10]),
.R(Q));
FDRE \iwcnt_reg[11]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[8]_i_1_n_4 ),
.Q(D[11]),
.R(Q));
FDRE \iwcnt_reg[12]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[12]_i_1_n_7 ),
.Q(D[12]),
.R(Q));
CARRY4 \iwcnt_reg[12]_i_1
(.CI(\iwcnt_reg[8]_i_1_n_0 ),
.CO({\NLW_iwcnt_reg[12]_i_1_CO_UNCONNECTED [3:2],\iwcnt_reg[12]_i_1_n_2 ,\iwcnt_reg[12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_iwcnt_reg[12]_i_1_O_UNCONNECTED [3],\iwcnt_reg[12]_i_1_n_5 ,\iwcnt_reg[12]_i_1_n_6 ,\iwcnt_reg[12]_i_1_n_7 }),
.S({1'b0,\iwcnt[12]_i_2_n_0 ,\iwcnt[12]_i_3_n_0 ,\iwcnt[12]_i_4_n_0 }));
FDRE \iwcnt_reg[13]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[12]_i_1_n_6 ),
.Q(D[13]),
.R(Q));
FDRE \iwcnt_reg[14]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[12]_i_1_n_5 ),
.Q(D[14]),
.R(Q));
FDRE \iwcnt_reg[1]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[0]_i_1_n_6 ),
.Q(D[1]),
.R(Q));
FDRE \iwcnt_reg[2]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[0]_i_1_n_5 ),
.Q(D[2]),
.R(Q));
FDRE \iwcnt_reg[3]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[0]_i_1_n_4 ),
.Q(D[3]),
.R(Q));
FDRE \iwcnt_reg[4]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[4]_i_1_n_7 ),
.Q(D[4]),
.R(Q));
CARRY4 \iwcnt_reg[4]_i_1
(.CI(\iwcnt_reg[0]_i_1_n_0 ),
.CO({\iwcnt_reg[4]_i_1_n_0 ,\iwcnt_reg[4]_i_1_n_1 ,\iwcnt_reg[4]_i_1_n_2 ,\iwcnt_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\iwcnt_reg[4]_i_1_n_4 ,\iwcnt_reg[4]_i_1_n_5 ,\iwcnt_reg[4]_i_1_n_6 ,\iwcnt_reg[4]_i_1_n_7 }),
.S({\iwcnt[4]_i_2_n_0 ,\iwcnt[4]_i_3_n_0 ,\iwcnt[4]_i_4_n_0 ,\iwcnt[4]_i_5_n_0 }));
FDRE \iwcnt_reg[5]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[4]_i_1_n_6 ),
.Q(D[5]),
.R(Q));
FDRE \iwcnt_reg[6]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[4]_i_1_n_5 ),
.Q(D[6]),
.R(Q));
FDRE \iwcnt_reg[7]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[4]_i_1_n_4 ),
.Q(D[7]),
.R(Q));
FDRE \iwcnt_reg[8]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[8]_i_1_n_7 ),
.Q(D[8]),
.R(Q));
CARRY4 \iwcnt_reg[8]_i_1
(.CI(\iwcnt_reg[4]_i_1_n_0 ),
.CO({\iwcnt_reg[8]_i_1_n_0 ,\iwcnt_reg[8]_i_1_n_1 ,\iwcnt_reg[8]_i_1_n_2 ,\iwcnt_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\iwcnt_reg[8]_i_1_n_4 ,\iwcnt_reg[8]_i_1_n_5 ,\iwcnt_reg[8]_i_1_n_6 ,\iwcnt_reg[8]_i_1_n_7 }),
.S({\iwcnt[8]_i_2_n_0 ,\iwcnt[8]_i_3_n_0 ,\iwcnt[8]_i_4_n_0 ,\iwcnt[8]_i_5_n_0 }));
FDRE \iwcnt_reg[9]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[8]_i_1_n_6 ),
.Q(D[9]),
.R(Q));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay u_wcnt_hcmp
(.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.PROBES_I({\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [29],D[14],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [27],D[13],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [25],D[12],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [23],D[11],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [21],D[10],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [19],D[9],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [17],D[8],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [15],D[7],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [13],D[6],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [11],D[5],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [9],D[4],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [7],D[3],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [5],D[2],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [3],D[1],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [1],D[0]}),
.SRL_D_I(cfg_data_3),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_hcmp_q(u_wcnt_hcmp_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
u_wcnt_hcmp_q
(.C(out),
.CE(wcnt_hcmp_ce),
.D(wcnt_hcmp_temp),
.Q(wcnt_hcmp),
.R(cmp_reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_185 u_wcnt_lcmp
(.E(E),
.PROBES_I(D),
.Q({\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [29],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [27],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [25],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [23],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [21],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [19],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [17],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [15],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [13],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [11],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [9],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [7],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [5],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [3],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [1]}),
.SRL_D_I(cfg_data_1),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.out(out),
.u_wcnt_lcmp_q(u_wcnt_lcmp_q_1));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
u_wcnt_lcmp_q
(.C(out),
.CE(wcnt_lcmp_ce),
.D(wcnt_lcmp_temp),
.Q(u_wcnt_lcmp_q_0),
.R(cmp_reset));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_window_counter
(u_wcnt_lcmp_q_0,
wcnt_hcmp,
D,
u_wcnt_lcmp_q_1,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
u_wcnt_hcmp_q_0,
E,
SRL_Q_O,
A,
S_DCLK_O,
cmp_reset,
wcnt_lcmp_temp,
out,
wcnt_hcmp_temp,
Q); |
output [0:0]u_wcnt_lcmp_q_0;
output wcnt_hcmp;
output [14:0]D;
output u_wcnt_lcmp_q_1;
output \I_YESLUT6.I_YES_OREG.O_reg_reg ;
output u_wcnt_hcmp_q_0;
input [0:0]E;
input SRL_Q_O;
input [3:0]A;
input S_DCLK_O;
input cmp_reset;
input wcnt_lcmp_temp;
input out;
input wcnt_hcmp_temp;
input [0:0]Q;
wire [3:0]A;
wire [14:0]D;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [0:0]Q;
wire SRL_Q_O;
wire S_DCLK_O;
wire [29:1]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in ;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire cfg_data_3;
wire cmp_reset;
wire \iwcnt[0]_i_2_n_0 ;
wire \iwcnt[0]_i_3_n_0 ;
wire \iwcnt[0]_i_4_n_0 ;
wire \iwcnt[0]_i_5_n_0 ;
wire \iwcnt[12]_i_2_n_0 ;
wire \iwcnt[12]_i_3_n_0 ;
wire \iwcnt[12]_i_4_n_0 ;
wire \iwcnt[4]_i_2_n_0 ;
wire \iwcnt[4]_i_3_n_0 ;
wire \iwcnt[4]_i_4_n_0 ;
wire \iwcnt[4]_i_5_n_0 ;
wire \iwcnt[8]_i_2_n_0 ;
wire \iwcnt[8]_i_3_n_0 ;
wire \iwcnt[8]_i_4_n_0 ;
wire \iwcnt[8]_i_5_n_0 ;
wire \iwcnt_reg[0]_i_1_n_0 ;
wire \iwcnt_reg[0]_i_1_n_1 ;
wire \iwcnt_reg[0]_i_1_n_2 ;
wire \iwcnt_reg[0]_i_1_n_3 ;
wire \iwcnt_reg[0]_i_1_n_4 ;
wire \iwcnt_reg[0]_i_1_n_5 ;
wire \iwcnt_reg[0]_i_1_n_6 ;
wire \iwcnt_reg[0]_i_1_n_7 ;
wire \iwcnt_reg[12]_i_1_n_2 ;
wire \iwcnt_reg[12]_i_1_n_3 ;
wire \iwcnt_reg[12]_i_1_n_5 ;
wire \iwcnt_reg[12]_i_1_n_6 ;
wire \iwcnt_reg[12]_i_1_n_7 ;
wire \iwcnt_reg[4]_i_1_n_0 ;
wire \iwcnt_reg[4]_i_1_n_1 ;
wire \iwcnt_reg[4]_i_1_n_2 ;
wire \iwcnt_reg[4]_i_1_n_3 ;
wire \iwcnt_reg[4]_i_1_n_4 ;
wire \iwcnt_reg[4]_i_1_n_5 ;
wire \iwcnt_reg[4]_i_1_n_6 ;
wire \iwcnt_reg[4]_i_1_n_7 ;
wire \iwcnt_reg[8]_i_1_n_0 ;
wire \iwcnt_reg[8]_i_1_n_1 ;
wire \iwcnt_reg[8]_i_1_n_2 ;
wire \iwcnt_reg[8]_i_1_n_3 ;
wire \iwcnt_reg[8]_i_1_n_4 ;
wire \iwcnt_reg[8]_i_1_n_5 ;
wire \iwcnt_reg[8]_i_1_n_6 ;
wire \iwcnt_reg[8]_i_1_n_7 ;
wire out;
wire u_wcnt_hcmp_q_0;
wire [0:0]u_wcnt_lcmp_q_0;
wire u_wcnt_lcmp_q_1;
wire wcnt_ce;
wire wcnt_hcmp;
wire wcnt_hcmp_ce;
wire wcnt_hcmp_temp;
wire wcnt_lcmp_ce;
wire wcnt_lcmp_temp;
wire [3:2]\NLW_iwcnt_reg[12]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_iwcnt_reg[12]_i_1_O_UNCONNECTED ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut4 U_WCE
(.A(A),
.E(E),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O),
.cfg_data_0(cfg_data_0),
.wcnt_ce(wcnt_ce));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5 U_WHCMPCE
(.A({wcnt_hcmp,A}),
.E(E),
.SRL_D_I(cfg_data_3),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.wcnt_hcmp_ce(wcnt_hcmp_ce));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_cfglut5_184 U_WLCMPCE
(.A({u_wcnt_lcmp_q_0,A}),
.E(E),
.SRL_D_I(cfg_data_1),
.S_DCLK_O(S_DCLK_O),
.cfg_data_0(cfg_data_0),
.wcnt_lcmp_ce(wcnt_lcmp_ce));
LUT1 #(
.INIT(2'h2))
\iwcnt[0]_i_2
(.I0(D[3]),
.O(\iwcnt[0]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[0]_i_3
(.I0(D[2]),
.O(\iwcnt[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[0]_i_4
(.I0(D[1]),
.O(\iwcnt[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h1))
\iwcnt[0]_i_5
(.I0(D[0]),
.O(\iwcnt[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[12]_i_2
(.I0(D[14]),
.O(\iwcnt[12]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[12]_i_3
(.I0(D[13]),
.O(\iwcnt[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[12]_i_4
(.I0(D[12]),
.O(\iwcnt[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[4]_i_2
(.I0(D[7]),
.O(\iwcnt[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[4]_i_3
(.I0(D[6]),
.O(\iwcnt[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[4]_i_4
(.I0(D[5]),
.O(\iwcnt[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[4]_i_5
(.I0(D[4]),
.O(\iwcnt[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[8]_i_2
(.I0(D[11]),
.O(\iwcnt[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[8]_i_3
(.I0(D[10]),
.O(\iwcnt[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[8]_i_4
(.I0(D[9]),
.O(\iwcnt[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\iwcnt[8]_i_5
(.I0(D[8]),
.O(\iwcnt[8]_i_5_n_0 ));
FDRE \iwcnt_reg[0]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[0]_i_1_n_7 ),
.Q(D[0]),
.R(Q));
CARRY4 \iwcnt_reg[0]_i_1
(.CI(1'b0),
.CO({\iwcnt_reg[0]_i_1_n_0 ,\iwcnt_reg[0]_i_1_n_1 ,\iwcnt_reg[0]_i_1_n_2 ,\iwcnt_reg[0]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\iwcnt_reg[0]_i_1_n_4 ,\iwcnt_reg[0]_i_1_n_5 ,\iwcnt_reg[0]_i_1_n_6 ,\iwcnt_reg[0]_i_1_n_7 }),
.S({\iwcnt[0]_i_2_n_0 ,\iwcnt[0]_i_3_n_0 ,\iwcnt[0]_i_4_n_0 ,\iwcnt[0]_i_5_n_0 }));
FDRE \iwcnt_reg[10]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[8]_i_1_n_5 ),
.Q(D[10]),
.R(Q));
FDRE \iwcnt_reg[11]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[8]_i_1_n_4 ),
.Q(D[11]),
.R(Q));
FDRE \iwcnt_reg[12]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[12]_i_1_n_7 ),
.Q(D[12]),
.R(Q));
CARRY4 \iwcnt_reg[12]_i_1
(.CI(\iwcnt_reg[8]_i_1_n_0 ),
.CO({\NLW_iwcnt_reg[12]_i_1_CO_UNCONNECTED [3:2],\iwcnt_reg[12]_i_1_n_2 ,\iwcnt_reg[12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_iwcnt_reg[12]_i_1_O_UNCONNECTED [3],\iwcnt_reg[12]_i_1_n_5 ,\iwcnt_reg[12]_i_1_n_6 ,\iwcnt_reg[12]_i_1_n_7 }),
.S({1'b0,\iwcnt[12]_i_2_n_0 ,\iwcnt[12]_i_3_n_0 ,\iwcnt[12]_i_4_n_0 }));
FDRE \iwcnt_reg[13]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[12]_i_1_n_6 ),
.Q(D[13]),
.R(Q));
FDRE \iwcnt_reg[14]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[12]_i_1_n_5 ),
.Q(D[14]),
.R(Q));
FDRE \iwcnt_reg[1]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[0]_i_1_n_6 ),
.Q(D[1]),
.R(Q));
FDRE \iwcnt_reg[2]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[0]_i_1_n_5 ),
.Q(D[2]),
.R(Q));
FDRE \iwcnt_reg[3]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[0]_i_1_n_4 ),
.Q(D[3]),
.R(Q));
FDRE \iwcnt_reg[4]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[4]_i_1_n_7 ),
.Q(D[4]),
.R(Q));
CARRY4 \iwcnt_reg[4]_i_1
(.CI(\iwcnt_reg[0]_i_1_n_0 ),
.CO({\iwcnt_reg[4]_i_1_n_0 ,\iwcnt_reg[4]_i_1_n_1 ,\iwcnt_reg[4]_i_1_n_2 ,\iwcnt_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\iwcnt_reg[4]_i_1_n_4 ,\iwcnt_reg[4]_i_1_n_5 ,\iwcnt_reg[4]_i_1_n_6 ,\iwcnt_reg[4]_i_1_n_7 }),
.S({\iwcnt[4]_i_2_n_0 ,\iwcnt[4]_i_3_n_0 ,\iwcnt[4]_i_4_n_0 ,\iwcnt[4]_i_5_n_0 }));
FDRE \iwcnt_reg[5]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[4]_i_1_n_6 ),
.Q(D[5]),
.R(Q));
FDRE \iwcnt_reg[6]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[4]_i_1_n_5 ),
.Q(D[6]),
.R(Q));
FDRE \iwcnt_reg[7]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[4]_i_1_n_4 ),
.Q(D[7]),
.R(Q));
FDRE \iwcnt_reg[8]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[8]_i_1_n_7 ),
.Q(D[8]),
.R(Q));
CARRY4 \iwcnt_reg[8]_i_1
(.CI(\iwcnt_reg[4]_i_1_n_0 ),
.CO({\iwcnt_reg[8]_i_1_n_0 ,\iwcnt_reg[8]_i_1_n_1 ,\iwcnt_reg[8]_i_1_n_2 ,\iwcnt_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\iwcnt_reg[8]_i_1_n_4 ,\iwcnt_reg[8]_i_1_n_5 ,\iwcnt_reg[8]_i_1_n_6 ,\iwcnt_reg[8]_i_1_n_7 }),
.S({\iwcnt[8]_i_2_n_0 ,\iwcnt[8]_i_3_n_0 ,\iwcnt[8]_i_4_n_0 ,\iwcnt[8]_i_5_n_0 }));
FDRE \iwcnt_reg[9]
(.C(out),
.CE(wcnt_ce),
.D(\iwcnt_reg[8]_i_1_n_6 ),
.Q(D[9]),
.R(Q));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay u_wcnt_hcmp
(.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.PROBES_I({\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [29],D[14],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [27],D[13],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [25],D[12],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [23],D[11],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [21],D[10],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [19],D[9],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [17],D[8],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [15],D[7],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [13],D[6],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [11],D[5],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [9],D[4],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [7],D[3],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [5],D[2],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [3],D[1],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [1],D[0]}),
.SRL_D_I(cfg_data_3),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_hcmp_q(u_wcnt_hcmp_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
u_wcnt_hcmp_q
(.C(out),
.CE(wcnt_hcmp_ce),
.D(wcnt_hcmp_temp),
.Q(wcnt_hcmp),
.R(cmp_reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_185 u_wcnt_lcmp
(.E(E),
.PROBES_I(D),
.Q({\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [29],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [27],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [25],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [23],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [21],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [19],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [17],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [15],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [13],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [11],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [9],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [7],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [5],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [3],\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_in [1]}),
.SRL_D_I(cfg_data_1),
.SRL_Q_O(cfg_data_2),
.S_DCLK_O(S_DCLK_O),
.out(out),
.u_wcnt_lcmp_q(u_wcnt_lcmp_q_1));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
u_wcnt_lcmp_q
(.C(out),
.CE(wcnt_lcmp_ce),
.D(wcnt_lcmp_temp),
.Q(u_wcnt_lcmp_q_0),
.R(cmp_reset));
endmodule | 8 |
2,146 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_core
(SL_OPORT_O,
out,
probe8,
probe7,
probe6,
probe5,
probe4,
probe3,
probe2,
probe1,
probe0,
SL_IPORT_I,
DUMMY_I);
output [16:0]SL_OPORT_O;
input out;
input [1:0]probe8;
input [0:0]probe7;
input [12:0]probe6;
input [0:0]probe5;
input [0:0]probe4;
input [15:0]probe3;
input [15:0]probe2;
input [0:0]probe1;
input [0:0]probe0;
input [36:0]SL_IPORT_I;
input DUMMY_I;
wire \ADV_TRIG.u_adv_trig_n_18 ;
wire \ADV_TRIG.u_adv_trig_n_6 ;
wire \ADV_TRIG.u_adv_trig_n_7 ;
wire \ADV_TRIG.u_adv_trig_n_8 ;
wire \ADV_TRIG.u_adv_trig_n_9 ;
wire [15:0]BRAM_DATA_reg;
wire [23:16]CFG_BRAM_DATA;
wire [23:0]CFG_BRAM_RD_DATA;
wire DUMMY_I;
wire \I_EN_CTL_EQ1.temp_en_i_2_n_0 ;
wire O_reg;
wire [15:0]SEQUENCER_STATE_O;
wire [36:0]SL_IPORT_I;
wire [16:0]SL_OPORT_O;
wire [7:0]\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ;
wire [52:0]\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/din_2D[7]__0 ;
wire address;
wire adv_drdy;
wire adv_drdy_i_1_n_0;
wire arm_ctrl;
wire arm_status;
wire basic_trigger;
wire bram_en;
wire bram_rd_en;
wire cap_done;
wire cap_trigger_out;
wire [14:0]cap_wr_addr;
wire cap_wr_en;
wire [14:0]capture_cnt;
wire capture_ctrl_config_cs_serial_input;
wire capture_ctrl_config_en;
wire capture_ctrl_config_serial_output;
wire capture_fsm;
wire [1:0]capture_qual_ctrl_1;
wire capture_strg_qual;
wire [3:0]cnt_config_cs_serial_input;
wire [3:0]cnt_config_cs_serial_output;
wire [3:0]cnt_config_cs_shift_en;
wire [15:0]config_fsm_data;
wire [15:0]config_fsm_data_rd;
wire count_tt;
wire count_tt_i_1_n_0;
wire [7:0]counter_ctrl;
wire [3:0]counter_out;
wire \current_state[1]_i_2__0_n_0 ;
wire \current_state[1]_i_2__1_n_0 ;
wire \current_state[1]_i_2__2_n_0 ;
wire \current_state[1]_i_2__3_n_0 ;
wire \current_state[1]_i_2__4_n_0 ;
wire \current_state[1]_i_2__5_n_0 ;
wire \current_state[1]_i_2__6_n_0 ;
wire \current_state[1]_i_2__7_n_0 ;
wire \current_state[1]_i_2__8_n_0 ;
wire \current_state[1]_i_2__9_n_0 ;
wire \current_state[1]_i_2_n_0 ;
wire \current_state[1]_i_3_n_0 ;
wire \current_state[1]_i_4_n_0 ;
wire \current_state[3]_i_5__0__0_n_0 ;
wire \current_state[3]_i_5__0_n_0 ;
wire data_out_en;
wire [15:0]data_word_out;
wire [1:0]debug_data_in;
wire drdy_ff9;
wire drdy_ffa;
wire drdy_ffa_i_2_n_0;
wire en_adv_trigger;
wire en_adv_trigger_1;
wire en_adv_trigger_2;
wire flag0_temp;
wire flag1_temp;
wire flag2_temp;
wire flag3_temp;
wire halt_ctrl;
wire halt_status;
wire [15:0]mu_config_cs_serial_input;
wire [15:0]mu_config_cs_serial_output;
wire [15:0]mu_config_cs_shift_en;
wire out;
wire [15:15]p_2_out;
wire [0:0]probe0;
wire [0:0]probe1;
wire [15:0]probe2;
wire [15:0]probe3;
wire [0:0]probe4;
wire [0:0]probe5;
wire [12:0]probe6;
wire [0:0]probe7;
wire [1:0]probe8;
wire [49:0]probe_data;
wire qual_strg_config_cs_serial_input;
wire qual_strg_config_cs_serial_output;
wire qual_strg_config_cs_shift_en;
wire read_addr_reset;
wire read_data_en;
wire [14:0]read_reset_addr;
wire [3:0]reset;
wire [12:0]s_daddr;
wire s_dclk;
wire s_den;
wire s_dwe;
wire s_rst;
wire scnt_reset;
wire [2:0]sel_i;
wire \shift_reg0[8]_i_1_n_0 ;
wire \shift_reg1[15]_i_1_n_0 ;
wire \shifted_data_in_reg[7][0]_srl8_n_0 ;
wire \shifted_data_in_reg[7][10]_srl7_n_0 ;
wire \shifted_data_in_reg[7][11]_srl7_n_0 ;
wire \shifted_data_in_reg[7][12]_srl7_n_0 ;
wire \shifted_data_in_reg[7][13]_srl7_n_0 ;
wire \shifted_data_in_reg[7][14]_srl7_n_0 ;
wire \shifted_data_in_reg[7][15]_srl7_n_0 ;
wire \shifted_data_in_reg[7][16]_srl7_n_0 ;
wire \shifted_data_in_reg[7][17]_srl7_n_0 ;
wire \shifted_data_in_reg[7][18]_srl7_n_0 ;
wire \shifted_data_in_reg[7][19]_srl7_n_0 ;
wire \shifted_data_in_reg[7][1]_srl8_n_0 ;
wire \shifted_data_in_reg[7][20]_srl7_n_0 ;
wire \shifted_data_in_reg[7][21]_srl7_n_0 ;
wire \shifted_data_in_reg[7][22]_srl7_n_0 ;
wire \shifted_data_in_reg[7][23]_srl7_n_0 ;
wire \shifted_data_in_reg[7][24]_srl7_n_0 ;
wire \shifted_data_in_reg[7][25]_srl7_n_0 ;
wire \shifted_data_in_reg[7][26]_srl7_n_0 ;
wire \shifted_data_in_reg[7][27]_srl7_n_0 ;
wire \shifted_data_in_reg[7][28]_srl7_n_0 ;
wire \shifted_data_in_reg[7][29]_srl7_n_0 ;
wire \shifted_data_in_reg[7][2]_srl7_n_0 ;
wire \shifted_data_in_reg[7][30]_srl7_n_0 ;
wire \shifted_data_in_reg[7][31]_srl7_n_0 ;
wire \shifted_data_in_reg[7][32]_srl7_n_0 ;
wire \shifted_data_in_reg[7][33]_srl7_n_0 ;
wire \shifted_data_in_reg[7][34]_srl8_n_0 ;
wire \shifted_data_in_reg[7][35]_srl8_n_0 ;
wire \shifted_data_in_reg[7][36]_srl7_n_0 ;
wire \shifted_data_in_reg[7][37]_srl7_n_0 ;
wire \shifted_data_in_reg[7][38]_srl7_n_0 ;
wire \shifted_data_in_reg[7][39]_srl7_n_0 ;
wire \shifted_data_in_reg[7][3]_srl7_n_0 ;
wire \shifted_data_in_reg[7][40]_srl7_n_0 ;
wire \shifted_data_in_reg[7][41]_srl7_n_0 ;
wire \shifted_data_in_reg[7][42]_srl7_n_0 ;
wire \shifted_data_in_reg[7][43]_srl7_n_0 ;
wire \shifted_data_in_reg[7][44]_srl7_n_0 ;
wire \shifted_data_in_reg[7][45]_srl7_n_0 ;
wire \shifted_data_in_reg[7][46]_srl7_n_0 ;
wire \shifted_data_in_reg[7][47]_srl7_n_0 ;
wire \shifted_data_in_reg[7][48]_srl7_n_0 ;
wire \shifted_data_in_reg[7][49]_srl8_n_0 ;
wire \shifted_data_in_reg[7][4]_srl7_n_0 ;
wire \shifted_data_in_reg[7][50]_srl7_n_0 ;
wire \shifted_data_in_reg[7][51]_srl7_n_0 ;
wire \shifted_data_in_reg[7][5]_srl7_n_0 ;
wire \shifted_data_in_reg[7][6]_srl7_n_0 ;
wire \shifted_data_in_reg[7][7]_srl7_n_0 ;
wire \shifted_data_in_reg[7][8]_srl7_n_0 ;
wire \shifted_data_in_reg[7][9]_srl7_n_0 ;
wire \shifted_data_in_reg_n_0_[0][10] ;
wire \shifted_data_in_reg_n_0_[0][11] ;
wire \shifted_data_in_reg_n_0_[0][12] ;
wire \shifted_data_in_reg_n_0_[0][13] ;
wire \shifted_data_in_reg_n_0_[0][14] ;
wire \shifted_data_in_reg_n_0_[0][15] ;
wire \shifted_data_in_reg_n_0_[0][16] ;
wire \shifted_data_in_reg_n_0_[0][17] ;
wire \shifted_data_in_reg_n_0_[0][18] ;
wire \shifted_data_in_reg_n_0_[0][19] ;
wire \shifted_data_in_reg_n_0_[0][20] ;
wire \shifted_data_in_reg_n_0_[0][21] ;
wire \shifted_data_in_reg_n_0_[0][22] ;
wire \shifted_data_in_reg_n_0_[0][23] ;
wire \shifted_data_in_reg_n_0_[0][24] ;
wire \shifted_data_in_reg_n_0_[0][25] ;
wire \shifted_data_in_reg_n_0_[0][26] ;
wire \shifted_data_in_reg_n_0_[0][27] ;
wire \shifted_data_in_reg_n_0_[0][28] ;
wire \shifted_data_in_reg_n_0_[0][29] ;
wire \shifted_data_in_reg_n_0_[0][2] ;
wire \shifted_data_in_reg_n_0_[0][30] ;
wire \shifted_data_in_reg_n_0_[0][31] ;
wire \shifted_data_in_reg_n_0_[0][32] ;
wire \shifted_data_in_reg_n_0_[0][33] ;
wire \shifted_data_in_reg_n_0_[0][36] ;
wire \shifted_data_in_reg_n_0_[0][37] ;
wire \shifted_data_in_reg_n_0_[0][38] ;
wire \shifted_data_in_reg_n_0_[0][39] ;
wire \shifted_data_in_reg_n_0_[0][3] ;
wire \shifted_data_in_reg_n_0_[0][40] ;
wire \shifted_data_in_reg_n_0_[0][41] ;
wire \shifted_data_in_reg_n_0_[0][42] ;
wire \shifted_data_in_reg_n_0_[0][43] ;
wire \shifted_data_in_reg_n_0_[0][44] ;
wire \shifted_data_in_reg_n_0_[0][45] ;
wire \shifted_data_in_reg_n_0_[0][46] ;
wire \shifted_data_in_reg_n_0_[0][47] ;
wire \shifted_data_in_reg_n_0_[0][48] ;
wire \shifted_data_in_reg_n_0_[0][4] ;
wire \shifted_data_in_reg_n_0_[0][50] ;
wire \shifted_data_in_reg_n_0_[0][51] ;
wire \shifted_data_in_reg_n_0_[0][5] ;
wire \shifted_data_in_reg_n_0_[0][6] ;
wire \shifted_data_in_reg_n_0_[0][7] ;
wire \shifted_data_in_reg_n_0_[0][8] ;
wire \shifted_data_in_reg_n_0_[0][9] ;
wire \shifted_data_in_reg_n_0_[8][0] ;
wire \shifted_data_in_reg_n_0_[8][10] ;
wire \shifted_data_in_reg_n_0_[8][11] ;
wire \shifted_data_in_reg_n_0_[8][12] ;
wire \shifted_data_in_reg_n_0_[8][13] ;
wire \shifted_data_in_reg_n_0_[8][14] ;
wire \shifted_data_in_reg_n_0_[8][15] ;
wire \shifted_data_in_reg_n_0_[8][16] ;
wire \shifted_data_in_reg_n_0_[8][17] ;
wire \shifted_data_in_reg_n_0_[8][18] ;
wire \shifted_data_in_reg_n_0_[8][19] ;
wire \shifted_data_in_reg_n_0_[8][1] ;
wire \shifted_data_in_reg_n_0_[8][20] ;
wire \shifted_data_in_reg_n_0_[8][21] ;
wire \shifted_data_in_reg_n_0_[8][22] ;
wire \shifted_data_in_reg_n_0_[8][23] ;
wire \shifted_data_in_reg_n_0_[8][24] ;
wire \shifted_data_in_reg_n_0_[8][25] ;
wire \shifted_data_in_reg_n_0_[8][26] ;
wire \shifted_data_in_reg_n_0_[8][27] ;
wire \shifted_data_in_reg_n_0_[8][28] ;
wire \shifted_data_in_reg_n_0_[8][29] ;
wire \shifted_data_in_reg_n_0_[8][2] ;
wire \shifted_data_in_reg_n_0_[8][30] ;
wire \shifted_data_in_reg_n_0_[8][31] ;
wire \shifted_data_in_reg_n_0_[8][32] ;
wire \shifted_data_in_reg_n_0_[8][33] ;
wire \shifted_data_in_reg_n_0_[8][34] ;
wire \shifted_data_in_reg_n_0_[8][35] ;
wire \shifted_data_in_reg_n_0_[8][36] ;
wire \shifted_data_in_reg_n_0_[8][37] ;
wire \shifted_data_in_reg_n_0_[8][38] ;
wire \shifted_data_in_reg_n_0_[8][39] ;
wire \shifted_data_in_reg_n_0_[8][3] ;
wire \shifted_data_in_reg_n_0_[8][40] ;
wire \shifted_data_in_reg_n_0_[8][41] ;
wire \shifted_data_in_reg_n_0_[8][42] ;
wire \shifted_data_in_reg_n_0_[8][43] ;
wire \shifted_data_in_reg_n_0_[8][44] ;
wire \shifted_data_in_reg_n_0_[8][45] ;
wire \shifted_data_in_reg_n_0_[8][46] ;
wire \shifted_data_in_reg_n_0_[8][47] ;
wire \shifted_data_in_reg_n_0_[8][48] ;
wire \shifted_data_in_reg_n_0_[8][49] ;
wire \shifted_data_in_reg_n_0_[8][4] ;
wire \shifted_data_in_reg_n_0_[8][50] ;
wire \shifted_data_in_reg_n_0_[8][51] ;
wire \shifted_data_in_reg_n_0_[8][5] ;
wire \shifted_data_in_reg_n_0_[8][6] ;
wire \shifted_data_in_reg_n_0_[8][7] ;
wire \shifted_data_in_reg_n_0_[8][8] ;
wire \shifted_data_in_reg_n_0_[8][9] ;
wire [12:12]slaveRegDo_ff8;
wire [31:0]tc_config_cs_serial_input;
wire [31:0]tc_config_cs_serial_output;
wire [31:0]tc_config_cs_shift_en;
wire toggle;
wire toggle_rd;
wire [1:1]trace_data_ack;
wire \trace_data_ack_reg_n_0_[0] ;
wire [11:0]trace_read_addr;
wire trace_read_en;
wire trig_out_fsm;
wire trigger_i;
wire \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp ;
wire \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1 ;
wire \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp ;
wire \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1 ;
wire \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp ;
wire \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1 ;
wire u_ila_cap_ctrl_n_1;
wire u_ila_cap_ctrl_n_22;
wire u_ila_cap_ctrl_n_23;
wire u_ila_cap_ctrl_n_25;
wire u_ila_regs_n_35;
wire u_ila_regs_n_37;
wire u_ila_regs_n_41;
wire u_ila_regs_n_59;
wire u_ila_regs_n_60;
wire u_ila_regs_n_61;
wire u_ila_regs_n_90;
wire u_ila_regs_n_92;
wire u_ila_regs_n_93;
wire u_ila_regs_n_94;
wire u_ila_reset_ctrl_n_2;
wire u_ila_reset_ctrl_n_6;
wire u_ila_reset_ctrl_n_7;
wire u_trig_n_45;
wire u_trig_n_46;
wire use_probe_debug_circuit;
wire use_probe_debug_circuit_1;
wire use_probe_debug_circuit_2;
wire xsdb_memory_read_inst_n_16;
wire xsdb_memory_read_inst_n_17;
wire xsdb_memory_read_inst_n_18;
wire xsdb_memory_read_inst_n_19;
wire xsdb_memory_read_inst_n_20;
wire xsdb_memory_read_inst_n_21;
wire xsdb_memory_read_inst_n_22;
wire xsdb_memory_read_inst_n_23;
wire xsdb_memory_read_inst_n_24;
wire xsdb_memory_read_inst_n_25;
wire xsdb_memory_read_inst_n_26;
wire xsdb_memory_read_inst_n_27;
wire \xsdb_reg[15]_i_2__0__0_n_0 ;
wire \xsdb_reg[15]_i_2__1__0_n_0 ;
wire \xsdb_reg[15]_i_2__5_n_0 ;
wire \xsdb_reg[15]_i_3__4_n_0 ;
wire \xsdb_reg[15]_i_4__0__0_n_0 ;
wire \xsdb_reg[15]_i_4__0_n_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_adv_trigger_sequencer \ADV_TRIG.u_adv_trig
(.A(trigger_i),
.ADDRA({address,u_trig_n_45}),
.\BRAM_DATA_reg[15] (BRAM_DATA_reg),
.\BRAM_DATA_reg[23] (CFG_BRAM_DATA),
.CAP_DONE_O_reg(u_ila_cap_ctrl_n_25),
.\CFG_DATA_O_reg[7] (CFG_BRAM_RD_DATA),
.CNT_CTRL(counter_ctrl),
.COUNTER_EQ(counter_out),
.E(toggle),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (u_ila_cap_ctrl_n_23),
.\I_YESLUT6.I_YES_OREG.O_reg_reg_0 (u_ila_cap_ctrl_n_1),
.\I_YESLUT6.I_YES_OREG.O_reg_reg_1 (u_ila_cap_ctrl_n_22),
.O_reg(O_reg),
.Q(reset[1:0]),
.SEQUENCER_STATE_O(SEQUENCER_STATE_O),
.\SEQUENCER_STATE_O_reg[11]_0 (\ADV_TRIG.u_adv_trig_n_6 ),
.\SEQUENCER_STATE_O_reg[11]_1 (\ADV_TRIG.u_adv_trig_n_7 ),
.\SEQUENCER_STATE_O_reg[11]_2 (\ADV_TRIG.u_adv_trig_n_8 ),
.S_DCLK_O(s_dclk),
.basic_trigger(basic_trigger),
.bram_en(bram_en),
.bram_rd_en(bram_rd_en),
.cap_done(cap_done),
.capture_fsm(capture_fsm),
.\current_state_reg[0]_0 (\ADV_TRIG.u_adv_trig_n_9 ),
.dout_reg1_reg(arm_status),
.dout_reg1_reg_0(u_ila_reset_ctrl_n_6),
.en_adv_trigger(en_adv_trigger),
.flag0_temp(flag0_temp),
.flag1_temp(flag1_temp),
.flag2_temp(flag2_temp),
.flag3_temp(flag3_temp),
.out(out),
.p_2_out(p_2_out),
.toggle_rd(toggle_rd),
.trig_out_fsm(trig_out_fsm),
.trigger_reg_0(\ADV_TRIG.u_adv_trig_n_18 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_fsm_memory_read \ADV_TRIG_MEM_READ.u_fsm_memory_read_inst
(.\CFG_BRAM_RD_DATA_reg[21] (CFG_BRAM_DATA),
.\CFG_BRAM_RD_DATA_reg[23] (CFG_BRAM_RD_DATA),
.D(config_fsm_data),
.E(toggle),
.\FSM_BRAM_ADDR_O_reg[0] (u_ila_regs_n_61),
.FSM_BRAM_CONFIG_DATA_I(config_fsm_data_rd),
.FSM_BRAM_EN_RB_O_reg(u_ila_regs_n_60),
.Q(BRAM_DATA_reg),
.S_DCLK_O(s_dclk),
.toggle_rd(toggle_rd));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_counter \COUNTER.u_count
(.CFG_CNT_DIN(cnt_config_cs_serial_output),
.CFG_CNT_DOUT(cnt_config_cs_serial_input),
.CNT_CTRL(counter_ctrl),
.COUNTER_EQ(counter_out),
.Q(reset[1:0]),
.S_DCLK_O(s_dclk),
.cnt_config_cs_shift_en(cnt_config_cs_shift_en),
.out(out),
.scnt_reset(scnt_reset));
LUT2 #(
.INIT(4'h7))
\I_EN_CTL_EQ1.temp_en_i_2
(.I0(s_daddr[10]),
.I1(s_daddr[11]),
.O(\I_EN_CTL_EQ1.temp_en_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0002))
adv_drdy_i_1
(.I0(s_den),
.I1(u_ila_regs_n_41),
.I2(s_daddr[1]),
.I3(u_ila_regs_n_90),
.I4(adv_drdy),
.O(adv_drdy_i_1_n_0));
FDRE basic_trigger_reg
(.C(out),
.CE(1'b1),
.D(u_trig_n_46),
.Q(basic_trigger),
.R(1'b0));
LUT2 #(
.INIT(4'h6))
count_tt_i_1
(.I0(slaveRegDo_ff8),
.I1(count_tt),
.O(count_tt_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair222" *)
LUT5 #(
.INIT(32'hFFFFFBFF))
\current_state[1]_i_2
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[3]),
.I3(s_daddr[2]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair223" *)
LUT5 #(
.INIT(32'hFFFFFEFF))
\current_state[1]_i_2__0
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[3]),
.I3(s_daddr[2]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair223" *)
LUT5 #(
.INIT(32'hFFFFFBFF))
\current_state[1]_i_2__1
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[2]),
.I3(s_daddr[3]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair222" *)
LUT5 #(
.INIT(32'hFFFFFEFF))
\current_state[1]_i_2__2
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[2]),
.I3(s_daddr[3]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF7FFFFFF))
\current_state[1]_i_2__3
(.I0(s_daddr[12]),
.I1(s_den),
.I2(s_daddr[11]),
.I3(s_daddr[10]),
.I4(s_daddr[0]),
.I5(s_daddr[1]),
.O(\current_state[1]_i_2__3_n_0 ));
LUT6 #(
.INIT(64'hF7FFFFFFFFFFFFFF))
\current_state[1]_i_2__4
(.I0(s_daddr[12]),
.I1(s_den),
.I2(s_daddr[11]),
.I3(s_daddr[10]),
.I4(s_daddr[1]),
.I5(s_daddr[0]),
.O(\current_state[1]_i_2__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair224" *)
LUT5 #(
.INIT(32'hFFFFBFFF))
\current_state[1]_i_2__5
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[3]),
.I3(s_daddr[2]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair224" *)
LUT5 #(
.INIT(32'hFFFFEFFF))
\current_state[1]_i_2__6
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[3]),
.I3(s_daddr[2]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair225" *)
LUT5 #(
.INIT(32'hFFFFFFFB))
\current_state[1]_i_2__7
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[2]),
.I3(s_daddr[3]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF7FFFFFF))
\current_state[1]_i_2__8
(.I0(s_daddr[12]),
.I1(s_den),
.I2(s_daddr[11]),
.I3(s_daddr[10]),
.I4(s_daddr[1]),
.I5(s_daddr[0]),
.O(\current_state[1]_i_2__8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFF7FF))
\current_state[1]_i_2__9
(.I0(s_daddr[12]),
.I1(s_den),
.I2(s_daddr[11]),
.I3(s_daddr[10]),
.I4(s_daddr[1]),
.I5(s_daddr[0]),
.O(\current_state[1]_i_2__9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair225" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\current_state[1]_i_3
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[2]),
.I3(s_daddr[3]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair227" *)
LUT4 #(
.INIT(16'hFFFE))
\current_state[1]_i_4
(.I0(s_daddr[7]),
.I1(s_daddr[6]),
.I2(s_daddr[9]),
.I3(s_daddr[8]),
.O(\current_state[1]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair226" *)
LUT4 #(
.INIT(16'hEFFF))
\current_state[3]_i_5__0
(.I0(s_daddr[11]),
.I1(s_daddr[10]),
.I2(s_den),
.I3(s_daddr[12]),
.O(\current_state[3]_i_5__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair226" *)
LUT4 #(
.INIT(16'hDFFF))
\current_state[3]_i_5__0__0
(.I0(s_daddr[11]),
.I1(s_daddr[10]),
.I2(s_den),
.I3(s_daddr[12]),
.O(\current_state[3]_i_5__0__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair229" *)
LUT2 #(
.INIT(4'hB))
drdy_ffa_i_2
(.I0(s_daddr[0]),
.I1(s_daddr[1]),
.O(drdy_ffa_i_2_n_0));
FDRE en_adv_trigger_2_reg
(.C(out),
.CE(1'b1),
.D(en_adv_trigger_1),
.Q(en_adv_trigger_2),
.R(1'b0));
FDRE en_adv_trigger_reg
(.C(out),
.CE(1'b1),
.D(en_adv_trigger_2),
.Q(en_adv_trigger),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trace_memory ila_trace_memory_inst
(.ADDRBWRADDR(xsdb_memory_read_inst_n_27),
.CAP_TRIGGER_O_reg({cap_trigger_out,\shifted_data_in_reg_n_0_[8][51] ,\shifted_data_in_reg_n_0_[8][50] ,\shifted_data_in_reg_n_0_[8][49] ,\shifted_data_in_reg_n_0_[8][48] ,\shifted_data_in_reg_n_0_[8][47] ,\shifted_data_in_reg_n_0_[8][46] ,\shifted_data_in_reg_n_0_[8][45] }),
.CAP_WR_EN_O_reg(cap_wr_en),
.D(\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/din_2D[7]__0 ),
.DIADI({\shifted_data_in_reg_n_0_[8][7] ,\shifted_data_in_reg_n_0_[8][6] ,\shifted_data_in_reg_n_0_[8][5] ,\shifted_data_in_reg_n_0_[8][4] ,\shifted_data_in_reg_n_0_[8][3] ,\shifted_data_in_reg_n_0_[8][2] ,\shifted_data_in_reg_n_0_[8][1] ,\shifted_data_in_reg_n_0_[8][0] }),
.DIPADIP(\shifted_data_in_reg_n_0_[8][8] ),
.E(trace_read_en),
.Q({sel_i,trace_read_addr}),
.S_DCLK_O(s_dclk),
.enb_array(\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ),
.\i_intcap.CAP_ADDR_O_reg[14] (cap_wr_addr),
.out(out),
.\read_addr_reg[11]_rep ({xsdb_memory_read_inst_n_16,xsdb_memory_read_inst_n_17,xsdb_memory_read_inst_n_18,xsdb_memory_read_inst_n_19,xsdb_memory_read_inst_n_20,xsdb_memory_read_inst_n_21,xsdb_memory_read_inst_n_22,xsdb_memory_read_inst_n_23,xsdb_memory_read_inst_n_24,xsdb_memory_read_inst_n_25,xsdb_memory_read_inst_n_26}),
.\shifted_data_in_reg[8][16] ({\shifted_data_in_reg_n_0_[8][16] ,\shifted_data_in_reg_n_0_[8][15] ,\shifted_data_in_reg_n_0_[8][14] ,\shifted_data_in_reg_n_0_[8][13] ,\shifted_data_in_reg_n_0_[8][12] ,\shifted_data_in_reg_n_0_[8][11] ,\shifted_data_in_reg_n_0_[8][10] ,\shifted_data_in_reg_n_0_[8][9] }),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg_n_0_[8][17] ),
.\shifted_data_in_reg[8][25] ({\shifted_data_in_reg_n_0_[8][25] ,\shifted_data_in_reg_n_0_[8][24] ,\shifted_data_in_reg_n_0_[8][23] ,\shifted_data_in_reg_n_0_[8][22] ,\shifted_data_in_reg_n_0_[8][21] ,\shifted_data_in_reg_n_0_[8][20] ,\shifted_data_in_reg_n_0_[8][19] ,\shifted_data_in_reg_n_0_[8][18] }),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg_n_0_[8][26] ),
.\shifted_data_in_reg[8][34] ({\shifted_data_in_reg_n_0_[8][34] ,\shifted_data_in_reg_n_0_[8][33] ,\shifted_data_in_reg_n_0_[8][32] ,\shifted_data_in_reg_n_0_[8][31] ,\shifted_data_in_reg_n_0_[8][30] ,\shifted_data_in_reg_n_0_[8][29] ,\shifted_data_in_reg_n_0_[8][28] ,\shifted_data_in_reg_n_0_[8][27] }),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg_n_0_[8][35] ),
.\shifted_data_in_reg[8][43] ({\shifted_data_in_reg_n_0_[8][43] ,\shifted_data_in_reg_n_0_[8][42] ,\shifted_data_in_reg_n_0_[8][41] ,\shifted_data_in_reg_n_0_[8][40] ,\shifted_data_in_reg_n_0_[8][39] ,\shifted_data_in_reg_n_0_[8][38] ,\shifted_data_in_reg_n_0_[8][37] ,\shifted_data_in_reg_n_0_[8][36] }),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg_n_0_[8][44] ));
(* SOFT_HLUTNM = "soft_lutpair230" *)
LUT3 #(
.INIT(8'hAC))
\probeDelay1[0]_i_1
(.I0(debug_data_in[0]),
.I1(probe0),
.I2(use_probe_debug_circuit),
.O(probe_data[0]));
(* SOFT_HLUTNM = "soft_lutpair230" *)
LUT3 #(
.INIT(8'hAC))
\probeDelay1[0]_i_1__0
(.I0(debug_data_in[1]),
.I1(probe1),
.I2(use_probe_debug_circuit),
.O(probe_data[1]));
(* SOFT_HLUTNM = "soft_lutpair231" *)
LUT2 #(
.INIT(4'h2))
\probeDelay1[0]_i_1__1
(.I0(probe4),
.I1(use_probe_debug_circuit),
.O(probe_data[34]));
(* SOFT_HLUTNM = "soft_lutpair231" *)
LUT2 #(
.INIT(4'h2))
\probeDelay1[0]_i_1__2
(.I0(probe5),
.I1(use_probe_debug_circuit),
.O(probe_data[35]));
LUT2 #(
.INIT(4'h2))
\probeDelay1[0]_i_1__3
(.I0(probe7),
.I1(use_probe_debug_circuit),
.O(probe_data[49]));
LUT5 #(
.INIT(32'hFFFF22F2))
\shift_reg0[8]_i_1
(.I0(u_ila_regs_n_35),
.I1(drdy_ff9),
.I2(u_ila_regs_n_93),
.I3(u_ila_regs_n_92),
.I4(s_rst),
.O(\shift_reg0[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFF22F2))
\shift_reg1[15]_i_1
(.I0(u_ila_regs_n_37),
.I1(drdy_ffa),
.I2(u_ila_regs_n_59),
.I3(u_ila_regs_n_94),
.I4(s_rst),
.O(\shift_reg1[15]_i_1_n_0 ));
FDRE \shifted_data_in_reg[0][10]
(.C(out),
.CE(1'b1),
.D(probe2[8]),
.Q(\shifted_data_in_reg_n_0_[0][10] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][11]
(.C(out),
.CE(1'b1),
.D(probe2[9]),
.Q(\shifted_data_in_reg_n_0_[0][11] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][12]
(.C(out),
.CE(1'b1),
.D(probe2[10]),
.Q(\shifted_data_in_reg_n_0_[0][12] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][13]
(.C(out),
.CE(1'b1),
.D(probe2[11]),
.Q(\shifted_data_in_reg_n_0_[0][13] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][14]
(.C(out),
.CE(1'b1),
.D(probe2[12]),
.Q(\shifted_data_in_reg_n_0_[0][14] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][15]
(.C(out),
.CE(1'b1),
.D(probe2[13]),
.Q(\shifted_data_in_reg_n_0_[0][15] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][16]
(.C(out),
.CE(1'b1),
.D(probe2[14]),
.Q(\shifted_data_in_reg_n_0_[0][16] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][17]
(.C(out),
.CE(1'b1),
.D(probe2[15]),
.Q(\shifted_data_in_reg_n_0_[0][17] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][18]
(.C(out),
.CE(1'b1),
.D(probe3[0]),
.Q(\shifted_data_in_reg_n_0_[0][18] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][19]
(.C(out),
.CE(1'b1),
.D(probe3[1]),
.Q(\shifted_data_in_reg_n_0_[0][19] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][20]
(.C(out),
.CE(1'b1),
.D(probe3[2]),
.Q(\shifted_data_in_reg_n_0_[0][20] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][21]
(.C(out),
.CE(1'b1),
.D(probe3[3]),
.Q(\shifted_data_in_reg_n_0_[0][21] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][22]
(.C(out),
.CE(1'b1),
.D(probe3[4]),
.Q(\shifted_data_in_reg_n_0_[0][22] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][23]
(.C(out),
.CE(1'b1),
.D(probe3[5]),
.Q(\shifted_data_in_reg_n_0_[0][23] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][24]
(.C(out),
.CE(1'b1),
.D(probe3[6]),
.Q(\shifted_data_in_reg_n_0_[0][24] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][25]
(.C(out),
.CE(1'b1),
.D(probe3[7]),
.Q(\shifted_data_in_reg_n_0_[0][25] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][26]
(.C(out),
.CE(1'b1),
.D(probe3[8]),
.Q(\shifted_data_in_reg_n_0_[0][26] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][27]
(.C(out),
.CE(1'b1),
.D(probe3[9]),
.Q(\shifted_data_in_reg_n_0_[0][27] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][28]
(.C(out),
.CE(1'b1),
.D(probe3[10]),
.Q(\shifted_data_in_reg_n_0_[0][28] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][29]
(.C(out),
.CE(1'b1),
.D(probe3[11]),
.Q(\shifted_data_in_reg_n_0_[0][29] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][2]
(.C(out),
.CE(1'b1),
.D(probe2[0]),
.Q(\shifted_data_in_reg_n_0_[0][2] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][30]
(.C(out),
.CE(1'b1),
.D(probe3[12]),
.Q(\shifted_data_in_reg_n_0_[0][30] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][31]
(.C(out),
.CE(1'b1),
.D(probe3[13]),
.Q(\shifted_data_in_reg_n_0_[0][31] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][32]
(.C(out),
.CE(1'b1),
.D(probe3[14]),
.Q(\shifted_data_in_reg_n_0_[0][32] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][33]
(.C(out),
.CE(1'b1),
.D(probe3[15]),
.Q(\shifted_data_in_reg_n_0_[0][33] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][36]
(.C(out),
.CE(1'b1),
.D(probe6[0]),
.Q(\shifted_data_in_reg_n_0_[0][36] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][37]
(.C(out),
.CE(1'b1),
.D(probe6[1]),
.Q(\shifted_data_in_reg_n_0_[0][37] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][38]
(.C(out),
.CE(1'b1),
.D(probe6[2]),
.Q(\shifted_data_in_reg_n_0_[0][38] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][39]
(.C(out),
.CE(1'b1),
.D(probe6[3]),
.Q(\shifted_data_in_reg_n_0_[0][39] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][3]
(.C(out),
.CE(1'b1),
.D(probe2[1]),
.Q(\shifted_data_in_reg_n_0_[0][3] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][40]
(.C(out),
.CE(1'b1),
.D(probe6[4]),
.Q(\shifted_data_in_reg_n_0_[0][40] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][41]
(.C(out),
.CE(1'b1),
.D(probe6[5]),
.Q(\shifted_data_in_reg_n_0_[0][41] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][42]
(.C(out),
.CE(1'b1),
.D(probe6[6]),
.Q(\shifted_data_in_reg_n_0_[0][42] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][43]
(.C(out),
.CE(1'b1),
.D(probe6[7]),
.Q(\shifted_data_in_reg_n_0_[0][43] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][44]
(.C(out),
.CE(1'b1),
.D(probe6[8]),
.Q(\shifted_data_in_reg_n_0_[0][44] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][45]
(.C(out),
.CE(1'b1),
.D(probe6[9]),
.Q(\shifted_data_in_reg_n_0_[0][45] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][46]
(.C(out),
.CE(1'b1),
.D(probe6[10]),
.Q(\shifted_data_in_reg_n_0_[0][46] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][47]
(.C(out),
.CE(1'b1),
.D(probe6[11]),
.Q(\shifted_data_in_reg_n_0_[0][47] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][48]
(.C(out),
.CE(1'b1),
.D(probe6[12]),
.Q(\shifted_data_in_reg_n_0_[0][48] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][4]
(.C(out),
.CE(1'b1),
.D(probe2[2]),
.Q(\shifted_data_in_reg_n_0_[0][4] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][50]
(.C(out),
.CE(1'b1),
.D(probe8[0]),
.Q(\shifted_data_in_reg_n_0_[0][50] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][51]
(.C(out),
.CE(1'b1),
.D(probe8[1]),
.Q(\shifted_data_in_reg_n_0_[0][51] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][5]
(.C(out),
.CE(1'b1),
.D(probe2[3]),
.Q(\shifted_data_in_reg_n_0_[0][5] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][6]
(.C(out),
.CE(1'b1),
.D(probe2[4]),
.Q(\shifted_data_in_reg_n_0_[0][6] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][7]
(.C(out),
.CE(1'b1),
.D(probe2[5]),
.Q(\shifted_data_in_reg_n_0_[0][7] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][8]
(.C(out),
.CE(1'b1),
.D(probe2[6]),
.Q(\shifted_data_in_reg_n_0_[0][8] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][9]
(.C(out),
.CE(1'b1),
.D(probe2[7]),
.Q(\shifted_data_in_reg_n_0_[0][9] ),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][0]_srl8 " *)
SRL16E \shifted_data_in_reg[7][0]_srl8
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(probe0),
.Q(\shifted_data_in_reg[7][0]_srl8_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][10]_srl7 " *)
SRL16E \shifted_data_in_reg[7][10]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][10] ),
.Q(\shifted_data_in_reg[7][10]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][11]_srl7 " *)
SRL16E \shifted_data_in_reg[7][11]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][11] ),
.Q(\shifted_data_in_reg[7][11]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][12]_srl7 " *)
SRL16E \shifted_data_in_reg[7][12]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][12] ),
.Q(\shifted_data_in_reg[7][12]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][13]_srl7 " *)
SRL16E \shifted_data_in_reg[7][13]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][13] ),
.Q(\shifted_data_in_reg[7][13]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][14]_srl7 " *)
SRL16E \shifted_data_in_reg[7][14]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][14] ),
.Q(\shifted_data_in_reg[7][14]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][15]_srl7 " *)
SRL16E \shifted_data_in_reg[7][15]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][15] ),
.Q(\shifted_data_in_reg[7][15]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][16]_srl7 " *)
SRL16E \shifted_data_in_reg[7][16]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][16] ),
.Q(\shifted_data_in_reg[7][16]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][17]_srl7 " *)
SRL16E \shifted_data_in_reg[7][17]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][17] ),
.Q(\shifted_data_in_reg[7][17]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][18]_srl7 " *)
SRL16E \shifted_data_in_reg[7][18]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][18] ),
.Q(\shifted_data_in_reg[7][18]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][19]_srl7 " *)
SRL16E \shifted_data_in_reg[7][19]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][19] ),
.Q(\shifted_data_in_reg[7][19]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][1]_srl8 " *)
SRL16E \shifted_data_in_reg[7][1]_srl8
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(probe1),
.Q(\shifted_data_in_reg[7][1]_srl8_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][20]_srl7 " *)
SRL16E \shifted_data_in_reg[7][20]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][20] ),
.Q(\shifted_data_in_reg[7][20]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][21]_srl7 " *)
SRL16E \shifted_data_in_reg[7][21]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][21] ),
.Q(\shifted_data_in_reg[7][21]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][22]_srl7 " *)
SRL16E \shifted_data_in_reg[7][22]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][22] ),
.Q(\shifted_data_in_reg[7][22]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][23]_srl7 " *)
SRL16E \shifted_data_in_reg[7][23]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][23] ),
.Q(\shifted_data_in_reg[7][23]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][24]_srl7 " *)
SRL16E \shifted_data_in_reg[7][24]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][24] ),
.Q(\shifted_data_in_reg[7][24]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][25]_srl7 " *)
SRL16E \shifted_data_in_reg[7][25]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][25] ),
.Q(\shifted_data_in_reg[7][25]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][26]_srl7 " *)
SRL16E \shifted_data_in_reg[7][26]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][26] ),
.Q(\shifted_data_in_reg[7][26]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][27]_srl7 " *)
SRL16E \shifted_data_in_reg[7][27]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][27] ),
.Q(\shifted_data_in_reg[7][27]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][28]_srl7 " *)
SRL16E \shifted_data_in_reg[7][28]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][28] ),
.Q(\shifted_data_in_reg[7][28]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][29]_srl7 " *)
SRL16E \shifted_data_in_reg[7][29]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][29] ),
.Q(\shifted_data_in_reg[7][29]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][2]_srl7 " *)
SRL16E \shifted_data_in_reg[7][2]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][2] ),
.Q(\shifted_data_in_reg[7][2]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][30]_srl7 " *)
SRL16E \shifted_data_in_reg[7][30]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][30] ),
.Q(\shifted_data_in_reg[7][30]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][31]_srl7 " *)
SRL16E \shifted_data_in_reg[7][31]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][31] ),
.Q(\shifted_data_in_reg[7][31]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][32]_srl7 " *)
SRL16E \shifted_data_in_reg[7][32]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][32] ),
.Q(\shifted_data_in_reg[7][32]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][33]_srl7 " *)
SRL16E \shifted_data_in_reg[7][33]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][33] ),
.Q(\shifted_data_in_reg[7][33]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][34]_srl8 " *)
SRL16E \shifted_data_in_reg[7][34]_srl8
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(probe4),
.Q(\shifted_data_in_reg[7][34]_srl8_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][35]_srl8 " *)
SRL16E \shifted_data_in_reg[7][35]_srl8
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(probe5),
.Q(\shifted_data_in_reg[7][35]_srl8_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][36]_srl7 " *)
SRL16E \shifted_data_in_reg[7][36]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][36] ),
.Q(\shifted_data_in_reg[7][36]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][37]_srl7 " *)
SRL16E \shifted_data_in_reg[7][37]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][37] ),
.Q(\shifted_data_in_reg[7][37]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][38]_srl7 " *)
SRL16E \shifted_data_in_reg[7][38]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][38] ),
.Q(\shifted_data_in_reg[7][38]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][39]_srl7 " *)
SRL16E \shifted_data_in_reg[7][39]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][39] ),
.Q(\shifted_data_in_reg[7][39]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][3]_srl7 " *)
SRL16E \shifted_data_in_reg[7][3]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][3] ),
.Q(\shifted_data_in_reg[7][3]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][40]_srl7 " *)
SRL16E \shifted_data_in_reg[7][40]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][40] ),
.Q(\shifted_data_in_reg[7][40]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][41]_srl7 " *)
SRL16E \shifted_data_in_reg[7][41]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][41] ),
.Q(\shifted_data_in_reg[7][41]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][42]_srl7 " *)
SRL16E \shifted_data_in_reg[7][42]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][42] ),
.Q(\shifted_data_in_reg[7][42]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][43]_srl7 " *)
SRL16E \shifted_data_in_reg[7][43]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][43] ),
.Q(\shifted_data_in_reg[7][43]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][44]_srl7 " *)
SRL16E \shifted_data_in_reg[7][44]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][44] ),
.Q(\shifted_data_in_reg[7][44]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][45]_srl7 " *)
SRL16E \shifted_data_in_reg[7][45]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][45] ),
.Q(\shifted_data_in_reg[7][45]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][46]_srl7 " *)
SRL16E \shifted_data_in_reg[7][46]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][46] ),
.Q(\shifted_data_in_reg[7][46]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][47]_srl7 " *)
SRL16E \shifted_data_in_reg[7][47]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][47] ),
.Q(\shifted_data_in_reg[7][47]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][48]_srl7 " *)
SRL16E \shifted_data_in_reg[7][48]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][48] ),
.Q(\shifted_data_in_reg[7][48]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][49]_srl8 " *)
SRL16E \shifted_data_in_reg[7][49]_srl8
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(probe7),
.Q(\shifted_data_in_reg[7][49]_srl8_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][4]_srl7 " *)
SRL16E \shifted_data_in_reg[7][4]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][4] ),
.Q(\shifted_data_in_reg[7][4]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][50]_srl7 " *)
SRL16E \shifted_data_in_reg[7][50]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][50] ),
.Q(\shifted_data_in_reg[7][50]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][51]_srl7 " *)
SRL16E \shifted_data_in_reg[7][51]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][51] ),
.Q(\shifted_data_in_reg[7][51]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][5]_srl7 " *)
SRL16E \shifted_data_in_reg[7][5]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][5] ),
.Q(\shifted_data_in_reg[7][5]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][6]_srl7 " *)
SRL16E \shifted_data_in_reg[7][6]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][6] ),
.Q(\shifted_data_in_reg[7][6]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][7]_srl7 " *)
SRL16E \shifted_data_in_reg[7][7]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][7] ),
.Q(\shifted_data_in_reg[7][7]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][8]_srl7 " *)
SRL16E \shifted_data_in_reg[7][8]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][8] ),
.Q(\shifted_data_in_reg[7][8]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][9]_srl7 " *)
SRL16E \shifted_data_in_reg[7][9]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][9] ),
.Q(\shifted_data_in_reg[7][9]_srl7_n_0 ));
FDRE \shifted_data_in_reg[8][0]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][0]_srl8_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][0] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][10]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][10]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][10] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][11]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][11]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][11] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][12]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][12]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][12] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][13]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][13]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][13] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][14]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][14]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][14] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][15]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][15]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][15] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][16]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][16]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][16] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][17]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][17]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][17] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][18]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][18]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][18] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][19]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][19]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][19] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][1]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][1]_srl8_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][1] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][20]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][20]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][20] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][21]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][21]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][21] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][22]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][22]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][22] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][23]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][23]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][23] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][24]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][24]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][24] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][25]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][25]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][25] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][26]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][26]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][26] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][27]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][27]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][27] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][28]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][28]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][28] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][29]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][29]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][29] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][2]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][2]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][2] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][30]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][30]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][30] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][31]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][31]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][31] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][32]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][32]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][32] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][33]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][33]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][33] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][34]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][34]_srl8_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][34] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][35]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][35]_srl8_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][35] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][36]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][36]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][36] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][37]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][37]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][37] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][38]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][38]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][38] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][39]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][39]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][39] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][3]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][3]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][3] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][40]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][40]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][40] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][41]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][41]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][41] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][42]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][42]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][42] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][43]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][43]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][43] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][44]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][44]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][44] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][45]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][45]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][45] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][46]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][46]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][46] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][47]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][47]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][47] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][48]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][48]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][48] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][49]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][49]_srl8_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][49] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][4]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][4]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][4] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][50]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][50]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][50] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][51]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][51]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][51] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][5]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][5]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][5] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][6]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][6]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][6] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][7]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][7]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][7] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][8]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][8]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][8] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][9]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][9]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][9] ),
.R(1'b0));
FDRE \trace_data_ack_reg[0]
(.C(s_dclk),
.CE(1'b1),
.D(trace_read_en),
.Q(\trace_data_ack_reg_n_0_[0] ),
.R(1'b0));
FDRE \trace_data_ack_reg[1]
(.C(s_dclk),
.CE(1'b1),
.D(\trace_data_ack_reg_n_0_[0] ),
.Q(trace_data_ack),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_ctrl_legacy u_ila_cap_ctrl
(.A(trigger_i),
.D(capture_ctrl_config_cs_serial_input),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (cap_wr_addr),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (cap_wr_en),
.DOUT_O(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1 ),
.E(capture_ctrl_config_en),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\ADV_TRIG.u_adv_trig_n_18 ),
.O_reg(O_reg),
.Q(reset[1:0]),
.S_DCLK_O(s_dclk),
.TRIGGERED_SL_I(cap_trigger_out),
.basic_trigger(basic_trigger),
.cap_done(cap_done),
.capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
.capture_fsm(capture_fsm),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.capture_strg_qual(capture_strg_qual),
.\current_state_reg[0] (u_ila_cap_ctrl_n_22),
.\current_state_reg[0]_0 (u_ila_cap_ctrl_n_23),
.dout_reg1_reg(arm_status),
.en_adv_trigger(en_adv_trigger),
.out(out),
.p_2_out(p_2_out),
.\reset_out_reg[0] (u_ila_reset_ctrl_n_7),
.scnt_cmp_temp(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp ),
.scnt_reset(scnt_reset),
.trig_out_fsm(trig_out_fsm),
.trigger_reg(u_ila_cap_ctrl_n_25),
.u_wcnt_hcmp_q(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1 ),
.u_wcnt_lcmp_q(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1 ),
.wcnt_hcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp ),
.wcnt_lcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp ),
.\xsdb_reg_reg[0] (u_ila_cap_ctrl_n_1),
.\xsdb_reg_reg[14] (capture_cnt));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_register u_ila_regs
(.CAP_DONE_O_reg({cap_done,cap_trigger_out,halt_status,arm_status}),
.CFG_CNT_DIN(cnt_config_cs_serial_output),
.CFG_CNT_DOUT(cnt_config_cs_serial_input),
.\CFG_DATA_O_reg[15] (config_fsm_data_rd),
.D(config_fsm_data),
.DOUT_O(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1 ),
.DUMMY_I(DUMMY_I),
.E(data_out_en),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\xsdb_reg[15]_i_2__0__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 (drdy_ffa_i_2_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[10] (\I_EN_CTL_EQ1.temp_en_i_2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\xsdb_reg[15]_i_2__1__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[11]_0 (\current_state[3]_i_5__0__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[11]_1 (\current_state[3]_i_5__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\current_state[1]_i_2__9_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 (\current_state[1]_i_2__3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 (\current_state[1]_i_2__8_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 (\current_state[1]_i_2__4_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\xsdb_reg[15]_i_4__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\xsdb_reg[15]_i_4__0__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\xsdb_reg[15]_i_2__5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 (\current_state[1]_i_2__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 (\current_state[1]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 (\current_state[1]_i_2__2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 (\current_state[1]_i_2__6_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 (\current_state[1]_i_2__7_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 (\current_state[1]_i_2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 (\current_state[1]_i_2__1_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 (\current_state[1]_i_2__5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\xsdb_reg[15]_i_3__4_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\current_state[1]_i_4_n_0 ),
.\G_1PIPE_IFACE.s_den_r_reg (adv_drdy_i_1_n_0),
.\I_EN_CTL_EQ1.temp_en_reg (u_ila_regs_n_41),
.\I_YESLUT6.I_YES_OREG.O_reg_reg ({O_reg,u_ila_cap_ctrl_n_1}),
.SEQUENCER_STATE_O(SEQUENCER_STATE_O),
.SL_IPORT_I(SL_IPORT_I),
.SL_OPORT_O(SL_OPORT_O),
.SR(read_addr_reset),
.adv_drdy(adv_drdy),
.arm_ctrl(arm_ctrl),
.bram_en(bram_en),
.bram_rd_en(bram_rd_en),
.capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.\captured_samples_reg[14] (capture_cnt),
.cnt_config_cs_shift_en(cnt_config_cs_shift_en),
.count_tt(count_tt),
.count_tt_reg_0(count_tt_i_1_n_0),
.debug_data_in(debug_data_in),
.drdy_ff9(drdy_ff9),
.drdy_ffa(drdy_ffa),
.en_adv_trigger(en_adv_trigger),
.en_adv_trigger_1(en_adv_trigger_1),
.flag0_temp(flag0_temp),
.flag1_temp(flag1_temp),
.flag2_temp(flag2_temp),
.flag3_temp(flag3_temp),
.halt_ctrl(halt_ctrl),
.\input_data_reg[31] (data_word_out),
.mu_config_cs_serial_input({mu_config_cs_serial_input[15:14],mu_config_cs_serial_input[11:8],mu_config_cs_serial_input[3:0]}),
.mu_config_cs_serial_output({mu_config_cs_serial_output[15:14],mu_config_cs_serial_output[11:8],mu_config_cs_serial_output[3:0]}),
.mu_config_cs_shift_en({mu_config_cs_shift_en[15:14],mu_config_cs_shift_en[11:8],mu_config_cs_shift_en[3:0]}),
.\parallel_dout_reg[0] (qual_strg_config_cs_shift_en),
.\parallel_dout_reg[0]_0 (capture_ctrl_config_en),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.read_data_en(read_data_en),
.read_reset_addr(read_reset_addr),
.regDrdy_reg_0(u_ila_regs_n_90),
.s_daddr_o(s_daddr),
.s_dclk_o(s_dclk),
.s_den_o(s_den),
.s_dwe_o(s_dwe),
.s_rst_o(s_rst),
.scnt_cmp_temp(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp ),
.shift_en_reg(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1 ),
.shift_en_reg_0(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1 ),
.shift_en_reg_1(qual_strg_config_cs_serial_input),
.shift_en_reg_2(capture_ctrl_config_cs_serial_input),
.\shift_reg0_reg[8]_0 (u_ila_regs_n_92),
.\shift_reg0_reg[8]_1 (u_ila_regs_n_93),
.\shift_reg0_reg[8]_2 (\shift_reg0[8]_i_1_n_0 ),
.\shift_reg1_reg[15]_0 (u_ila_regs_n_59),
.\shift_reg1_reg[15]_1 (u_ila_regs_n_94),
.\shift_reg1_reg[15]_2 (\shift_reg1[15]_i_1_n_0 ),
.slaveRegDo_ff8(slaveRegDo_ff8),
.\slaveRegDo_ff9_reg[8]_0 (u_ila_regs_n_35),
.\slaveRegDo_ffa_reg[15]_0 (u_ila_regs_n_37),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en),
.toggle_rd(toggle_rd),
.toggle_rd_reg(u_ila_regs_n_60),
.toggle_reg(u_ila_regs_n_61),
.toggle_reg_0(toggle),
.use_probe_debug_circuit_1(use_probe_debug_circuit_1),
.wcnt_hcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp ),
.wcnt_lcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_reset_ctrl u_ila_reset_ctrl
(.\I_YESLUT6.I_YES_OREG.O_reg_reg (u_ila_cap_ctrl_n_1),
.Q({u_ila_reset_ctrl_n_2,reset[3],reset[1:0]}),
.\SEQUENCER_STATE_O_reg[8] (u_ila_reset_ctrl_n_6),
.arm_ctrl(arm_ctrl),
.cap_done(cap_done),
.\captured_samples_reg[0] (u_ila_reset_ctrl_n_7),
.\current_state_reg[3] (\ADV_TRIG.u_adv_trig_n_9 ),
.halt_ctrl(halt_ctrl),
.out(out),
.s_dclk_o(s_dclk),
.temp_reg0_reg({halt_status,arm_status}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trigger u_trig
(.ADDRA({address,u_trig_n_45}),
.Q({u_ila_reset_ctrl_n_2,reset[3],reset[0]}),
.basic_trigger_reg(u_trig_n_46),
.capture_strg_qual(capture_strg_qual),
.\current_state_reg[0] (\ADV_TRIG.u_adv_trig_n_6 ),
.\current_state_reg[1] (\ADV_TRIG.u_adv_trig_n_7 ),
.\current_state_reg[2] (\ADV_TRIG.u_adv_trig_n_8 ),
.\current_state_reg[3] (\ADV_TRIG.u_adv_trig_n_9 ),
.mu_config_cs_serial_input({mu_config_cs_serial_input[15:14],mu_config_cs_serial_input[11:8],mu_config_cs_serial_input[3:0]}),
.mu_config_cs_serial_output({mu_config_cs_serial_output[15:14],mu_config_cs_serial_output[11:8],mu_config_cs_serial_output[3:0]}),
.mu_config_cs_shift_en({mu_config_cs_shift_en[15:14],mu_config_cs_shift_en[11:8],mu_config_cs_shift_en[3:0]}),
.out(out),
.\parallel_dout_reg[15] (qual_strg_config_cs_serial_input),
.probe_data({probe_data[49],probe_data[35:34],probe_data[1:0]}),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.s_dclk_o(s_dclk),
.shift_en_reg(qual_strg_config_cs_shift_en),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE use_probe_debug_circuit_2_reg
(.C(out),
.CE(1'b1),
.D(use_probe_debug_circuit_1),
.Q(use_probe_debug_circuit_2),
.R(1'b0));
FDRE use_probe_debug_circuit_reg
(.C(out),
.CE(1'b1),
.D(use_probe_debug_circuit_2),
.Q(use_probe_debug_circuit),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_generic_memrd xsdb_memory_read_inst
(.ADDRBWRADDR(xsdb_memory_read_inst_n_27),
.D(\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/din_2D[7]__0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ({xsdb_memory_read_inst_n_16,xsdb_memory_read_inst_n_17,xsdb_memory_read_inst_n_18,xsdb_memory_read_inst_n_19,xsdb_memory_read_inst_n_20,xsdb_memory_read_inst_n_21,xsdb_memory_read_inst_n_22,xsdb_memory_read_inst_n_23,xsdb_memory_read_inst_n_24,xsdb_memory_read_inst_n_25,xsdb_memory_read_inst_n_26}),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (trace_read_en),
.E(data_out_en),
.Q({sel_i,trace_read_addr}),
.SR(read_addr_reset),
.enb_array(\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ),
.read_data_en(read_data_en),
.read_reset_addr(read_reset_addr),
.s_dclk_o(s_dclk),
.\trace_data_ack_reg[1] (trace_data_ack),
.\xsdb_reg_reg[15] (data_word_out));
(* SOFT_HLUTNM = "soft_lutpair229" *)
LUT4 #(
.INIT(16'h0100))
\xsdb_reg[15]_i_2__0__0
(.I0(s_daddr[0]),
.I1(s_daddr[1]),
.I2(s_daddr[2]),
.I3(\xsdb_reg[15]_i_2__1__0_n_0 ),
.O(\xsdb_reg[15]_i_2__0__0_n_0 ));
LUT6 #(
.INIT(64'h0001000000000000))
\xsdb_reg[15]_i_2__1__0
(.I0(s_daddr[11]),
.I1(s_daddr[12]),
.I2(s_daddr[9]),
.I3(s_daddr[10]),
.I4(s_dwe),
.I5(s_den),
.O(\xsdb_reg[15]_i_2__1__0_n_0 ));
LUT6 #(
.INIT(64'h0000000100000000))
\xsdb_reg[15]_i_2__5
(.I0(s_daddr[5]),
.I1(s_daddr[6]),
.I2(s_daddr[3]),
.I3(s_daddr[4]),
.I4(s_daddr[8]),
.I5(s_daddr[7]),
.O(\xsdb_reg[15]_i_2__5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair227" *)
LUT2 #(
.INIT(4'h1))
\xsdb_reg[15]_i_3__4
(.I0(s_daddr[7]),
.I1(s_daddr[8]),
.O(\xsdb_reg[15]_i_3__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair228" *)
LUT2 #(
.INIT(4'hE))
\xsdb_reg[15]_i_4__0
(.I0(s_daddr[2]),
.I1(s_daddr[3]),
.O(\xsdb_reg[15]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair228" *)
LUT4 #(
.INIT(16'h0001))
\xsdb_reg[15]_i_4__0__0
(.I0(s_daddr[4]),
.I1(s_daddr[3]),
.I2(s_daddr[6]),
.I3(s_daddr[5]),
.O(\xsdb_reg[15]_i_4__0__0_n_0 ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_core
(SL_OPORT_O,
out,
probe8,
probe7,
probe6,
probe5,
probe4,
probe3,
probe2,
probe1,
probe0,
SL_IPORT_I,
DUMMY_I); |
output [16:0]SL_OPORT_O;
input out;
input [1:0]probe8;
input [0:0]probe7;
input [12:0]probe6;
input [0:0]probe5;
input [0:0]probe4;
input [15:0]probe3;
input [15:0]probe2;
input [0:0]probe1;
input [0:0]probe0;
input [36:0]SL_IPORT_I;
input DUMMY_I;
wire \ADV_TRIG.u_adv_trig_n_18 ;
wire \ADV_TRIG.u_adv_trig_n_6 ;
wire \ADV_TRIG.u_adv_trig_n_7 ;
wire \ADV_TRIG.u_adv_trig_n_8 ;
wire \ADV_TRIG.u_adv_trig_n_9 ;
wire [15:0]BRAM_DATA_reg;
wire [23:16]CFG_BRAM_DATA;
wire [23:0]CFG_BRAM_RD_DATA;
wire DUMMY_I;
wire \I_EN_CTL_EQ1.temp_en_i_2_n_0 ;
wire O_reg;
wire [15:0]SEQUENCER_STATE_O;
wire [36:0]SL_IPORT_I;
wire [16:0]SL_OPORT_O;
wire [7:0]\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ;
wire [52:0]\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/din_2D[7]__0 ;
wire address;
wire adv_drdy;
wire adv_drdy_i_1_n_0;
wire arm_ctrl;
wire arm_status;
wire basic_trigger;
wire bram_en;
wire bram_rd_en;
wire cap_done;
wire cap_trigger_out;
wire [14:0]cap_wr_addr;
wire cap_wr_en;
wire [14:0]capture_cnt;
wire capture_ctrl_config_cs_serial_input;
wire capture_ctrl_config_en;
wire capture_ctrl_config_serial_output;
wire capture_fsm;
wire [1:0]capture_qual_ctrl_1;
wire capture_strg_qual;
wire [3:0]cnt_config_cs_serial_input;
wire [3:0]cnt_config_cs_serial_output;
wire [3:0]cnt_config_cs_shift_en;
wire [15:0]config_fsm_data;
wire [15:0]config_fsm_data_rd;
wire count_tt;
wire count_tt_i_1_n_0;
wire [7:0]counter_ctrl;
wire [3:0]counter_out;
wire \current_state[1]_i_2__0_n_0 ;
wire \current_state[1]_i_2__1_n_0 ;
wire \current_state[1]_i_2__2_n_0 ;
wire \current_state[1]_i_2__3_n_0 ;
wire \current_state[1]_i_2__4_n_0 ;
wire \current_state[1]_i_2__5_n_0 ;
wire \current_state[1]_i_2__6_n_0 ;
wire \current_state[1]_i_2__7_n_0 ;
wire \current_state[1]_i_2__8_n_0 ;
wire \current_state[1]_i_2__9_n_0 ;
wire \current_state[1]_i_2_n_0 ;
wire \current_state[1]_i_3_n_0 ;
wire \current_state[1]_i_4_n_0 ;
wire \current_state[3]_i_5__0__0_n_0 ;
wire \current_state[3]_i_5__0_n_0 ;
wire data_out_en;
wire [15:0]data_word_out;
wire [1:0]debug_data_in;
wire drdy_ff9;
wire drdy_ffa;
wire drdy_ffa_i_2_n_0;
wire en_adv_trigger;
wire en_adv_trigger_1;
wire en_adv_trigger_2;
wire flag0_temp;
wire flag1_temp;
wire flag2_temp;
wire flag3_temp;
wire halt_ctrl;
wire halt_status;
wire [15:0]mu_config_cs_serial_input;
wire [15:0]mu_config_cs_serial_output;
wire [15:0]mu_config_cs_shift_en;
wire out;
wire [15:15]p_2_out;
wire [0:0]probe0;
wire [0:0]probe1;
wire [15:0]probe2;
wire [15:0]probe3;
wire [0:0]probe4;
wire [0:0]probe5;
wire [12:0]probe6;
wire [0:0]probe7;
wire [1:0]probe8;
wire [49:0]probe_data;
wire qual_strg_config_cs_serial_input;
wire qual_strg_config_cs_serial_output;
wire qual_strg_config_cs_shift_en;
wire read_addr_reset;
wire read_data_en;
wire [14:0]read_reset_addr;
wire [3:0]reset;
wire [12:0]s_daddr;
wire s_dclk;
wire s_den;
wire s_dwe;
wire s_rst;
wire scnt_reset;
wire [2:0]sel_i;
wire \shift_reg0[8]_i_1_n_0 ;
wire \shift_reg1[15]_i_1_n_0 ;
wire \shifted_data_in_reg[7][0]_srl8_n_0 ;
wire \shifted_data_in_reg[7][10]_srl7_n_0 ;
wire \shifted_data_in_reg[7][11]_srl7_n_0 ;
wire \shifted_data_in_reg[7][12]_srl7_n_0 ;
wire \shifted_data_in_reg[7][13]_srl7_n_0 ;
wire \shifted_data_in_reg[7][14]_srl7_n_0 ;
wire \shifted_data_in_reg[7][15]_srl7_n_0 ;
wire \shifted_data_in_reg[7][16]_srl7_n_0 ;
wire \shifted_data_in_reg[7][17]_srl7_n_0 ;
wire \shifted_data_in_reg[7][18]_srl7_n_0 ;
wire \shifted_data_in_reg[7][19]_srl7_n_0 ;
wire \shifted_data_in_reg[7][1]_srl8_n_0 ;
wire \shifted_data_in_reg[7][20]_srl7_n_0 ;
wire \shifted_data_in_reg[7][21]_srl7_n_0 ;
wire \shifted_data_in_reg[7][22]_srl7_n_0 ;
wire \shifted_data_in_reg[7][23]_srl7_n_0 ;
wire \shifted_data_in_reg[7][24]_srl7_n_0 ;
wire \shifted_data_in_reg[7][25]_srl7_n_0 ;
wire \shifted_data_in_reg[7][26]_srl7_n_0 ;
wire \shifted_data_in_reg[7][27]_srl7_n_0 ;
wire \shifted_data_in_reg[7][28]_srl7_n_0 ;
wire \shifted_data_in_reg[7][29]_srl7_n_0 ;
wire \shifted_data_in_reg[7][2]_srl7_n_0 ;
wire \shifted_data_in_reg[7][30]_srl7_n_0 ;
wire \shifted_data_in_reg[7][31]_srl7_n_0 ;
wire \shifted_data_in_reg[7][32]_srl7_n_0 ;
wire \shifted_data_in_reg[7][33]_srl7_n_0 ;
wire \shifted_data_in_reg[7][34]_srl8_n_0 ;
wire \shifted_data_in_reg[7][35]_srl8_n_0 ;
wire \shifted_data_in_reg[7][36]_srl7_n_0 ;
wire \shifted_data_in_reg[7][37]_srl7_n_0 ;
wire \shifted_data_in_reg[7][38]_srl7_n_0 ;
wire \shifted_data_in_reg[7][39]_srl7_n_0 ;
wire \shifted_data_in_reg[7][3]_srl7_n_0 ;
wire \shifted_data_in_reg[7][40]_srl7_n_0 ;
wire \shifted_data_in_reg[7][41]_srl7_n_0 ;
wire \shifted_data_in_reg[7][42]_srl7_n_0 ;
wire \shifted_data_in_reg[7][43]_srl7_n_0 ;
wire \shifted_data_in_reg[7][44]_srl7_n_0 ;
wire \shifted_data_in_reg[7][45]_srl7_n_0 ;
wire \shifted_data_in_reg[7][46]_srl7_n_0 ;
wire \shifted_data_in_reg[7][47]_srl7_n_0 ;
wire \shifted_data_in_reg[7][48]_srl7_n_0 ;
wire \shifted_data_in_reg[7][49]_srl8_n_0 ;
wire \shifted_data_in_reg[7][4]_srl7_n_0 ;
wire \shifted_data_in_reg[7][50]_srl7_n_0 ;
wire \shifted_data_in_reg[7][51]_srl7_n_0 ;
wire \shifted_data_in_reg[7][5]_srl7_n_0 ;
wire \shifted_data_in_reg[7][6]_srl7_n_0 ;
wire \shifted_data_in_reg[7][7]_srl7_n_0 ;
wire \shifted_data_in_reg[7][8]_srl7_n_0 ;
wire \shifted_data_in_reg[7][9]_srl7_n_0 ;
wire \shifted_data_in_reg_n_0_[0][10] ;
wire \shifted_data_in_reg_n_0_[0][11] ;
wire \shifted_data_in_reg_n_0_[0][12] ;
wire \shifted_data_in_reg_n_0_[0][13] ;
wire \shifted_data_in_reg_n_0_[0][14] ;
wire \shifted_data_in_reg_n_0_[0][15] ;
wire \shifted_data_in_reg_n_0_[0][16] ;
wire \shifted_data_in_reg_n_0_[0][17] ;
wire \shifted_data_in_reg_n_0_[0][18] ;
wire \shifted_data_in_reg_n_0_[0][19] ;
wire \shifted_data_in_reg_n_0_[0][20] ;
wire \shifted_data_in_reg_n_0_[0][21] ;
wire \shifted_data_in_reg_n_0_[0][22] ;
wire \shifted_data_in_reg_n_0_[0][23] ;
wire \shifted_data_in_reg_n_0_[0][24] ;
wire \shifted_data_in_reg_n_0_[0][25] ;
wire \shifted_data_in_reg_n_0_[0][26] ;
wire \shifted_data_in_reg_n_0_[0][27] ;
wire \shifted_data_in_reg_n_0_[0][28] ;
wire \shifted_data_in_reg_n_0_[0][29] ;
wire \shifted_data_in_reg_n_0_[0][2] ;
wire \shifted_data_in_reg_n_0_[0][30] ;
wire \shifted_data_in_reg_n_0_[0][31] ;
wire \shifted_data_in_reg_n_0_[0][32] ;
wire \shifted_data_in_reg_n_0_[0][33] ;
wire \shifted_data_in_reg_n_0_[0][36] ;
wire \shifted_data_in_reg_n_0_[0][37] ;
wire \shifted_data_in_reg_n_0_[0][38] ;
wire \shifted_data_in_reg_n_0_[0][39] ;
wire \shifted_data_in_reg_n_0_[0][3] ;
wire \shifted_data_in_reg_n_0_[0][40] ;
wire \shifted_data_in_reg_n_0_[0][41] ;
wire \shifted_data_in_reg_n_0_[0][42] ;
wire \shifted_data_in_reg_n_0_[0][43] ;
wire \shifted_data_in_reg_n_0_[0][44] ;
wire \shifted_data_in_reg_n_0_[0][45] ;
wire \shifted_data_in_reg_n_0_[0][46] ;
wire \shifted_data_in_reg_n_0_[0][47] ;
wire \shifted_data_in_reg_n_0_[0][48] ;
wire \shifted_data_in_reg_n_0_[0][4] ;
wire \shifted_data_in_reg_n_0_[0][50] ;
wire \shifted_data_in_reg_n_0_[0][51] ;
wire \shifted_data_in_reg_n_0_[0][5] ;
wire \shifted_data_in_reg_n_0_[0][6] ;
wire \shifted_data_in_reg_n_0_[0][7] ;
wire \shifted_data_in_reg_n_0_[0][8] ;
wire \shifted_data_in_reg_n_0_[0][9] ;
wire \shifted_data_in_reg_n_0_[8][0] ;
wire \shifted_data_in_reg_n_0_[8][10] ;
wire \shifted_data_in_reg_n_0_[8][11] ;
wire \shifted_data_in_reg_n_0_[8][12] ;
wire \shifted_data_in_reg_n_0_[8][13] ;
wire \shifted_data_in_reg_n_0_[8][14] ;
wire \shifted_data_in_reg_n_0_[8][15] ;
wire \shifted_data_in_reg_n_0_[8][16] ;
wire \shifted_data_in_reg_n_0_[8][17] ;
wire \shifted_data_in_reg_n_0_[8][18] ;
wire \shifted_data_in_reg_n_0_[8][19] ;
wire \shifted_data_in_reg_n_0_[8][1] ;
wire \shifted_data_in_reg_n_0_[8][20] ;
wire \shifted_data_in_reg_n_0_[8][21] ;
wire \shifted_data_in_reg_n_0_[8][22] ;
wire \shifted_data_in_reg_n_0_[8][23] ;
wire \shifted_data_in_reg_n_0_[8][24] ;
wire \shifted_data_in_reg_n_0_[8][25] ;
wire \shifted_data_in_reg_n_0_[8][26] ;
wire \shifted_data_in_reg_n_0_[8][27] ;
wire \shifted_data_in_reg_n_0_[8][28] ;
wire \shifted_data_in_reg_n_0_[8][29] ;
wire \shifted_data_in_reg_n_0_[8][2] ;
wire \shifted_data_in_reg_n_0_[8][30] ;
wire \shifted_data_in_reg_n_0_[8][31] ;
wire \shifted_data_in_reg_n_0_[8][32] ;
wire \shifted_data_in_reg_n_0_[8][33] ;
wire \shifted_data_in_reg_n_0_[8][34] ;
wire \shifted_data_in_reg_n_0_[8][35] ;
wire \shifted_data_in_reg_n_0_[8][36] ;
wire \shifted_data_in_reg_n_0_[8][37] ;
wire \shifted_data_in_reg_n_0_[8][38] ;
wire \shifted_data_in_reg_n_0_[8][39] ;
wire \shifted_data_in_reg_n_0_[8][3] ;
wire \shifted_data_in_reg_n_0_[8][40] ;
wire \shifted_data_in_reg_n_0_[8][41] ;
wire \shifted_data_in_reg_n_0_[8][42] ;
wire \shifted_data_in_reg_n_0_[8][43] ;
wire \shifted_data_in_reg_n_0_[8][44] ;
wire \shifted_data_in_reg_n_0_[8][45] ;
wire \shifted_data_in_reg_n_0_[8][46] ;
wire \shifted_data_in_reg_n_0_[8][47] ;
wire \shifted_data_in_reg_n_0_[8][48] ;
wire \shifted_data_in_reg_n_0_[8][49] ;
wire \shifted_data_in_reg_n_0_[8][4] ;
wire \shifted_data_in_reg_n_0_[8][50] ;
wire \shifted_data_in_reg_n_0_[8][51] ;
wire \shifted_data_in_reg_n_0_[8][5] ;
wire \shifted_data_in_reg_n_0_[8][6] ;
wire \shifted_data_in_reg_n_0_[8][7] ;
wire \shifted_data_in_reg_n_0_[8][8] ;
wire \shifted_data_in_reg_n_0_[8][9] ;
wire [12:12]slaveRegDo_ff8;
wire [31:0]tc_config_cs_serial_input;
wire [31:0]tc_config_cs_serial_output;
wire [31:0]tc_config_cs_shift_en;
wire toggle;
wire toggle_rd;
wire [1:1]trace_data_ack;
wire \trace_data_ack_reg_n_0_[0] ;
wire [11:0]trace_read_addr;
wire trace_read_en;
wire trig_out_fsm;
wire trigger_i;
wire \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp ;
wire \u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1 ;
wire \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp ;
wire \u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1 ;
wire \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp ;
wire \u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1 ;
wire u_ila_cap_ctrl_n_1;
wire u_ila_cap_ctrl_n_22;
wire u_ila_cap_ctrl_n_23;
wire u_ila_cap_ctrl_n_25;
wire u_ila_regs_n_35;
wire u_ila_regs_n_37;
wire u_ila_regs_n_41;
wire u_ila_regs_n_59;
wire u_ila_regs_n_60;
wire u_ila_regs_n_61;
wire u_ila_regs_n_90;
wire u_ila_regs_n_92;
wire u_ila_regs_n_93;
wire u_ila_regs_n_94;
wire u_ila_reset_ctrl_n_2;
wire u_ila_reset_ctrl_n_6;
wire u_ila_reset_ctrl_n_7;
wire u_trig_n_45;
wire u_trig_n_46;
wire use_probe_debug_circuit;
wire use_probe_debug_circuit_1;
wire use_probe_debug_circuit_2;
wire xsdb_memory_read_inst_n_16;
wire xsdb_memory_read_inst_n_17;
wire xsdb_memory_read_inst_n_18;
wire xsdb_memory_read_inst_n_19;
wire xsdb_memory_read_inst_n_20;
wire xsdb_memory_read_inst_n_21;
wire xsdb_memory_read_inst_n_22;
wire xsdb_memory_read_inst_n_23;
wire xsdb_memory_read_inst_n_24;
wire xsdb_memory_read_inst_n_25;
wire xsdb_memory_read_inst_n_26;
wire xsdb_memory_read_inst_n_27;
wire \xsdb_reg[15]_i_2__0__0_n_0 ;
wire \xsdb_reg[15]_i_2__1__0_n_0 ;
wire \xsdb_reg[15]_i_2__5_n_0 ;
wire \xsdb_reg[15]_i_3__4_n_0 ;
wire \xsdb_reg[15]_i_4__0__0_n_0 ;
wire \xsdb_reg[15]_i_4__0_n_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_adv_trigger_sequencer \ADV_TRIG.u_adv_trig
(.A(trigger_i),
.ADDRA({address,u_trig_n_45}),
.\BRAM_DATA_reg[15] (BRAM_DATA_reg),
.\BRAM_DATA_reg[23] (CFG_BRAM_DATA),
.CAP_DONE_O_reg(u_ila_cap_ctrl_n_25),
.\CFG_DATA_O_reg[7] (CFG_BRAM_RD_DATA),
.CNT_CTRL(counter_ctrl),
.COUNTER_EQ(counter_out),
.E(toggle),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (u_ila_cap_ctrl_n_23),
.\I_YESLUT6.I_YES_OREG.O_reg_reg_0 (u_ila_cap_ctrl_n_1),
.\I_YESLUT6.I_YES_OREG.O_reg_reg_1 (u_ila_cap_ctrl_n_22),
.O_reg(O_reg),
.Q(reset[1:0]),
.SEQUENCER_STATE_O(SEQUENCER_STATE_O),
.\SEQUENCER_STATE_O_reg[11]_0 (\ADV_TRIG.u_adv_trig_n_6 ),
.\SEQUENCER_STATE_O_reg[11]_1 (\ADV_TRIG.u_adv_trig_n_7 ),
.\SEQUENCER_STATE_O_reg[11]_2 (\ADV_TRIG.u_adv_trig_n_8 ),
.S_DCLK_O(s_dclk),
.basic_trigger(basic_trigger),
.bram_en(bram_en),
.bram_rd_en(bram_rd_en),
.cap_done(cap_done),
.capture_fsm(capture_fsm),
.\current_state_reg[0]_0 (\ADV_TRIG.u_adv_trig_n_9 ),
.dout_reg1_reg(arm_status),
.dout_reg1_reg_0(u_ila_reset_ctrl_n_6),
.en_adv_trigger(en_adv_trigger),
.flag0_temp(flag0_temp),
.flag1_temp(flag1_temp),
.flag2_temp(flag2_temp),
.flag3_temp(flag3_temp),
.out(out),
.p_2_out(p_2_out),
.toggle_rd(toggle_rd),
.trig_out_fsm(trig_out_fsm),
.trigger_reg_0(\ADV_TRIG.u_adv_trig_n_18 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_fsm_memory_read \ADV_TRIG_MEM_READ.u_fsm_memory_read_inst
(.\CFG_BRAM_RD_DATA_reg[21] (CFG_BRAM_DATA),
.\CFG_BRAM_RD_DATA_reg[23] (CFG_BRAM_RD_DATA),
.D(config_fsm_data),
.E(toggle),
.\FSM_BRAM_ADDR_O_reg[0] (u_ila_regs_n_61),
.FSM_BRAM_CONFIG_DATA_I(config_fsm_data_rd),
.FSM_BRAM_EN_RB_O_reg(u_ila_regs_n_60),
.Q(BRAM_DATA_reg),
.S_DCLK_O(s_dclk),
.toggle_rd(toggle_rd));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_counter \COUNTER.u_count
(.CFG_CNT_DIN(cnt_config_cs_serial_output),
.CFG_CNT_DOUT(cnt_config_cs_serial_input),
.CNT_CTRL(counter_ctrl),
.COUNTER_EQ(counter_out),
.Q(reset[1:0]),
.S_DCLK_O(s_dclk),
.cnt_config_cs_shift_en(cnt_config_cs_shift_en),
.out(out),
.scnt_reset(scnt_reset));
LUT2 #(
.INIT(4'h7))
\I_EN_CTL_EQ1.temp_en_i_2
(.I0(s_daddr[10]),
.I1(s_daddr[11]),
.O(\I_EN_CTL_EQ1.temp_en_i_2_n_0 ));
LUT5 #(
.INIT(32'hFFFE0002))
adv_drdy_i_1
(.I0(s_den),
.I1(u_ila_regs_n_41),
.I2(s_daddr[1]),
.I3(u_ila_regs_n_90),
.I4(adv_drdy),
.O(adv_drdy_i_1_n_0));
FDRE basic_trigger_reg
(.C(out),
.CE(1'b1),
.D(u_trig_n_46),
.Q(basic_trigger),
.R(1'b0));
LUT2 #(
.INIT(4'h6))
count_tt_i_1
(.I0(slaveRegDo_ff8),
.I1(count_tt),
.O(count_tt_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair222" *)
LUT5 #(
.INIT(32'hFFFFFBFF))
\current_state[1]_i_2
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[3]),
.I3(s_daddr[2]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair223" *)
LUT5 #(
.INIT(32'hFFFFFEFF))
\current_state[1]_i_2__0
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[3]),
.I3(s_daddr[2]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair223" *)
LUT5 #(
.INIT(32'hFFFFFBFF))
\current_state[1]_i_2__1
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[2]),
.I3(s_daddr[3]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair222" *)
LUT5 #(
.INIT(32'hFFFFFEFF))
\current_state[1]_i_2__2
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[2]),
.I3(s_daddr[3]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF7FFFFFF))
\current_state[1]_i_2__3
(.I0(s_daddr[12]),
.I1(s_den),
.I2(s_daddr[11]),
.I3(s_daddr[10]),
.I4(s_daddr[0]),
.I5(s_daddr[1]),
.O(\current_state[1]_i_2__3_n_0 ));
LUT6 #(
.INIT(64'hF7FFFFFFFFFFFFFF))
\current_state[1]_i_2__4
(.I0(s_daddr[12]),
.I1(s_den),
.I2(s_daddr[11]),
.I3(s_daddr[10]),
.I4(s_daddr[1]),
.I5(s_daddr[0]),
.O(\current_state[1]_i_2__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair224" *)
LUT5 #(
.INIT(32'hFFFFBFFF))
\current_state[1]_i_2__5
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[3]),
.I3(s_daddr[2]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair224" *)
LUT5 #(
.INIT(32'hFFFFEFFF))
\current_state[1]_i_2__6
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[3]),
.I3(s_daddr[2]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair225" *)
LUT5 #(
.INIT(32'hFFFFFFFB))
\current_state[1]_i_2__7
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[2]),
.I3(s_daddr[3]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_2__7_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF7FFFFFF))
\current_state[1]_i_2__8
(.I0(s_daddr[12]),
.I1(s_den),
.I2(s_daddr[11]),
.I3(s_daddr[10]),
.I4(s_daddr[1]),
.I5(s_daddr[0]),
.O(\current_state[1]_i_2__8_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFF7FF))
\current_state[1]_i_2__9
(.I0(s_daddr[12]),
.I1(s_den),
.I2(s_daddr[11]),
.I3(s_daddr[10]),
.I4(s_daddr[1]),
.I5(s_daddr[0]),
.O(\current_state[1]_i_2__9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair225" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\current_state[1]_i_3
(.I0(s_daddr[5]),
.I1(s_daddr[4]),
.I2(s_daddr[2]),
.I3(s_daddr[3]),
.I4(\current_state[1]_i_4_n_0 ),
.O(\current_state[1]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair227" *)
LUT4 #(
.INIT(16'hFFFE))
\current_state[1]_i_4
(.I0(s_daddr[7]),
.I1(s_daddr[6]),
.I2(s_daddr[9]),
.I3(s_daddr[8]),
.O(\current_state[1]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair226" *)
LUT4 #(
.INIT(16'hEFFF))
\current_state[3]_i_5__0
(.I0(s_daddr[11]),
.I1(s_daddr[10]),
.I2(s_den),
.I3(s_daddr[12]),
.O(\current_state[3]_i_5__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair226" *)
LUT4 #(
.INIT(16'hDFFF))
\current_state[3]_i_5__0__0
(.I0(s_daddr[11]),
.I1(s_daddr[10]),
.I2(s_den),
.I3(s_daddr[12]),
.O(\current_state[3]_i_5__0__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair229" *)
LUT2 #(
.INIT(4'hB))
drdy_ffa_i_2
(.I0(s_daddr[0]),
.I1(s_daddr[1]),
.O(drdy_ffa_i_2_n_0));
FDRE en_adv_trigger_2_reg
(.C(out),
.CE(1'b1),
.D(en_adv_trigger_1),
.Q(en_adv_trigger_2),
.R(1'b0));
FDRE en_adv_trigger_reg
(.C(out),
.CE(1'b1),
.D(en_adv_trigger_2),
.Q(en_adv_trigger),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trace_memory ila_trace_memory_inst
(.ADDRBWRADDR(xsdb_memory_read_inst_n_27),
.CAP_TRIGGER_O_reg({cap_trigger_out,\shifted_data_in_reg_n_0_[8][51] ,\shifted_data_in_reg_n_0_[8][50] ,\shifted_data_in_reg_n_0_[8][49] ,\shifted_data_in_reg_n_0_[8][48] ,\shifted_data_in_reg_n_0_[8][47] ,\shifted_data_in_reg_n_0_[8][46] ,\shifted_data_in_reg_n_0_[8][45] }),
.CAP_WR_EN_O_reg(cap_wr_en),
.D(\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/din_2D[7]__0 ),
.DIADI({\shifted_data_in_reg_n_0_[8][7] ,\shifted_data_in_reg_n_0_[8][6] ,\shifted_data_in_reg_n_0_[8][5] ,\shifted_data_in_reg_n_0_[8][4] ,\shifted_data_in_reg_n_0_[8][3] ,\shifted_data_in_reg_n_0_[8][2] ,\shifted_data_in_reg_n_0_[8][1] ,\shifted_data_in_reg_n_0_[8][0] }),
.DIPADIP(\shifted_data_in_reg_n_0_[8][8] ),
.E(trace_read_en),
.Q({sel_i,trace_read_addr}),
.S_DCLK_O(s_dclk),
.enb_array(\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ),
.\i_intcap.CAP_ADDR_O_reg[14] (cap_wr_addr),
.out(out),
.\read_addr_reg[11]_rep ({xsdb_memory_read_inst_n_16,xsdb_memory_read_inst_n_17,xsdb_memory_read_inst_n_18,xsdb_memory_read_inst_n_19,xsdb_memory_read_inst_n_20,xsdb_memory_read_inst_n_21,xsdb_memory_read_inst_n_22,xsdb_memory_read_inst_n_23,xsdb_memory_read_inst_n_24,xsdb_memory_read_inst_n_25,xsdb_memory_read_inst_n_26}),
.\shifted_data_in_reg[8][16] ({\shifted_data_in_reg_n_0_[8][16] ,\shifted_data_in_reg_n_0_[8][15] ,\shifted_data_in_reg_n_0_[8][14] ,\shifted_data_in_reg_n_0_[8][13] ,\shifted_data_in_reg_n_0_[8][12] ,\shifted_data_in_reg_n_0_[8][11] ,\shifted_data_in_reg_n_0_[8][10] ,\shifted_data_in_reg_n_0_[8][9] }),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg_n_0_[8][17] ),
.\shifted_data_in_reg[8][25] ({\shifted_data_in_reg_n_0_[8][25] ,\shifted_data_in_reg_n_0_[8][24] ,\shifted_data_in_reg_n_0_[8][23] ,\shifted_data_in_reg_n_0_[8][22] ,\shifted_data_in_reg_n_0_[8][21] ,\shifted_data_in_reg_n_0_[8][20] ,\shifted_data_in_reg_n_0_[8][19] ,\shifted_data_in_reg_n_0_[8][18] }),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg_n_0_[8][26] ),
.\shifted_data_in_reg[8][34] ({\shifted_data_in_reg_n_0_[8][34] ,\shifted_data_in_reg_n_0_[8][33] ,\shifted_data_in_reg_n_0_[8][32] ,\shifted_data_in_reg_n_0_[8][31] ,\shifted_data_in_reg_n_0_[8][30] ,\shifted_data_in_reg_n_0_[8][29] ,\shifted_data_in_reg_n_0_[8][28] ,\shifted_data_in_reg_n_0_[8][27] }),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg_n_0_[8][35] ),
.\shifted_data_in_reg[8][43] ({\shifted_data_in_reg_n_0_[8][43] ,\shifted_data_in_reg_n_0_[8][42] ,\shifted_data_in_reg_n_0_[8][41] ,\shifted_data_in_reg_n_0_[8][40] ,\shifted_data_in_reg_n_0_[8][39] ,\shifted_data_in_reg_n_0_[8][38] ,\shifted_data_in_reg_n_0_[8][37] ,\shifted_data_in_reg_n_0_[8][36] }),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg_n_0_[8][44] ));
(* SOFT_HLUTNM = "soft_lutpair230" *)
LUT3 #(
.INIT(8'hAC))
\probeDelay1[0]_i_1
(.I0(debug_data_in[0]),
.I1(probe0),
.I2(use_probe_debug_circuit),
.O(probe_data[0]));
(* SOFT_HLUTNM = "soft_lutpair230" *)
LUT3 #(
.INIT(8'hAC))
\probeDelay1[0]_i_1__0
(.I0(debug_data_in[1]),
.I1(probe1),
.I2(use_probe_debug_circuit),
.O(probe_data[1]));
(* SOFT_HLUTNM = "soft_lutpair231" *)
LUT2 #(
.INIT(4'h2))
\probeDelay1[0]_i_1__1
(.I0(probe4),
.I1(use_probe_debug_circuit),
.O(probe_data[34]));
(* SOFT_HLUTNM = "soft_lutpair231" *)
LUT2 #(
.INIT(4'h2))
\probeDelay1[0]_i_1__2
(.I0(probe5),
.I1(use_probe_debug_circuit),
.O(probe_data[35]));
LUT2 #(
.INIT(4'h2))
\probeDelay1[0]_i_1__3
(.I0(probe7),
.I1(use_probe_debug_circuit),
.O(probe_data[49]));
LUT5 #(
.INIT(32'hFFFF22F2))
\shift_reg0[8]_i_1
(.I0(u_ila_regs_n_35),
.I1(drdy_ff9),
.I2(u_ila_regs_n_93),
.I3(u_ila_regs_n_92),
.I4(s_rst),
.O(\shift_reg0[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFF22F2))
\shift_reg1[15]_i_1
(.I0(u_ila_regs_n_37),
.I1(drdy_ffa),
.I2(u_ila_regs_n_59),
.I3(u_ila_regs_n_94),
.I4(s_rst),
.O(\shift_reg1[15]_i_1_n_0 ));
FDRE \shifted_data_in_reg[0][10]
(.C(out),
.CE(1'b1),
.D(probe2[8]),
.Q(\shifted_data_in_reg_n_0_[0][10] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][11]
(.C(out),
.CE(1'b1),
.D(probe2[9]),
.Q(\shifted_data_in_reg_n_0_[0][11] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][12]
(.C(out),
.CE(1'b1),
.D(probe2[10]),
.Q(\shifted_data_in_reg_n_0_[0][12] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][13]
(.C(out),
.CE(1'b1),
.D(probe2[11]),
.Q(\shifted_data_in_reg_n_0_[0][13] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][14]
(.C(out),
.CE(1'b1),
.D(probe2[12]),
.Q(\shifted_data_in_reg_n_0_[0][14] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][15]
(.C(out),
.CE(1'b1),
.D(probe2[13]),
.Q(\shifted_data_in_reg_n_0_[0][15] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][16]
(.C(out),
.CE(1'b1),
.D(probe2[14]),
.Q(\shifted_data_in_reg_n_0_[0][16] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][17]
(.C(out),
.CE(1'b1),
.D(probe2[15]),
.Q(\shifted_data_in_reg_n_0_[0][17] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][18]
(.C(out),
.CE(1'b1),
.D(probe3[0]),
.Q(\shifted_data_in_reg_n_0_[0][18] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][19]
(.C(out),
.CE(1'b1),
.D(probe3[1]),
.Q(\shifted_data_in_reg_n_0_[0][19] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][20]
(.C(out),
.CE(1'b1),
.D(probe3[2]),
.Q(\shifted_data_in_reg_n_0_[0][20] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][21]
(.C(out),
.CE(1'b1),
.D(probe3[3]),
.Q(\shifted_data_in_reg_n_0_[0][21] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][22]
(.C(out),
.CE(1'b1),
.D(probe3[4]),
.Q(\shifted_data_in_reg_n_0_[0][22] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][23]
(.C(out),
.CE(1'b1),
.D(probe3[5]),
.Q(\shifted_data_in_reg_n_0_[0][23] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][24]
(.C(out),
.CE(1'b1),
.D(probe3[6]),
.Q(\shifted_data_in_reg_n_0_[0][24] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][25]
(.C(out),
.CE(1'b1),
.D(probe3[7]),
.Q(\shifted_data_in_reg_n_0_[0][25] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][26]
(.C(out),
.CE(1'b1),
.D(probe3[8]),
.Q(\shifted_data_in_reg_n_0_[0][26] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][27]
(.C(out),
.CE(1'b1),
.D(probe3[9]),
.Q(\shifted_data_in_reg_n_0_[0][27] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][28]
(.C(out),
.CE(1'b1),
.D(probe3[10]),
.Q(\shifted_data_in_reg_n_0_[0][28] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][29]
(.C(out),
.CE(1'b1),
.D(probe3[11]),
.Q(\shifted_data_in_reg_n_0_[0][29] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][2]
(.C(out),
.CE(1'b1),
.D(probe2[0]),
.Q(\shifted_data_in_reg_n_0_[0][2] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][30]
(.C(out),
.CE(1'b1),
.D(probe3[12]),
.Q(\shifted_data_in_reg_n_0_[0][30] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][31]
(.C(out),
.CE(1'b1),
.D(probe3[13]),
.Q(\shifted_data_in_reg_n_0_[0][31] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][32]
(.C(out),
.CE(1'b1),
.D(probe3[14]),
.Q(\shifted_data_in_reg_n_0_[0][32] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][33]
(.C(out),
.CE(1'b1),
.D(probe3[15]),
.Q(\shifted_data_in_reg_n_0_[0][33] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][36]
(.C(out),
.CE(1'b1),
.D(probe6[0]),
.Q(\shifted_data_in_reg_n_0_[0][36] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][37]
(.C(out),
.CE(1'b1),
.D(probe6[1]),
.Q(\shifted_data_in_reg_n_0_[0][37] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][38]
(.C(out),
.CE(1'b1),
.D(probe6[2]),
.Q(\shifted_data_in_reg_n_0_[0][38] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][39]
(.C(out),
.CE(1'b1),
.D(probe6[3]),
.Q(\shifted_data_in_reg_n_0_[0][39] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][3]
(.C(out),
.CE(1'b1),
.D(probe2[1]),
.Q(\shifted_data_in_reg_n_0_[0][3] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][40]
(.C(out),
.CE(1'b1),
.D(probe6[4]),
.Q(\shifted_data_in_reg_n_0_[0][40] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][41]
(.C(out),
.CE(1'b1),
.D(probe6[5]),
.Q(\shifted_data_in_reg_n_0_[0][41] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][42]
(.C(out),
.CE(1'b1),
.D(probe6[6]),
.Q(\shifted_data_in_reg_n_0_[0][42] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][43]
(.C(out),
.CE(1'b1),
.D(probe6[7]),
.Q(\shifted_data_in_reg_n_0_[0][43] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][44]
(.C(out),
.CE(1'b1),
.D(probe6[8]),
.Q(\shifted_data_in_reg_n_0_[0][44] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][45]
(.C(out),
.CE(1'b1),
.D(probe6[9]),
.Q(\shifted_data_in_reg_n_0_[0][45] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][46]
(.C(out),
.CE(1'b1),
.D(probe6[10]),
.Q(\shifted_data_in_reg_n_0_[0][46] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][47]
(.C(out),
.CE(1'b1),
.D(probe6[11]),
.Q(\shifted_data_in_reg_n_0_[0][47] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][48]
(.C(out),
.CE(1'b1),
.D(probe6[12]),
.Q(\shifted_data_in_reg_n_0_[0][48] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][4]
(.C(out),
.CE(1'b1),
.D(probe2[2]),
.Q(\shifted_data_in_reg_n_0_[0][4] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][50]
(.C(out),
.CE(1'b1),
.D(probe8[0]),
.Q(\shifted_data_in_reg_n_0_[0][50] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][51]
(.C(out),
.CE(1'b1),
.D(probe8[1]),
.Q(\shifted_data_in_reg_n_0_[0][51] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][5]
(.C(out),
.CE(1'b1),
.D(probe2[3]),
.Q(\shifted_data_in_reg_n_0_[0][5] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][6]
(.C(out),
.CE(1'b1),
.D(probe2[4]),
.Q(\shifted_data_in_reg_n_0_[0][6] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][7]
(.C(out),
.CE(1'b1),
.D(probe2[5]),
.Q(\shifted_data_in_reg_n_0_[0][7] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][8]
(.C(out),
.CE(1'b1),
.D(probe2[6]),
.Q(\shifted_data_in_reg_n_0_[0][8] ),
.R(1'b0));
FDRE \shifted_data_in_reg[0][9]
(.C(out),
.CE(1'b1),
.D(probe2[7]),
.Q(\shifted_data_in_reg_n_0_[0][9] ),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][0]_srl8 " *)
SRL16E \shifted_data_in_reg[7][0]_srl8
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(probe0),
.Q(\shifted_data_in_reg[7][0]_srl8_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][10]_srl7 " *)
SRL16E \shifted_data_in_reg[7][10]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][10] ),
.Q(\shifted_data_in_reg[7][10]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][11]_srl7 " *)
SRL16E \shifted_data_in_reg[7][11]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][11] ),
.Q(\shifted_data_in_reg[7][11]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][12]_srl7 " *)
SRL16E \shifted_data_in_reg[7][12]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][12] ),
.Q(\shifted_data_in_reg[7][12]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][13]_srl7 " *)
SRL16E \shifted_data_in_reg[7][13]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][13] ),
.Q(\shifted_data_in_reg[7][13]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][14]_srl7 " *)
SRL16E \shifted_data_in_reg[7][14]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][14] ),
.Q(\shifted_data_in_reg[7][14]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][15]_srl7 " *)
SRL16E \shifted_data_in_reg[7][15]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][15] ),
.Q(\shifted_data_in_reg[7][15]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][16]_srl7 " *)
SRL16E \shifted_data_in_reg[7][16]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][16] ),
.Q(\shifted_data_in_reg[7][16]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][17]_srl7 " *)
SRL16E \shifted_data_in_reg[7][17]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][17] ),
.Q(\shifted_data_in_reg[7][17]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][18]_srl7 " *)
SRL16E \shifted_data_in_reg[7][18]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][18] ),
.Q(\shifted_data_in_reg[7][18]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][19]_srl7 " *)
SRL16E \shifted_data_in_reg[7][19]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][19] ),
.Q(\shifted_data_in_reg[7][19]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][1]_srl8 " *)
SRL16E \shifted_data_in_reg[7][1]_srl8
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(probe1),
.Q(\shifted_data_in_reg[7][1]_srl8_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][20]_srl7 " *)
SRL16E \shifted_data_in_reg[7][20]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][20] ),
.Q(\shifted_data_in_reg[7][20]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][21]_srl7 " *)
SRL16E \shifted_data_in_reg[7][21]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][21] ),
.Q(\shifted_data_in_reg[7][21]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][22]_srl7 " *)
SRL16E \shifted_data_in_reg[7][22]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][22] ),
.Q(\shifted_data_in_reg[7][22]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][23]_srl7 " *)
SRL16E \shifted_data_in_reg[7][23]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][23] ),
.Q(\shifted_data_in_reg[7][23]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][24]_srl7 " *)
SRL16E \shifted_data_in_reg[7][24]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][24] ),
.Q(\shifted_data_in_reg[7][24]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][25]_srl7 " *)
SRL16E \shifted_data_in_reg[7][25]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][25] ),
.Q(\shifted_data_in_reg[7][25]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][26]_srl7 " *)
SRL16E \shifted_data_in_reg[7][26]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][26] ),
.Q(\shifted_data_in_reg[7][26]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][27]_srl7 " *)
SRL16E \shifted_data_in_reg[7][27]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][27] ),
.Q(\shifted_data_in_reg[7][27]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][28]_srl7 " *)
SRL16E \shifted_data_in_reg[7][28]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][28] ),
.Q(\shifted_data_in_reg[7][28]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][29]_srl7 " *)
SRL16E \shifted_data_in_reg[7][29]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][29] ),
.Q(\shifted_data_in_reg[7][29]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][2]_srl7 " *)
SRL16E \shifted_data_in_reg[7][2]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][2] ),
.Q(\shifted_data_in_reg[7][2]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][30]_srl7 " *)
SRL16E \shifted_data_in_reg[7][30]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][30] ),
.Q(\shifted_data_in_reg[7][30]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][31]_srl7 " *)
SRL16E \shifted_data_in_reg[7][31]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][31] ),
.Q(\shifted_data_in_reg[7][31]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][32]_srl7 " *)
SRL16E \shifted_data_in_reg[7][32]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][32] ),
.Q(\shifted_data_in_reg[7][32]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][33]_srl7 " *)
SRL16E \shifted_data_in_reg[7][33]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][33] ),
.Q(\shifted_data_in_reg[7][33]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][34]_srl8 " *)
SRL16E \shifted_data_in_reg[7][34]_srl8
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(probe4),
.Q(\shifted_data_in_reg[7][34]_srl8_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][35]_srl8 " *)
SRL16E \shifted_data_in_reg[7][35]_srl8
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(probe5),
.Q(\shifted_data_in_reg[7][35]_srl8_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][36]_srl7 " *)
SRL16E \shifted_data_in_reg[7][36]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][36] ),
.Q(\shifted_data_in_reg[7][36]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][37]_srl7 " *)
SRL16E \shifted_data_in_reg[7][37]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][37] ),
.Q(\shifted_data_in_reg[7][37]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][38]_srl7 " *)
SRL16E \shifted_data_in_reg[7][38]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][38] ),
.Q(\shifted_data_in_reg[7][38]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][39]_srl7 " *)
SRL16E \shifted_data_in_reg[7][39]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][39] ),
.Q(\shifted_data_in_reg[7][39]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][3]_srl7 " *)
SRL16E \shifted_data_in_reg[7][3]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][3] ),
.Q(\shifted_data_in_reg[7][3]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][40]_srl7 " *)
SRL16E \shifted_data_in_reg[7][40]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][40] ),
.Q(\shifted_data_in_reg[7][40]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][41]_srl7 " *)
SRL16E \shifted_data_in_reg[7][41]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][41] ),
.Q(\shifted_data_in_reg[7][41]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][42]_srl7 " *)
SRL16E \shifted_data_in_reg[7][42]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][42] ),
.Q(\shifted_data_in_reg[7][42]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][43]_srl7 " *)
SRL16E \shifted_data_in_reg[7][43]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][43] ),
.Q(\shifted_data_in_reg[7][43]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][44]_srl7 " *)
SRL16E \shifted_data_in_reg[7][44]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][44] ),
.Q(\shifted_data_in_reg[7][44]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][45]_srl7 " *)
SRL16E \shifted_data_in_reg[7][45]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][45] ),
.Q(\shifted_data_in_reg[7][45]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][46]_srl7 " *)
SRL16E \shifted_data_in_reg[7][46]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][46] ),
.Q(\shifted_data_in_reg[7][46]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][47]_srl7 " *)
SRL16E \shifted_data_in_reg[7][47]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][47] ),
.Q(\shifted_data_in_reg[7][47]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][48]_srl7 " *)
SRL16E \shifted_data_in_reg[7][48]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][48] ),
.Q(\shifted_data_in_reg[7][48]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][49]_srl8 " *)
SRL16E \shifted_data_in_reg[7][49]_srl8
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(probe7),
.Q(\shifted_data_in_reg[7][49]_srl8_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][4]_srl7 " *)
SRL16E \shifted_data_in_reg[7][4]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][4] ),
.Q(\shifted_data_in_reg[7][4]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][50]_srl7 " *)
SRL16E \shifted_data_in_reg[7][50]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][50] ),
.Q(\shifted_data_in_reg[7][50]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][51]_srl7 " *)
SRL16E \shifted_data_in_reg[7][51]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][51] ),
.Q(\shifted_data_in_reg[7][51]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][5]_srl7 " *)
SRL16E \shifted_data_in_reg[7][5]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][5] ),
.Q(\shifted_data_in_reg[7][5]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][6]_srl7 " *)
SRL16E \shifted_data_in_reg[7][6]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][6] ),
.Q(\shifted_data_in_reg[7][6]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][7]_srl7 " *)
SRL16E \shifted_data_in_reg[7][7]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][7] ),
.Q(\shifted_data_in_reg[7][7]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][8]_srl7 " *)
SRL16E \shifted_data_in_reg[7][8]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][8] ),
.Q(\shifted_data_in_reg[7][8]_srl7_n_0 ));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7] " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/shifted_data_in_reg[7][9]_srl7 " *)
SRL16E \shifted_data_in_reg[7][9]_srl7
(.A0(1'b0),
.A1(1'b1),
.A2(1'b1),
.A3(1'b0),
.CE(1'b1),
.CLK(out),
.D(\shifted_data_in_reg_n_0_[0][9] ),
.Q(\shifted_data_in_reg[7][9]_srl7_n_0 ));
FDRE \shifted_data_in_reg[8][0]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][0]_srl8_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][0] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][10]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][10]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][10] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][11]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][11]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][11] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][12]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][12]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][12] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][13]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][13]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][13] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][14]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][14]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][14] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][15]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][15]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][15] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][16]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][16]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][16] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][17]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][17]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][17] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][18]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][18]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][18] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][19]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][19]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][19] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][1]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][1]_srl8_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][1] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][20]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][20]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][20] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][21]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][21]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][21] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][22]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][22]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][22] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][23]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][23]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][23] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][24]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][24]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][24] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][25]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][25]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][25] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][26]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][26]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][26] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][27]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][27]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][27] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][28]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][28]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][28] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][29]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][29]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][29] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][2]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][2]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][2] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][30]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][30]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][30] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][31]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][31]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][31] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][32]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][32]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][32] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][33]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][33]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][33] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][34]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][34]_srl8_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][34] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][35]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][35]_srl8_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][35] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][36]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][36]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][36] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][37]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][37]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][37] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][38]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][38]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][38] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][39]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][39]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][39] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][3]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][3]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][3] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][40]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][40]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][40] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][41]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][41]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][41] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][42]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][42]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][42] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][43]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][43]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][43] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][44]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][44]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][44] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][45]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][45]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][45] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][46]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][46]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][46] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][47]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][47]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][47] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][48]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][48]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][48] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][49]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][49]_srl8_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][49] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][4]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][4]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][4] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][50]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][50]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][50] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][51]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][51]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][51] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][5]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][5]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][5] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][6]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][6]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][6] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][7]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][7]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][7] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][8]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][8]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][8] ),
.R(1'b0));
FDRE \shifted_data_in_reg[8][9]
(.C(out),
.CE(1'b1),
.D(\shifted_data_in_reg[7][9]_srl7_n_0 ),
.Q(\shifted_data_in_reg_n_0_[8][9] ),
.R(1'b0));
FDRE \trace_data_ack_reg[0]
(.C(s_dclk),
.CE(1'b1),
.D(trace_read_en),
.Q(\trace_data_ack_reg_n_0_[0] ),
.R(1'b0));
FDRE \trace_data_ack_reg[1]
(.C(s_dclk),
.CE(1'b1),
.D(\trace_data_ack_reg_n_0_[0] ),
.Q(trace_data_ack),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_cap_ctrl_legacy u_ila_cap_ctrl
(.A(trigger_i),
.D(capture_ctrl_config_cs_serial_input),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (cap_wr_addr),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (cap_wr_en),
.DOUT_O(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1 ),
.E(capture_ctrl_config_en),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\ADV_TRIG.u_adv_trig_n_18 ),
.O_reg(O_reg),
.Q(reset[1:0]),
.S_DCLK_O(s_dclk),
.TRIGGERED_SL_I(cap_trigger_out),
.basic_trigger(basic_trigger),
.cap_done(cap_done),
.capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
.capture_fsm(capture_fsm),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.capture_strg_qual(capture_strg_qual),
.\current_state_reg[0] (u_ila_cap_ctrl_n_22),
.\current_state_reg[0]_0 (u_ila_cap_ctrl_n_23),
.dout_reg1_reg(arm_status),
.en_adv_trigger(en_adv_trigger),
.out(out),
.p_2_out(p_2_out),
.\reset_out_reg[0] (u_ila_reset_ctrl_n_7),
.scnt_cmp_temp(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp ),
.scnt_reset(scnt_reset),
.trig_out_fsm(trig_out_fsm),
.trigger_reg(u_ila_cap_ctrl_n_25),
.u_wcnt_hcmp_q(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1 ),
.u_wcnt_lcmp_q(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1 ),
.wcnt_hcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp ),
.wcnt_lcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp ),
.\xsdb_reg_reg[0] (u_ila_cap_ctrl_n_1),
.\xsdb_reg_reg[14] (capture_cnt));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_register u_ila_regs
(.CAP_DONE_O_reg({cap_done,cap_trigger_out,halt_status,arm_status}),
.CFG_CNT_DIN(cnt_config_cs_serial_output),
.CFG_CNT_DOUT(cnt_config_cs_serial_input),
.\CFG_DATA_O_reg[15] (config_fsm_data_rd),
.D(config_fsm_data),
.DOUT_O(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp1 ),
.DUMMY_I(DUMMY_I),
.E(data_out_en),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\xsdb_reg[15]_i_2__0__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 (drdy_ffa_i_2_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[10] (\I_EN_CTL_EQ1.temp_en_i_2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\xsdb_reg[15]_i_2__1__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[11]_0 (\current_state[3]_i_5__0__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[11]_1 (\current_state[3]_i_5__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\current_state[1]_i_2__9_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 (\current_state[1]_i_2__3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 (\current_state[1]_i_2__8_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 (\current_state[1]_i_2__4_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\xsdb_reg[15]_i_4__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\xsdb_reg[15]_i_4__0__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\xsdb_reg[15]_i_2__5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 (\current_state[1]_i_2__0_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 (\current_state[1]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 (\current_state[1]_i_2__2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 (\current_state[1]_i_2__6_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 (\current_state[1]_i_2__7_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 (\current_state[1]_i_2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 (\current_state[1]_i_2__1_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 (\current_state[1]_i_2__5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\xsdb_reg[15]_i_3__4_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\current_state[1]_i_4_n_0 ),
.\G_1PIPE_IFACE.s_den_r_reg (adv_drdy_i_1_n_0),
.\I_EN_CTL_EQ1.temp_en_reg (u_ila_regs_n_41),
.\I_YESLUT6.I_YES_OREG.O_reg_reg ({O_reg,u_ila_cap_ctrl_n_1}),
.SEQUENCER_STATE_O(SEQUENCER_STATE_O),
.SL_IPORT_I(SL_IPORT_I),
.SL_OPORT_O(SL_OPORT_O),
.SR(read_addr_reset),
.adv_drdy(adv_drdy),
.arm_ctrl(arm_ctrl),
.bram_en(bram_en),
.bram_rd_en(bram_rd_en),
.capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.\captured_samples_reg[14] (capture_cnt),
.cnt_config_cs_shift_en(cnt_config_cs_shift_en),
.count_tt(count_tt),
.count_tt_reg_0(count_tt_i_1_n_0),
.debug_data_in(debug_data_in),
.drdy_ff9(drdy_ff9),
.drdy_ffa(drdy_ffa),
.en_adv_trigger(en_adv_trigger),
.en_adv_trigger_1(en_adv_trigger_1),
.flag0_temp(flag0_temp),
.flag1_temp(flag1_temp),
.flag2_temp(flag2_temp),
.flag3_temp(flag3_temp),
.halt_ctrl(halt_ctrl),
.\input_data_reg[31] (data_word_out),
.mu_config_cs_serial_input({mu_config_cs_serial_input[15:14],mu_config_cs_serial_input[11:8],mu_config_cs_serial_input[3:0]}),
.mu_config_cs_serial_output({mu_config_cs_serial_output[15:14],mu_config_cs_serial_output[11:8],mu_config_cs_serial_output[3:0]}),
.mu_config_cs_shift_en({mu_config_cs_shift_en[15:14],mu_config_cs_shift_en[11:8],mu_config_cs_shift_en[3:0]}),
.\parallel_dout_reg[0] (qual_strg_config_cs_shift_en),
.\parallel_dout_reg[0]_0 (capture_ctrl_config_en),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.read_data_en(read_data_en),
.read_reset_addr(read_reset_addr),
.regDrdy_reg_0(u_ila_regs_n_90),
.s_daddr_o(s_daddr),
.s_dclk_o(s_dclk),
.s_den_o(s_den),
.s_dwe_o(s_dwe),
.s_rst_o(s_rst),
.scnt_cmp_temp(\u_cap_addrgen/u_cap_sample_counter/scnt_cmp_temp ),
.shift_en_reg(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp1 ),
.shift_en_reg_0(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp1 ),
.shift_en_reg_1(qual_strg_config_cs_serial_input),
.shift_en_reg_2(capture_ctrl_config_cs_serial_input),
.\shift_reg0_reg[8]_0 (u_ila_regs_n_92),
.\shift_reg0_reg[8]_1 (u_ila_regs_n_93),
.\shift_reg0_reg[8]_2 (\shift_reg0[8]_i_1_n_0 ),
.\shift_reg1_reg[15]_0 (u_ila_regs_n_59),
.\shift_reg1_reg[15]_1 (u_ila_regs_n_94),
.\shift_reg1_reg[15]_2 (\shift_reg1[15]_i_1_n_0 ),
.slaveRegDo_ff8(slaveRegDo_ff8),
.\slaveRegDo_ff9_reg[8]_0 (u_ila_regs_n_35),
.\slaveRegDo_ffa_reg[15]_0 (u_ila_regs_n_37),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en),
.toggle_rd(toggle_rd),
.toggle_rd_reg(u_ila_regs_n_60),
.toggle_reg(u_ila_regs_n_61),
.toggle_reg_0(toggle),
.use_probe_debug_circuit_1(use_probe_debug_circuit_1),
.wcnt_hcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_hcmp_temp ),
.wcnt_lcmp_temp(\u_cap_addrgen/u_cap_window_counter/wcnt_lcmp_temp ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_reset_ctrl u_ila_reset_ctrl
(.\I_YESLUT6.I_YES_OREG.O_reg_reg (u_ila_cap_ctrl_n_1),
.Q({u_ila_reset_ctrl_n_2,reset[3],reset[1:0]}),
.\SEQUENCER_STATE_O_reg[8] (u_ila_reset_ctrl_n_6),
.arm_ctrl(arm_ctrl),
.cap_done(cap_done),
.\captured_samples_reg[0] (u_ila_reset_ctrl_n_7),
.\current_state_reg[3] (\ADV_TRIG.u_adv_trig_n_9 ),
.halt_ctrl(halt_ctrl),
.out(out),
.s_dclk_o(s_dclk),
.temp_reg0_reg({halt_status,arm_status}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trigger u_trig
(.ADDRA({address,u_trig_n_45}),
.Q({u_ila_reset_ctrl_n_2,reset[3],reset[0]}),
.basic_trigger_reg(u_trig_n_46),
.capture_strg_qual(capture_strg_qual),
.\current_state_reg[0] (\ADV_TRIG.u_adv_trig_n_6 ),
.\current_state_reg[1] (\ADV_TRIG.u_adv_trig_n_7 ),
.\current_state_reg[2] (\ADV_TRIG.u_adv_trig_n_8 ),
.\current_state_reg[3] (\ADV_TRIG.u_adv_trig_n_9 ),
.mu_config_cs_serial_input({mu_config_cs_serial_input[15:14],mu_config_cs_serial_input[11:8],mu_config_cs_serial_input[3:0]}),
.mu_config_cs_serial_output({mu_config_cs_serial_output[15:14],mu_config_cs_serial_output[11:8],mu_config_cs_serial_output[3:0]}),
.mu_config_cs_shift_en({mu_config_cs_shift_en[15:14],mu_config_cs_shift_en[11:8],mu_config_cs_shift_en[3:0]}),
.out(out),
.\parallel_dout_reg[15] (qual_strg_config_cs_serial_input),
.probe_data({probe_data[49],probe_data[35:34],probe_data[1:0]}),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.s_dclk_o(s_dclk),
.shift_en_reg(qual_strg_config_cs_shift_en),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE use_probe_debug_circuit_2_reg
(.C(out),
.CE(1'b1),
.D(use_probe_debug_circuit_1),
.Q(use_probe_debug_circuit_2),
.R(1'b0));
FDRE use_probe_debug_circuit_reg
(.C(out),
.CE(1'b1),
.D(use_probe_debug_circuit_2),
.Q(use_probe_debug_circuit),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_generic_memrd xsdb_memory_read_inst
(.ADDRBWRADDR(xsdb_memory_read_inst_n_27),
.D(\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/has_mux_b.B/din_2D[7]__0 ),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ({xsdb_memory_read_inst_n_16,xsdb_memory_read_inst_n_17,xsdb_memory_read_inst_n_18,xsdb_memory_read_inst_n_19,xsdb_memory_read_inst_n_20,xsdb_memory_read_inst_n_21,xsdb_memory_read_inst_n_22,xsdb_memory_read_inst_n_23,xsdb_memory_read_inst_n_24,xsdb_memory_read_inst_n_25,xsdb_memory_read_inst_n_26}),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 (trace_read_en),
.E(data_out_en),
.Q({sel_i,trace_read_addr}),
.SR(read_addr_reset),
.enb_array(\SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/enb_array ),
.read_data_en(read_data_en),
.read_reset_addr(read_reset_addr),
.s_dclk_o(s_dclk),
.\trace_data_ack_reg[1] (trace_data_ack),
.\xsdb_reg_reg[15] (data_word_out));
(* SOFT_HLUTNM = "soft_lutpair229" *)
LUT4 #(
.INIT(16'h0100))
\xsdb_reg[15]_i_2__0__0
(.I0(s_daddr[0]),
.I1(s_daddr[1]),
.I2(s_daddr[2]),
.I3(\xsdb_reg[15]_i_2__1__0_n_0 ),
.O(\xsdb_reg[15]_i_2__0__0_n_0 ));
LUT6 #(
.INIT(64'h0001000000000000))
\xsdb_reg[15]_i_2__1__0
(.I0(s_daddr[11]),
.I1(s_daddr[12]),
.I2(s_daddr[9]),
.I3(s_daddr[10]),
.I4(s_dwe),
.I5(s_den),
.O(\xsdb_reg[15]_i_2__1__0_n_0 ));
LUT6 #(
.INIT(64'h0000000100000000))
\xsdb_reg[15]_i_2__5
(.I0(s_daddr[5]),
.I1(s_daddr[6]),
.I2(s_daddr[3]),
.I3(s_daddr[4]),
.I4(s_daddr[8]),
.I5(s_daddr[7]),
.O(\xsdb_reg[15]_i_2__5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair227" *)
LUT2 #(
.INIT(4'h1))
\xsdb_reg[15]_i_3__4
(.I0(s_daddr[7]),
.I1(s_daddr[8]),
.O(\xsdb_reg[15]_i_3__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair228" *)
LUT2 #(
.INIT(4'hE))
\xsdb_reg[15]_i_4__0
(.I0(s_daddr[2]),
.I1(s_daddr[3]),
.O(\xsdb_reg[15]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair228" *)
LUT4 #(
.INIT(16'h0001))
\xsdb_reg[15]_i_4__0__0
(.I0(s_daddr[4]),
.I1(s_daddr[3]),
.I2(s_daddr[6]),
.I3(s_daddr[5]),
.O(\xsdb_reg[15]_i_4__0__0_n_0 ));
endmodule | 8 |
2,147 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_counter
(CFG_CNT_DOUT,
COUNTER_EQ,
out,
S_DCLK_O,
Q,
scnt_reset,
CNT_CTRL,
CFG_CNT_DIN,
cnt_config_cs_shift_en);
output [3:0]CFG_CNT_DOUT;
output [3:0]COUNTER_EQ;
input out;
input S_DCLK_O;
input [1:0]Q;
input scnt_reset;
input [7:0]CNT_CTRL;
input [3:0]CFG_CNT_DIN;
input [3:0]cnt_config_cs_shift_en;
wire [3:0]CFG_CNT_DIN;
wire [3:0]CFG_CNT_DOUT;
wire [7:0]CNT_CTRL;
wire [3:0]COUNTER_EQ;
wire [1:0]Q;
wire S_DCLK_O;
wire [3:0]cnt_config_cs_shift_en;
wire out;
wire scnt_reset;
(* CNT_MAX = "17'b10000000000000000" *)
(* C_COUNTER_WIDTH = "17" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__4 \G_COUNTER[0].U_COUNTER
(.CFG_CLK(S_DCLK_O),
.CLK(out),
.CNT_CTRL(CNT_CTRL[1:0]),
.CNT_LOAD_DOUT(CFG_CNT_DOUT[0]),
.CNT_LOAD_EN(cnt_config_cs_shift_en[0]),
.CNT_LOAD_IN(CFG_CNT_DIN[0]),
.COUNTER_MATCH(COUNTER_EQ[0]),
.RESET(Q),
.SCNT_RESET(scnt_reset));
(* CNT_MAX = "17'b10000000000000000" *)
(* C_COUNTER_WIDTH = "17" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__5 \G_COUNTER[1].U_COUNTER
(.CFG_CLK(S_DCLK_O),
.CLK(out),
.CNT_CTRL(CNT_CTRL[3:2]),
.CNT_LOAD_DOUT(CFG_CNT_DOUT[1]),
.CNT_LOAD_EN(cnt_config_cs_shift_en[1]),
.CNT_LOAD_IN(CFG_CNT_DIN[1]),
.COUNTER_MATCH(COUNTER_EQ[1]),
.RESET(Q),
.SCNT_RESET(scnt_reset));
(* CNT_MAX = "17'b10000000000000000" *)
(* C_COUNTER_WIDTH = "17" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__6 \G_COUNTER[2].U_COUNTER
(.CFG_CLK(S_DCLK_O),
.CLK(out),
.CNT_CTRL(CNT_CTRL[5:4]),
.CNT_LOAD_DOUT(CFG_CNT_DOUT[2]),
.CNT_LOAD_EN(cnt_config_cs_shift_en[2]),
.CNT_LOAD_IN(CFG_CNT_DIN[2]),
.COUNTER_MATCH(COUNTER_EQ[2]),
.RESET(Q),
.SCNT_RESET(scnt_reset));
(* CNT_MAX = "17'b10000000000000000" *)
(* C_COUNTER_WIDTH = "17" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter \G_COUNTER[3].U_COUNTER
(.CFG_CLK(S_DCLK_O),
.CLK(out),
.CNT_CTRL(CNT_CTRL[7:6]),
.CNT_LOAD_DOUT(CFG_CNT_DOUT[3]),
.CNT_LOAD_EN(cnt_config_cs_shift_en[3]),
.CNT_LOAD_IN(CFG_CNT_DIN[3]),
.COUNTER_MATCH(COUNTER_EQ[3]),
.RESET(Q),
.SCNT_RESET(scnt_reset));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_counter
(CFG_CNT_DOUT,
COUNTER_EQ,
out,
S_DCLK_O,
Q,
scnt_reset,
CNT_CTRL,
CFG_CNT_DIN,
cnt_config_cs_shift_en); |
output [3:0]CFG_CNT_DOUT;
output [3:0]COUNTER_EQ;
input out;
input S_DCLK_O;
input [1:0]Q;
input scnt_reset;
input [7:0]CNT_CTRL;
input [3:0]CFG_CNT_DIN;
input [3:0]cnt_config_cs_shift_en;
wire [3:0]CFG_CNT_DIN;
wire [3:0]CFG_CNT_DOUT;
wire [7:0]CNT_CTRL;
wire [3:0]COUNTER_EQ;
wire [1:0]Q;
wire S_DCLK_O;
wire [3:0]cnt_config_cs_shift_en;
wire out;
wire scnt_reset;
(* CNT_MAX = "17'b10000000000000000" *)
(* C_COUNTER_WIDTH = "17" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__4 \G_COUNTER[0].U_COUNTER
(.CFG_CLK(S_DCLK_O),
.CLK(out),
.CNT_CTRL(CNT_CTRL[1:0]),
.CNT_LOAD_DOUT(CFG_CNT_DOUT[0]),
.CNT_LOAD_EN(cnt_config_cs_shift_en[0]),
.CNT_LOAD_IN(CFG_CNT_DIN[0]),
.COUNTER_MATCH(COUNTER_EQ[0]),
.RESET(Q),
.SCNT_RESET(scnt_reset));
(* CNT_MAX = "17'b10000000000000000" *)
(* C_COUNTER_WIDTH = "17" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__5 \G_COUNTER[1].U_COUNTER
(.CFG_CLK(S_DCLK_O),
.CLK(out),
.CNT_CTRL(CNT_CTRL[3:2]),
.CNT_LOAD_DOUT(CFG_CNT_DOUT[1]),
.CNT_LOAD_EN(cnt_config_cs_shift_en[1]),
.CNT_LOAD_IN(CFG_CNT_DIN[1]),
.COUNTER_MATCH(COUNTER_EQ[1]),
.RESET(Q),
.SCNT_RESET(scnt_reset));
(* CNT_MAX = "17'b10000000000000000" *)
(* C_COUNTER_WIDTH = "17" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter__6 \G_COUNTER[2].U_COUNTER
(.CFG_CLK(S_DCLK_O),
.CLK(out),
.CNT_CTRL(CNT_CTRL[5:4]),
.CNT_LOAD_DOUT(CFG_CNT_DOUT[2]),
.CNT_LOAD_EN(cnt_config_cs_shift_en[2]),
.CNT_LOAD_IN(CFG_CNT_DIN[2]),
.COUNTER_MATCH(COUNTER_EQ[2]),
.RESET(Q),
.SCNT_RESET(scnt_reset));
(* CNT_MAX = "17'b10000000000000000" *)
(* C_COUNTER_WIDTH = "17" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_generic_counter \G_COUNTER[3].U_COUNTER
(.CFG_CLK(S_DCLK_O),
.CLK(out),
.CNT_CTRL(CNT_CTRL[7:6]),
.CNT_LOAD_DOUT(CFG_CNT_DOUT[3]),
.CNT_LOAD_EN(cnt_config_cs_shift_en[3]),
.CNT_LOAD_IN(CFG_CNT_DIN[3]),
.COUNTER_MATCH(COUNTER_EQ[3]),
.RESET(Q),
.SCNT_RESET(scnt_reset));
endmodule | 8 |
2,148 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_fsm_memory_read
(toggle_rd,
E,
Q,
\CFG_BRAM_RD_DATA_reg[21] ,
FSM_BRAM_CONFIG_DATA_I,
FSM_BRAM_EN_RB_O_reg,
S_DCLK_O,
\FSM_BRAM_ADDR_O_reg[0] ,
D,
\CFG_BRAM_RD_DATA_reg[23] );
output toggle_rd;
output [0:0]E;
output [15:0]Q;
output [7:0]\CFG_BRAM_RD_DATA_reg[21] ;
output [15:0]FSM_BRAM_CONFIG_DATA_I;
input FSM_BRAM_EN_RB_O_reg;
input S_DCLK_O;
input \FSM_BRAM_ADDR_O_reg[0] ;
input [15:0]D;
input [23:0]\CFG_BRAM_RD_DATA_reg[23] ;
wire \BRAM_DATA[15]_i_1_n_0 ;
wire [7:0]\CFG_BRAM_RD_DATA_reg[21] ;
wire [23:0]\CFG_BRAM_RD_DATA_reg[23] ;
wire \CFG_DATA_O[0]_i_1_n_0 ;
wire \CFG_DATA_O[15]_i_1_n_0 ;
wire \CFG_DATA_O[1]_i_1_n_0 ;
wire \CFG_DATA_O[2]_i_1_n_0 ;
wire \CFG_DATA_O[3]_i_1_n_0 ;
wire \CFG_DATA_O[4]_i_1_n_0 ;
wire \CFG_DATA_O[5]_i_1_n_0 ;
wire \CFG_DATA_O[6]_i_1_n_0 ;
wire \CFG_DATA_O[7]_i_1_n_0 ;
wire [15:0]D;
wire [0:0]E;
wire \FSM_BRAM_ADDR_O_reg[0] ;
wire [15:0]FSM_BRAM_CONFIG_DATA_I;
wire FSM_BRAM_EN_RB_O_reg;
wire [15:0]Q;
wire S_DCLK_O;
wire toggle_rd;
LUT1 #(
.INIT(2'h1))
\BRAM_DATA[15]_i_1
(.I0(E),
.O(\BRAM_DATA[15]_i_1_n_0 ));
FDRE \BRAM_DATA_reg[0]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \BRAM_DATA_reg[10]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \BRAM_DATA_reg[11]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \BRAM_DATA_reg[12]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \BRAM_DATA_reg[13]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \BRAM_DATA_reg[14]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \BRAM_DATA_reg[15]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \BRAM_DATA_reg[16]
(.C(S_DCLK_O),
.CE(E),
.D(D[0]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [0]),
.R(1'b0));
FDRE \BRAM_DATA_reg[17]
(.C(S_DCLK_O),
.CE(E),
.D(D[1]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [1]),
.R(1'b0));
FDRE \BRAM_DATA_reg[18]
(.C(S_DCLK_O),
.CE(E),
.D(D[2]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [2]),
.R(1'b0));
FDRE \BRAM_DATA_reg[19]
(.C(S_DCLK_O),
.CE(E),
.D(D[3]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [3]),
.R(1'b0));
FDRE \BRAM_DATA_reg[1]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \BRAM_DATA_reg[20]
(.C(S_DCLK_O),
.CE(E),
.D(D[4]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [4]),
.R(1'b0));
FDRE \BRAM_DATA_reg[21]
(.C(S_DCLK_O),
.CE(E),
.D(D[5]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [5]),
.R(1'b0));
FDRE \BRAM_DATA_reg[22]
(.C(S_DCLK_O),
.CE(E),
.D(D[6]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [6]),
.R(1'b0));
FDRE \BRAM_DATA_reg[23]
(.C(S_DCLK_O),
.CE(E),
.D(D[7]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [7]),
.R(1'b0));
FDRE \BRAM_DATA_reg[2]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \BRAM_DATA_reg[3]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \BRAM_DATA_reg[4]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \BRAM_DATA_reg[5]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \BRAM_DATA_reg[6]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \BRAM_DATA_reg[7]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \BRAM_DATA_reg[8]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \BRAM_DATA_reg[9]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[9]),
.Q(Q[9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[0]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [0]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [16]),
.I2(toggle_rd),
.O(\CFG_DATA_O[0]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\CFG_DATA_O[15]_i_1
(.I0(toggle_rd),
.O(\CFG_DATA_O[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[1]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [1]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [17]),
.I2(toggle_rd),
.O(\CFG_DATA_O[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[2]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [2]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [18]),
.I2(toggle_rd),
.O(\CFG_DATA_O[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[3]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [3]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [19]),
.I2(toggle_rd),
.O(\CFG_DATA_O[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[4]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [4]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [20]),
.I2(toggle_rd),
.O(\CFG_DATA_O[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[5]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [5]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [21]),
.I2(toggle_rd),
.O(\CFG_DATA_O[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[6]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [6]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [22]),
.I2(toggle_rd),
.O(\CFG_DATA_O[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[7]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [7]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [23]),
.I2(toggle_rd),
.O(\CFG_DATA_O[7]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[0]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[0]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[0]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[10]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [10]),
.Q(FSM_BRAM_CONFIG_DATA_I[10]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[11]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [11]),
.Q(FSM_BRAM_CONFIG_DATA_I[11]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[12]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [12]),
.Q(FSM_BRAM_CONFIG_DATA_I[12]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[13]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [13]),
.Q(FSM_BRAM_CONFIG_DATA_I[13]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[14]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [14]),
.Q(FSM_BRAM_CONFIG_DATA_I[14]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[15]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [15]),
.Q(FSM_BRAM_CONFIG_DATA_I[15]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[1]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[1]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[1]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[2]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[2]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[2]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[3]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[3]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[3]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[4]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[4]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[4]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[5]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[5]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[5]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[6]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[6]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[6]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[7]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[7]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[7]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[8]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [8]),
.Q(FSM_BRAM_CONFIG_DATA_I[8]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[9]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [9]),
.Q(FSM_BRAM_CONFIG_DATA_I[9]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
toggle_rd_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(FSM_BRAM_EN_RB_O_reg),
.Q(toggle_rd),
.R(1'b0));
FDRE #(
.INIT(1'b0))
toggle_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(\FSM_BRAM_ADDR_O_reg[0] ),
.Q(E),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_fsm_memory_read
(toggle_rd,
E,
Q,
\CFG_BRAM_RD_DATA_reg[21] ,
FSM_BRAM_CONFIG_DATA_I,
FSM_BRAM_EN_RB_O_reg,
S_DCLK_O,
\FSM_BRAM_ADDR_O_reg[0] ,
D,
\CFG_BRAM_RD_DATA_reg[23] ); |
output toggle_rd;
output [0:0]E;
output [15:0]Q;
output [7:0]\CFG_BRAM_RD_DATA_reg[21] ;
output [15:0]FSM_BRAM_CONFIG_DATA_I;
input FSM_BRAM_EN_RB_O_reg;
input S_DCLK_O;
input \FSM_BRAM_ADDR_O_reg[0] ;
input [15:0]D;
input [23:0]\CFG_BRAM_RD_DATA_reg[23] ;
wire \BRAM_DATA[15]_i_1_n_0 ;
wire [7:0]\CFG_BRAM_RD_DATA_reg[21] ;
wire [23:0]\CFG_BRAM_RD_DATA_reg[23] ;
wire \CFG_DATA_O[0]_i_1_n_0 ;
wire \CFG_DATA_O[15]_i_1_n_0 ;
wire \CFG_DATA_O[1]_i_1_n_0 ;
wire \CFG_DATA_O[2]_i_1_n_0 ;
wire \CFG_DATA_O[3]_i_1_n_0 ;
wire \CFG_DATA_O[4]_i_1_n_0 ;
wire \CFG_DATA_O[5]_i_1_n_0 ;
wire \CFG_DATA_O[6]_i_1_n_0 ;
wire \CFG_DATA_O[7]_i_1_n_0 ;
wire [15:0]D;
wire [0:0]E;
wire \FSM_BRAM_ADDR_O_reg[0] ;
wire [15:0]FSM_BRAM_CONFIG_DATA_I;
wire FSM_BRAM_EN_RB_O_reg;
wire [15:0]Q;
wire S_DCLK_O;
wire toggle_rd;
LUT1 #(
.INIT(2'h1))
\BRAM_DATA[15]_i_1
(.I0(E),
.O(\BRAM_DATA[15]_i_1_n_0 ));
FDRE \BRAM_DATA_reg[0]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \BRAM_DATA_reg[10]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \BRAM_DATA_reg[11]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \BRAM_DATA_reg[12]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \BRAM_DATA_reg[13]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \BRAM_DATA_reg[14]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \BRAM_DATA_reg[15]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \BRAM_DATA_reg[16]
(.C(S_DCLK_O),
.CE(E),
.D(D[0]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [0]),
.R(1'b0));
FDRE \BRAM_DATA_reg[17]
(.C(S_DCLK_O),
.CE(E),
.D(D[1]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [1]),
.R(1'b0));
FDRE \BRAM_DATA_reg[18]
(.C(S_DCLK_O),
.CE(E),
.D(D[2]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [2]),
.R(1'b0));
FDRE \BRAM_DATA_reg[19]
(.C(S_DCLK_O),
.CE(E),
.D(D[3]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [3]),
.R(1'b0));
FDRE \BRAM_DATA_reg[1]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \BRAM_DATA_reg[20]
(.C(S_DCLK_O),
.CE(E),
.D(D[4]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [4]),
.R(1'b0));
FDRE \BRAM_DATA_reg[21]
(.C(S_DCLK_O),
.CE(E),
.D(D[5]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [5]),
.R(1'b0));
FDRE \BRAM_DATA_reg[22]
(.C(S_DCLK_O),
.CE(E),
.D(D[6]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [6]),
.R(1'b0));
FDRE \BRAM_DATA_reg[23]
(.C(S_DCLK_O),
.CE(E),
.D(D[7]),
.Q(\CFG_BRAM_RD_DATA_reg[21] [7]),
.R(1'b0));
FDRE \BRAM_DATA_reg[2]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \BRAM_DATA_reg[3]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \BRAM_DATA_reg[4]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \BRAM_DATA_reg[5]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \BRAM_DATA_reg[6]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \BRAM_DATA_reg[7]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \BRAM_DATA_reg[8]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \BRAM_DATA_reg[9]
(.C(S_DCLK_O),
.CE(\BRAM_DATA[15]_i_1_n_0 ),
.D(D[9]),
.Q(Q[9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[0]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [0]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [16]),
.I2(toggle_rd),
.O(\CFG_DATA_O[0]_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\CFG_DATA_O[15]_i_1
(.I0(toggle_rd),
.O(\CFG_DATA_O[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[1]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [1]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [17]),
.I2(toggle_rd),
.O(\CFG_DATA_O[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[2]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [2]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [18]),
.I2(toggle_rd),
.O(\CFG_DATA_O[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[3]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [3]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [19]),
.I2(toggle_rd),
.O(\CFG_DATA_O[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[4]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [4]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [20]),
.I2(toggle_rd),
.O(\CFG_DATA_O[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[5]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [5]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [21]),
.I2(toggle_rd),
.O(\CFG_DATA_O[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[6]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [6]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [22]),
.I2(toggle_rd),
.O(\CFG_DATA_O[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\CFG_DATA_O[7]_i_1
(.I0(\CFG_BRAM_RD_DATA_reg[23] [7]),
.I1(\CFG_BRAM_RD_DATA_reg[23] [23]),
.I2(toggle_rd),
.O(\CFG_DATA_O[7]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[0]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[0]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[0]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[10]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [10]),
.Q(FSM_BRAM_CONFIG_DATA_I[10]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[11]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [11]),
.Q(FSM_BRAM_CONFIG_DATA_I[11]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[12]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [12]),
.Q(FSM_BRAM_CONFIG_DATA_I[12]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[13]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [13]),
.Q(FSM_BRAM_CONFIG_DATA_I[13]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[14]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [14]),
.Q(FSM_BRAM_CONFIG_DATA_I[14]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[15]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [15]),
.Q(FSM_BRAM_CONFIG_DATA_I[15]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[1]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[1]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[1]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[2]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[2]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[2]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[3]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[3]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[3]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[4]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[4]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[4]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[5]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[5]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[5]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[6]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[6]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[6]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[7]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_DATA_O[7]_i_1_n_0 ),
.Q(FSM_BRAM_CONFIG_DATA_I[7]),
.R(1'b0));
FDRE \CFG_DATA_O_reg[8]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [8]),
.Q(FSM_BRAM_CONFIG_DATA_I[8]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE \CFG_DATA_O_reg[9]
(.C(S_DCLK_O),
.CE(1'b1),
.D(\CFG_BRAM_RD_DATA_reg[23] [9]),
.Q(FSM_BRAM_CONFIG_DATA_I[9]),
.R(\CFG_DATA_O[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
toggle_rd_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(FSM_BRAM_EN_RB_O_reg),
.Q(toggle_rd),
.R(1'b0));
FDRE #(
.INIT(1'b0))
toggle_reg
(.C(S_DCLK_O),
.CE(1'b1),
.D(\FSM_BRAM_ADDR_O_reg[0] ),
.Q(E),
.R(1'b0));
endmodule | 8 |
2,149 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_register
(s_dclk_o,
s_rst_o,
s_den_o,
s_dwe_o,
s_daddr_o,
SL_OPORT_O,
drdy_ff9,
\slaveRegDo_ff9_reg[8]_0 ,
drdy_ffa,
\slaveRegDo_ffa_reg[15]_0 ,
slaveRegDo_ff8,
count_tt,
adv_drdy,
\I_EN_CTL_EQ1.temp_en_reg ,
read_reset_addr,
capture_qual_ctrl_1,
\shift_reg1_reg[15]_0 ,
toggle_rd_reg,
toggle_reg,
D,
halt_ctrl,
arm_ctrl,
use_probe_debug_circuit_1,
SR,
en_adv_trigger_1,
debug_data_in,
bram_rd_en,
bram_en,
scnt_cmp_temp,
wcnt_lcmp_temp,
wcnt_hcmp_temp,
regDrdy_reg_0,
read_data_en,
\shift_reg0_reg[8]_0 ,
\shift_reg0_reg[8]_1 ,
\shift_reg1_reg[15]_1 ,
\parallel_dout_reg[0] ,
qual_strg_config_cs_serial_output,
\parallel_dout_reg[0]_0 ,
capture_ctrl_config_serial_output,
mu_config_cs_shift_en,
mu_config_cs_serial_output,
tc_config_cs_shift_en,
tc_config_cs_serial_output,
cnt_config_cs_shift_en,
CFG_CNT_DIN,
SL_IPORT_I,
E,
DUMMY_I,
count_tt_reg_0,
\shift_reg0_reg[8]_2 ,
\shift_reg1_reg[15]_2 ,
\G_1PIPE_IFACE.s_den_r_reg ,
en_adv_trigger,
toggle_rd,
toggle_reg_0,
\CFG_DATA_O_reg[15] ,
\input_data_reg[31] ,
CAP_DONE_O_reg,
\captured_samples_reg[14] ,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
flag3_temp,
flag2_temp,
flag1_temp,
flag0_temp,
SEQUENCER_STATE_O,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
DOUT_O,
shift_en_reg,
shift_en_reg_0,
\G_1PIPE_IFACE.s_daddr_r_reg[10] ,
\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
shift_en_reg_1,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[11]_0 ,
shift_en_reg_2,
mu_config_cs_serial_input,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[11]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ,
CFG_CNT_DOUT);
output s_dclk_o;
output s_rst_o;
output s_den_o;
output s_dwe_o;
output [12:0]s_daddr_o;
output [16:0]SL_OPORT_O;
output drdy_ff9;
output \slaveRegDo_ff9_reg[8]_0 ;
output drdy_ffa;
output \slaveRegDo_ffa_reg[15]_0 ;
output [0:0]slaveRegDo_ff8;
output count_tt;
output adv_drdy;
output \I_EN_CTL_EQ1.temp_en_reg ;
output [14:0]read_reset_addr;
output [1:0]capture_qual_ctrl_1;
output \shift_reg1_reg[15]_0 ;
output toggle_rd_reg;
output toggle_reg;
output [15:0]D;
output halt_ctrl;
output arm_ctrl;
output use_probe_debug_circuit_1;
output [0:0]SR;
output en_adv_trigger_1;
output [1:0]debug_data_in;
output bram_rd_en;
output bram_en;
output scnt_cmp_temp;
output wcnt_lcmp_temp;
output wcnt_hcmp_temp;
output regDrdy_reg_0;
output read_data_en;
output \shift_reg0_reg[8]_0 ;
output \shift_reg0_reg[8]_1 ;
output \shift_reg1_reg[15]_1 ;
output [0:0]\parallel_dout_reg[0] ;
output qual_strg_config_cs_serial_output;
output [0:0]\parallel_dout_reg[0]_0 ;
output capture_ctrl_config_serial_output;
output [9:0]mu_config_cs_shift_en;
output [9:0]mu_config_cs_serial_output;
output [31:0]tc_config_cs_shift_en;
output [31:0]tc_config_cs_serial_output;
output [3:0]cnt_config_cs_shift_en;
output [3:0]CFG_CNT_DIN;
input [36:0]SL_IPORT_I;
input [0:0]E;
input DUMMY_I;
input count_tt_reg_0;
input \shift_reg0_reg[8]_2 ;
input \shift_reg1_reg[15]_2 ;
input \G_1PIPE_IFACE.s_den_r_reg ;
input en_adv_trigger;
input toggle_rd;
input [0:0]toggle_reg_0;
input [15:0]\CFG_DATA_O_reg[15] ;
input [15:0]\input_data_reg[31] ;
input [3:0]CAP_DONE_O_reg;
input [14:0]\captured_samples_reg[14] ;
input [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ;
input flag3_temp;
input flag2_temp;
input flag1_temp;
input flag0_temp;
input [15:0]SEQUENCER_STATE_O;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input DOUT_O;
input shift_en_reg;
input shift_en_reg_0;
input \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input [0:0]shift_en_reg_1;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[11]_0 ;
input [0:0]shift_en_reg_2;
input [9:0]mu_config_cs_serial_input;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[11]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ;
input [31:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ;
input [3:0]CFG_CNT_DOUT;
wire \ADV_TRIG_STREAM.reg_stream_ffc_n_3 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_0 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_1 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_10 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_11 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_12 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_13 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_14 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_15 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_2 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_3 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_4 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_5 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_6 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_7 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_8 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_9 ;
wire [3:0]CAP_DONE_O_reg;
wire [3:0]CFG_CNT_DIN;
wire [3:0]CFG_CNT_DOUT;
wire [15:0]\CFG_DATA_O_reg[15] ;
wire \CNT.CNT_SRL[1].cnt_srl_reg_n_0 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_0 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_1 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_10 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_11 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_12 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_13 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_14 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_15 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_16 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_2 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_3 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_4 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_5 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_6 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_7 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_8 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_9 ;
wire [15:0]D;
wire DOUT_O;
wire DUMMY_I;
wire [0:0]E;
wire FSM_BRAM_EN_RB_O_i_2_n_0;
wire FSM_BRAM_EN_RB_O_i_3_n_0;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_den_r_reg ;
wire \I_EN_CTL_EQ1.temp_en_reg ;
wire [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire \MU_SRL[11].mu_srl_reg_n_0 ;
wire \MU_SRL[11].mu_srl_reg_n_1 ;
wire \MU_SRL[11].mu_srl_reg_n_10 ;
wire \MU_SRL[11].mu_srl_reg_n_11 ;
wire \MU_SRL[11].mu_srl_reg_n_12 ;
wire \MU_SRL[11].mu_srl_reg_n_13 ;
wire \MU_SRL[11].mu_srl_reg_n_14 ;
wire \MU_SRL[11].mu_srl_reg_n_15 ;
wire \MU_SRL[11].mu_srl_reg_n_2 ;
wire \MU_SRL[11].mu_srl_reg_n_3 ;
wire \MU_SRL[11].mu_srl_reg_n_4 ;
wire \MU_SRL[11].mu_srl_reg_n_5 ;
wire \MU_SRL[11].mu_srl_reg_n_6 ;
wire \MU_SRL[11].mu_srl_reg_n_7 ;
wire \MU_SRL[11].mu_srl_reg_n_8 ;
wire \MU_SRL[11].mu_srl_reg_n_9 ;
wire \MU_SRL[15].mu_srl_reg_n_0 ;
wire \MU_SRL[15].mu_srl_reg_n_1 ;
wire \MU_SRL[15].mu_srl_reg_n_10 ;
wire \MU_SRL[15].mu_srl_reg_n_11 ;
wire \MU_SRL[15].mu_srl_reg_n_12 ;
wire \MU_SRL[15].mu_srl_reg_n_13 ;
wire \MU_SRL[15].mu_srl_reg_n_14 ;
wire \MU_SRL[15].mu_srl_reg_n_15 ;
wire \MU_SRL[15].mu_srl_reg_n_2 ;
wire \MU_SRL[15].mu_srl_reg_n_3 ;
wire \MU_SRL[15].mu_srl_reg_n_4 ;
wire \MU_SRL[15].mu_srl_reg_n_5 ;
wire \MU_SRL[15].mu_srl_reg_n_6 ;
wire \MU_SRL[15].mu_srl_reg_n_7 ;
wire \MU_SRL[15].mu_srl_reg_n_8 ;
wire \MU_SRL[15].mu_srl_reg_n_9 ;
wire \MU_SRL[3].mu_srl_reg_n_0 ;
wire \MU_SRL[3].mu_srl_reg_n_1 ;
wire \MU_SRL[3].mu_srl_reg_n_10 ;
wire \MU_SRL[3].mu_srl_reg_n_11 ;
wire \MU_SRL[3].mu_srl_reg_n_12 ;
wire \MU_SRL[3].mu_srl_reg_n_13 ;
wire \MU_SRL[3].mu_srl_reg_n_14 ;
wire \MU_SRL[3].mu_srl_reg_n_15 ;
wire \MU_SRL[3].mu_srl_reg_n_2 ;
wire \MU_SRL[3].mu_srl_reg_n_3 ;
wire \MU_SRL[3].mu_srl_reg_n_4 ;
wire \MU_SRL[3].mu_srl_reg_n_5 ;
wire \MU_SRL[3].mu_srl_reg_n_6 ;
wire \MU_SRL[3].mu_srl_reg_n_7 ;
wire \MU_SRL[3].mu_srl_reg_n_8 ;
wire \MU_SRL[3].mu_srl_reg_n_9 ;
wire [15:0]SEQUENCER_STATE_O;
wire [36:0]SL_IPORT_I;
wire [16:0]SL_OPORT_O;
wire [0:0]SR;
wire \STRG_QUAL.qual_strg_srl_reg_n_1 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_10 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_11 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_12 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_13 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_14 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_15 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_2 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_3 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_4 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_5 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_6 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_7 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_8 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_9 ;
wire \TC_SRL[11].tc_srl_reg_n_0 ;
wire \TC_SRL[11].tc_srl_reg_n_1 ;
wire \TC_SRL[11].tc_srl_reg_n_10 ;
wire \TC_SRL[11].tc_srl_reg_n_11 ;
wire \TC_SRL[11].tc_srl_reg_n_12 ;
wire \TC_SRL[11].tc_srl_reg_n_13 ;
wire \TC_SRL[11].tc_srl_reg_n_14 ;
wire \TC_SRL[11].tc_srl_reg_n_15 ;
wire \TC_SRL[11].tc_srl_reg_n_2 ;
wire \TC_SRL[11].tc_srl_reg_n_3 ;
wire \TC_SRL[11].tc_srl_reg_n_4 ;
wire \TC_SRL[11].tc_srl_reg_n_5 ;
wire \TC_SRL[11].tc_srl_reg_n_6 ;
wire \TC_SRL[11].tc_srl_reg_n_7 ;
wire \TC_SRL[11].tc_srl_reg_n_8 ;
wire \TC_SRL[11].tc_srl_reg_n_9 ;
wire \TC_SRL[15].tc_srl_reg_n_0 ;
wire \TC_SRL[15].tc_srl_reg_n_1 ;
wire \TC_SRL[15].tc_srl_reg_n_10 ;
wire \TC_SRL[15].tc_srl_reg_n_11 ;
wire \TC_SRL[15].tc_srl_reg_n_12 ;
wire \TC_SRL[15].tc_srl_reg_n_13 ;
wire \TC_SRL[15].tc_srl_reg_n_14 ;
wire \TC_SRL[15].tc_srl_reg_n_15 ;
wire \TC_SRL[15].tc_srl_reg_n_2 ;
wire \TC_SRL[15].tc_srl_reg_n_3 ;
wire \TC_SRL[15].tc_srl_reg_n_4 ;
wire \TC_SRL[15].tc_srl_reg_n_5 ;
wire \TC_SRL[15].tc_srl_reg_n_6 ;
wire \TC_SRL[15].tc_srl_reg_n_7 ;
wire \TC_SRL[15].tc_srl_reg_n_8 ;
wire \TC_SRL[15].tc_srl_reg_n_9 ;
wire \TC_SRL[19].tc_srl_reg_n_0 ;
wire \TC_SRL[19].tc_srl_reg_n_1 ;
wire \TC_SRL[19].tc_srl_reg_n_10 ;
wire \TC_SRL[19].tc_srl_reg_n_11 ;
wire \TC_SRL[19].tc_srl_reg_n_12 ;
wire \TC_SRL[19].tc_srl_reg_n_13 ;
wire \TC_SRL[19].tc_srl_reg_n_14 ;
wire \TC_SRL[19].tc_srl_reg_n_15 ;
wire \TC_SRL[19].tc_srl_reg_n_2 ;
wire \TC_SRL[19].tc_srl_reg_n_3 ;
wire \TC_SRL[19].tc_srl_reg_n_4 ;
wire \TC_SRL[19].tc_srl_reg_n_5 ;
wire \TC_SRL[19].tc_srl_reg_n_6 ;
wire \TC_SRL[19].tc_srl_reg_n_7 ;
wire \TC_SRL[19].tc_srl_reg_n_8 ;
wire \TC_SRL[19].tc_srl_reg_n_9 ;
wire \TC_SRL[23].tc_srl_reg_n_0 ;
wire \TC_SRL[23].tc_srl_reg_n_1 ;
wire \TC_SRL[23].tc_srl_reg_n_10 ;
wire \TC_SRL[23].tc_srl_reg_n_11 ;
wire \TC_SRL[23].tc_srl_reg_n_12 ;
wire \TC_SRL[23].tc_srl_reg_n_13 ;
wire \TC_SRL[23].tc_srl_reg_n_14 ;
wire \TC_SRL[23].tc_srl_reg_n_15 ;
wire \TC_SRL[23].tc_srl_reg_n_2 ;
wire \TC_SRL[23].tc_srl_reg_n_3 ;
wire \TC_SRL[23].tc_srl_reg_n_4 ;
wire \TC_SRL[23].tc_srl_reg_n_5 ;
wire \TC_SRL[23].tc_srl_reg_n_6 ;
wire \TC_SRL[23].tc_srl_reg_n_7 ;
wire \TC_SRL[23].tc_srl_reg_n_8 ;
wire \TC_SRL[23].tc_srl_reg_n_9 ;
wire \TC_SRL[27].tc_srl_reg_n_0 ;
wire \TC_SRL[27].tc_srl_reg_n_1 ;
wire \TC_SRL[27].tc_srl_reg_n_10 ;
wire \TC_SRL[27].tc_srl_reg_n_11 ;
wire \TC_SRL[27].tc_srl_reg_n_12 ;
wire \TC_SRL[27].tc_srl_reg_n_13 ;
wire \TC_SRL[27].tc_srl_reg_n_14 ;
wire \TC_SRL[27].tc_srl_reg_n_15 ;
wire \TC_SRL[27].tc_srl_reg_n_2 ;
wire \TC_SRL[27].tc_srl_reg_n_3 ;
wire \TC_SRL[27].tc_srl_reg_n_4 ;
wire \TC_SRL[27].tc_srl_reg_n_5 ;
wire \TC_SRL[27].tc_srl_reg_n_6 ;
wire \TC_SRL[27].tc_srl_reg_n_7 ;
wire \TC_SRL[27].tc_srl_reg_n_8 ;
wire \TC_SRL[27].tc_srl_reg_n_9 ;
wire \TC_SRL[31].tc_srl_reg_n_0 ;
wire \TC_SRL[31].tc_srl_reg_n_1 ;
wire \TC_SRL[31].tc_srl_reg_n_10 ;
wire \TC_SRL[31].tc_srl_reg_n_11 ;
wire \TC_SRL[31].tc_srl_reg_n_12 ;
wire \TC_SRL[31].tc_srl_reg_n_13 ;
wire \TC_SRL[31].tc_srl_reg_n_14 ;
wire \TC_SRL[31].tc_srl_reg_n_15 ;
wire \TC_SRL[31].tc_srl_reg_n_2 ;
wire \TC_SRL[31].tc_srl_reg_n_3 ;
wire \TC_SRL[31].tc_srl_reg_n_4 ;
wire \TC_SRL[31].tc_srl_reg_n_5 ;
wire \TC_SRL[31].tc_srl_reg_n_6 ;
wire \TC_SRL[31].tc_srl_reg_n_7 ;
wire \TC_SRL[31].tc_srl_reg_n_8 ;
wire \TC_SRL[31].tc_srl_reg_n_9 ;
wire \TC_SRL[3].tc_srl_reg_n_0 ;
wire \TC_SRL[3].tc_srl_reg_n_1 ;
wire \TC_SRL[3].tc_srl_reg_n_10 ;
wire \TC_SRL[3].tc_srl_reg_n_11 ;
wire \TC_SRL[3].tc_srl_reg_n_12 ;
wire \TC_SRL[3].tc_srl_reg_n_13 ;
wire \TC_SRL[3].tc_srl_reg_n_14 ;
wire \TC_SRL[3].tc_srl_reg_n_15 ;
wire \TC_SRL[3].tc_srl_reg_n_2 ;
wire \TC_SRL[3].tc_srl_reg_n_3 ;
wire \TC_SRL[3].tc_srl_reg_n_4 ;
wire \TC_SRL[3].tc_srl_reg_n_5 ;
wire \TC_SRL[3].tc_srl_reg_n_6 ;
wire \TC_SRL[3].tc_srl_reg_n_7 ;
wire \TC_SRL[3].tc_srl_reg_n_8 ;
wire \TC_SRL[3].tc_srl_reg_n_9 ;
wire \TC_SRL[7].tc_srl_reg_n_0 ;
wire \TC_SRL[7].tc_srl_reg_n_1 ;
wire \TC_SRL[7].tc_srl_reg_n_10 ;
wire \TC_SRL[7].tc_srl_reg_n_11 ;
wire \TC_SRL[7].tc_srl_reg_n_12 ;
wire \TC_SRL[7].tc_srl_reg_n_13 ;
wire \TC_SRL[7].tc_srl_reg_n_14 ;
wire \TC_SRL[7].tc_srl_reg_n_15 ;
wire \TC_SRL[7].tc_srl_reg_n_2 ;
wire \TC_SRL[7].tc_srl_reg_n_3 ;
wire \TC_SRL[7].tc_srl_reg_n_4 ;
wire \TC_SRL[7].tc_srl_reg_n_5 ;
wire \TC_SRL[7].tc_srl_reg_n_6 ;
wire \TC_SRL[7].tc_srl_reg_n_7 ;
wire \TC_SRL[7].tc_srl_reg_n_8 ;
wire \TC_SRL[7].tc_srl_reg_n_9 ;
wire adv_drdy;
wire adv_rb_drdy;
wire adv_rb_drdy1;
wire adv_rb_drdy3_reg_srl2_n_0;
wire adv_rb_drdy4;
wire arm_ctrl;
wire bram_en;
wire bram_en_i_2_n_0;
wire bram_en_i_3_n_0;
wire bram_rd_en;
wire bram_rd_en_i_2_n_0;
wire bram_rd_en_i_3_n_0;
wire bram_rd_en_i_4_n_0;
wire capture_ctrl_config_serial_output;
wire [1:0]capture_qual_ctrl_1;
wire [14:0]\captured_samples_reg[14] ;
wire [3:0]cnt_config_cs_shift_en;
wire [16:0]config_fsm_addr;
wire config_fsm_en_rb;
wire config_fsm_we;
wire count00;
wire \count0[6]_i_3_n_0 ;
wire [6:0]count0_reg__0;
wire count10;
wire \count1[6]_i_3_n_0 ;
wire [6:0]count1_reg__0;
wire count_tt;
wire count_tt_reg_0;
wire [1:0]debug_data_in;
wire [5:0]drdyCount;
wire drdyCount1;
wire \drdyCount[0]_i_1_n_0 ;
wire \drdyCount[1]_i_1_n_0 ;
wire \drdyCount[2]_i_1_n_0 ;
wire \drdyCount[3]_i_1_n_0 ;
wire \drdyCount[4]_i_1_n_0 ;
wire \drdyCount[4]_i_2_n_0 ;
wire \drdyCount[4]_i_3_n_0 ;
wire \drdyCount[5]_i_1_n_0 ;
wire \drdyCount[5]_i_2_n_0 ;
wire \drdyCount[5]_i_3_n_0 ;
wire \drdyCount[5]_i_5_n_0 ;
wire \drdyCount[5]_i_6_n_0 ;
wire drdy_ff7;
wire drdy_ff7_i_2_n_0;
wire drdy_ff7_i_3_n_0;
wire drdy_ff8;
wire drdy_ff8_i_2_n_0;
wire drdy_ff9;
wire drdy_ff9_i_2_n_0;
wire drdy_ff9_i_3_n_0;
wire drdy_ffa;
wire drdy_mux_ff;
wire drdy_mux_ff1;
wire drdy_mux_temp;
(* DONT_TOUCH *) wire dummy_temp;
(* DONT_TOUCH *) wire dummy_temp1;
wire en_adv_trigger;
wire en_adv_trigger_1;
wire flag0_temp;
wire flag1_temp;
wire flag2_temp;
wire flag3_temp;
wire halt_ctrl;
wire [15:0]\input_data_reg[31] ;
wire [9:0]mu_config_cs_serial_input;
wire [9:0]mu_config_cs_serial_output;
wire [9:0]mu_config_cs_shift_en;
wire [4:0]p_0_in;
wire [6:0]p_0_in__0;
wire [6:0]p_0_in__1;
wire [0:0]\parallel_dout_reg[0] ;
wire [0:0]\parallel_dout_reg[0]_0 ;
wire qual_strg_config_cs_serial_output;
wire read_data_en;
wire [14:0]read_reset_addr;
wire regAck_reg;
wire \regAck_reg_n_0_[1] ;
wire regAck_temp;
wire regAck_temp_reg;
wire regDrdy_i_1_n_0;
wire regDrdy_i_3_n_0;
wire regDrdy_i_5_n_0;
wire regDrdy_i_6_n_0;
wire regDrdy_reg_0;
wire regDrdy_reg_i_4_n_0;
wire regDrdy_reg_n_0;
wire reg_15_n_0;
wire reg_15_n_1;
wire reg_15_n_10;
wire reg_15_n_11;
wire reg_15_n_12;
wire reg_15_n_13;
wire reg_15_n_14;
wire reg_15_n_15;
wire reg_15_n_16;
wire reg_15_n_17;
wire reg_15_n_2;
wire reg_15_n_5;
wire reg_15_n_6;
wire reg_15_n_8;
wire reg_15_n_9;
wire reg_16_n_0;
wire reg_16_n_1;
wire reg_17_n_1;
wire reg_17_n_10;
wire reg_17_n_11;
wire reg_17_n_12;
wire reg_17_n_13;
wire reg_17_n_14;
wire reg_17_n_15;
wire reg_17_n_2;
wire reg_17_n_3;
wire reg_17_n_4;
wire reg_17_n_5;
wire reg_17_n_6;
wire reg_17_n_7;
wire reg_17_n_8;
wire reg_17_n_9;
wire reg_18_n_0;
wire reg_18_n_10;
wire reg_18_n_11;
wire reg_18_n_12;
wire reg_18_n_13;
wire reg_18_n_14;
wire reg_18_n_15;
wire reg_18_n_5;
wire reg_18_n_6;
wire reg_18_n_7;
wire reg_18_n_8;
wire reg_18_n_9;
wire reg_19_n_0;
wire reg_19_n_1;
wire reg_19_n_10;
wire reg_19_n_11;
wire reg_19_n_12;
wire reg_19_n_13;
wire reg_19_n_14;
wire reg_19_n_15;
wire reg_19_n_16;
wire reg_19_n_17;
wire reg_19_n_2;
wire reg_19_n_3;
wire reg_19_n_4;
wire reg_19_n_5;
wire reg_19_n_6;
wire reg_19_n_7;
wire reg_19_n_8;
wire reg_19_n_9;
wire reg_1a_n_10;
wire reg_1a_n_11;
wire reg_1a_n_12;
wire reg_1a_n_13;
wire reg_1a_n_14;
wire reg_1a_n_2;
wire reg_1a_n_4;
wire reg_1a_n_5;
wire reg_1a_n_6;
wire reg_1a_n_7;
wire reg_1a_n_8;
wire reg_1a_n_9;
wire reg_6_n_0;
wire reg_6_n_14;
wire reg_6_n_15;
wire reg_7_n_0;
wire reg_7_n_1;
wire reg_7_n_10;
wire reg_7_n_11;
wire reg_7_n_12;
wire reg_7_n_13;
wire reg_7_n_14;
wire reg_7_n_15;
wire reg_7_n_16;
wire reg_7_n_2;
wire reg_7_n_4;
wire reg_7_n_5;
wire reg_7_n_6;
wire reg_7_n_7;
wire reg_7_n_8;
wire reg_7_n_9;
wire reg_83_n_0;
wire reg_83_n_1;
wire reg_83_n_10;
wire reg_83_n_11;
wire reg_83_n_12;
wire reg_83_n_13;
wire reg_83_n_14;
wire reg_83_n_15;
wire reg_83_n_16;
wire reg_83_n_17;
wire reg_83_n_2;
wire reg_83_n_3;
wire reg_83_n_4;
wire reg_83_n_5;
wire reg_83_n_6;
wire reg_83_n_7;
wire reg_83_n_8;
wire reg_83_n_9;
wire reg_84_n_0;
wire reg_84_n_12;
wire reg_84_n_13;
wire reg_84_n_14;
wire reg_84_n_15;
wire reg_85_n_0;
wire reg_85_n_1;
wire reg_85_n_10;
wire reg_85_n_11;
wire reg_85_n_12;
wire reg_85_n_13;
wire reg_85_n_14;
wire reg_85_n_15;
wire reg_85_n_2;
wire reg_85_n_3;
wire reg_85_n_4;
wire reg_85_n_5;
wire reg_85_n_6;
wire reg_85_n_7;
wire reg_85_n_8;
wire reg_85_n_9;
wire reg_887_n_0;
wire reg_88d_n_0;
wire reg_88d_n_1;
wire reg_88f_n_0;
wire reg_88f_n_1;
wire reg_88f_n_10;
wire reg_88f_n_11;
wire reg_88f_n_12;
wire reg_88f_n_13;
wire reg_88f_n_14;
wire reg_88f_n_15;
wire reg_88f_n_16;
wire reg_88f_n_2;
wire reg_88f_n_3;
wire reg_88f_n_4;
wire reg_88f_n_5;
wire reg_88f_n_6;
wire reg_88f_n_7;
wire reg_88f_n_8;
wire reg_88f_n_9;
wire reg_892_n_0;
wire reg_892_n_1;
wire reg_892_n_2;
wire reg_892_n_3;
wire reg_8_n_0;
wire reg_8_n_1;
wire reg_8_n_2;
wire reg_8_n_3;
wire reg_9_n_0;
wire reg_9_n_1;
wire reg_9_n_10;
wire reg_9_n_11;
wire reg_9_n_12;
wire reg_9_n_13;
wire reg_9_n_14;
wire reg_9_n_2;
wire reg_9_n_3;
wire reg_9_n_4;
wire reg_9_n_5;
wire reg_9_n_6;
wire reg_9_n_7;
wire reg_9_n_8;
wire reg_9_n_9;
wire reg_ce;
wire reg_srl_fff_n_0;
wire reg_srl_fff_n_1;
wire reg_srl_fff_n_10;
wire reg_srl_fff_n_11;
wire reg_srl_fff_n_12;
wire reg_srl_fff_n_13;
wire reg_srl_fff_n_14;
wire reg_srl_fff_n_15;
wire reg_srl_fff_n_2;
wire reg_srl_fff_n_3;
wire reg_srl_fff_n_4;
wire reg_srl_fff_n_5;
wire reg_srl_fff_n_6;
wire reg_srl_fff_n_7;
wire reg_srl_fff_n_8;
wire reg_srl_fff_n_9;
wire reg_stream_ffd_n_0;
wire reg_stream_ffd_n_1;
wire reg_stream_ffd_n_10;
wire reg_stream_ffd_n_11;
wire reg_stream_ffd_n_12;
wire reg_stream_ffd_n_13;
wire reg_stream_ffd_n_14;
wire reg_stream_ffd_n_15;
wire reg_stream_ffd_n_16;
wire reg_stream_ffd_n_2;
wire reg_stream_ffd_n_3;
wire reg_stream_ffd_n_4;
wire reg_stream_ffd_n_5;
wire reg_stream_ffd_n_6;
wire reg_stream_ffd_n_7;
wire reg_stream_ffd_n_8;
wire reg_stream_ffd_n_9;
wire reg_stream_ffe_n_0;
wire reg_stream_ffe_n_1;
wire reg_stream_ffe_n_10;
wire reg_stream_ffe_n_11;
wire reg_stream_ffe_n_12;
wire reg_stream_ffe_n_13;
wire reg_stream_ffe_n_14;
wire reg_stream_ffe_n_15;
wire reg_stream_ffe_n_2;
wire reg_stream_ffe_n_3;
wire reg_stream_ffe_n_4;
wire reg_stream_ffe_n_5;
wire reg_stream_ffe_n_6;
wire reg_stream_ffe_n_7;
wire reg_stream_ffe_n_8;
wire reg_stream_ffe_n_9;
wire [16:13]s_daddr;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di;
wire s_dwe_o;
wire s_rst_o;
wire scnt_cmp_temp;
wire shift_en_reg;
wire shift_en_reg_0;
wire [0:0]shift_en_reg_1;
wire [0:0]shift_en_reg_2;
wire \shift_reg0_reg[8]_0 ;
wire \shift_reg0_reg[8]_1 ;
wire \shift_reg0_reg[8]_2 ;
wire \shift_reg1_reg[15]_0 ;
wire \shift_reg1_reg[15]_1 ;
wire \shift_reg1_reg[15]_2 ;
wire [15:0]slaveRegDo_18;
wire [15:0]slaveRegDo_6;
wire [15:0]slaveRegDo_80;
wire [15:0]slaveRegDo_81;
wire [15:0]slaveRegDo_82;
wire [15:5]slaveRegDo_84;
wire [15:0]slaveRegDo_890;
wire [15:0]\slaveRegDo_cntConfig[6144]_42 ;
wire [15:0]\slaveRegDo_cntConfig[6145]_43 ;
wire [15:0]\slaveRegDo_cntConfig[6146]_44 ;
wire [0:0]slaveRegDo_ff8;
wire \slaveRegDo_ff8[12]_i_1_n_0 ;
wire \slaveRegDo_ff8[7]_i_1_n_0 ;
wire \slaveRegDo_ff8_reg_n_0_[12] ;
wire \slaveRegDo_ff8_reg_n_0_[7] ;
wire [8:8]slaveRegDo_ff9;
wire \slaveRegDo_ff9_reg[8]_0 ;
wire [15:15]slaveRegDo_ffa;
wire \slaveRegDo_ffa_reg[15]_0 ;
wire [15:0]\slaveRegDo_muConfig[4096]_0 ;
wire [15:0]\slaveRegDo_muConfig[4097]_1 ;
wire [15:0]\slaveRegDo_muConfig[4098]_2 ;
wire [15:0]\slaveRegDo_muConfig[4104]_4 ;
wire [15:0]\slaveRegDo_muConfig[4105]_5 ;
wire [15:0]\slaveRegDo_muConfig[4106]_6 ;
wire [15:0]\slaveRegDo_muConfig[4110]_8 ;
wire [15:0]slaveRegDo_mux;
wire \slaveRegDo_mux[0]_i_2_n_0 ;
wire \slaveRegDo_mux[0]_i_3_n_0 ;
wire \slaveRegDo_mux[10]_i_2_n_0 ;
wire \slaveRegDo_mux[10]_i_3_n_0 ;
wire \slaveRegDo_mux[11]_i_2_n_0 ;
wire \slaveRegDo_mux[11]_i_3_n_0 ;
wire \slaveRegDo_mux[12]_i_2_n_0 ;
wire \slaveRegDo_mux[12]_i_3_n_0 ;
wire \slaveRegDo_mux[13]_i_2_n_0 ;
wire \slaveRegDo_mux[13]_i_3_n_0 ;
wire \slaveRegDo_mux[14]_i_2_n_0 ;
wire \slaveRegDo_mux[14]_i_3_n_0 ;
wire \slaveRegDo_mux[15]_i_2_n_0 ;
wire \slaveRegDo_mux[15]_i_3_n_0 ;
wire \slaveRegDo_mux[1]_i_2_n_0 ;
wire \slaveRegDo_mux[1]_i_3_n_0 ;
wire \slaveRegDo_mux[2]_i_2_n_0 ;
wire \slaveRegDo_mux[2]_i_3_n_0 ;
wire \slaveRegDo_mux[3]_i_2_n_0 ;
wire \slaveRegDo_mux[3]_i_3_n_0 ;
wire \slaveRegDo_mux[4]_i_2_n_0 ;
wire \slaveRegDo_mux[4]_i_3_n_0 ;
wire \slaveRegDo_mux[5]_i_2_n_0 ;
wire \slaveRegDo_mux[5]_i_3_n_0 ;
wire \slaveRegDo_mux[6]_i_2_n_0 ;
wire \slaveRegDo_mux[6]_i_3_n_0 ;
wire \slaveRegDo_mux[7]_i_2_n_0 ;
wire \slaveRegDo_mux[7]_i_3_n_0 ;
wire \slaveRegDo_mux[8]_i_2_n_0 ;
wire \slaveRegDo_mux[8]_i_3_n_0 ;
wire \slaveRegDo_mux[9]_i_2_n_0 ;
wire \slaveRegDo_mux[9]_i_3_n_0 ;
wire [15:0]slaveRegDo_mux_0;
wire \slaveRegDo_mux_0[15]_i_1_n_0 ;
wire \slaveRegDo_mux_0[15]_i_9_n_0 ;
wire \slaveRegDo_mux_0[3]_i_9_n_0 ;
wire \slaveRegDo_mux_0[4]_i_12_n_0 ;
wire \slaveRegDo_mux_0[4]_i_3_n_0 ;
wire \slaveRegDo_mux_0[4]_i_5_n_0 ;
wire \slaveRegDo_mux_0[4]_i_8_n_0 ;
wire [4:0]slaveRegDo_mux_1;
wire \slaveRegDo_mux_1[0]_i_1_n_0 ;
wire \slaveRegDo_mux_1[1]_i_1_n_0 ;
wire \slaveRegDo_mux_1[2]_i_1_n_0 ;
wire \slaveRegDo_mux_1[3]_i_1_n_0 ;
wire \slaveRegDo_mux_1[4]_i_1_n_0 ;
wire [15:0]slaveRegDo_mux_2;
wire \slaveRegDo_mux_2[0]_i_2_n_0 ;
wire \slaveRegDo_mux_2[0]_i_3_n_0 ;
wire \slaveRegDo_mux_2[0]_i_5_n_0 ;
wire \slaveRegDo_mux_2[15]_i_1_n_0 ;
wire \slaveRegDo_mux_2[15]_i_3_n_0 ;
wire \slaveRegDo_mux_2[15]_i_4_n_0 ;
wire \slaveRegDo_mux_2[2]_i_3_n_0 ;
wire \slaveRegDo_mux_2[4]_i_3_n_0 ;
wire \slaveRegDo_mux_2[4]_i_4_n_0 ;
wire \slaveRegDo_mux_2[4]_i_5_n_0 ;
wire \slaveRegDo_mux_2[4]_i_6_n_0 ;
wire [15:0]slaveRegDo_mux_3;
wire \slaveRegDo_mux_3[11]_i_3_n_0 ;
wire \slaveRegDo_mux_3[12]_i_2_n_0 ;
wire \slaveRegDo_mux_3[15]_i_3_n_0 ;
wire \slaveRegDo_mux_3[15]_i_4_n_0 ;
wire \slaveRegDo_mux_3[6]_i_2_n_0 ;
wire \slaveRegDo_mux_3[7]_i_3_n_0 ;
wire [15:0]slaveRegDo_mux_4;
wire [15:0]slaveRegDo_mux_5;
wire \slaveRegDo_mux_6[15]_i_2_n_0 ;
wire \slaveRegDo_mux_6[15]_i_4_n_0 ;
wire \slaveRegDo_mux_6_reg_n_0_[0] ;
wire \slaveRegDo_mux_6_reg_n_0_[10] ;
wire \slaveRegDo_mux_6_reg_n_0_[11] ;
wire \slaveRegDo_mux_6_reg_n_0_[12] ;
wire \slaveRegDo_mux_6_reg_n_0_[13] ;
wire \slaveRegDo_mux_6_reg_n_0_[14] ;
wire \slaveRegDo_mux_6_reg_n_0_[15] ;
wire \slaveRegDo_mux_6_reg_n_0_[1] ;
wire \slaveRegDo_mux_6_reg_n_0_[2] ;
wire \slaveRegDo_mux_6_reg_n_0_[3] ;
wire \slaveRegDo_mux_6_reg_n_0_[4] ;
wire \slaveRegDo_mux_6_reg_n_0_[5] ;
wire \slaveRegDo_mux_6_reg_n_0_[6] ;
wire \slaveRegDo_mux_6_reg_n_0_[7] ;
wire \slaveRegDo_mux_6_reg_n_0_[8] ;
wire \slaveRegDo_mux_6_reg_n_0_[9] ;
wire \slaveRegDo_mux_reg_n_0_[0] ;
wire \slaveRegDo_mux_reg_n_0_[10] ;
wire \slaveRegDo_mux_reg_n_0_[11] ;
wire \slaveRegDo_mux_reg_n_0_[12] ;
wire \slaveRegDo_mux_reg_n_0_[13] ;
wire \slaveRegDo_mux_reg_n_0_[14] ;
wire \slaveRegDo_mux_reg_n_0_[15] ;
wire \slaveRegDo_mux_reg_n_0_[1] ;
wire \slaveRegDo_mux_reg_n_0_[2] ;
wire \slaveRegDo_mux_reg_n_0_[3] ;
wire \slaveRegDo_mux_reg_n_0_[4] ;
wire \slaveRegDo_mux_reg_n_0_[5] ;
wire \slaveRegDo_mux_reg_n_0_[6] ;
wire \slaveRegDo_mux_reg_n_0_[7] ;
wire \slaveRegDo_mux_reg_n_0_[8] ;
wire \slaveRegDo_mux_reg_n_0_[9] ;
wire [15:15]slaveRegDo_qualStrgConfig;
wire [15:0]\slaveRegDo_tcConfig[5120]_10 ;
wire [15:0]\slaveRegDo_tcConfig[5121]_11 ;
wire [15:0]\slaveRegDo_tcConfig[5122]_12 ;
wire [15:0]\slaveRegDo_tcConfig[5124]_14 ;
wire [15:0]\slaveRegDo_tcConfig[5125]_15 ;
wire [15:0]\slaveRegDo_tcConfig[5126]_16 ;
wire [15:0]\slaveRegDo_tcConfig[5128]_18 ;
wire [15:0]\slaveRegDo_tcConfig[5129]_19 ;
wire [15:0]\slaveRegDo_tcConfig[5130]_20 ;
wire [15:0]\slaveRegDo_tcConfig[5132]_22 ;
wire [15:0]\slaveRegDo_tcConfig[5133]_23 ;
wire [15:0]\slaveRegDo_tcConfig[5134]_24 ;
wire [15:0]\slaveRegDo_tcConfig[5136]_26 ;
wire [15:0]\slaveRegDo_tcConfig[5137]_27 ;
wire [15:0]\slaveRegDo_tcConfig[5138]_28 ;
wire [15:0]\slaveRegDo_tcConfig[5140]_30 ;
wire [15:0]\slaveRegDo_tcConfig[5141]_31 ;
wire [15:0]\slaveRegDo_tcConfig[5142]_32 ;
wire [15:0]\slaveRegDo_tcConfig[5144]_34 ;
wire [15:0]\slaveRegDo_tcConfig[5145]_35 ;
wire [15:0]\slaveRegDo_tcConfig[5146]_36 ;
wire [15:0]\slaveRegDo_tcConfig[5148]_38 ;
wire [15:0]\slaveRegDo_tcConfig[5149]_39 ;
wire [15:0]\slaveRegDo_tcConfig[5150]_40 ;
wire [31:0]tc_config_cs_serial_input;
wire [31:0]tc_config_cs_serial_output;
wire [31:0]tc_config_cs_shift_en;
wire toggle_rd;
wire toggle_rd_reg;
wire toggle_reg;
wire [0:0]toggle_reg_0;
wire use_probe_debug_circuit_1;
wire wcnt_hcmp_temp;
wire wcnt_lcmp_temp;
wire xsdb_rden_ff7;
wire xsdb_rden_ff9;
wire xsdb_rden_ffa;
wire [15:0]NLW_reg_890_dout_o_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized0 \ADV_TRIG_STREAM.reg_stream_ffc
(.\BRAM_DATA_reg[15] (D),
.D({s_daddr_o[12],s_daddr_o[9:0]}),
.E(s_den_o),
.\FSM_BRAM_ADDR_O_reg[3] (bram_en_i_3_n_0),
.\FSM_BRAM_ADDR_O_reg[9] (bram_en_i_2_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[10] (\G_1PIPE_IFACE.s_daddr_r_reg[10] ),
.\I_EN_CTL_EQ1.temp_en_reg_0 (\I_EN_CTL_EQ1.temp_en_reg ),
.Q({config_fsm_addr[16:13],config_fsm_addr[0]}),
.bram_en(bram_en),
.config_fsm_we(config_fsm_we),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_3_reg[0] (\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ),
.toggle_reg(toggle_reg),
.toggle_reg_0(toggle_reg_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream \ADV_TRIG_STREAM_READBACK.reg_stream_ffb
(.\CFG_DATA_O_reg[15] (\CFG_DATA_O_reg[15] ),
.D(s_daddr_o[3:0]),
.E(adv_rb_drdy1),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\slaveRegDo_mux_3[15]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_3[15]_i_4_n_0 ),
.Q({\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_11 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_12 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_13 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_14 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_15 }),
.\parallel_dout_reg[10] (reg_srl_fff_n_14),
.\parallel_dout_reg[12] (reg_srl_fff_n_13),
.\parallel_dout_reg[13] (reg_srl_fff_n_12),
.\parallel_dout_reg[14] (reg_srl_fff_n_11),
.\parallel_dout_reg[15] (reg_srl_fff_n_10),
.\parallel_dout_reg[6] (reg_srl_fff_n_15),
.s_dclk_o(s_dclk_o),
.\slaveRegDo_ff8_reg[12] (\slaveRegDo_mux_3[12]_i_2_n_0 ),
.\slaveRegDo_ff8_reg[12]_0 (\slaveRegDo_ff8_reg_n_0_[12] ),
.\slaveRegDo_ff8_reg[7] (\slaveRegDo_ff8_reg_n_0_[7] ),
.slaveRegDo_ff9(slaveRegDo_ff9),
.\slaveRegDo_ff9_reg[8] (\slaveRegDo_mux_3[6]_i_2_n_0 ),
.slaveRegDo_ffa(slaveRegDo_ffa),
.\slaveRegDo_mux_3_reg[0] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_6 ),
.\slaveRegDo_mux_3_reg[10] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_2 ),
.\slaveRegDo_mux_3_reg[12] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_0 ),
.\slaveRegDo_mux_3_reg[13] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_10 ),
.\slaveRegDo_mux_3_reg[14] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_3 ),
.\slaveRegDo_mux_3_reg[15] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_4 ),
.\slaveRegDo_mux_3_reg[1] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_7 ),
.\slaveRegDo_mux_3_reg[2] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_8 ),
.\slaveRegDo_mux_3_reg[3] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_5 ),
.\slaveRegDo_mux_3_reg[6] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_1 ),
.\slaveRegDo_mux_3_reg[8] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_9 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized41 \CNT.CNT_SRL[0].cnt_srl_reg
(.CFG_CNT_DIN(CFG_CNT_DIN[0]),
.CFG_CNT_DOUT(CFG_CNT_DOUT[0]),
.E(cnt_config_cs_shift_en[0]),
.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_cntConfig[6144]_42 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized42 \CNT.CNT_SRL[1].cnt_srl_reg
(.CFG_CNT_DIN(CFG_CNT_DIN[1]),
.CFG_CNT_DOUT(CFG_CNT_DOUT[1]),
.E(cnt_config_cs_shift_en[1]),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_den_r_reg (s_den_o),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\count0_reg[6] (\CNT.CNT_SRL[1].cnt_srl_reg_n_0 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[1:0]}),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_cntConfig[6145]_43 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized43 \CNT.CNT_SRL[2].cnt_srl_reg
(.CFG_CNT_DIN(CFG_CNT_DIN[2]),
.CFG_CNT_DOUT(CFG_CNT_DOUT[2]),
.D(s_daddr_o[12:10]),
.E(cnt_config_cs_shift_en[2]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_cntConfig[6146]_44 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized44 \CNT.CNT_SRL[3].cnt_srl_reg
(.CFG_CNT_DIN(CFG_CNT_DIN[3]),
.CFG_CNT_DOUT(CFG_CNT_DOUT[3]),
.D(\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
.E(cnt_config_cs_shift_en[3]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_6[15]_i_4_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\slaveRegDo_mux_6[15]_i_2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.Q(slaveRegDo_qualStrgConfig),
.\parallel_dout_reg[15]_0 (\slaveRegDo_cntConfig[6146]_44 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_cntConfig[6144]_42 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[1:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_do_o(\slaveRegDo_cntConfig[6145]_43 ),
.s_dwe_o(s_dwe_o),
.\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\slaveRegDo_mux_6_reg[0] (\CNT.CNT_SRL[3].cnt_srl_reg_n_15 ),
.\slaveRegDo_mux_6_reg[10] (\CNT.CNT_SRL[3].cnt_srl_reg_n_5 ),
.\slaveRegDo_mux_6_reg[11] (\CNT.CNT_SRL[3].cnt_srl_reg_n_4 ),
.\slaveRegDo_mux_6_reg[12] (\CNT.CNT_SRL[3].cnt_srl_reg_n_3 ),
.\slaveRegDo_mux_6_reg[13] (\CNT.CNT_SRL[3].cnt_srl_reg_n_2 ),
.\slaveRegDo_mux_6_reg[14] (\CNT.CNT_SRL[3].cnt_srl_reg_n_1 ),
.\slaveRegDo_mux_6_reg[1] (\CNT.CNT_SRL[3].cnt_srl_reg_n_14 ),
.\slaveRegDo_mux_6_reg[2] (\CNT.CNT_SRL[3].cnt_srl_reg_n_13 ),
.\slaveRegDo_mux_6_reg[3] (\CNT.CNT_SRL[3].cnt_srl_reg_n_12 ),
.\slaveRegDo_mux_6_reg[4] (\CNT.CNT_SRL[3].cnt_srl_reg_n_11 ),
.\slaveRegDo_mux_6_reg[5] (\CNT.CNT_SRL[3].cnt_srl_reg_n_10 ),
.\slaveRegDo_mux_6_reg[6] (\CNT.CNT_SRL[3].cnt_srl_reg_n_9 ),
.\slaveRegDo_mux_6_reg[7] (\CNT.CNT_SRL[3].cnt_srl_reg_n_8 ),
.\slaveRegDo_mux_6_reg[8] (\CNT.CNT_SRL[3].cnt_srl_reg_n_7 ),
.\slaveRegDo_mux_6_reg[9] (\CNT.CNT_SRL[3].cnt_srl_reg_n_6 ));
FDRE \FSM_BRAM_ADDR_O_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[0]),
.Q(config_fsm_addr[0]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[10]),
.Q(config_fsm_addr[10]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[11]),
.Q(config_fsm_addr[11]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[12]),
.Q(config_fsm_addr[12]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr[13]),
.Q(config_fsm_addr[13]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr[14]),
.Q(config_fsm_addr[14]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr[15]),
.Q(config_fsm_addr[15]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[16]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr[16]),
.Q(config_fsm_addr[16]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[1]),
.Q(config_fsm_addr[1]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[2]),
.Q(config_fsm_addr[2]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[3]),
.Q(config_fsm_addr[3]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[4]),
.Q(config_fsm_addr[4]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[5]),
.Q(config_fsm_addr[5]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[6]),
.Q(config_fsm_addr[6]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[7]),
.Q(config_fsm_addr[7]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[8]),
.Q(config_fsm_addr[8]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[9]),
.Q(config_fsm_addr[9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair197" *)
LUT4 #(
.INIT(16'h4000))
FSM_BRAM_EN_RB_O_i_1
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(FSM_BRAM_EN_RB_O_i_2_n_0),
.O(reg_ce));
LUT6 #(
.INIT(64'h0000000004000000))
FSM_BRAM_EN_RB_O_i_2
(.I0(FSM_BRAM_EN_RB_O_i_3_n_0),
.I1(s_daddr_o[7]),
.I2(s_daddr_o[12]),
.I3(s_daddr_o[11]),
.I4(s_daddr_o[3]),
.I5(reg_stream_ffd_n_2),
.O(FSM_BRAM_EN_RB_O_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair187" *)
LUT3 #(
.INIT(8'h7F))
FSM_BRAM_EN_RB_O_i_3
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[6]),
.I2(s_daddr_o[5]),
.O(FSM_BRAM_EN_RB_O_i_3_n_0));
FDRE FSM_BRAM_EN_RB_O_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_ce),
.Q(config_fsm_en_rb),
.R(1'b0));
FDRE FSM_BRAM_WE_O_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(s_dwe_o),
.Q(config_fsm_we),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s \MU_SRL[0].mu_srl_reg
(.E(mu_config_cs_shift_en[0]),
.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[0]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[0]),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4096]_0 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized5 \MU_SRL[10].mu_srl_reg
(.E(mu_config_cs_shift_en[6]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[6]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[6]),
.s_daddr_o(s_daddr_o[12:10]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4106]_6 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized6 \MU_SRL[11].mu_srl_reg
(.E(mu_config_cs_shift_en[7]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\MU_SRL[15].mu_srl_reg_n_15 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (\MU_SRL[15].mu_srl_reg_n_14 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (\MU_SRL[15].mu_srl_reg_n_13 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_10 (\MU_SRL[15].mu_srl_reg_n_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_11 (\MU_SRL[15].mu_srl_reg_n_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_12 (\MU_SRL[15].mu_srl_reg_n_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_13 (\MU_SRL[15].mu_srl_reg_n_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_14 (\MU_SRL[15].mu_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 (\MU_SRL[15].mu_srl_reg_n_12 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 (\MU_SRL[15].mu_srl_reg_n_11 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 (\MU_SRL[15].mu_srl_reg_n_10 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 (\MU_SRL[15].mu_srl_reg_n_9 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 (\MU_SRL[15].mu_srl_reg_n_8 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 (\MU_SRL[15].mu_srl_reg_n_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_8 (\MU_SRL[15].mu_srl_reg_n_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_9 (\MU_SRL[15].mu_srl_reg_n_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.Q(\slaveRegDo_muConfig[4105]_5 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[7]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[7]),
.\parallel_dout_reg[0]_0 (\MU_SRL[3].mu_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\MU_SRL[3].mu_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\MU_SRL[3].mu_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\MU_SRL[3].mu_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\MU_SRL[3].mu_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\MU_SRL[3].mu_srl_reg_n_1 ),
.\parallel_dout_reg[15]_0 (\MU_SRL[3].mu_srl_reg_n_0 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_muConfig[4104]_4 ),
.\parallel_dout_reg[1]_0 (\MU_SRL[3].mu_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\MU_SRL[3].mu_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\MU_SRL[3].mu_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\MU_SRL[3].mu_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\MU_SRL[3].mu_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\MU_SRL[3].mu_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\MU_SRL[3].mu_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\MU_SRL[3].mu_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\MU_SRL[3].mu_srl_reg_n_6 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[3:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4106]_6 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_4_reg[0] (\MU_SRL[11].mu_srl_reg_n_15 ),
.\slaveRegDo_mux_4_reg[10] (\MU_SRL[11].mu_srl_reg_n_5 ),
.\slaveRegDo_mux_4_reg[11] (\MU_SRL[11].mu_srl_reg_n_4 ),
.\slaveRegDo_mux_4_reg[12] (\MU_SRL[11].mu_srl_reg_n_3 ),
.\slaveRegDo_mux_4_reg[13] (\MU_SRL[11].mu_srl_reg_n_2 ),
.\slaveRegDo_mux_4_reg[14] (\MU_SRL[11].mu_srl_reg_n_1 ),
.\slaveRegDo_mux_4_reg[15] (\MU_SRL[11].mu_srl_reg_n_0 ),
.\slaveRegDo_mux_4_reg[1] (\MU_SRL[11].mu_srl_reg_n_14 ),
.\slaveRegDo_mux_4_reg[2] (\MU_SRL[11].mu_srl_reg_n_13 ),
.\slaveRegDo_mux_4_reg[3] (\MU_SRL[11].mu_srl_reg_n_12 ),
.\slaveRegDo_mux_4_reg[4] (\MU_SRL[11].mu_srl_reg_n_11 ),
.\slaveRegDo_mux_4_reg[5] (\MU_SRL[11].mu_srl_reg_n_10 ),
.\slaveRegDo_mux_4_reg[6] (\MU_SRL[11].mu_srl_reg_n_9 ),
.\slaveRegDo_mux_4_reg[7] (\MU_SRL[11].mu_srl_reg_n_8 ),
.\slaveRegDo_mux_4_reg[8] (\MU_SRL[11].mu_srl_reg_n_7 ),
.\slaveRegDo_mux_4_reg[9] (\MU_SRL[11].mu_srl_reg_n_6 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized7 \MU_SRL[14].mu_srl_reg
(.E(mu_config_cs_shift_en[8]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[8]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[8]),
.s_daddr_o(s_daddr_o[12:10]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4110]_8 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized8 \MU_SRL[15].mu_srl_reg
(.E(mu_config_cs_shift_en[9]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[9]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[9]),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[3:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4110]_8 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_4_reg[0] (\MU_SRL[15].mu_srl_reg_n_0 ),
.\slaveRegDo_mux_4_reg[10] (\MU_SRL[15].mu_srl_reg_n_10 ),
.\slaveRegDo_mux_4_reg[11] (\MU_SRL[15].mu_srl_reg_n_11 ),
.\slaveRegDo_mux_4_reg[12] (\MU_SRL[15].mu_srl_reg_n_12 ),
.\slaveRegDo_mux_4_reg[13] (\MU_SRL[15].mu_srl_reg_n_13 ),
.\slaveRegDo_mux_4_reg[14] (\MU_SRL[15].mu_srl_reg_n_14 ),
.\slaveRegDo_mux_4_reg[15] (\MU_SRL[15].mu_srl_reg_n_15 ),
.\slaveRegDo_mux_4_reg[1] (\MU_SRL[15].mu_srl_reg_n_1 ),
.\slaveRegDo_mux_4_reg[2] (\MU_SRL[15].mu_srl_reg_n_2 ),
.\slaveRegDo_mux_4_reg[3] (\MU_SRL[15].mu_srl_reg_n_3 ),
.\slaveRegDo_mux_4_reg[4] (\MU_SRL[15].mu_srl_reg_n_4 ),
.\slaveRegDo_mux_4_reg[5] (\MU_SRL[15].mu_srl_reg_n_5 ),
.\slaveRegDo_mux_4_reg[6] (\MU_SRL[15].mu_srl_reg_n_6 ),
.\slaveRegDo_mux_4_reg[7] (\MU_SRL[15].mu_srl_reg_n_7 ),
.\slaveRegDo_mux_4_reg[8] (\MU_SRL[15].mu_srl_reg_n_8 ),
.\slaveRegDo_mux_4_reg[9] (\MU_SRL[15].mu_srl_reg_n_9 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized0 \MU_SRL[1].mu_srl_reg
(.E(mu_config_cs_shift_en[1]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\CNT.CNT_SRL[1].cnt_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[1]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[1]),
.s_daddr_o(s_daddr_o[12:10]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4097]_1 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized1 \MU_SRL[2].mu_srl_reg
(.E(mu_config_cs_shift_en[2]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[2]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[2]),
.s_daddr_o(s_daddr_o[12:10]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4098]_2 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized2 \MU_SRL[3].mu_srl_reg
(.E(mu_config_cs_shift_en[3]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[3]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[3]),
.\parallel_dout_reg[15]_0 (\slaveRegDo_muConfig[4097]_1 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_muConfig[4096]_0 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[1:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4098]_2 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_4_reg[0] (\MU_SRL[3].mu_srl_reg_n_15 ),
.\slaveRegDo_mux_4_reg[10] (\MU_SRL[3].mu_srl_reg_n_5 ),
.\slaveRegDo_mux_4_reg[11] (\MU_SRL[3].mu_srl_reg_n_4 ),
.\slaveRegDo_mux_4_reg[12] (\MU_SRL[3].mu_srl_reg_n_3 ),
.\slaveRegDo_mux_4_reg[13] (\MU_SRL[3].mu_srl_reg_n_2 ),
.\slaveRegDo_mux_4_reg[14] (\MU_SRL[3].mu_srl_reg_n_1 ),
.\slaveRegDo_mux_4_reg[15] (\MU_SRL[3].mu_srl_reg_n_0 ),
.\slaveRegDo_mux_4_reg[1] (\MU_SRL[3].mu_srl_reg_n_14 ),
.\slaveRegDo_mux_4_reg[2] (\MU_SRL[3].mu_srl_reg_n_13 ),
.\slaveRegDo_mux_4_reg[3] (\MU_SRL[3].mu_srl_reg_n_12 ),
.\slaveRegDo_mux_4_reg[4] (\MU_SRL[3].mu_srl_reg_n_11 ),
.\slaveRegDo_mux_4_reg[5] (\MU_SRL[3].mu_srl_reg_n_10 ),
.\slaveRegDo_mux_4_reg[6] (\MU_SRL[3].mu_srl_reg_n_9 ),
.\slaveRegDo_mux_4_reg[7] (\MU_SRL[3].mu_srl_reg_n_8 ),
.\slaveRegDo_mux_4_reg[8] (\MU_SRL[3].mu_srl_reg_n_7 ),
.\slaveRegDo_mux_4_reg[9] (\MU_SRL[3].mu_srl_reg_n_6 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized3 \MU_SRL[8].mu_srl_reg
(.E(mu_config_cs_shift_en[4]),
.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[4]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[4]),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4104]_4 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized4 \MU_SRL[9].mu_srl_reg
(.E(mu_config_cs_shift_en[5]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\CNT.CNT_SRL[1].cnt_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[5]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[5]),
.s_daddr_o(s_daddr_o[12:10]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4105]_5 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized45 \STRG_QUAL.qual_strg_srl_reg
(.D({\STRG_QUAL.qual_strg_srl_reg_n_1 ,\STRG_QUAL.qual_strg_srl_reg_n_2 ,\STRG_QUAL.qual_strg_srl_reg_n_3 ,\STRG_QUAL.qual_strg_srl_reg_n_4 ,\STRG_QUAL.qual_strg_srl_reg_n_5 ,\STRG_QUAL.qual_strg_srl_reg_n_6 ,\STRG_QUAL.qual_strg_srl_reg_n_7 ,\STRG_QUAL.qual_strg_srl_reg_n_8 ,\STRG_QUAL.qual_strg_srl_reg_n_9 ,\STRG_QUAL.qual_strg_srl_reg_n_10 ,\STRG_QUAL.qual_strg_srl_reg_n_11 ,\STRG_QUAL.qual_strg_srl_reg_n_12 ,\STRG_QUAL.qual_strg_srl_reg_n_13 ,\STRG_QUAL.qual_strg_srl_reg_n_14 ,\STRG_QUAL.qual_strg_srl_reg_n_15 }),
.E(\parallel_dout_reg[0] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_6[15]_i_4_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\slaveRegDo_mux_6[15]_i_2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.Q(slaveRegDo_qualStrgConfig),
.\parallel_dout_reg[0]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_1 ),
.\parallel_dout_reg[1]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_6 ),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_dwe_o(s_dwe_o),
.shift_en_reg_0(shift_en_reg_1));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized9 \TC_SRL[0].tc_srl_reg
(.E(tc_config_cs_shift_en[0]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5120]_10 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[0]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized19 \TC_SRL[10].tc_srl_reg
(.E(tc_config_cs_shift_en[10]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5130]_20 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[10]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[10]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized20 \TC_SRL[11].tc_srl_reg
(.E(tc_config_cs_shift_en[11]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.Q(\slaveRegDo_tcConfig[5129]_19 ),
.\parallel_dout_reg[0]_0 (\TC_SRL[15].tc_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\TC_SRL[15].tc_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\TC_SRL[15].tc_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\TC_SRL[15].tc_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\TC_SRL[15].tc_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\TC_SRL[15].tc_srl_reg_n_1 ),
.\parallel_dout_reg[15]_0 (\TC_SRL[15].tc_srl_reg_n_0 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5128]_18 ),
.\parallel_dout_reg[1]_0 (\TC_SRL[15].tc_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\TC_SRL[15].tc_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\TC_SRL[15].tc_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\TC_SRL[15].tc_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\TC_SRL[15].tc_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\TC_SRL[15].tc_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\TC_SRL[15].tc_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\TC_SRL[15].tc_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\TC_SRL[15].tc_srl_reg_n_6 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[2:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5130]_20 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[11].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[11].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[11].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[11].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[11].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[11].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[11].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[11].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[11].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[11].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[11].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[11].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[11].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[11].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[11].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[11].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[11]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[11]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized21 \TC_SRL[12].tc_srl_reg
(.E(tc_config_cs_shift_en[12]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5132]_22 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[12]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[12]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized22 \TC_SRL[13].tc_srl_reg
(.E(tc_config_cs_shift_en[13]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5133]_23 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[13]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[13]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized23 \TC_SRL[14].tc_srl_reg
(.E(tc_config_cs_shift_en[14]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5134]_24 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[14]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[14]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized24 \TC_SRL[15].tc_srl_reg
(.E(tc_config_cs_shift_en[15]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[15]_0 (\slaveRegDo_tcConfig[5133]_23 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5132]_22 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[1:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5134]_24 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[15].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[15].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[15].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[15].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[15].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[15].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[15].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[15].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[15].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[15].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[15].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[15].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[15].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[15].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[15].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[15].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[15]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[15]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized25 \TC_SRL[16].tc_srl_reg
(.E(tc_config_cs_shift_en[16]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5136]_26 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[16]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[16]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized26 \TC_SRL[17].tc_srl_reg
(.E(tc_config_cs_shift_en[17]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5137]_27 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[17]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[17]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized27 \TC_SRL[18].tc_srl_reg
(.E(tc_config_cs_shift_en[18]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5138]_28 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[18]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[18]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized28 \TC_SRL[19].tc_srl_reg
(.E(tc_config_cs_shift_en[19]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[0]_0 (\TC_SRL[23].tc_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\TC_SRL[23].tc_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\TC_SRL[23].tc_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\TC_SRL[23].tc_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\TC_SRL[23].tc_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\TC_SRL[23].tc_srl_reg_n_1 ),
.\parallel_dout_reg[15]_0 (\TC_SRL[23].tc_srl_reg_n_0 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5137]_27 ),
.\parallel_dout_reg[15]_2 (\slaveRegDo_tcConfig[5136]_26 ),
.\parallel_dout_reg[1]_0 (\TC_SRL[23].tc_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\TC_SRL[23].tc_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\TC_SRL[23].tc_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\TC_SRL[23].tc_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\TC_SRL[23].tc_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\TC_SRL[23].tc_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\TC_SRL[23].tc_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\TC_SRL[23].tc_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\TC_SRL[23].tc_srl_reg_n_6 ),
.s_daddr_o(s_daddr_o[5:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5138]_28 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[19].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[19].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[19].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[19].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[19].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[19].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[19].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[19].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[19].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[19].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[19].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[19].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[19].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[19].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[19].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[19].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[19]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[19]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized10 \TC_SRL[1].tc_srl_reg
(.E(tc_config_cs_shift_en[1]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5121]_11 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[1]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[1]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized29 \TC_SRL[20].tc_srl_reg
(.E(tc_config_cs_shift_en[20]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5140]_30 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[20]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[20]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized30 \TC_SRL[21].tc_srl_reg
(.E(tc_config_cs_shift_en[21]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5141]_31 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[21]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[21]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized31 \TC_SRL[22].tc_srl_reg
(.E(tc_config_cs_shift_en[22]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5142]_32 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[22]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[22]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized32 \TC_SRL[23].tc_srl_reg
(.E(tc_config_cs_shift_en[23]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[15]_0 (\slaveRegDo_tcConfig[5141]_31 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5140]_30 ),
.s_daddr_o(s_daddr_o[5:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5142]_32 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[23].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[23].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[23].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[23].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[23].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[23].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[23].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[23].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[23].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[23].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[23].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[23].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[23].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[23].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[23].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[23].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[23]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[23]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized33 \TC_SRL[24].tc_srl_reg
(.E(tc_config_cs_shift_en[24]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5144]_34 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[24]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[24]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized34 \TC_SRL[25].tc_srl_reg
(.E(tc_config_cs_shift_en[25]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5145]_35 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[25]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[25]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized35 \TC_SRL[26].tc_srl_reg
(.E(tc_config_cs_shift_en[26]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5146]_36 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[26]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[26]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized36 \TC_SRL[27].tc_srl_reg
(.D({\TC_SRL[27].tc_srl_reg_n_0 ,\TC_SRL[27].tc_srl_reg_n_1 ,\TC_SRL[27].tc_srl_reg_n_2 ,\TC_SRL[27].tc_srl_reg_n_3 ,\TC_SRL[27].tc_srl_reg_n_4 ,\TC_SRL[27].tc_srl_reg_n_5 ,\TC_SRL[27].tc_srl_reg_n_6 ,\TC_SRL[27].tc_srl_reg_n_7 ,\TC_SRL[27].tc_srl_reg_n_8 ,\TC_SRL[27].tc_srl_reg_n_9 ,\TC_SRL[27].tc_srl_reg_n_10 ,\TC_SRL[27].tc_srl_reg_n_11 ,\TC_SRL[27].tc_srl_reg_n_12 ,\TC_SRL[27].tc_srl_reg_n_13 ,\TC_SRL[27].tc_srl_reg_n_14 ,\TC_SRL[27].tc_srl_reg_n_15 }),
.E(tc_config_cs_shift_en[27]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\TC_SRL[19].tc_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\TC_SRL[11].tc_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (\TC_SRL[3].tc_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_10 (\TC_SRL[3].tc_srl_reg_n_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_11 (\TC_SRL[19].tc_srl_reg_n_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_12 (\TC_SRL[11].tc_srl_reg_n_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_13 (\TC_SRL[3].tc_srl_reg_n_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_14 (\TC_SRL[19].tc_srl_reg_n_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_15 (\TC_SRL[11].tc_srl_reg_n_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_16 (\TC_SRL[3].tc_srl_reg_n_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_17 (\TC_SRL[19].tc_srl_reg_n_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_18 (\TC_SRL[11].tc_srl_reg_n_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_19 (\TC_SRL[3].tc_srl_reg_n_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 (\TC_SRL[19].tc_srl_reg_n_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_20 (\TC_SRL[19].tc_srl_reg_n_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_21 (\TC_SRL[11].tc_srl_reg_n_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_22 (\TC_SRL[3].tc_srl_reg_n_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_23 (\TC_SRL[19].tc_srl_reg_n_8 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_24 (\TC_SRL[11].tc_srl_reg_n_8 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_25 (\TC_SRL[3].tc_srl_reg_n_8 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_26 (\TC_SRL[19].tc_srl_reg_n_9 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_27 (\TC_SRL[11].tc_srl_reg_n_9 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_28 (\TC_SRL[3].tc_srl_reg_n_9 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_29 (\TC_SRL[19].tc_srl_reg_n_10 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 (\TC_SRL[11].tc_srl_reg_n_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_30 (\TC_SRL[11].tc_srl_reg_n_10 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_31 (\TC_SRL[3].tc_srl_reg_n_10 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_32 (\TC_SRL[19].tc_srl_reg_n_11 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_33 (\TC_SRL[11].tc_srl_reg_n_11 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_34 (\TC_SRL[3].tc_srl_reg_n_11 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_35 (\TC_SRL[19].tc_srl_reg_n_12 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_36 (\TC_SRL[11].tc_srl_reg_n_12 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_37 (\TC_SRL[3].tc_srl_reg_n_12 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_38 (\TC_SRL[19].tc_srl_reg_n_13 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_39 (\TC_SRL[11].tc_srl_reg_n_13 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 (\TC_SRL[3].tc_srl_reg_n_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_40 (\TC_SRL[3].tc_srl_reg_n_13 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_41 (\TC_SRL[19].tc_srl_reg_n_14 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_42 (\TC_SRL[11].tc_srl_reg_n_14 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_43 (\TC_SRL[3].tc_srl_reg_n_14 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_44 (\TC_SRL[19].tc_srl_reg_n_15 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_45 (\TC_SRL[11].tc_srl_reg_n_15 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_46 (\TC_SRL[3].tc_srl_reg_n_15 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_5 (\TC_SRL[19].tc_srl_reg_n_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_6 (\TC_SRL[11].tc_srl_reg_n_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_7 (\TC_SRL[3].tc_srl_reg_n_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_8 (\TC_SRL[19].tc_srl_reg_n_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_9 (\TC_SRL[11].tc_srl_reg_n_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[0]_0 (\TC_SRL[31].tc_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\TC_SRL[31].tc_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\TC_SRL[31].tc_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\TC_SRL[31].tc_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\TC_SRL[31].tc_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\TC_SRL[31].tc_srl_reg_n_1 ),
.\parallel_dout_reg[15]_0 (\TC_SRL[31].tc_srl_reg_n_0 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5145]_35 ),
.\parallel_dout_reg[15]_2 (\slaveRegDo_tcConfig[5144]_34 ),
.\parallel_dout_reg[1]_0 (\TC_SRL[31].tc_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\TC_SRL[31].tc_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\TC_SRL[31].tc_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\TC_SRL[31].tc_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\TC_SRL[31].tc_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\TC_SRL[31].tc_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\TC_SRL[31].tc_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\TC_SRL[31].tc_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\TC_SRL[31].tc_srl_reg_n_6 ),
.s_daddr_o(s_daddr_o[5:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5146]_36 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[27]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[27]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized37 \TC_SRL[28].tc_srl_reg
(.E(tc_config_cs_shift_en[28]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5148]_38 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[28]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[28]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized38 \TC_SRL[29].tc_srl_reg
(.E(tc_config_cs_shift_en[29]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5149]_39 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[29]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[29]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized11 \TC_SRL[2].tc_srl_reg
(.E(tc_config_cs_shift_en[2]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5122]_12 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[2]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[2]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized39 \TC_SRL[30].tc_srl_reg
(.E(tc_config_cs_shift_en[30]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5150]_40 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[30]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[30]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized40 \TC_SRL[31].tc_srl_reg
(.E(tc_config_cs_shift_en[31]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[15]_0 (\slaveRegDo_tcConfig[5149]_39 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5148]_38 ),
.s_daddr_o(s_daddr_o[5:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5150]_40 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[31].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[31].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[31].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[31].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[31].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[31].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[31].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[31].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[31].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[31].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[31].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[31].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[31].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[31].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[31].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[31].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[31]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[31]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized12 \TC_SRL[3].tc_srl_reg
(.E(tc_config_cs_shift_en[3]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[0]_0 (\TC_SRL[7].tc_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\TC_SRL[7].tc_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\TC_SRL[7].tc_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\TC_SRL[7].tc_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\TC_SRL[7].tc_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\TC_SRL[7].tc_srl_reg_n_1 ),
.\parallel_dout_reg[15]_0 (\TC_SRL[7].tc_srl_reg_n_0 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5121]_11 ),
.\parallel_dout_reg[15]_2 (\slaveRegDo_tcConfig[5120]_10 ),
.\parallel_dout_reg[1]_0 (\TC_SRL[7].tc_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\TC_SRL[7].tc_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\TC_SRL[7].tc_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\TC_SRL[7].tc_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\TC_SRL[7].tc_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\TC_SRL[7].tc_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\TC_SRL[7].tc_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\TC_SRL[7].tc_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\TC_SRL[7].tc_srl_reg_n_6 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[2:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5122]_12 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[3].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[3].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[3].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[3].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[3].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[3].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[3].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[3].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[3].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[3].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[3].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[3].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[3].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[3].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[3].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[3].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[3]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[3]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized13 \TC_SRL[4].tc_srl_reg
(.E(tc_config_cs_shift_en[4]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5124]_14 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[4]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[4]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized14 \TC_SRL[5].tc_srl_reg
(.E(tc_config_cs_shift_en[5]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5125]_15 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[5]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[5]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized15 \TC_SRL[6].tc_srl_reg
(.E(tc_config_cs_shift_en[6]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5126]_16 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[6]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[6]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized16 \TC_SRL[7].tc_srl_reg
(.E(tc_config_cs_shift_en[7]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[15]_0 (\slaveRegDo_tcConfig[5125]_15 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5124]_14 ),
.s_daddr_o(s_daddr_o[5:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5126]_16 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[7].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[7].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[7].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[7].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[7].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[7].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[7].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[7].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[7].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[7].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[7].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[7].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[7].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[7].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[7].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[7].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[7]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[7]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized17 \TC_SRL[8].tc_srl_reg
(.E(tc_config_cs_shift_en[8]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5128]_18 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[8]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[8]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized18 \TC_SRL[9].tc_srl_reg
(.E(tc_config_cs_shift_en[9]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5129]_19 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[9]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[9]));
(* C_BUILD_REVISION = "0" *)
(* C_CORE_INFO1 = "0" *)
(* C_CORE_INFO2 = "0" *)
(* C_CORE_MAJOR_VER = "6" *)
(* C_CORE_MINOR_VER = "2" *)
(* C_CORE_TYPE = "1" *)
(* C_CSE_DRV_VER = "2" *)
(* C_MAJOR_VERSION = "2016" *)
(* C_MINOR_VERSION = "4" *)
(* C_NEXT_SLAVE = "0" *)
(* C_PIPE_IFACE = "1" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* C_XSDB_SLAVE_TYPE = "17" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE
(.s_daddr_o({s_daddr,s_daddr_o}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_do_i({\slaveRegDo_mux_reg_n_0_[15] ,\slaveRegDo_mux_reg_n_0_[14] ,\slaveRegDo_mux_reg_n_0_[13] ,\slaveRegDo_mux_reg_n_0_[12] ,\slaveRegDo_mux_reg_n_0_[11] ,\slaveRegDo_mux_reg_n_0_[10] ,\slaveRegDo_mux_reg_n_0_[9] ,\slaveRegDo_mux_reg_n_0_[8] ,\slaveRegDo_mux_reg_n_0_[7] ,\slaveRegDo_mux_reg_n_0_[6] ,\slaveRegDo_mux_reg_n_0_[5] ,\slaveRegDo_mux_reg_n_0_[4] ,\slaveRegDo_mux_reg_n_0_[3] ,\slaveRegDo_mux_reg_n_0_[2] ,\slaveRegDo_mux_reg_n_0_[1] ,\slaveRegDo_mux_reg_n_0_[0] }),
.s_drdy_i(regDrdy_reg_n_0),
.s_dwe_o(s_dwe_o),
.s_rst_o(s_rst_o),
.sl_iport_i(SL_IPORT_I),
.sl_oport_o(SL_OPORT_O));
FDRE adv_drdy_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\G_1PIPE_IFACE.s_den_r_reg ),
.Q(adv_drdy),
.R(1'b0));
FDRE adv_rb_drdy1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(adv_rb_drdy),
.Q(adv_rb_drdy1),
.R(1'b0));
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_regs/adv_rb_drdy3_reg_srl2 " *)
SRL16E adv_rb_drdy3_reg_srl2
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(1'b1),
.CLK(s_dclk_o),
.D(adv_rb_drdy1),
.Q(adv_rb_drdy3_reg_srl2_n_0));
FDRE adv_rb_drdy4_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(adv_rb_drdy3_reg_srl2_n_0),
.Q(adv_rb_drdy4),
.R(1'b0));
FDRE adv_rb_drdy_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(drdy_mux_ff1),
.Q(adv_rb_drdy),
.R(1'b0));
LUT6 #(
.INIT(64'h0000800000000000))
bram_en_i_2
(.I0(config_fsm_addr[9]),
.I1(config_fsm_addr[10]),
.I2(config_fsm_addr[7]),
.I3(config_fsm_addr[8]),
.I4(config_fsm_addr[12]),
.I5(config_fsm_addr[11]),
.O(bram_en_i_2_n_0));
LUT6 #(
.INIT(64'h0080000000000000))
bram_en_i_3
(.I0(config_fsm_addr[3]),
.I1(config_fsm_addr[4]),
.I2(config_fsm_addr[2]),
.I3(config_fsm_addr[1]),
.I4(config_fsm_addr[6]),
.I5(config_fsm_addr[5]),
.O(bram_en_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair191" *)
LUT4 #(
.INIT(16'h8000))
bram_rd_en_i_1
(.I0(bram_rd_en_i_2_n_0),
.I1(bram_rd_en_i_3_n_0),
.I2(config_fsm_en_rb),
.I3(bram_rd_en_i_4_n_0),
.O(bram_rd_en));
LUT6 #(
.INIT(64'h8000000000000000))
bram_rd_en_i_2
(.I0(config_fsm_addr[8]),
.I1(config_fsm_addr[9]),
.I2(config_fsm_addr[6]),
.I3(config_fsm_addr[7]),
.I4(config_fsm_addr[11]),
.I5(config_fsm_addr[10]),
.O(bram_rd_en_i_2_n_0));
LUT6 #(
.INIT(64'h2000000000000000))
bram_rd_en_i_3
(.I0(config_fsm_addr[3]),
.I1(config_fsm_addr[2]),
.I2(config_fsm_addr[0]),
.I3(config_fsm_addr[1]),
.I4(config_fsm_addr[5]),
.I5(config_fsm_addr[4]),
.O(bram_rd_en_i_3_n_0));
LUT6 #(
.INIT(64'h0000000000000001))
bram_rd_en_i_4
(.I0(config_fsm_addr[14]),
.I1(config_fsm_addr[15]),
.I2(config_fsm_addr[12]),
.I3(config_fsm_addr[13]),
.I4(config_fsm_we),
.I5(config_fsm_addr[16]),
.O(bram_rd_en_i_4_n_0));
LUT1 #(
.INIT(2'h1))
\count0[0]_i_1
(.I0(count0_reg__0[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair198" *)
LUT2 #(
.INIT(4'h6))
\count0[1]_i_1
(.I0(count0_reg__0[0]),
.I1(count0_reg__0[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair194" *)
LUT3 #(
.INIT(8'h6A))
\count0[2]_i_1
(.I0(count0_reg__0[2]),
.I1(count0_reg__0[1]),
.I2(count0_reg__0[0]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair198" *)
LUT4 #(
.INIT(16'h6AAA))
\count0[3]_i_1
(.I0(count0_reg__0[3]),
.I1(count0_reg__0[0]),
.I2(count0_reg__0[1]),
.I3(count0_reg__0[2]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair189" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\count0[4]_i_1
(.I0(count0_reg__0[4]),
.I1(count0_reg__0[2]),
.I2(count0_reg__0[1]),
.I3(count0_reg__0[0]),
.I4(count0_reg__0[3]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\count0[5]_i_1
(.I0(count0_reg__0[5]),
.I1(count0_reg__0[3]),
.I2(count0_reg__0[0]),
.I3(count0_reg__0[1]),
.I4(count0_reg__0[2]),
.I5(count0_reg__0[4]),
.O(p_0_in__0[5]));
LUT2 #(
.INIT(4'hE))
\count0[6]_i_1
(.I0(count0_reg__0[6]),
.I1(s_rst_o),
.O(count00));
(* SOFT_HLUTNM = "soft_lutpair203" *)
LUT3 #(
.INIT(8'h6A))
\count0[6]_i_2
(.I0(count0_reg__0[6]),
.I1(\count0[6]_i_3_n_0 ),
.I2(count0_reg__0[5]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair189" *)
LUT5 #(
.INIT(32'h80000000))
\count0[6]_i_3
(.I0(count0_reg__0[4]),
.I1(count0_reg__0[2]),
.I2(count0_reg__0[1]),
.I3(count0_reg__0[0]),
.I4(count0_reg__0[3]),
.O(\count0[6]_i_3_n_0 ));
FDRE \count0_reg[0]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[0]),
.Q(count0_reg__0[0]),
.R(count00));
FDRE \count0_reg[1]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[1]),
.Q(count0_reg__0[1]),
.R(count00));
FDRE \count0_reg[2]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[2]),
.Q(count0_reg__0[2]),
.R(count00));
FDRE \count0_reg[3]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[3]),
.Q(count0_reg__0[3]),
.R(count00));
FDRE \count0_reg[4]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[4]),
.Q(count0_reg__0[4]),
.R(count00));
FDRE \count0_reg[5]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[5]),
.Q(count0_reg__0[5]),
.R(count00));
FDRE \count0_reg[6]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[6]),
.Q(count0_reg__0[6]),
.R(count00));
LUT1 #(
.INIT(2'h1))
\count1[0]_i_1
(.I0(count1_reg__0[0]),
.O(p_0_in__1[0]));
(* SOFT_HLUTNM = "soft_lutpair206" *)
LUT2 #(
.INIT(4'h6))
\count1[1]_i_1
(.I0(count1_reg__0[0]),
.I1(count1_reg__0[1]),
.O(p_0_in__1[1]));
(* SOFT_HLUTNM = "soft_lutpair206" *)
LUT3 #(
.INIT(8'h6A))
\count1[2]_i_1
(.I0(count1_reg__0[2]),
.I1(count1_reg__0[1]),
.I2(count1_reg__0[0]),
.O(p_0_in__1[2]));
(* SOFT_HLUTNM = "soft_lutpair193" *)
LUT4 #(
.INIT(16'h6AAA))
\count1[3]_i_1
(.I0(count1_reg__0[3]),
.I1(count1_reg__0[0]),
.I2(count1_reg__0[1]),
.I3(count1_reg__0[2]),
.O(p_0_in__1[3]));
(* SOFT_HLUTNM = "soft_lutpair188" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\count1[4]_i_1
(.I0(count1_reg__0[4]),
.I1(count1_reg__0[2]),
.I2(count1_reg__0[1]),
.I3(count1_reg__0[0]),
.I4(count1_reg__0[3]),
.O(p_0_in__1[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\count1[5]_i_1
(.I0(count1_reg__0[5]),
.I1(count1_reg__0[3]),
.I2(count1_reg__0[0]),
.I3(count1_reg__0[1]),
.I4(count1_reg__0[2]),
.I5(count1_reg__0[4]),
.O(p_0_in__1[5]));
LUT2 #(
.INIT(4'hE))
\count1[6]_i_1
(.I0(s_rst_o),
.I1(count1_reg__0[6]),
.O(count10));
(* SOFT_HLUTNM = "soft_lutpair205" *)
LUT3 #(
.INIT(8'h6A))
\count1[6]_i_2
(.I0(count1_reg__0[6]),
.I1(count1_reg__0[5]),
.I2(\count1[6]_i_3_n_0 ),
.O(p_0_in__1[6]));
(* SOFT_HLUTNM = "soft_lutpair188" *)
LUT5 #(
.INIT(32'h80000000))
\count1[6]_i_3
(.I0(count1_reg__0[4]),
.I1(count1_reg__0[2]),
.I2(count1_reg__0[1]),
.I3(count1_reg__0[0]),
.I4(count1_reg__0[3]),
.O(\count1[6]_i_3_n_0 ));
FDRE \count1_reg[0]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[0]),
.Q(count1_reg__0[0]),
.R(count10));
FDRE \count1_reg[1]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[1]),
.Q(count1_reg__0[1]),
.R(count10));
FDRE \count1_reg[2]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[2]),
.Q(count1_reg__0[2]),
.R(count10));
FDRE \count1_reg[3]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[3]),
.Q(count1_reg__0[3]),
.R(count10));
FDRE \count1_reg[4]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[4]),
.Q(count1_reg__0[4]),
.R(count10));
FDRE \count1_reg[5]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[5]),
.Q(count1_reg__0[5]),
.R(count10));
FDRE \count1_reg[6]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[6]),
.Q(count1_reg__0[6]),
.R(count10));
FDSE count_tt_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(count_tt_reg_0),
.Q(count_tt),
.S(s_rst_o));
LUT6 #(
.INIT(64'h0000000004000000))
\current_state[4]_i_2
(.I0(reg_stream_ffd_n_2),
.I1(reg_stream_ffd_n_1),
.I2(s_daddr_o[12]),
.I3(reg_stream_ffd_n_0),
.I4(s_daddr_o[2]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.O(read_data_en));
LUT6 #(
.INIT(64'h00000000BABA000B))
\drdyCount[0]_i_1
(.I0(s_den_o),
.I1(drdyCount[0]),
.I2(drdyCount[4]),
.I3(drdyCount[5]),
.I4(\drdyCount[5]_i_5_n_0 ),
.I5(s_rst_o),
.O(\drdyCount[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\drdyCount[1]_i_1
(.I0(drdyCount[0]),
.I1(drdyCount[1]),
.O(\drdyCount[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair201" *)
LUT3 #(
.INIT(8'h6A))
\drdyCount[2]_i_1
(.I0(drdyCount[2]),
.I1(drdyCount[1]),
.I2(drdyCount[0]),
.O(\drdyCount[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair195" *)
LUT4 #(
.INIT(16'h6AAA))
\drdyCount[3]_i_1
(.I0(drdyCount[3]),
.I1(drdyCount[0]),
.I2(drdyCount[1]),
.I3(drdyCount[2]),
.O(\drdyCount[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00000000FF6A006A))
\drdyCount[4]_i_1
(.I0(drdyCount[4]),
.I1(\drdyCount[5]_i_2_n_0 ),
.I2(\drdyCount[5]_i_6_n_0 ),
.I3(s_den_o),
.I4(\drdyCount[4]_i_2_n_0 ),
.I5(drdyCount1),
.O(\drdyCount[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1555555555555555))
\drdyCount[4]_i_2
(.I0(s_daddr_o[12]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[6]),
.I3(s_daddr_o[4]),
.I4(regDrdy_i_3_n_0),
.I5(\drdyCount[4]_i_3_n_0 ),
.O(\drdyCount[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\drdyCount[4]_i_3
(.I0(s_daddr_o[11]),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[10]),
.I3(s_daddr_o[8]),
.I4(s_daddr_o[9]),
.I5(s_daddr_o[7]),
.O(\drdyCount[4]_i_3_n_0 ));
LUT2 #(
.INIT(4'hE))
\drdyCount[5]_i_1
(.I0(s_den_o),
.I1(drdyCount1),
.O(\drdyCount[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFFFD))
\drdyCount[5]_i_2
(.I0(\drdyCount[5]_i_5_n_0 ),
.I1(s_den_o),
.I2(drdyCount[0]),
.I3(drdyCount[4]),
.O(\drdyCount[5]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1540))
\drdyCount[5]_i_3
(.I0(s_den_o),
.I1(drdyCount[4]),
.I2(\drdyCount[5]_i_6_n_0 ),
.I3(drdyCount[5]),
.O(\drdyCount[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFEFAFAFAFA))
\drdyCount[5]_i_4
(.I0(s_rst_o),
.I1(drdyCount[3]),
.I2(drdyCount[5]),
.I3(drdyCount[2]),
.I4(drdyCount[1]),
.I5(drdyCount[4]),
.O(drdyCount1));
(* SOFT_HLUTNM = "soft_lutpair201" *)
LUT4 #(
.INIT(16'h0001))
\drdyCount[5]_i_5
(.I0(drdyCount[3]),
.I1(drdyCount[5]),
.I2(drdyCount[2]),
.I3(drdyCount[1]),
.O(\drdyCount[5]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair195" *)
LUT4 #(
.INIT(16'h8000))
\drdyCount[5]_i_6
(.I0(drdyCount[3]),
.I1(drdyCount[0]),
.I2(drdyCount[1]),
.I3(drdyCount[2]),
.O(\drdyCount[5]_i_6_n_0 ));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\drdyCount[0]_i_1_n_0 ),
.Q(drdyCount[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[1]
(.C(s_dclk_o),
.CE(\drdyCount[5]_i_2_n_0 ),
.D(\drdyCount[1]_i_1_n_0 ),
.Q(drdyCount[1]),
.R(\drdyCount[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[2]
(.C(s_dclk_o),
.CE(\drdyCount[5]_i_2_n_0 ),
.D(\drdyCount[2]_i_1_n_0 ),
.Q(drdyCount[2]),
.R(\drdyCount[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[3]
(.C(s_dclk_o),
.CE(\drdyCount[5]_i_2_n_0 ),
.D(\drdyCount[3]_i_1_n_0 ),
.Q(drdyCount[3]),
.R(\drdyCount[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\drdyCount[4]_i_1_n_0 ),
.Q(drdyCount[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[5]
(.C(s_dclk_o),
.CE(\drdyCount[5]_i_2_n_0 ),
.D(\drdyCount[5]_i_3_n_0 ),
.Q(drdyCount[5]),
.R(\drdyCount[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
drdy_ff7_i_1
(.I0(drdy_ff9_i_3_n_0),
.I1(drdy_ff7_i_2_n_0),
.I2(s_daddr_o[10]),
.I3(s_daddr_o[11]),
.I4(reg_83_n_1),
.I5(drdy_ff7_i_3_n_0),
.O(xsdb_rden_ff7));
(* SOFT_HLUTNM = "soft_lutpair208" *)
LUT2 #(
.INIT(4'h2))
drdy_ff7_i_2
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[3]),
.O(drdy_ff7_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair190" *)
LUT3 #(
.INIT(8'h7F))
drdy_ff7_i_3
(.I0(s_daddr_o[8]),
.I1(s_daddr_o[9]),
.I2(s_daddr_o[7]),
.O(drdy_ff7_i_3_n_0));
FDRE drdy_ff7_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(xsdb_rden_ff7),
.Q(drdy_ff7),
.R(s_rst_o));
LUT6 #(
.INIT(64'h0000000000000080))
drdy_ff8_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[11]),
.I2(drdy_ff9_i_3_n_0),
.I3(drdy_ff9_i_2_n_0),
.I4(s_daddr_o[2]),
.I5(drdy_ff8_i_2_n_0),
.O(slaveRegDo_ff8));
(* SOFT_HLUTNM = "soft_lutpair202" *)
LUT2 #(
.INIT(4'hE))
drdy_ff8_i_2
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[0]),
.O(drdy_ff8_i_2_n_0));
FDRE drdy_ff8_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_ff8),
.Q(drdy_ff8),
.R(s_rst_o));
LUT6 #(
.INIT(64'h0000400000000000))
drdy_ff9_i_1
(.I0(drdy_ff9_i_2_n_0),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[11]),
.I3(drdy_ff9_i_3_n_0),
.I4(s_daddr_o[2]),
.I5(\CNT.CNT_SRL[1].cnt_srl_reg_n_0 ),
.O(xsdb_rden_ff9));
(* SOFT_HLUTNM = "soft_lutpair192" *)
LUT4 #(
.INIT(16'h7FFF))
drdy_ff9_i_2
(.I0(s_daddr_o[7]),
.I1(s_daddr_o[9]),
.I2(s_daddr_o[8]),
.I3(s_daddr_o[10]),
.O(drdy_ff9_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair187" *)
LUT5 #(
.INIT(32'h00008000))
drdy_ff9_i_3
(.I0(s_daddr_o[5]),
.I1(s_daddr_o[6]),
.I2(s_daddr_o[4]),
.I3(s_den_o),
.I4(s_dwe_o),
.O(drdy_ff9_i_3_n_0));
FDRE drdy_ff9_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(xsdb_rden_ff9),
.Q(drdy_ff9),
.R(s_rst_o));
LUT6 #(
.INIT(64'h0000000000000080))
drdy_ffa_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[11]),
.I2(drdy_ff9_i_3_n_0),
.I3(s_daddr_o[2]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.I5(drdy_ff9_i_2_n_0),
.O(xsdb_rden_ffa));
FDRE drdy_ffa_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(xsdb_rden_ffa),
.Q(drdy_ffa),
.R(s_rst_o));
FDRE drdy_mux_ff1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(drdy_mux_ff),
.Q(drdy_mux_ff1),
.R(1'b0));
LUT6 #(
.INIT(64'h0001000000000000))
drdy_mux_ff_i_1
(.I0(drdyCount[1]),
.I1(drdyCount[2]),
.I2(drdyCount[5]),
.I3(drdyCount[3]),
.I4(drdyCount[4]),
.I5(drdyCount[0]),
.O(drdy_mux_temp));
FDRE drdy_mux_ff_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(drdy_mux_temp),
.Q(drdy_mux_ff),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE dummy_temp1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(DUMMY_I),
.Q(dummy_temp1),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE dummy_temp_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(dummy_temp1),
.Q(dummy_temp),
.R(1'b0));
FDRE \regAck_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(regAck_temp),
.Q(regAck_reg),
.R(1'b0));
FDRE \regAck_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(regAck_temp_reg),
.Q(\regAck_reg_n_0_[1] ),
.R(1'b0));
FDRE \regAck_temp_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_den_o),
.Q(regAck_temp),
.R(1'b0));
FDRE \regAck_temp_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(E),
.Q(regAck_temp_reg),
.R(1'b0));
LUT6 #(
.INIT(64'hFF55AA00EF40EF40))
regDrdy_i_1
(.I0(regDrdy_reg_0),
.I1(drdy_ff7),
.I2(regDrdy_i_3_n_0),
.I3(drdy_mux_ff1),
.I4(regDrdy_reg_i_4_n_0),
.I5(s_daddr_o[3]),
.O(regDrdy_i_1_n_0));
LUT4 #(
.INIT(16'hFFBF))
regDrdy_i_2
(.I0(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ),
.I1(s_daddr_o[10]),
.I2(s_daddr_o[11]),
.I3(s_daddr_o[12]),
.O(regDrdy_reg_0));
(* SOFT_HLUTNM = "soft_lutpair197" *)
LUT3 #(
.INIT(8'h80))
regDrdy_i_3
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[2]),
.O(regDrdy_i_3_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
regDrdy_i_5
(.I0(adv_rb_drdy4),
.I1(drdy_ffa),
.I2(s_daddr_o[1]),
.I3(drdy_ff9),
.I4(s_daddr_o[0]),
.I5(drdy_ff8),
.O(regDrdy_i_5_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
regDrdy_i_6
(.I0(drdy_mux_ff1),
.I1(\regAck_reg_n_0_[1] ),
.I2(s_daddr_o[1]),
.I3(regAck_reg),
.I4(s_daddr_o[0]),
.I5(adv_drdy),
.O(regDrdy_i_6_n_0));
FDRE regDrdy_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(regDrdy_i_1_n_0),
.Q(regDrdy_reg_n_0),
.R(1'b0));
MUXF7 regDrdy_reg_i_4
(.I0(regDrdy_i_5_n_0),
.I1(regDrdy_i_6_n_0),
.O(regDrdy_reg_i_4_n_0),
.S(s_daddr_o[2]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized43 reg_15
(.D(p_0_in[2:1]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] ({\slaveRegDo_mux_1[2]_i_1_n_0 ,\slaveRegDo_mux_1[1]_i_1_n_0 }),
.\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (reg_19_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (drdy_ff7_i_2_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (reg_9_n_2),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (reg_9_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\slaveRegDo_mux_2[15]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (reg_7_n_4),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (reg_7_n_6),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 (reg_7_n_7),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 (reg_7_n_8),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 (reg_7_n_9),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 (reg_7_n_10),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 (reg_7_n_13),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 (reg_7_n_14),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (reg_83_n_15),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 (reg_83_n_16),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\slaveRegDo_mux_0[4]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\slaveRegDo_mux_0[4]_i_8_n_0 ),
.Q({reg_9_n_3,reg_9_n_4,reg_9_n_7,reg_9_n_8,reg_9_n_9,reg_9_n_10,reg_9_n_11}),
.SR(SR),
.read_reset_addr({read_reset_addr[14:5],read_reset_addr[2:1]}),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[10] (reg_15_n_12),
.\slaveRegDo_mux_0_reg[11] (reg_15_n_1),
.\slaveRegDo_mux_0_reg[12] (reg_15_n_0),
.\slaveRegDo_mux_0_reg[13] (reg_15_n_13),
.\slaveRegDo_mux_0_reg[14] (reg_15_n_14),
.\slaveRegDo_mux_0_reg[15] (reg_15_n_15),
.\slaveRegDo_mux_0_reg[3] (reg_15_n_17),
.\slaveRegDo_mux_0_reg[4] (reg_15_n_16),
.\slaveRegDo_mux_0_reg[5] (reg_15_n_2),
.\slaveRegDo_mux_0_reg[6] (reg_15_n_8),
.\slaveRegDo_mux_0_reg[7] (reg_15_n_9),
.\slaveRegDo_mux_0_reg[8] (reg_15_n_10),
.\slaveRegDo_mux_0_reg[9] (reg_15_n_11),
.use_probe_debug_circuit_1(use_probe_debug_circuit_1),
.\xsdb_reg_reg[0] (reg_15_n_5),
.\xsdb_reg_reg[0]_0 (reg_15_n_6),
.\xsdb_reg_reg[10] (reg_18_n_6),
.\xsdb_reg_reg[10]_0 (reg_17_n_8),
.\xsdb_reg_reg[11] (reg_17_n_7),
.\xsdb_reg_reg[12] (reg_17_n_6),
.\xsdb_reg_reg[13] (reg_18_n_5),
.\xsdb_reg_reg[13]_0 (reg_17_n_5),
.\xsdb_reg_reg[14] (reg_18_n_0),
.\xsdb_reg_reg[14]_0 (reg_17_n_4),
.\xsdb_reg_reg[1] (reg_18_n_12),
.\xsdb_reg_reg[1]_0 (reg_6_n_14),
.\xsdb_reg_reg[1]_1 (reg_17_n_15),
.\xsdb_reg_reg[2] (reg_18_n_11),
.\xsdb_reg_reg[2]_0 (reg_17_n_14),
.\xsdb_reg_reg[5] (reg_17_n_13),
.\xsdb_reg_reg[6] (reg_18_n_10),
.\xsdb_reg_reg[6]_0 (reg_17_n_12),
.\xsdb_reg_reg[7] (reg_18_n_9),
.\xsdb_reg_reg[7]_0 (reg_17_n_11),
.\xsdb_reg_reg[8] (reg_18_n_8),
.\xsdb_reg_reg[8]_0 (reg_17_n_10),
.\xsdb_reg_reg[9] (reg_18_n_7),
.\xsdb_reg_reg[9]_0 (reg_17_n_9));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized44 reg_16
(.\G_1PIPE_IFACE.s_daddr_r_reg[9] (reg_15_n_5),
.read_reset_addr(read_reset_addr),
.s_daddr_o(s_daddr_o[6:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[15] (reg_16_n_1),
.\xsdb_reg_reg[15] (reg_16_n_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized45 reg_17
(.D(p_0_in[0]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_8_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_1[0]_i_1_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (reg_7_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (reg_83_n_17),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\slaveRegDo_mux_0[4]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\slaveRegDo_mux_0[4]_i_8_n_0 ),
.SR(SR),
.read_reset_addr({read_reset_addr[4:3],read_reset_addr[0]}),
.s_daddr_o(s_daddr_o[6:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[10] (reg_17_n_8),
.\slaveRegDo_mux_0_reg[11] (reg_17_n_7),
.\slaveRegDo_mux_0_reg[12] (reg_17_n_6),
.\slaveRegDo_mux_0_reg[13] (reg_17_n_5),
.\slaveRegDo_mux_0_reg[14] (reg_17_n_4),
.\slaveRegDo_mux_0_reg[15] (reg_17_n_1),
.\slaveRegDo_mux_0_reg[1] (reg_17_n_15),
.\slaveRegDo_mux_0_reg[2] (reg_17_n_14),
.\slaveRegDo_mux_0_reg[3] (reg_17_n_3),
.\slaveRegDo_mux_0_reg[4] (reg_17_n_2),
.\slaveRegDo_mux_0_reg[5] (reg_17_n_13),
.\slaveRegDo_mux_0_reg[6] (reg_17_n_12),
.\slaveRegDo_mux_0_reg[7] (reg_17_n_11),
.\slaveRegDo_mux_0_reg[8] (reg_17_n_10),
.\slaveRegDo_mux_0_reg[9] (reg_17_n_9),
.\xsdb_reg_reg[0] (reg_1a_n_4),
.\xsdb_reg_reg[15] (reg_16_n_1),
.\xsdb_reg_reg[15]_0 (reg_15_n_15),
.\xsdb_reg_reg[3] (reg_15_n_17),
.\xsdb_reg_reg[4] (reg_15_n_16));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized46 reg_18
(.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_19_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (reg_6_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\slaveRegDo_mux_0[3]_i_9_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (reg_7_n_12),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (reg_7_n_11),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_8_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.Q({reg_9_n_5,reg_9_n_6,reg_9_n_12}),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.s_daddr_o({s_daddr_o[6:3],s_daddr_o[1:0]}),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.\slaveRegDo_mux_0_reg[10] (reg_18_n_6),
.\slaveRegDo_mux_0_reg[11] (reg_18_n_14),
.\slaveRegDo_mux_0_reg[12] (reg_18_n_13),
.\slaveRegDo_mux_0_reg[13] (reg_18_n_5),
.\slaveRegDo_mux_0_reg[14] (reg_18_n_0),
.\slaveRegDo_mux_0_reg[15] ({slaveRegDo_18[15],slaveRegDo_18[4:3],slaveRegDo_18[0]}),
.\slaveRegDo_mux_0_reg[1] (reg_18_n_12),
.\slaveRegDo_mux_0_reg[2] (reg_18_n_11),
.\slaveRegDo_mux_0_reg[5] (reg_18_n_15),
.\slaveRegDo_mux_0_reg[6] (reg_18_n_10),
.\slaveRegDo_mux_0_reg[7] (reg_18_n_9),
.\slaveRegDo_mux_0_reg[8] (reg_18_n_8),
.\slaveRegDo_mux_0_reg[9] (reg_18_n_7),
.\xsdb_reg_reg[10] (reg_19_n_7),
.\xsdb_reg_reg[10]_0 (reg_1a_n_9),
.\xsdb_reg_reg[11] (reg_15_n_1),
.\xsdb_reg_reg[11]_0 (reg_19_n_6),
.\xsdb_reg_reg[11]_1 (reg_1a_n_8),
.\xsdb_reg_reg[12] (reg_15_n_0),
.\xsdb_reg_reg[12]_0 (reg_19_n_5),
.\xsdb_reg_reg[12]_1 (reg_1a_n_7),
.\xsdb_reg_reg[13] (reg_19_n_4),
.\xsdb_reg_reg[13]_0 (reg_1a_n_6),
.\xsdb_reg_reg[14] (reg_19_n_3),
.\xsdb_reg_reg[14]_0 (reg_1a_n_5),
.\xsdb_reg_reg[1] (reg_19_n_16),
.\xsdb_reg_reg[2] (reg_19_n_15),
.\xsdb_reg_reg[5] (reg_15_n_2),
.\xsdb_reg_reg[5]_0 (reg_19_n_12),
.\xsdb_reg_reg[5]_1 (reg_1a_n_14),
.\xsdb_reg_reg[6] (reg_19_n_11),
.\xsdb_reg_reg[6]_0 (reg_1a_n_13),
.\xsdb_reg_reg[7] (reg_19_n_10),
.\xsdb_reg_reg[7]_0 (reg_1a_n_12),
.\xsdb_reg_reg[8] (reg_19_n_9),
.\xsdb_reg_reg[8]_0 (reg_1a_n_11),
.\xsdb_reg_reg[9] (reg_19_n_8),
.\xsdb_reg_reg[9]_0 (reg_1a_n_10));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized47 reg_19
(.\G_1PIPE_IFACE.s_daddr_r_reg[9] (reg_15_n_5),
.s_daddr_o(s_daddr_o[6:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[0] (reg_19_n_17),
.\slaveRegDo_mux_0_reg[10] (reg_19_n_7),
.\slaveRegDo_mux_0_reg[11] (reg_19_n_6),
.\slaveRegDo_mux_0_reg[12] (reg_19_n_5),
.\slaveRegDo_mux_0_reg[13] (reg_19_n_4),
.\slaveRegDo_mux_0_reg[14] (reg_19_n_3),
.\slaveRegDo_mux_0_reg[15] (reg_19_n_2),
.\slaveRegDo_mux_0_reg[1] (reg_19_n_16),
.\slaveRegDo_mux_0_reg[2] (reg_19_n_15),
.\slaveRegDo_mux_0_reg[3] (reg_19_n_14),
.\slaveRegDo_mux_0_reg[4] (reg_19_n_13),
.\slaveRegDo_mux_0_reg[5] (reg_19_n_12),
.\slaveRegDo_mux_0_reg[6] (reg_19_n_11),
.\slaveRegDo_mux_0_reg[7] (reg_19_n_10),
.\slaveRegDo_mux_0_reg[8] (reg_19_n_9),
.\slaveRegDo_mux_0_reg[9] (reg_19_n_8),
.\xsdb_reg_reg[0] (reg_19_n_0),
.\xsdb_reg_reg[0]_0 (reg_19_n_1));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized48 reg_1a
(.D(p_0_in[4:3]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] ({\slaveRegDo_mux_1[4]_i_1_n_0 ,\slaveRegDo_mux_1[3]_i_1_n_0 }),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_8_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (reg_9_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (reg_7_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (reg_16_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 (reg_83_n_14),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 (reg_83_n_13),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\slaveRegDo_mux_0[4]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\slaveRegDo_mux_0[4]_i_8_n_0 ),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.en_adv_trigger_1(en_adv_trigger_1),
.s_daddr_o(s_daddr_o[7:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.\slaveRegDo_mux_0_reg[0] (reg_1a_n_4),
.\slaveRegDo_mux_0_reg[10] (reg_1a_n_9),
.\slaveRegDo_mux_0_reg[11] (reg_1a_n_8),
.\slaveRegDo_mux_0_reg[12] (reg_1a_n_7),
.\slaveRegDo_mux_0_reg[13] (reg_1a_n_6),
.\slaveRegDo_mux_0_reg[14] (reg_1a_n_5),
.\slaveRegDo_mux_0_reg[15] (reg_1a_n_2),
.\slaveRegDo_mux_0_reg[5] (reg_1a_n_14),
.\slaveRegDo_mux_0_reg[6] (reg_1a_n_13),
.\slaveRegDo_mux_0_reg[7] (reg_1a_n_12),
.\slaveRegDo_mux_0_reg[8] (reg_1a_n_11),
.\slaveRegDo_mux_0_reg[9] (reg_1a_n_10),
.\xsdb_reg_reg[0] (reg_19_n_17),
.\xsdb_reg_reg[15] (reg_83_n_2),
.\xsdb_reg_reg[15]_0 (reg_17_n_1),
.\xsdb_reg_reg[15]_1 (reg_19_n_2),
.\xsdb_reg_reg[15]_2 ({slaveRegDo_18[15],slaveRegDo_18[4:3],slaveRegDo_18[0]}),
.\xsdb_reg_reg[3] (reg_17_n_3),
.\xsdb_reg_reg[3]_0 (reg_19_n_14),
.\xsdb_reg_reg[4] (reg_17_n_2),
.\xsdb_reg_reg[4]_0 (reg_19_n_13));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized28 reg_6
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.halt_ctrl(halt_ctrl),
.s_daddr_o({s_daddr_o[8:7],s_daddr_o[3:0]}),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.\slaveRegDo_mux_0_reg[15] ({slaveRegDo_6[15:6],slaveRegDo_6[3:2],slaveRegDo_6[0]}),
.\slaveRegDo_mux_0_reg[1] (reg_6_n_14),
.\slaveRegDo_mux_0_reg[4] (reg_6_n_15),
.\slaveRegDo_mux_0_reg[5] (reg_6_n_0),
.\xsdb_reg_reg[4] (reg_7_n_16),
.\xsdb_reg_reg[5] (reg_7_n_15));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized29 reg_7
(.DOUT_O(DOUT_O),
.\G_1PIPE_IFACE.s_daddr_r_reg[9] (reg_15_n_5),
.halt_ctrl(halt_ctrl),
.s_daddr_o(s_daddr_o[6:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.scnt_cmp_temp(scnt_cmp_temp),
.shift_en_reg(shift_en_reg),
.shift_en_reg_0(shift_en_reg_0),
.\slaveRegDo_mux_0_reg[0] (reg_7_n_2),
.\slaveRegDo_mux_0_reg[10] (reg_7_n_10),
.\slaveRegDo_mux_0_reg[11] (reg_7_n_11),
.\slaveRegDo_mux_0_reg[12] (reg_7_n_12),
.\slaveRegDo_mux_0_reg[13] (reg_7_n_13),
.\slaveRegDo_mux_0_reg[14] (reg_7_n_14),
.\slaveRegDo_mux_0_reg[15] (reg_7_n_0),
.\slaveRegDo_mux_0_reg[2] (reg_7_n_4),
.\slaveRegDo_mux_0_reg[3] (reg_7_n_5),
.\slaveRegDo_mux_0_reg[4] (reg_7_n_16),
.\slaveRegDo_mux_0_reg[5] (reg_7_n_15),
.\slaveRegDo_mux_0_reg[6] (reg_7_n_6),
.\slaveRegDo_mux_0_reg[7] (reg_7_n_7),
.\slaveRegDo_mux_0_reg[8] (reg_7_n_8),
.\slaveRegDo_mux_0_reg[9] (reg_7_n_9),
.u_scnt_cmp_q(arm_ctrl),
.wcnt_hcmp_temp(wcnt_hcmp_temp),
.wcnt_lcmp_temp(wcnt_lcmp_temp),
.\xsdb_reg_reg[0] (reg_7_n_1),
.\xsdb_reg_reg[15] ({slaveRegDo_6[15:6],slaveRegDo_6[3:2],slaveRegDo_6[0]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized30 reg_8
(.CAP_DONE_O_reg(CAP_DONE_O_reg),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\slaveRegDo_mux_0[3]_i_9_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (reg_7_n_2),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (reg_7_n_5),
.Q({reg_9_n_13,reg_9_n_14}),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_0_reg[0] (reg_8_n_0),
.\slaveRegDo_mux_0_reg[2] ({reg_8_n_2,reg_8_n_3}),
.\slaveRegDo_mux_0_reg[3] (reg_8_n_1));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized49 reg_80
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o[2:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.slaveRegDo_80(slaveRegDo_80));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized50 reg_81
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o[2:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.slaveRegDo_81(slaveRegDo_81));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized51 reg_82
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o[2:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.slaveRegDo_82(slaveRegDo_82));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized52 reg_83
(.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\slaveRegDo_mux_0[15]_i_9_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_8_n_0 ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.slaveRegDo_80(slaveRegDo_80),
.slaveRegDo_81(slaveRegDo_81),
.slaveRegDo_82(slaveRegDo_82),
.slaveRegDo_84(slaveRegDo_84),
.\slaveRegDo_mux_0_reg[0] (reg_83_n_17),
.\slaveRegDo_mux_0_reg[10] (reg_83_n_7),
.\slaveRegDo_mux_0_reg[11] (reg_83_n_6),
.\slaveRegDo_mux_0_reg[12] (reg_83_n_5),
.\slaveRegDo_mux_0_reg[13] (reg_83_n_4),
.\slaveRegDo_mux_0_reg[14] (reg_83_n_3),
.\slaveRegDo_mux_0_reg[15] (reg_83_n_2),
.\slaveRegDo_mux_0_reg[1] (reg_83_n_16),
.\slaveRegDo_mux_0_reg[2] (reg_83_n_15),
.\slaveRegDo_mux_0_reg[3] (reg_83_n_14),
.\slaveRegDo_mux_0_reg[4] (reg_83_n_13),
.\slaveRegDo_mux_0_reg[5] (reg_83_n_12),
.\slaveRegDo_mux_0_reg[6] (reg_83_n_11),
.\slaveRegDo_mux_0_reg[7] (reg_83_n_10),
.\slaveRegDo_mux_0_reg[8] (reg_83_n_9),
.\slaveRegDo_mux_0_reg[9] (reg_83_n_8),
.\xsdb_reg_reg[0] (reg_83_n_0),
.\xsdb_reg_reg[0]_0 (reg_83_n_1),
.\xsdb_reg_reg[0]_1 (reg_84_n_15),
.\xsdb_reg_reg[10] (reg_15_n_12),
.\xsdb_reg_reg[10]_0 (reg_85_n_5),
.\xsdb_reg_reg[11] (reg_18_n_14),
.\xsdb_reg_reg[11]_0 (reg_85_n_4),
.\xsdb_reg_reg[12] (reg_18_n_13),
.\xsdb_reg_reg[12]_0 (reg_85_n_3),
.\xsdb_reg_reg[13] (reg_15_n_13),
.\xsdb_reg_reg[13]_0 (reg_85_n_2),
.\xsdb_reg_reg[14] (reg_15_n_14),
.\xsdb_reg_reg[14]_0 (reg_85_n_1),
.\xsdb_reg_reg[15] (reg_85_n_0),
.\xsdb_reg_reg[1] (reg_84_n_14),
.\xsdb_reg_reg[2] (reg_84_n_13),
.\xsdb_reg_reg[3] (reg_84_n_12),
.\xsdb_reg_reg[4] (reg_84_n_0),
.\xsdb_reg_reg[5] (reg_18_n_15),
.\xsdb_reg_reg[5]_0 (reg_85_n_10),
.\xsdb_reg_reg[6] (reg_15_n_8),
.\xsdb_reg_reg[6]_0 (reg_85_n_9),
.\xsdb_reg_reg[7] (reg_15_n_9),
.\xsdb_reg_reg[7]_0 (reg_85_n_8),
.\xsdb_reg_reg[8] (reg_15_n_10),
.\xsdb_reg_reg[8]_0 (reg_85_n_7),
.\xsdb_reg_reg[9] (reg_15_n_11),
.\xsdb_reg_reg[9]_0 (reg_85_n_6));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized53 reg_84
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o[2:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.\slaveRegDo_mux_0_reg[0] (reg_84_n_15),
.\slaveRegDo_mux_0_reg[15] (slaveRegDo_84),
.\slaveRegDo_mux_0_reg[1] (reg_84_n_14),
.\slaveRegDo_mux_0_reg[2] (reg_84_n_13),
.\slaveRegDo_mux_0_reg[3] (reg_84_n_12),
.\slaveRegDo_mux_0_reg[4] (reg_84_n_0),
.\xsdb_reg_reg[0] (reg_85_n_15),
.\xsdb_reg_reg[1] (reg_85_n_14),
.\xsdb_reg_reg[2] (reg_85_n_13),
.\xsdb_reg_reg[3] (reg_85_n_12),
.\xsdb_reg_reg[4] (reg_85_n_11));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized54 reg_85
(.\G_1PIPE_IFACE.s_daddr_r_reg[10] (reg_83_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_15_n_6),
.s_daddr_o(s_daddr_o[6:4]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.\slaveRegDo_mux_0_reg[0] (reg_85_n_15),
.\slaveRegDo_mux_0_reg[10] (reg_85_n_5),
.\slaveRegDo_mux_0_reg[11] (reg_85_n_4),
.\slaveRegDo_mux_0_reg[12] (reg_85_n_3),
.\slaveRegDo_mux_0_reg[13] (reg_85_n_2),
.\slaveRegDo_mux_0_reg[14] (reg_85_n_1),
.\slaveRegDo_mux_0_reg[15] (reg_85_n_0),
.\slaveRegDo_mux_0_reg[1] (reg_85_n_14),
.\slaveRegDo_mux_0_reg[2] (reg_85_n_13),
.\slaveRegDo_mux_0_reg[3] (reg_85_n_12),
.\slaveRegDo_mux_0_reg[4] (reg_85_n_11),
.\slaveRegDo_mux_0_reg[5] (reg_85_n_10),
.\slaveRegDo_mux_0_reg[6] (reg_85_n_9),
.\slaveRegDo_mux_0_reg[7] (reg_85_n_8),
.\slaveRegDo_mux_0_reg[8] (reg_85_n_7),
.\slaveRegDo_mux_0_reg[9] (reg_85_n_6));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized56 reg_887
(.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\slaveRegDo_mux_0[4]_i_12_n_0 ),
.out(dummy_temp),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_do_o(slaveRegDo_890[3]),
.\slaveRegDo_mux_2_reg[3] (reg_887_n_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized58 reg_88d
(.D(reg_88d_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_1[0]_i_1_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\slaveRegDo_mux_2[0]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\slaveRegDo_mux_2[0]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\slaveRegDo_mux_2[0]_i_2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\slaveRegDo_mux_2[4]_i_4_n_0 ),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.Q(reg_88d_n_1),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\xsdb_reg_reg[0] (reg_892_n_3),
.\xsdb_reg_reg[0]_0 (reg_88f_n_16));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized60 reg_88f
(.D({reg_88f_n_12,reg_88f_n_13,reg_88f_n_14,reg_88f_n_15}),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\slaveRegDo_mux_2[15]_i_4_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ({\slaveRegDo_mux_1[4]_i_1_n_0 ,\slaveRegDo_mux_1[3]_i_1_n_0 ,\slaveRegDo_mux_1[2]_i_1_n_0 ,\slaveRegDo_mux_1[1]_i_1_n_0 }),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (drdy_ff8_i_2_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_2[2]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\slaveRegDo_mux_2[4]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\slaveRegDo_mux_2[15]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\slaveRegDo_mux_2[4]_i_4_n_0 ),
.Q(reg_88d_n_1),
.SEQUENCER_STATE_O(SEQUENCER_STATE_O),
.en_adv_trigger(en_adv_trigger),
.s_daddr_o(s_daddr_o[4:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_do_o({slaveRegDo_890[15:4],slaveRegDo_890[1]}),
.\slaveRegDo_mux_2_reg[0] (reg_88f_n_16),
.\slaveRegDo_mux_2_reg[10] (reg_88f_n_5),
.\slaveRegDo_mux_2_reg[11] (reg_88f_n_6),
.\slaveRegDo_mux_2_reg[12] (reg_88f_n_7),
.\slaveRegDo_mux_2_reg[13] (reg_88f_n_8),
.\slaveRegDo_mux_2_reg[14] (reg_88f_n_9),
.\slaveRegDo_mux_2_reg[15] (reg_88f_n_10),
.\slaveRegDo_mux_2_reg[5] (reg_88f_n_0),
.\slaveRegDo_mux_2_reg[6] (reg_88f_n_1),
.\slaveRegDo_mux_2_reg[7] (reg_88f_n_2),
.\slaveRegDo_mux_2_reg[8] (reg_88f_n_3),
.\slaveRegDo_mux_2_reg[9] (reg_88f_n_4),
.\xsdb_reg_reg[15] (reg_88f_n_11),
.\xsdb_reg_reg[1] (reg_892_n_2),
.\xsdb_reg_reg[2] (reg_892_n_1),
.\xsdb_reg_reg[3] (reg_892_n_0),
.\xsdb_reg_reg[3]_0 (reg_887_n_0));
(* C_ADDR_W = "13" *)
(* C_CTLRST_VAL = "47'b00000000000000000000000000000000000000000000000" *)
(* C_DATA_W = "16" *)
(* C_EN_CTL = "0" *)
(* C_EN_STAT = "1" *)
(* C_REG_ADDR = "13'b0100010010000" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized61 reg_890
(.din_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.dout_o(NLW_reg_890_dout_o_UNCONNECTED[15:0]),
.rst_reg_i(1'b0),
.s_daddr_i(s_daddr_o),
.s_dclk_i(s_dclk_o),
.s_den_i(s_den_o),
.s_di_i(s_di),
.s_do_o(slaveRegDo_890),
.s_dwe_i(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized59 reg_892
(.\G_1PIPE_IFACE.s_den_r_reg (reg_88f_n_11),
.flag0_temp(flag0_temp),
.flag1_temp(flag1_temp),
.flag2_temp(flag2_temp),
.flag3_temp(flag3_temp),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_2_reg[0] (reg_892_n_3),
.\slaveRegDo_mux_2_reg[1] (reg_892_n_2),
.\slaveRegDo_mux_2_reg[2] (reg_892_n_1),
.\slaveRegDo_mux_2_reg[3] (reg_892_n_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized31 reg_9
(.Q({reg_9_n_3,reg_9_n_4,reg_9_n_5,reg_9_n_6,reg_9_n_7,reg_9_n_8,reg_9_n_9,reg_9_n_10,reg_9_n_11,reg_9_n_12,reg_9_n_13,reg_9_n_14}),
.\captured_samples_reg[14] (\captured_samples_reg[14] ),
.s_daddr_o(s_daddr_o[3:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_0_reg[1] (reg_9_n_2),
.\slaveRegDo_mux_0_reg[2] (reg_9_n_0),
.\slaveRegDo_mux_0_reg[4] (reg_9_n_1),
.\xsdb_reg_reg[2] ({reg_8_n_2,reg_8_n_3}),
.\xsdb_reg_reg[4] (reg_6_n_15));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized46 reg_srl_fff
(.D(D),
.E(\parallel_dout_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.Q({\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_11 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_12 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_13 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_14 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_15 }),
.capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
.debug_data_in(debug_data_in),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_dwe_o(s_dwe_o),
.shift_en_reg_0(shift_en_reg_2),
.\slaveRegDo_ff8_reg[12] (\slaveRegDo_mux_3[11]_i_3_n_0 ),
.\slaveRegDo_ff8_reg[7] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_6 ),
.\slaveRegDo_ff8_reg[7]_0 (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_8 ),
.\slaveRegDo_ff8_reg[7]_1 (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_7 ),
.\slaveRegDo_ff9_reg[8] (\slaveRegDo_mux_3[7]_i_3_n_0 ),
.\slaveRegDo_ffa_reg[15] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_5 ),
.\slaveRegDo_mux_3_reg[0] (reg_srl_fff_n_0),
.\slaveRegDo_mux_3_reg[10] (reg_srl_fff_n_14),
.\slaveRegDo_mux_3_reg[11] (reg_srl_fff_n_1),
.\slaveRegDo_mux_3_reg[12] (reg_srl_fff_n_13),
.\slaveRegDo_mux_3_reg[13] (reg_srl_fff_n_12),
.\slaveRegDo_mux_3_reg[14] (reg_srl_fff_n_11),
.\slaveRegDo_mux_3_reg[15] (reg_srl_fff_n_10),
.\slaveRegDo_mux_3_reg[1] (reg_srl_fff_n_9),
.\slaveRegDo_mux_3_reg[2] (reg_srl_fff_n_8),
.\slaveRegDo_mux_3_reg[3] (reg_srl_fff_n_7),
.\slaveRegDo_mux_3_reg[4] (reg_srl_fff_n_6),
.\slaveRegDo_mux_3_reg[5] (reg_srl_fff_n_5),
.\slaveRegDo_mux_3_reg[6] (reg_srl_fff_n_15),
.\slaveRegDo_mux_3_reg[7] (reg_srl_fff_n_4),
.\slaveRegDo_mux_3_reg[8] (reg_srl_fff_n_3),
.\slaveRegDo_mux_3_reg[9] (reg_srl_fff_n_2),
.\xsdb_reg_reg[10] (reg_stream_ffd_n_8),
.\xsdb_reg_reg[11] (reg_stream_ffd_n_7),
.\xsdb_reg_reg[12] (reg_stream_ffd_n_6),
.\xsdb_reg_reg[13] (reg_stream_ffd_n_5),
.\xsdb_reg_reg[14] (reg_stream_ffd_n_4),
.\xsdb_reg_reg[15] ({reg_stream_ffe_n_0,reg_stream_ffe_n_1,reg_stream_ffe_n_2,reg_stream_ffe_n_3,reg_stream_ffe_n_4,reg_stream_ffe_n_5,reg_stream_ffe_n_6,reg_stream_ffe_n_7,reg_stream_ffe_n_8,reg_stream_ffe_n_9,reg_stream_ffe_n_10,reg_stream_ffe_n_11,reg_stream_ffe_n_12,reg_stream_ffe_n_13,reg_stream_ffe_n_14,reg_stream_ffe_n_15}),
.\xsdb_reg_reg[15]_0 (reg_stream_ffd_n_3),
.\xsdb_reg_reg[2] (reg_stream_ffd_n_16),
.\xsdb_reg_reg[3] (reg_stream_ffd_n_15),
.\xsdb_reg_reg[4] (reg_stream_ffd_n_14),
.\xsdb_reg_reg[5] (reg_stream_ffd_n_13),
.\xsdb_reg_reg[6] (reg_stream_ffd_n_12),
.\xsdb_reg_reg[7] (reg_stream_ffd_n_11),
.\xsdb_reg_reg[8] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_9 ),
.\xsdb_reg_reg[8]_0 (reg_stream_ffd_n_10),
.\xsdb_reg_reg[9] (reg_stream_ffd_n_9));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized1 reg_stream_ffd
(.debug_data_in(debug_data_in),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_3_reg[10] (reg_stream_ffd_n_8),
.\slaveRegDo_mux_3_reg[11] (reg_stream_ffd_n_7),
.\slaveRegDo_mux_3_reg[12] (reg_stream_ffd_n_6),
.\slaveRegDo_mux_3_reg[13] (reg_stream_ffd_n_5),
.\slaveRegDo_mux_3_reg[14] (reg_stream_ffd_n_4),
.\slaveRegDo_mux_3_reg[15] (reg_stream_ffd_n_3),
.\slaveRegDo_mux_3_reg[2] (reg_stream_ffd_n_16),
.\slaveRegDo_mux_3_reg[3] (reg_stream_ffd_n_15),
.\slaveRegDo_mux_3_reg[4] (reg_stream_ffd_n_14),
.\slaveRegDo_mux_3_reg[5] (reg_stream_ffd_n_13),
.\slaveRegDo_mux_3_reg[6] (reg_stream_ffd_n_12),
.\slaveRegDo_mux_3_reg[7] (reg_stream_ffd_n_11),
.\slaveRegDo_mux_3_reg[8] (reg_stream_ffd_n_10),
.\slaveRegDo_mux_3_reg[9] (reg_stream_ffd_n_9),
.\xsdb_reg_reg[0] (reg_stream_ffd_n_0),
.\xsdb_reg_reg[0]_0 (reg_stream_ffd_n_1),
.\xsdb_reg_reg[0]_1 (reg_stream_ffd_n_2));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized2 reg_stream_ffe
(.E(E),
.Q({reg_stream_ffe_n_0,reg_stream_ffe_n_1,reg_stream_ffe_n_2,reg_stream_ffe_n_3,reg_stream_ffe_n_4,reg_stream_ffe_n_5,reg_stream_ffe_n_6,reg_stream_ffe_n_7,reg_stream_ffe_n_8,reg_stream_ffe_n_9,reg_stream_ffe_n_10,reg_stream_ffe_n_11,reg_stream_ffe_n_12,reg_stream_ffe_n_13,reg_stream_ffe_n_14,reg_stream_ffe_n_15}),
.\input_data_reg[31] (\input_data_reg[31] ),
.s_dclk_o(s_dclk_o));
(* SOFT_HLUTNM = "soft_lutpair203" *)
LUT3 #(
.INIT(8'h01))
\shift_reg0[8]_i_2
(.I0(count0_reg__0[4]),
.I1(count0_reg__0[3]),
.I2(count0_reg__0[6]),
.O(\shift_reg0_reg[8]_1 ));
(* SOFT_HLUTNM = "soft_lutpair194" *)
LUT4 #(
.INIT(16'hFFFE))
\shift_reg0[8]_i_3
(.I0(count0_reg__0[1]),
.I1(count0_reg__0[0]),
.I2(count0_reg__0[5]),
.I3(count0_reg__0[2]),
.O(\shift_reg0_reg[8]_0 ));
FDRE \shift_reg0_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shift_reg0_reg[8]_2 ),
.Q(\slaveRegDo_ff9_reg[8]_0 ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair205" *)
LUT3 #(
.INIT(8'h01))
\shift_reg1[15]_i_2
(.I0(count1_reg__0[5]),
.I1(count1_reg__0[4]),
.I2(count1_reg__0[6]),
.O(\shift_reg1_reg[15]_0 ));
(* SOFT_HLUTNM = "soft_lutpair193" *)
LUT4 #(
.INIT(16'hFFFE))
\shift_reg1[15]_i_3
(.I0(count1_reg__0[1]),
.I1(count1_reg__0[0]),
.I2(count1_reg__0[3]),
.I3(count1_reg__0[2]),
.O(\shift_reg1_reg[15]_1 ));
FDRE \shift_reg1_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shift_reg1_reg[15]_2 ),
.Q(\slaveRegDo_ffa_reg[15]_0 ),
.R(1'b0));
LUT3 #(
.INIT(8'h74))
\slaveRegDo_ff8[12]_i_1
(.I0(count_tt),
.I1(slaveRegDo_ff8),
.I2(\slaveRegDo_ff8_reg_n_0_[12] ),
.O(\slaveRegDo_ff8[12]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\slaveRegDo_ff8[7]_i_1
(.I0(count_tt),
.I1(slaveRegDo_ff8),
.I2(\slaveRegDo_ff8_reg_n_0_[7] ),
.O(\slaveRegDo_ff8[7]_i_1_n_0 ));
FDSE \slaveRegDo_ff8_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_ff8[12]_i_1_n_0 ),
.Q(\slaveRegDo_ff8_reg_n_0_[12] ),
.S(s_rst_o));
FDRE \slaveRegDo_ff8_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_ff8[7]_i_1_n_0 ),
.Q(\slaveRegDo_ff8_reg_n_0_[7] ),
.R(s_rst_o));
FDRE \slaveRegDo_ff9_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_ff9_reg[8]_0 ),
.Q(slaveRegDo_ff9),
.R(s_rst_o));
FDRE \slaveRegDo_ffa_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_ffa_reg[15]_0 ),
.Q(slaveRegDo_ffa),
.R(s_rst_o));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux[0]_i_2
(.I0(slaveRegDo_mux_3[0]),
.I1(slaveRegDo_mux_2[0]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_1[0]),
.I4(s_daddr_o[10]),
.I5(slaveRegDo_mux_0[0]),
.O(\slaveRegDo_mux[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[0]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[0] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[0]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[0]),
.O(\slaveRegDo_mux[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[10]_i_2
(.I0(slaveRegDo_mux_3[10]),
.I1(slaveRegDo_mux_2[10]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[10]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[10]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[10] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[10]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[10]),
.O(\slaveRegDo_mux[10]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[11]_i_2
(.I0(slaveRegDo_mux_3[11]),
.I1(slaveRegDo_mux_2[11]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[11]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[11]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[11]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[11] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[11]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[11]),
.O(\slaveRegDo_mux[11]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[12]_i_2
(.I0(slaveRegDo_mux_3[12]),
.I1(slaveRegDo_mux_2[12]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[12]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[12]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[12]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[12] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[12]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[12]),
.O(\slaveRegDo_mux[12]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[13]_i_2
(.I0(slaveRegDo_mux_3[13]),
.I1(slaveRegDo_mux_2[13]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[13]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[13]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[13]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[13] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[13]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[13]),
.O(\slaveRegDo_mux[13]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[14]_i_2
(.I0(slaveRegDo_mux_3[14]),
.I1(slaveRegDo_mux_2[14]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[14]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[14]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[14]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[14] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[14]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[14]),
.O(\slaveRegDo_mux[14]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[15]_i_2
(.I0(slaveRegDo_mux_3[15]),
.I1(slaveRegDo_mux_2[15]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[15]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[15]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[15] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[15]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[15]),
.O(\slaveRegDo_mux[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux[1]_i_2
(.I0(slaveRegDo_mux_3[1]),
.I1(slaveRegDo_mux_2[1]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_1[1]),
.I4(s_daddr_o[10]),
.I5(slaveRegDo_mux_0[1]),
.O(\slaveRegDo_mux[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[1]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[1] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[1]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[1]),
.O(\slaveRegDo_mux[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux[2]_i_2
(.I0(slaveRegDo_mux_3[2]),
.I1(slaveRegDo_mux_2[2]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_1[2]),
.I4(s_daddr_o[10]),
.I5(slaveRegDo_mux_0[2]),
.O(\slaveRegDo_mux[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[2]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[2] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[2]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[2]),
.O(\slaveRegDo_mux[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux[3]_i_2
(.I0(slaveRegDo_mux_3[3]),
.I1(slaveRegDo_mux_2[3]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_1[3]),
.I4(s_daddr_o[10]),
.I5(slaveRegDo_mux_0[3]),
.O(\slaveRegDo_mux[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[3]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[3] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[3]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[3]),
.O(\slaveRegDo_mux[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux[4]_i_2
(.I0(slaveRegDo_mux_3[4]),
.I1(slaveRegDo_mux_2[4]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_1[4]),
.I4(s_daddr_o[10]),
.I5(slaveRegDo_mux_0[4]),
.O(\slaveRegDo_mux[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[4]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[4] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[4]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[4]),
.O(\slaveRegDo_mux[4]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[5]_i_2
(.I0(slaveRegDo_mux_3[5]),
.I1(slaveRegDo_mux_2[5]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[5]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[5]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[5] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[5]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[5]),
.O(\slaveRegDo_mux[5]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[6]_i_2
(.I0(slaveRegDo_mux_3[6]),
.I1(slaveRegDo_mux_2[6]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[6]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[6]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[6]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[6] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[6]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[6]),
.O(\slaveRegDo_mux[6]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[7]_i_2
(.I0(slaveRegDo_mux_3[7]),
.I1(slaveRegDo_mux_2[7]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[7]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[7]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[7]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[7] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[7]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[7]),
.O(\slaveRegDo_mux[7]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[8]_i_2
(.I0(slaveRegDo_mux_3[8]),
.I1(slaveRegDo_mux_2[8]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[8]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[8]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[8] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[8]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[8]),
.O(\slaveRegDo_mux[8]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[9]_i_2
(.I0(slaveRegDo_mux_3[9]),
.I1(slaveRegDo_mux_2[9]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[9]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[9]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[9]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[9] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[9]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[9]),
.O(\slaveRegDo_mux[9]_i_3_n_0 ));
LUT2 #(
.INIT(4'hE))
\slaveRegDo_mux_0[15]_i_1
(.I0(\slaveRegDo_mux_0[4]_i_5_n_0 ),
.I1(s_daddr_o[6]),
.O(\slaveRegDo_mux_0[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair204" *)
LUT3 #(
.INIT(8'h45))
\slaveRegDo_mux_0[15]_i_9
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[2]),
.O(\slaveRegDo_mux_0[15]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair208" *)
LUT2 #(
.INIT(4'h2))
\slaveRegDo_mux_0[3]_i_9
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.O(\slaveRegDo_mux_0[3]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair209" *)
LUT2 #(
.INIT(4'h1))
\slaveRegDo_mux_0[4]_i_12
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[3]),
.O(\slaveRegDo_mux_0[4]_i_12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair207" *)
LUT2 #(
.INIT(4'h1))
\slaveRegDo_mux_0[4]_i_3
(.I0(s_daddr_o[7]),
.I1(s_daddr_o[5]),
.O(\slaveRegDo_mux_0[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFF8AFFFFFFAA))
\slaveRegDo_mux_0[4]_i_5
(.I0(s_daddr_o[7]),
.I1(regDrdy_i_3_n_0),
.I2(\slaveRegDo_mux_0[4]_i_12_n_0 ),
.I3(s_daddr_o[9]),
.I4(s_daddr_o[8]),
.I5(reg_19_n_0),
.O(\slaveRegDo_mux_0[4]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair207" *)
LUT3 #(
.INIT(8'hDC))
\slaveRegDo_mux_0[4]_i_8
(.I0(s_daddr_o[7]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[4]),
.O(\slaveRegDo_mux_0[4]_i_8_n_0 ));
FDRE \slaveRegDo_mux_0_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(slaveRegDo_mux_0[0]),
.R(1'b0));
FDRE \slaveRegDo_mux_0_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_7),
.Q(slaveRegDo_mux_0[10]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_6),
.Q(slaveRegDo_mux_0[11]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_5),
.Q(slaveRegDo_mux_0[12]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_4),
.Q(slaveRegDo_mux_0[13]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_3),
.Q(slaveRegDo_mux_0[14]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_1a_n_2),
.Q(slaveRegDo_mux_0[15]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(slaveRegDo_mux_0[1]),
.R(1'b0));
FDRE \slaveRegDo_mux_0_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(slaveRegDo_mux_0[2]),
.R(1'b0));
FDRE \slaveRegDo_mux_0_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(slaveRegDo_mux_0[3]),
.R(1'b0));
FDRE \slaveRegDo_mux_0_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[4]),
.Q(slaveRegDo_mux_0[4]),
.R(1'b0));
FDRE \slaveRegDo_mux_0_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_12),
.Q(slaveRegDo_mux_0[5]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_11),
.Q(slaveRegDo_mux_0[6]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_10),
.Q(slaveRegDo_mux_0[7]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_9),
.Q(slaveRegDo_mux_0[8]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_8),
.Q(slaveRegDo_mux_0[9]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000A009A0A700AFF))
\slaveRegDo_mux_1[0]_i_1
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[4]),
.I5(s_daddr_o[3]),
.O(\slaveRegDo_mux_1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000002000CC00))
\slaveRegDo_mux_1[1]_i_1
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[0]),
.I5(s_daddr_o[3]),
.O(\slaveRegDo_mux_1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0030003033080000))
\slaveRegDo_mux_1[2]_i_1
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[4]),
.I5(s_daddr_o[5]),
.O(\slaveRegDo_mux_1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000004000))
\slaveRegDo_mux_1[3]_i_1
(.I0(s_daddr_o[5]),
.I1(s_daddr_o[4]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(s_daddr_o[2]),
.I5(s_daddr_o[3]),
.O(\slaveRegDo_mux_1[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000002800000000))
\slaveRegDo_mux_1[4]_i_1
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[4]),
.I5(s_daddr_o[3]),
.O(\slaveRegDo_mux_1[4]_i_1_n_0 ));
FDRE \slaveRegDo_mux_1_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_mux_1[0]_i_1_n_0 ),
.Q(slaveRegDo_mux_1[0]),
.R(1'b0));
FDRE \slaveRegDo_mux_1_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_mux_1[1]_i_1_n_0 ),
.Q(slaveRegDo_mux_1[1]),
.R(1'b0));
FDRE \slaveRegDo_mux_1_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_mux_1[2]_i_1_n_0 ),
.Q(slaveRegDo_mux_1[2]),
.R(1'b0));
FDRE \slaveRegDo_mux_1_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_mux_1[3]_i_1_n_0 ),
.Q(slaveRegDo_mux_1[3]),
.R(1'b0));
FDRE \slaveRegDo_mux_1_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_mux_1[4]_i_1_n_0 ),
.Q(slaveRegDo_mux_1[4]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair190" *)
LUT5 #(
.INIT(32'h00000010))
\slaveRegDo_mux_2[0]_i_2
(.I0(s_daddr_o[5]),
.I1(s_daddr_o[6]),
.I2(s_daddr_o[7]),
.I3(s_daddr_o[9]),
.I4(s_daddr_o[8]),
.O(\slaveRegDo_mux_2[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000400))
\slaveRegDo_mux_2[0]_i_3
(.I0(s_daddr_o[3]),
.I1(slaveRegDo_890[0]),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[4]),
.I4(s_daddr_o[0]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_2[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair204" *)
LUT3 #(
.INIT(8'h40))
\slaveRegDo_mux_2[0]_i_5
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[2]),
.O(\slaveRegDo_mux_2[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\slaveRegDo_mux_2[15]_i_1
(.I0(\slaveRegDo_mux_2[4]_i_3_n_0 ),
.O(\slaveRegDo_mux_2[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair199" *)
LUT4 #(
.INIT(16'hFFFE))
\slaveRegDo_mux_2[15]_i_3
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_2[15]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair202" *)
LUT3 #(
.INIT(8'h08))
\slaveRegDo_mux_2[15]_i_4
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[4]),
.O(\slaveRegDo_mux_2[15]_i_4_n_0 ));
LUT6 #(
.INIT(64'h000F000000000044))
\slaveRegDo_mux_2[2]_i_3
(.I0(s_daddr_o[2]),
.I1(slaveRegDo_890[2]),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[1]),
.I5(s_daddr_o[0]),
.O(\slaveRegDo_mux_2[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000E00000000000))
\slaveRegDo_mux_2[4]_i_3
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[4]),
.I2(reg_19_n_0),
.I3(s_daddr_o[7]),
.I4(\slaveRegDo_mux_2[4]_i_5_n_0 ),
.I5(\slaveRegDo_mux_2[4]_i_6_n_0 ),
.O(\slaveRegDo_mux_2[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000080000))
\slaveRegDo_mux_2[4]_i_4
(.I0(s_daddr_o[7]),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[2]),
.I4(reg_19_n_0),
.I5(\slaveRegDo_mux_2[4]_i_5_n_0 ),
.O(\slaveRegDo_mux_2[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair192" *)
LUT2 #(
.INIT(4'hE))
\slaveRegDo_mux_2[4]_i_5
(.I0(s_daddr_o[9]),
.I1(s_daddr_o[8]),
.O(\slaveRegDo_mux_2[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF80FF))
\slaveRegDo_mux_2[4]_i_6
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(\slaveRegDo_mux_0[4]_i_12_n_0 ),
.I4(s_daddr_o[9]),
.I5(s_daddr_o[8]),
.O(\slaveRegDo_mux_2[4]_i_6_n_0 ));
FDRE \slaveRegDo_mux_2_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88d_n_0),
.Q(slaveRegDo_mux_2[0]),
.R(1'b0));
FDRE \slaveRegDo_mux_2_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_5),
.Q(slaveRegDo_mux_2[10]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_6),
.Q(slaveRegDo_mux_2[11]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_7),
.Q(slaveRegDo_mux_2[12]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_8),
.Q(slaveRegDo_mux_2[13]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_9),
.Q(slaveRegDo_mux_2[14]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_10),
.Q(slaveRegDo_mux_2[15]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_15),
.Q(slaveRegDo_mux_2[1]),
.R(1'b0));
FDRE \slaveRegDo_mux_2_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_14),
.Q(slaveRegDo_mux_2[2]),
.R(1'b0));
FDRE \slaveRegDo_mux_2_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_13),
.Q(slaveRegDo_mux_2[3]),
.R(1'b0));
FDRE \slaveRegDo_mux_2_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_12),
.Q(slaveRegDo_mux_2[4]),
.R(1'b0));
FDRE \slaveRegDo_mux_2_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_0),
.Q(slaveRegDo_mux_2[5]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_1),
.Q(slaveRegDo_mux_2[6]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_2),
.Q(slaveRegDo_mux_2[7]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_3),
.Q(slaveRegDo_mux_2[8]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_4),
.Q(slaveRegDo_mux_2[9]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair200" *)
LUT4 #(
.INIT(16'h3022))
\slaveRegDo_mux_3[11]_i_3
(.I0(\slaveRegDo_ff8_reg_n_0_[12] ),
.I1(s_daddr_o[0]),
.I2(slaveRegDo_ffa),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_3[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair200" *)
LUT3 #(
.INIT(8'h02))
\slaveRegDo_mux_3[12]_i_2
(.I0(\slaveRegDo_ff8_reg_n_0_[12] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.O(\slaveRegDo_mux_3[12]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair199" *)
LUT3 #(
.INIT(8'hDF))
\slaveRegDo_mux_3[15]_i_3
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[3]),
.O(\slaveRegDo_mux_3[15]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair209" *)
LUT2 #(
.INIT(4'h8))
\slaveRegDo_mux_3[15]_i_4
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[3]),
.O(\slaveRegDo_mux_3[15]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair196" *)
LUT3 #(
.INIT(8'h20))
\slaveRegDo_mux_3[6]_i_2
(.I0(slaveRegDo_ff9),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.O(\slaveRegDo_mux_3[6]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair196" *)
LUT4 #(
.INIT(16'h2320))
\slaveRegDo_mux_3[7]_i_3
(.I0(slaveRegDo_ff9),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(\slaveRegDo_ff8_reg_n_0_[7] ),
.O(\slaveRegDo_mux_3[7]_i_3_n_0 ));
FDRE \slaveRegDo_mux_3_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_0),
.Q(slaveRegDo_mux_3[0]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_2 ),
.Q(slaveRegDo_mux_3[10]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_1),
.Q(slaveRegDo_mux_3[11]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_0 ),
.Q(slaveRegDo_mux_3[12]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_10 ),
.Q(slaveRegDo_mux_3[13]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_3 ),
.Q(slaveRegDo_mux_3[14]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_4 ),
.Q(slaveRegDo_mux_3[15]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_9),
.Q(slaveRegDo_mux_3[1]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_8),
.Q(slaveRegDo_mux_3[2]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_7),
.Q(slaveRegDo_mux_3[3]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_6),
.Q(slaveRegDo_mux_3[4]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_5),
.Q(slaveRegDo_mux_3[5]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_1 ),
.Q(slaveRegDo_mux_3[6]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_4),
.Q(slaveRegDo_mux_3[7]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_3),
.Q(slaveRegDo_mux_3[8]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_2),
.Q(slaveRegDo_mux_3[9]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_4_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_15 ),
.Q(slaveRegDo_mux_4[0]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_5 ),
.Q(slaveRegDo_mux_4[10]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_4 ),
.Q(slaveRegDo_mux_4[11]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_3 ),
.Q(slaveRegDo_mux_4[12]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_2 ),
.Q(slaveRegDo_mux_4[13]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_1 ),
.Q(slaveRegDo_mux_4[14]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_0 ),
.Q(slaveRegDo_mux_4[15]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_14 ),
.Q(slaveRegDo_mux_4[1]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_13 ),
.Q(slaveRegDo_mux_4[2]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_12 ),
.Q(slaveRegDo_mux_4[3]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_11 ),
.Q(slaveRegDo_mux_4[4]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_10 ),
.Q(slaveRegDo_mux_4[5]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_9 ),
.Q(slaveRegDo_mux_4[6]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_8 ),
.Q(slaveRegDo_mux_4[7]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_7 ),
.Q(slaveRegDo_mux_4[8]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_6 ),
.Q(slaveRegDo_mux_4[9]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_5_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_15 ),
.Q(slaveRegDo_mux_5[0]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_5 ),
.Q(slaveRegDo_mux_5[10]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_4 ),
.Q(slaveRegDo_mux_5[11]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_3 ),
.Q(slaveRegDo_mux_5[12]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_2 ),
.Q(slaveRegDo_mux_5[13]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_1 ),
.Q(slaveRegDo_mux_5[14]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_0 ),
.Q(slaveRegDo_mux_5[15]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_14 ),
.Q(slaveRegDo_mux_5[1]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_13 ),
.Q(slaveRegDo_mux_5[2]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_12 ),
.Q(slaveRegDo_mux_5[3]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_11 ),
.Q(slaveRegDo_mux_5[4]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_10 ),
.Q(slaveRegDo_mux_5[5]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_9 ),
.Q(slaveRegDo_mux_5[6]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_8 ),
.Q(slaveRegDo_mux_5[7]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_7 ),
.Q(slaveRegDo_mux_5[8]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_6 ),
.Q(slaveRegDo_mux_5[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\slaveRegDo_mux_6[15]_i_2
(.I0(s_daddr_o[4]),
.I1(reg_19_n_0),
.I2(s_daddr_o[7]),
.I3(s_daddr_o[8]),
.I4(s_daddr_o[9]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.O(\slaveRegDo_mux_6[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFDFFFFF))
\slaveRegDo_mux_6[15]_i_4
(.I0(\slaveRegDo_mux_0[4]_i_12_n_0 ),
.I1(\slaveRegDo_mux_2[4]_i_5_n_0 ),
.I2(\slaveRegDo_mux_0[4]_i_3_n_0 ),
.I3(drdy_ff8_i_2_n_0),
.I4(s_daddr_o[2]),
.I5(s_daddr_o[6]),
.O(\slaveRegDo_mux_6[15]_i_4_n_0 ));
FDRE \slaveRegDo_mux_6_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_15 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[0] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_5 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[10] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_4 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[11] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_3 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[12] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_2 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[13] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_1 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[14] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[15] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_14 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[1] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_13 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[2] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_12 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[3] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_11 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[4] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_10 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[5] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_9 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[6] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_8 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[7] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_7 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[8] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_6 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[9] ),
.R(1'b0));
FDRE \slaveRegDo_mux_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[0]),
.Q(\slaveRegDo_mux_reg_n_0_[0] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[0]_i_1
(.I0(\slaveRegDo_mux[0]_i_2_n_0 ),
.I1(\slaveRegDo_mux[0]_i_3_n_0 ),
.O(slaveRegDo_mux[0]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[10]),
.Q(\slaveRegDo_mux_reg_n_0_[10] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[10]_i_1
(.I0(\slaveRegDo_mux[10]_i_2_n_0 ),
.I1(\slaveRegDo_mux[10]_i_3_n_0 ),
.O(slaveRegDo_mux[10]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[11]),
.Q(\slaveRegDo_mux_reg_n_0_[11] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[11]_i_1
(.I0(\slaveRegDo_mux[11]_i_2_n_0 ),
.I1(\slaveRegDo_mux[11]_i_3_n_0 ),
.O(slaveRegDo_mux[11]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[12]),
.Q(\slaveRegDo_mux_reg_n_0_[12] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[12]_i_1
(.I0(\slaveRegDo_mux[12]_i_2_n_0 ),
.I1(\slaveRegDo_mux[12]_i_3_n_0 ),
.O(slaveRegDo_mux[12]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[13]),
.Q(\slaveRegDo_mux_reg_n_0_[13] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[13]_i_1
(.I0(\slaveRegDo_mux[13]_i_2_n_0 ),
.I1(\slaveRegDo_mux[13]_i_3_n_0 ),
.O(slaveRegDo_mux[13]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[14]),
.Q(\slaveRegDo_mux_reg_n_0_[14] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[14]_i_1
(.I0(\slaveRegDo_mux[14]_i_2_n_0 ),
.I1(\slaveRegDo_mux[14]_i_3_n_0 ),
.O(slaveRegDo_mux[14]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[15]),
.Q(\slaveRegDo_mux_reg_n_0_[15] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[15]_i_1
(.I0(\slaveRegDo_mux[15]_i_2_n_0 ),
.I1(\slaveRegDo_mux[15]_i_3_n_0 ),
.O(slaveRegDo_mux[15]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[1]),
.Q(\slaveRegDo_mux_reg_n_0_[1] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[1]_i_1
(.I0(\slaveRegDo_mux[1]_i_2_n_0 ),
.I1(\slaveRegDo_mux[1]_i_3_n_0 ),
.O(slaveRegDo_mux[1]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[2]),
.Q(\slaveRegDo_mux_reg_n_0_[2] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[2]_i_1
(.I0(\slaveRegDo_mux[2]_i_2_n_0 ),
.I1(\slaveRegDo_mux[2]_i_3_n_0 ),
.O(slaveRegDo_mux[2]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[3]),
.Q(\slaveRegDo_mux_reg_n_0_[3] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[3]_i_1
(.I0(\slaveRegDo_mux[3]_i_2_n_0 ),
.I1(\slaveRegDo_mux[3]_i_3_n_0 ),
.O(slaveRegDo_mux[3]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[4]),
.Q(\slaveRegDo_mux_reg_n_0_[4] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[4]_i_1
(.I0(\slaveRegDo_mux[4]_i_2_n_0 ),
.I1(\slaveRegDo_mux[4]_i_3_n_0 ),
.O(slaveRegDo_mux[4]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[5]),
.Q(\slaveRegDo_mux_reg_n_0_[5] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[5]_i_1
(.I0(\slaveRegDo_mux[5]_i_2_n_0 ),
.I1(\slaveRegDo_mux[5]_i_3_n_0 ),
.O(slaveRegDo_mux[5]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[6]),
.Q(\slaveRegDo_mux_reg_n_0_[6] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[6]_i_1
(.I0(\slaveRegDo_mux[6]_i_2_n_0 ),
.I1(\slaveRegDo_mux[6]_i_3_n_0 ),
.O(slaveRegDo_mux[6]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[7]),
.Q(\slaveRegDo_mux_reg_n_0_[7] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[7]_i_1
(.I0(\slaveRegDo_mux[7]_i_2_n_0 ),
.I1(\slaveRegDo_mux[7]_i_3_n_0 ),
.O(slaveRegDo_mux[7]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[8]),
.Q(\slaveRegDo_mux_reg_n_0_[8] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[8]_i_1
(.I0(\slaveRegDo_mux[8]_i_2_n_0 ),
.I1(\slaveRegDo_mux[8]_i_3_n_0 ),
.O(slaveRegDo_mux[8]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[9]),
.Q(\slaveRegDo_mux_reg_n_0_[9] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[9]_i_1
(.I0(\slaveRegDo_mux[9]_i_2_n_0 ),
.I1(\slaveRegDo_mux[9]_i_3_n_0 ),
.O(slaveRegDo_mux[9]),
.S(s_daddr_o[12]));
(* SOFT_HLUTNM = "soft_lutpair191" *)
LUT5 #(
.INIT(32'h7FFF8000))
toggle_rd_i_1
(.I0(bram_rd_en_i_2_n_0),
.I1(bram_rd_en_i_3_n_0),
.I2(config_fsm_en_rb),
.I3(bram_rd_en_i_4_n_0),
.I4(toggle_rd),
.O(toggle_rd_reg));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_register
(s_dclk_o,
s_rst_o,
s_den_o,
s_dwe_o,
s_daddr_o,
SL_OPORT_O,
drdy_ff9,
\slaveRegDo_ff9_reg[8]_0 ,
drdy_ffa,
\slaveRegDo_ffa_reg[15]_0 ,
slaveRegDo_ff8,
count_tt,
adv_drdy,
\I_EN_CTL_EQ1.temp_en_reg ,
read_reset_addr,
capture_qual_ctrl_1,
\shift_reg1_reg[15]_0 ,
toggle_rd_reg,
toggle_reg,
D,
halt_ctrl,
arm_ctrl,
use_probe_debug_circuit_1,
SR,
en_adv_trigger_1,
debug_data_in,
bram_rd_en,
bram_en,
scnt_cmp_temp,
wcnt_lcmp_temp,
wcnt_hcmp_temp,
regDrdy_reg_0,
read_data_en,
\shift_reg0_reg[8]_0 ,
\shift_reg0_reg[8]_1 ,
\shift_reg1_reg[15]_1 ,
\parallel_dout_reg[0] ,
qual_strg_config_cs_serial_output,
\parallel_dout_reg[0]_0 ,
capture_ctrl_config_serial_output,
mu_config_cs_shift_en,
mu_config_cs_serial_output,
tc_config_cs_shift_en,
tc_config_cs_serial_output,
cnt_config_cs_shift_en,
CFG_CNT_DIN,
SL_IPORT_I,
E,
DUMMY_I,
count_tt_reg_0,
\shift_reg0_reg[8]_2 ,
\shift_reg1_reg[15]_2 ,
\G_1PIPE_IFACE.s_den_r_reg ,
en_adv_trigger,
toggle_rd,
toggle_reg_0,
\CFG_DATA_O_reg[15] ,
\input_data_reg[31] ,
CAP_DONE_O_reg,
\captured_samples_reg[14] ,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
flag3_temp,
flag2_temp,
flag1_temp,
flag0_temp,
SEQUENCER_STATE_O,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
DOUT_O,
shift_en_reg,
shift_en_reg_0,
\G_1PIPE_IFACE.s_daddr_r_reg[10] ,
\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
shift_en_reg_1,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[11]_0 ,
shift_en_reg_2,
mu_config_cs_serial_input,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[11]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ,
\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ,
CFG_CNT_DOUT); |
output s_dclk_o;
output s_rst_o;
output s_den_o;
output s_dwe_o;
output [12:0]s_daddr_o;
output [16:0]SL_OPORT_O;
output drdy_ff9;
output \slaveRegDo_ff9_reg[8]_0 ;
output drdy_ffa;
output \slaveRegDo_ffa_reg[15]_0 ;
output [0:0]slaveRegDo_ff8;
output count_tt;
output adv_drdy;
output \I_EN_CTL_EQ1.temp_en_reg ;
output [14:0]read_reset_addr;
output [1:0]capture_qual_ctrl_1;
output \shift_reg1_reg[15]_0 ;
output toggle_rd_reg;
output toggle_reg;
output [15:0]D;
output halt_ctrl;
output arm_ctrl;
output use_probe_debug_circuit_1;
output [0:0]SR;
output en_adv_trigger_1;
output [1:0]debug_data_in;
output bram_rd_en;
output bram_en;
output scnt_cmp_temp;
output wcnt_lcmp_temp;
output wcnt_hcmp_temp;
output regDrdy_reg_0;
output read_data_en;
output \shift_reg0_reg[8]_0 ;
output \shift_reg0_reg[8]_1 ;
output \shift_reg1_reg[15]_1 ;
output [0:0]\parallel_dout_reg[0] ;
output qual_strg_config_cs_serial_output;
output [0:0]\parallel_dout_reg[0]_0 ;
output capture_ctrl_config_serial_output;
output [9:0]mu_config_cs_shift_en;
output [9:0]mu_config_cs_serial_output;
output [31:0]tc_config_cs_shift_en;
output [31:0]tc_config_cs_serial_output;
output [3:0]cnt_config_cs_shift_en;
output [3:0]CFG_CNT_DIN;
input [36:0]SL_IPORT_I;
input [0:0]E;
input DUMMY_I;
input count_tt_reg_0;
input \shift_reg0_reg[8]_2 ;
input \shift_reg1_reg[15]_2 ;
input \G_1PIPE_IFACE.s_den_r_reg ;
input en_adv_trigger;
input toggle_rd;
input [0:0]toggle_reg_0;
input [15:0]\CFG_DATA_O_reg[15] ;
input [15:0]\input_data_reg[31] ;
input [3:0]CAP_DONE_O_reg;
input [14:0]\captured_samples_reg[14] ;
input [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ;
input flag3_temp;
input flag2_temp;
input flag1_temp;
input flag0_temp;
input [15:0]SEQUENCER_STATE_O;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input DOUT_O;
input shift_en_reg;
input shift_en_reg_0;
input \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input [0:0]shift_en_reg_1;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[11]_0 ;
input [0:0]shift_en_reg_2;
input [9:0]mu_config_cs_serial_input;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[11]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ;
input [31:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ;
input [3:0]CFG_CNT_DOUT;
wire \ADV_TRIG_STREAM.reg_stream_ffc_n_3 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_0 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_1 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_10 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_11 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_12 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_13 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_14 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_15 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_2 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_3 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_4 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_5 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_6 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_7 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_8 ;
wire \ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_9 ;
wire [3:0]CAP_DONE_O_reg;
wire [3:0]CFG_CNT_DIN;
wire [3:0]CFG_CNT_DOUT;
wire [15:0]\CFG_DATA_O_reg[15] ;
wire \CNT.CNT_SRL[1].cnt_srl_reg_n_0 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_0 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_1 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_10 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_11 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_12 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_13 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_14 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_15 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_16 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_2 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_3 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_4 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_5 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_6 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_7 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_8 ;
wire \CNT.CNT_SRL[3].cnt_srl_reg_n_9 ;
wire [15:0]D;
wire DOUT_O;
wire DUMMY_I;
wire [0:0]E;
wire FSM_BRAM_EN_RB_O_i_2_n_0;
wire FSM_BRAM_EN_RB_O_i_3_n_0;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_den_r_reg ;
wire \I_EN_CTL_EQ1.temp_en_reg ;
wire [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire \MU_SRL[11].mu_srl_reg_n_0 ;
wire \MU_SRL[11].mu_srl_reg_n_1 ;
wire \MU_SRL[11].mu_srl_reg_n_10 ;
wire \MU_SRL[11].mu_srl_reg_n_11 ;
wire \MU_SRL[11].mu_srl_reg_n_12 ;
wire \MU_SRL[11].mu_srl_reg_n_13 ;
wire \MU_SRL[11].mu_srl_reg_n_14 ;
wire \MU_SRL[11].mu_srl_reg_n_15 ;
wire \MU_SRL[11].mu_srl_reg_n_2 ;
wire \MU_SRL[11].mu_srl_reg_n_3 ;
wire \MU_SRL[11].mu_srl_reg_n_4 ;
wire \MU_SRL[11].mu_srl_reg_n_5 ;
wire \MU_SRL[11].mu_srl_reg_n_6 ;
wire \MU_SRL[11].mu_srl_reg_n_7 ;
wire \MU_SRL[11].mu_srl_reg_n_8 ;
wire \MU_SRL[11].mu_srl_reg_n_9 ;
wire \MU_SRL[15].mu_srl_reg_n_0 ;
wire \MU_SRL[15].mu_srl_reg_n_1 ;
wire \MU_SRL[15].mu_srl_reg_n_10 ;
wire \MU_SRL[15].mu_srl_reg_n_11 ;
wire \MU_SRL[15].mu_srl_reg_n_12 ;
wire \MU_SRL[15].mu_srl_reg_n_13 ;
wire \MU_SRL[15].mu_srl_reg_n_14 ;
wire \MU_SRL[15].mu_srl_reg_n_15 ;
wire \MU_SRL[15].mu_srl_reg_n_2 ;
wire \MU_SRL[15].mu_srl_reg_n_3 ;
wire \MU_SRL[15].mu_srl_reg_n_4 ;
wire \MU_SRL[15].mu_srl_reg_n_5 ;
wire \MU_SRL[15].mu_srl_reg_n_6 ;
wire \MU_SRL[15].mu_srl_reg_n_7 ;
wire \MU_SRL[15].mu_srl_reg_n_8 ;
wire \MU_SRL[15].mu_srl_reg_n_9 ;
wire \MU_SRL[3].mu_srl_reg_n_0 ;
wire \MU_SRL[3].mu_srl_reg_n_1 ;
wire \MU_SRL[3].mu_srl_reg_n_10 ;
wire \MU_SRL[3].mu_srl_reg_n_11 ;
wire \MU_SRL[3].mu_srl_reg_n_12 ;
wire \MU_SRL[3].mu_srl_reg_n_13 ;
wire \MU_SRL[3].mu_srl_reg_n_14 ;
wire \MU_SRL[3].mu_srl_reg_n_15 ;
wire \MU_SRL[3].mu_srl_reg_n_2 ;
wire \MU_SRL[3].mu_srl_reg_n_3 ;
wire \MU_SRL[3].mu_srl_reg_n_4 ;
wire \MU_SRL[3].mu_srl_reg_n_5 ;
wire \MU_SRL[3].mu_srl_reg_n_6 ;
wire \MU_SRL[3].mu_srl_reg_n_7 ;
wire \MU_SRL[3].mu_srl_reg_n_8 ;
wire \MU_SRL[3].mu_srl_reg_n_9 ;
wire [15:0]SEQUENCER_STATE_O;
wire [36:0]SL_IPORT_I;
wire [16:0]SL_OPORT_O;
wire [0:0]SR;
wire \STRG_QUAL.qual_strg_srl_reg_n_1 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_10 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_11 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_12 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_13 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_14 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_15 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_2 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_3 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_4 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_5 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_6 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_7 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_8 ;
wire \STRG_QUAL.qual_strg_srl_reg_n_9 ;
wire \TC_SRL[11].tc_srl_reg_n_0 ;
wire \TC_SRL[11].tc_srl_reg_n_1 ;
wire \TC_SRL[11].tc_srl_reg_n_10 ;
wire \TC_SRL[11].tc_srl_reg_n_11 ;
wire \TC_SRL[11].tc_srl_reg_n_12 ;
wire \TC_SRL[11].tc_srl_reg_n_13 ;
wire \TC_SRL[11].tc_srl_reg_n_14 ;
wire \TC_SRL[11].tc_srl_reg_n_15 ;
wire \TC_SRL[11].tc_srl_reg_n_2 ;
wire \TC_SRL[11].tc_srl_reg_n_3 ;
wire \TC_SRL[11].tc_srl_reg_n_4 ;
wire \TC_SRL[11].tc_srl_reg_n_5 ;
wire \TC_SRL[11].tc_srl_reg_n_6 ;
wire \TC_SRL[11].tc_srl_reg_n_7 ;
wire \TC_SRL[11].tc_srl_reg_n_8 ;
wire \TC_SRL[11].tc_srl_reg_n_9 ;
wire \TC_SRL[15].tc_srl_reg_n_0 ;
wire \TC_SRL[15].tc_srl_reg_n_1 ;
wire \TC_SRL[15].tc_srl_reg_n_10 ;
wire \TC_SRL[15].tc_srl_reg_n_11 ;
wire \TC_SRL[15].tc_srl_reg_n_12 ;
wire \TC_SRL[15].tc_srl_reg_n_13 ;
wire \TC_SRL[15].tc_srl_reg_n_14 ;
wire \TC_SRL[15].tc_srl_reg_n_15 ;
wire \TC_SRL[15].tc_srl_reg_n_2 ;
wire \TC_SRL[15].tc_srl_reg_n_3 ;
wire \TC_SRL[15].tc_srl_reg_n_4 ;
wire \TC_SRL[15].tc_srl_reg_n_5 ;
wire \TC_SRL[15].tc_srl_reg_n_6 ;
wire \TC_SRL[15].tc_srl_reg_n_7 ;
wire \TC_SRL[15].tc_srl_reg_n_8 ;
wire \TC_SRL[15].tc_srl_reg_n_9 ;
wire \TC_SRL[19].tc_srl_reg_n_0 ;
wire \TC_SRL[19].tc_srl_reg_n_1 ;
wire \TC_SRL[19].tc_srl_reg_n_10 ;
wire \TC_SRL[19].tc_srl_reg_n_11 ;
wire \TC_SRL[19].tc_srl_reg_n_12 ;
wire \TC_SRL[19].tc_srl_reg_n_13 ;
wire \TC_SRL[19].tc_srl_reg_n_14 ;
wire \TC_SRL[19].tc_srl_reg_n_15 ;
wire \TC_SRL[19].tc_srl_reg_n_2 ;
wire \TC_SRL[19].tc_srl_reg_n_3 ;
wire \TC_SRL[19].tc_srl_reg_n_4 ;
wire \TC_SRL[19].tc_srl_reg_n_5 ;
wire \TC_SRL[19].tc_srl_reg_n_6 ;
wire \TC_SRL[19].tc_srl_reg_n_7 ;
wire \TC_SRL[19].tc_srl_reg_n_8 ;
wire \TC_SRL[19].tc_srl_reg_n_9 ;
wire \TC_SRL[23].tc_srl_reg_n_0 ;
wire \TC_SRL[23].tc_srl_reg_n_1 ;
wire \TC_SRL[23].tc_srl_reg_n_10 ;
wire \TC_SRL[23].tc_srl_reg_n_11 ;
wire \TC_SRL[23].tc_srl_reg_n_12 ;
wire \TC_SRL[23].tc_srl_reg_n_13 ;
wire \TC_SRL[23].tc_srl_reg_n_14 ;
wire \TC_SRL[23].tc_srl_reg_n_15 ;
wire \TC_SRL[23].tc_srl_reg_n_2 ;
wire \TC_SRL[23].tc_srl_reg_n_3 ;
wire \TC_SRL[23].tc_srl_reg_n_4 ;
wire \TC_SRL[23].tc_srl_reg_n_5 ;
wire \TC_SRL[23].tc_srl_reg_n_6 ;
wire \TC_SRL[23].tc_srl_reg_n_7 ;
wire \TC_SRL[23].tc_srl_reg_n_8 ;
wire \TC_SRL[23].tc_srl_reg_n_9 ;
wire \TC_SRL[27].tc_srl_reg_n_0 ;
wire \TC_SRL[27].tc_srl_reg_n_1 ;
wire \TC_SRL[27].tc_srl_reg_n_10 ;
wire \TC_SRL[27].tc_srl_reg_n_11 ;
wire \TC_SRL[27].tc_srl_reg_n_12 ;
wire \TC_SRL[27].tc_srl_reg_n_13 ;
wire \TC_SRL[27].tc_srl_reg_n_14 ;
wire \TC_SRL[27].tc_srl_reg_n_15 ;
wire \TC_SRL[27].tc_srl_reg_n_2 ;
wire \TC_SRL[27].tc_srl_reg_n_3 ;
wire \TC_SRL[27].tc_srl_reg_n_4 ;
wire \TC_SRL[27].tc_srl_reg_n_5 ;
wire \TC_SRL[27].tc_srl_reg_n_6 ;
wire \TC_SRL[27].tc_srl_reg_n_7 ;
wire \TC_SRL[27].tc_srl_reg_n_8 ;
wire \TC_SRL[27].tc_srl_reg_n_9 ;
wire \TC_SRL[31].tc_srl_reg_n_0 ;
wire \TC_SRL[31].tc_srl_reg_n_1 ;
wire \TC_SRL[31].tc_srl_reg_n_10 ;
wire \TC_SRL[31].tc_srl_reg_n_11 ;
wire \TC_SRL[31].tc_srl_reg_n_12 ;
wire \TC_SRL[31].tc_srl_reg_n_13 ;
wire \TC_SRL[31].tc_srl_reg_n_14 ;
wire \TC_SRL[31].tc_srl_reg_n_15 ;
wire \TC_SRL[31].tc_srl_reg_n_2 ;
wire \TC_SRL[31].tc_srl_reg_n_3 ;
wire \TC_SRL[31].tc_srl_reg_n_4 ;
wire \TC_SRL[31].tc_srl_reg_n_5 ;
wire \TC_SRL[31].tc_srl_reg_n_6 ;
wire \TC_SRL[31].tc_srl_reg_n_7 ;
wire \TC_SRL[31].tc_srl_reg_n_8 ;
wire \TC_SRL[31].tc_srl_reg_n_9 ;
wire \TC_SRL[3].tc_srl_reg_n_0 ;
wire \TC_SRL[3].tc_srl_reg_n_1 ;
wire \TC_SRL[3].tc_srl_reg_n_10 ;
wire \TC_SRL[3].tc_srl_reg_n_11 ;
wire \TC_SRL[3].tc_srl_reg_n_12 ;
wire \TC_SRL[3].tc_srl_reg_n_13 ;
wire \TC_SRL[3].tc_srl_reg_n_14 ;
wire \TC_SRL[3].tc_srl_reg_n_15 ;
wire \TC_SRL[3].tc_srl_reg_n_2 ;
wire \TC_SRL[3].tc_srl_reg_n_3 ;
wire \TC_SRL[3].tc_srl_reg_n_4 ;
wire \TC_SRL[3].tc_srl_reg_n_5 ;
wire \TC_SRL[3].tc_srl_reg_n_6 ;
wire \TC_SRL[3].tc_srl_reg_n_7 ;
wire \TC_SRL[3].tc_srl_reg_n_8 ;
wire \TC_SRL[3].tc_srl_reg_n_9 ;
wire \TC_SRL[7].tc_srl_reg_n_0 ;
wire \TC_SRL[7].tc_srl_reg_n_1 ;
wire \TC_SRL[7].tc_srl_reg_n_10 ;
wire \TC_SRL[7].tc_srl_reg_n_11 ;
wire \TC_SRL[7].tc_srl_reg_n_12 ;
wire \TC_SRL[7].tc_srl_reg_n_13 ;
wire \TC_SRL[7].tc_srl_reg_n_14 ;
wire \TC_SRL[7].tc_srl_reg_n_15 ;
wire \TC_SRL[7].tc_srl_reg_n_2 ;
wire \TC_SRL[7].tc_srl_reg_n_3 ;
wire \TC_SRL[7].tc_srl_reg_n_4 ;
wire \TC_SRL[7].tc_srl_reg_n_5 ;
wire \TC_SRL[7].tc_srl_reg_n_6 ;
wire \TC_SRL[7].tc_srl_reg_n_7 ;
wire \TC_SRL[7].tc_srl_reg_n_8 ;
wire \TC_SRL[7].tc_srl_reg_n_9 ;
wire adv_drdy;
wire adv_rb_drdy;
wire adv_rb_drdy1;
wire adv_rb_drdy3_reg_srl2_n_0;
wire adv_rb_drdy4;
wire arm_ctrl;
wire bram_en;
wire bram_en_i_2_n_0;
wire bram_en_i_3_n_0;
wire bram_rd_en;
wire bram_rd_en_i_2_n_0;
wire bram_rd_en_i_3_n_0;
wire bram_rd_en_i_4_n_0;
wire capture_ctrl_config_serial_output;
wire [1:0]capture_qual_ctrl_1;
wire [14:0]\captured_samples_reg[14] ;
wire [3:0]cnt_config_cs_shift_en;
wire [16:0]config_fsm_addr;
wire config_fsm_en_rb;
wire config_fsm_we;
wire count00;
wire \count0[6]_i_3_n_0 ;
wire [6:0]count0_reg__0;
wire count10;
wire \count1[6]_i_3_n_0 ;
wire [6:0]count1_reg__0;
wire count_tt;
wire count_tt_reg_0;
wire [1:0]debug_data_in;
wire [5:0]drdyCount;
wire drdyCount1;
wire \drdyCount[0]_i_1_n_0 ;
wire \drdyCount[1]_i_1_n_0 ;
wire \drdyCount[2]_i_1_n_0 ;
wire \drdyCount[3]_i_1_n_0 ;
wire \drdyCount[4]_i_1_n_0 ;
wire \drdyCount[4]_i_2_n_0 ;
wire \drdyCount[4]_i_3_n_0 ;
wire \drdyCount[5]_i_1_n_0 ;
wire \drdyCount[5]_i_2_n_0 ;
wire \drdyCount[5]_i_3_n_0 ;
wire \drdyCount[5]_i_5_n_0 ;
wire \drdyCount[5]_i_6_n_0 ;
wire drdy_ff7;
wire drdy_ff7_i_2_n_0;
wire drdy_ff7_i_3_n_0;
wire drdy_ff8;
wire drdy_ff8_i_2_n_0;
wire drdy_ff9;
wire drdy_ff9_i_2_n_0;
wire drdy_ff9_i_3_n_0;
wire drdy_ffa;
wire drdy_mux_ff;
wire drdy_mux_ff1;
wire drdy_mux_temp;
(* DONT_TOUCH *) wire dummy_temp;
(* DONT_TOUCH *) wire dummy_temp1;
wire en_adv_trigger;
wire en_adv_trigger_1;
wire flag0_temp;
wire flag1_temp;
wire flag2_temp;
wire flag3_temp;
wire halt_ctrl;
wire [15:0]\input_data_reg[31] ;
wire [9:0]mu_config_cs_serial_input;
wire [9:0]mu_config_cs_serial_output;
wire [9:0]mu_config_cs_shift_en;
wire [4:0]p_0_in;
wire [6:0]p_0_in__0;
wire [6:0]p_0_in__1;
wire [0:0]\parallel_dout_reg[0] ;
wire [0:0]\parallel_dout_reg[0]_0 ;
wire qual_strg_config_cs_serial_output;
wire read_data_en;
wire [14:0]read_reset_addr;
wire regAck_reg;
wire \regAck_reg_n_0_[1] ;
wire regAck_temp;
wire regAck_temp_reg;
wire regDrdy_i_1_n_0;
wire regDrdy_i_3_n_0;
wire regDrdy_i_5_n_0;
wire regDrdy_i_6_n_0;
wire regDrdy_reg_0;
wire regDrdy_reg_i_4_n_0;
wire regDrdy_reg_n_0;
wire reg_15_n_0;
wire reg_15_n_1;
wire reg_15_n_10;
wire reg_15_n_11;
wire reg_15_n_12;
wire reg_15_n_13;
wire reg_15_n_14;
wire reg_15_n_15;
wire reg_15_n_16;
wire reg_15_n_17;
wire reg_15_n_2;
wire reg_15_n_5;
wire reg_15_n_6;
wire reg_15_n_8;
wire reg_15_n_9;
wire reg_16_n_0;
wire reg_16_n_1;
wire reg_17_n_1;
wire reg_17_n_10;
wire reg_17_n_11;
wire reg_17_n_12;
wire reg_17_n_13;
wire reg_17_n_14;
wire reg_17_n_15;
wire reg_17_n_2;
wire reg_17_n_3;
wire reg_17_n_4;
wire reg_17_n_5;
wire reg_17_n_6;
wire reg_17_n_7;
wire reg_17_n_8;
wire reg_17_n_9;
wire reg_18_n_0;
wire reg_18_n_10;
wire reg_18_n_11;
wire reg_18_n_12;
wire reg_18_n_13;
wire reg_18_n_14;
wire reg_18_n_15;
wire reg_18_n_5;
wire reg_18_n_6;
wire reg_18_n_7;
wire reg_18_n_8;
wire reg_18_n_9;
wire reg_19_n_0;
wire reg_19_n_1;
wire reg_19_n_10;
wire reg_19_n_11;
wire reg_19_n_12;
wire reg_19_n_13;
wire reg_19_n_14;
wire reg_19_n_15;
wire reg_19_n_16;
wire reg_19_n_17;
wire reg_19_n_2;
wire reg_19_n_3;
wire reg_19_n_4;
wire reg_19_n_5;
wire reg_19_n_6;
wire reg_19_n_7;
wire reg_19_n_8;
wire reg_19_n_9;
wire reg_1a_n_10;
wire reg_1a_n_11;
wire reg_1a_n_12;
wire reg_1a_n_13;
wire reg_1a_n_14;
wire reg_1a_n_2;
wire reg_1a_n_4;
wire reg_1a_n_5;
wire reg_1a_n_6;
wire reg_1a_n_7;
wire reg_1a_n_8;
wire reg_1a_n_9;
wire reg_6_n_0;
wire reg_6_n_14;
wire reg_6_n_15;
wire reg_7_n_0;
wire reg_7_n_1;
wire reg_7_n_10;
wire reg_7_n_11;
wire reg_7_n_12;
wire reg_7_n_13;
wire reg_7_n_14;
wire reg_7_n_15;
wire reg_7_n_16;
wire reg_7_n_2;
wire reg_7_n_4;
wire reg_7_n_5;
wire reg_7_n_6;
wire reg_7_n_7;
wire reg_7_n_8;
wire reg_7_n_9;
wire reg_83_n_0;
wire reg_83_n_1;
wire reg_83_n_10;
wire reg_83_n_11;
wire reg_83_n_12;
wire reg_83_n_13;
wire reg_83_n_14;
wire reg_83_n_15;
wire reg_83_n_16;
wire reg_83_n_17;
wire reg_83_n_2;
wire reg_83_n_3;
wire reg_83_n_4;
wire reg_83_n_5;
wire reg_83_n_6;
wire reg_83_n_7;
wire reg_83_n_8;
wire reg_83_n_9;
wire reg_84_n_0;
wire reg_84_n_12;
wire reg_84_n_13;
wire reg_84_n_14;
wire reg_84_n_15;
wire reg_85_n_0;
wire reg_85_n_1;
wire reg_85_n_10;
wire reg_85_n_11;
wire reg_85_n_12;
wire reg_85_n_13;
wire reg_85_n_14;
wire reg_85_n_15;
wire reg_85_n_2;
wire reg_85_n_3;
wire reg_85_n_4;
wire reg_85_n_5;
wire reg_85_n_6;
wire reg_85_n_7;
wire reg_85_n_8;
wire reg_85_n_9;
wire reg_887_n_0;
wire reg_88d_n_0;
wire reg_88d_n_1;
wire reg_88f_n_0;
wire reg_88f_n_1;
wire reg_88f_n_10;
wire reg_88f_n_11;
wire reg_88f_n_12;
wire reg_88f_n_13;
wire reg_88f_n_14;
wire reg_88f_n_15;
wire reg_88f_n_16;
wire reg_88f_n_2;
wire reg_88f_n_3;
wire reg_88f_n_4;
wire reg_88f_n_5;
wire reg_88f_n_6;
wire reg_88f_n_7;
wire reg_88f_n_8;
wire reg_88f_n_9;
wire reg_892_n_0;
wire reg_892_n_1;
wire reg_892_n_2;
wire reg_892_n_3;
wire reg_8_n_0;
wire reg_8_n_1;
wire reg_8_n_2;
wire reg_8_n_3;
wire reg_9_n_0;
wire reg_9_n_1;
wire reg_9_n_10;
wire reg_9_n_11;
wire reg_9_n_12;
wire reg_9_n_13;
wire reg_9_n_14;
wire reg_9_n_2;
wire reg_9_n_3;
wire reg_9_n_4;
wire reg_9_n_5;
wire reg_9_n_6;
wire reg_9_n_7;
wire reg_9_n_8;
wire reg_9_n_9;
wire reg_ce;
wire reg_srl_fff_n_0;
wire reg_srl_fff_n_1;
wire reg_srl_fff_n_10;
wire reg_srl_fff_n_11;
wire reg_srl_fff_n_12;
wire reg_srl_fff_n_13;
wire reg_srl_fff_n_14;
wire reg_srl_fff_n_15;
wire reg_srl_fff_n_2;
wire reg_srl_fff_n_3;
wire reg_srl_fff_n_4;
wire reg_srl_fff_n_5;
wire reg_srl_fff_n_6;
wire reg_srl_fff_n_7;
wire reg_srl_fff_n_8;
wire reg_srl_fff_n_9;
wire reg_stream_ffd_n_0;
wire reg_stream_ffd_n_1;
wire reg_stream_ffd_n_10;
wire reg_stream_ffd_n_11;
wire reg_stream_ffd_n_12;
wire reg_stream_ffd_n_13;
wire reg_stream_ffd_n_14;
wire reg_stream_ffd_n_15;
wire reg_stream_ffd_n_16;
wire reg_stream_ffd_n_2;
wire reg_stream_ffd_n_3;
wire reg_stream_ffd_n_4;
wire reg_stream_ffd_n_5;
wire reg_stream_ffd_n_6;
wire reg_stream_ffd_n_7;
wire reg_stream_ffd_n_8;
wire reg_stream_ffd_n_9;
wire reg_stream_ffe_n_0;
wire reg_stream_ffe_n_1;
wire reg_stream_ffe_n_10;
wire reg_stream_ffe_n_11;
wire reg_stream_ffe_n_12;
wire reg_stream_ffe_n_13;
wire reg_stream_ffe_n_14;
wire reg_stream_ffe_n_15;
wire reg_stream_ffe_n_2;
wire reg_stream_ffe_n_3;
wire reg_stream_ffe_n_4;
wire reg_stream_ffe_n_5;
wire reg_stream_ffe_n_6;
wire reg_stream_ffe_n_7;
wire reg_stream_ffe_n_8;
wire reg_stream_ffe_n_9;
wire [16:13]s_daddr;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di;
wire s_dwe_o;
wire s_rst_o;
wire scnt_cmp_temp;
wire shift_en_reg;
wire shift_en_reg_0;
wire [0:0]shift_en_reg_1;
wire [0:0]shift_en_reg_2;
wire \shift_reg0_reg[8]_0 ;
wire \shift_reg0_reg[8]_1 ;
wire \shift_reg0_reg[8]_2 ;
wire \shift_reg1_reg[15]_0 ;
wire \shift_reg1_reg[15]_1 ;
wire \shift_reg1_reg[15]_2 ;
wire [15:0]slaveRegDo_18;
wire [15:0]slaveRegDo_6;
wire [15:0]slaveRegDo_80;
wire [15:0]slaveRegDo_81;
wire [15:0]slaveRegDo_82;
wire [15:5]slaveRegDo_84;
wire [15:0]slaveRegDo_890;
wire [15:0]\slaveRegDo_cntConfig[6144]_42 ;
wire [15:0]\slaveRegDo_cntConfig[6145]_43 ;
wire [15:0]\slaveRegDo_cntConfig[6146]_44 ;
wire [0:0]slaveRegDo_ff8;
wire \slaveRegDo_ff8[12]_i_1_n_0 ;
wire \slaveRegDo_ff8[7]_i_1_n_0 ;
wire \slaveRegDo_ff8_reg_n_0_[12] ;
wire \slaveRegDo_ff8_reg_n_0_[7] ;
wire [8:8]slaveRegDo_ff9;
wire \slaveRegDo_ff9_reg[8]_0 ;
wire [15:15]slaveRegDo_ffa;
wire \slaveRegDo_ffa_reg[15]_0 ;
wire [15:0]\slaveRegDo_muConfig[4096]_0 ;
wire [15:0]\slaveRegDo_muConfig[4097]_1 ;
wire [15:0]\slaveRegDo_muConfig[4098]_2 ;
wire [15:0]\slaveRegDo_muConfig[4104]_4 ;
wire [15:0]\slaveRegDo_muConfig[4105]_5 ;
wire [15:0]\slaveRegDo_muConfig[4106]_6 ;
wire [15:0]\slaveRegDo_muConfig[4110]_8 ;
wire [15:0]slaveRegDo_mux;
wire \slaveRegDo_mux[0]_i_2_n_0 ;
wire \slaveRegDo_mux[0]_i_3_n_0 ;
wire \slaveRegDo_mux[10]_i_2_n_0 ;
wire \slaveRegDo_mux[10]_i_3_n_0 ;
wire \slaveRegDo_mux[11]_i_2_n_0 ;
wire \slaveRegDo_mux[11]_i_3_n_0 ;
wire \slaveRegDo_mux[12]_i_2_n_0 ;
wire \slaveRegDo_mux[12]_i_3_n_0 ;
wire \slaveRegDo_mux[13]_i_2_n_0 ;
wire \slaveRegDo_mux[13]_i_3_n_0 ;
wire \slaveRegDo_mux[14]_i_2_n_0 ;
wire \slaveRegDo_mux[14]_i_3_n_0 ;
wire \slaveRegDo_mux[15]_i_2_n_0 ;
wire \slaveRegDo_mux[15]_i_3_n_0 ;
wire \slaveRegDo_mux[1]_i_2_n_0 ;
wire \slaveRegDo_mux[1]_i_3_n_0 ;
wire \slaveRegDo_mux[2]_i_2_n_0 ;
wire \slaveRegDo_mux[2]_i_3_n_0 ;
wire \slaveRegDo_mux[3]_i_2_n_0 ;
wire \slaveRegDo_mux[3]_i_3_n_0 ;
wire \slaveRegDo_mux[4]_i_2_n_0 ;
wire \slaveRegDo_mux[4]_i_3_n_0 ;
wire \slaveRegDo_mux[5]_i_2_n_0 ;
wire \slaveRegDo_mux[5]_i_3_n_0 ;
wire \slaveRegDo_mux[6]_i_2_n_0 ;
wire \slaveRegDo_mux[6]_i_3_n_0 ;
wire \slaveRegDo_mux[7]_i_2_n_0 ;
wire \slaveRegDo_mux[7]_i_3_n_0 ;
wire \slaveRegDo_mux[8]_i_2_n_0 ;
wire \slaveRegDo_mux[8]_i_3_n_0 ;
wire \slaveRegDo_mux[9]_i_2_n_0 ;
wire \slaveRegDo_mux[9]_i_3_n_0 ;
wire [15:0]slaveRegDo_mux_0;
wire \slaveRegDo_mux_0[15]_i_1_n_0 ;
wire \slaveRegDo_mux_0[15]_i_9_n_0 ;
wire \slaveRegDo_mux_0[3]_i_9_n_0 ;
wire \slaveRegDo_mux_0[4]_i_12_n_0 ;
wire \slaveRegDo_mux_0[4]_i_3_n_0 ;
wire \slaveRegDo_mux_0[4]_i_5_n_0 ;
wire \slaveRegDo_mux_0[4]_i_8_n_0 ;
wire [4:0]slaveRegDo_mux_1;
wire \slaveRegDo_mux_1[0]_i_1_n_0 ;
wire \slaveRegDo_mux_1[1]_i_1_n_0 ;
wire \slaveRegDo_mux_1[2]_i_1_n_0 ;
wire \slaveRegDo_mux_1[3]_i_1_n_0 ;
wire \slaveRegDo_mux_1[4]_i_1_n_0 ;
wire [15:0]slaveRegDo_mux_2;
wire \slaveRegDo_mux_2[0]_i_2_n_0 ;
wire \slaveRegDo_mux_2[0]_i_3_n_0 ;
wire \slaveRegDo_mux_2[0]_i_5_n_0 ;
wire \slaveRegDo_mux_2[15]_i_1_n_0 ;
wire \slaveRegDo_mux_2[15]_i_3_n_0 ;
wire \slaveRegDo_mux_2[15]_i_4_n_0 ;
wire \slaveRegDo_mux_2[2]_i_3_n_0 ;
wire \slaveRegDo_mux_2[4]_i_3_n_0 ;
wire \slaveRegDo_mux_2[4]_i_4_n_0 ;
wire \slaveRegDo_mux_2[4]_i_5_n_0 ;
wire \slaveRegDo_mux_2[4]_i_6_n_0 ;
wire [15:0]slaveRegDo_mux_3;
wire \slaveRegDo_mux_3[11]_i_3_n_0 ;
wire \slaveRegDo_mux_3[12]_i_2_n_0 ;
wire \slaveRegDo_mux_3[15]_i_3_n_0 ;
wire \slaveRegDo_mux_3[15]_i_4_n_0 ;
wire \slaveRegDo_mux_3[6]_i_2_n_0 ;
wire \slaveRegDo_mux_3[7]_i_3_n_0 ;
wire [15:0]slaveRegDo_mux_4;
wire [15:0]slaveRegDo_mux_5;
wire \slaveRegDo_mux_6[15]_i_2_n_0 ;
wire \slaveRegDo_mux_6[15]_i_4_n_0 ;
wire \slaveRegDo_mux_6_reg_n_0_[0] ;
wire \slaveRegDo_mux_6_reg_n_0_[10] ;
wire \slaveRegDo_mux_6_reg_n_0_[11] ;
wire \slaveRegDo_mux_6_reg_n_0_[12] ;
wire \slaveRegDo_mux_6_reg_n_0_[13] ;
wire \slaveRegDo_mux_6_reg_n_0_[14] ;
wire \slaveRegDo_mux_6_reg_n_0_[15] ;
wire \slaveRegDo_mux_6_reg_n_0_[1] ;
wire \slaveRegDo_mux_6_reg_n_0_[2] ;
wire \slaveRegDo_mux_6_reg_n_0_[3] ;
wire \slaveRegDo_mux_6_reg_n_0_[4] ;
wire \slaveRegDo_mux_6_reg_n_0_[5] ;
wire \slaveRegDo_mux_6_reg_n_0_[6] ;
wire \slaveRegDo_mux_6_reg_n_0_[7] ;
wire \slaveRegDo_mux_6_reg_n_0_[8] ;
wire \slaveRegDo_mux_6_reg_n_0_[9] ;
wire \slaveRegDo_mux_reg_n_0_[0] ;
wire \slaveRegDo_mux_reg_n_0_[10] ;
wire \slaveRegDo_mux_reg_n_0_[11] ;
wire \slaveRegDo_mux_reg_n_0_[12] ;
wire \slaveRegDo_mux_reg_n_0_[13] ;
wire \slaveRegDo_mux_reg_n_0_[14] ;
wire \slaveRegDo_mux_reg_n_0_[15] ;
wire \slaveRegDo_mux_reg_n_0_[1] ;
wire \slaveRegDo_mux_reg_n_0_[2] ;
wire \slaveRegDo_mux_reg_n_0_[3] ;
wire \slaveRegDo_mux_reg_n_0_[4] ;
wire \slaveRegDo_mux_reg_n_0_[5] ;
wire \slaveRegDo_mux_reg_n_0_[6] ;
wire \slaveRegDo_mux_reg_n_0_[7] ;
wire \slaveRegDo_mux_reg_n_0_[8] ;
wire \slaveRegDo_mux_reg_n_0_[9] ;
wire [15:15]slaveRegDo_qualStrgConfig;
wire [15:0]\slaveRegDo_tcConfig[5120]_10 ;
wire [15:0]\slaveRegDo_tcConfig[5121]_11 ;
wire [15:0]\slaveRegDo_tcConfig[5122]_12 ;
wire [15:0]\slaveRegDo_tcConfig[5124]_14 ;
wire [15:0]\slaveRegDo_tcConfig[5125]_15 ;
wire [15:0]\slaveRegDo_tcConfig[5126]_16 ;
wire [15:0]\slaveRegDo_tcConfig[5128]_18 ;
wire [15:0]\slaveRegDo_tcConfig[5129]_19 ;
wire [15:0]\slaveRegDo_tcConfig[5130]_20 ;
wire [15:0]\slaveRegDo_tcConfig[5132]_22 ;
wire [15:0]\slaveRegDo_tcConfig[5133]_23 ;
wire [15:0]\slaveRegDo_tcConfig[5134]_24 ;
wire [15:0]\slaveRegDo_tcConfig[5136]_26 ;
wire [15:0]\slaveRegDo_tcConfig[5137]_27 ;
wire [15:0]\slaveRegDo_tcConfig[5138]_28 ;
wire [15:0]\slaveRegDo_tcConfig[5140]_30 ;
wire [15:0]\slaveRegDo_tcConfig[5141]_31 ;
wire [15:0]\slaveRegDo_tcConfig[5142]_32 ;
wire [15:0]\slaveRegDo_tcConfig[5144]_34 ;
wire [15:0]\slaveRegDo_tcConfig[5145]_35 ;
wire [15:0]\slaveRegDo_tcConfig[5146]_36 ;
wire [15:0]\slaveRegDo_tcConfig[5148]_38 ;
wire [15:0]\slaveRegDo_tcConfig[5149]_39 ;
wire [15:0]\slaveRegDo_tcConfig[5150]_40 ;
wire [31:0]tc_config_cs_serial_input;
wire [31:0]tc_config_cs_serial_output;
wire [31:0]tc_config_cs_shift_en;
wire toggle_rd;
wire toggle_rd_reg;
wire toggle_reg;
wire [0:0]toggle_reg_0;
wire use_probe_debug_circuit_1;
wire wcnt_hcmp_temp;
wire wcnt_lcmp_temp;
wire xsdb_rden_ff7;
wire xsdb_rden_ff9;
wire xsdb_rden_ffa;
wire [15:0]NLW_reg_890_dout_o_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized0 \ADV_TRIG_STREAM.reg_stream_ffc
(.\BRAM_DATA_reg[15] (D),
.D({s_daddr_o[12],s_daddr_o[9:0]}),
.E(s_den_o),
.\FSM_BRAM_ADDR_O_reg[3] (bram_en_i_3_n_0),
.\FSM_BRAM_ADDR_O_reg[9] (bram_en_i_2_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[10] (\G_1PIPE_IFACE.s_daddr_r_reg[10] ),
.\I_EN_CTL_EQ1.temp_en_reg_0 (\I_EN_CTL_EQ1.temp_en_reg ),
.Q({config_fsm_addr[16:13],config_fsm_addr[0]}),
.bram_en(bram_en),
.config_fsm_we(config_fsm_we),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_3_reg[0] (\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ),
.toggle_reg(toggle_reg),
.toggle_reg_0(toggle_reg_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream \ADV_TRIG_STREAM_READBACK.reg_stream_ffb
(.\CFG_DATA_O_reg[15] (\CFG_DATA_O_reg[15] ),
.D(s_daddr_o[3:0]),
.E(adv_rb_drdy1),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\slaveRegDo_mux_3[15]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_3[15]_i_4_n_0 ),
.Q({\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_11 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_12 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_13 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_14 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_15 }),
.\parallel_dout_reg[10] (reg_srl_fff_n_14),
.\parallel_dout_reg[12] (reg_srl_fff_n_13),
.\parallel_dout_reg[13] (reg_srl_fff_n_12),
.\parallel_dout_reg[14] (reg_srl_fff_n_11),
.\parallel_dout_reg[15] (reg_srl_fff_n_10),
.\parallel_dout_reg[6] (reg_srl_fff_n_15),
.s_dclk_o(s_dclk_o),
.\slaveRegDo_ff8_reg[12] (\slaveRegDo_mux_3[12]_i_2_n_0 ),
.\slaveRegDo_ff8_reg[12]_0 (\slaveRegDo_ff8_reg_n_0_[12] ),
.\slaveRegDo_ff8_reg[7] (\slaveRegDo_ff8_reg_n_0_[7] ),
.slaveRegDo_ff9(slaveRegDo_ff9),
.\slaveRegDo_ff9_reg[8] (\slaveRegDo_mux_3[6]_i_2_n_0 ),
.slaveRegDo_ffa(slaveRegDo_ffa),
.\slaveRegDo_mux_3_reg[0] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_6 ),
.\slaveRegDo_mux_3_reg[10] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_2 ),
.\slaveRegDo_mux_3_reg[12] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_0 ),
.\slaveRegDo_mux_3_reg[13] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_10 ),
.\slaveRegDo_mux_3_reg[14] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_3 ),
.\slaveRegDo_mux_3_reg[15] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_4 ),
.\slaveRegDo_mux_3_reg[1] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_7 ),
.\slaveRegDo_mux_3_reg[2] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_8 ),
.\slaveRegDo_mux_3_reg[3] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_5 ),
.\slaveRegDo_mux_3_reg[6] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_1 ),
.\slaveRegDo_mux_3_reg[8] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_9 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized41 \CNT.CNT_SRL[0].cnt_srl_reg
(.CFG_CNT_DIN(CFG_CNT_DIN[0]),
.CFG_CNT_DOUT(CFG_CNT_DOUT[0]),
.E(cnt_config_cs_shift_en[0]),
.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_cntConfig[6144]_42 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized42 \CNT.CNT_SRL[1].cnt_srl_reg
(.CFG_CNT_DIN(CFG_CNT_DIN[1]),
.CFG_CNT_DOUT(CFG_CNT_DOUT[1]),
.E(cnt_config_cs_shift_en[1]),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_den_r_reg (s_den_o),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\count0_reg[6] (\CNT.CNT_SRL[1].cnt_srl_reg_n_0 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[1:0]}),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_cntConfig[6145]_43 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized43 \CNT.CNT_SRL[2].cnt_srl_reg
(.CFG_CNT_DIN(CFG_CNT_DIN[2]),
.CFG_CNT_DOUT(CFG_CNT_DOUT[2]),
.D(s_daddr_o[12:10]),
.E(cnt_config_cs_shift_en[2]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_cntConfig[6146]_44 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized44 \CNT.CNT_SRL[3].cnt_srl_reg
(.CFG_CNT_DIN(CFG_CNT_DIN[3]),
.CFG_CNT_DOUT(CFG_CNT_DOUT[3]),
.D(\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
.E(cnt_config_cs_shift_en[3]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_6[15]_i_4_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\slaveRegDo_mux_6[15]_i_2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.Q(slaveRegDo_qualStrgConfig),
.\parallel_dout_reg[15]_0 (\slaveRegDo_cntConfig[6146]_44 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_cntConfig[6144]_42 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[1:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_do_o(\slaveRegDo_cntConfig[6145]_43 ),
.s_dwe_o(s_dwe_o),
.\shadow_reg[15]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\slaveRegDo_mux_6_reg[0] (\CNT.CNT_SRL[3].cnt_srl_reg_n_15 ),
.\slaveRegDo_mux_6_reg[10] (\CNT.CNT_SRL[3].cnt_srl_reg_n_5 ),
.\slaveRegDo_mux_6_reg[11] (\CNT.CNT_SRL[3].cnt_srl_reg_n_4 ),
.\slaveRegDo_mux_6_reg[12] (\CNT.CNT_SRL[3].cnt_srl_reg_n_3 ),
.\slaveRegDo_mux_6_reg[13] (\CNT.CNT_SRL[3].cnt_srl_reg_n_2 ),
.\slaveRegDo_mux_6_reg[14] (\CNT.CNT_SRL[3].cnt_srl_reg_n_1 ),
.\slaveRegDo_mux_6_reg[1] (\CNT.CNT_SRL[3].cnt_srl_reg_n_14 ),
.\slaveRegDo_mux_6_reg[2] (\CNT.CNT_SRL[3].cnt_srl_reg_n_13 ),
.\slaveRegDo_mux_6_reg[3] (\CNT.CNT_SRL[3].cnt_srl_reg_n_12 ),
.\slaveRegDo_mux_6_reg[4] (\CNT.CNT_SRL[3].cnt_srl_reg_n_11 ),
.\slaveRegDo_mux_6_reg[5] (\CNT.CNT_SRL[3].cnt_srl_reg_n_10 ),
.\slaveRegDo_mux_6_reg[6] (\CNT.CNT_SRL[3].cnt_srl_reg_n_9 ),
.\slaveRegDo_mux_6_reg[7] (\CNT.CNT_SRL[3].cnt_srl_reg_n_8 ),
.\slaveRegDo_mux_6_reg[8] (\CNT.CNT_SRL[3].cnt_srl_reg_n_7 ),
.\slaveRegDo_mux_6_reg[9] (\CNT.CNT_SRL[3].cnt_srl_reg_n_6 ));
FDRE \FSM_BRAM_ADDR_O_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[0]),
.Q(config_fsm_addr[0]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[10]),
.Q(config_fsm_addr[10]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[11]),
.Q(config_fsm_addr[11]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[12]),
.Q(config_fsm_addr[12]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr[13]),
.Q(config_fsm_addr[13]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr[14]),
.Q(config_fsm_addr[14]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr[15]),
.Q(config_fsm_addr[15]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[16]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr[16]),
.Q(config_fsm_addr[16]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[1]),
.Q(config_fsm_addr[1]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[2]),
.Q(config_fsm_addr[2]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[3]),
.Q(config_fsm_addr[3]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[4]),
.Q(config_fsm_addr[4]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[5]),
.Q(config_fsm_addr[5]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[6]),
.Q(config_fsm_addr[6]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[7]),
.Q(config_fsm_addr[7]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[8]),
.Q(config_fsm_addr[8]),
.R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_daddr_o[9]),
.Q(config_fsm_addr[9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair197" *)
LUT4 #(
.INIT(16'h4000))
FSM_BRAM_EN_RB_O_i_1
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(FSM_BRAM_EN_RB_O_i_2_n_0),
.O(reg_ce));
LUT6 #(
.INIT(64'h0000000004000000))
FSM_BRAM_EN_RB_O_i_2
(.I0(FSM_BRAM_EN_RB_O_i_3_n_0),
.I1(s_daddr_o[7]),
.I2(s_daddr_o[12]),
.I3(s_daddr_o[11]),
.I4(s_daddr_o[3]),
.I5(reg_stream_ffd_n_2),
.O(FSM_BRAM_EN_RB_O_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair187" *)
LUT3 #(
.INIT(8'h7F))
FSM_BRAM_EN_RB_O_i_3
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[6]),
.I2(s_daddr_o[5]),
.O(FSM_BRAM_EN_RB_O_i_3_n_0));
FDRE FSM_BRAM_EN_RB_O_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_ce),
.Q(config_fsm_en_rb),
.R(1'b0));
FDRE FSM_BRAM_WE_O_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(s_dwe_o),
.Q(config_fsm_we),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s \MU_SRL[0].mu_srl_reg
(.E(mu_config_cs_shift_en[0]),
.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[0]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[0]),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4096]_0 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized5 \MU_SRL[10].mu_srl_reg
(.E(mu_config_cs_shift_en[6]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[6]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[6]),
.s_daddr_o(s_daddr_o[12:10]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4106]_6 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized6 \MU_SRL[11].mu_srl_reg
(.E(mu_config_cs_shift_en[7]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\MU_SRL[15].mu_srl_reg_n_15 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (\MU_SRL[15].mu_srl_reg_n_14 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (\MU_SRL[15].mu_srl_reg_n_13 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_10 (\MU_SRL[15].mu_srl_reg_n_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_11 (\MU_SRL[15].mu_srl_reg_n_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_12 (\MU_SRL[15].mu_srl_reg_n_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_13 (\MU_SRL[15].mu_srl_reg_n_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_14 (\MU_SRL[15].mu_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 (\MU_SRL[15].mu_srl_reg_n_12 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 (\MU_SRL[15].mu_srl_reg_n_11 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 (\MU_SRL[15].mu_srl_reg_n_10 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 (\MU_SRL[15].mu_srl_reg_n_9 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 (\MU_SRL[15].mu_srl_reg_n_8 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 (\MU_SRL[15].mu_srl_reg_n_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_8 (\MU_SRL[15].mu_srl_reg_n_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_9 (\MU_SRL[15].mu_srl_reg_n_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.Q(\slaveRegDo_muConfig[4105]_5 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[7]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[7]),
.\parallel_dout_reg[0]_0 (\MU_SRL[3].mu_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\MU_SRL[3].mu_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\MU_SRL[3].mu_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\MU_SRL[3].mu_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\MU_SRL[3].mu_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\MU_SRL[3].mu_srl_reg_n_1 ),
.\parallel_dout_reg[15]_0 (\MU_SRL[3].mu_srl_reg_n_0 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_muConfig[4104]_4 ),
.\parallel_dout_reg[1]_0 (\MU_SRL[3].mu_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\MU_SRL[3].mu_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\MU_SRL[3].mu_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\MU_SRL[3].mu_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\MU_SRL[3].mu_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\MU_SRL[3].mu_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\MU_SRL[3].mu_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\MU_SRL[3].mu_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\MU_SRL[3].mu_srl_reg_n_6 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[3:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4106]_6 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_4_reg[0] (\MU_SRL[11].mu_srl_reg_n_15 ),
.\slaveRegDo_mux_4_reg[10] (\MU_SRL[11].mu_srl_reg_n_5 ),
.\slaveRegDo_mux_4_reg[11] (\MU_SRL[11].mu_srl_reg_n_4 ),
.\slaveRegDo_mux_4_reg[12] (\MU_SRL[11].mu_srl_reg_n_3 ),
.\slaveRegDo_mux_4_reg[13] (\MU_SRL[11].mu_srl_reg_n_2 ),
.\slaveRegDo_mux_4_reg[14] (\MU_SRL[11].mu_srl_reg_n_1 ),
.\slaveRegDo_mux_4_reg[15] (\MU_SRL[11].mu_srl_reg_n_0 ),
.\slaveRegDo_mux_4_reg[1] (\MU_SRL[11].mu_srl_reg_n_14 ),
.\slaveRegDo_mux_4_reg[2] (\MU_SRL[11].mu_srl_reg_n_13 ),
.\slaveRegDo_mux_4_reg[3] (\MU_SRL[11].mu_srl_reg_n_12 ),
.\slaveRegDo_mux_4_reg[4] (\MU_SRL[11].mu_srl_reg_n_11 ),
.\slaveRegDo_mux_4_reg[5] (\MU_SRL[11].mu_srl_reg_n_10 ),
.\slaveRegDo_mux_4_reg[6] (\MU_SRL[11].mu_srl_reg_n_9 ),
.\slaveRegDo_mux_4_reg[7] (\MU_SRL[11].mu_srl_reg_n_8 ),
.\slaveRegDo_mux_4_reg[8] (\MU_SRL[11].mu_srl_reg_n_7 ),
.\slaveRegDo_mux_4_reg[9] (\MU_SRL[11].mu_srl_reg_n_6 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized7 \MU_SRL[14].mu_srl_reg
(.E(mu_config_cs_shift_en[8]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[8]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[8]),
.s_daddr_o(s_daddr_o[12:10]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4110]_8 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized8 \MU_SRL[15].mu_srl_reg
(.E(mu_config_cs_shift_en[9]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[9]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[9]),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[3:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4110]_8 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_4_reg[0] (\MU_SRL[15].mu_srl_reg_n_0 ),
.\slaveRegDo_mux_4_reg[10] (\MU_SRL[15].mu_srl_reg_n_10 ),
.\slaveRegDo_mux_4_reg[11] (\MU_SRL[15].mu_srl_reg_n_11 ),
.\slaveRegDo_mux_4_reg[12] (\MU_SRL[15].mu_srl_reg_n_12 ),
.\slaveRegDo_mux_4_reg[13] (\MU_SRL[15].mu_srl_reg_n_13 ),
.\slaveRegDo_mux_4_reg[14] (\MU_SRL[15].mu_srl_reg_n_14 ),
.\slaveRegDo_mux_4_reg[15] (\MU_SRL[15].mu_srl_reg_n_15 ),
.\slaveRegDo_mux_4_reg[1] (\MU_SRL[15].mu_srl_reg_n_1 ),
.\slaveRegDo_mux_4_reg[2] (\MU_SRL[15].mu_srl_reg_n_2 ),
.\slaveRegDo_mux_4_reg[3] (\MU_SRL[15].mu_srl_reg_n_3 ),
.\slaveRegDo_mux_4_reg[4] (\MU_SRL[15].mu_srl_reg_n_4 ),
.\slaveRegDo_mux_4_reg[5] (\MU_SRL[15].mu_srl_reg_n_5 ),
.\slaveRegDo_mux_4_reg[6] (\MU_SRL[15].mu_srl_reg_n_6 ),
.\slaveRegDo_mux_4_reg[7] (\MU_SRL[15].mu_srl_reg_n_7 ),
.\slaveRegDo_mux_4_reg[8] (\MU_SRL[15].mu_srl_reg_n_8 ),
.\slaveRegDo_mux_4_reg[9] (\MU_SRL[15].mu_srl_reg_n_9 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized0 \MU_SRL[1].mu_srl_reg
(.E(mu_config_cs_shift_en[1]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\CNT.CNT_SRL[1].cnt_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[1]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[1]),
.s_daddr_o(s_daddr_o[12:10]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4097]_1 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized1 \MU_SRL[2].mu_srl_reg
(.E(mu_config_cs_shift_en[2]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[2]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[2]),
.s_daddr_o(s_daddr_o[12:10]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4098]_2 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized2 \MU_SRL[3].mu_srl_reg
(.E(mu_config_cs_shift_en[3]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[3]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[3]),
.\parallel_dout_reg[15]_0 (\slaveRegDo_muConfig[4097]_1 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_muConfig[4096]_0 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[1:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4098]_2 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_4_reg[0] (\MU_SRL[3].mu_srl_reg_n_15 ),
.\slaveRegDo_mux_4_reg[10] (\MU_SRL[3].mu_srl_reg_n_5 ),
.\slaveRegDo_mux_4_reg[11] (\MU_SRL[3].mu_srl_reg_n_4 ),
.\slaveRegDo_mux_4_reg[12] (\MU_SRL[3].mu_srl_reg_n_3 ),
.\slaveRegDo_mux_4_reg[13] (\MU_SRL[3].mu_srl_reg_n_2 ),
.\slaveRegDo_mux_4_reg[14] (\MU_SRL[3].mu_srl_reg_n_1 ),
.\slaveRegDo_mux_4_reg[15] (\MU_SRL[3].mu_srl_reg_n_0 ),
.\slaveRegDo_mux_4_reg[1] (\MU_SRL[3].mu_srl_reg_n_14 ),
.\slaveRegDo_mux_4_reg[2] (\MU_SRL[3].mu_srl_reg_n_13 ),
.\slaveRegDo_mux_4_reg[3] (\MU_SRL[3].mu_srl_reg_n_12 ),
.\slaveRegDo_mux_4_reg[4] (\MU_SRL[3].mu_srl_reg_n_11 ),
.\slaveRegDo_mux_4_reg[5] (\MU_SRL[3].mu_srl_reg_n_10 ),
.\slaveRegDo_mux_4_reg[6] (\MU_SRL[3].mu_srl_reg_n_9 ),
.\slaveRegDo_mux_4_reg[7] (\MU_SRL[3].mu_srl_reg_n_8 ),
.\slaveRegDo_mux_4_reg[8] (\MU_SRL[3].mu_srl_reg_n_7 ),
.\slaveRegDo_mux_4_reg[9] (\MU_SRL[3].mu_srl_reg_n_6 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized3 \MU_SRL[8].mu_srl_reg
(.E(mu_config_cs_shift_en[4]),
.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[4]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[4]),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4104]_4 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized4 \MU_SRL[9].mu_srl_reg
(.E(mu_config_cs_shift_en[5]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\CNT.CNT_SRL[1].cnt_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[5]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[5]),
.s_daddr_o(s_daddr_o[12:10]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_muConfig[4105]_5 ),
.s_dwe_o(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized45 \STRG_QUAL.qual_strg_srl_reg
(.D({\STRG_QUAL.qual_strg_srl_reg_n_1 ,\STRG_QUAL.qual_strg_srl_reg_n_2 ,\STRG_QUAL.qual_strg_srl_reg_n_3 ,\STRG_QUAL.qual_strg_srl_reg_n_4 ,\STRG_QUAL.qual_strg_srl_reg_n_5 ,\STRG_QUAL.qual_strg_srl_reg_n_6 ,\STRG_QUAL.qual_strg_srl_reg_n_7 ,\STRG_QUAL.qual_strg_srl_reg_n_8 ,\STRG_QUAL.qual_strg_srl_reg_n_9 ,\STRG_QUAL.qual_strg_srl_reg_n_10 ,\STRG_QUAL.qual_strg_srl_reg_n_11 ,\STRG_QUAL.qual_strg_srl_reg_n_12 ,\STRG_QUAL.qual_strg_srl_reg_n_13 ,\STRG_QUAL.qual_strg_srl_reg_n_14 ,\STRG_QUAL.qual_strg_srl_reg_n_15 }),
.E(\parallel_dout_reg[0] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_6[15]_i_4_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\slaveRegDo_mux_6[15]_i_2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.Q(slaveRegDo_qualStrgConfig),
.\parallel_dout_reg[0]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_1 ),
.\parallel_dout_reg[1]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\CNT.CNT_SRL[3].cnt_srl_reg_n_6 ),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_dwe_o(s_dwe_o),
.shift_en_reg_0(shift_en_reg_1));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized9 \TC_SRL[0].tc_srl_reg
(.E(tc_config_cs_shift_en[0]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5120]_10 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[0]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized19 \TC_SRL[10].tc_srl_reg
(.E(tc_config_cs_shift_en[10]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5130]_20 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[10]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[10]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized20 \TC_SRL[11].tc_srl_reg
(.E(tc_config_cs_shift_en[11]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.Q(\slaveRegDo_tcConfig[5129]_19 ),
.\parallel_dout_reg[0]_0 (\TC_SRL[15].tc_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\TC_SRL[15].tc_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\TC_SRL[15].tc_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\TC_SRL[15].tc_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\TC_SRL[15].tc_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\TC_SRL[15].tc_srl_reg_n_1 ),
.\parallel_dout_reg[15]_0 (\TC_SRL[15].tc_srl_reg_n_0 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5128]_18 ),
.\parallel_dout_reg[1]_0 (\TC_SRL[15].tc_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\TC_SRL[15].tc_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\TC_SRL[15].tc_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\TC_SRL[15].tc_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\TC_SRL[15].tc_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\TC_SRL[15].tc_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\TC_SRL[15].tc_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\TC_SRL[15].tc_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\TC_SRL[15].tc_srl_reg_n_6 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[2:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5130]_20 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[11].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[11].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[11].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[11].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[11].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[11].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[11].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[11].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[11].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[11].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[11].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[11].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[11].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[11].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[11].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[11].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[11]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[11]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized21 \TC_SRL[12].tc_srl_reg
(.E(tc_config_cs_shift_en[12]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5132]_22 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[12]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[12]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized22 \TC_SRL[13].tc_srl_reg
(.E(tc_config_cs_shift_en[13]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5133]_23 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[13]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[13]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized23 \TC_SRL[14].tc_srl_reg
(.E(tc_config_cs_shift_en[14]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5134]_24 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[14]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[14]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized24 \TC_SRL[15].tc_srl_reg
(.E(tc_config_cs_shift_en[15]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_3 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[15]_0 (\slaveRegDo_tcConfig[5133]_23 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5132]_22 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[1:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5134]_24 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[15].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[15].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[15].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[15].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[15].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[15].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[15].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[15].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[15].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[15].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[15].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[15].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[15].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[15].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[15].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[15].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[15]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[15]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized25 \TC_SRL[16].tc_srl_reg
(.E(tc_config_cs_shift_en[16]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5136]_26 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[16]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[16]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized26 \TC_SRL[17].tc_srl_reg
(.E(tc_config_cs_shift_en[17]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5137]_27 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[17]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[17]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized27 \TC_SRL[18].tc_srl_reg
(.E(tc_config_cs_shift_en[18]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5138]_28 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[18]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[18]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized28 \TC_SRL[19].tc_srl_reg
(.E(tc_config_cs_shift_en[19]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[0]_0 (\TC_SRL[23].tc_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\TC_SRL[23].tc_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\TC_SRL[23].tc_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\TC_SRL[23].tc_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\TC_SRL[23].tc_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\TC_SRL[23].tc_srl_reg_n_1 ),
.\parallel_dout_reg[15]_0 (\TC_SRL[23].tc_srl_reg_n_0 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5137]_27 ),
.\parallel_dout_reg[15]_2 (\slaveRegDo_tcConfig[5136]_26 ),
.\parallel_dout_reg[1]_0 (\TC_SRL[23].tc_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\TC_SRL[23].tc_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\TC_SRL[23].tc_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\TC_SRL[23].tc_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\TC_SRL[23].tc_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\TC_SRL[23].tc_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\TC_SRL[23].tc_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\TC_SRL[23].tc_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\TC_SRL[23].tc_srl_reg_n_6 ),
.s_daddr_o(s_daddr_o[5:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5138]_28 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[19].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[19].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[19].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[19].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[19].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[19].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[19].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[19].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[19].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[19].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[19].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[19].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[19].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[19].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[19].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[19].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[19]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[19]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized10 \TC_SRL[1].tc_srl_reg
(.E(tc_config_cs_shift_en[1]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5121]_11 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[1]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[1]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized29 \TC_SRL[20].tc_srl_reg
(.E(tc_config_cs_shift_en[20]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5140]_30 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[20]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[20]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized30 \TC_SRL[21].tc_srl_reg
(.E(tc_config_cs_shift_en[21]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5141]_31 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[21]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[21]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized31 \TC_SRL[22].tc_srl_reg
(.E(tc_config_cs_shift_en[22]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5142]_32 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[22]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[22]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized32 \TC_SRL[23].tc_srl_reg
(.E(tc_config_cs_shift_en[23]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[15]_0 (\slaveRegDo_tcConfig[5141]_31 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5140]_30 ),
.s_daddr_o(s_daddr_o[5:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5142]_32 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[23].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[23].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[23].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[23].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[23].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[23].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[23].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[23].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[23].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[23].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[23].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[23].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[23].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[23].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[23].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[23].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[23]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[23]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized33 \TC_SRL[24].tc_srl_reg
(.E(tc_config_cs_shift_en[24]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5144]_34 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[24]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[24]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized34 \TC_SRL[25].tc_srl_reg
(.E(tc_config_cs_shift_en[25]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5145]_35 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[25]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[25]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized35 \TC_SRL[26].tc_srl_reg
(.E(tc_config_cs_shift_en[26]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5146]_36 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[26]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[26]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized36 \TC_SRL[27].tc_srl_reg
(.D({\TC_SRL[27].tc_srl_reg_n_0 ,\TC_SRL[27].tc_srl_reg_n_1 ,\TC_SRL[27].tc_srl_reg_n_2 ,\TC_SRL[27].tc_srl_reg_n_3 ,\TC_SRL[27].tc_srl_reg_n_4 ,\TC_SRL[27].tc_srl_reg_n_5 ,\TC_SRL[27].tc_srl_reg_n_6 ,\TC_SRL[27].tc_srl_reg_n_7 ,\TC_SRL[27].tc_srl_reg_n_8 ,\TC_SRL[27].tc_srl_reg_n_9 ,\TC_SRL[27].tc_srl_reg_n_10 ,\TC_SRL[27].tc_srl_reg_n_11 ,\TC_SRL[27].tc_srl_reg_n_12 ,\TC_SRL[27].tc_srl_reg_n_13 ,\TC_SRL[27].tc_srl_reg_n_14 ,\TC_SRL[27].tc_srl_reg_n_15 }),
.E(tc_config_cs_shift_en[27]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\TC_SRL[19].tc_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\TC_SRL[11].tc_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (\TC_SRL[3].tc_srl_reg_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_10 (\TC_SRL[3].tc_srl_reg_n_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_11 (\TC_SRL[19].tc_srl_reg_n_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_12 (\TC_SRL[11].tc_srl_reg_n_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_13 (\TC_SRL[3].tc_srl_reg_n_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_14 (\TC_SRL[19].tc_srl_reg_n_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_15 (\TC_SRL[11].tc_srl_reg_n_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_16 (\TC_SRL[3].tc_srl_reg_n_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_17 (\TC_SRL[19].tc_srl_reg_n_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_18 (\TC_SRL[11].tc_srl_reg_n_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_19 (\TC_SRL[3].tc_srl_reg_n_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_2 (\TC_SRL[19].tc_srl_reg_n_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_20 (\TC_SRL[19].tc_srl_reg_n_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_21 (\TC_SRL[11].tc_srl_reg_n_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_22 (\TC_SRL[3].tc_srl_reg_n_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_23 (\TC_SRL[19].tc_srl_reg_n_8 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_24 (\TC_SRL[11].tc_srl_reg_n_8 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_25 (\TC_SRL[3].tc_srl_reg_n_8 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_26 (\TC_SRL[19].tc_srl_reg_n_9 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_27 (\TC_SRL[11].tc_srl_reg_n_9 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_28 (\TC_SRL[3].tc_srl_reg_n_9 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_29 (\TC_SRL[19].tc_srl_reg_n_10 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_3 (\TC_SRL[11].tc_srl_reg_n_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_30 (\TC_SRL[11].tc_srl_reg_n_10 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_31 (\TC_SRL[3].tc_srl_reg_n_10 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_32 (\TC_SRL[19].tc_srl_reg_n_11 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_33 (\TC_SRL[11].tc_srl_reg_n_11 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_34 (\TC_SRL[3].tc_srl_reg_n_11 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_35 (\TC_SRL[19].tc_srl_reg_n_12 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_36 (\TC_SRL[11].tc_srl_reg_n_12 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_37 (\TC_SRL[3].tc_srl_reg_n_12 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_38 (\TC_SRL[19].tc_srl_reg_n_13 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_39 (\TC_SRL[11].tc_srl_reg_n_13 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_4 (\TC_SRL[3].tc_srl_reg_n_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_40 (\TC_SRL[3].tc_srl_reg_n_13 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_41 (\TC_SRL[19].tc_srl_reg_n_14 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_42 (\TC_SRL[11].tc_srl_reg_n_14 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_43 (\TC_SRL[3].tc_srl_reg_n_14 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_44 (\TC_SRL[19].tc_srl_reg_n_15 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_45 (\TC_SRL[11].tc_srl_reg_n_15 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_46 (\TC_SRL[3].tc_srl_reg_n_15 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_5 (\TC_SRL[19].tc_srl_reg_n_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_6 (\TC_SRL[11].tc_srl_reg_n_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_7 (\TC_SRL[3].tc_srl_reg_n_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_8 (\TC_SRL[19].tc_srl_reg_n_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_9 (\TC_SRL[11].tc_srl_reg_n_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[0]_0 (\TC_SRL[31].tc_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\TC_SRL[31].tc_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\TC_SRL[31].tc_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\TC_SRL[31].tc_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\TC_SRL[31].tc_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\TC_SRL[31].tc_srl_reg_n_1 ),
.\parallel_dout_reg[15]_0 (\TC_SRL[31].tc_srl_reg_n_0 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5145]_35 ),
.\parallel_dout_reg[15]_2 (\slaveRegDo_tcConfig[5144]_34 ),
.\parallel_dout_reg[1]_0 (\TC_SRL[31].tc_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\TC_SRL[31].tc_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\TC_SRL[31].tc_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\TC_SRL[31].tc_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\TC_SRL[31].tc_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\TC_SRL[31].tc_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\TC_SRL[31].tc_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\TC_SRL[31].tc_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\TC_SRL[31].tc_srl_reg_n_6 ),
.s_daddr_o(s_daddr_o[5:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5146]_36 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[27]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[27]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized37 \TC_SRL[28].tc_srl_reg
(.E(tc_config_cs_shift_en[28]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5148]_38 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[28]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[28]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized38 \TC_SRL[29].tc_srl_reg
(.E(tc_config_cs_shift_en[29]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5149]_39 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[29]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[29]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized11 \TC_SRL[2].tc_srl_reg
(.E(tc_config_cs_shift_en[2]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5122]_12 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[2]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[2]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized39 \TC_SRL[30].tc_srl_reg
(.E(tc_config_cs_shift_en[30]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5150]_40 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[30]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[30]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized40 \TC_SRL[31].tc_srl_reg
(.E(tc_config_cs_shift_en[31]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[15]_0 (\slaveRegDo_tcConfig[5149]_39 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5148]_38 ),
.s_daddr_o(s_daddr_o[5:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5150]_40 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[31].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[31].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[31].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[31].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[31].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[31].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[31].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[31].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[31].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[31].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[31].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[31].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[31].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[31].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[31].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[31].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[31]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[31]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized12 \TC_SRL[3].tc_srl_reg
(.E(tc_config_cs_shift_en[3]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_1 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[0]_0 (\TC_SRL[7].tc_srl_reg_n_15 ),
.\parallel_dout_reg[10]_0 (\TC_SRL[7].tc_srl_reg_n_5 ),
.\parallel_dout_reg[11]_0 (\TC_SRL[7].tc_srl_reg_n_4 ),
.\parallel_dout_reg[12]_0 (\TC_SRL[7].tc_srl_reg_n_3 ),
.\parallel_dout_reg[13]_0 (\TC_SRL[7].tc_srl_reg_n_2 ),
.\parallel_dout_reg[14]_0 (\TC_SRL[7].tc_srl_reg_n_1 ),
.\parallel_dout_reg[15]_0 (\TC_SRL[7].tc_srl_reg_n_0 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5121]_11 ),
.\parallel_dout_reg[15]_2 (\slaveRegDo_tcConfig[5120]_10 ),
.\parallel_dout_reg[1]_0 (\TC_SRL[7].tc_srl_reg_n_14 ),
.\parallel_dout_reg[2]_0 (\TC_SRL[7].tc_srl_reg_n_13 ),
.\parallel_dout_reg[3]_0 (\TC_SRL[7].tc_srl_reg_n_12 ),
.\parallel_dout_reg[4]_0 (\TC_SRL[7].tc_srl_reg_n_11 ),
.\parallel_dout_reg[5]_0 (\TC_SRL[7].tc_srl_reg_n_10 ),
.\parallel_dout_reg[6]_0 (\TC_SRL[7].tc_srl_reg_n_9 ),
.\parallel_dout_reg[7]_0 (\TC_SRL[7].tc_srl_reg_n_8 ),
.\parallel_dout_reg[8]_0 (\TC_SRL[7].tc_srl_reg_n_7 ),
.\parallel_dout_reg[9]_0 (\TC_SRL[7].tc_srl_reg_n_6 ),
.s_daddr_o({s_daddr_o[12:10],s_daddr_o[2:0]}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5122]_12 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[3].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[3].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[3].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[3].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[3].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[3].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[3].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[3].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[3].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[3].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[3].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[3].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[3].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[3].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[3].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[3].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[3]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[3]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized13 \TC_SRL[4].tc_srl_reg
(.E(tc_config_cs_shift_en[4]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5124]_14 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[4]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[4]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized14 \TC_SRL[5].tc_srl_reg
(.E(tc_config_cs_shift_en[5]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5125]_15 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[5]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[5]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized15 \TC_SRL[6].tc_srl_reg
(.E(tc_config_cs_shift_en[6]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5126]_16 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[6]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[6]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized16 \TC_SRL[7].tc_srl_reg
(.E(tc_config_cs_shift_en[7]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.\parallel_dout_reg[15]_0 (\slaveRegDo_tcConfig[5125]_15 ),
.\parallel_dout_reg[15]_1 (\slaveRegDo_tcConfig[5124]_14 ),
.s_daddr_o(s_daddr_o[5:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5126]_16 ),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_5_reg[0] (\TC_SRL[7].tc_srl_reg_n_15 ),
.\slaveRegDo_mux_5_reg[10] (\TC_SRL[7].tc_srl_reg_n_5 ),
.\slaveRegDo_mux_5_reg[11] (\TC_SRL[7].tc_srl_reg_n_4 ),
.\slaveRegDo_mux_5_reg[12] (\TC_SRL[7].tc_srl_reg_n_3 ),
.\slaveRegDo_mux_5_reg[13] (\TC_SRL[7].tc_srl_reg_n_2 ),
.\slaveRegDo_mux_5_reg[14] (\TC_SRL[7].tc_srl_reg_n_1 ),
.\slaveRegDo_mux_5_reg[15] (\TC_SRL[7].tc_srl_reg_n_0 ),
.\slaveRegDo_mux_5_reg[1] (\TC_SRL[7].tc_srl_reg_n_14 ),
.\slaveRegDo_mux_5_reg[2] (\TC_SRL[7].tc_srl_reg_n_13 ),
.\slaveRegDo_mux_5_reg[3] (\TC_SRL[7].tc_srl_reg_n_12 ),
.\slaveRegDo_mux_5_reg[4] (\TC_SRL[7].tc_srl_reg_n_11 ),
.\slaveRegDo_mux_5_reg[5] (\TC_SRL[7].tc_srl_reg_n_10 ),
.\slaveRegDo_mux_5_reg[6] (\TC_SRL[7].tc_srl_reg_n_9 ),
.\slaveRegDo_mux_5_reg[7] (\TC_SRL[7].tc_srl_reg_n_8 ),
.\slaveRegDo_mux_5_reg[8] (\TC_SRL[7].tc_srl_reg_n_7 ),
.\slaveRegDo_mux_5_reg[9] (\TC_SRL[7].tc_srl_reg_n_6 ),
.tc_config_cs_serial_input(tc_config_cs_serial_input[7]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[7]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized17 \TC_SRL[8].tc_srl_reg
(.E(tc_config_cs_shift_en[8]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5128]_18 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[8]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[8]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized18 \TC_SRL[9].tc_srl_reg
(.E(tc_config_cs_shift_en[9]),
.\G_1PIPE_IFACE.s_daddr_r_reg[12] (\G_1PIPE_IFACE.s_daddr_r_reg[12]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.s_daddr_o(s_daddr_o[5:2]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di[14:0]),
.s_do_o(\slaveRegDo_tcConfig[5129]_19 ),
.s_dwe_o(s_dwe_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[9]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[9]));
(* C_BUILD_REVISION = "0" *)
(* C_CORE_INFO1 = "0" *)
(* C_CORE_INFO2 = "0" *)
(* C_CORE_MAJOR_VER = "6" *)
(* C_CORE_MINOR_VER = "2" *)
(* C_CORE_TYPE = "1" *)
(* C_CSE_DRV_VER = "2" *)
(* C_MAJOR_VERSION = "2016" *)
(* C_MINOR_VERSION = "4" *)
(* C_NEXT_SLAVE = "0" *)
(* C_PIPE_IFACE = "1" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* C_XSDB_SLAVE_TYPE = "17" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE
(.s_daddr_o({s_daddr,s_daddr_o}),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_do_i({\slaveRegDo_mux_reg_n_0_[15] ,\slaveRegDo_mux_reg_n_0_[14] ,\slaveRegDo_mux_reg_n_0_[13] ,\slaveRegDo_mux_reg_n_0_[12] ,\slaveRegDo_mux_reg_n_0_[11] ,\slaveRegDo_mux_reg_n_0_[10] ,\slaveRegDo_mux_reg_n_0_[9] ,\slaveRegDo_mux_reg_n_0_[8] ,\slaveRegDo_mux_reg_n_0_[7] ,\slaveRegDo_mux_reg_n_0_[6] ,\slaveRegDo_mux_reg_n_0_[5] ,\slaveRegDo_mux_reg_n_0_[4] ,\slaveRegDo_mux_reg_n_0_[3] ,\slaveRegDo_mux_reg_n_0_[2] ,\slaveRegDo_mux_reg_n_0_[1] ,\slaveRegDo_mux_reg_n_0_[0] }),
.s_drdy_i(regDrdy_reg_n_0),
.s_dwe_o(s_dwe_o),
.s_rst_o(s_rst_o),
.sl_iport_i(SL_IPORT_I),
.sl_oport_o(SL_OPORT_O));
FDRE adv_drdy_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\G_1PIPE_IFACE.s_den_r_reg ),
.Q(adv_drdy),
.R(1'b0));
FDRE adv_rb_drdy1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(adv_rb_drdy),
.Q(adv_rb_drdy1),
.R(1'b0));
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/u_ila_regs/adv_rb_drdy3_reg_srl2 " *)
SRL16E adv_rb_drdy3_reg_srl2
(.A0(1'b1),
.A1(1'b0),
.A2(1'b0),
.A3(1'b0),
.CE(1'b1),
.CLK(s_dclk_o),
.D(adv_rb_drdy1),
.Q(adv_rb_drdy3_reg_srl2_n_0));
FDRE adv_rb_drdy4_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(adv_rb_drdy3_reg_srl2_n_0),
.Q(adv_rb_drdy4),
.R(1'b0));
FDRE adv_rb_drdy_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(drdy_mux_ff1),
.Q(adv_rb_drdy),
.R(1'b0));
LUT6 #(
.INIT(64'h0000800000000000))
bram_en_i_2
(.I0(config_fsm_addr[9]),
.I1(config_fsm_addr[10]),
.I2(config_fsm_addr[7]),
.I3(config_fsm_addr[8]),
.I4(config_fsm_addr[12]),
.I5(config_fsm_addr[11]),
.O(bram_en_i_2_n_0));
LUT6 #(
.INIT(64'h0080000000000000))
bram_en_i_3
(.I0(config_fsm_addr[3]),
.I1(config_fsm_addr[4]),
.I2(config_fsm_addr[2]),
.I3(config_fsm_addr[1]),
.I4(config_fsm_addr[6]),
.I5(config_fsm_addr[5]),
.O(bram_en_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair191" *)
LUT4 #(
.INIT(16'h8000))
bram_rd_en_i_1
(.I0(bram_rd_en_i_2_n_0),
.I1(bram_rd_en_i_3_n_0),
.I2(config_fsm_en_rb),
.I3(bram_rd_en_i_4_n_0),
.O(bram_rd_en));
LUT6 #(
.INIT(64'h8000000000000000))
bram_rd_en_i_2
(.I0(config_fsm_addr[8]),
.I1(config_fsm_addr[9]),
.I2(config_fsm_addr[6]),
.I3(config_fsm_addr[7]),
.I4(config_fsm_addr[11]),
.I5(config_fsm_addr[10]),
.O(bram_rd_en_i_2_n_0));
LUT6 #(
.INIT(64'h2000000000000000))
bram_rd_en_i_3
(.I0(config_fsm_addr[3]),
.I1(config_fsm_addr[2]),
.I2(config_fsm_addr[0]),
.I3(config_fsm_addr[1]),
.I4(config_fsm_addr[5]),
.I5(config_fsm_addr[4]),
.O(bram_rd_en_i_3_n_0));
LUT6 #(
.INIT(64'h0000000000000001))
bram_rd_en_i_4
(.I0(config_fsm_addr[14]),
.I1(config_fsm_addr[15]),
.I2(config_fsm_addr[12]),
.I3(config_fsm_addr[13]),
.I4(config_fsm_we),
.I5(config_fsm_addr[16]),
.O(bram_rd_en_i_4_n_0));
LUT1 #(
.INIT(2'h1))
\count0[0]_i_1
(.I0(count0_reg__0[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair198" *)
LUT2 #(
.INIT(4'h6))
\count0[1]_i_1
(.I0(count0_reg__0[0]),
.I1(count0_reg__0[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair194" *)
LUT3 #(
.INIT(8'h6A))
\count0[2]_i_1
(.I0(count0_reg__0[2]),
.I1(count0_reg__0[1]),
.I2(count0_reg__0[0]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair198" *)
LUT4 #(
.INIT(16'h6AAA))
\count0[3]_i_1
(.I0(count0_reg__0[3]),
.I1(count0_reg__0[0]),
.I2(count0_reg__0[1]),
.I3(count0_reg__0[2]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair189" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\count0[4]_i_1
(.I0(count0_reg__0[4]),
.I1(count0_reg__0[2]),
.I2(count0_reg__0[1]),
.I3(count0_reg__0[0]),
.I4(count0_reg__0[3]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\count0[5]_i_1
(.I0(count0_reg__0[5]),
.I1(count0_reg__0[3]),
.I2(count0_reg__0[0]),
.I3(count0_reg__0[1]),
.I4(count0_reg__0[2]),
.I5(count0_reg__0[4]),
.O(p_0_in__0[5]));
LUT2 #(
.INIT(4'hE))
\count0[6]_i_1
(.I0(count0_reg__0[6]),
.I1(s_rst_o),
.O(count00));
(* SOFT_HLUTNM = "soft_lutpair203" *)
LUT3 #(
.INIT(8'h6A))
\count0[6]_i_2
(.I0(count0_reg__0[6]),
.I1(\count0[6]_i_3_n_0 ),
.I2(count0_reg__0[5]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair189" *)
LUT5 #(
.INIT(32'h80000000))
\count0[6]_i_3
(.I0(count0_reg__0[4]),
.I1(count0_reg__0[2]),
.I2(count0_reg__0[1]),
.I3(count0_reg__0[0]),
.I4(count0_reg__0[3]),
.O(\count0[6]_i_3_n_0 ));
FDRE \count0_reg[0]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[0]),
.Q(count0_reg__0[0]),
.R(count00));
FDRE \count0_reg[1]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[1]),
.Q(count0_reg__0[1]),
.R(count00));
FDRE \count0_reg[2]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[2]),
.Q(count0_reg__0[2]),
.R(count00));
FDRE \count0_reg[3]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[3]),
.Q(count0_reg__0[3]),
.R(count00));
FDRE \count0_reg[4]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[4]),
.Q(count0_reg__0[4]),
.R(count00));
FDRE \count0_reg[5]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[5]),
.Q(count0_reg__0[5]),
.R(count00));
FDRE \count0_reg[6]
(.C(s_dclk_o),
.CE(xsdb_rden_ff9),
.D(p_0_in__0[6]),
.Q(count0_reg__0[6]),
.R(count00));
LUT1 #(
.INIT(2'h1))
\count1[0]_i_1
(.I0(count1_reg__0[0]),
.O(p_0_in__1[0]));
(* SOFT_HLUTNM = "soft_lutpair206" *)
LUT2 #(
.INIT(4'h6))
\count1[1]_i_1
(.I0(count1_reg__0[0]),
.I1(count1_reg__0[1]),
.O(p_0_in__1[1]));
(* SOFT_HLUTNM = "soft_lutpair206" *)
LUT3 #(
.INIT(8'h6A))
\count1[2]_i_1
(.I0(count1_reg__0[2]),
.I1(count1_reg__0[1]),
.I2(count1_reg__0[0]),
.O(p_0_in__1[2]));
(* SOFT_HLUTNM = "soft_lutpair193" *)
LUT4 #(
.INIT(16'h6AAA))
\count1[3]_i_1
(.I0(count1_reg__0[3]),
.I1(count1_reg__0[0]),
.I2(count1_reg__0[1]),
.I3(count1_reg__0[2]),
.O(p_0_in__1[3]));
(* SOFT_HLUTNM = "soft_lutpair188" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\count1[4]_i_1
(.I0(count1_reg__0[4]),
.I1(count1_reg__0[2]),
.I2(count1_reg__0[1]),
.I3(count1_reg__0[0]),
.I4(count1_reg__0[3]),
.O(p_0_in__1[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\count1[5]_i_1
(.I0(count1_reg__0[5]),
.I1(count1_reg__0[3]),
.I2(count1_reg__0[0]),
.I3(count1_reg__0[1]),
.I4(count1_reg__0[2]),
.I5(count1_reg__0[4]),
.O(p_0_in__1[5]));
LUT2 #(
.INIT(4'hE))
\count1[6]_i_1
(.I0(s_rst_o),
.I1(count1_reg__0[6]),
.O(count10));
(* SOFT_HLUTNM = "soft_lutpair205" *)
LUT3 #(
.INIT(8'h6A))
\count1[6]_i_2
(.I0(count1_reg__0[6]),
.I1(count1_reg__0[5]),
.I2(\count1[6]_i_3_n_0 ),
.O(p_0_in__1[6]));
(* SOFT_HLUTNM = "soft_lutpair188" *)
LUT5 #(
.INIT(32'h80000000))
\count1[6]_i_3
(.I0(count1_reg__0[4]),
.I1(count1_reg__0[2]),
.I2(count1_reg__0[1]),
.I3(count1_reg__0[0]),
.I4(count1_reg__0[3]),
.O(\count1[6]_i_3_n_0 ));
FDRE \count1_reg[0]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[0]),
.Q(count1_reg__0[0]),
.R(count10));
FDRE \count1_reg[1]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[1]),
.Q(count1_reg__0[1]),
.R(count10));
FDRE \count1_reg[2]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[2]),
.Q(count1_reg__0[2]),
.R(count10));
FDRE \count1_reg[3]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[3]),
.Q(count1_reg__0[3]),
.R(count10));
FDRE \count1_reg[4]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[4]),
.Q(count1_reg__0[4]),
.R(count10));
FDRE \count1_reg[5]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[5]),
.Q(count1_reg__0[5]),
.R(count10));
FDRE \count1_reg[6]
(.C(s_dclk_o),
.CE(xsdb_rden_ffa),
.D(p_0_in__1[6]),
.Q(count1_reg__0[6]),
.R(count10));
FDSE count_tt_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(count_tt_reg_0),
.Q(count_tt),
.S(s_rst_o));
LUT6 #(
.INIT(64'h0000000004000000))
\current_state[4]_i_2
(.I0(reg_stream_ffd_n_2),
.I1(reg_stream_ffd_n_1),
.I2(s_daddr_o[12]),
.I3(reg_stream_ffd_n_0),
.I4(s_daddr_o[2]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.O(read_data_en));
LUT6 #(
.INIT(64'h00000000BABA000B))
\drdyCount[0]_i_1
(.I0(s_den_o),
.I1(drdyCount[0]),
.I2(drdyCount[4]),
.I3(drdyCount[5]),
.I4(\drdyCount[5]_i_5_n_0 ),
.I5(s_rst_o),
.O(\drdyCount[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\drdyCount[1]_i_1
(.I0(drdyCount[0]),
.I1(drdyCount[1]),
.O(\drdyCount[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair201" *)
LUT3 #(
.INIT(8'h6A))
\drdyCount[2]_i_1
(.I0(drdyCount[2]),
.I1(drdyCount[1]),
.I2(drdyCount[0]),
.O(\drdyCount[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair195" *)
LUT4 #(
.INIT(16'h6AAA))
\drdyCount[3]_i_1
(.I0(drdyCount[3]),
.I1(drdyCount[0]),
.I2(drdyCount[1]),
.I3(drdyCount[2]),
.O(\drdyCount[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00000000FF6A006A))
\drdyCount[4]_i_1
(.I0(drdyCount[4]),
.I1(\drdyCount[5]_i_2_n_0 ),
.I2(\drdyCount[5]_i_6_n_0 ),
.I3(s_den_o),
.I4(\drdyCount[4]_i_2_n_0 ),
.I5(drdyCount1),
.O(\drdyCount[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h1555555555555555))
\drdyCount[4]_i_2
(.I0(s_daddr_o[12]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[6]),
.I3(s_daddr_o[4]),
.I4(regDrdy_i_3_n_0),
.I5(\drdyCount[4]_i_3_n_0 ),
.O(\drdyCount[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8000000000000000))
\drdyCount[4]_i_3
(.I0(s_daddr_o[11]),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[10]),
.I3(s_daddr_o[8]),
.I4(s_daddr_o[9]),
.I5(s_daddr_o[7]),
.O(\drdyCount[4]_i_3_n_0 ));
LUT2 #(
.INIT(4'hE))
\drdyCount[5]_i_1
(.I0(s_den_o),
.I1(drdyCount1),
.O(\drdyCount[5]_i_1_n_0 ));
LUT4 #(
.INIT(16'hFFFD))
\drdyCount[5]_i_2
(.I0(\drdyCount[5]_i_5_n_0 ),
.I1(s_den_o),
.I2(drdyCount[0]),
.I3(drdyCount[4]),
.O(\drdyCount[5]_i_2_n_0 ));
LUT4 #(
.INIT(16'h1540))
\drdyCount[5]_i_3
(.I0(s_den_o),
.I1(drdyCount[4]),
.I2(\drdyCount[5]_i_6_n_0 ),
.I3(drdyCount[5]),
.O(\drdyCount[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFEFAFAFAFA))
\drdyCount[5]_i_4
(.I0(s_rst_o),
.I1(drdyCount[3]),
.I2(drdyCount[5]),
.I3(drdyCount[2]),
.I4(drdyCount[1]),
.I5(drdyCount[4]),
.O(drdyCount1));
(* SOFT_HLUTNM = "soft_lutpair201" *)
LUT4 #(
.INIT(16'h0001))
\drdyCount[5]_i_5
(.I0(drdyCount[3]),
.I1(drdyCount[5]),
.I2(drdyCount[2]),
.I3(drdyCount[1]),
.O(\drdyCount[5]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair195" *)
LUT4 #(
.INIT(16'h8000))
\drdyCount[5]_i_6
(.I0(drdyCount[3]),
.I1(drdyCount[0]),
.I2(drdyCount[1]),
.I3(drdyCount[2]),
.O(\drdyCount[5]_i_6_n_0 ));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\drdyCount[0]_i_1_n_0 ),
.Q(drdyCount[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[1]
(.C(s_dclk_o),
.CE(\drdyCount[5]_i_2_n_0 ),
.D(\drdyCount[1]_i_1_n_0 ),
.Q(drdyCount[1]),
.R(\drdyCount[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[2]
(.C(s_dclk_o),
.CE(\drdyCount[5]_i_2_n_0 ),
.D(\drdyCount[2]_i_1_n_0 ),
.Q(drdyCount[2]),
.R(\drdyCount[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[3]
(.C(s_dclk_o),
.CE(\drdyCount[5]_i_2_n_0 ),
.D(\drdyCount[3]_i_1_n_0 ),
.Q(drdyCount[3]),
.R(\drdyCount[5]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\drdyCount[4]_i_1_n_0 ),
.Q(drdyCount[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\drdyCount_reg[5]
(.C(s_dclk_o),
.CE(\drdyCount[5]_i_2_n_0 ),
.D(\drdyCount[5]_i_3_n_0 ),
.Q(drdyCount[5]),
.R(\drdyCount[5]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
drdy_ff7_i_1
(.I0(drdy_ff9_i_3_n_0),
.I1(drdy_ff7_i_2_n_0),
.I2(s_daddr_o[10]),
.I3(s_daddr_o[11]),
.I4(reg_83_n_1),
.I5(drdy_ff7_i_3_n_0),
.O(xsdb_rden_ff7));
(* SOFT_HLUTNM = "soft_lutpair208" *)
LUT2 #(
.INIT(4'h2))
drdy_ff7_i_2
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[3]),
.O(drdy_ff7_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair190" *)
LUT3 #(
.INIT(8'h7F))
drdy_ff7_i_3
(.I0(s_daddr_o[8]),
.I1(s_daddr_o[9]),
.I2(s_daddr_o[7]),
.O(drdy_ff7_i_3_n_0));
FDRE drdy_ff7_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(xsdb_rden_ff7),
.Q(drdy_ff7),
.R(s_rst_o));
LUT6 #(
.INIT(64'h0000000000000080))
drdy_ff8_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[11]),
.I2(drdy_ff9_i_3_n_0),
.I3(drdy_ff9_i_2_n_0),
.I4(s_daddr_o[2]),
.I5(drdy_ff8_i_2_n_0),
.O(slaveRegDo_ff8));
(* SOFT_HLUTNM = "soft_lutpair202" *)
LUT2 #(
.INIT(4'hE))
drdy_ff8_i_2
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[0]),
.O(drdy_ff8_i_2_n_0));
FDRE drdy_ff8_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_ff8),
.Q(drdy_ff8),
.R(s_rst_o));
LUT6 #(
.INIT(64'h0000400000000000))
drdy_ff9_i_1
(.I0(drdy_ff9_i_2_n_0),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[11]),
.I3(drdy_ff9_i_3_n_0),
.I4(s_daddr_o[2]),
.I5(\CNT.CNT_SRL[1].cnt_srl_reg_n_0 ),
.O(xsdb_rden_ff9));
(* SOFT_HLUTNM = "soft_lutpair192" *)
LUT4 #(
.INIT(16'h7FFF))
drdy_ff9_i_2
(.I0(s_daddr_o[7]),
.I1(s_daddr_o[9]),
.I2(s_daddr_o[8]),
.I3(s_daddr_o[10]),
.O(drdy_ff9_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair187" *)
LUT5 #(
.INIT(32'h00008000))
drdy_ff9_i_3
(.I0(s_daddr_o[5]),
.I1(s_daddr_o[6]),
.I2(s_daddr_o[4]),
.I3(s_den_o),
.I4(s_dwe_o),
.O(drdy_ff9_i_3_n_0));
FDRE drdy_ff9_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(xsdb_rden_ff9),
.Q(drdy_ff9),
.R(s_rst_o));
LUT6 #(
.INIT(64'h0000000000000080))
drdy_ffa_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[11]),
.I2(drdy_ff9_i_3_n_0),
.I3(s_daddr_o[2]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.I5(drdy_ff9_i_2_n_0),
.O(xsdb_rden_ffa));
FDRE drdy_ffa_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(xsdb_rden_ffa),
.Q(drdy_ffa),
.R(s_rst_o));
FDRE drdy_mux_ff1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(drdy_mux_ff),
.Q(drdy_mux_ff1),
.R(1'b0));
LUT6 #(
.INIT(64'h0001000000000000))
drdy_mux_ff_i_1
(.I0(drdyCount[1]),
.I1(drdyCount[2]),
.I2(drdyCount[5]),
.I3(drdyCount[3]),
.I4(drdyCount[4]),
.I5(drdyCount[0]),
.O(drdy_mux_temp));
FDRE drdy_mux_ff_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(drdy_mux_temp),
.Q(drdy_mux_ff),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE dummy_temp1_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(DUMMY_I),
.Q(dummy_temp1),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE dummy_temp_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(dummy_temp1),
.Q(dummy_temp),
.R(1'b0));
FDRE \regAck_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(regAck_temp),
.Q(regAck_reg),
.R(1'b0));
FDRE \regAck_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(regAck_temp_reg),
.Q(\regAck_reg_n_0_[1] ),
.R(1'b0));
FDRE \regAck_temp_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(s_den_o),
.Q(regAck_temp),
.R(1'b0));
FDRE \regAck_temp_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(E),
.Q(regAck_temp_reg),
.R(1'b0));
LUT6 #(
.INIT(64'hFF55AA00EF40EF40))
regDrdy_i_1
(.I0(regDrdy_reg_0),
.I1(drdy_ff7),
.I2(regDrdy_i_3_n_0),
.I3(drdy_mux_ff1),
.I4(regDrdy_reg_i_4_n_0),
.I5(s_daddr_o[3]),
.O(regDrdy_i_1_n_0));
LUT4 #(
.INIT(16'hFFBF))
regDrdy_i_2
(.I0(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ),
.I1(s_daddr_o[10]),
.I2(s_daddr_o[11]),
.I3(s_daddr_o[12]),
.O(regDrdy_reg_0));
(* SOFT_HLUTNM = "soft_lutpair197" *)
LUT3 #(
.INIT(8'h80))
regDrdy_i_3
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[2]),
.O(regDrdy_i_3_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
regDrdy_i_5
(.I0(adv_rb_drdy4),
.I1(drdy_ffa),
.I2(s_daddr_o[1]),
.I3(drdy_ff9),
.I4(s_daddr_o[0]),
.I5(drdy_ff8),
.O(regDrdy_i_5_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
regDrdy_i_6
(.I0(drdy_mux_ff1),
.I1(\regAck_reg_n_0_[1] ),
.I2(s_daddr_o[1]),
.I3(regAck_reg),
.I4(s_daddr_o[0]),
.I5(adv_drdy),
.O(regDrdy_i_6_n_0));
FDRE regDrdy_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(regDrdy_i_1_n_0),
.Q(regDrdy_reg_n_0),
.R(1'b0));
MUXF7 regDrdy_reg_i_4
(.I0(regDrdy_i_5_n_0),
.I1(regDrdy_i_6_n_0),
.O(regDrdy_reg_i_4_n_0),
.S(s_daddr_o[2]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized43 reg_15
(.D(p_0_in[2:1]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] ({\slaveRegDo_mux_1[2]_i_1_n_0 ,\slaveRegDo_mux_1[1]_i_1_n_0 }),
.\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (reg_19_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (drdy_ff7_i_2_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (reg_9_n_2),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (reg_9_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\slaveRegDo_mux_2[15]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (reg_7_n_4),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (reg_7_n_6),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 (reg_7_n_7),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 (reg_7_n_8),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 (reg_7_n_9),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 (reg_7_n_10),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 (reg_7_n_13),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 (reg_7_n_14),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (reg_83_n_15),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 (reg_83_n_16),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\slaveRegDo_mux_0[4]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\slaveRegDo_mux_0[4]_i_8_n_0 ),
.Q({reg_9_n_3,reg_9_n_4,reg_9_n_7,reg_9_n_8,reg_9_n_9,reg_9_n_10,reg_9_n_11}),
.SR(SR),
.read_reset_addr({read_reset_addr[14:5],read_reset_addr[2:1]}),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[10] (reg_15_n_12),
.\slaveRegDo_mux_0_reg[11] (reg_15_n_1),
.\slaveRegDo_mux_0_reg[12] (reg_15_n_0),
.\slaveRegDo_mux_0_reg[13] (reg_15_n_13),
.\slaveRegDo_mux_0_reg[14] (reg_15_n_14),
.\slaveRegDo_mux_0_reg[15] (reg_15_n_15),
.\slaveRegDo_mux_0_reg[3] (reg_15_n_17),
.\slaveRegDo_mux_0_reg[4] (reg_15_n_16),
.\slaveRegDo_mux_0_reg[5] (reg_15_n_2),
.\slaveRegDo_mux_0_reg[6] (reg_15_n_8),
.\slaveRegDo_mux_0_reg[7] (reg_15_n_9),
.\slaveRegDo_mux_0_reg[8] (reg_15_n_10),
.\slaveRegDo_mux_0_reg[9] (reg_15_n_11),
.use_probe_debug_circuit_1(use_probe_debug_circuit_1),
.\xsdb_reg_reg[0] (reg_15_n_5),
.\xsdb_reg_reg[0]_0 (reg_15_n_6),
.\xsdb_reg_reg[10] (reg_18_n_6),
.\xsdb_reg_reg[10]_0 (reg_17_n_8),
.\xsdb_reg_reg[11] (reg_17_n_7),
.\xsdb_reg_reg[12] (reg_17_n_6),
.\xsdb_reg_reg[13] (reg_18_n_5),
.\xsdb_reg_reg[13]_0 (reg_17_n_5),
.\xsdb_reg_reg[14] (reg_18_n_0),
.\xsdb_reg_reg[14]_0 (reg_17_n_4),
.\xsdb_reg_reg[1] (reg_18_n_12),
.\xsdb_reg_reg[1]_0 (reg_6_n_14),
.\xsdb_reg_reg[1]_1 (reg_17_n_15),
.\xsdb_reg_reg[2] (reg_18_n_11),
.\xsdb_reg_reg[2]_0 (reg_17_n_14),
.\xsdb_reg_reg[5] (reg_17_n_13),
.\xsdb_reg_reg[6] (reg_18_n_10),
.\xsdb_reg_reg[6]_0 (reg_17_n_12),
.\xsdb_reg_reg[7] (reg_18_n_9),
.\xsdb_reg_reg[7]_0 (reg_17_n_11),
.\xsdb_reg_reg[8] (reg_18_n_8),
.\xsdb_reg_reg[8]_0 (reg_17_n_10),
.\xsdb_reg_reg[9] (reg_18_n_7),
.\xsdb_reg_reg[9]_0 (reg_17_n_9));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized44 reg_16
(.\G_1PIPE_IFACE.s_daddr_r_reg[9] (reg_15_n_5),
.read_reset_addr(read_reset_addr),
.s_daddr_o(s_daddr_o[6:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[15] (reg_16_n_1),
.\xsdb_reg_reg[15] (reg_16_n_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized45 reg_17
(.D(p_0_in[0]),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_8_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_1[0]_i_1_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (reg_7_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (reg_83_n_17),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\slaveRegDo_mux_0[4]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\slaveRegDo_mux_0[4]_i_8_n_0 ),
.SR(SR),
.read_reset_addr({read_reset_addr[4:3],read_reset_addr[0]}),
.s_daddr_o(s_daddr_o[6:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[10] (reg_17_n_8),
.\slaveRegDo_mux_0_reg[11] (reg_17_n_7),
.\slaveRegDo_mux_0_reg[12] (reg_17_n_6),
.\slaveRegDo_mux_0_reg[13] (reg_17_n_5),
.\slaveRegDo_mux_0_reg[14] (reg_17_n_4),
.\slaveRegDo_mux_0_reg[15] (reg_17_n_1),
.\slaveRegDo_mux_0_reg[1] (reg_17_n_15),
.\slaveRegDo_mux_0_reg[2] (reg_17_n_14),
.\slaveRegDo_mux_0_reg[3] (reg_17_n_3),
.\slaveRegDo_mux_0_reg[4] (reg_17_n_2),
.\slaveRegDo_mux_0_reg[5] (reg_17_n_13),
.\slaveRegDo_mux_0_reg[6] (reg_17_n_12),
.\slaveRegDo_mux_0_reg[7] (reg_17_n_11),
.\slaveRegDo_mux_0_reg[8] (reg_17_n_10),
.\slaveRegDo_mux_0_reg[9] (reg_17_n_9),
.\xsdb_reg_reg[0] (reg_1a_n_4),
.\xsdb_reg_reg[15] (reg_16_n_1),
.\xsdb_reg_reg[15]_0 (reg_15_n_15),
.\xsdb_reg_reg[3] (reg_15_n_17),
.\xsdb_reg_reg[4] (reg_15_n_16));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized46 reg_18
(.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_19_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (reg_6_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\slaveRegDo_mux_0[3]_i_9_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (reg_7_n_12),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (reg_7_n_11),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_8_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.Q({reg_9_n_5,reg_9_n_6,reg_9_n_12}),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.s_daddr_o({s_daddr_o[6:3],s_daddr_o[1:0]}),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.\slaveRegDo_mux_0_reg[10] (reg_18_n_6),
.\slaveRegDo_mux_0_reg[11] (reg_18_n_14),
.\slaveRegDo_mux_0_reg[12] (reg_18_n_13),
.\slaveRegDo_mux_0_reg[13] (reg_18_n_5),
.\slaveRegDo_mux_0_reg[14] (reg_18_n_0),
.\slaveRegDo_mux_0_reg[15] ({slaveRegDo_18[15],slaveRegDo_18[4:3],slaveRegDo_18[0]}),
.\slaveRegDo_mux_0_reg[1] (reg_18_n_12),
.\slaveRegDo_mux_0_reg[2] (reg_18_n_11),
.\slaveRegDo_mux_0_reg[5] (reg_18_n_15),
.\slaveRegDo_mux_0_reg[6] (reg_18_n_10),
.\slaveRegDo_mux_0_reg[7] (reg_18_n_9),
.\slaveRegDo_mux_0_reg[8] (reg_18_n_8),
.\slaveRegDo_mux_0_reg[9] (reg_18_n_7),
.\xsdb_reg_reg[10] (reg_19_n_7),
.\xsdb_reg_reg[10]_0 (reg_1a_n_9),
.\xsdb_reg_reg[11] (reg_15_n_1),
.\xsdb_reg_reg[11]_0 (reg_19_n_6),
.\xsdb_reg_reg[11]_1 (reg_1a_n_8),
.\xsdb_reg_reg[12] (reg_15_n_0),
.\xsdb_reg_reg[12]_0 (reg_19_n_5),
.\xsdb_reg_reg[12]_1 (reg_1a_n_7),
.\xsdb_reg_reg[13] (reg_19_n_4),
.\xsdb_reg_reg[13]_0 (reg_1a_n_6),
.\xsdb_reg_reg[14] (reg_19_n_3),
.\xsdb_reg_reg[14]_0 (reg_1a_n_5),
.\xsdb_reg_reg[1] (reg_19_n_16),
.\xsdb_reg_reg[2] (reg_19_n_15),
.\xsdb_reg_reg[5] (reg_15_n_2),
.\xsdb_reg_reg[5]_0 (reg_19_n_12),
.\xsdb_reg_reg[5]_1 (reg_1a_n_14),
.\xsdb_reg_reg[6] (reg_19_n_11),
.\xsdb_reg_reg[6]_0 (reg_1a_n_13),
.\xsdb_reg_reg[7] (reg_19_n_10),
.\xsdb_reg_reg[7]_0 (reg_1a_n_12),
.\xsdb_reg_reg[8] (reg_19_n_9),
.\xsdb_reg_reg[8]_0 (reg_1a_n_11),
.\xsdb_reg_reg[9] (reg_19_n_8),
.\xsdb_reg_reg[9]_0 (reg_1a_n_10));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized47 reg_19
(.\G_1PIPE_IFACE.s_daddr_r_reg[9] (reg_15_n_5),
.s_daddr_o(s_daddr_o[6:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[0] (reg_19_n_17),
.\slaveRegDo_mux_0_reg[10] (reg_19_n_7),
.\slaveRegDo_mux_0_reg[11] (reg_19_n_6),
.\slaveRegDo_mux_0_reg[12] (reg_19_n_5),
.\slaveRegDo_mux_0_reg[13] (reg_19_n_4),
.\slaveRegDo_mux_0_reg[14] (reg_19_n_3),
.\slaveRegDo_mux_0_reg[15] (reg_19_n_2),
.\slaveRegDo_mux_0_reg[1] (reg_19_n_16),
.\slaveRegDo_mux_0_reg[2] (reg_19_n_15),
.\slaveRegDo_mux_0_reg[3] (reg_19_n_14),
.\slaveRegDo_mux_0_reg[4] (reg_19_n_13),
.\slaveRegDo_mux_0_reg[5] (reg_19_n_12),
.\slaveRegDo_mux_0_reg[6] (reg_19_n_11),
.\slaveRegDo_mux_0_reg[7] (reg_19_n_10),
.\slaveRegDo_mux_0_reg[8] (reg_19_n_9),
.\slaveRegDo_mux_0_reg[9] (reg_19_n_8),
.\xsdb_reg_reg[0] (reg_19_n_0),
.\xsdb_reg_reg[0]_0 (reg_19_n_1));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized48 reg_1a
(.D(p_0_in[4:3]),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] ({\slaveRegDo_mux_1[4]_i_1_n_0 ,\slaveRegDo_mux_1[3]_i_1_n_0 }),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_8_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (reg_9_n_1),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (reg_7_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (reg_16_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 (reg_83_n_14),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 (reg_83_n_13),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\slaveRegDo_mux_0[4]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\slaveRegDo_mux_0[4]_i_8_n_0 ),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.en_adv_trigger_1(en_adv_trigger_1),
.s_daddr_o(s_daddr_o[7:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.\slaveRegDo_mux_0_reg[0] (reg_1a_n_4),
.\slaveRegDo_mux_0_reg[10] (reg_1a_n_9),
.\slaveRegDo_mux_0_reg[11] (reg_1a_n_8),
.\slaveRegDo_mux_0_reg[12] (reg_1a_n_7),
.\slaveRegDo_mux_0_reg[13] (reg_1a_n_6),
.\slaveRegDo_mux_0_reg[14] (reg_1a_n_5),
.\slaveRegDo_mux_0_reg[15] (reg_1a_n_2),
.\slaveRegDo_mux_0_reg[5] (reg_1a_n_14),
.\slaveRegDo_mux_0_reg[6] (reg_1a_n_13),
.\slaveRegDo_mux_0_reg[7] (reg_1a_n_12),
.\slaveRegDo_mux_0_reg[8] (reg_1a_n_11),
.\slaveRegDo_mux_0_reg[9] (reg_1a_n_10),
.\xsdb_reg_reg[0] (reg_19_n_17),
.\xsdb_reg_reg[15] (reg_83_n_2),
.\xsdb_reg_reg[15]_0 (reg_17_n_1),
.\xsdb_reg_reg[15]_1 (reg_19_n_2),
.\xsdb_reg_reg[15]_2 ({slaveRegDo_18[15],slaveRegDo_18[4:3],slaveRegDo_18[0]}),
.\xsdb_reg_reg[3] (reg_17_n_3),
.\xsdb_reg_reg[3]_0 (reg_19_n_14),
.\xsdb_reg_reg[4] (reg_17_n_2),
.\xsdb_reg_reg[4]_0 (reg_19_n_13));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized28 reg_6
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.halt_ctrl(halt_ctrl),
.s_daddr_o({s_daddr_o[8:7],s_daddr_o[3:0]}),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.\slaveRegDo_mux_0_reg[15] ({slaveRegDo_6[15:6],slaveRegDo_6[3:2],slaveRegDo_6[0]}),
.\slaveRegDo_mux_0_reg[1] (reg_6_n_14),
.\slaveRegDo_mux_0_reg[4] (reg_6_n_15),
.\slaveRegDo_mux_0_reg[5] (reg_6_n_0),
.\xsdb_reg_reg[4] (reg_7_n_16),
.\xsdb_reg_reg[5] (reg_7_n_15));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized29 reg_7
(.DOUT_O(DOUT_O),
.\G_1PIPE_IFACE.s_daddr_r_reg[9] (reg_15_n_5),
.halt_ctrl(halt_ctrl),
.s_daddr_o(s_daddr_o[6:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.scnt_cmp_temp(scnt_cmp_temp),
.shift_en_reg(shift_en_reg),
.shift_en_reg_0(shift_en_reg_0),
.\slaveRegDo_mux_0_reg[0] (reg_7_n_2),
.\slaveRegDo_mux_0_reg[10] (reg_7_n_10),
.\slaveRegDo_mux_0_reg[11] (reg_7_n_11),
.\slaveRegDo_mux_0_reg[12] (reg_7_n_12),
.\slaveRegDo_mux_0_reg[13] (reg_7_n_13),
.\slaveRegDo_mux_0_reg[14] (reg_7_n_14),
.\slaveRegDo_mux_0_reg[15] (reg_7_n_0),
.\slaveRegDo_mux_0_reg[2] (reg_7_n_4),
.\slaveRegDo_mux_0_reg[3] (reg_7_n_5),
.\slaveRegDo_mux_0_reg[4] (reg_7_n_16),
.\slaveRegDo_mux_0_reg[5] (reg_7_n_15),
.\slaveRegDo_mux_0_reg[6] (reg_7_n_6),
.\slaveRegDo_mux_0_reg[7] (reg_7_n_7),
.\slaveRegDo_mux_0_reg[8] (reg_7_n_8),
.\slaveRegDo_mux_0_reg[9] (reg_7_n_9),
.u_scnt_cmp_q(arm_ctrl),
.wcnt_hcmp_temp(wcnt_hcmp_temp),
.wcnt_lcmp_temp(wcnt_lcmp_temp),
.\xsdb_reg_reg[0] (reg_7_n_1),
.\xsdb_reg_reg[15] ({slaveRegDo_6[15:6],slaveRegDo_6[3:2],slaveRegDo_6[0]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized30 reg_8
(.CAP_DONE_O_reg(CAP_DONE_O_reg),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\slaveRegDo_mux_0[3]_i_9_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (reg_7_n_2),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (reg_7_n_5),
.Q({reg_9_n_13,reg_9_n_14}),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_0_reg[0] (reg_8_n_0),
.\slaveRegDo_mux_0_reg[2] ({reg_8_n_2,reg_8_n_3}),
.\slaveRegDo_mux_0_reg[3] (reg_8_n_1));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized49 reg_80
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o[2:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.slaveRegDo_80(slaveRegDo_80));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized50 reg_81
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o[2:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.slaveRegDo_81(slaveRegDo_81));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized51 reg_82
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o[2:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.slaveRegDo_82(slaveRegDo_82));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized52 reg_83
(.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\slaveRegDo_mux_0[15]_i_9_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_8_n_0 ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.slaveRegDo_80(slaveRegDo_80),
.slaveRegDo_81(slaveRegDo_81),
.slaveRegDo_82(slaveRegDo_82),
.slaveRegDo_84(slaveRegDo_84),
.\slaveRegDo_mux_0_reg[0] (reg_83_n_17),
.\slaveRegDo_mux_0_reg[10] (reg_83_n_7),
.\slaveRegDo_mux_0_reg[11] (reg_83_n_6),
.\slaveRegDo_mux_0_reg[12] (reg_83_n_5),
.\slaveRegDo_mux_0_reg[13] (reg_83_n_4),
.\slaveRegDo_mux_0_reg[14] (reg_83_n_3),
.\slaveRegDo_mux_0_reg[15] (reg_83_n_2),
.\slaveRegDo_mux_0_reg[1] (reg_83_n_16),
.\slaveRegDo_mux_0_reg[2] (reg_83_n_15),
.\slaveRegDo_mux_0_reg[3] (reg_83_n_14),
.\slaveRegDo_mux_0_reg[4] (reg_83_n_13),
.\slaveRegDo_mux_0_reg[5] (reg_83_n_12),
.\slaveRegDo_mux_0_reg[6] (reg_83_n_11),
.\slaveRegDo_mux_0_reg[7] (reg_83_n_10),
.\slaveRegDo_mux_0_reg[8] (reg_83_n_9),
.\slaveRegDo_mux_0_reg[9] (reg_83_n_8),
.\xsdb_reg_reg[0] (reg_83_n_0),
.\xsdb_reg_reg[0]_0 (reg_83_n_1),
.\xsdb_reg_reg[0]_1 (reg_84_n_15),
.\xsdb_reg_reg[10] (reg_15_n_12),
.\xsdb_reg_reg[10]_0 (reg_85_n_5),
.\xsdb_reg_reg[11] (reg_18_n_14),
.\xsdb_reg_reg[11]_0 (reg_85_n_4),
.\xsdb_reg_reg[12] (reg_18_n_13),
.\xsdb_reg_reg[12]_0 (reg_85_n_3),
.\xsdb_reg_reg[13] (reg_15_n_13),
.\xsdb_reg_reg[13]_0 (reg_85_n_2),
.\xsdb_reg_reg[14] (reg_15_n_14),
.\xsdb_reg_reg[14]_0 (reg_85_n_1),
.\xsdb_reg_reg[15] (reg_85_n_0),
.\xsdb_reg_reg[1] (reg_84_n_14),
.\xsdb_reg_reg[2] (reg_84_n_13),
.\xsdb_reg_reg[3] (reg_84_n_12),
.\xsdb_reg_reg[4] (reg_84_n_0),
.\xsdb_reg_reg[5] (reg_18_n_15),
.\xsdb_reg_reg[5]_0 (reg_85_n_10),
.\xsdb_reg_reg[6] (reg_15_n_8),
.\xsdb_reg_reg[6]_0 (reg_85_n_9),
.\xsdb_reg_reg[7] (reg_15_n_9),
.\xsdb_reg_reg[7]_0 (reg_85_n_8),
.\xsdb_reg_reg[8] (reg_15_n_10),
.\xsdb_reg_reg[8]_0 (reg_85_n_7),
.\xsdb_reg_reg[9] (reg_15_n_11),
.\xsdb_reg_reg[9]_0 (reg_85_n_6));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized53 reg_84
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o[2:0]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.\slaveRegDo_mux_0_reg[0] (reg_84_n_15),
.\slaveRegDo_mux_0_reg[15] (slaveRegDo_84),
.\slaveRegDo_mux_0_reg[1] (reg_84_n_14),
.\slaveRegDo_mux_0_reg[2] (reg_84_n_13),
.\slaveRegDo_mux_0_reg[3] (reg_84_n_12),
.\slaveRegDo_mux_0_reg[4] (reg_84_n_0),
.\xsdb_reg_reg[0] (reg_85_n_15),
.\xsdb_reg_reg[1] (reg_85_n_14),
.\xsdb_reg_reg[2] (reg_85_n_13),
.\xsdb_reg_reg[3] (reg_85_n_12),
.\xsdb_reg_reg[4] (reg_85_n_11));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized54 reg_85
(.\G_1PIPE_IFACE.s_daddr_r_reg[10] (reg_83_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_15_n_6),
.s_daddr_o(s_daddr_o[6:4]),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di),
.\slaveRegDo_mux_0_reg[0] (reg_85_n_15),
.\slaveRegDo_mux_0_reg[10] (reg_85_n_5),
.\slaveRegDo_mux_0_reg[11] (reg_85_n_4),
.\slaveRegDo_mux_0_reg[12] (reg_85_n_3),
.\slaveRegDo_mux_0_reg[13] (reg_85_n_2),
.\slaveRegDo_mux_0_reg[14] (reg_85_n_1),
.\slaveRegDo_mux_0_reg[15] (reg_85_n_0),
.\slaveRegDo_mux_0_reg[1] (reg_85_n_14),
.\slaveRegDo_mux_0_reg[2] (reg_85_n_13),
.\slaveRegDo_mux_0_reg[3] (reg_85_n_12),
.\slaveRegDo_mux_0_reg[4] (reg_85_n_11),
.\slaveRegDo_mux_0_reg[5] (reg_85_n_10),
.\slaveRegDo_mux_0_reg[6] (reg_85_n_9),
.\slaveRegDo_mux_0_reg[7] (reg_85_n_8),
.\slaveRegDo_mux_0_reg[8] (reg_85_n_7),
.\slaveRegDo_mux_0_reg[9] (reg_85_n_6));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized56 reg_887
(.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\slaveRegDo_mux_0[4]_i_12_n_0 ),
.out(dummy_temp),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_do_o(slaveRegDo_890[3]),
.\slaveRegDo_mux_2_reg[3] (reg_887_n_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized58 reg_88d
(.D(reg_88d_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_1[0]_i_1_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\slaveRegDo_mux_2[0]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\slaveRegDo_mux_2[0]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\slaveRegDo_mux_2[0]_i_2_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\slaveRegDo_mux_2[4]_i_4_n_0 ),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.Q(reg_88d_n_1),
.s_daddr_o(s_daddr_o[1:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\xsdb_reg_reg[0] (reg_892_n_3),
.\xsdb_reg_reg[0]_0 (reg_88f_n_16));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized60 reg_88f
(.D({reg_88f_n_12,reg_88f_n_13,reg_88f_n_14,reg_88f_n_15}),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\slaveRegDo_mux_2[15]_i_4_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ({\slaveRegDo_mux_1[4]_i_1_n_0 ,\slaveRegDo_mux_1[3]_i_1_n_0 ,\slaveRegDo_mux_1[2]_i_1_n_0 ,\slaveRegDo_mux_1[1]_i_1_n_0 }),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (drdy_ff8_i_2_n_0),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\slaveRegDo_mux_2[2]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\slaveRegDo_mux_2[4]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\slaveRegDo_mux_2[15]_i_3_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\slaveRegDo_mux_0[4]_i_5_n_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\slaveRegDo_mux_2[4]_i_4_n_0 ),
.Q(reg_88d_n_1),
.SEQUENCER_STATE_O(SEQUENCER_STATE_O),
.en_adv_trigger(en_adv_trigger),
.s_daddr_o(s_daddr_o[4:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_do_o({slaveRegDo_890[15:4],slaveRegDo_890[1]}),
.\slaveRegDo_mux_2_reg[0] (reg_88f_n_16),
.\slaveRegDo_mux_2_reg[10] (reg_88f_n_5),
.\slaveRegDo_mux_2_reg[11] (reg_88f_n_6),
.\slaveRegDo_mux_2_reg[12] (reg_88f_n_7),
.\slaveRegDo_mux_2_reg[13] (reg_88f_n_8),
.\slaveRegDo_mux_2_reg[14] (reg_88f_n_9),
.\slaveRegDo_mux_2_reg[15] (reg_88f_n_10),
.\slaveRegDo_mux_2_reg[5] (reg_88f_n_0),
.\slaveRegDo_mux_2_reg[6] (reg_88f_n_1),
.\slaveRegDo_mux_2_reg[7] (reg_88f_n_2),
.\slaveRegDo_mux_2_reg[8] (reg_88f_n_3),
.\slaveRegDo_mux_2_reg[9] (reg_88f_n_4),
.\xsdb_reg_reg[15] (reg_88f_n_11),
.\xsdb_reg_reg[1] (reg_892_n_2),
.\xsdb_reg_reg[2] (reg_892_n_1),
.\xsdb_reg_reg[3] (reg_892_n_0),
.\xsdb_reg_reg[3]_0 (reg_887_n_0));
(* C_ADDR_W = "13" *)
(* C_CTLRST_VAL = "47'b00000000000000000000000000000000000000000000000" *)
(* C_DATA_W = "16" *)
(* C_EN_CTL = "0" *)
(* C_EN_STAT = "1" *)
(* C_REG_ADDR = "13'b0100010010000" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized61 reg_890
(.din_i({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.dout_o(NLW_reg_890_dout_o_UNCONNECTED[15:0]),
.rst_reg_i(1'b0),
.s_daddr_i(s_daddr_o),
.s_dclk_i(s_dclk_o),
.s_den_i(s_den_o),
.s_di_i(s_di),
.s_do_o(slaveRegDo_890),
.s_dwe_i(s_dwe_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized59 reg_892
(.\G_1PIPE_IFACE.s_den_r_reg (reg_88f_n_11),
.flag0_temp(flag0_temp),
.flag1_temp(flag1_temp),
.flag2_temp(flag2_temp),
.flag3_temp(flag3_temp),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_2_reg[0] (reg_892_n_3),
.\slaveRegDo_mux_2_reg[1] (reg_892_n_2),
.\slaveRegDo_mux_2_reg[2] (reg_892_n_1),
.\slaveRegDo_mux_2_reg[3] (reg_892_n_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized31 reg_9
(.Q({reg_9_n_3,reg_9_n_4,reg_9_n_5,reg_9_n_6,reg_9_n_7,reg_9_n_8,reg_9_n_9,reg_9_n_10,reg_9_n_11,reg_9_n_12,reg_9_n_13,reg_9_n_14}),
.\captured_samples_reg[14] (\captured_samples_reg[14] ),
.s_daddr_o(s_daddr_o[3:0]),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_0_reg[1] (reg_9_n_2),
.\slaveRegDo_mux_0_reg[2] (reg_9_n_0),
.\slaveRegDo_mux_0_reg[4] (reg_9_n_1),
.\xsdb_reg_reg[2] ({reg_8_n_2,reg_8_n_3}),
.\xsdb_reg_reg[4] (reg_6_n_15));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized46 reg_srl_fff
(.D(D),
.E(\parallel_dout_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (reg_83_n_1),
.\G_1PIPE_IFACE.s_di_r_reg[15] (\CNT.CNT_SRL[3].cnt_srl_reg_n_16 ),
.Q({\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_11 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_12 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_13 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_14 ,\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_15 }),
.capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
.debug_data_in(debug_data_in),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di[14:0]),
.s_dwe_o(s_dwe_o),
.shift_en_reg_0(shift_en_reg_2),
.\slaveRegDo_ff8_reg[12] (\slaveRegDo_mux_3[11]_i_3_n_0 ),
.\slaveRegDo_ff8_reg[7] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_6 ),
.\slaveRegDo_ff8_reg[7]_0 (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_8 ),
.\slaveRegDo_ff8_reg[7]_1 (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_7 ),
.\slaveRegDo_ff9_reg[8] (\slaveRegDo_mux_3[7]_i_3_n_0 ),
.\slaveRegDo_ffa_reg[15] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_5 ),
.\slaveRegDo_mux_3_reg[0] (reg_srl_fff_n_0),
.\slaveRegDo_mux_3_reg[10] (reg_srl_fff_n_14),
.\slaveRegDo_mux_3_reg[11] (reg_srl_fff_n_1),
.\slaveRegDo_mux_3_reg[12] (reg_srl_fff_n_13),
.\slaveRegDo_mux_3_reg[13] (reg_srl_fff_n_12),
.\slaveRegDo_mux_3_reg[14] (reg_srl_fff_n_11),
.\slaveRegDo_mux_3_reg[15] (reg_srl_fff_n_10),
.\slaveRegDo_mux_3_reg[1] (reg_srl_fff_n_9),
.\slaveRegDo_mux_3_reg[2] (reg_srl_fff_n_8),
.\slaveRegDo_mux_3_reg[3] (reg_srl_fff_n_7),
.\slaveRegDo_mux_3_reg[4] (reg_srl_fff_n_6),
.\slaveRegDo_mux_3_reg[5] (reg_srl_fff_n_5),
.\slaveRegDo_mux_3_reg[6] (reg_srl_fff_n_15),
.\slaveRegDo_mux_3_reg[7] (reg_srl_fff_n_4),
.\slaveRegDo_mux_3_reg[8] (reg_srl_fff_n_3),
.\slaveRegDo_mux_3_reg[9] (reg_srl_fff_n_2),
.\xsdb_reg_reg[10] (reg_stream_ffd_n_8),
.\xsdb_reg_reg[11] (reg_stream_ffd_n_7),
.\xsdb_reg_reg[12] (reg_stream_ffd_n_6),
.\xsdb_reg_reg[13] (reg_stream_ffd_n_5),
.\xsdb_reg_reg[14] (reg_stream_ffd_n_4),
.\xsdb_reg_reg[15] ({reg_stream_ffe_n_0,reg_stream_ffe_n_1,reg_stream_ffe_n_2,reg_stream_ffe_n_3,reg_stream_ffe_n_4,reg_stream_ffe_n_5,reg_stream_ffe_n_6,reg_stream_ffe_n_7,reg_stream_ffe_n_8,reg_stream_ffe_n_9,reg_stream_ffe_n_10,reg_stream_ffe_n_11,reg_stream_ffe_n_12,reg_stream_ffe_n_13,reg_stream_ffe_n_14,reg_stream_ffe_n_15}),
.\xsdb_reg_reg[15]_0 (reg_stream_ffd_n_3),
.\xsdb_reg_reg[2] (reg_stream_ffd_n_16),
.\xsdb_reg_reg[3] (reg_stream_ffd_n_15),
.\xsdb_reg_reg[4] (reg_stream_ffd_n_14),
.\xsdb_reg_reg[5] (reg_stream_ffd_n_13),
.\xsdb_reg_reg[6] (reg_stream_ffd_n_12),
.\xsdb_reg_reg[7] (reg_stream_ffd_n_11),
.\xsdb_reg_reg[8] (\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_9 ),
.\xsdb_reg_reg[8]_0 (reg_stream_ffd_n_10),
.\xsdb_reg_reg[9] (reg_stream_ffd_n_9));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized1 reg_stream_ffd
(.debug_data_in(debug_data_in),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_3_reg[10] (reg_stream_ffd_n_8),
.\slaveRegDo_mux_3_reg[11] (reg_stream_ffd_n_7),
.\slaveRegDo_mux_3_reg[12] (reg_stream_ffd_n_6),
.\slaveRegDo_mux_3_reg[13] (reg_stream_ffd_n_5),
.\slaveRegDo_mux_3_reg[14] (reg_stream_ffd_n_4),
.\slaveRegDo_mux_3_reg[15] (reg_stream_ffd_n_3),
.\slaveRegDo_mux_3_reg[2] (reg_stream_ffd_n_16),
.\slaveRegDo_mux_3_reg[3] (reg_stream_ffd_n_15),
.\slaveRegDo_mux_3_reg[4] (reg_stream_ffd_n_14),
.\slaveRegDo_mux_3_reg[5] (reg_stream_ffd_n_13),
.\slaveRegDo_mux_3_reg[6] (reg_stream_ffd_n_12),
.\slaveRegDo_mux_3_reg[7] (reg_stream_ffd_n_11),
.\slaveRegDo_mux_3_reg[8] (reg_stream_ffd_n_10),
.\slaveRegDo_mux_3_reg[9] (reg_stream_ffd_n_9),
.\xsdb_reg_reg[0] (reg_stream_ffd_n_0),
.\xsdb_reg_reg[0]_0 (reg_stream_ffd_n_1),
.\xsdb_reg_reg[0]_1 (reg_stream_ffd_n_2));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stream__parameterized2 reg_stream_ffe
(.E(E),
.Q({reg_stream_ffe_n_0,reg_stream_ffe_n_1,reg_stream_ffe_n_2,reg_stream_ffe_n_3,reg_stream_ffe_n_4,reg_stream_ffe_n_5,reg_stream_ffe_n_6,reg_stream_ffe_n_7,reg_stream_ffe_n_8,reg_stream_ffe_n_9,reg_stream_ffe_n_10,reg_stream_ffe_n_11,reg_stream_ffe_n_12,reg_stream_ffe_n_13,reg_stream_ffe_n_14,reg_stream_ffe_n_15}),
.\input_data_reg[31] (\input_data_reg[31] ),
.s_dclk_o(s_dclk_o));
(* SOFT_HLUTNM = "soft_lutpair203" *)
LUT3 #(
.INIT(8'h01))
\shift_reg0[8]_i_2
(.I0(count0_reg__0[4]),
.I1(count0_reg__0[3]),
.I2(count0_reg__0[6]),
.O(\shift_reg0_reg[8]_1 ));
(* SOFT_HLUTNM = "soft_lutpair194" *)
LUT4 #(
.INIT(16'hFFFE))
\shift_reg0[8]_i_3
(.I0(count0_reg__0[1]),
.I1(count0_reg__0[0]),
.I2(count0_reg__0[5]),
.I3(count0_reg__0[2]),
.O(\shift_reg0_reg[8]_0 ));
FDRE \shift_reg0_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shift_reg0_reg[8]_2 ),
.Q(\slaveRegDo_ff9_reg[8]_0 ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair205" *)
LUT3 #(
.INIT(8'h01))
\shift_reg1[15]_i_2
(.I0(count1_reg__0[5]),
.I1(count1_reg__0[4]),
.I2(count1_reg__0[6]),
.O(\shift_reg1_reg[15]_0 ));
(* SOFT_HLUTNM = "soft_lutpair193" *)
LUT4 #(
.INIT(16'hFFFE))
\shift_reg1[15]_i_3
(.I0(count1_reg__0[1]),
.I1(count1_reg__0[0]),
.I2(count1_reg__0[3]),
.I3(count1_reg__0[2]),
.O(\shift_reg1_reg[15]_1 ));
FDRE \shift_reg1_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shift_reg1_reg[15]_2 ),
.Q(\slaveRegDo_ffa_reg[15]_0 ),
.R(1'b0));
LUT3 #(
.INIT(8'h74))
\slaveRegDo_ff8[12]_i_1
(.I0(count_tt),
.I1(slaveRegDo_ff8),
.I2(\slaveRegDo_ff8_reg_n_0_[12] ),
.O(\slaveRegDo_ff8[12]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\slaveRegDo_ff8[7]_i_1
(.I0(count_tt),
.I1(slaveRegDo_ff8),
.I2(\slaveRegDo_ff8_reg_n_0_[7] ),
.O(\slaveRegDo_ff8[7]_i_1_n_0 ));
FDSE \slaveRegDo_ff8_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_ff8[12]_i_1_n_0 ),
.Q(\slaveRegDo_ff8_reg_n_0_[12] ),
.S(s_rst_o));
FDRE \slaveRegDo_ff8_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_ff8[7]_i_1_n_0 ),
.Q(\slaveRegDo_ff8_reg_n_0_[7] ),
.R(s_rst_o));
FDRE \slaveRegDo_ff9_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_ff9_reg[8]_0 ),
.Q(slaveRegDo_ff9),
.R(s_rst_o));
FDRE \slaveRegDo_ffa_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_ffa_reg[15]_0 ),
.Q(slaveRegDo_ffa),
.R(s_rst_o));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux[0]_i_2
(.I0(slaveRegDo_mux_3[0]),
.I1(slaveRegDo_mux_2[0]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_1[0]),
.I4(s_daddr_o[10]),
.I5(slaveRegDo_mux_0[0]),
.O(\slaveRegDo_mux[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[0]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[0] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[0]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[0]),
.O(\slaveRegDo_mux[0]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[10]_i_2
(.I0(slaveRegDo_mux_3[10]),
.I1(slaveRegDo_mux_2[10]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[10]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[10]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[10]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[10] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[10]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[10]),
.O(\slaveRegDo_mux[10]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[11]_i_2
(.I0(slaveRegDo_mux_3[11]),
.I1(slaveRegDo_mux_2[11]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[11]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[11]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[11]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[11] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[11]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[11]),
.O(\slaveRegDo_mux[11]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[12]_i_2
(.I0(slaveRegDo_mux_3[12]),
.I1(slaveRegDo_mux_2[12]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[12]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[12]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[12]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[12] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[12]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[12]),
.O(\slaveRegDo_mux[12]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[13]_i_2
(.I0(slaveRegDo_mux_3[13]),
.I1(slaveRegDo_mux_2[13]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[13]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[13]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[13]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[13] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[13]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[13]),
.O(\slaveRegDo_mux[13]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[14]_i_2
(.I0(slaveRegDo_mux_3[14]),
.I1(slaveRegDo_mux_2[14]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[14]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[14]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[14]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[14] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[14]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[14]),
.O(\slaveRegDo_mux[14]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[15]_i_2
(.I0(slaveRegDo_mux_3[15]),
.I1(slaveRegDo_mux_2[15]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[15]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[15]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[15] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[15]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[15]),
.O(\slaveRegDo_mux[15]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux[1]_i_2
(.I0(slaveRegDo_mux_3[1]),
.I1(slaveRegDo_mux_2[1]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_1[1]),
.I4(s_daddr_o[10]),
.I5(slaveRegDo_mux_0[1]),
.O(\slaveRegDo_mux[1]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[1]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[1] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[1]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[1]),
.O(\slaveRegDo_mux[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux[2]_i_2
(.I0(slaveRegDo_mux_3[2]),
.I1(slaveRegDo_mux_2[2]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_1[2]),
.I4(s_daddr_o[10]),
.I5(slaveRegDo_mux_0[2]),
.O(\slaveRegDo_mux[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[2]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[2] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[2]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[2]),
.O(\slaveRegDo_mux[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux[3]_i_2
(.I0(slaveRegDo_mux_3[3]),
.I1(slaveRegDo_mux_2[3]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_1[3]),
.I4(s_daddr_o[10]),
.I5(slaveRegDo_mux_0[3]),
.O(\slaveRegDo_mux[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[3]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[3] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[3]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[3]),
.O(\slaveRegDo_mux[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux[4]_i_2
(.I0(slaveRegDo_mux_3[4]),
.I1(slaveRegDo_mux_2[4]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_1[4]),
.I4(s_daddr_o[10]),
.I5(slaveRegDo_mux_0[4]),
.O(\slaveRegDo_mux[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[4]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[4] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[4]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[4]),
.O(\slaveRegDo_mux[4]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[5]_i_2
(.I0(slaveRegDo_mux_3[5]),
.I1(slaveRegDo_mux_2[5]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[5]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[5]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[5] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[5]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[5]),
.O(\slaveRegDo_mux[5]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[6]_i_2
(.I0(slaveRegDo_mux_3[6]),
.I1(slaveRegDo_mux_2[6]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[6]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[6]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[6]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[6] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[6]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[6]),
.O(\slaveRegDo_mux[6]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[7]_i_2
(.I0(slaveRegDo_mux_3[7]),
.I1(slaveRegDo_mux_2[7]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[7]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[7]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[7]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[7] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[7]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[7]),
.O(\slaveRegDo_mux[7]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[8]_i_2
(.I0(slaveRegDo_mux_3[8]),
.I1(slaveRegDo_mux_2[8]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[8]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[8]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[8] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[8]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[8]),
.O(\slaveRegDo_mux[8]_i_3_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\slaveRegDo_mux[9]_i_2
(.I0(slaveRegDo_mux_3[9]),
.I1(slaveRegDo_mux_2[9]),
.I2(s_daddr_o[11]),
.I3(slaveRegDo_mux_0[9]),
.I4(s_daddr_o[10]),
.O(\slaveRegDo_mux[9]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux[9]_i_3
(.I0(\slaveRegDo_mux_6_reg_n_0_[9] ),
.I1(s_daddr_o[11]),
.I2(slaveRegDo_mux_5[9]),
.I3(s_daddr_o[10]),
.I4(slaveRegDo_mux_4[9]),
.O(\slaveRegDo_mux[9]_i_3_n_0 ));
LUT2 #(
.INIT(4'hE))
\slaveRegDo_mux_0[15]_i_1
(.I0(\slaveRegDo_mux_0[4]_i_5_n_0 ),
.I1(s_daddr_o[6]),
.O(\slaveRegDo_mux_0[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair204" *)
LUT3 #(
.INIT(8'h45))
\slaveRegDo_mux_0[15]_i_9
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[2]),
.O(\slaveRegDo_mux_0[15]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair208" *)
LUT2 #(
.INIT(4'h2))
\slaveRegDo_mux_0[3]_i_9
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.O(\slaveRegDo_mux_0[3]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair209" *)
LUT2 #(
.INIT(4'h1))
\slaveRegDo_mux_0[4]_i_12
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[3]),
.O(\slaveRegDo_mux_0[4]_i_12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair207" *)
LUT2 #(
.INIT(4'h1))
\slaveRegDo_mux_0[4]_i_3
(.I0(s_daddr_o[7]),
.I1(s_daddr_o[5]),
.O(\slaveRegDo_mux_0[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFF8AFFFFFFAA))
\slaveRegDo_mux_0[4]_i_5
(.I0(s_daddr_o[7]),
.I1(regDrdy_i_3_n_0),
.I2(\slaveRegDo_mux_0[4]_i_12_n_0 ),
.I3(s_daddr_o[9]),
.I4(s_daddr_o[8]),
.I5(reg_19_n_0),
.O(\slaveRegDo_mux_0[4]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair207" *)
LUT3 #(
.INIT(8'hDC))
\slaveRegDo_mux_0[4]_i_8
(.I0(s_daddr_o[7]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[4]),
.O(\slaveRegDo_mux_0[4]_i_8_n_0 ));
FDRE \slaveRegDo_mux_0_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(slaveRegDo_mux_0[0]),
.R(1'b0));
FDRE \slaveRegDo_mux_0_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_7),
.Q(slaveRegDo_mux_0[10]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_6),
.Q(slaveRegDo_mux_0[11]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_5),
.Q(slaveRegDo_mux_0[12]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_4),
.Q(slaveRegDo_mux_0[13]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_3),
.Q(slaveRegDo_mux_0[14]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_1a_n_2),
.Q(slaveRegDo_mux_0[15]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(slaveRegDo_mux_0[1]),
.R(1'b0));
FDRE \slaveRegDo_mux_0_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(slaveRegDo_mux_0[2]),
.R(1'b0));
FDRE \slaveRegDo_mux_0_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(slaveRegDo_mux_0[3]),
.R(1'b0));
FDRE \slaveRegDo_mux_0_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[4]),
.Q(slaveRegDo_mux_0[4]),
.R(1'b0));
FDRE \slaveRegDo_mux_0_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_12),
.Q(slaveRegDo_mux_0[5]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_11),
.Q(slaveRegDo_mux_0[6]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_10),
.Q(slaveRegDo_mux_0[7]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_9),
.Q(slaveRegDo_mux_0[8]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_0_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_83_n_8),
.Q(slaveRegDo_mux_0[9]),
.R(\slaveRegDo_mux_0[15]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000A009A0A700AFF))
\slaveRegDo_mux_1[0]_i_1
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[4]),
.I5(s_daddr_o[3]),
.O(\slaveRegDo_mux_1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000002000CC00))
\slaveRegDo_mux_1[1]_i_1
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[0]),
.I5(s_daddr_o[3]),
.O(\slaveRegDo_mux_1[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0030003033080000))
\slaveRegDo_mux_1[2]_i_1
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[4]),
.I5(s_daddr_o[5]),
.O(\slaveRegDo_mux_1[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000004000))
\slaveRegDo_mux_1[3]_i_1
(.I0(s_daddr_o[5]),
.I1(s_daddr_o[4]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(s_daddr_o[2]),
.I5(s_daddr_o[3]),
.O(\slaveRegDo_mux_1[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000002800000000))
\slaveRegDo_mux_1[4]_i_1
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[4]),
.I5(s_daddr_o[3]),
.O(\slaveRegDo_mux_1[4]_i_1_n_0 ));
FDRE \slaveRegDo_mux_1_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_mux_1[0]_i_1_n_0 ),
.Q(slaveRegDo_mux_1[0]),
.R(1'b0));
FDRE \slaveRegDo_mux_1_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_mux_1[1]_i_1_n_0 ),
.Q(slaveRegDo_mux_1[1]),
.R(1'b0));
FDRE \slaveRegDo_mux_1_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_mux_1[2]_i_1_n_0 ),
.Q(slaveRegDo_mux_1[2]),
.R(1'b0));
FDRE \slaveRegDo_mux_1_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_mux_1[3]_i_1_n_0 ),
.Q(slaveRegDo_mux_1[3]),
.R(1'b0));
FDRE \slaveRegDo_mux_1_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\slaveRegDo_mux_1[4]_i_1_n_0 ),
.Q(slaveRegDo_mux_1[4]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair190" *)
LUT5 #(
.INIT(32'h00000010))
\slaveRegDo_mux_2[0]_i_2
(.I0(s_daddr_o[5]),
.I1(s_daddr_o[6]),
.I2(s_daddr_o[7]),
.I3(s_daddr_o[9]),
.I4(s_daddr_o[8]),
.O(\slaveRegDo_mux_2[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000400))
\slaveRegDo_mux_2[0]_i_3
(.I0(s_daddr_o[3]),
.I1(slaveRegDo_890[0]),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[4]),
.I4(s_daddr_o[0]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_2[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair204" *)
LUT3 #(
.INIT(8'h40))
\slaveRegDo_mux_2[0]_i_5
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[2]),
.O(\slaveRegDo_mux_2[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\slaveRegDo_mux_2[15]_i_1
(.I0(\slaveRegDo_mux_2[4]_i_3_n_0 ),
.O(\slaveRegDo_mux_2[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair199" *)
LUT4 #(
.INIT(16'hFFFE))
\slaveRegDo_mux_2[15]_i_3
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_2[15]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair202" *)
LUT3 #(
.INIT(8'h08))
\slaveRegDo_mux_2[15]_i_4
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[4]),
.O(\slaveRegDo_mux_2[15]_i_4_n_0 ));
LUT6 #(
.INIT(64'h000F000000000044))
\slaveRegDo_mux_2[2]_i_3
(.I0(s_daddr_o[2]),
.I1(slaveRegDo_890[2]),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[1]),
.I5(s_daddr_o[0]),
.O(\slaveRegDo_mux_2[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000E00000000000))
\slaveRegDo_mux_2[4]_i_3
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[4]),
.I2(reg_19_n_0),
.I3(s_daddr_o[7]),
.I4(\slaveRegDo_mux_2[4]_i_5_n_0 ),
.I5(\slaveRegDo_mux_2[4]_i_6_n_0 ),
.O(\slaveRegDo_mux_2[4]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000080000))
\slaveRegDo_mux_2[4]_i_4
(.I0(s_daddr_o[7]),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[2]),
.I4(reg_19_n_0),
.I5(\slaveRegDo_mux_2[4]_i_5_n_0 ),
.O(\slaveRegDo_mux_2[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair192" *)
LUT2 #(
.INIT(4'hE))
\slaveRegDo_mux_2[4]_i_5
(.I0(s_daddr_o[9]),
.I1(s_daddr_o[8]),
.O(\slaveRegDo_mux_2[4]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF80FF))
\slaveRegDo_mux_2[4]_i_6
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(\slaveRegDo_mux_0[4]_i_12_n_0 ),
.I4(s_daddr_o[9]),
.I5(s_daddr_o[8]),
.O(\slaveRegDo_mux_2[4]_i_6_n_0 ));
FDRE \slaveRegDo_mux_2_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88d_n_0),
.Q(slaveRegDo_mux_2[0]),
.R(1'b0));
FDRE \slaveRegDo_mux_2_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_5),
.Q(slaveRegDo_mux_2[10]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_6),
.Q(slaveRegDo_mux_2[11]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_7),
.Q(slaveRegDo_mux_2[12]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_8),
.Q(slaveRegDo_mux_2[13]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_9),
.Q(slaveRegDo_mux_2[14]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_10),
.Q(slaveRegDo_mux_2[15]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_15),
.Q(slaveRegDo_mux_2[1]),
.R(1'b0));
FDRE \slaveRegDo_mux_2_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_14),
.Q(slaveRegDo_mux_2[2]),
.R(1'b0));
FDRE \slaveRegDo_mux_2_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_13),
.Q(slaveRegDo_mux_2[3]),
.R(1'b0));
FDRE \slaveRegDo_mux_2_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_12),
.Q(slaveRegDo_mux_2[4]),
.R(1'b0));
FDRE \slaveRegDo_mux_2_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_0),
.Q(slaveRegDo_mux_2[5]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_1),
.Q(slaveRegDo_mux_2[6]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_2),
.Q(slaveRegDo_mux_2[7]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_3),
.Q(slaveRegDo_mux_2[8]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
FDRE \slaveRegDo_mux_2_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_88f_n_4),
.Q(slaveRegDo_mux_2[9]),
.R(\slaveRegDo_mux_2[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair200" *)
LUT4 #(
.INIT(16'h3022))
\slaveRegDo_mux_3[11]_i_3
(.I0(\slaveRegDo_ff8_reg_n_0_[12] ),
.I1(s_daddr_o[0]),
.I2(slaveRegDo_ffa),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_3[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair200" *)
LUT3 #(
.INIT(8'h02))
\slaveRegDo_mux_3[12]_i_2
(.I0(\slaveRegDo_ff8_reg_n_0_[12] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.O(\slaveRegDo_mux_3[12]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair199" *)
LUT3 #(
.INIT(8'hDF))
\slaveRegDo_mux_3[15]_i_3
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[3]),
.O(\slaveRegDo_mux_3[15]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair209" *)
LUT2 #(
.INIT(4'h8))
\slaveRegDo_mux_3[15]_i_4
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[3]),
.O(\slaveRegDo_mux_3[15]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair196" *)
LUT3 #(
.INIT(8'h20))
\slaveRegDo_mux_3[6]_i_2
(.I0(slaveRegDo_ff9),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.O(\slaveRegDo_mux_3[6]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair196" *)
LUT4 #(
.INIT(16'h2320))
\slaveRegDo_mux_3[7]_i_3
(.I0(slaveRegDo_ff9),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(\slaveRegDo_ff8_reg_n_0_[7] ),
.O(\slaveRegDo_mux_3[7]_i_3_n_0 ));
FDRE \slaveRegDo_mux_3_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_0),
.Q(slaveRegDo_mux_3[0]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_2 ),
.Q(slaveRegDo_mux_3[10]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_1),
.Q(slaveRegDo_mux_3[11]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_0 ),
.Q(slaveRegDo_mux_3[12]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_10 ),
.Q(slaveRegDo_mux_3[13]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_3 ),
.Q(slaveRegDo_mux_3[14]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_4 ),
.Q(slaveRegDo_mux_3[15]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_9),
.Q(slaveRegDo_mux_3[1]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_8),
.Q(slaveRegDo_mux_3[2]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_7),
.Q(slaveRegDo_mux_3[3]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_6),
.Q(slaveRegDo_mux_3[4]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_5),
.Q(slaveRegDo_mux_3[5]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\ADV_TRIG_STREAM_READBACK.reg_stream_ffb_n_1 ),
.Q(slaveRegDo_mux_3[6]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_4),
.Q(slaveRegDo_mux_3[7]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_3),
.Q(slaveRegDo_mux_3[8]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_3_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(reg_srl_fff_n_2),
.Q(slaveRegDo_mux_3[9]),
.R(\ADV_TRIG_STREAM.reg_stream_ffc_n_3 ));
FDRE \slaveRegDo_mux_4_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_15 ),
.Q(slaveRegDo_mux_4[0]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_5 ),
.Q(slaveRegDo_mux_4[10]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_4 ),
.Q(slaveRegDo_mux_4[11]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_3 ),
.Q(slaveRegDo_mux_4[12]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_2 ),
.Q(slaveRegDo_mux_4[13]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_1 ),
.Q(slaveRegDo_mux_4[14]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_0 ),
.Q(slaveRegDo_mux_4[15]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_14 ),
.Q(slaveRegDo_mux_4[1]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_13 ),
.Q(slaveRegDo_mux_4[2]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_12 ),
.Q(slaveRegDo_mux_4[3]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_11 ),
.Q(slaveRegDo_mux_4[4]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_10 ),
.Q(slaveRegDo_mux_4[5]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_9 ),
.Q(slaveRegDo_mux_4[6]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_8 ),
.Q(slaveRegDo_mux_4[7]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_7 ),
.Q(slaveRegDo_mux_4[8]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_4_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\MU_SRL[11].mu_srl_reg_n_6 ),
.Q(slaveRegDo_mux_4[9]),
.R(s_daddr_o[4]));
FDRE \slaveRegDo_mux_5_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_15 ),
.Q(slaveRegDo_mux_5[0]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_5 ),
.Q(slaveRegDo_mux_5[10]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_4 ),
.Q(slaveRegDo_mux_5[11]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_3 ),
.Q(slaveRegDo_mux_5[12]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_2 ),
.Q(slaveRegDo_mux_5[13]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_1 ),
.Q(slaveRegDo_mux_5[14]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_0 ),
.Q(slaveRegDo_mux_5[15]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_14 ),
.Q(slaveRegDo_mux_5[1]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_13 ),
.Q(slaveRegDo_mux_5[2]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_12 ),
.Q(slaveRegDo_mux_5[3]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_11 ),
.Q(slaveRegDo_mux_5[4]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_10 ),
.Q(slaveRegDo_mux_5[5]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_9 ),
.Q(slaveRegDo_mux_5[6]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_8 ),
.Q(slaveRegDo_mux_5[7]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_7 ),
.Q(slaveRegDo_mux_5[8]),
.R(1'b0));
FDRE \slaveRegDo_mux_5_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\TC_SRL[27].tc_srl_reg_n_6 ),
.Q(slaveRegDo_mux_5[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\slaveRegDo_mux_6[15]_i_2
(.I0(s_daddr_o[4]),
.I1(reg_19_n_0),
.I2(s_daddr_o[7]),
.I3(s_daddr_o[8]),
.I4(s_daddr_o[9]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.O(\slaveRegDo_mux_6[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFDFFFFF))
\slaveRegDo_mux_6[15]_i_4
(.I0(\slaveRegDo_mux_0[4]_i_12_n_0 ),
.I1(\slaveRegDo_mux_2[4]_i_5_n_0 ),
.I2(\slaveRegDo_mux_0[4]_i_3_n_0 ),
.I3(drdy_ff8_i_2_n_0),
.I4(s_daddr_o[2]),
.I5(s_daddr_o[6]),
.O(\slaveRegDo_mux_6[15]_i_4_n_0 ));
FDRE \slaveRegDo_mux_6_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_15 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[0] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_5 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[10] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_4 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[11] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_3 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[12] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_2 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[13] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_1 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[14] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\CNT.CNT_SRL[3].cnt_srl_reg_n_0 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[15] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_14 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[1] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_13 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[2] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_12 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[3] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_11 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[4] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_10 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[5] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_9 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[6] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_8 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[7] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_7 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[8] ),
.R(1'b0));
FDRE \slaveRegDo_mux_6_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\STRG_QUAL.qual_strg_srl_reg_n_6 ),
.Q(\slaveRegDo_mux_6_reg_n_0_[9] ),
.R(1'b0));
FDRE \slaveRegDo_mux_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[0]),
.Q(\slaveRegDo_mux_reg_n_0_[0] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[0]_i_1
(.I0(\slaveRegDo_mux[0]_i_2_n_0 ),
.I1(\slaveRegDo_mux[0]_i_3_n_0 ),
.O(slaveRegDo_mux[0]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[10]),
.Q(\slaveRegDo_mux_reg_n_0_[10] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[10]_i_1
(.I0(\slaveRegDo_mux[10]_i_2_n_0 ),
.I1(\slaveRegDo_mux[10]_i_3_n_0 ),
.O(slaveRegDo_mux[10]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[11]),
.Q(\slaveRegDo_mux_reg_n_0_[11] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[11]_i_1
(.I0(\slaveRegDo_mux[11]_i_2_n_0 ),
.I1(\slaveRegDo_mux[11]_i_3_n_0 ),
.O(slaveRegDo_mux[11]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[12]),
.Q(\slaveRegDo_mux_reg_n_0_[12] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[12]_i_1
(.I0(\slaveRegDo_mux[12]_i_2_n_0 ),
.I1(\slaveRegDo_mux[12]_i_3_n_0 ),
.O(slaveRegDo_mux[12]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[13]),
.Q(\slaveRegDo_mux_reg_n_0_[13] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[13]_i_1
(.I0(\slaveRegDo_mux[13]_i_2_n_0 ),
.I1(\slaveRegDo_mux[13]_i_3_n_0 ),
.O(slaveRegDo_mux[13]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[14]),
.Q(\slaveRegDo_mux_reg_n_0_[14] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[14]_i_1
(.I0(\slaveRegDo_mux[14]_i_2_n_0 ),
.I1(\slaveRegDo_mux[14]_i_3_n_0 ),
.O(slaveRegDo_mux[14]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[15]),
.Q(\slaveRegDo_mux_reg_n_0_[15] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[15]_i_1
(.I0(\slaveRegDo_mux[15]_i_2_n_0 ),
.I1(\slaveRegDo_mux[15]_i_3_n_0 ),
.O(slaveRegDo_mux[15]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[1]),
.Q(\slaveRegDo_mux_reg_n_0_[1] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[1]_i_1
(.I0(\slaveRegDo_mux[1]_i_2_n_0 ),
.I1(\slaveRegDo_mux[1]_i_3_n_0 ),
.O(slaveRegDo_mux[1]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[2]),
.Q(\slaveRegDo_mux_reg_n_0_[2] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[2]_i_1
(.I0(\slaveRegDo_mux[2]_i_2_n_0 ),
.I1(\slaveRegDo_mux[2]_i_3_n_0 ),
.O(slaveRegDo_mux[2]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[3]),
.Q(\slaveRegDo_mux_reg_n_0_[3] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[3]_i_1
(.I0(\slaveRegDo_mux[3]_i_2_n_0 ),
.I1(\slaveRegDo_mux[3]_i_3_n_0 ),
.O(slaveRegDo_mux[3]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[4]),
.Q(\slaveRegDo_mux_reg_n_0_[4] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[4]_i_1
(.I0(\slaveRegDo_mux[4]_i_2_n_0 ),
.I1(\slaveRegDo_mux[4]_i_3_n_0 ),
.O(slaveRegDo_mux[4]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[5]),
.Q(\slaveRegDo_mux_reg_n_0_[5] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[5]_i_1
(.I0(\slaveRegDo_mux[5]_i_2_n_0 ),
.I1(\slaveRegDo_mux[5]_i_3_n_0 ),
.O(slaveRegDo_mux[5]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[6]),
.Q(\slaveRegDo_mux_reg_n_0_[6] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[6]_i_1
(.I0(\slaveRegDo_mux[6]_i_2_n_0 ),
.I1(\slaveRegDo_mux[6]_i_3_n_0 ),
.O(slaveRegDo_mux[6]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[7]),
.Q(\slaveRegDo_mux_reg_n_0_[7] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[7]_i_1
(.I0(\slaveRegDo_mux[7]_i_2_n_0 ),
.I1(\slaveRegDo_mux[7]_i_3_n_0 ),
.O(slaveRegDo_mux[7]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[8]),
.Q(\slaveRegDo_mux_reg_n_0_[8] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[8]_i_1
(.I0(\slaveRegDo_mux[8]_i_2_n_0 ),
.I1(\slaveRegDo_mux[8]_i_3_n_0 ),
.O(slaveRegDo_mux[8]),
.S(s_daddr_o[12]));
FDRE \slaveRegDo_mux_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(slaveRegDo_mux[9]),
.Q(\slaveRegDo_mux_reg_n_0_[9] ),
.R(1'b0));
MUXF7 \slaveRegDo_mux_reg[9]_i_1
(.I0(\slaveRegDo_mux[9]_i_2_n_0 ),
.I1(\slaveRegDo_mux[9]_i_3_n_0 ),
.O(slaveRegDo_mux[9]),
.S(s_daddr_o[12]));
(* SOFT_HLUTNM = "soft_lutpair191" *)
LUT5 #(
.INIT(32'h7FFF8000))
toggle_rd_i_1
(.I0(bram_rd_en_i_2_n_0),
.I1(bram_rd_en_i_3_n_0),
.I2(config_fsm_en_rb),
.I3(bram_rd_en_i_4_n_0),
.I4(toggle_rd),
.O(toggle_rd_reg));
endmodule | 8 |
2,150 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_reset_ctrl
(temp_reg0_reg,
Q,
\SEQUENCER_STATE_O_reg[8] ,
\captured_samples_reg[0] ,
out,
s_dclk_o,
cap_done,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
\current_state_reg[3] ,
halt_ctrl,
arm_ctrl);
output [1:0]temp_reg0_reg;
output [3:0]Q;
output \SEQUENCER_STATE_O_reg[8] ;
output [0:0]\captured_samples_reg[0] ;
input out;
input s_dclk_o;
input cap_done;
input \I_YESLUT6.I_YES_OREG.O_reg_reg ;
input \current_state_reg[3] ;
input halt_ctrl;
input arm_ctrl;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [3:0]Q;
wire \SEQUENCER_STATE_O_reg[8] ;
wire arm_ctrl;
wire arm_detection_inst_n_1;
wire arm_in_detection;
wire arm_in_transferred;
wire \asyncrounous_transfer.arm_in_transfer_inst_n_1 ;
wire \asyncrounous_transfer.halt_in_transfer_inst_n_1 ;
wire cap_done;
wire [0:0]\captured_samples_reg[0] ;
wire \current_state_reg[3] ;
wire halt_ctrl;
wire halt_detection_inst_n_1;
wire halt_detection_inst_n_2;
wire halt_in_transferred;
wire halt_out;
wire last_din;
wire last_din_0;
wire out;
wire prev_cap_done;
wire [4:2]reset;
wire s_dclk_o;
wire [1:0]temp_reg0_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection arm_detection_inst
(.D(arm_detection_inst_n_1),
.Q(Q[1]),
.clk(out),
.dout_reg1_reg(\asyncrounous_transfer.arm_in_transfer_inst_n_1 ),
.last_din(last_din),
.out(arm_in_transferred),
.\reset_out_reg[0] (arm_in_detection));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer \asyncrounous_transfer.arm_in_transfer_inst
(.arm_ctrl(arm_ctrl),
.clk(out),
.\dout_pulse_reg[0] (\asyncrounous_transfer.arm_in_transfer_inst_n_1 ),
.last_din(last_din),
.out(arm_in_transferred),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_160 \asyncrounous_transfer.arm_out_transfer_inst
(.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.Q(Q[0]),
.\SEQUENCER_STATE_O_reg[8] (\SEQUENCER_STATE_O_reg[8] ),
.\current_state_reg[3] (\current_state_reg[3] ),
.out(out),
.s_dclk_o(s_dclk_o),
.temp_reg0_reg_0(temp_reg0_reg[0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_161 \asyncrounous_transfer.halt_in_transfer_inst
(.D(\asyncrounous_transfer.halt_in_transfer_inst_n_1 ),
.clk(out),
.halt_ctrl(halt_ctrl),
.last_din(last_din_0),
.out(halt_in_transferred),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_162 \asyncrounous_transfer.halt_out_transfer_inst
(.halt_out(halt_out),
.out(out),
.s_dclk_o(s_dclk_o),
.temp_reg0_reg_0(temp_reg0_reg[1]));
LUT1 #(
.INIT(2'h1))
\captured_samples[14]_i_1
(.I0(Q[0]),
.O(\captured_samples_reg[0] ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection_163 halt_detection_inst
(.D(\asyncrounous_transfer.halt_in_transfer_inst_n_1 ),
.Q(Q[0]),
.SS(halt_detection_inst_n_1),
.cap_done(cap_done),
.clk(out),
.\dout_pulse_reg[1]_0 (arm_in_detection),
.halt_out(halt_out),
.halt_out_reg(halt_detection_inst_n_2),
.last_din(last_din_0),
.out(halt_in_transferred),
.prev_cap_done(prev_cap_done));
FDRE #(
.INIT(1'b0))
halt_out_reg
(.C(out),
.CE(1'b1),
.D(halt_detection_inst_n_2),
.Q(halt_out),
.R(1'b0));
FDRE prev_cap_done_reg
(.C(out),
.CE(1'b1),
.D(cap_done),
.Q(prev_cap_done),
.R(1'b0));
FDSE #(
.INIT(1'b1))
\reset_out_reg[0]
(.C(out),
.CE(1'b1),
.D(arm_detection_inst_n_1),
.Q(Q[0]),
.S(halt_detection_inst_n_1));
FDSE #(
.INIT(1'b1))
\reset_out_reg[1]
(.C(out),
.CE(1'b1),
.D(Q[0]),
.Q(Q[1]),
.S(halt_detection_inst_n_1));
FDSE #(
.INIT(1'b1))
\reset_out_reg[2]
(.C(out),
.CE(1'b1),
.D(Q[1]),
.Q(reset[2]),
.S(halt_detection_inst_n_1));
FDSE #(
.INIT(1'b1))
\reset_out_reg[3]
(.C(out),
.CE(1'b1),
.D(reset[2]),
.Q(Q[2]),
.S(halt_detection_inst_n_1));
FDSE #(
.INIT(1'b1))
\reset_out_reg[4]
(.C(out),
.CE(1'b1),
.D(Q[2]),
.Q(reset[4]),
.S(halt_detection_inst_n_1));
FDSE #(
.INIT(1'b1))
\reset_out_reg[5]
(.C(out),
.CE(1'b1),
.D(reset[4]),
.Q(Q[3]),
.S(halt_detection_inst_n_1));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_reset_ctrl
(temp_reg0_reg,
Q,
\SEQUENCER_STATE_O_reg[8] ,
\captured_samples_reg[0] ,
out,
s_dclk_o,
cap_done,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
\current_state_reg[3] ,
halt_ctrl,
arm_ctrl); |
output [1:0]temp_reg0_reg;
output [3:0]Q;
output \SEQUENCER_STATE_O_reg[8] ;
output [0:0]\captured_samples_reg[0] ;
input out;
input s_dclk_o;
input cap_done;
input \I_YESLUT6.I_YES_OREG.O_reg_reg ;
input \current_state_reg[3] ;
input halt_ctrl;
input arm_ctrl;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [3:0]Q;
wire \SEQUENCER_STATE_O_reg[8] ;
wire arm_ctrl;
wire arm_detection_inst_n_1;
wire arm_in_detection;
wire arm_in_transferred;
wire \asyncrounous_transfer.arm_in_transfer_inst_n_1 ;
wire \asyncrounous_transfer.halt_in_transfer_inst_n_1 ;
wire cap_done;
wire [0:0]\captured_samples_reg[0] ;
wire \current_state_reg[3] ;
wire halt_ctrl;
wire halt_detection_inst_n_1;
wire halt_detection_inst_n_2;
wire halt_in_transferred;
wire halt_out;
wire last_din;
wire last_din_0;
wire out;
wire prev_cap_done;
wire [4:2]reset;
wire s_dclk_o;
wire [1:0]temp_reg0_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection arm_detection_inst
(.D(arm_detection_inst_n_1),
.Q(Q[1]),
.clk(out),
.dout_reg1_reg(\asyncrounous_transfer.arm_in_transfer_inst_n_1 ),
.last_din(last_din),
.out(arm_in_transferred),
.\reset_out_reg[0] (arm_in_detection));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer \asyncrounous_transfer.arm_in_transfer_inst
(.arm_ctrl(arm_ctrl),
.clk(out),
.\dout_pulse_reg[0] (\asyncrounous_transfer.arm_in_transfer_inst_n_1 ),
.last_din(last_din),
.out(arm_in_transferred),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_160 \asyncrounous_transfer.arm_out_transfer_inst
(.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.Q(Q[0]),
.\SEQUENCER_STATE_O_reg[8] (\SEQUENCER_STATE_O_reg[8] ),
.\current_state_reg[3] (\current_state_reg[3] ),
.out(out),
.s_dclk_o(s_dclk_o),
.temp_reg0_reg_0(temp_reg0_reg[0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_161 \asyncrounous_transfer.halt_in_transfer_inst
(.D(\asyncrounous_transfer.halt_in_transfer_inst_n_1 ),
.clk(out),
.halt_ctrl(halt_ctrl),
.last_din(last_din_0),
.out(halt_in_transferred),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_async_edge_xfer_162 \asyncrounous_transfer.halt_out_transfer_inst
(.halt_out(halt_out),
.out(out),
.s_dclk_o(s_dclk_o),
.temp_reg0_reg_0(temp_reg0_reg[1]));
LUT1 #(
.INIT(2'h1))
\captured_samples[14]_i_1
(.I0(Q[0]),
.O(\captured_samples_reg[0] ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection_163 halt_detection_inst
(.D(\asyncrounous_transfer.halt_in_transfer_inst_n_1 ),
.Q(Q[0]),
.SS(halt_detection_inst_n_1),
.cap_done(cap_done),
.clk(out),
.\dout_pulse_reg[1]_0 (arm_in_detection),
.halt_out(halt_out),
.halt_out_reg(halt_detection_inst_n_2),
.last_din(last_din_0),
.out(halt_in_transferred),
.prev_cap_done(prev_cap_done));
FDRE #(
.INIT(1'b0))
halt_out_reg
(.C(out),
.CE(1'b1),
.D(halt_detection_inst_n_2),
.Q(halt_out),
.R(1'b0));
FDRE prev_cap_done_reg
(.C(out),
.CE(1'b1),
.D(cap_done),
.Q(prev_cap_done),
.R(1'b0));
FDSE #(
.INIT(1'b1))
\reset_out_reg[0]
(.C(out),
.CE(1'b1),
.D(arm_detection_inst_n_1),
.Q(Q[0]),
.S(halt_detection_inst_n_1));
FDSE #(
.INIT(1'b1))
\reset_out_reg[1]
(.C(out),
.CE(1'b1),
.D(Q[0]),
.Q(Q[1]),
.S(halt_detection_inst_n_1));
FDSE #(
.INIT(1'b1))
\reset_out_reg[2]
(.C(out),
.CE(1'b1),
.D(Q[1]),
.Q(reset[2]),
.S(halt_detection_inst_n_1));
FDSE #(
.INIT(1'b1))
\reset_out_reg[3]
(.C(out),
.CE(1'b1),
.D(reset[2]),
.Q(Q[2]),
.S(halt_detection_inst_n_1));
FDSE #(
.INIT(1'b1))
\reset_out_reg[4]
(.C(out),
.CE(1'b1),
.D(Q[2]),
.Q(reset[4]),
.S(halt_detection_inst_n_1));
FDSE #(
.INIT(1'b1))
\reset_out_reg[5]
(.C(out),
.CE(1'b1),
.D(reset[4]),
.Q(Q[3]),
.S(halt_detection_inst_n_1));
endmodule | 8 |
2,151 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trace_memory
(D,
out,
S_DCLK_O,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[14] ,
Q,
ADDRBWRADDR,
DIADI,
DIPADIP,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ,
\read_addr_reg[11]_rep ,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ,
CAP_TRIGGER_O_reg,
CAP_WR_EN_O_reg);
output [52:0]D;
input out;
input S_DCLK_O;
input [7:0]enb_array;
input [0:0]E;
input [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
input [14:0]Q;
input [0:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
input [10:0]\read_addr_reg[11]_rep ;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
input [7:0]CAP_TRIGGER_O_reg;
input CAP_WR_EN_O_reg;
wire [0:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire CAP_WR_EN_O_reg;
wire [52:0]D;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire [14:0]Q;
wire S_DCLK_O;
wire [7:0]enb_array;
wire [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
wire out;
wire [10:0]\read_addr_reg[11]_rep ;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 \SUBCORE_RAM_BLK_MEM_1.trace_block_memory
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.CAP_WR_EN_O_reg(CAP_WR_EN_O_reg),
.D(D),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.Q(Q),
.S_DCLK_O(S_DCLK_O),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[14] (\i_intcap.CAP_ADDR_O_reg[14] ),
.out(out),
.\read_addr_reg[11]_rep (\read_addr_reg[11]_rep ),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trace_memory
(D,
out,
S_DCLK_O,
enb_array,
E,
\i_intcap.CAP_ADDR_O_reg[14] ,
Q,
ADDRBWRADDR,
DIADI,
DIPADIP,
\shifted_data_in_reg[8][16] ,
\shifted_data_in_reg[8][17] ,
\shifted_data_in_reg[8][25] ,
\shifted_data_in_reg[8][26] ,
\read_addr_reg[11]_rep ,
\shifted_data_in_reg[8][34] ,
\shifted_data_in_reg[8][35] ,
\shifted_data_in_reg[8][43] ,
\shifted_data_in_reg[8][44] ,
CAP_TRIGGER_O_reg,
CAP_WR_EN_O_reg); |
output [52:0]D;
input out;
input S_DCLK_O;
input [7:0]enb_array;
input [0:0]E;
input [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
input [14:0]Q;
input [0:0]ADDRBWRADDR;
input [7:0]DIADI;
input [0:0]DIPADIP;
input [7:0]\shifted_data_in_reg[8][16] ;
input [0:0]\shifted_data_in_reg[8][17] ;
input [7:0]\shifted_data_in_reg[8][25] ;
input [0:0]\shifted_data_in_reg[8][26] ;
input [10:0]\read_addr_reg[11]_rep ;
input [7:0]\shifted_data_in_reg[8][34] ;
input [0:0]\shifted_data_in_reg[8][35] ;
input [7:0]\shifted_data_in_reg[8][43] ;
input [0:0]\shifted_data_in_reg[8][44] ;
input [7:0]CAP_TRIGGER_O_reg;
input CAP_WR_EN_O_reg;
wire [0:0]ADDRBWRADDR;
wire [7:0]CAP_TRIGGER_O_reg;
wire CAP_WR_EN_O_reg;
wire [52:0]D;
wire [7:0]DIADI;
wire [0:0]DIPADIP;
wire [0:0]E;
wire [14:0]Q;
wire S_DCLK_O;
wire [7:0]enb_array;
wire [14:0]\i_intcap.CAP_ADDR_O_reg[14] ;
wire out;
wire [10:0]\read_addr_reg[11]_rep ;
wire [7:0]\shifted_data_in_reg[8][16] ;
wire [0:0]\shifted_data_in_reg[8][17] ;
wire [7:0]\shifted_data_in_reg[8][25] ;
wire [0:0]\shifted_data_in_reg[8][26] ;
wire [7:0]\shifted_data_in_reg[8][34] ;
wire [0:0]\shifted_data_in_reg[8][35] ;
wire [7:0]\shifted_data_in_reg[8][43] ;
wire [0:0]\shifted_data_in_reg[8][44] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 \SUBCORE_RAM_BLK_MEM_1.trace_block_memory
(.ADDRBWRADDR(ADDRBWRADDR),
.CAP_TRIGGER_O_reg(CAP_TRIGGER_O_reg),
.CAP_WR_EN_O_reg(CAP_WR_EN_O_reg),
.D(D),
.DIADI(DIADI),
.DIPADIP(DIPADIP),
.E(E),
.Q(Q),
.S_DCLK_O(S_DCLK_O),
.enb_array(enb_array),
.\i_intcap.CAP_ADDR_O_reg[14] (\i_intcap.CAP_ADDR_O_reg[14] ),
.out(out),
.\read_addr_reg[11]_rep (\read_addr_reg[11]_rep ),
.\shifted_data_in_reg[8][16] (\shifted_data_in_reg[8][16] ),
.\shifted_data_in_reg[8][17] (\shifted_data_in_reg[8][17] ),
.\shifted_data_in_reg[8][25] (\shifted_data_in_reg[8][25] ),
.\shifted_data_in_reg[8][26] (\shifted_data_in_reg[8][26] ),
.\shifted_data_in_reg[8][34] (\shifted_data_in_reg[8][34] ),
.\shifted_data_in_reg[8][35] (\shifted_data_in_reg[8][35] ),
.\shifted_data_in_reg[8][43] (\shifted_data_in_reg[8][43] ),
.\shifted_data_in_reg[8][44] (\shifted_data_in_reg[8][44] ));
endmodule | 8 |
2,152 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trig_match
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data);
output [9:0]mu_config_cs_serial_input;
output [9:0]D;
input [9:0]mu_config_cs_shift_en;
input s_dclk_o;
input [9:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [4:0]probe_data;
wire [9:0]D;
wire [0:0]Q;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_1 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_3 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_5 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_7 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_0 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_2 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_4 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_6 ;
wire [9:0]mu_config_cs_serial_input;
wire [9:0]mu_config_cs_serial_output;
wire [9:0]mu_config_cs_shift_en;
wire out;
wire [4:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0 \N_DDR_MODE.G_NMU[0].U_M
(.D(D[0]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[0]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[0]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[0]),
.out(out),
.probe_data(probe_data[0]),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized6 \N_DDR_MODE.G_NMU[10].U_M
(.D(D[6]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_1 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_0 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[6]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[6]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[6]),
.out(out),
.probe_data(probe_data[3]),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized7 \N_DDR_MODE.G_NMU[11].U_M
(.D(D[7]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_1 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_0 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[7]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[7]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[7]),
.out(out),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized8 \N_DDR_MODE.G_NMU[14].U_M
(.D(D[8]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_3 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_2 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[8]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[8]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[8]),
.out(out),
.probe_data(probe_data[4]),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized9 \N_DDR_MODE.G_NMU[15].U_M
(.D(D[9]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_3 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_2 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[9]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[9]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[9]),
.out(out),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1 \N_DDR_MODE.G_NMU[1].U_M
(.D(D[1]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[1]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[1]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[1]),
.out(out),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized2 \N_DDR_MODE.G_NMU[2].U_M
(.D(D[2]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_5 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_4 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[2]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[2]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[2]),
.out(out),
.probe_data(probe_data[1]),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized3 \N_DDR_MODE.G_NMU[3].U_M
(.D(D[3]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_5 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_4 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[3]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[3]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[3]),
.out(out),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized4 \N_DDR_MODE.G_NMU[8].U_M
(.D(D[4]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_7 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_6 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[4]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[4]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[4]),
.out(out),
.probe_data(probe_data[2]),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized5 \N_DDR_MODE.G_NMU[9].U_M
(.D(D[5]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_7 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_6 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[5]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[5]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[5]),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trig_match
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data); |
output [9:0]mu_config_cs_serial_input;
output [9:0]D;
input [9:0]mu_config_cs_shift_en;
input s_dclk_o;
input [9:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [4:0]probe_data;
wire [9:0]D;
wire [0:0]Q;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_1 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_3 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_5 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_7 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_0 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_2 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_4 ;
wire [0:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_6 ;
wire [9:0]mu_config_cs_serial_input;
wire [9:0]mu_config_cs_serial_output;
wire [9:0]mu_config_cs_shift_en;
wire out;
wire [4:0]probe_data;
wire s_dclk_o;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0 \N_DDR_MODE.G_NMU[0].U_M
(.D(D[0]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[0]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[0]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[0]),
.out(out),
.probe_data(probe_data[0]),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized6 \N_DDR_MODE.G_NMU[10].U_M
(.D(D[6]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_1 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_0 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[6]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[6]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[6]),
.out(out),
.probe_data(probe_data[3]),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized7 \N_DDR_MODE.G_NMU[11].U_M
(.D(D[7]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_1 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_0 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[7]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[7]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[7]),
.out(out),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized8 \N_DDR_MODE.G_NMU[14].U_M
(.D(D[8]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_3 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_2 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[8]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[8]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[8]),
.out(out),
.probe_data(probe_data[4]),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized9 \N_DDR_MODE.G_NMU[15].U_M
(.D(D[9]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_3 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_2 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[9]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[9]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[9]),
.out(out),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1 \N_DDR_MODE.G_NMU[1].U_M
(.D(D[1]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[1]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[1]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[1]),
.out(out),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized2 \N_DDR_MODE.G_NMU[2].U_M
(.D(D[2]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_5 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_4 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[2]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[2]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[2]),
.out(out),
.probe_data(probe_data[1]),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized3 \N_DDR_MODE.G_NMU[3].U_M
(.D(D[3]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_5 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_4 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[3]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[3]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[3]),
.out(out),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized4 \N_DDR_MODE.G_NMU[8].U_M
(.D(D[4]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_7 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_6 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[4]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[4]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[4]),
.out(out),
.probe_data(probe_data[2]),
.s_dclk_o(s_dclk_o));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized5 \N_DDR_MODE.G_NMU[9].U_M
(.D(D[5]),
.Q(Q),
.all_dly1(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly1_7 ),
.all_dly2(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2_6 ),
.mu_config_cs_serial_input(mu_config_cs_serial_input[5]),
.mu_config_cs_serial_output(mu_config_cs_serial_output[5]),
.mu_config_cs_shift_en(mu_config_cs_shift_en[5]),
.out(out),
.s_dclk_o(s_dclk_o));
endmodule | 8 |
2,153 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trigger
(\parallel_dout_reg[15] ,
mu_config_cs_serial_input,
tc_config_cs_serial_input,
capture_strg_qual,
ADDRA,
basic_trigger_reg,
shift_en_reg,
s_dclk_o,
qual_strg_config_cs_serial_output,
mu_config_cs_shift_en,
mu_config_cs_serial_output,
tc_config_cs_shift_en,
tc_config_cs_serial_output,
out,
Q,
probe_data,
\current_state_reg[3] ,
\current_state_reg[2] ,
\current_state_reg[1] ,
\current_state_reg[0] );
output [0:0]\parallel_dout_reg[15] ;
output [9:0]mu_config_cs_serial_input;
output [31:0]tc_config_cs_serial_input;
output capture_strg_qual;
output [1:0]ADDRA;
output [0:0]basic_trigger_reg;
input [0:0]shift_en_reg;
input s_dclk_o;
input qual_strg_config_cs_serial_output;
input [9:0]mu_config_cs_shift_en;
input [9:0]mu_config_cs_serial_output;
input [31:0]tc_config_cs_shift_en;
input [31:0]tc_config_cs_serial_output;
input out;
input [2:0]Q;
input [4:0]probe_data;
input \current_state_reg[3] ;
input \current_state_reg[2] ;
input \current_state_reg[1] ;
input \current_state_reg[0] ;
wire [1:0]ADDRA;
wire [2:0]Q;
wire \TRIGGER_EQ_reg_n_0_[10] ;
wire \TRIGGER_EQ_reg_n_0_[11] ;
wire \TRIGGER_EQ_reg_n_0_[12] ;
wire \TRIGGER_EQ_reg_n_0_[13] ;
wire \TRIGGER_EQ_reg_n_0_[14] ;
wire \TRIGGER_EQ_reg_n_0_[15] ;
wire \TRIGGER_EQ_reg_n_0_[1] ;
wire \TRIGGER_EQ_reg_n_0_[2] ;
wire \TRIGGER_EQ_reg_n_0_[3] ;
wire \TRIGGER_EQ_reg_n_0_[4] ;
wire \TRIGGER_EQ_reg_n_0_[5] ;
wire \TRIGGER_EQ_reg_n_0_[6] ;
wire \TRIGGER_EQ_reg_n_0_[7] ;
wire \TRIGGER_EQ_reg_n_0_[8] ;
wire \TRIGGER_EQ_reg_n_0_[9] ;
wire [9:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ;
wire [0:0]basic_trigger_reg;
wire cap_strg_qual;
wire capture_strg_qual;
wire \current_state_reg[0] ;
wire \current_state_reg[1] ;
wire \current_state_reg[2] ;
wire \current_state_reg[3] ;
wire data0;
wire data1;
wire data10;
wire data11;
wire data12;
wire data13;
wire data14;
wire data15;
wire data2;
wire data3;
wire data4;
wire data5;
wire data6;
wire data7;
wire data8;
wire data9;
wire fsm_mem_data_reg_r1_0_63_0_2_i_10_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_11_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_12_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_13_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_14_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_15_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_4_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_5_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_6_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_7_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_8_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_9_n_0;
wire [9:0]mu_config_cs_serial_input;
wire [9:0]mu_config_cs_serial_output;
wire [9:0]mu_config_cs_shift_en;
wire out;
wire [0:0]\parallel_dout_reg[15] ;
wire [4:0]probe_data;
wire qual_strg_config_cs_serial_output;
wire s_dclk_o;
wire shift_cap_strg_qual;
wire [0:0]shift_en_reg;
wire [31:0]tc_config_cs_serial_input;
wire [31:0]tc_config_cs_serial_output;
wire [31:0]tc_config_cs_shift_en;
wire [15:0]trigCondIn_temp;
wire [31:0]trigEqOut;
FDRE CAP_QUAL_STRG_reg
(.C(out),
.CE(1'b1),
.D(shift_cap_strg_qual),
.Q(capture_strg_qual),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match \N_DDR_TC.N_DDR_TC_INST[0].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[0] (trigEqOut[0]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[0]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[0]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_0 \N_DDR_TC.N_DDR_TC_INST[10].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[10] (trigEqOut[10]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[10]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[10]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[10]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_1 \N_DDR_TC.N_DDR_TC_INST[11].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[11] (trigEqOut[11]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[11]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[11]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[11]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_2 \N_DDR_TC.N_DDR_TC_INST[12].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[12] (trigEqOut[12]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[12]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[12]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[12]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_3 \N_DDR_TC.N_DDR_TC_INST[13].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[13] (trigEqOut[13]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[13]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[13]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[13]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_4 \N_DDR_TC.N_DDR_TC_INST[14].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[14] (trigEqOut[14]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[14]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[14]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[14]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_5 \N_DDR_TC.N_DDR_TC_INST[15].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[15] (trigEqOut[15]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[15]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[15]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[15]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_6 \N_DDR_TC.N_DDR_TC_INST[16].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[16] (trigEqOut[16]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[16]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[16]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[16]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_7 \N_DDR_TC.N_DDR_TC_INST[17].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[17] (trigEqOut[17]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[17]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[17]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[17]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_8 \N_DDR_TC.N_DDR_TC_INST[18].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[18] (trigEqOut[18]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[18]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[18]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[18]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_9 \N_DDR_TC.N_DDR_TC_INST[19].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[19] (trigEqOut[19]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[19]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[19]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[19]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_10 \N_DDR_TC.N_DDR_TC_INST[1].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[1] (trigEqOut[1]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[1]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[1]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[1]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_11 \N_DDR_TC.N_DDR_TC_INST[20].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[20] (trigEqOut[20]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[20]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[20]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[20]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_12 \N_DDR_TC.N_DDR_TC_INST[21].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[21] (trigEqOut[21]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[21]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[21]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[21]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_13 \N_DDR_TC.N_DDR_TC_INST[22].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[22] (trigEqOut[22]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[22]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[22]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[22]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_14 \N_DDR_TC.N_DDR_TC_INST[23].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[23] (trigEqOut[23]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[23]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[23]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[23]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_15 \N_DDR_TC.N_DDR_TC_INST[24].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[24] (trigEqOut[24]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[24]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[24]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[24]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_16 \N_DDR_TC.N_DDR_TC_INST[25].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[25] (trigEqOut[25]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[25]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[25]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[25]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_17 \N_DDR_TC.N_DDR_TC_INST[26].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[26] (trigEqOut[26]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[26]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[26]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[26]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_18 \N_DDR_TC.N_DDR_TC_INST[27].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[27] (trigEqOut[27]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[27]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[27]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[27]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_19 \N_DDR_TC.N_DDR_TC_INST[28].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[28] (trigEqOut[28]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[28]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[28]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[28]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_20 \N_DDR_TC.N_DDR_TC_INST[29].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[29] (trigEqOut[29]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[29]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[29]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[29]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_21 \N_DDR_TC.N_DDR_TC_INST[2].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[2] (trigEqOut[2]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[2]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[2]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[2]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_22 \N_DDR_TC.N_DDR_TC_INST[30].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[30] (trigEqOut[30]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[30]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[30]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[30]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_23 \N_DDR_TC.N_DDR_TC_INST[31].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[31] (trigEqOut[31]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[31]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[31]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[31]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_24 \N_DDR_TC.N_DDR_TC_INST[3].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[3] (trigEqOut[3]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[3]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[3]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[3]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_25 \N_DDR_TC.N_DDR_TC_INST[4].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[4] (trigEqOut[4]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[4]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[4]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[4]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_26 \N_DDR_TC.N_DDR_TC_INST[5].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[5] (trigEqOut[5]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[5]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[5]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[5]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_27 \N_DDR_TC.N_DDR_TC_INST[6].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[6] (trigEqOut[6]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[6]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[6]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[6]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_28 \N_DDR_TC.N_DDR_TC_INST[7].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[7] (trigEqOut[7]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[7]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[7]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[7]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_29 \N_DDR_TC.N_DDR_TC_INST[8].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[8] (trigEqOut[8]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[8]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[8]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[8]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_30 \N_DDR_TC.N_DDR_TC_INST[9].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[9] (trigEqOut[9]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[9]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[9]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[9]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_31 \STRG_QUAL.U_STRG_QUAL
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.clk(out),
.out(cap_strg_qual),
.\parallel_dout_reg[15] (\parallel_dout_reg[15] ),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.shift_en_reg(shift_en_reg));
FDRE \TRIGGER_EQ_reg[0]
(.C(out),
.CE(1'b1),
.D(trigEqOut[0]),
.Q(basic_trigger_reg),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[10]
(.C(out),
.CE(1'b1),
.D(trigEqOut[10]),
.Q(\TRIGGER_EQ_reg_n_0_[10] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[11]
(.C(out),
.CE(1'b1),
.D(trigEqOut[11]),
.Q(\TRIGGER_EQ_reg_n_0_[11] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[12]
(.C(out),
.CE(1'b1),
.D(trigEqOut[12]),
.Q(\TRIGGER_EQ_reg_n_0_[12] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[13]
(.C(out),
.CE(1'b1),
.D(trigEqOut[13]),
.Q(\TRIGGER_EQ_reg_n_0_[13] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[14]
(.C(out),
.CE(1'b1),
.D(trigEqOut[14]),
.Q(\TRIGGER_EQ_reg_n_0_[14] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[15]
(.C(out),
.CE(1'b1),
.D(trigEqOut[15]),
.Q(\TRIGGER_EQ_reg_n_0_[15] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[16]
(.C(out),
.CE(1'b1),
.D(trigEqOut[16]),
.Q(data0),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[17]
(.C(out),
.CE(1'b1),
.D(trigEqOut[17]),
.Q(data1),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[18]
(.C(out),
.CE(1'b1),
.D(trigEqOut[18]),
.Q(data2),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[19]
(.C(out),
.CE(1'b1),
.D(trigEqOut[19]),
.Q(data3),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[1]
(.C(out),
.CE(1'b1),
.D(trigEqOut[1]),
.Q(\TRIGGER_EQ_reg_n_0_[1] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[20]
(.C(out),
.CE(1'b1),
.D(trigEqOut[20]),
.Q(data4),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[21]
(.C(out),
.CE(1'b1),
.D(trigEqOut[21]),
.Q(data5),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[22]
(.C(out),
.CE(1'b1),
.D(trigEqOut[22]),
.Q(data6),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[23]
(.C(out),
.CE(1'b1),
.D(trigEqOut[23]),
.Q(data7),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[24]
(.C(out),
.CE(1'b1),
.D(trigEqOut[24]),
.Q(data8),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[25]
(.C(out),
.CE(1'b1),
.D(trigEqOut[25]),
.Q(data9),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[26]
(.C(out),
.CE(1'b1),
.D(trigEqOut[26]),
.Q(data10),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[27]
(.C(out),
.CE(1'b1),
.D(trigEqOut[27]),
.Q(data11),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[28]
(.C(out),
.CE(1'b1),
.D(trigEqOut[28]),
.Q(data12),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[29]
(.C(out),
.CE(1'b1),
.D(trigEqOut[29]),
.Q(data13),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[2]
(.C(out),
.CE(1'b1),
.D(trigEqOut[2]),
.Q(\TRIGGER_EQ_reg_n_0_[2] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[30]
(.C(out),
.CE(1'b1),
.D(trigEqOut[30]),
.Q(data14),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[31]
(.C(out),
.CE(1'b1),
.D(trigEqOut[31]),
.Q(data15),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[3]
(.C(out),
.CE(1'b1),
.D(trigEqOut[3]),
.Q(\TRIGGER_EQ_reg_n_0_[3] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[4]
(.C(out),
.CE(1'b1),
.D(trigEqOut[4]),
.Q(\TRIGGER_EQ_reg_n_0_[4] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[5]
(.C(out),
.CE(1'b1),
.D(trigEqOut[5]),
.Q(\TRIGGER_EQ_reg_n_0_[5] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[6]
(.C(out),
.CE(1'b1),
.D(trigEqOut[6]),
.Q(\TRIGGER_EQ_reg_n_0_[6] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[7]
(.C(out),
.CE(1'b1),
.D(trigEqOut[7]),
.Q(\TRIGGER_EQ_reg_n_0_[7] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[8]
(.C(out),
.CE(1'b1),
.D(trigEqOut[8]),
.Q(\TRIGGER_EQ_reg_n_0_[8] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[9]
(.C(out),
.CE(1'b1),
.D(trigEqOut[9]),
.Q(\TRIGGER_EQ_reg_n_0_[9] ),
.R(Q[2]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trig_match U_TM
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(Q[0]),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_10
(.I0(\TRIGGER_EQ_reg_n_0_[11] ),
.I1(\TRIGGER_EQ_reg_n_0_[10] ),
.I2(\current_state_reg[1] ),
.I3(\TRIGGER_EQ_reg_n_0_[9] ),
.I4(\current_state_reg[0] ),
.I5(\TRIGGER_EQ_reg_n_0_[8] ),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_10_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_11
(.I0(\TRIGGER_EQ_reg_n_0_[15] ),
.I1(\TRIGGER_EQ_reg_n_0_[14] ),
.I2(\current_state_reg[1] ),
.I3(\TRIGGER_EQ_reg_n_0_[13] ),
.I4(\current_state_reg[0] ),
.I5(\TRIGGER_EQ_reg_n_0_[12] ),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_11_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_12
(.I0(data3),
.I1(data2),
.I2(\current_state_reg[1] ),
.I3(data1),
.I4(\current_state_reg[0] ),
.I5(data0),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_12_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_13
(.I0(data7),
.I1(data6),
.I2(\current_state_reg[1] ),
.I3(data5),
.I4(\current_state_reg[0] ),
.I5(data4),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_13_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_14
(.I0(data11),
.I1(data10),
.I2(\current_state_reg[1] ),
.I3(data9),
.I4(\current_state_reg[0] ),
.I5(data8),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_14_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_15
(.I0(data15),
.I1(data14),
.I2(\current_state_reg[1] ),
.I3(data13),
.I4(\current_state_reg[0] ),
.I5(data12),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_15_n_0));
MUXF8 fsm_mem_data_reg_r1_0_63_0_2_i_2
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_4_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_5_n_0),
.O(ADDRA[1]),
.S(\current_state_reg[3] ));
MUXF8 fsm_mem_data_reg_r1_0_63_0_2_i_3
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_6_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_7_n_0),
.O(ADDRA[0]),
.S(\current_state_reg[3] ));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_4
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_8_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_9_n_0),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_4_n_0),
.S(\current_state_reg[2] ));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_5
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_10_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_11_n_0),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_5_n_0),
.S(\current_state_reg[2] ));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_6
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_12_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_13_n_0),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_6_n_0),
.S(\current_state_reg[2] ));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_7
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_14_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_15_n_0),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_7_n_0),
.S(\current_state_reg[2] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_8
(.I0(\TRIGGER_EQ_reg_n_0_[3] ),
.I1(\TRIGGER_EQ_reg_n_0_[2] ),
.I2(\current_state_reg[1] ),
.I3(\TRIGGER_EQ_reg_n_0_[1] ),
.I4(\current_state_reg[0] ),
.I5(basic_trigger_reg),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_8_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_9
(.I0(\TRIGGER_EQ_reg_n_0_[7] ),
.I1(\TRIGGER_EQ_reg_n_0_[6] ),
.I2(\current_state_reg[1] ),
.I3(\TRIGGER_EQ_reg_n_0_[5] ),
.I4(\current_state_reg[0] ),
.I5(\TRIGGER_EQ_reg_n_0_[4] ),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_9_n_0));
FDRE shift_cap_strg_qual_reg
(.C(out),
.CE(1'b1),
.D(cap_strg_qual),
.Q(shift_cap_strg_qual),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trigger
(\parallel_dout_reg[15] ,
mu_config_cs_serial_input,
tc_config_cs_serial_input,
capture_strg_qual,
ADDRA,
basic_trigger_reg,
shift_en_reg,
s_dclk_o,
qual_strg_config_cs_serial_output,
mu_config_cs_shift_en,
mu_config_cs_serial_output,
tc_config_cs_shift_en,
tc_config_cs_serial_output,
out,
Q,
probe_data,
\current_state_reg[3] ,
\current_state_reg[2] ,
\current_state_reg[1] ,
\current_state_reg[0] ); |
output [0:0]\parallel_dout_reg[15] ;
output [9:0]mu_config_cs_serial_input;
output [31:0]tc_config_cs_serial_input;
output capture_strg_qual;
output [1:0]ADDRA;
output [0:0]basic_trigger_reg;
input [0:0]shift_en_reg;
input s_dclk_o;
input qual_strg_config_cs_serial_output;
input [9:0]mu_config_cs_shift_en;
input [9:0]mu_config_cs_serial_output;
input [31:0]tc_config_cs_shift_en;
input [31:0]tc_config_cs_serial_output;
input out;
input [2:0]Q;
input [4:0]probe_data;
input \current_state_reg[3] ;
input \current_state_reg[2] ;
input \current_state_reg[1] ;
input \current_state_reg[0] ;
wire [1:0]ADDRA;
wire [2:0]Q;
wire \TRIGGER_EQ_reg_n_0_[10] ;
wire \TRIGGER_EQ_reg_n_0_[11] ;
wire \TRIGGER_EQ_reg_n_0_[12] ;
wire \TRIGGER_EQ_reg_n_0_[13] ;
wire \TRIGGER_EQ_reg_n_0_[14] ;
wire \TRIGGER_EQ_reg_n_0_[15] ;
wire \TRIGGER_EQ_reg_n_0_[1] ;
wire \TRIGGER_EQ_reg_n_0_[2] ;
wire \TRIGGER_EQ_reg_n_0_[3] ;
wire \TRIGGER_EQ_reg_n_0_[4] ;
wire \TRIGGER_EQ_reg_n_0_[5] ;
wire \TRIGGER_EQ_reg_n_0_[6] ;
wire \TRIGGER_EQ_reg_n_0_[7] ;
wire \TRIGGER_EQ_reg_n_0_[8] ;
wire \TRIGGER_EQ_reg_n_0_[9] ;
wire [9:0]\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ;
wire [0:0]basic_trigger_reg;
wire cap_strg_qual;
wire capture_strg_qual;
wire \current_state_reg[0] ;
wire \current_state_reg[1] ;
wire \current_state_reg[2] ;
wire \current_state_reg[3] ;
wire data0;
wire data1;
wire data10;
wire data11;
wire data12;
wire data13;
wire data14;
wire data15;
wire data2;
wire data3;
wire data4;
wire data5;
wire data6;
wire data7;
wire data8;
wire data9;
wire fsm_mem_data_reg_r1_0_63_0_2_i_10_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_11_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_12_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_13_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_14_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_15_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_4_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_5_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_6_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_7_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_8_n_0;
wire fsm_mem_data_reg_r1_0_63_0_2_i_9_n_0;
wire [9:0]mu_config_cs_serial_input;
wire [9:0]mu_config_cs_serial_output;
wire [9:0]mu_config_cs_shift_en;
wire out;
wire [0:0]\parallel_dout_reg[15] ;
wire [4:0]probe_data;
wire qual_strg_config_cs_serial_output;
wire s_dclk_o;
wire shift_cap_strg_qual;
wire [0:0]shift_en_reg;
wire [31:0]tc_config_cs_serial_input;
wire [31:0]tc_config_cs_serial_output;
wire [31:0]tc_config_cs_shift_en;
wire [15:0]trigCondIn_temp;
wire [31:0]trigEqOut;
FDRE CAP_QUAL_STRG_reg
(.C(out),
.CE(1'b1),
.D(shift_cap_strg_qual),
.Q(capture_strg_qual),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match \N_DDR_TC.N_DDR_TC_INST[0].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[0] (trigEqOut[0]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[0]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[0]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[0]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_0 \N_DDR_TC.N_DDR_TC_INST[10].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[10] (trigEqOut[10]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[10]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[10]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[10]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_1 \N_DDR_TC.N_DDR_TC_INST[11].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[11] (trigEqOut[11]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[11]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[11]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[11]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_2 \N_DDR_TC.N_DDR_TC_INST[12].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[12] (trigEqOut[12]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[12]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[12]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[12]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_3 \N_DDR_TC.N_DDR_TC_INST[13].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[13] (trigEqOut[13]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[13]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[13]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[13]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_4 \N_DDR_TC.N_DDR_TC_INST[14].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[14] (trigEqOut[14]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[14]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[14]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[14]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_5 \N_DDR_TC.N_DDR_TC_INST[15].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[15] (trigEqOut[15]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[15]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[15]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[15]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_6 \N_DDR_TC.N_DDR_TC_INST[16].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[16] (trigEqOut[16]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[16]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[16]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[16]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_7 \N_DDR_TC.N_DDR_TC_INST[17].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[17] (trigEqOut[17]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[17]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[17]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[17]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_8 \N_DDR_TC.N_DDR_TC_INST[18].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[18] (trigEqOut[18]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[18]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[18]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[18]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_9 \N_DDR_TC.N_DDR_TC_INST[19].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[19] (trigEqOut[19]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[19]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[19]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[19]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_10 \N_DDR_TC.N_DDR_TC_INST[1].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[1] (trigEqOut[1]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[1]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[1]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[1]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_11 \N_DDR_TC.N_DDR_TC_INST[20].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[20] (trigEqOut[20]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[20]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[20]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[20]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_12 \N_DDR_TC.N_DDR_TC_INST[21].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[21] (trigEqOut[21]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[21]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[21]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[21]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_13 \N_DDR_TC.N_DDR_TC_INST[22].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[22] (trigEqOut[22]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[22]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[22]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[22]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_14 \N_DDR_TC.N_DDR_TC_INST[23].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[23] (trigEqOut[23]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[23]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[23]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[23]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_15 \N_DDR_TC.N_DDR_TC_INST[24].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[24] (trigEqOut[24]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[24]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[24]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[24]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_16 \N_DDR_TC.N_DDR_TC_INST[25].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[25] (trigEqOut[25]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[25]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[25]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[25]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_17 \N_DDR_TC.N_DDR_TC_INST[26].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[26] (trigEqOut[26]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[26]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[26]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[26]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_18 \N_DDR_TC.N_DDR_TC_INST[27].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[27] (trigEqOut[27]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[27]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[27]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[27]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_19 \N_DDR_TC.N_DDR_TC_INST[28].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[28] (trigEqOut[28]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[28]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[28]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[28]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_20 \N_DDR_TC.N_DDR_TC_INST[29].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[29] (trigEqOut[29]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[29]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[29]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[29]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_21 \N_DDR_TC.N_DDR_TC_INST[2].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[2] (trigEqOut[2]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[2]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[2]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[2]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_22 \N_DDR_TC.N_DDR_TC_INST[30].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[30] (trigEqOut[30]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[30]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[30]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[30]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_23 \N_DDR_TC.N_DDR_TC_INST[31].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[31] (trigEqOut[31]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[31]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[31]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[31]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_24 \N_DDR_TC.N_DDR_TC_INST[3].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[3] (trigEqOut[3]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[3]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[3]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[3]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_25 \N_DDR_TC.N_DDR_TC_INST[4].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[4] (trigEqOut[4]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[4]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[4]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[4]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_26 \N_DDR_TC.N_DDR_TC_INST[5].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[5] (trigEqOut[5]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[5]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[5]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[5]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_27 \N_DDR_TC.N_DDR_TC_INST[6].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[6] (trigEqOut[6]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[6]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[6]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[6]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_28 \N_DDR_TC.N_DDR_TC_INST[7].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[7] (trigEqOut[7]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[7]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[7]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[7]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_29 \N_DDR_TC.N_DDR_TC_INST[8].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[8] (trigEqOut[8]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[8]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[8]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[8]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_30 \N_DDR_TC.N_DDR_TC_INST[9].U_TC
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.\TRIGGER_EQ_reg[9] (trigEqOut[9]),
.out(out),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input[9]),
.tc_config_cs_serial_output(tc_config_cs_serial_output[9]),
.tc_config_cs_shift_en(tc_config_cs_shift_en[9]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_31 \STRG_QUAL.U_STRG_QUAL
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(\allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst/all_dly2 ),
.clk(out),
.out(cap_strg_qual),
.\parallel_dout_reg[15] (\parallel_dout_reg[15] ),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.\reset_out_reg[3] (Q[1]),
.s_dclk_o(s_dclk_o),
.shift_en_reg(shift_en_reg));
FDRE \TRIGGER_EQ_reg[0]
(.C(out),
.CE(1'b1),
.D(trigEqOut[0]),
.Q(basic_trigger_reg),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[10]
(.C(out),
.CE(1'b1),
.D(trigEqOut[10]),
.Q(\TRIGGER_EQ_reg_n_0_[10] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[11]
(.C(out),
.CE(1'b1),
.D(trigEqOut[11]),
.Q(\TRIGGER_EQ_reg_n_0_[11] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[12]
(.C(out),
.CE(1'b1),
.D(trigEqOut[12]),
.Q(\TRIGGER_EQ_reg_n_0_[12] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[13]
(.C(out),
.CE(1'b1),
.D(trigEqOut[13]),
.Q(\TRIGGER_EQ_reg_n_0_[13] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[14]
(.C(out),
.CE(1'b1),
.D(trigEqOut[14]),
.Q(\TRIGGER_EQ_reg_n_0_[14] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[15]
(.C(out),
.CE(1'b1),
.D(trigEqOut[15]),
.Q(\TRIGGER_EQ_reg_n_0_[15] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[16]
(.C(out),
.CE(1'b1),
.D(trigEqOut[16]),
.Q(data0),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[17]
(.C(out),
.CE(1'b1),
.D(trigEqOut[17]),
.Q(data1),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[18]
(.C(out),
.CE(1'b1),
.D(trigEqOut[18]),
.Q(data2),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[19]
(.C(out),
.CE(1'b1),
.D(trigEqOut[19]),
.Q(data3),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[1]
(.C(out),
.CE(1'b1),
.D(trigEqOut[1]),
.Q(\TRIGGER_EQ_reg_n_0_[1] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[20]
(.C(out),
.CE(1'b1),
.D(trigEqOut[20]),
.Q(data4),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[21]
(.C(out),
.CE(1'b1),
.D(trigEqOut[21]),
.Q(data5),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[22]
(.C(out),
.CE(1'b1),
.D(trigEqOut[22]),
.Q(data6),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[23]
(.C(out),
.CE(1'b1),
.D(trigEqOut[23]),
.Q(data7),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[24]
(.C(out),
.CE(1'b1),
.D(trigEqOut[24]),
.Q(data8),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[25]
(.C(out),
.CE(1'b1),
.D(trigEqOut[25]),
.Q(data9),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[26]
(.C(out),
.CE(1'b1),
.D(trigEqOut[26]),
.Q(data10),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[27]
(.C(out),
.CE(1'b1),
.D(trigEqOut[27]),
.Q(data11),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[28]
(.C(out),
.CE(1'b1),
.D(trigEqOut[28]),
.Q(data12),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[29]
(.C(out),
.CE(1'b1),
.D(trigEqOut[29]),
.Q(data13),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[2]
(.C(out),
.CE(1'b1),
.D(trigEqOut[2]),
.Q(\TRIGGER_EQ_reg_n_0_[2] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[30]
(.C(out),
.CE(1'b1),
.D(trigEqOut[30]),
.Q(data14),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[31]
(.C(out),
.CE(1'b1),
.D(trigEqOut[31]),
.Q(data15),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[3]
(.C(out),
.CE(1'b1),
.D(trigEqOut[3]),
.Q(\TRIGGER_EQ_reg_n_0_[3] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[4]
(.C(out),
.CE(1'b1),
.D(trigEqOut[4]),
.Q(\TRIGGER_EQ_reg_n_0_[4] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[5]
(.C(out),
.CE(1'b1),
.D(trigEqOut[5]),
.Q(\TRIGGER_EQ_reg_n_0_[5] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[6]
(.C(out),
.CE(1'b1),
.D(trigEqOut[6]),
.Q(\TRIGGER_EQ_reg_n_0_[6] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[7]
(.C(out),
.CE(1'b1),
.D(trigEqOut[7]),
.Q(\TRIGGER_EQ_reg_n_0_[7] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[8]
(.C(out),
.CE(1'b1),
.D(trigEqOut[8]),
.Q(\TRIGGER_EQ_reg_n_0_[8] ),
.R(Q[2]));
FDRE \TRIGGER_EQ_reg[9]
(.C(out),
.CE(1'b1),
.D(trigEqOut[9]),
.Q(\TRIGGER_EQ_reg_n_0_[9] ),
.R(Q[2]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ila_v6_2_1_ila_trig_match U_TM
(.D({trigCondIn_temp[15:14],trigCondIn_temp[11:8],trigCondIn_temp[3:0]}),
.Q(Q[0]),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_10
(.I0(\TRIGGER_EQ_reg_n_0_[11] ),
.I1(\TRIGGER_EQ_reg_n_0_[10] ),
.I2(\current_state_reg[1] ),
.I3(\TRIGGER_EQ_reg_n_0_[9] ),
.I4(\current_state_reg[0] ),
.I5(\TRIGGER_EQ_reg_n_0_[8] ),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_10_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_11
(.I0(\TRIGGER_EQ_reg_n_0_[15] ),
.I1(\TRIGGER_EQ_reg_n_0_[14] ),
.I2(\current_state_reg[1] ),
.I3(\TRIGGER_EQ_reg_n_0_[13] ),
.I4(\current_state_reg[0] ),
.I5(\TRIGGER_EQ_reg_n_0_[12] ),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_11_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_12
(.I0(data3),
.I1(data2),
.I2(\current_state_reg[1] ),
.I3(data1),
.I4(\current_state_reg[0] ),
.I5(data0),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_12_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_13
(.I0(data7),
.I1(data6),
.I2(\current_state_reg[1] ),
.I3(data5),
.I4(\current_state_reg[0] ),
.I5(data4),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_13_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_14
(.I0(data11),
.I1(data10),
.I2(\current_state_reg[1] ),
.I3(data9),
.I4(\current_state_reg[0] ),
.I5(data8),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_14_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_15
(.I0(data15),
.I1(data14),
.I2(\current_state_reg[1] ),
.I3(data13),
.I4(\current_state_reg[0] ),
.I5(data12),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_15_n_0));
MUXF8 fsm_mem_data_reg_r1_0_63_0_2_i_2
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_4_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_5_n_0),
.O(ADDRA[1]),
.S(\current_state_reg[3] ));
MUXF8 fsm_mem_data_reg_r1_0_63_0_2_i_3
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_6_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_7_n_0),
.O(ADDRA[0]),
.S(\current_state_reg[3] ));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_4
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_8_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_9_n_0),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_4_n_0),
.S(\current_state_reg[2] ));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_5
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_10_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_11_n_0),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_5_n_0),
.S(\current_state_reg[2] ));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_6
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_12_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_13_n_0),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_6_n_0),
.S(\current_state_reg[2] ));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_7
(.I0(fsm_mem_data_reg_r1_0_63_0_2_i_14_n_0),
.I1(fsm_mem_data_reg_r1_0_63_0_2_i_15_n_0),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_7_n_0),
.S(\current_state_reg[2] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_8
(.I0(\TRIGGER_EQ_reg_n_0_[3] ),
.I1(\TRIGGER_EQ_reg_n_0_[2] ),
.I2(\current_state_reg[1] ),
.I3(\TRIGGER_EQ_reg_n_0_[1] ),
.I4(\current_state_reg[0] ),
.I5(basic_trigger_reg),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_8_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
fsm_mem_data_reg_r1_0_63_0_2_i_9
(.I0(\TRIGGER_EQ_reg_n_0_[7] ),
.I1(\TRIGGER_EQ_reg_n_0_[6] ),
.I2(\current_state_reg[1] ),
.I3(\TRIGGER_EQ_reg_n_0_[5] ),
.I4(\current_state_reg[0] ),
.I5(\TRIGGER_EQ_reg_n_0_[4] ),
.O(fsm_mem_data_reg_r1_0_63_0_2_i_9_n_0));
FDRE shift_cap_strg_qual_reg
(.C(out),
.CE(1'b1),
.D(cap_strg_qual),
.Q(shift_cap_strg_qual),
.R(1'b0));
endmodule | 8 |
2,154 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA
(\parallel_dout_reg[15] ,
out,
shift_en_reg,
s_dclk_o,
qual_strg_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]\parallel_dout_reg[15] ;
output out;
input [0:0]shift_en_reg;
input s_dclk_o;
input qual_strg_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\parallel_dout_reg[15] ;
wire qual_strg_config_cs_serial_output;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]shift_en_reg;
wire srl_q_0;
wire srl_q_1;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.shift_en_reg(shift_en_reg));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.shift_en_reg(shift_en_reg));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(\parallel_dout_reg[15] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA
(\parallel_dout_reg[15] ,
out,
shift_en_reg,
s_dclk_o,
qual_strg_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]\parallel_dout_reg[15] ;
output out;
input [0:0]shift_en_reg;
input s_dclk_o;
input qual_strg_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\parallel_dout_reg[15] ;
wire qual_strg_config_cs_serial_output;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]shift_en_reg;
wire srl_q_0;
wire srl_q_1;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.shift_en_reg(shift_en_reg));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.shift_en_reg(shift_en_reg));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(\parallel_dout_reg[15] ));
endmodule | 8 |
2,155 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_101
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_102 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_103 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_101
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_102 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_103 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,156 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_105
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_106 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_107 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_105
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_106 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_107 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,157 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_109
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_110 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_111 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_109
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_110 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_111 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,158 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_113
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_114 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_115 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_113
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_114 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_115 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,159 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_117
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_118 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_119 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_117
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_118 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_119 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,160 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_121
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_122 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_123 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_121
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_122 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_123 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,161 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_125
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_126 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_127 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_125
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_126 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_127 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,162 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_129
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_130 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_131 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_129
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_130 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_131 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,163 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_133
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_134 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_135 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_133
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_134 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_135 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,164 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_137
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_138 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_139 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_137
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_138 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_139 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,165 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_141
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_142 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_143 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_141
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_142 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_143 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,166 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_145
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_146 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_147 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_145
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_146 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_147 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,167 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_149
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_150 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_151 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_149
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_150 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_151 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,168 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_153
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_154 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_155 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_153
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_154 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_155 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,169 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_157
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_158 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_159 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_157
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_158 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_159 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,170 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_33
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_34 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_35 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_33
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_34 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_35 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,171 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_37
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_38 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_39 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_37
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_38 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_39 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,172 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_41
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_42 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_43 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_41
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_42 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_43 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,173 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_45
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_46 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_47 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_45
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_46 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_47 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,174 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_49
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_50 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_51 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_49
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_50 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_51 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,175 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_53
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_54 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_55 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_53
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_54 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_55 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,176 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_57
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_58 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_59 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_57
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_58 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_59 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,177 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_61
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_62 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_63 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_61
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_62 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_63 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,178 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_65
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_66 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_67 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_65
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_66 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_67 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,179 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_69
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_70 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_71 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_69
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_70 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_71 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,180 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_73
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_74 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_75 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_73
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_74 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_75 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,181 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_77
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_78 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_79 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_77
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_78 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_79 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,182 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_81
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_82 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_83 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_81
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_82 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_83 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,183 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_85
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_86 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_87 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_85
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_86 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_87 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,184 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_89
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_90 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_91 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_89
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_90 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_91 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,185 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_93
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_94 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_95 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_93
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_94 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_95 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,186 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_97
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk);
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_98 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_99 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_97
(tc_config_cs_serial_input,
out,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
clk); |
output [0:0]tc_config_cs_serial_input;
output out;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire all_carry_0;
wire all_carry_1;
wire clk;
wire drive_ci;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire srl_q_0;
wire srl_q_1;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_98 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
.SRL_D_I(srl_q_1),
.SRL_Q_O(srl_q_0),
.s_dclk_o(s_dclk_o),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_99 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.D(D[9:8]),
.DOUT_O(all_carry_1),
.Q(Q[9:8]),
.SRL_D_I(srl_q_1),
.clk(clk),
.out(out),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(tc_config_cs_serial_input));
endmodule | 8 |
2,187 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized1 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized0
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized1 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | 8 |
2,188 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized1
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized2 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized1
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized2 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | 8 |
2,189 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10
(SRL_Q_O,
u_wcnt_lcmp_q,
E,
S_DCLK_O,
PROBES_I,
SRL_D_I);
output SRL_Q_O;
output u_wcnt_lcmp_q;
input [0:0]E;
input S_DCLK_O;
input [29:0]PROBES_I;
input SRL_D_I;
wire [0:0]E;
wire [29:0]PROBES_I;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire all_carry_0;
wire all_carry_1;
wire drive_ci;
wire srl_q_0;
wire srl_q_1;
wire u_wcnt_lcmp_q;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.E(E),
.PROBES_I(PROBES_I[15:0]),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_hcmp_q(srl_q_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.CI_I(all_carry_1),
.E(E),
.PROBES_I(PROBES_I[29:16]),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_lcmp_q(u_wcnt_lcmp_q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(E),
.CLK(S_DCLK_O),
.D(srl_q_0),
.Q(drive_ci),
.Q31(SRL_Q_O));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10
(SRL_Q_O,
u_wcnt_lcmp_q,
E,
S_DCLK_O,
PROBES_I,
SRL_D_I); |
output SRL_Q_O;
output u_wcnt_lcmp_q;
input [0:0]E;
input S_DCLK_O;
input [29:0]PROBES_I;
input SRL_D_I;
wire [0:0]E;
wire [29:0]PROBES_I;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire all_carry_0;
wire all_carry_1;
wire drive_ci;
wire srl_q_0;
wire srl_q_1;
wire u_wcnt_lcmp_q;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.E(E),
.PROBES_I(PROBES_I[15:0]),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_hcmp_q(srl_q_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.CI_I(all_carry_1),
.E(E),
.PROBES_I(PROBES_I[29:16]),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_lcmp_q(u_wcnt_lcmp_q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(E),
.CLK(S_DCLK_O),
.D(srl_q_0),
.Q(drive_ci),
.Q31(SRL_Q_O));
endmodule | 8 |
2,190 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10_187
(\I_YESLUT6.I_YES_OREG.O_reg_reg ,
u_wcnt_hcmp_q,
E,
S_DCLK_O,
PROBES_I,
SRL_D_I);
output \I_YESLUT6.I_YES_OREG.O_reg_reg ;
output u_wcnt_hcmp_q;
input [0:0]E;
input S_DCLK_O;
input [29:0]PROBES_I;
input SRL_D_I;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [29:0]PROBES_I;
wire SRL_D_I;
wire S_DCLK_O;
wire all_carry_0;
wire all_carry_1;
wire drive_ci;
wire srl_q_0;
wire srl_q_1;
wire u_wcnt_hcmp_q;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11_188 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (srl_q_0),
.PROBES_I(PROBES_I[15:0]),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12_189 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.CI_I(all_carry_1),
.E(E),
.PROBES_I(PROBES_I[29:16]),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_hcmp_q(u_wcnt_hcmp_q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(E),
.CLK(S_DCLK_O),
.D(srl_q_0),
.Q(drive_ci),
.Q31(\I_YESLUT6.I_YES_OREG.O_reg_reg ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10_187
(\I_YESLUT6.I_YES_OREG.O_reg_reg ,
u_wcnt_hcmp_q,
E,
S_DCLK_O,
PROBES_I,
SRL_D_I); |
output \I_YESLUT6.I_YES_OREG.O_reg_reg ;
output u_wcnt_hcmp_q;
input [0:0]E;
input S_DCLK_O;
input [29:0]PROBES_I;
input SRL_D_I;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [29:0]PROBES_I;
wire SRL_D_I;
wire S_DCLK_O;
wire all_carry_0;
wire all_carry_1;
wire drive_ci;
wire srl_q_0;
wire srl_q_1;
wire u_wcnt_hcmp_q;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11_188 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (srl_q_0),
.PROBES_I(PROBES_I[15:0]),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12_189 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.CI_I(all_carry_1),
.E(E),
.PROBES_I(PROBES_I[29:16]),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_hcmp_q(u_wcnt_hcmp_q));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(E),
.CLK(S_DCLK_O),
.D(srl_q_0),
.Q(drive_ci),
.Q31(\I_YESLUT6.I_YES_OREG.O_reg_reg ));
endmodule | 8 |
2,191 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10_195
(SRL_Q_O,
DOUT_O,
E,
S_DCLK_O,
PROBES_I,
SRL_D_I);
output SRL_Q_O;
output DOUT_O;
input [0:0]E;
input S_DCLK_O;
input [29:0]PROBES_I;
input SRL_D_I;
wire DOUT_O;
wire [0:0]E;
wire [29:0]PROBES_I;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire all_carry_0;
wire all_carry_1;
wire drive_ci;
wire srl_q_0;
wire srl_q_1;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11_196 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.E(E),
.PROBES_I(PROBES_I[15:0]),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O),
.\iwcnt_reg[0] (srl_q_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12_197 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.CI_I(all_carry_1),
.DOUT_O(DOUT_O),
.E(E),
.PROBES_I(PROBES_I[29:16]),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(E),
.CLK(S_DCLK_O),
.D(srl_q_0),
.Q(drive_ci),
.Q31(SRL_Q_O));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized10_195
(SRL_Q_O,
DOUT_O,
E,
S_DCLK_O,
PROBES_I,
SRL_D_I); |
output SRL_Q_O;
output DOUT_O;
input [0:0]E;
input S_DCLK_O;
input [29:0]PROBES_I;
input SRL_D_I;
wire DOUT_O;
wire [0:0]E;
wire [29:0]PROBES_I;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire all_carry_0;
wire all_carry_1;
wire drive_ci;
wire srl_q_0;
wire srl_q_1;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized11_196 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CI_I(all_carry_0),
.DOUT_O(all_carry_1),
.E(E),
.PROBES_I(PROBES_I[15:0]),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O),
.\iwcnt_reg[0] (srl_q_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized12_197 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE
(.CI_I(all_carry_1),
.DOUT_O(DOUT_O),
.E(E),
.PROBES_I(PROBES_I[29:16]),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(srl_q_1),
.S_DCLK_O(S_DCLK_O));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(E),
.CLK(S_DCLK_O),
.D(srl_q_0),
.Q(drive_ci),
.Q31(SRL_Q_O));
endmodule | 8 |
2,192 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized2
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized3 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized2
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized3 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | 8 |
2,193 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized3
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized4 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized3
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized4 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | 8 |
2,194 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized4
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized5 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized4
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized5 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | 8 |
2,195 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized5
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized6 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized5
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized6 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | 8 |
2,196 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized6
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized7 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized6
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized7 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | 8 |
2,197 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized7
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized8 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized7
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized8 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | 8 |
2,198 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized8
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized9 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized8
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized9 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | 8 |
2,199 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized9
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk);
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized10 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA__parameterized9
(mu_config_cs_serial_input,
out,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
clk); |
output [0:0]mu_config_cs_serial_input;
output out;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input clk;
wire [0:0]Q;
wire all_carry_0;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
wire clk;
wire drive_ci;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
wire srl_q_0;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized10 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE
(.CO(all_carry_0),
.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(clk),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(out),
.s_dclk_o(s_dclk_o),
.srl_q_0(srl_q_0));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(1'b0),
.CO({all_carry_0,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "CFGLUT5" *)
(* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srl_drive
(.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
.CE(mu_config_cs_shift_en),
.CLK(s_dclk_o),
.D(srl_q_0),
.Q(drive_ci),
.Q31(mu_config_cs_serial_input));
endmodule | 8 |
2,200 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice
(SRL_Q_O,
DOUT_O,
SRL_D_I,
shift_en_reg,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]shift_en_reg;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]shift_en_reg;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice
(SRL_Q_O,
DOUT_O,
SRL_D_I,
shift_en_reg,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]shift_en_reg;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]shift_en_reg;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,201 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_102
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_102
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,202 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_106
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_106
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,203 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_110
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_110
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,204 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_114
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_114
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,205 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_118
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_118
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,206 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_122
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_122
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,207 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_126
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_126
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,208 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_130
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_130
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,209 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_134
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_134
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,210 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_138
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_138
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,211 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_142
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_142
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,212 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_146
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_146
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,213 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_150
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_150
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,214 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_154
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_154
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,215 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_158
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_158
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,216 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_34
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_34
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,217 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_38
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_38
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,218 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_42
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_42
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,219 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_46
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_46
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,220 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_50
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_50
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,221 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_54
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_54
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,222 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_58
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_58
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,223 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_62
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_62
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,224 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_66
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_66
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,225 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_70
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_70
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,226 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_74
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_74
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,227 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_78
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_78
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,228 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_82
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_82
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,229 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_86
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_86
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,230 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_90
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_90
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,231 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_94
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_94
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,232 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_98
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I);
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice_98
(SRL_Q_O,
DOUT_O,
SRL_D_I,
tc_config_cs_shift_en,
s_dclk_o,
SRL_A_I,
CI_I); |
output SRL_Q_O;
output DOUT_O;
input SRL_D_I;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [15:0]SRL_A_I;
input CI_I;
wire CI_I;
(* async_reg = "true" *) wire DOUT_O;
wire [15:0]SRL_A_I;
wire SRL_D_I;
wire SRL_Q_O;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire [3:0]mux_di;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(CI_I),
.CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_Q_O),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[0]),
.I1(SRL_A_I[1]),
.I2(SRL_A_I[2]),
.I3(SRL_A_I[3]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[4]),
.I1(SRL_A_I[5]),
.I2(SRL_A_I[6]),
.I3(SRL_A_I[7]),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[8]),
.I1(SRL_A_I[9]),
.I2(SRL_A_I[10]),
.I3(SRL_A_I[11]),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(SRL_D_I),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(SRL_A_I[12]),
.I1(SRL_A_I[13]),
.I2(SRL_A_I[14]),
.I3(SRL_A_I[15]),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,233 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0
(SRL_D_I,
out,
qual_strg_config_cs_serial_output,
shift_en_reg,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input qual_strg_config_cs_serial_output;
input [0:0]shift_en_reg;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire qual_strg_config_cs_serial_output;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]shift_en_reg;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(qual_strg_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0
(SRL_D_I,
out,
qual_strg_config_cs_serial_output,
shift_en_reg,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input qual_strg_config_cs_serial_output;
input [0:0]shift_en_reg;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire qual_strg_config_cs_serial_output;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]shift_en_reg;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(qual_strg_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(shift_en_reg),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,234 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_103
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_103
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,235 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_107
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_107
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,236 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_111
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_111
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,237 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_115
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_115
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,238 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_119
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_119
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,239 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_123
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_123
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,240 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_127
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_127
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
2,241 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_131
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk);
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_all_typeA_slice__parameterized0_131
(SRL_D_I,
out,
tc_config_cs_serial_output,
tc_config_cs_shift_en,
s_dclk_o,
D,
Q,
DOUT_O,
\reset_out_reg[3] ,
clk); |
output SRL_D_I;
output out;
input [0:0]tc_config_cs_serial_output;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [1:0]D;
input [1:0]Q;
input DOUT_O;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [1:0]D;
wire DOUT_O;
wire [1:0]Q;
wire SRL_D_I;
wire cfg_data_0;
wire cfg_data_1;
wire cfg_data_2;
wire clk;
wire [3:0]mux_di;
wire [3:3]muxcy_lo;
(* async_reg = "true" *) wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [3:0]sel;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg
(.C(clk),
.CE(1'b1),
.D(muxcy_lo),
.Q(out),
.R(\reset_out_reg[3] ));
(* BOX_TYPE = "PRIMITIVE" *)
CARRY4 u_carry4_inst
(.CI(DOUT_O),
.CO({muxcy_lo,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
.CYINIT(1'b0),
.DI(mux_di),
.O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
.S(sel));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlA
(.CDI(cfg_data_0),
.CDO(SRL_D_I),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(D[0]),
.I1(Q[0]),
.I2(D[1]),
.I3(Q[1]),
.I4(1'b1),
.O5(mux_di[0]),
.O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlB
(.CDI(cfg_data_1),
.CDO(cfg_data_0),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[1]),
.O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlC
(.CDI(cfg_data_2),
.CDO(cfg_data_1),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[2]),
.O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *)
CFGLUT5 #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
u_srlD
(.CDI(tc_config_cs_serial_output),
.CDO(cfg_data_2),
.CE(tc_config_cs_shift_en),
.CLK(s_dclk_o),
.I0(1'b1),
.I1(1'b1),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.O5(mux_di[3]),
.O6(sel[3]));
endmodule | 8 |
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