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2,342 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_generic_memrd
(E,
Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
ADDRBWRADDR,
enb_array,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
\xsdb_reg_reg[15] ,
s_dclk_o,
SR,
D,
read_data_en,
read_reset_addr,
\trace_data_ack_reg[1] );
output [0:0]E;
output [14:0]Q;
output [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [0:0]ADDRBWRADDR;
output [7:0]enb_array;
output [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
output [15:0]\xsdb_reg_reg[15] ;
input s_dclk_o;
input [0:0]SR;
input [52:0]D;
input read_data_en;
input [14:0]read_reset_addr;
input [0:0]\trace_data_ack_reg[1] ;
wire [0:0]ADDRBWRADDR;
wire [52:0]D;
wire [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
wire [0:0]E;
wire [14:0]Q;
wire [0:0]SR;
wire [1:0]curr_read_block;
wire \curr_read_block[0]_i_1_n_0 ;
wire \curr_read_block[1]_i_1_n_0 ;
wire \current_state[0]_i_2_n_0 ;
wire \current_state[0]_i_3_n_0 ;
wire \current_state[0]_i_4_n_0 ;
wire \current_state[1]_i_2__10_n_0 ;
wire \current_state[3]_i_2__47_n_0 ;
wire \current_state[4]_i_3_n_0 ;
wire \current_state[6]_i_2_n_0 ;
wire \current_state_reg_n_0_[0] ;
wire \current_state_reg_n_0_[1] ;
wire \current_state_reg_n_0_[2] ;
wire \current_state_reg_n_0_[3] ;
wire \current_state_reg_n_0_[4] ;
wire \current_state_reg_n_0_[5] ;
wire \current_state_reg_n_0_[6] ;
wire [7:0]enb_array;
wire [52:0]input_data;
wire mahesh_temp;
wire \multiple_enable_latency.enable_out_reg[2]_srl3_n_0 ;
wire \multiple_read_latency.read_enable_out_reg[2]_srl3_n_0 ;
wire [6:0]next_state;
wire p_0_in;
wire read_addr;
wire read_addr0_carry__0_i_1_n_0;
wire read_addr0_carry__0_i_2_n_0;
wire read_addr0_carry__0_i_3_n_0;
wire read_addr0_carry__0_i_4_n_0;
wire read_addr0_carry__0_n_0;
wire read_addr0_carry__0_n_1;
wire read_addr0_carry__0_n_2;
wire read_addr0_carry__0_n_3;
wire read_addr0_carry__0_n_4;
wire read_addr0_carry__0_n_5;
wire read_addr0_carry__0_n_6;
wire read_addr0_carry__0_n_7;
wire read_addr0_carry__1_i_1_n_0;
wire read_addr0_carry__1_i_2_n_0;
wire read_addr0_carry__1_i_3_n_0;
wire read_addr0_carry__1_i_4_n_0;
wire read_addr0_carry__1_n_0;
wire read_addr0_carry__1_n_1;
wire read_addr0_carry__1_n_2;
wire read_addr0_carry__1_n_3;
wire read_addr0_carry__1_n_4;
wire read_addr0_carry__1_n_5;
wire read_addr0_carry__1_n_6;
wire read_addr0_carry__1_n_7;
wire read_addr0_carry__2_i_1_n_0;
wire read_addr0_carry__2_i_2_n_0;
wire read_addr0_carry__2_n_3;
wire read_addr0_carry__2_n_6;
wire read_addr0_carry__2_n_7;
wire read_addr0_carry_i_1_n_0;
wire read_addr0_carry_i_2_n_0;
wire read_addr0_carry_i_3_n_0;
wire read_addr0_carry_i_4_n_0;
wire read_addr0_carry_n_0;
wire read_addr0_carry_n_1;
wire read_addr0_carry_n_2;
wire read_addr0_carry_n_3;
wire read_addr0_carry_n_4;
wire read_addr0_carry_n_5;
wire read_addr0_carry_n_6;
wire read_addr0_carry_n_7;
wire \read_addr[0]_i_1_n_0 ;
wire \read_addr[0]_rep_i_1_n_0 ;
wire \read_addr[10]_i_1_n_0 ;
wire \read_addr[10]_rep_i_1_n_0 ;
wire \read_addr[11]_i_1_n_0 ;
wire \read_addr[11]_rep_i_1_n_0 ;
wire \read_addr[12]_i_1_n_0 ;
wire \read_addr[13]_i_1_n_0 ;
wire \read_addr[14]_i_2_n_0 ;
wire \read_addr[1]_i_1_n_0 ;
wire \read_addr[1]_rep_i_1_n_0 ;
wire \read_addr[2]_i_1_n_0 ;
wire \read_addr[2]_rep_i_1_n_0 ;
wire \read_addr[3]_i_1_n_0 ;
wire \read_addr[3]_rep_i_1_n_0 ;
wire \read_addr[4]_i_1_n_0 ;
wire \read_addr[4]_rep_i_1_n_0 ;
wire \read_addr[5]_i_1_n_0 ;
wire \read_addr[5]_rep_i_1_n_0 ;
wire \read_addr[6]_i_1_n_0 ;
wire \read_addr[6]_rep_i_1_n_0 ;
wire \read_addr[7]_i_1_n_0 ;
wire \read_addr[7]_rep_i_1_n_0 ;
wire \read_addr[8]_i_1_n_0 ;
wire \read_addr[8]_rep_i_1_n_0 ;
wire \read_addr[9]_i_1_n_0 ;
wire \read_addr[9]_rep_i_1_n_0 ;
wire read_data_en;
wire [14:0]read_reset_addr;
wire s_dclk_o;
wire [0:0]\trace_data_ack_reg[1] ;
wire [15:0]\xsdb_reg_reg[15] ;
wire [3:1]NLW_read_addr0_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_read_addr0_carry__2_O_UNCONNECTED;
LUT5 #(
.INIT(32'h0000000E))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[13]),
.I4(Q[14]),
.O(enb_array[0]));
LUT5 #(
.INIT(32'h00000E00))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[13]),
.I4(Q[14]),
.O(enb_array[2]));
LUT5 #(
.INIT(32'h00000E00))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__1
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[14]),
.I4(Q[13]),
.O(enb_array[4]));
LUT5 #(
.INIT(32'h00008880))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__2
(.I0(Q[13]),
.I1(Q[14]),
.I2(mahesh_temp),
.I3(p_0_in),
.I4(Q[12]),
.O(enb_array[6]));
LUT5 #(
.INIT(32'h000000E0))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__3
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[13]),
.I4(Q[14]),
.O(enb_array[1]));
LUT5 #(
.INIT(32'h0000E000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__4
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[13]),
.I4(Q[14]),
.O(enb_array[3]));
LUT5 #(
.INIT(32'h0000E000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__5
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[14]),
.I4(Q[13]),
.O(enb_array[5]));
LUT5 #(
.INIT(32'hE0000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__6
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[13]),
.I4(Q[14]),
.O(enb_array[7]));
LUT2 #(
.INIT(4'hE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3
(.I0(p_0_in),
.I1(mahesh_temp),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ));
(* SOFT_HLUTNM = "soft_lutpair213" *)
LUT3 #(
.INIT(8'h85))
\curr_read_block[0]_i_1
(.I0(\current_state[6]_i_2_n_0 ),
.I1(\current_state[0]_i_2_n_0 ),
.I2(curr_read_block[0]),
.O(\curr_read_block[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair213" *)
LUT4 #(
.INIT(16'hD122))
\curr_read_block[1]_i_1
(.I0(curr_read_block[0]),
.I1(\current_state[6]_i_2_n_0 ),
.I2(\current_state[0]_i_2_n_0 ),
.I3(curr_read_block[1]),
.O(\curr_read_block[1]_i_1_n_0 ));
FDRE \curr_read_block_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\curr_read_block[0]_i_1_n_0 ),
.Q(curr_read_block[0]),
.R(1'b0));
FDRE \curr_read_block_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\curr_read_block[1]_i_1_n_0 ),
.Q(curr_read_block[1]),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\current_state[0]_i_1__48
(.I0(\current_state[0]_i_2_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00004909))
\current_state[0]_i_2
(.I0(\current_state_reg_n_0_[1] ),
.I1(\current_state[0]_i_3_n_0 ),
.I2(\current_state_reg_n_0_[0] ),
.I3(read_data_en),
.I4(\current_state[0]_i_4_n_0 ),
.O(\current_state[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair211" *)
LUT5 #(
.INIT(32'h00000001))
\current_state[0]_i_3
(.I0(\current_state_reg_n_0_[6] ),
.I1(\current_state_reg_n_0_[5] ),
.I2(\current_state_reg_n_0_[4] ),
.I3(\current_state_reg_n_0_[2] ),
.I4(\current_state_reg_n_0_[3] ),
.O(\current_state[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair211" *)
LUT5 #(
.INIT(32'hFFFEFEE8))
\current_state[0]_i_4
(.I0(\current_state_reg_n_0_[3] ),
.I1(\current_state_reg_n_0_[2] ),
.I2(\current_state_reg_n_0_[4] ),
.I3(\current_state_reg_n_0_[5] ),
.I4(\current_state_reg_n_0_[6] ),
.O(\current_state[0]_i_4_n_0 ));
LUT4 #(
.INIT(16'h2808))
\current_state[1]_i_1__48
(.I0(\current_state[1]_i_2__10_n_0 ),
.I1(\current_state_reg_n_0_[6] ),
.I2(\current_state_reg_n_0_[0] ),
.I3(read_data_en),
.O(next_state[1]));
LUT5 #(
.INIT(32'h00000001))
\current_state[1]_i_2__10
(.I0(\current_state_reg_n_0_[5] ),
.I1(\current_state_reg_n_0_[3] ),
.I2(\current_state_reg_n_0_[4] ),
.I3(\current_state_reg_n_0_[1] ),
.I4(\current_state_reg_n_0_[2] ),
.O(\current_state[1]_i_2__10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair212" *)
LUT5 #(
.INIT(32'h00000310))
\current_state[2]_i_1__48
(.I0(\trace_data_ack_reg[1] ),
.I1(\current_state_reg_n_0_[5] ),
.I2(\current_state_reg_n_0_[2] ),
.I3(\current_state_reg_n_0_[1] ),
.I4(\current_state[3]_i_2__47_n_0 ),
.O(next_state[2]));
(* SOFT_HLUTNM = "soft_lutpair212" *)
LUT5 #(
.INIT(32'h00111000))
\current_state[3]_i_1__48
(.I0(\current_state_reg_n_0_[1] ),
.I1(\current_state[3]_i_2__47_n_0 ),
.I2(\trace_data_ack_reg[1] ),
.I3(\current_state_reg_n_0_[2] ),
.I4(\current_state_reg_n_0_[5] ),
.O(next_state[3]));
LUT4 #(
.INIT(16'hFFFE))
\current_state[3]_i_2__47
(.I0(\current_state_reg_n_0_[3] ),
.I1(\current_state_reg_n_0_[6] ),
.I2(\current_state_reg_n_0_[0] ),
.I3(\current_state_reg_n_0_[4] ),
.O(\current_state[3]_i_2__47_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair210" *)
LUT5 #(
.INIT(32'h00000414))
\current_state[4]_i_1
(.I0(\current_state_reg_n_0_[2] ),
.I1(\current_state_reg_n_0_[3] ),
.I2(\current_state_reg_n_0_[4] ),
.I3(read_data_en),
.I4(\current_state[4]_i_3_n_0 ),
.O(next_state[4]));
LUT4 #(
.INIT(16'hFFFE))
\current_state[4]_i_3
(.I0(\current_state_reg_n_0_[5] ),
.I1(\current_state_reg_n_0_[6] ),
.I2(\current_state_reg_n_0_[0] ),
.I3(\current_state_reg_n_0_[1] ),
.O(\current_state[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair221" *)
LUT3 #(
.INIT(8'h07))
\current_state[5]_i_1
(.I0(curr_read_block[1]),
.I1(curr_read_block[0]),
.I2(\current_state[6]_i_2_n_0 ),
.O(next_state[5]));
(* SOFT_HLUTNM = "soft_lutpair221" *)
LUT3 #(
.INIT(8'h08))
\current_state[6]_i_1
(.I0(curr_read_block[1]),
.I1(curr_read_block[0]),
.I2(\current_state[6]_i_2_n_0 ),
.O(next_state[6]));
(* SOFT_HLUTNM = "soft_lutpair210" *)
LUT5 #(
.INIT(32'hFFFFFFBF))
\current_state[6]_i_2
(.I0(\current_state[4]_i_3_n_0 ),
.I1(read_data_en),
.I2(\current_state_reg_n_0_[4] ),
.I3(\current_state_reg_n_0_[3] ),
.I4(\current_state_reg_n_0_[2] ),
.O(\current_state[6]_i_2_n_0 ));
FDSE #(
.INIT(1'b1))
\current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(\current_state_reg_n_0_[0] ),
.S(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(\current_state_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(\current_state_reg_n_0_[2] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(\current_state_reg_n_0_[3] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[4]),
.Q(\current_state_reg_n_0_[4] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[5]),
.Q(\current_state_reg_n_0_[5] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[6]),
.Q(\current_state_reg_n_0_[6] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\input_data_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[0]),
.Q(input_data[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[10]),
.Q(input_data[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[11]),
.Q(input_data[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[12]),
.Q(input_data[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[13]),
.Q(input_data[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[14]),
.Q(input_data[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[15]),
.Q(input_data[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[16]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[16]),
.Q(input_data[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[17]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[17]),
.Q(input_data[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[18]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[18]),
.Q(input_data[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[19]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[19]),
.Q(input_data[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[1]),
.Q(input_data[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[20]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[20]),
.Q(input_data[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[21]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[21]),
.Q(input_data[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[22]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[22]),
.Q(input_data[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[23]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[23]),
.Q(input_data[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[24]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[24]),
.Q(input_data[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[25]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[25]),
.Q(input_data[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[26]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[26]),
.Q(input_data[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[27]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[27]),
.Q(input_data[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[28]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[28]),
.Q(input_data[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[29]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[29]),
.Q(input_data[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[2]),
.Q(input_data[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[30]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[30]),
.Q(input_data[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[31]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[31]),
.Q(input_data[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[32]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[32]),
.Q(input_data[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[33]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[33]),
.Q(input_data[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[34]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[34]),
.Q(input_data[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[35]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[35]),
.Q(input_data[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[36]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[36]),
.Q(input_data[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[37]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[37]),
.Q(input_data[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[38]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[38]),
.Q(input_data[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[39]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[39]),
.Q(input_data[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[3]),
.Q(input_data[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[40]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[40]),
.Q(input_data[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[41]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[41]),
.Q(input_data[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[42]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[42]),
.Q(input_data[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[43]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[43]),
.Q(input_data[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[44]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[44]),
.Q(input_data[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[45]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[45]),
.Q(input_data[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[46]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[46]),
.Q(input_data[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[47]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[47]),
.Q(input_data[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[48]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[48]),
.Q(input_data[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[49]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[49]),
.Q(input_data[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[4]),
.Q(input_data[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[50]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[50]),
.Q(input_data[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[51]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[51]),
.Q(input_data[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[52]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[52]),
.Q(input_data[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[5]),
.Q(input_data[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[6]),
.Q(input_data[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[7]),
.Q(input_data[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[8]),
.Q(input_data[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[9]),
.Q(input_data[9]),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[2]_srl3 " *)
SRL16E \multiple_enable_latency.enable_out_reg[2]_srl3
(.A0(1'b0),
.A1(1'b1),
.A2(1'b0),
.A3(1'b0),
.CE(1'b1),
.CLK(s_dclk_o),
.D(next_state[3]),
.Q(\multiple_enable_latency.enable_out_reg[2]_srl3_n_0 ));
FDRE \multiple_enable_latency.enable_out_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\multiple_enable_latency.enable_out_reg[2]_srl3_n_0 ),
.Q(E),
.R(1'b0));
FDRE \multiple_read_latency.mahesh_temp_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in),
.Q(mahesh_temp),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[2]_srl3 " *)
SRL16E \multiple_read_latency.read_enable_out_reg[2]_srl3
(.A0(1'b0),
.A1(1'b1),
.A2(1'b0),
.A3(1'b0),
.CE(1'b1),
.CLK(s_dclk_o),
.D(next_state[1]),
.Q(\multiple_read_latency.read_enable_out_reg[2]_srl3_n_0 ));
FDRE \multiple_read_latency.read_enable_out_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\multiple_read_latency.read_enable_out_reg[2]_srl3_n_0 ),
.Q(p_0_in),
.R(1'b0));
CARRY4 read_addr0_carry
(.CI(1'b0),
.CO({read_addr0_carry_n_0,read_addr0_carry_n_1,read_addr0_carry_n_2,read_addr0_carry_n_3}),
.CYINIT(Q[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({read_addr0_carry_n_4,read_addr0_carry_n_5,read_addr0_carry_n_6,read_addr0_carry_n_7}),
.S({read_addr0_carry_i_1_n_0,read_addr0_carry_i_2_n_0,read_addr0_carry_i_3_n_0,read_addr0_carry_i_4_n_0}));
CARRY4 read_addr0_carry__0
(.CI(read_addr0_carry_n_0),
.CO({read_addr0_carry__0_n_0,read_addr0_carry__0_n_1,read_addr0_carry__0_n_2,read_addr0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({read_addr0_carry__0_n_4,read_addr0_carry__0_n_5,read_addr0_carry__0_n_6,read_addr0_carry__0_n_7}),
.S({read_addr0_carry__0_i_1_n_0,read_addr0_carry__0_i_2_n_0,read_addr0_carry__0_i_3_n_0,read_addr0_carry__0_i_4_n_0}));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__0_i_1
(.I0(Q[8]),
.O(read_addr0_carry__0_i_1_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__0_i_2
(.I0(Q[7]),
.O(read_addr0_carry__0_i_2_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__0_i_3
(.I0(Q[6]),
.O(read_addr0_carry__0_i_3_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__0_i_4
(.I0(Q[5]),
.O(read_addr0_carry__0_i_4_n_0));
CARRY4 read_addr0_carry__1
(.CI(read_addr0_carry__0_n_0),
.CO({read_addr0_carry__1_n_0,read_addr0_carry__1_n_1,read_addr0_carry__1_n_2,read_addr0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({read_addr0_carry__1_n_4,read_addr0_carry__1_n_5,read_addr0_carry__1_n_6,read_addr0_carry__1_n_7}),
.S({read_addr0_carry__1_i_1_n_0,read_addr0_carry__1_i_2_n_0,read_addr0_carry__1_i_3_n_0,read_addr0_carry__1_i_4_n_0}));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__1_i_1
(.I0(Q[12]),
.O(read_addr0_carry__1_i_1_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__1_i_2
(.I0(Q[11]),
.O(read_addr0_carry__1_i_2_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__1_i_3
(.I0(Q[10]),
.O(read_addr0_carry__1_i_3_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__1_i_4
(.I0(Q[9]),
.O(read_addr0_carry__1_i_4_n_0));
CARRY4 read_addr0_carry__2
(.CI(read_addr0_carry__1_n_0),
.CO({NLW_read_addr0_carry__2_CO_UNCONNECTED[3:1],read_addr0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW_read_addr0_carry__2_O_UNCONNECTED[3:2],read_addr0_carry__2_n_6,read_addr0_carry__2_n_7}),
.S({1'b0,1'b0,read_addr0_carry__2_i_1_n_0,read_addr0_carry__2_i_2_n_0}));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__2_i_1
(.I0(Q[14]),
.O(read_addr0_carry__2_i_1_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__2_i_2
(.I0(Q[13]),
.O(read_addr0_carry__2_i_2_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry_i_1
(.I0(Q[4]),
.O(read_addr0_carry_i_1_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry_i_2
(.I0(Q[3]),
.O(read_addr0_carry_i_2_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry_i_3
(.I0(Q[2]),
.O(read_addr0_carry_i_3_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry_i_4
(.I0(Q[1]),
.O(read_addr0_carry_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair214" *)
LUT3 #(
.INIT(8'h74))
\read_addr[0]_i_1
(.I0(Q[0]),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[0]),
.O(\read_addr[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'h74))
\read_addr[0]_rep_i_1
(.I0(Q[0]),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[0]),
.O(\read_addr[0]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair218" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[10]_i_1
(.I0(read_addr0_carry__1_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[10]),
.O(\read_addr[10]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[10]_rep_i_1
(.I0(read_addr0_carry__1_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[10]),
.O(\read_addr[10]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair217" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[11]_i_1
(.I0(read_addr0_carry__1_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[11]),
.O(\read_addr[11]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[11]_rep_i_1
(.I0(read_addr0_carry__1_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[11]),
.O(\read_addr[11]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair216" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[12]_i_1
(.I0(read_addr0_carry__1_n_4),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[12]),
.O(\read_addr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair215" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[13]_i_1
(.I0(read_addr0_carry__2_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[13]),
.O(\read_addr[13]_i_1_n_0 ));
LUT4 #(
.INIT(16'h7444))
\read_addr[14]_i_1
(.I0(\current_state[0]_i_2_n_0 ),
.I1(\current_state[6]_i_2_n_0 ),
.I2(curr_read_block[0]),
.I3(curr_read_block[1]),
.O(read_addr));
(* SOFT_HLUTNM = "soft_lutpair214" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[14]_i_2
(.I0(read_addr0_carry__2_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[14]),
.O(\read_addr[14]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair215" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[1]_i_1
(.I0(read_addr0_carry_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[1]),
.O(\read_addr[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[1]_rep_i_1
(.I0(read_addr0_carry_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[1]),
.O(\read_addr[1]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair216" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[2]_i_1
(.I0(read_addr0_carry_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[2]),
.O(\read_addr[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[2]_rep_i_1
(.I0(read_addr0_carry_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[2]),
.O(\read_addr[2]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair217" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[3]_i_1
(.I0(read_addr0_carry_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[3]),
.O(\read_addr[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[3]_rep_i_1
(.I0(read_addr0_carry_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[3]),
.O(\read_addr[3]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair218" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[4]_i_1
(.I0(read_addr0_carry_n_4),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[4]),
.O(\read_addr[4]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[4]_rep_i_1
(.I0(read_addr0_carry_n_4),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[4]),
.O(\read_addr[4]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair219" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[5]_i_1
(.I0(read_addr0_carry__0_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[5]),
.O(\read_addr[5]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[5]_rep_i_1
(.I0(read_addr0_carry__0_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[5]),
.O(\read_addr[5]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair220" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[6]_i_1
(.I0(read_addr0_carry__0_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[6]),
.O(\read_addr[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[6]_rep_i_1
(.I0(read_addr0_carry__0_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[6]),
.O(\read_addr[6]_rep_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[7]_i_1
(.I0(read_addr0_carry__0_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[7]),
.O(\read_addr[7]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[7]_rep_i_1
(.I0(read_addr0_carry__0_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[7]),
.O(\read_addr[7]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair220" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[8]_i_1
(.I0(read_addr0_carry__0_n_4),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[8]),
.O(\read_addr[8]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[8]_rep_i_1
(.I0(read_addr0_carry__0_n_4),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[8]),
.O(\read_addr[8]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair219" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[9]_i_1
(.I0(read_addr0_carry__1_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[9]),
.O(\read_addr[9]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[9]_rep_i_1
(.I0(read_addr0_carry__1_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[9]),
.O(\read_addr[9]_rep_i_1_n_0 ));
(* ORIG_CELL_NAME = "read_addr_reg[0]" *)
FDRE \read_addr_reg[0]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[0]_i_1_n_0 ),
.Q(Q[0]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[0]" *)
FDRE \read_addr_reg[0]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[0]_rep_i_1_n_0 ),
.Q(ADDRBWRADDR),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[10]" *)
FDRE \read_addr_reg[10]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[10]_i_1_n_0 ),
.Q(Q[10]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[10]" *)
FDRE \read_addr_reg[10]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[10]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[11]" *)
FDRE \read_addr_reg[11]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[11]_i_1_n_0 ),
.Q(Q[11]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[11]" *)
FDRE \read_addr_reg[11]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[11]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [10]),
.R(1'b0));
FDRE \read_addr_reg[12]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[12]_i_1_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \read_addr_reg[13]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[13]_i_1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \read_addr_reg[14]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[14]_i_2_n_0 ),
.Q(Q[14]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[1]" *)
FDRE \read_addr_reg[1]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[1]_i_1_n_0 ),
.Q(Q[1]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[1]" *)
FDRE \read_addr_reg[1]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[1]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[2]" *)
FDRE \read_addr_reg[2]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[2]_i_1_n_0 ),
.Q(Q[2]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[2]" *)
FDRE \read_addr_reg[2]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[2]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[3]" *)
FDRE \read_addr_reg[3]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[3]_i_1_n_0 ),
.Q(Q[3]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[3]" *)
FDRE \read_addr_reg[3]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[3]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[4]" *)
FDRE \read_addr_reg[4]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[4]_i_1_n_0 ),
.Q(Q[4]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[4]" *)
FDRE \read_addr_reg[4]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[4]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[5]" *)
FDRE \read_addr_reg[5]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[5]_i_1_n_0 ),
.Q(Q[5]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[5]" *)
FDRE \read_addr_reg[5]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[5]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[6]" *)
FDRE \read_addr_reg[6]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[6]_i_1_n_0 ),
.Q(Q[6]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[6]" *)
FDRE \read_addr_reg[6]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[6]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[7]" *)
FDRE \read_addr_reg[7]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[7]_i_1_n_0 ),
.Q(Q[7]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[7]" *)
FDRE \read_addr_reg[7]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[7]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[8]" *)
FDRE \read_addr_reg[8]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[8]_i_1_n_0 ),
.Q(Q[8]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[8]" *)
FDRE \read_addr_reg[8]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[8]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[9]" *)
FDRE \read_addr_reg[9]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[9]_i_1_n_0 ),
.Q(Q[9]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[9]" *)
FDRE \read_addr_reg[9]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[9]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.R(1'b0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\xsdb_reg[0]_i_1
(.I0(input_data[48]),
.I1(input_data[16]),
.I2(curr_read_block[0]),
.I3(input_data[32]),
.I4(curr_read_block[1]),
.I5(input_data[0]),
.O(\xsdb_reg_reg[15] [0]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[10]_i_1
(.I0(input_data[26]),
.I1(curr_read_block[0]),
.I2(input_data[42]),
.I3(curr_read_block[1]),
.I4(input_data[10]),
.O(\xsdb_reg_reg[15] [10]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[11]_i_1
(.I0(input_data[27]),
.I1(curr_read_block[0]),
.I2(input_data[43]),
.I3(curr_read_block[1]),
.I4(input_data[11]),
.O(\xsdb_reg_reg[15] [11]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[12]_i_1
(.I0(input_data[28]),
.I1(curr_read_block[0]),
.I2(input_data[44]),
.I3(curr_read_block[1]),
.I4(input_data[12]),
.O(\xsdb_reg_reg[15] [12]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[13]_i_1
(.I0(input_data[29]),
.I1(curr_read_block[0]),
.I2(input_data[45]),
.I3(curr_read_block[1]),
.I4(input_data[13]),
.O(\xsdb_reg_reg[15] [13]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[14]_i_1
(.I0(input_data[30]),
.I1(curr_read_block[0]),
.I2(input_data[46]),
.I3(curr_read_block[1]),
.I4(input_data[14]),
.O(\xsdb_reg_reg[15] [14]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[15]_i_1__13
(.I0(input_data[31]),
.I1(curr_read_block[0]),
.I2(input_data[47]),
.I3(curr_read_block[1]),
.I4(input_data[15]),
.O(\xsdb_reg_reg[15] [15]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\xsdb_reg[1]_i_1
(.I0(input_data[49]),
.I1(input_data[17]),
.I2(curr_read_block[0]),
.I3(input_data[33]),
.I4(curr_read_block[1]),
.I5(input_data[1]),
.O(\xsdb_reg_reg[15] [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\xsdb_reg[2]_i_1
(.I0(input_data[50]),
.I1(input_data[18]),
.I2(curr_read_block[0]),
.I3(input_data[34]),
.I4(curr_read_block[1]),
.I5(input_data[2]),
.O(\xsdb_reg_reg[15] [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\xsdb_reg[3]_i_1
(.I0(input_data[51]),
.I1(input_data[19]),
.I2(curr_read_block[0]),
.I3(input_data[35]),
.I4(curr_read_block[1]),
.I5(input_data[3]),
.O(\xsdb_reg_reg[15] [3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\xsdb_reg[4]_i_1
(.I0(input_data[52]),
.I1(input_data[20]),
.I2(curr_read_block[0]),
.I3(input_data[36]),
.I4(curr_read_block[1]),
.I5(input_data[4]),
.O(\xsdb_reg_reg[15] [4]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[5]_i_1
(.I0(input_data[21]),
.I1(curr_read_block[0]),
.I2(input_data[37]),
.I3(curr_read_block[1]),
.I4(input_data[5]),
.O(\xsdb_reg_reg[15] [5]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[6]_i_1
(.I0(input_data[22]),
.I1(curr_read_block[0]),
.I2(input_data[38]),
.I3(curr_read_block[1]),
.I4(input_data[6]),
.O(\xsdb_reg_reg[15] [6]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[7]_i_1
(.I0(input_data[23]),
.I1(curr_read_block[0]),
.I2(input_data[39]),
.I3(curr_read_block[1]),
.I4(input_data[7]),
.O(\xsdb_reg_reg[15] [7]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[8]_i_1
(.I0(input_data[24]),
.I1(curr_read_block[0]),
.I2(input_data[40]),
.I3(curr_read_block[1]),
.I4(input_data[8]),
.O(\xsdb_reg_reg[15] [8]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[9]_i_1
(.I0(input_data[25]),
.I1(curr_read_block[0]),
.I2(input_data[41]),
.I3(curr_read_block[1]),
.I4(input_data[9]),
.O(\xsdb_reg_reg[15] [9]));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_generic_memrd
(E,
Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
ADDRBWRADDR,
enb_array,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ,
\xsdb_reg_reg[15] ,
s_dclk_o,
SR,
D,
read_data_en,
read_reset_addr,
\trace_data_ack_reg[1] ); |
output [0:0]E;
output [14:0]Q;
output [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [0:0]ADDRBWRADDR;
output [7:0]enb_array;
output [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
output [15:0]\xsdb_reg_reg[15] ;
input s_dclk_o;
input [0:0]SR;
input [52:0]D;
input read_data_en;
input [14:0]read_reset_addr;
input [0:0]\trace_data_ack_reg[1] ;
wire [0:0]ADDRBWRADDR;
wire [52:0]D;
wire [10:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ;
wire [0:0]E;
wire [14:0]Q;
wire [0:0]SR;
wire [1:0]curr_read_block;
wire \curr_read_block[0]_i_1_n_0 ;
wire \curr_read_block[1]_i_1_n_0 ;
wire \current_state[0]_i_2_n_0 ;
wire \current_state[0]_i_3_n_0 ;
wire \current_state[0]_i_4_n_0 ;
wire \current_state[1]_i_2__10_n_0 ;
wire \current_state[3]_i_2__47_n_0 ;
wire \current_state[4]_i_3_n_0 ;
wire \current_state[6]_i_2_n_0 ;
wire \current_state_reg_n_0_[0] ;
wire \current_state_reg_n_0_[1] ;
wire \current_state_reg_n_0_[2] ;
wire \current_state_reg_n_0_[3] ;
wire \current_state_reg_n_0_[4] ;
wire \current_state_reg_n_0_[5] ;
wire \current_state_reg_n_0_[6] ;
wire [7:0]enb_array;
wire [52:0]input_data;
wire mahesh_temp;
wire \multiple_enable_latency.enable_out_reg[2]_srl3_n_0 ;
wire \multiple_read_latency.read_enable_out_reg[2]_srl3_n_0 ;
wire [6:0]next_state;
wire p_0_in;
wire read_addr;
wire read_addr0_carry__0_i_1_n_0;
wire read_addr0_carry__0_i_2_n_0;
wire read_addr0_carry__0_i_3_n_0;
wire read_addr0_carry__0_i_4_n_0;
wire read_addr0_carry__0_n_0;
wire read_addr0_carry__0_n_1;
wire read_addr0_carry__0_n_2;
wire read_addr0_carry__0_n_3;
wire read_addr0_carry__0_n_4;
wire read_addr0_carry__0_n_5;
wire read_addr0_carry__0_n_6;
wire read_addr0_carry__0_n_7;
wire read_addr0_carry__1_i_1_n_0;
wire read_addr0_carry__1_i_2_n_0;
wire read_addr0_carry__1_i_3_n_0;
wire read_addr0_carry__1_i_4_n_0;
wire read_addr0_carry__1_n_0;
wire read_addr0_carry__1_n_1;
wire read_addr0_carry__1_n_2;
wire read_addr0_carry__1_n_3;
wire read_addr0_carry__1_n_4;
wire read_addr0_carry__1_n_5;
wire read_addr0_carry__1_n_6;
wire read_addr0_carry__1_n_7;
wire read_addr0_carry__2_i_1_n_0;
wire read_addr0_carry__2_i_2_n_0;
wire read_addr0_carry__2_n_3;
wire read_addr0_carry__2_n_6;
wire read_addr0_carry__2_n_7;
wire read_addr0_carry_i_1_n_0;
wire read_addr0_carry_i_2_n_0;
wire read_addr0_carry_i_3_n_0;
wire read_addr0_carry_i_4_n_0;
wire read_addr0_carry_n_0;
wire read_addr0_carry_n_1;
wire read_addr0_carry_n_2;
wire read_addr0_carry_n_3;
wire read_addr0_carry_n_4;
wire read_addr0_carry_n_5;
wire read_addr0_carry_n_6;
wire read_addr0_carry_n_7;
wire \read_addr[0]_i_1_n_0 ;
wire \read_addr[0]_rep_i_1_n_0 ;
wire \read_addr[10]_i_1_n_0 ;
wire \read_addr[10]_rep_i_1_n_0 ;
wire \read_addr[11]_i_1_n_0 ;
wire \read_addr[11]_rep_i_1_n_0 ;
wire \read_addr[12]_i_1_n_0 ;
wire \read_addr[13]_i_1_n_0 ;
wire \read_addr[14]_i_2_n_0 ;
wire \read_addr[1]_i_1_n_0 ;
wire \read_addr[1]_rep_i_1_n_0 ;
wire \read_addr[2]_i_1_n_0 ;
wire \read_addr[2]_rep_i_1_n_0 ;
wire \read_addr[3]_i_1_n_0 ;
wire \read_addr[3]_rep_i_1_n_0 ;
wire \read_addr[4]_i_1_n_0 ;
wire \read_addr[4]_rep_i_1_n_0 ;
wire \read_addr[5]_i_1_n_0 ;
wire \read_addr[5]_rep_i_1_n_0 ;
wire \read_addr[6]_i_1_n_0 ;
wire \read_addr[6]_rep_i_1_n_0 ;
wire \read_addr[7]_i_1_n_0 ;
wire \read_addr[7]_rep_i_1_n_0 ;
wire \read_addr[8]_i_1_n_0 ;
wire \read_addr[8]_rep_i_1_n_0 ;
wire \read_addr[9]_i_1_n_0 ;
wire \read_addr[9]_rep_i_1_n_0 ;
wire read_data_en;
wire [14:0]read_reset_addr;
wire s_dclk_o;
wire [0:0]\trace_data_ack_reg[1] ;
wire [15:0]\xsdb_reg_reg[15] ;
wire [3:1]NLW_read_addr0_carry__2_CO_UNCONNECTED;
wire [3:2]NLW_read_addr0_carry__2_O_UNCONNECTED;
LUT5 #(
.INIT(32'h0000000E))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[13]),
.I4(Q[14]),
.O(enb_array[0]));
LUT5 #(
.INIT(32'h00000E00))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[13]),
.I4(Q[14]),
.O(enb_array[2]));
LUT5 #(
.INIT(32'h00000E00))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__1
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[14]),
.I4(Q[13]),
.O(enb_array[4]));
LUT5 #(
.INIT(32'h00008880))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__2
(.I0(Q[13]),
.I1(Q[14]),
.I2(mahesh_temp),
.I3(p_0_in),
.I4(Q[12]),
.O(enb_array[6]));
LUT5 #(
.INIT(32'h000000E0))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__3
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[13]),
.I4(Q[14]),
.O(enb_array[1]));
LUT5 #(
.INIT(32'h0000E000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__4
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[13]),
.I4(Q[14]),
.O(enb_array[3]));
LUT5 #(
.INIT(32'h0000E000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__5
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[14]),
.I4(Q[13]),
.O(enb_array[5]));
LUT5 #(
.INIT(32'hE0000000))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__6
(.I0(mahesh_temp),
.I1(p_0_in),
.I2(Q[12]),
.I3(Q[13]),
.I4(Q[14]),
.O(enb_array[7]));
LUT2 #(
.INIT(4'hE))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_3
(.I0(p_0_in),
.I1(mahesh_temp),
.O(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0 ));
(* SOFT_HLUTNM = "soft_lutpair213" *)
LUT3 #(
.INIT(8'h85))
\curr_read_block[0]_i_1
(.I0(\current_state[6]_i_2_n_0 ),
.I1(\current_state[0]_i_2_n_0 ),
.I2(curr_read_block[0]),
.O(\curr_read_block[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair213" *)
LUT4 #(
.INIT(16'hD122))
\curr_read_block[1]_i_1
(.I0(curr_read_block[0]),
.I1(\current_state[6]_i_2_n_0 ),
.I2(\current_state[0]_i_2_n_0 ),
.I3(curr_read_block[1]),
.O(\curr_read_block[1]_i_1_n_0 ));
FDRE \curr_read_block_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\curr_read_block[0]_i_1_n_0 ),
.Q(curr_read_block[0]),
.R(1'b0));
FDRE \curr_read_block_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\curr_read_block[1]_i_1_n_0 ),
.Q(curr_read_block[1]),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\current_state[0]_i_1__48
(.I0(\current_state[0]_i_2_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00004909))
\current_state[0]_i_2
(.I0(\current_state_reg_n_0_[1] ),
.I1(\current_state[0]_i_3_n_0 ),
.I2(\current_state_reg_n_0_[0] ),
.I3(read_data_en),
.I4(\current_state[0]_i_4_n_0 ),
.O(\current_state[0]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair211" *)
LUT5 #(
.INIT(32'h00000001))
\current_state[0]_i_3
(.I0(\current_state_reg_n_0_[6] ),
.I1(\current_state_reg_n_0_[5] ),
.I2(\current_state_reg_n_0_[4] ),
.I3(\current_state_reg_n_0_[2] ),
.I4(\current_state_reg_n_0_[3] ),
.O(\current_state[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair211" *)
LUT5 #(
.INIT(32'hFFFEFEE8))
\current_state[0]_i_4
(.I0(\current_state_reg_n_0_[3] ),
.I1(\current_state_reg_n_0_[2] ),
.I2(\current_state_reg_n_0_[4] ),
.I3(\current_state_reg_n_0_[5] ),
.I4(\current_state_reg_n_0_[6] ),
.O(\current_state[0]_i_4_n_0 ));
LUT4 #(
.INIT(16'h2808))
\current_state[1]_i_1__48
(.I0(\current_state[1]_i_2__10_n_0 ),
.I1(\current_state_reg_n_0_[6] ),
.I2(\current_state_reg_n_0_[0] ),
.I3(read_data_en),
.O(next_state[1]));
LUT5 #(
.INIT(32'h00000001))
\current_state[1]_i_2__10
(.I0(\current_state_reg_n_0_[5] ),
.I1(\current_state_reg_n_0_[3] ),
.I2(\current_state_reg_n_0_[4] ),
.I3(\current_state_reg_n_0_[1] ),
.I4(\current_state_reg_n_0_[2] ),
.O(\current_state[1]_i_2__10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair212" *)
LUT5 #(
.INIT(32'h00000310))
\current_state[2]_i_1__48
(.I0(\trace_data_ack_reg[1] ),
.I1(\current_state_reg_n_0_[5] ),
.I2(\current_state_reg_n_0_[2] ),
.I3(\current_state_reg_n_0_[1] ),
.I4(\current_state[3]_i_2__47_n_0 ),
.O(next_state[2]));
(* SOFT_HLUTNM = "soft_lutpair212" *)
LUT5 #(
.INIT(32'h00111000))
\current_state[3]_i_1__48
(.I0(\current_state_reg_n_0_[1] ),
.I1(\current_state[3]_i_2__47_n_0 ),
.I2(\trace_data_ack_reg[1] ),
.I3(\current_state_reg_n_0_[2] ),
.I4(\current_state_reg_n_0_[5] ),
.O(next_state[3]));
LUT4 #(
.INIT(16'hFFFE))
\current_state[3]_i_2__47
(.I0(\current_state_reg_n_0_[3] ),
.I1(\current_state_reg_n_0_[6] ),
.I2(\current_state_reg_n_0_[0] ),
.I3(\current_state_reg_n_0_[4] ),
.O(\current_state[3]_i_2__47_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair210" *)
LUT5 #(
.INIT(32'h00000414))
\current_state[4]_i_1
(.I0(\current_state_reg_n_0_[2] ),
.I1(\current_state_reg_n_0_[3] ),
.I2(\current_state_reg_n_0_[4] ),
.I3(read_data_en),
.I4(\current_state[4]_i_3_n_0 ),
.O(next_state[4]));
LUT4 #(
.INIT(16'hFFFE))
\current_state[4]_i_3
(.I0(\current_state_reg_n_0_[5] ),
.I1(\current_state_reg_n_0_[6] ),
.I2(\current_state_reg_n_0_[0] ),
.I3(\current_state_reg_n_0_[1] ),
.O(\current_state[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair221" *)
LUT3 #(
.INIT(8'h07))
\current_state[5]_i_1
(.I0(curr_read_block[1]),
.I1(curr_read_block[0]),
.I2(\current_state[6]_i_2_n_0 ),
.O(next_state[5]));
(* SOFT_HLUTNM = "soft_lutpair221" *)
LUT3 #(
.INIT(8'h08))
\current_state[6]_i_1
(.I0(curr_read_block[1]),
.I1(curr_read_block[0]),
.I2(\current_state[6]_i_2_n_0 ),
.O(next_state[6]));
(* SOFT_HLUTNM = "soft_lutpair210" *)
LUT5 #(
.INIT(32'hFFFFFFBF))
\current_state[6]_i_2
(.I0(\current_state[4]_i_3_n_0 ),
.I1(read_data_en),
.I2(\current_state_reg_n_0_[4] ),
.I3(\current_state_reg_n_0_[3] ),
.I4(\current_state_reg_n_0_[2] ),
.O(\current_state[6]_i_2_n_0 ));
FDSE #(
.INIT(1'b1))
\current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(\current_state_reg_n_0_[0] ),
.S(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(\current_state_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(\current_state_reg_n_0_[2] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(\current_state_reg_n_0_[3] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[4]),
.Q(\current_state_reg_n_0_[4] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[5]),
.Q(\current_state_reg_n_0_[5] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\current_state_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[6]),
.Q(\current_state_reg_n_0_[6] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\input_data_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[0]),
.Q(input_data[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[10]),
.Q(input_data[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[11]),
.Q(input_data[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[12]),
.Q(input_data[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[13]),
.Q(input_data[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[14]),
.Q(input_data[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[15]),
.Q(input_data[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[16]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[16]),
.Q(input_data[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[17]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[17]),
.Q(input_data[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[18]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[18]),
.Q(input_data[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[19]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[19]),
.Q(input_data[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[1]),
.Q(input_data[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[20]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[20]),
.Q(input_data[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[21]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[21]),
.Q(input_data[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[22]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[22]),
.Q(input_data[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[23]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[23]),
.Q(input_data[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[24]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[24]),
.Q(input_data[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[25]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[25]),
.Q(input_data[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[26]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[26]),
.Q(input_data[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[27]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[27]),
.Q(input_data[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[28]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[28]),
.Q(input_data[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[29]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[29]),
.Q(input_data[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[2]),
.Q(input_data[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[30]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[30]),
.Q(input_data[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[31]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[31]),
.Q(input_data[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[32]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[32]),
.Q(input_data[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[33]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[33]),
.Q(input_data[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[34]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[34]),
.Q(input_data[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[35]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[35]),
.Q(input_data[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[36]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[36]),
.Q(input_data[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[37]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[37]),
.Q(input_data[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[38]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[38]),
.Q(input_data[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[39]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[39]),
.Q(input_data[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[3]),
.Q(input_data[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[40]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[40]),
.Q(input_data[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[41]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[41]),
.Q(input_data[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[42]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[42]),
.Q(input_data[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[43]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[43]),
.Q(input_data[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[44]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[44]),
.Q(input_data[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[45]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[45]),
.Q(input_data[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[46]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[46]),
.Q(input_data[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[47]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[47]),
.Q(input_data[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[48]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[48]),
.Q(input_data[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[49]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[49]),
.Q(input_data[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[4]),
.Q(input_data[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[50]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[50]),
.Q(input_data[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[51]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[51]),
.Q(input_data[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[52]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[52]),
.Q(input_data[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[5]),
.Q(input_data[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[6]),
.Q(input_data[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[7]),
.Q(input_data[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[8]),
.Q(input_data[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\input_data_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(D[9]),
.Q(input_data[9]),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[2]_srl3 " *)
SRL16E \multiple_enable_latency.enable_out_reg[2]_srl3
(.A0(1'b0),
.A1(1'b1),
.A2(1'b0),
.A3(1'b0),
.CE(1'b1),
.CLK(s_dclk_o),
.D(next_state[3]),
.Q(\multiple_enable_latency.enable_out_reg[2]_srl3_n_0 ));
FDRE \multiple_enable_latency.enable_out_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\multiple_enable_latency.enable_out_reg[2]_srl3_n_0 ),
.Q(E),
.R(1'b0));
FDRE \multiple_read_latency.mahesh_temp_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in),
.Q(mahesh_temp),
.R(1'b0));
(* srl_bus_name = "U0/ila_lib/U0/\ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg " *)
(* srl_name = "U0/ila_lib/U0/\ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[2]_srl3 " *)
SRL16E \multiple_read_latency.read_enable_out_reg[2]_srl3
(.A0(1'b0),
.A1(1'b1),
.A2(1'b0),
.A3(1'b0),
.CE(1'b1),
.CLK(s_dclk_o),
.D(next_state[1]),
.Q(\multiple_read_latency.read_enable_out_reg[2]_srl3_n_0 ));
FDRE \multiple_read_latency.read_enable_out_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\multiple_read_latency.read_enable_out_reg[2]_srl3_n_0 ),
.Q(p_0_in),
.R(1'b0));
CARRY4 read_addr0_carry
(.CI(1'b0),
.CO({read_addr0_carry_n_0,read_addr0_carry_n_1,read_addr0_carry_n_2,read_addr0_carry_n_3}),
.CYINIT(Q[0]),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({read_addr0_carry_n_4,read_addr0_carry_n_5,read_addr0_carry_n_6,read_addr0_carry_n_7}),
.S({read_addr0_carry_i_1_n_0,read_addr0_carry_i_2_n_0,read_addr0_carry_i_3_n_0,read_addr0_carry_i_4_n_0}));
CARRY4 read_addr0_carry__0
(.CI(read_addr0_carry_n_0),
.CO({read_addr0_carry__0_n_0,read_addr0_carry__0_n_1,read_addr0_carry__0_n_2,read_addr0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({read_addr0_carry__0_n_4,read_addr0_carry__0_n_5,read_addr0_carry__0_n_6,read_addr0_carry__0_n_7}),
.S({read_addr0_carry__0_i_1_n_0,read_addr0_carry__0_i_2_n_0,read_addr0_carry__0_i_3_n_0,read_addr0_carry__0_i_4_n_0}));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__0_i_1
(.I0(Q[8]),
.O(read_addr0_carry__0_i_1_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__0_i_2
(.I0(Q[7]),
.O(read_addr0_carry__0_i_2_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__0_i_3
(.I0(Q[6]),
.O(read_addr0_carry__0_i_3_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__0_i_4
(.I0(Q[5]),
.O(read_addr0_carry__0_i_4_n_0));
CARRY4 read_addr0_carry__1
(.CI(read_addr0_carry__0_n_0),
.CO({read_addr0_carry__1_n_0,read_addr0_carry__1_n_1,read_addr0_carry__1_n_2,read_addr0_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({read_addr0_carry__1_n_4,read_addr0_carry__1_n_5,read_addr0_carry__1_n_6,read_addr0_carry__1_n_7}),
.S({read_addr0_carry__1_i_1_n_0,read_addr0_carry__1_i_2_n_0,read_addr0_carry__1_i_3_n_0,read_addr0_carry__1_i_4_n_0}));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__1_i_1
(.I0(Q[12]),
.O(read_addr0_carry__1_i_1_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__1_i_2
(.I0(Q[11]),
.O(read_addr0_carry__1_i_2_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__1_i_3
(.I0(Q[10]),
.O(read_addr0_carry__1_i_3_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__1_i_4
(.I0(Q[9]),
.O(read_addr0_carry__1_i_4_n_0));
CARRY4 read_addr0_carry__2
(.CI(read_addr0_carry__1_n_0),
.CO({NLW_read_addr0_carry__2_CO_UNCONNECTED[3:1],read_addr0_carry__2_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW_read_addr0_carry__2_O_UNCONNECTED[3:2],read_addr0_carry__2_n_6,read_addr0_carry__2_n_7}),
.S({1'b0,1'b0,read_addr0_carry__2_i_1_n_0,read_addr0_carry__2_i_2_n_0}));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__2_i_1
(.I0(Q[14]),
.O(read_addr0_carry__2_i_1_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry__2_i_2
(.I0(Q[13]),
.O(read_addr0_carry__2_i_2_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry_i_1
(.I0(Q[4]),
.O(read_addr0_carry_i_1_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry_i_2
(.I0(Q[3]),
.O(read_addr0_carry_i_2_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry_i_3
(.I0(Q[2]),
.O(read_addr0_carry_i_3_n_0));
LUT1 #(
.INIT(2'h2))
read_addr0_carry_i_4
(.I0(Q[1]),
.O(read_addr0_carry_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair214" *)
LUT3 #(
.INIT(8'h74))
\read_addr[0]_i_1
(.I0(Q[0]),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[0]),
.O(\read_addr[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'h74))
\read_addr[0]_rep_i_1
(.I0(Q[0]),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[0]),
.O(\read_addr[0]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair218" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[10]_i_1
(.I0(read_addr0_carry__1_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[10]),
.O(\read_addr[10]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[10]_rep_i_1
(.I0(read_addr0_carry__1_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[10]),
.O(\read_addr[10]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair217" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[11]_i_1
(.I0(read_addr0_carry__1_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[11]),
.O(\read_addr[11]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[11]_rep_i_1
(.I0(read_addr0_carry__1_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[11]),
.O(\read_addr[11]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair216" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[12]_i_1
(.I0(read_addr0_carry__1_n_4),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[12]),
.O(\read_addr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair215" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[13]_i_1
(.I0(read_addr0_carry__2_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[13]),
.O(\read_addr[13]_i_1_n_0 ));
LUT4 #(
.INIT(16'h7444))
\read_addr[14]_i_1
(.I0(\current_state[0]_i_2_n_0 ),
.I1(\current_state[6]_i_2_n_0 ),
.I2(curr_read_block[0]),
.I3(curr_read_block[1]),
.O(read_addr));
(* SOFT_HLUTNM = "soft_lutpair214" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[14]_i_2
(.I0(read_addr0_carry__2_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[14]),
.O(\read_addr[14]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair215" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[1]_i_1
(.I0(read_addr0_carry_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[1]),
.O(\read_addr[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[1]_rep_i_1
(.I0(read_addr0_carry_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[1]),
.O(\read_addr[1]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair216" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[2]_i_1
(.I0(read_addr0_carry_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[2]),
.O(\read_addr[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[2]_rep_i_1
(.I0(read_addr0_carry_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[2]),
.O(\read_addr[2]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair217" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[3]_i_1
(.I0(read_addr0_carry_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[3]),
.O(\read_addr[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[3]_rep_i_1
(.I0(read_addr0_carry_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[3]),
.O(\read_addr[3]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair218" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[4]_i_1
(.I0(read_addr0_carry_n_4),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[4]),
.O(\read_addr[4]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[4]_rep_i_1
(.I0(read_addr0_carry_n_4),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[4]),
.O(\read_addr[4]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair219" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[5]_i_1
(.I0(read_addr0_carry__0_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[5]),
.O(\read_addr[5]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[5]_rep_i_1
(.I0(read_addr0_carry__0_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[5]),
.O(\read_addr[5]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair220" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[6]_i_1
(.I0(read_addr0_carry__0_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[6]),
.O(\read_addr[6]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[6]_rep_i_1
(.I0(read_addr0_carry__0_n_6),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[6]),
.O(\read_addr[6]_rep_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[7]_i_1
(.I0(read_addr0_carry__0_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[7]),
.O(\read_addr[7]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[7]_rep_i_1
(.I0(read_addr0_carry__0_n_5),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[7]),
.O(\read_addr[7]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair220" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[8]_i_1
(.I0(read_addr0_carry__0_n_4),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[8]),
.O(\read_addr[8]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[8]_rep_i_1
(.I0(read_addr0_carry__0_n_4),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[8]),
.O(\read_addr[8]_rep_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair219" *)
LUT3 #(
.INIT(8'hB8))
\read_addr[9]_i_1
(.I0(read_addr0_carry__1_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[9]),
.O(\read_addr[9]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\read_addr[9]_rep_i_1
(.I0(read_addr0_carry__1_n_7),
.I1(\current_state[0]_i_2_n_0 ),
.I2(read_reset_addr[9]),
.O(\read_addr[9]_rep_i_1_n_0 ));
(* ORIG_CELL_NAME = "read_addr_reg[0]" *)
FDRE \read_addr_reg[0]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[0]_i_1_n_0 ),
.Q(Q[0]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[0]" *)
FDRE \read_addr_reg[0]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[0]_rep_i_1_n_0 ),
.Q(ADDRBWRADDR),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[10]" *)
FDRE \read_addr_reg[10]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[10]_i_1_n_0 ),
.Q(Q[10]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[10]" *)
FDRE \read_addr_reg[10]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[10]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[11]" *)
FDRE \read_addr_reg[11]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[11]_i_1_n_0 ),
.Q(Q[11]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[11]" *)
FDRE \read_addr_reg[11]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[11]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [10]),
.R(1'b0));
FDRE \read_addr_reg[12]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[12]_i_1_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \read_addr_reg[13]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[13]_i_1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \read_addr_reg[14]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[14]_i_2_n_0 ),
.Q(Q[14]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[1]" *)
FDRE \read_addr_reg[1]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[1]_i_1_n_0 ),
.Q(Q[1]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[1]" *)
FDRE \read_addr_reg[1]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[1]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[2]" *)
FDRE \read_addr_reg[2]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[2]_i_1_n_0 ),
.Q(Q[2]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[2]" *)
FDRE \read_addr_reg[2]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[2]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[3]" *)
FDRE \read_addr_reg[3]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[3]_i_1_n_0 ),
.Q(Q[3]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[3]" *)
FDRE \read_addr_reg[3]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[3]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[4]" *)
FDRE \read_addr_reg[4]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[4]_i_1_n_0 ),
.Q(Q[4]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[4]" *)
FDRE \read_addr_reg[4]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[4]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[5]" *)
FDRE \read_addr_reg[5]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[5]_i_1_n_0 ),
.Q(Q[5]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[5]" *)
FDRE \read_addr_reg[5]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[5]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[6]" *)
FDRE \read_addr_reg[6]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[6]_i_1_n_0 ),
.Q(Q[6]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[6]" *)
FDRE \read_addr_reg[6]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[6]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[7]" *)
FDRE \read_addr_reg[7]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[7]_i_1_n_0 ),
.Q(Q[7]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[7]" *)
FDRE \read_addr_reg[7]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[7]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[8]" *)
FDRE \read_addr_reg[8]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[8]_i_1_n_0 ),
.Q(Q[8]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[8]" *)
FDRE \read_addr_reg[8]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[8]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[9]" *)
FDRE \read_addr_reg[9]
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[9]_i_1_n_0 ),
.Q(Q[9]),
.R(1'b0));
(* ORIG_CELL_NAME = "read_addr_reg[9]" *)
FDRE \read_addr_reg[9]_rep
(.C(s_dclk_o),
.CE(read_addr),
.D(\read_addr[9]_rep_i_1_n_0 ),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.R(1'b0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\xsdb_reg[0]_i_1
(.I0(input_data[48]),
.I1(input_data[16]),
.I2(curr_read_block[0]),
.I3(input_data[32]),
.I4(curr_read_block[1]),
.I5(input_data[0]),
.O(\xsdb_reg_reg[15] [0]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[10]_i_1
(.I0(input_data[26]),
.I1(curr_read_block[0]),
.I2(input_data[42]),
.I3(curr_read_block[1]),
.I4(input_data[10]),
.O(\xsdb_reg_reg[15] [10]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[11]_i_1
(.I0(input_data[27]),
.I1(curr_read_block[0]),
.I2(input_data[43]),
.I3(curr_read_block[1]),
.I4(input_data[11]),
.O(\xsdb_reg_reg[15] [11]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[12]_i_1
(.I0(input_data[28]),
.I1(curr_read_block[0]),
.I2(input_data[44]),
.I3(curr_read_block[1]),
.I4(input_data[12]),
.O(\xsdb_reg_reg[15] [12]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[13]_i_1
(.I0(input_data[29]),
.I1(curr_read_block[0]),
.I2(input_data[45]),
.I3(curr_read_block[1]),
.I4(input_data[13]),
.O(\xsdb_reg_reg[15] [13]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[14]_i_1
(.I0(input_data[30]),
.I1(curr_read_block[0]),
.I2(input_data[46]),
.I3(curr_read_block[1]),
.I4(input_data[14]),
.O(\xsdb_reg_reg[15] [14]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[15]_i_1__13
(.I0(input_data[31]),
.I1(curr_read_block[0]),
.I2(input_data[47]),
.I3(curr_read_block[1]),
.I4(input_data[15]),
.O(\xsdb_reg_reg[15] [15]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\xsdb_reg[1]_i_1
(.I0(input_data[49]),
.I1(input_data[17]),
.I2(curr_read_block[0]),
.I3(input_data[33]),
.I4(curr_read_block[1]),
.I5(input_data[1]),
.O(\xsdb_reg_reg[15] [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\xsdb_reg[2]_i_1
(.I0(input_data[50]),
.I1(input_data[18]),
.I2(curr_read_block[0]),
.I3(input_data[34]),
.I4(curr_read_block[1]),
.I5(input_data[2]),
.O(\xsdb_reg_reg[15] [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\xsdb_reg[3]_i_1
(.I0(input_data[51]),
.I1(input_data[19]),
.I2(curr_read_block[0]),
.I3(input_data[35]),
.I4(curr_read_block[1]),
.I5(input_data[3]),
.O(\xsdb_reg_reg[15] [3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\xsdb_reg[4]_i_1
(.I0(input_data[52]),
.I1(input_data[20]),
.I2(curr_read_block[0]),
.I3(input_data[36]),
.I4(curr_read_block[1]),
.I5(input_data[4]),
.O(\xsdb_reg_reg[15] [4]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[5]_i_1
(.I0(input_data[21]),
.I1(curr_read_block[0]),
.I2(input_data[37]),
.I3(curr_read_block[1]),
.I4(input_data[5]),
.O(\xsdb_reg_reg[15] [5]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[6]_i_1
(.I0(input_data[22]),
.I1(curr_read_block[0]),
.I2(input_data[38]),
.I3(curr_read_block[1]),
.I4(input_data[6]),
.O(\xsdb_reg_reg[15] [6]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[7]_i_1
(.I0(input_data[23]),
.I1(curr_read_block[0]),
.I2(input_data[39]),
.I3(curr_read_block[1]),
.I4(input_data[7]),
.O(\xsdb_reg_reg[15] [7]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[8]_i_1
(.I0(input_data[24]),
.I1(curr_read_block[0]),
.I2(input_data[40]),
.I3(curr_read_block[1]),
.I4(input_data[8]),
.O(\xsdb_reg_reg[15] [8]));
LUT5 #(
.INIT(32'h30BB3088))
\xsdb_reg[9]_i_1
(.I0(input_data[25]),
.I1(curr_read_block[0]),
.I2(input_data[41]),
.I3(curr_read_block[1]),
.I4(input_data[9]),
.O(\xsdb_reg_reg[15] [9]));
endmodule | 8 |
2,343 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[0] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[0] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[0] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_156 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[0] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[0] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[0] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_156 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,344 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_0
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[10] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[10] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[10] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_152 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_0
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[10] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[10] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[10] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_152 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,345 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_1
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[11] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[11] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[11] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_148 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_1
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[11] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[11] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[11] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_148 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,346 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_10
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[1] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[1] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[1] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_112 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_10
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[1] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[1] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[1] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_112 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,347 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_11
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[20] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[20] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[20] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_108 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_11
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[20] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[20] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[20] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_108 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,348 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_12
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[21] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[21] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[21] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_104 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_12
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[21] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[21] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[21] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_104 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,349 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_13
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[22] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[22] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[22] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_100 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_13
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[22] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[22] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[22] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_100 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,350 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_14
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[23] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[23] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[23] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_96 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_14
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[23] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[23] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[23] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_96 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,351 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_15
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[24] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[24] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[24] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_92 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_15
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[24] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[24] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[24] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_92 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,352 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_16
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[25] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[25] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[25] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_88 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_16
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[25] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[25] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[25] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_88 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,353 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_17
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[26] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[26] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[26] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_84 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_17
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[26] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[26] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[26] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_84 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,354 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_18
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[27] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[27] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[27] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_80 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_18
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[27] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[27] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[27] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_80 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,355 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_19
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[28] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[28] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[28] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_76 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_19
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[28] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[28] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[28] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_76 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,356 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_2
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[12] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[12] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[12] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_144 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_2
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[12] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[12] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[12] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_144 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,357 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_20
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[29] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[29] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[29] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_72 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_20
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[29] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[29] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[29] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_72 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,358 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_21
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[2] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[2] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[2] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_68 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_21
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[2] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[2] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[2] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_68 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,359 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_22
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[30] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[30] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[30] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_64 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_22
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[30] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[30] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[30] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_64 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,360 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_23
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[31] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[31] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[31] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_60 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_23
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[31] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[31] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[31] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_60 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,361 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_24
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[3] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[3] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[3] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_56 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_24
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[3] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[3] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[3] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_56 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,362 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_25
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[4] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[4] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[4] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_52 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_25
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[4] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[4] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[4] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_52 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,363 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_26
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[5] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[5] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[5] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_48 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_26
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[5] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[5] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[5] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_48 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,364 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_27
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[6] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[6] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[6] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_44 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_27
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[6] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[6] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[6] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_44 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,365 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_28
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[7] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[7] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[7] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_40 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_28
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[7] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[7] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[7] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_40 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,366 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_29
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[8] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[8] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[8] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_36 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_29
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[8] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[8] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[8] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_36 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,367 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_3
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[13] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[13] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[13] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_140 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_3
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[13] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[13] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[13] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_140 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,368 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_30
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[9] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[9] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[9] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_32 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_30
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[9] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[9] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[9] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_32 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,369 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_31
(\parallel_dout_reg[15] ,
Q,
out,
shift_en_reg,
s_dclk_o,
qual_strg_config_cs_serial_output,
D,
\reset_out_reg[3] ,
clk);
output [0:0]\parallel_dout_reg[15] ;
output [9:0]Q;
output out;
input [0:0]shift_en_reg;
input s_dclk_o;
input qual_strg_config_cs_serial_output;
input [9:0]D;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]\parallel_dout_reg[15] ;
wire qual_strg_config_cs_serial_output;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]shift_en_reg;
assign out = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(clk),
.out(match_dout),
.\parallel_dout_reg[15] (\parallel_dout_reg[15] ),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.shift_en_reg(shift_en_reg));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(clk),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_31
(\parallel_dout_reg[15] ,
Q,
out,
shift_en_reg,
s_dclk_o,
qual_strg_config_cs_serial_output,
D,
\reset_out_reg[3] ,
clk); |
output [0:0]\parallel_dout_reg[15] ;
output [9:0]Q;
output out;
input [0:0]shift_en_reg;
input s_dclk_o;
input qual_strg_config_cs_serial_output;
input [9:0]D;
input [0:0]\reset_out_reg[3] ;
input clk;
wire [9:0]D;
wire [9:0]Q;
wire clk;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]\parallel_dout_reg[15] ;
wire qual_strg_config_cs_serial_output;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]shift_en_reg;
assign out = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(clk),
.out(match_dout),
.\parallel_dout_reg[15] (\parallel_dout_reg[15] ),
.qual_strg_config_cs_serial_output(qual_strg_config_cs_serial_output),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.shift_en_reg(shift_en_reg));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(clk),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,370 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_4
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[14] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[14] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[14] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_136 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_4
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[14] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[14] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[14] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_136 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,371 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_5
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[15] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[15] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[15] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_132 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_5
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[15] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[15] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[15] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_132 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,372 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_6
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[16] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[16] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[16] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_128 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_6
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[16] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[16] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[16] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_128 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,373 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_7
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[17] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[17] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[17] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_124 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_7
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[17] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[17] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[17] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_124 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,374 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_8
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[18] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[18] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[18] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_120 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_8
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[18] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[18] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[18] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_120 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,375 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_9
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[19] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out);
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[19] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[19] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_116 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_9
(tc_config_cs_serial_input,
\TRIGGER_EQ_reg[19] ,
tc_config_cs_shift_en,
s_dclk_o,
tc_config_cs_serial_output,
D,
Q,
\reset_out_reg[3] ,
out); |
output [0:0]tc_config_cs_serial_input;
output [0:0]\TRIGGER_EQ_reg[19] ;
input [0:0]tc_config_cs_shift_en;
input s_dclk_o;
input [0:0]tc_config_cs_serial_output;
input [9:0]D;
input [9:0]Q;
input [0:0]\reset_out_reg[3] ;
input out;
wire [9:0]D;
wire [9:0]Q;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire out;
wire [0:0]\reset_out_reg[3] ;
wire s_dclk_o;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
wire [0:0]tc_config_cs_shift_en;
assign \TRIGGER_EQ_reg[19] [0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_116 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.Q(Q),
.clk(out),
.out(match_dout),
.\reset_out_reg[3] (\reset_out_reg[3] ),
.s_dclk_o(s_dclk_o),
.tc_config_cs_serial_input(tc_config_cs_serial_input),
.tc_config_cs_serial_output(tc_config_cs_serial_output),
.tc_config_cs_shift_en(tc_config_cs_shift_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(\reset_out_reg[3] ));
endmodule | 8 |
2,376 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data);
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized0
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data); |
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized0 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | 8 |
2,377 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
out);
output [0:0]mu_config_cs_serial_input;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input out;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized1
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
out); |
output [0:0]mu_config_cs_serial_input;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input out;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized1 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | 8 |
2,378 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized2
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data);
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized2 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized2
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data); |
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized2 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | 8 |
2,379 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized3
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
out);
output [0:0]mu_config_cs_serial_input;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input out;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized3 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized3
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
out); |
output [0:0]mu_config_cs_serial_input;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input out;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized3 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | 8 |
2,380 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized4
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data);
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized4 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized4
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data); |
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized4 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | 8 |
2,381 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized5
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
out);
output [0:0]mu_config_cs_serial_input;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input out;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized5 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized5
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
out); |
output [0:0]mu_config_cs_serial_input;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input out;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized5 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | 8 |
2,382 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized6
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data);
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized6 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized6
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data); |
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized6 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | 8 |
2,383 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized7
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
out);
output [0:0]mu_config_cs_serial_input;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input out;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized7 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized7
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
out); |
output [0:0]mu_config_cs_serial_input;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input out;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized7 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | 8 |
2,384 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized8
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data);
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized8 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized8
(mu_config_cs_serial_input,
all_dly1,
all_dly2,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
Q,
out,
probe_data); |
output [0:0]mu_config_cs_serial_input;
output [0:0]all_dly1;
output [0:0]all_dly2;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]Q;
input out;
input [0:0]probe_data;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire [0:0]probe_data;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized8 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.probe_data(probe_data),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | 8 |
2,385 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized9
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
out);
output [0:0]mu_config_cs_serial_input;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input out;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized9 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match__parameterized9
(mu_config_cs_serial_input,
D,
mu_config_cs_shift_en,
s_dclk_o,
mu_config_cs_serial_output,
all_dly1,
all_dly2,
Q,
out); |
output [0:0]mu_config_cs_serial_input;
output [0:0]D;
input [0:0]mu_config_cs_shift_en;
input s_dclk_o;
input [0:0]mu_config_cs_serial_output;
input [0:0]all_dly1;
input [0:0]all_dly2;
input [0:0]Q;
input out;
wire [0:0]Q;
wire [0:0]all_dly1;
wire [0:0]all_dly2;
(* async_reg = "true" *) wire dout_reg;
wire match_dout;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [0:0]mu_config_cs_shift_en;
wire out;
wire s_dclk_o;
assign D[0] = dout_reg;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA__parameterized9 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.Q(Q),
.all_dly1(all_dly1),
.all_dly2(all_dly2),
.clk(out),
.mu_config_cs_serial_input(mu_config_cs_serial_input),
.mu_config_cs_serial_output(mu_config_cs_serial_output),
.mu_config_cs_shift_en(mu_config_cs_shift_en),
.out(match_dout),
.s_dclk_o(s_dclk_o));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE \yes_output_reg.dout_reg_reg
(.C(out),
.CE(1'b1),
.D(match_dout),
.Q(dout_reg),
.R(Q));
endmodule | 8 |
2,386 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay
(\I_YESLUT6.I_YES_OREG.O_reg_reg ,
u_wcnt_hcmp_q,
E,
S_DCLK_O,
PROBES_I,
SRL_D_I);
output \I_YESLUT6.I_YES_OREG.O_reg_reg ;
output u_wcnt_hcmp_q;
input [0:0]E;
input S_DCLK_O;
input [29:0]PROBES_I;
input SRL_D_I;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [29:0]PROBES_I;
wire SRL_D_I;
wire S_DCLK_O;
wire u_wcnt_hcmp_q;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_186 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.PROBES_I(PROBES_I),
.SRL_D_I(SRL_D_I),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_hcmp_q(u_wcnt_hcmp_q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay
(\I_YESLUT6.I_YES_OREG.O_reg_reg ,
u_wcnt_hcmp_q,
E,
S_DCLK_O,
PROBES_I,
SRL_D_I); |
output \I_YESLUT6.I_YES_OREG.O_reg_reg ;
output u_wcnt_hcmp_q;
input [0:0]E;
input S_DCLK_O;
input [29:0]PROBES_I;
input SRL_D_I;
wire [0:0]E;
wire \I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [29:0]PROBES_I;
wire SRL_D_I;
wire S_DCLK_O;
wire u_wcnt_hcmp_q;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_186 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.E(E),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.PROBES_I(PROBES_I),
.SRL_D_I(SRL_D_I),
.S_DCLK_O(S_DCLK_O),
.u_wcnt_hcmp_q(u_wcnt_hcmp_q));
endmodule | 8 |
2,387 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_185
(Q,
SRL_Q_O,
u_wcnt_lcmp_q,
PROBES_I,
out,
E,
S_DCLK_O,
SRL_D_I);
output [14:0]Q;
output SRL_Q_O;
output u_wcnt_lcmp_q;
input [14:0]PROBES_I;
input out;
input [0:0]E;
input S_DCLK_O;
input SRL_D_I;
wire [0:0]E;
wire [14:0]PROBES_I;
wire [14:0]Q;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire out;
wire u_wcnt_lcmp_q;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.E(E),
.PROBES_I(PROBES_I),
.Q(Q),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O),
.out(out),
.u_wcnt_lcmp_q(u_wcnt_lcmp_q));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_185
(Q,
SRL_Q_O,
u_wcnt_lcmp_q,
PROBES_I,
out,
E,
S_DCLK_O,
SRL_D_I); |
output [14:0]Q;
output SRL_Q_O;
output u_wcnt_lcmp_q;
input [14:0]PROBES_I;
input out;
input [0:0]E;
input S_DCLK_O;
input SRL_D_I;
wire [0:0]E;
wire [14:0]PROBES_I;
wire [14:0]Q;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire out;
wire u_wcnt_lcmp_q;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.E(E),
.PROBES_I(PROBES_I),
.Q(Q),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O),
.out(out),
.u_wcnt_lcmp_q(u_wcnt_lcmp_q));
endmodule | 8 |
2,388 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_193
(SRL_Q_O,
DOUT_O,
D,
out,
E,
S_DCLK_O,
SRL_D_I);
output SRL_Q_O;
output DOUT_O;
input [14:0]D;
input out;
input [0:0]E;
input S_DCLK_O;
input SRL_D_I;
wire [14:0]D;
wire DOUT_O;
wire [0:0]E;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_194 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.DOUT_O(DOUT_O),
.E(E),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O),
.out(out));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_match_nodelay_193
(SRL_Q_O,
DOUT_O,
D,
out,
E,
S_DCLK_O,
SRL_D_I); |
output SRL_Q_O;
output DOUT_O;
input [14:0]D;
input out;
input [0:0]E;
input S_DCLK_O;
input SRL_D_I;
wire [14:0]D;
wire DOUT_O;
wire [0:0]E;
wire SRL_D_I;
wire SRL_Q_O;
wire S_DCLK_O;
wire out;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_allx_typeA_nodelay_194 \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst
(.D(D),
.DOUT_O(DOUT_O),
.E(E),
.SRL_D_I(SRL_D_I),
.SRL_Q_O(SRL_Q_O),
.S_DCLK_O(S_DCLK_O),
.out(out));
endmodule | 8 |
2,389 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection
(last_din,
D,
\reset_out_reg[0] ,
out,
clk,
Q,
dout_reg1_reg);
output last_din;
output [0:0]D;
output [0:0]\reset_out_reg[0] ;
input out;
input clk;
input [0:0]Q;
input [0:0]dout_reg1_reg;
wire [0:0]D;
wire [0:0]Q;
wire clk;
wire \dout_pulse[1]_i_1__0_n_0 ;
wire [0:0]dout_reg1_reg;
wire last_din;
wire out;
wire [1:1]p_0_in;
wire [0:0]\reset_out_reg[0] ;
LUT3 #(
.INIT(8'hF4))
\dout_pulse[1]_i_1__0
(.I0(last_din),
.I1(out),
.I2(p_0_in),
.O(\dout_pulse[1]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\dout_pulse_reg[0]
(.C(clk),
.CE(1'b1),
.D(dout_reg1_reg),
.Q(p_0_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\dout_pulse_reg[1]
(.C(clk),
.CE(1'b1),
.D(\dout_pulse[1]_i_1__0_n_0 ),
.Q(\reset_out_reg[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
last_din_reg
(.C(clk),
.CE(1'b1),
.D(out),
.Q(last_din),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\reset_out[0]_i_1
(.I0(Q),
.I1(\reset_out_reg[0] ),
.O(D));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection
(last_din,
D,
\reset_out_reg[0] ,
out,
clk,
Q,
dout_reg1_reg); |
output last_din;
output [0:0]D;
output [0:0]\reset_out_reg[0] ;
input out;
input clk;
input [0:0]Q;
input [0:0]dout_reg1_reg;
wire [0:0]D;
wire [0:0]Q;
wire clk;
wire \dout_pulse[1]_i_1__0_n_0 ;
wire [0:0]dout_reg1_reg;
wire last_din;
wire out;
wire [1:1]p_0_in;
wire [0:0]\reset_out_reg[0] ;
LUT3 #(
.INIT(8'hF4))
\dout_pulse[1]_i_1__0
(.I0(last_din),
.I1(out),
.I2(p_0_in),
.O(\dout_pulse[1]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\dout_pulse_reg[0]
(.C(clk),
.CE(1'b1),
.D(dout_reg1_reg),
.Q(p_0_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\dout_pulse_reg[1]
(.C(clk),
.CE(1'b1),
.D(\dout_pulse[1]_i_1__0_n_0 ),
.Q(\reset_out_reg[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
last_din_reg
(.C(clk),
.CE(1'b1),
.D(out),
.Q(last_din),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\reset_out[0]_i_1
(.I0(Q),
.I1(\reset_out_reg[0] ),
.O(D));
endmodule | 8 |
2,390 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection_163
(last_din,
SS,
halt_out_reg,
out,
clk,
prev_cap_done,
cap_done,
halt_out,
Q,
\dout_pulse_reg[1]_0 ,
D);
output last_din;
output [0:0]SS;
output halt_out_reg;
input out;
input clk;
input prev_cap_done;
input cap_done;
input halt_out;
input [0:0]Q;
input [0:0]\dout_pulse_reg[1]_0 ;
input [0:0]D;
wire [0:0]D;
wire [0:0]Q;
wire [0:0]SS;
wire cap_done;
wire clk;
wire \dout_pulse[1]_i_1_n_0 ;
wire [0:0]\dout_pulse_reg[1]_0 ;
wire halt_in_detection;
wire halt_out;
wire halt_out_reg;
wire last_din;
wire out;
wire [1:1]p_0_in;
wire prev_cap_done;
LUT3 #(
.INIT(8'hF4))
\dout_pulse[1]_i_1
(.I0(last_din),
.I1(out),
.I2(p_0_in),
.O(\dout_pulse[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\dout_pulse_reg[0]
(.C(clk),
.CE(1'b1),
.D(D),
.Q(p_0_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\dout_pulse_reg[1]
(.C(clk),
.CE(1'b1),
.D(\dout_pulse[1]_i_1_n_0 ),
.Q(halt_in_detection),
.R(1'b0));
LUT4 #(
.INIT(16'h00AE))
halt_out_i_1
(.I0(halt_out),
.I1(halt_in_detection),
.I2(Q),
.I3(\dout_pulse_reg[1]_0 ),
.O(halt_out_reg));
FDRE #(
.INIT(1'b0))
last_din_reg
(.C(clk),
.CE(1'b1),
.D(out),
.Q(last_din),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\reset_out[5]_i_1
(.I0(halt_in_detection),
.I1(prev_cap_done),
.I2(cap_done),
.O(SS));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ltlib_v1_0_0_rising_edge_detection_163
(last_din,
SS,
halt_out_reg,
out,
clk,
prev_cap_done,
cap_done,
halt_out,
Q,
\dout_pulse_reg[1]_0 ,
D); |
output last_din;
output [0:0]SS;
output halt_out_reg;
input out;
input clk;
input prev_cap_done;
input cap_done;
input halt_out;
input [0:0]Q;
input [0:0]\dout_pulse_reg[1]_0 ;
input [0:0]D;
wire [0:0]D;
wire [0:0]Q;
wire [0:0]SS;
wire cap_done;
wire clk;
wire \dout_pulse[1]_i_1_n_0 ;
wire [0:0]\dout_pulse_reg[1]_0 ;
wire halt_in_detection;
wire halt_out;
wire halt_out_reg;
wire last_din;
wire out;
wire [1:1]p_0_in;
wire prev_cap_done;
LUT3 #(
.INIT(8'hF4))
\dout_pulse[1]_i_1
(.I0(last_din),
.I1(out),
.I2(p_0_in),
.O(\dout_pulse[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\dout_pulse_reg[0]
(.C(clk),
.CE(1'b1),
.D(D),
.Q(p_0_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\dout_pulse_reg[1]
(.C(clk),
.CE(1'b1),
.D(\dout_pulse[1]_i_1_n_0 ),
.Q(halt_in_detection),
.R(1'b0));
LUT4 #(
.INIT(16'h00AE))
halt_out_i_1
(.I0(halt_out),
.I1(halt_in_detection),
.I2(Q),
.I3(\dout_pulse_reg[1]_0 ),
.O(halt_out_reg));
FDRE #(
.INIT(1'b0))
last_din_reg
(.C(clk),
.CE(1'b1),
.D(out),
.Q(last_din),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\reset_out[5]_i_1
(.I0(halt_in_detection),
.I1(prev_cap_done),
.I2(cap_done),
.O(SS));
endmodule | 8 |
2,391 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized28
(\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[4] ,
s_daddr_o,
\xsdb_reg_reg[5] ,
halt_ctrl,
\xsdb_reg_reg[4] ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] );
output \slaveRegDo_mux_0_reg[5] ;
output [12:0]\slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[4] ;
input [5:0]s_daddr_o;
input \xsdb_reg_reg[5] ;
input halt_ctrl;
input \xsdb_reg_reg[4] ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire halt_ctrl;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [12:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \xsdb_reg_reg[4] ;
wire \xsdb_reg_reg[5] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_174 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.halt_ctrl(halt_ctrl),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
.\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized28
(\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[4] ,
s_daddr_o,
\xsdb_reg_reg[5] ,
halt_ctrl,
\xsdb_reg_reg[4] ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ); |
output \slaveRegDo_mux_0_reg[5] ;
output [12:0]\slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[4] ;
input [5:0]s_daddr_o;
input \xsdb_reg_reg[5] ;
input halt_ctrl;
input \xsdb_reg_reg[4] ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire halt_ctrl;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [12:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \xsdb_reg_reg[4] ;
wire \xsdb_reg_reg[5] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_174 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.halt_ctrl(halt_ctrl),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
.\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ));
endmodule | 8 |
2,392 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized29
(\slaveRegDo_mux_0_reg[15] ,
\xsdb_reg_reg[0] ,
\slaveRegDo_mux_0_reg[0] ,
u_scnt_cmp_q,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
halt_ctrl,
scnt_cmp_temp,
wcnt_lcmp_temp,
wcnt_hcmp_temp,
s_daddr_o,
\xsdb_reg_reg[15] ,
s_dwe_o,
s_den_o,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_di_o,
s_dclk_o,
DOUT_O,
shift_en_reg,
shift_en_reg_0);
output \slaveRegDo_mux_0_reg[15] ;
output \xsdb_reg_reg[0] ;
output \slaveRegDo_mux_0_reg[0] ;
output u_scnt_cmp_q;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output halt_ctrl;
output scnt_cmp_temp;
output wcnt_lcmp_temp;
output wcnt_hcmp_temp;
input [6:0]s_daddr_o;
input [12:0]\xsdb_reg_reg[15] ;
input s_dwe_o;
input s_den_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input [15:0]s_di_o;
input s_dclk_o;
input DOUT_O;
input shift_en_reg;
input shift_en_reg_0;
wire DOUT_O;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire halt_ctrl;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire scnt_cmp_temp;
wire shift_en_reg;
wire shift_en_reg_0;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire u_scnt_cmp_q;
wire wcnt_hcmp_temp;
wire wcnt_lcmp_temp;
wire \xsdb_reg_reg[0] ;
wire [12:0]\xsdb_reg_reg[15] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized0 \I_EN_CTL_EQ1.U_CTL
(.DOUT_O(DOUT_O),
.\G_1PIPE_IFACE.s_daddr_r_reg[9] (\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.halt_ctrl(halt_ctrl),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.scnt_cmp_temp(scnt_cmp_temp),
.shift_en_reg(shift_en_reg),
.shift_en_reg_0(shift_en_reg_0),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.u_scnt_cmp_q(u_scnt_cmp_q),
.wcnt_hcmp_temp(wcnt_hcmp_temp),
.wcnt_lcmp_temp(wcnt_lcmp_temp),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized29
(\slaveRegDo_mux_0_reg[15] ,
\xsdb_reg_reg[0] ,
\slaveRegDo_mux_0_reg[0] ,
u_scnt_cmp_q,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
halt_ctrl,
scnt_cmp_temp,
wcnt_lcmp_temp,
wcnt_hcmp_temp,
s_daddr_o,
\xsdb_reg_reg[15] ,
s_dwe_o,
s_den_o,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_di_o,
s_dclk_o,
DOUT_O,
shift_en_reg,
shift_en_reg_0); |
output \slaveRegDo_mux_0_reg[15] ;
output \xsdb_reg_reg[0] ;
output \slaveRegDo_mux_0_reg[0] ;
output u_scnt_cmp_q;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output halt_ctrl;
output scnt_cmp_temp;
output wcnt_lcmp_temp;
output wcnt_hcmp_temp;
input [6:0]s_daddr_o;
input [12:0]\xsdb_reg_reg[15] ;
input s_dwe_o;
input s_den_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input [15:0]s_di_o;
input s_dclk_o;
input DOUT_O;
input shift_en_reg;
input shift_en_reg_0;
wire DOUT_O;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire halt_ctrl;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire scnt_cmp_temp;
wire shift_en_reg;
wire shift_en_reg_0;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire u_scnt_cmp_q;
wire wcnt_hcmp_temp;
wire wcnt_lcmp_temp;
wire \xsdb_reg_reg[0] ;
wire [12:0]\xsdb_reg_reg[15] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized0 \I_EN_CTL_EQ1.U_CTL
(.DOUT_O(DOUT_O),
.\G_1PIPE_IFACE.s_daddr_r_reg[9] (\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.halt_ctrl(halt_ctrl),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.scnt_cmp_temp(scnt_cmp_temp),
.shift_en_reg(shift_en_reg),
.shift_en_reg_0(shift_en_reg_0),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.u_scnt_cmp_q(u_scnt_cmp_q),
.wcnt_hcmp_temp(wcnt_hcmp_temp),
.wcnt_lcmp_temp(wcnt_lcmp_temp),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ));
endmodule | 8 |
2,393 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized30
(\slaveRegDo_mux_0_reg[0] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
s_daddr_o,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
s_den_o,
CAP_DONE_O_reg,
s_dclk_o);
output \slaveRegDo_mux_0_reg[0] ;
output \slaveRegDo_mux_0_reg[3] ;
output [1:0]\slaveRegDo_mux_0_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input [1:0]s_daddr_o;
input [1:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
input s_den_o;
input [3:0]CAP_DONE_O_reg;
input s_dclk_o;
wire [3:0]CAP_DONE_O_reg;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
wire [1:0]Q;
wire [1:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire [1:0]\slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_173 \I_EN_STAT_EQ1.U_STAT
(.CAP_DONE_O_reg(CAP_DONE_O_reg),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
.Q(Q),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized30
(\slaveRegDo_mux_0_reg[0] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
s_daddr_o,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
s_den_o,
CAP_DONE_O_reg,
s_dclk_o); |
output \slaveRegDo_mux_0_reg[0] ;
output \slaveRegDo_mux_0_reg[3] ;
output [1:0]\slaveRegDo_mux_0_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input [1:0]s_daddr_o;
input [1:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
input s_den_o;
input [3:0]CAP_DONE_O_reg;
input s_dclk_o;
wire [3:0]CAP_DONE_O_reg;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
wire [1:0]Q;
wire [1:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire [1:0]\slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_173 \I_EN_STAT_EQ1.U_STAT
(.CAP_DONE_O_reg(CAP_DONE_O_reg),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
.Q(Q),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ));
endmodule | 8 |
2,394 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized31
(\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[1] ,
Q,
s_daddr_o,
\xsdb_reg_reg[2] ,
\xsdb_reg_reg[4] ,
s_den_o,
\captured_samples_reg[14] ,
s_dclk_o);
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[1] ;
output [11:0]Q;
input [3:0]s_daddr_o;
input [1:0]\xsdb_reg_reg[2] ;
input \xsdb_reg_reg[4] ;
input s_den_o;
input [14:0]\captured_samples_reg[14] ;
input s_dclk_o;
wire [11:0]Q;
wire [14:0]\captured_samples_reg[14] ;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire [1:0]\xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[4] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_164 \I_EN_STAT_EQ1.U_STAT
(.Q(Q),
.\captured_samples_reg[14] (\captured_samples_reg[14] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized31
(\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[1] ,
Q,
s_daddr_o,
\xsdb_reg_reg[2] ,
\xsdb_reg_reg[4] ,
s_den_o,
\captured_samples_reg[14] ,
s_dclk_o); |
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[1] ;
output [11:0]Q;
input [3:0]s_daddr_o;
input [1:0]\xsdb_reg_reg[2] ;
input \xsdb_reg_reg[4] ;
input s_den_o;
input [14:0]\captured_samples_reg[14] ;
input s_dclk_o;
wire [11:0]Q;
wire [14:0]\captured_samples_reg[14] ;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire [1:0]\xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[4] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_164 \I_EN_STAT_EQ1.U_STAT
(.Q(Q),
.\captured_samples_reg[14] (\captured_samples_reg[14] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ));
endmodule | 8 |
2,395 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized43
(\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[5] ,
D,
\xsdb_reg_reg[0] ,
\xsdb_reg_reg[0]_0 ,
use_probe_debug_circuit_1,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
SR,
s_daddr_o,
read_reset_addr,
\xsdb_reg_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\xsdb_reg_reg[11] ,
\xsdb_reg_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ,
s_den_o,
s_dwe_o,
\xsdb_reg_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
\xsdb_reg_reg[1]_0 ,
\xsdb_reg_reg[1]_1 ,
\xsdb_reg_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
\xsdb_reg_reg[2]_0 ,
\xsdb_reg_reg[6] ,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
\xsdb_reg_reg[6]_0 ,
\xsdb_reg_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ,
\xsdb_reg_reg[7]_0 ,
\xsdb_reg_reg[8] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ,
\xsdb_reg_reg[8]_0 ,
\xsdb_reg_reg[9] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ,
\xsdb_reg_reg[9]_0 ,
\xsdb_reg_reg[10] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ,
\xsdb_reg_reg[10]_0 ,
\xsdb_reg_reg[13] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ,
\xsdb_reg_reg[13]_0 ,
\xsdb_reg_reg[14] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ,
\xsdb_reg_reg[14]_0 ,
s_di_o,
s_dclk_o);
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[5] ;
output [1:0]D;
output \xsdb_reg_reg[0] ;
output \xsdb_reg_reg[0]_0 ;
output use_probe_debug_circuit_1;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output [0:0]SR;
input [12:0]s_daddr_o;
input [11:0]read_reset_addr;
input \xsdb_reg_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \xsdb_reg_reg[11] ;
input \xsdb_reg_reg[5] ;
input [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
input s_den_o;
input s_dwe_o;
input \xsdb_reg_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
input \xsdb_reg_reg[1]_0 ;
input \xsdb_reg_reg[1]_1 ;
input \xsdb_reg_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
input \xsdb_reg_reg[2]_0 ;
input \xsdb_reg_reg[6] ;
input [6:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
input \xsdb_reg_reg[6]_0 ;
input \xsdb_reg_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
input \xsdb_reg_reg[7]_0 ;
input \xsdb_reg_reg[8] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
input \xsdb_reg_reg[8]_0 ;
input \xsdb_reg_reg[9] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
input \xsdb_reg_reg[9]_0 ;
input \xsdb_reg_reg[10] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
input \xsdb_reg_reg[10]_0 ;
input \xsdb_reg_reg[13] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
input \xsdb_reg_reg[13]_0 ;
input \xsdb_reg_reg[14] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
input \xsdb_reg_reg[14]_0 ;
input [15:0]s_di_o;
input s_dclk_o;
wire [1:0]D;
wire [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [6:0]Q;
wire [0:0]SR;
wire [11:0]read_reset_addr;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire use_probe_debug_circuit_1;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[10] ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[11] ;
wire \xsdb_reg_reg[12] ;
wire \xsdb_reg_reg[13] ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[14] ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[1] ;
wire \xsdb_reg_reg[1]_0 ;
wire \xsdb_reg_reg[1]_1 ;
wire \xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[2]_0 ;
wire \xsdb_reg_reg[5] ;
wire \xsdb_reg_reg[6] ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[7] ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[8] ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[9] ;
wire \xsdb_reg_reg[9]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_179 \I_EN_CTL_EQ1.U_CTL
(.D(D),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.Q(Q),
.SR(SR),
.read_reset_addr(read_reset_addr),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.use_probe_debug_circuit_1(use_probe_debug_circuit_1),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ),
.\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
.\xsdb_reg_reg[10]_1 (\xsdb_reg_reg[10]_0 ),
.\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
.\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
.\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
.\xsdb_reg_reg[13]_1 (\xsdb_reg_reg[13]_0 ),
.\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
.\xsdb_reg_reg[14]_1 (\xsdb_reg_reg[14]_0 ),
.\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
.\xsdb_reg_reg[1]_1 (\xsdb_reg_reg[1]_0 ),
.\xsdb_reg_reg[1]_2 (\xsdb_reg_reg[1]_1 ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[2]_1 (\xsdb_reg_reg[2]_0 ),
.\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
.\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
.\xsdb_reg_reg[6]_1 (\xsdb_reg_reg[6]_0 ),
.\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
.\xsdb_reg_reg[7]_1 (\xsdb_reg_reg[7]_0 ),
.\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
.\xsdb_reg_reg[8]_1 (\xsdb_reg_reg[8]_0 ),
.\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ),
.\xsdb_reg_reg[9]_1 (\xsdb_reg_reg[9]_0 ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized43
(\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[5] ,
D,
\xsdb_reg_reg[0] ,
\xsdb_reg_reg[0]_0 ,
use_probe_debug_circuit_1,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
SR,
s_daddr_o,
read_reset_addr,
\xsdb_reg_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\xsdb_reg_reg[11] ,
\xsdb_reg_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ,
s_den_o,
s_dwe_o,
\xsdb_reg_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
\xsdb_reg_reg[1]_0 ,
\xsdb_reg_reg[1]_1 ,
\xsdb_reg_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
\xsdb_reg_reg[2]_0 ,
\xsdb_reg_reg[6] ,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
\xsdb_reg_reg[6]_0 ,
\xsdb_reg_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ,
\xsdb_reg_reg[7]_0 ,
\xsdb_reg_reg[8] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ,
\xsdb_reg_reg[8]_0 ,
\xsdb_reg_reg[9] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ,
\xsdb_reg_reg[9]_0 ,
\xsdb_reg_reg[10] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ,
\xsdb_reg_reg[10]_0 ,
\xsdb_reg_reg[13] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ,
\xsdb_reg_reg[13]_0 ,
\xsdb_reg_reg[14] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ,
\xsdb_reg_reg[14]_0 ,
s_di_o,
s_dclk_o); |
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[5] ;
output [1:0]D;
output \xsdb_reg_reg[0] ;
output \xsdb_reg_reg[0]_0 ;
output use_probe_debug_circuit_1;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output [0:0]SR;
input [12:0]s_daddr_o;
input [11:0]read_reset_addr;
input \xsdb_reg_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \xsdb_reg_reg[11] ;
input \xsdb_reg_reg[5] ;
input [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
input s_den_o;
input s_dwe_o;
input \xsdb_reg_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
input \xsdb_reg_reg[1]_0 ;
input \xsdb_reg_reg[1]_1 ;
input \xsdb_reg_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
input \xsdb_reg_reg[2]_0 ;
input \xsdb_reg_reg[6] ;
input [6:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
input \xsdb_reg_reg[6]_0 ;
input \xsdb_reg_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
input \xsdb_reg_reg[7]_0 ;
input \xsdb_reg_reg[8] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
input \xsdb_reg_reg[8]_0 ;
input \xsdb_reg_reg[9] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
input \xsdb_reg_reg[9]_0 ;
input \xsdb_reg_reg[10] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
input \xsdb_reg_reg[10]_0 ;
input \xsdb_reg_reg[13] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
input \xsdb_reg_reg[13]_0 ;
input \xsdb_reg_reg[14] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
input \xsdb_reg_reg[14]_0 ;
input [15:0]s_di_o;
input s_dclk_o;
wire [1:0]D;
wire [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [6:0]Q;
wire [0:0]SR;
wire [11:0]read_reset_addr;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire use_probe_debug_circuit_1;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[10] ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[11] ;
wire \xsdb_reg_reg[12] ;
wire \xsdb_reg_reg[13] ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[14] ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[1] ;
wire \xsdb_reg_reg[1]_0 ;
wire \xsdb_reg_reg[1]_1 ;
wire \xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[2]_0 ;
wire \xsdb_reg_reg[5] ;
wire \xsdb_reg_reg[6] ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[7] ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[8] ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[9] ;
wire \xsdb_reg_reg[9]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_179 \I_EN_CTL_EQ1.U_CTL
(.D(D),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.Q(Q),
.SR(SR),
.read_reset_addr(read_reset_addr),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.use_probe_debug_circuit_1(use_probe_debug_circuit_1),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ),
.\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
.\xsdb_reg_reg[10]_1 (\xsdb_reg_reg[10]_0 ),
.\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
.\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
.\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
.\xsdb_reg_reg[13]_1 (\xsdb_reg_reg[13]_0 ),
.\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
.\xsdb_reg_reg[14]_1 (\xsdb_reg_reg[14]_0 ),
.\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
.\xsdb_reg_reg[1]_1 (\xsdb_reg_reg[1]_0 ),
.\xsdb_reg_reg[1]_2 (\xsdb_reg_reg[1]_1 ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[2]_1 (\xsdb_reg_reg[2]_0 ),
.\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
.\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
.\xsdb_reg_reg[6]_1 (\xsdb_reg_reg[6]_0 ),
.\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
.\xsdb_reg_reg[7]_1 (\xsdb_reg_reg[7]_0 ),
.\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
.\xsdb_reg_reg[8]_1 (\xsdb_reg_reg[8]_0 ),
.\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ),
.\xsdb_reg_reg[9]_1 (\xsdb_reg_reg[9]_0 ));
endmodule | 8 |
2,396 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized44
(\xsdb_reg_reg[15] ,
\slaveRegDo_mux_0_reg[15] ,
read_reset_addr,
s_daddr_o,
s_dwe_o,
s_den_o,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_di_o,
s_dclk_o);
output \xsdb_reg_reg[15] ;
output \slaveRegDo_mux_0_reg[15] ;
output [14:0]read_reset_addr;
input [6:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire [14:0]read_reset_addr;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[15] ;
wire \xsdb_reg_reg[15] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_178 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[9] (\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.read_reset_addr(read_reset_addr),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized44
(\xsdb_reg_reg[15] ,
\slaveRegDo_mux_0_reg[15] ,
read_reset_addr,
s_daddr_o,
s_dwe_o,
s_den_o,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_di_o,
s_dclk_o); |
output \xsdb_reg_reg[15] ;
output \slaveRegDo_mux_0_reg[15] ;
output [14:0]read_reset_addr;
input [6:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire [14:0]read_reset_addr;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[15] ;
wire \xsdb_reg_reg[15] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_178 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[9] (\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.read_reset_addr(read_reset_addr),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ));
endmodule | 8 |
2,397 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized45
(D,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
s_dwe_o,
s_den_o,
\xsdb_reg_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\xsdb_reg_reg[15] ,
\xsdb_reg_reg[15]_0 ,
read_reset_addr,
\xsdb_reg_reg[4] ,
\xsdb_reg_reg[3] ,
SR,
s_di_o,
s_dclk_o);
output [0:0]D;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
input [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [6:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input s_dwe_o;
input s_den_o;
input \xsdb_reg_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \xsdb_reg_reg[15] ;
input \xsdb_reg_reg[15]_0 ;
input [2:0]read_reset_addr;
input \xsdb_reg_reg[4] ;
input \xsdb_reg_reg[3] ;
input [0:0]SR;
input [15:0]s_di_o;
input s_dclk_o;
wire [0:0]D;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [0:0]SR;
wire [2:0]read_reset_addr;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[15] ;
wire \xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg[3] ;
wire \xsdb_reg_reg[4] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_177 \I_EN_CTL_EQ1.U_CTL
(.D(D),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.SR(SR),
.read_reset_addr(read_reset_addr),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
.\xsdb_reg_reg[15]_1 (\xsdb_reg_reg[15]_0 ),
.\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized45
(D,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
s_dwe_o,
s_den_o,
\xsdb_reg_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\xsdb_reg_reg[15] ,
\xsdb_reg_reg[15]_0 ,
read_reset_addr,
\xsdb_reg_reg[4] ,
\xsdb_reg_reg[3] ,
SR,
s_di_o,
s_dclk_o); |
output [0:0]D;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
input [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [6:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input s_dwe_o;
input s_den_o;
input \xsdb_reg_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \xsdb_reg_reg[15] ;
input \xsdb_reg_reg[15]_0 ;
input [2:0]read_reset_addr;
input \xsdb_reg_reg[4] ;
input \xsdb_reg_reg[3] ;
input [0:0]SR;
input [15:0]s_di_o;
input s_dclk_o;
wire [0:0]D;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [0:0]SR;
wire [2:0]read_reset_addr;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[15] ;
wire \xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg[3] ;
wire \xsdb_reg_reg[4] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_177 \I_EN_CTL_EQ1.U_CTL
(.D(D),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.SR(SR),
.read_reset_addr(read_reset_addr),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
.\xsdb_reg_reg[15]_1 (\xsdb_reg_reg[15]_0 ),
.\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ));
endmodule | 8 |
2,398 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized46
(\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[5] ,
s_daddr_o,
\xsdb_reg_reg[14] ,
\xsdb_reg_reg[14]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\xsdb_reg_reg[13] ,
\xsdb_reg_reg[13]_0 ,
\xsdb_reg_reg[10] ,
\xsdb_reg_reg[10]_0 ,
\xsdb_reg_reg[9] ,
\xsdb_reg_reg[9]_0 ,
\xsdb_reg_reg[8] ,
\xsdb_reg_reg[8]_0 ,
\xsdb_reg_reg[7] ,
\xsdb_reg_reg[7]_0 ,
\xsdb_reg_reg[6] ,
\xsdb_reg_reg[6]_0 ,
\xsdb_reg_reg[2] ,
capture_qual_ctrl_1,
\xsdb_reg_reg[1] ,
\xsdb_reg_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
\xsdb_reg_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
\xsdb_reg_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
\xsdb_reg_reg[5]_0 ,
\xsdb_reg_reg[5]_1 ,
\xsdb_reg_reg[11]_0 ,
\xsdb_reg_reg[11]_1 ,
\xsdb_reg_reg[12]_0 ,
\xsdb_reg_reg[12]_1 ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 );
output \slaveRegDo_mux_0_reg[14] ;
output [3:0]\slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[5] ;
input [5:0]s_daddr_o;
input \xsdb_reg_reg[14] ;
input \xsdb_reg_reg[14]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \xsdb_reg_reg[13] ;
input \xsdb_reg_reg[13]_0 ;
input \xsdb_reg_reg[10] ;
input \xsdb_reg_reg[10]_0 ;
input \xsdb_reg_reg[9] ;
input \xsdb_reg_reg[9]_0 ;
input \xsdb_reg_reg[8] ;
input \xsdb_reg_reg[8]_0 ;
input \xsdb_reg_reg[7] ;
input \xsdb_reg_reg[7]_0 ;
input \xsdb_reg_reg[6] ;
input \xsdb_reg_reg[6]_0 ;
input \xsdb_reg_reg[2] ;
input [1:0]capture_qual_ctrl_1;
input \xsdb_reg_reg[1] ;
input \xsdb_reg_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [2:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
input \xsdb_reg_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
input \xsdb_reg_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
input \xsdb_reg_reg[5]_0 ;
input \xsdb_reg_reg[5]_1 ;
input \xsdb_reg_reg[11]_0 ;
input \xsdb_reg_reg[11]_1 ;
input \xsdb_reg_reg[12]_0 ;
input \xsdb_reg_reg[12]_1 ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire [2:0]Q;
wire [1:0]capture_qual_ctrl_1;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire [3:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg_reg[10] ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[11] ;
wire \xsdb_reg_reg[11]_0 ;
wire \xsdb_reg_reg[11]_1 ;
wire \xsdb_reg_reg[12] ;
wire \xsdb_reg_reg[12]_0 ;
wire \xsdb_reg_reg[12]_1 ;
wire \xsdb_reg_reg[13] ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[14] ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[1] ;
wire \xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[5] ;
wire \xsdb_reg_reg[5]_0 ;
wire \xsdb_reg_reg[5]_1 ;
wire \xsdb_reg_reg[6] ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[7] ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[8] ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[9] ;
wire \xsdb_reg_reg[9]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_176 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.Q(Q),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
.\xsdb_reg_reg[10]_1 (\xsdb_reg_reg[10]_0 ),
.\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
.\xsdb_reg_reg[11]_1 (\xsdb_reg_reg[11]_0 ),
.\xsdb_reg_reg[11]_2 (\xsdb_reg_reg[11]_1 ),
.\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
.\xsdb_reg_reg[12]_1 (\xsdb_reg_reg[12]_0 ),
.\xsdb_reg_reg[12]_2 (\xsdb_reg_reg[12]_1 ),
.\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
.\xsdb_reg_reg[13]_1 (\xsdb_reg_reg[13]_0 ),
.\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
.\xsdb_reg_reg[14]_1 (\xsdb_reg_reg[14]_0 ),
.\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
.\xsdb_reg_reg[5]_1 (\xsdb_reg_reg[5]_0 ),
.\xsdb_reg_reg[5]_2 (\xsdb_reg_reg[5]_1 ),
.\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
.\xsdb_reg_reg[6]_1 (\xsdb_reg_reg[6]_0 ),
.\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
.\xsdb_reg_reg[7]_1 (\xsdb_reg_reg[7]_0 ),
.\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
.\xsdb_reg_reg[8]_1 (\xsdb_reg_reg[8]_0 ),
.\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ),
.\xsdb_reg_reg[9]_1 (\xsdb_reg_reg[9]_0 ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized46
(\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[5] ,
s_daddr_o,
\xsdb_reg_reg[14] ,
\xsdb_reg_reg[14]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\xsdb_reg_reg[13] ,
\xsdb_reg_reg[13]_0 ,
\xsdb_reg_reg[10] ,
\xsdb_reg_reg[10]_0 ,
\xsdb_reg_reg[9] ,
\xsdb_reg_reg[9]_0 ,
\xsdb_reg_reg[8] ,
\xsdb_reg_reg[8]_0 ,
\xsdb_reg_reg[7] ,
\xsdb_reg_reg[7]_0 ,
\xsdb_reg_reg[6] ,
\xsdb_reg_reg[6]_0 ,
\xsdb_reg_reg[2] ,
capture_qual_ctrl_1,
\xsdb_reg_reg[1] ,
\xsdb_reg_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
\xsdb_reg_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
\xsdb_reg_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
\xsdb_reg_reg[5]_0 ,
\xsdb_reg_reg[5]_1 ,
\xsdb_reg_reg[11]_0 ,
\xsdb_reg_reg[11]_1 ,
\xsdb_reg_reg[12]_0 ,
\xsdb_reg_reg[12]_1 ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ); |
output \slaveRegDo_mux_0_reg[14] ;
output [3:0]\slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[5] ;
input [5:0]s_daddr_o;
input \xsdb_reg_reg[14] ;
input \xsdb_reg_reg[14]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \xsdb_reg_reg[13] ;
input \xsdb_reg_reg[13]_0 ;
input \xsdb_reg_reg[10] ;
input \xsdb_reg_reg[10]_0 ;
input \xsdb_reg_reg[9] ;
input \xsdb_reg_reg[9]_0 ;
input \xsdb_reg_reg[8] ;
input \xsdb_reg_reg[8]_0 ;
input \xsdb_reg_reg[7] ;
input \xsdb_reg_reg[7]_0 ;
input \xsdb_reg_reg[6] ;
input \xsdb_reg_reg[6]_0 ;
input \xsdb_reg_reg[2] ;
input [1:0]capture_qual_ctrl_1;
input \xsdb_reg_reg[1] ;
input \xsdb_reg_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [2:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
input \xsdb_reg_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
input \xsdb_reg_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
input \xsdb_reg_reg[5]_0 ;
input \xsdb_reg_reg[5]_1 ;
input \xsdb_reg_reg[11]_0 ;
input \xsdb_reg_reg[11]_1 ;
input \xsdb_reg_reg[12]_0 ;
input \xsdb_reg_reg[12]_1 ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire [2:0]Q;
wire [1:0]capture_qual_ctrl_1;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire [3:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg_reg[10] ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[11] ;
wire \xsdb_reg_reg[11]_0 ;
wire \xsdb_reg_reg[11]_1 ;
wire \xsdb_reg_reg[12] ;
wire \xsdb_reg_reg[12]_0 ;
wire \xsdb_reg_reg[12]_1 ;
wire \xsdb_reg_reg[13] ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[14] ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[1] ;
wire \xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[5] ;
wire \xsdb_reg_reg[5]_0 ;
wire \xsdb_reg_reg[5]_1 ;
wire \xsdb_reg_reg[6] ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[7] ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[8] ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[9] ;
wire \xsdb_reg_reg[9]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_176 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.Q(Q),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
.\xsdb_reg_reg[10]_1 (\xsdb_reg_reg[10]_0 ),
.\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
.\xsdb_reg_reg[11]_1 (\xsdb_reg_reg[11]_0 ),
.\xsdb_reg_reg[11]_2 (\xsdb_reg_reg[11]_1 ),
.\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
.\xsdb_reg_reg[12]_1 (\xsdb_reg_reg[12]_0 ),
.\xsdb_reg_reg[12]_2 (\xsdb_reg_reg[12]_1 ),
.\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
.\xsdb_reg_reg[13]_1 (\xsdb_reg_reg[13]_0 ),
.\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
.\xsdb_reg_reg[14]_1 (\xsdb_reg_reg[14]_0 ),
.\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
.\xsdb_reg_reg[5]_1 (\xsdb_reg_reg[5]_0 ),
.\xsdb_reg_reg[5]_2 (\xsdb_reg_reg[5]_1 ),
.\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
.\xsdb_reg_reg[6]_1 (\xsdb_reg_reg[6]_0 ),
.\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
.\xsdb_reg_reg[7]_1 (\xsdb_reg_reg[7]_0 ),
.\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
.\xsdb_reg_reg[8]_1 (\xsdb_reg_reg[8]_0 ),
.\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ),
.\xsdb_reg_reg[9]_1 (\xsdb_reg_reg[9]_0 ));
endmodule | 8 |
2,399 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized47
(\xsdb_reg_reg[0] ,
\xsdb_reg_reg[0]_0 ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_den_o,
s_dwe_o,
s_daddr_o,
s_di_o,
s_dclk_o);
output \xsdb_reg_reg[0] ;
output \xsdb_reg_reg[0]_0 ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input s_den_o;
input s_dwe_o;
input [6:0]s_daddr_o;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[0]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_175 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[9] (\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized47
(\xsdb_reg_reg[0] ,
\xsdb_reg_reg[0]_0 ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_den_o,
s_dwe_o,
s_daddr_o,
s_di_o,
s_dclk_o); |
output \xsdb_reg_reg[0] ;
output \xsdb_reg_reg[0]_0 ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input s_den_o;
input s_dwe_o;
input [6:0]s_daddr_o;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[0]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_175 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[9] (\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ));
endmodule | 8 |
2,400 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized48
(D,
\slaveRegDo_mux_0_reg[15] ,
en_adv_trigger_1,
\slaveRegDo_mux_0_reg[0] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
capture_qual_ctrl_1,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ,
\xsdb_reg_reg[15] ,
\xsdb_reg_reg[15]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\xsdb_reg_reg[4] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\xsdb_reg_reg[3] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\xsdb_reg_reg[15]_1 ,
\xsdb_reg_reg[15]_2 ,
\xsdb_reg_reg[4]_0 ,
\xsdb_reg_reg[3]_0 ,
\xsdb_reg_reg[0] ,
s_di_o,
s_dclk_o);
output [1:0]D;
output \slaveRegDo_mux_0_reg[15] ;
output en_adv_trigger_1;
output \slaveRegDo_mux_0_reg[0] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output [1:0]capture_qual_ctrl_1;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [7:0]s_daddr_o;
input [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ;
input \xsdb_reg_reg[15] ;
input \xsdb_reg_reg[15]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \xsdb_reg_reg[4] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \xsdb_reg_reg[3] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \xsdb_reg_reg[15]_1 ;
input [3:0]\xsdb_reg_reg[15]_2 ;
input \xsdb_reg_reg[4]_0 ;
input \xsdb_reg_reg[3]_0 ;
input \xsdb_reg_reg[0] ;
input [15:0]s_di_o;
input s_dclk_o;
wire [1:0]D;
wire [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [1:0]capture_qual_ctrl_1;
wire en_adv_trigger_1;
wire [7:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[15] ;
wire \xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg[15]_1 ;
wire [3:0]\xsdb_reg_reg[15]_2 ;
wire \xsdb_reg_reg[3] ;
wire \xsdb_reg_reg[3]_0 ;
wire \xsdb_reg_reg[4] ;
wire \xsdb_reg_reg[4]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized1 \I_EN_CTL_EQ1.U_CTL
(.D(D),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.en_adv_trigger_1(en_adv_trigger_1),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
.\xsdb_reg_reg[15]_1 (\xsdb_reg_reg[15]_0 ),
.\xsdb_reg_reg[15]_2 (\xsdb_reg_reg[15]_1 ),
.\xsdb_reg_reg[15]_3 (\xsdb_reg_reg[15]_2 ),
.\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
.\xsdb_reg_reg[3]_1 (\xsdb_reg_reg[3]_0 ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
.\xsdb_reg_reg[4]_1 (\xsdb_reg_reg[4]_0 ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized48
(D,
\slaveRegDo_mux_0_reg[15] ,
en_adv_trigger_1,
\slaveRegDo_mux_0_reg[0] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
capture_qual_ctrl_1,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ,
\xsdb_reg_reg[15] ,
\xsdb_reg_reg[15]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\xsdb_reg_reg[4] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\xsdb_reg_reg[3] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\xsdb_reg_reg[15]_1 ,
\xsdb_reg_reg[15]_2 ,
\xsdb_reg_reg[4]_0 ,
\xsdb_reg_reg[3]_0 ,
\xsdb_reg_reg[0] ,
s_di_o,
s_dclk_o); |
output [1:0]D;
output \slaveRegDo_mux_0_reg[15] ;
output en_adv_trigger_1;
output \slaveRegDo_mux_0_reg[0] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output [1:0]capture_qual_ctrl_1;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [7:0]s_daddr_o;
input [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ;
input \xsdb_reg_reg[15] ;
input \xsdb_reg_reg[15]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \xsdb_reg_reg[4] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \xsdb_reg_reg[3] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \xsdb_reg_reg[15]_1 ;
input [3:0]\xsdb_reg_reg[15]_2 ;
input \xsdb_reg_reg[4]_0 ;
input \xsdb_reg_reg[3]_0 ;
input \xsdb_reg_reg[0] ;
input [15:0]s_di_o;
input s_dclk_o;
wire [1:0]D;
wire [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [1:0]capture_qual_ctrl_1;
wire en_adv_trigger_1;
wire [7:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[15] ;
wire \xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg[15]_1 ;
wire [3:0]\xsdb_reg_reg[15]_2 ;
wire \xsdb_reg_reg[3] ;
wire \xsdb_reg_reg[3]_0 ;
wire \xsdb_reg_reg[4] ;
wire \xsdb_reg_reg[4]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized1 \I_EN_CTL_EQ1.U_CTL
(.D(D),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.capture_qual_ctrl_1(capture_qual_ctrl_1),
.en_adv_trigger_1(en_adv_trigger_1),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
.\xsdb_reg_reg[15]_1 (\xsdb_reg_reg[15]_0 ),
.\xsdb_reg_reg[15]_2 (\xsdb_reg_reg[15]_1 ),
.\xsdb_reg_reg[15]_3 (\xsdb_reg_reg[15]_2 ),
.\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
.\xsdb_reg_reg[3]_1 (\xsdb_reg_reg[3]_0 ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
.\xsdb_reg_reg[4]_1 (\xsdb_reg_reg[4]_0 ));
endmodule | 8 |
2,401 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized49
(slaveRegDo_80,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] );
output [15:0]slaveRegDo_80;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_80;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized2 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.slaveRegDo_80(slaveRegDo_80));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized49
(slaveRegDo_80,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ); |
output [15:0]slaveRegDo_80;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_80;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized2 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.slaveRegDo_80(slaveRegDo_80));
endmodule | 8 |
2,402 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized50
(slaveRegDo_81,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] );
output [15:0]slaveRegDo_81;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_81;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_172 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.slaveRegDo_81(slaveRegDo_81));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized50
(slaveRegDo_81,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ); |
output [15:0]slaveRegDo_81;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_81;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_172 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.slaveRegDo_81(slaveRegDo_81));
endmodule | 8 |
2,403 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized51
(slaveRegDo_82,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] );
output [15:0]slaveRegDo_82;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_82;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized3 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.slaveRegDo_82(slaveRegDo_82));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized51
(slaveRegDo_82,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ); |
output [15:0]slaveRegDo_82;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_82;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized3 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.slaveRegDo_82(slaveRegDo_82));
endmodule | 8 |
2,404 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized52
(\xsdb_reg_reg[0] ,
\xsdb_reg_reg[0]_0 ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
s_den_o,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
slaveRegDo_84,
\xsdb_reg_reg[15] ,
\xsdb_reg_reg[14] ,
\xsdb_reg_reg[14]_0 ,
\xsdb_reg_reg[13] ,
\xsdb_reg_reg[13]_0 ,
\xsdb_reg_reg[12] ,
\xsdb_reg_reg[12]_0 ,
\xsdb_reg_reg[11] ,
\xsdb_reg_reg[11]_0 ,
\xsdb_reg_reg[10] ,
\xsdb_reg_reg[10]_0 ,
\xsdb_reg_reg[9] ,
\xsdb_reg_reg[9]_0 ,
\xsdb_reg_reg[8] ,
\xsdb_reg_reg[8]_0 ,
\xsdb_reg_reg[7] ,
\xsdb_reg_reg[7]_0 ,
\xsdb_reg_reg[6] ,
\xsdb_reg_reg[6]_0 ,
\xsdb_reg_reg[5] ,
\xsdb_reg_reg[5]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\xsdb_reg_reg[4] ,
\xsdb_reg_reg[3] ,
\xsdb_reg_reg[2] ,
\xsdb_reg_reg[1] ,
\xsdb_reg_reg[0]_1 ,
slaveRegDo_82,
slaveRegDo_81,
slaveRegDo_80,
s_di_o,
s_dclk_o);
output \xsdb_reg_reg[0] ;
output \xsdb_reg_reg[0]_0 ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input s_den_o;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input [12:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [10:0]slaveRegDo_84;
input \xsdb_reg_reg[15] ;
input \xsdb_reg_reg[14] ;
input \xsdb_reg_reg[14]_0 ;
input \xsdb_reg_reg[13] ;
input \xsdb_reg_reg[13]_0 ;
input \xsdb_reg_reg[12] ;
input \xsdb_reg_reg[12]_0 ;
input \xsdb_reg_reg[11] ;
input \xsdb_reg_reg[11]_0 ;
input \xsdb_reg_reg[10] ;
input \xsdb_reg_reg[10]_0 ;
input \xsdb_reg_reg[9] ;
input \xsdb_reg_reg[9]_0 ;
input \xsdb_reg_reg[8] ;
input \xsdb_reg_reg[8]_0 ;
input \xsdb_reg_reg[7] ;
input \xsdb_reg_reg[7]_0 ;
input \xsdb_reg_reg[6] ;
input \xsdb_reg_reg[6]_0 ;
input \xsdb_reg_reg[5] ;
input \xsdb_reg_reg[5]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \xsdb_reg_reg[4] ;
input \xsdb_reg_reg[3] ;
input \xsdb_reg_reg[2] ;
input \xsdb_reg_reg[1] ;
input \xsdb_reg_reg[0]_1 ;
input [15:0]slaveRegDo_82;
input [15:0]slaveRegDo_81;
input [15:0]slaveRegDo_80;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire [15:0]slaveRegDo_80;
wire [15:0]slaveRegDo_81;
wire [15:0]slaveRegDo_82;
wire [10:0]slaveRegDo_84;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[0]_1 ;
wire \xsdb_reg_reg[10] ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[11] ;
wire \xsdb_reg_reg[11]_0 ;
wire \xsdb_reg_reg[12] ;
wire \xsdb_reg_reg[12]_0 ;
wire \xsdb_reg_reg[13] ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[14] ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[15] ;
wire \xsdb_reg_reg[1] ;
wire \xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[3] ;
wire \xsdb_reg_reg[4] ;
wire \xsdb_reg_reg[5] ;
wire \xsdb_reg_reg[5]_0 ;
wire \xsdb_reg_reg[6] ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[7] ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[8] ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[9] ;
wire \xsdb_reg_reg[9]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_171 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.slaveRegDo_80(slaveRegDo_80),
.slaveRegDo_81(slaveRegDo_81),
.slaveRegDo_82(slaveRegDo_82),
.slaveRegDo_84(slaveRegDo_84),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ),
.\xsdb_reg_reg[0]_2 (\xsdb_reg_reg[0]_1 ),
.\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
.\xsdb_reg_reg[10]_1 (\xsdb_reg_reg[10]_0 ),
.\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
.\xsdb_reg_reg[11]_1 (\xsdb_reg_reg[11]_0 ),
.\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
.\xsdb_reg_reg[12]_1 (\xsdb_reg_reg[12]_0 ),
.\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
.\xsdb_reg_reg[13]_1 (\xsdb_reg_reg[13]_0 ),
.\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
.\xsdb_reg_reg[14]_1 (\xsdb_reg_reg[14]_0 ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
.\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
.\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
.\xsdb_reg_reg[5]_1 (\xsdb_reg_reg[5]_0 ),
.\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
.\xsdb_reg_reg[6]_1 (\xsdb_reg_reg[6]_0 ),
.\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
.\xsdb_reg_reg[7]_1 (\xsdb_reg_reg[7]_0 ),
.\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
.\xsdb_reg_reg[8]_1 (\xsdb_reg_reg[8]_0 ),
.\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ),
.\xsdb_reg_reg[9]_1 (\xsdb_reg_reg[9]_0 ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized52
(\xsdb_reg_reg[0] ,
\xsdb_reg_reg[0]_0 ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
s_den_o,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
slaveRegDo_84,
\xsdb_reg_reg[15] ,
\xsdb_reg_reg[14] ,
\xsdb_reg_reg[14]_0 ,
\xsdb_reg_reg[13] ,
\xsdb_reg_reg[13]_0 ,
\xsdb_reg_reg[12] ,
\xsdb_reg_reg[12]_0 ,
\xsdb_reg_reg[11] ,
\xsdb_reg_reg[11]_0 ,
\xsdb_reg_reg[10] ,
\xsdb_reg_reg[10]_0 ,
\xsdb_reg_reg[9] ,
\xsdb_reg_reg[9]_0 ,
\xsdb_reg_reg[8] ,
\xsdb_reg_reg[8]_0 ,
\xsdb_reg_reg[7] ,
\xsdb_reg_reg[7]_0 ,
\xsdb_reg_reg[6] ,
\xsdb_reg_reg[6]_0 ,
\xsdb_reg_reg[5] ,
\xsdb_reg_reg[5]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\xsdb_reg_reg[4] ,
\xsdb_reg_reg[3] ,
\xsdb_reg_reg[2] ,
\xsdb_reg_reg[1] ,
\xsdb_reg_reg[0]_1 ,
slaveRegDo_82,
slaveRegDo_81,
slaveRegDo_80,
s_di_o,
s_dclk_o); |
output \xsdb_reg_reg[0] ;
output \xsdb_reg_reg[0]_0 ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input s_den_o;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input [12:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [10:0]slaveRegDo_84;
input \xsdb_reg_reg[15] ;
input \xsdb_reg_reg[14] ;
input \xsdb_reg_reg[14]_0 ;
input \xsdb_reg_reg[13] ;
input \xsdb_reg_reg[13]_0 ;
input \xsdb_reg_reg[12] ;
input \xsdb_reg_reg[12]_0 ;
input \xsdb_reg_reg[11] ;
input \xsdb_reg_reg[11]_0 ;
input \xsdb_reg_reg[10] ;
input \xsdb_reg_reg[10]_0 ;
input \xsdb_reg_reg[9] ;
input \xsdb_reg_reg[9]_0 ;
input \xsdb_reg_reg[8] ;
input \xsdb_reg_reg[8]_0 ;
input \xsdb_reg_reg[7] ;
input \xsdb_reg_reg[7]_0 ;
input \xsdb_reg_reg[6] ;
input \xsdb_reg_reg[6]_0 ;
input \xsdb_reg_reg[5] ;
input \xsdb_reg_reg[5]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \xsdb_reg_reg[4] ;
input \xsdb_reg_reg[3] ;
input \xsdb_reg_reg[2] ;
input \xsdb_reg_reg[1] ;
input \xsdb_reg_reg[0]_1 ;
input [15:0]slaveRegDo_82;
input [15:0]slaveRegDo_81;
input [15:0]slaveRegDo_80;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire [15:0]slaveRegDo_80;
wire [15:0]slaveRegDo_81;
wire [15:0]slaveRegDo_82;
wire [10:0]slaveRegDo_84;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[0]_1 ;
wire \xsdb_reg_reg[10] ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[11] ;
wire \xsdb_reg_reg[11]_0 ;
wire \xsdb_reg_reg[12] ;
wire \xsdb_reg_reg[12]_0 ;
wire \xsdb_reg_reg[13] ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[14] ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[15] ;
wire \xsdb_reg_reg[1] ;
wire \xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[3] ;
wire \xsdb_reg_reg[4] ;
wire \xsdb_reg_reg[5] ;
wire \xsdb_reg_reg[5]_0 ;
wire \xsdb_reg_reg[6] ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[7] ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[8] ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[9] ;
wire \xsdb_reg_reg[9]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_171 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_di_o(s_di_o),
.s_dwe_o(s_dwe_o),
.slaveRegDo_80(slaveRegDo_80),
.slaveRegDo_81(slaveRegDo_81),
.slaveRegDo_82(slaveRegDo_82),
.slaveRegDo_84(slaveRegDo_84),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ),
.\xsdb_reg_reg[0]_2 (\xsdb_reg_reg[0]_1 ),
.\xsdb_reg_reg[10]_0 (\xsdb_reg_reg[10] ),
.\xsdb_reg_reg[10]_1 (\xsdb_reg_reg[10]_0 ),
.\xsdb_reg_reg[11]_0 (\xsdb_reg_reg[11] ),
.\xsdb_reg_reg[11]_1 (\xsdb_reg_reg[11]_0 ),
.\xsdb_reg_reg[12]_0 (\xsdb_reg_reg[12] ),
.\xsdb_reg_reg[12]_1 (\xsdb_reg_reg[12]_0 ),
.\xsdb_reg_reg[13]_0 (\xsdb_reg_reg[13] ),
.\xsdb_reg_reg[13]_1 (\xsdb_reg_reg[13]_0 ),
.\xsdb_reg_reg[14]_0 (\xsdb_reg_reg[14] ),
.\xsdb_reg_reg[14]_1 (\xsdb_reg_reg[14]_0 ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
.\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ),
.\xsdb_reg_reg[5]_0 (\xsdb_reg_reg[5] ),
.\xsdb_reg_reg[5]_1 (\xsdb_reg_reg[5]_0 ),
.\xsdb_reg_reg[6]_0 (\xsdb_reg_reg[6] ),
.\xsdb_reg_reg[6]_1 (\xsdb_reg_reg[6]_0 ),
.\xsdb_reg_reg[7]_0 (\xsdb_reg_reg[7] ),
.\xsdb_reg_reg[7]_1 (\xsdb_reg_reg[7]_0 ),
.\xsdb_reg_reg[8]_0 (\xsdb_reg_reg[8] ),
.\xsdb_reg_reg[8]_1 (\xsdb_reg_reg[8]_0 ),
.\xsdb_reg_reg[9]_0 (\xsdb_reg_reg[9] ),
.\xsdb_reg_reg[9]_1 (\xsdb_reg_reg[9]_0 ));
endmodule | 8 |
2,405 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized53
(\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
s_daddr_o,
\xsdb_reg_reg[4] ,
\xsdb_reg_reg[3] ,
\xsdb_reg_reg[2] ,
\xsdb_reg_reg[1] ,
\xsdb_reg_reg[0] ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] );
output \slaveRegDo_mux_0_reg[4] ;
output [10:0]\slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input [2:0]s_daddr_o;
input \xsdb_reg_reg[4] ;
input \xsdb_reg_reg[3] ;
input \xsdb_reg_reg[2] ;
input \xsdb_reg_reg[1] ;
input \xsdb_reg_reg[0] ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire [10:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[1] ;
wire \xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[3] ;
wire \xsdb_reg_reg[4] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_170 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized53
(\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
s_daddr_o,
\xsdb_reg_reg[4] ,
\xsdb_reg_reg[3] ,
\xsdb_reg_reg[2] ,
\xsdb_reg_reg[1] ,
\xsdb_reg_reg[0] ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ); |
output \slaveRegDo_mux_0_reg[4] ;
output [10:0]\slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input [2:0]s_daddr_o;
input \xsdb_reg_reg[4] ;
input \xsdb_reg_reg[3] ;
input \xsdb_reg_reg[2] ;
input \xsdb_reg_reg[1] ;
input \xsdb_reg_reg[0] ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire [10:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[1] ;
wire \xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[3] ;
wire \xsdb_reg_reg[4] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_170 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[11] (\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
.\xsdb_reg_reg[4]_0 (\xsdb_reg_reg[4] ));
endmodule | 8 |
2,406 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized54
(\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[10] ,
s_daddr_o,
s_di_o,
s_dclk_o);
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
input [2:0]s_daddr_o;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_169 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[10] (\G_1PIPE_IFACE.s_daddr_r_reg[10] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized54
(\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[10] ,
s_daddr_o,
s_di_o,
s_dclk_o); |
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
input [2:0]s_daddr_o;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_169 \I_EN_CTL_EQ1.U_CTL
(.\G_1PIPE_IFACE.s_daddr_r_reg[10] (\G_1PIPE_IFACE.s_daddr_r_reg[10] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_di_o(s_di_o),
.\slaveRegDo_mux_0_reg[0] (\slaveRegDo_mux_0_reg[0] ),
.\slaveRegDo_mux_0_reg[10] (\slaveRegDo_mux_0_reg[10] ),
.\slaveRegDo_mux_0_reg[11] (\slaveRegDo_mux_0_reg[11] ),
.\slaveRegDo_mux_0_reg[12] (\slaveRegDo_mux_0_reg[12] ),
.\slaveRegDo_mux_0_reg[13] (\slaveRegDo_mux_0_reg[13] ),
.\slaveRegDo_mux_0_reg[14] (\slaveRegDo_mux_0_reg[14] ),
.\slaveRegDo_mux_0_reg[15] (\slaveRegDo_mux_0_reg[15] ),
.\slaveRegDo_mux_0_reg[1] (\slaveRegDo_mux_0_reg[1] ),
.\slaveRegDo_mux_0_reg[2] (\slaveRegDo_mux_0_reg[2] ),
.\slaveRegDo_mux_0_reg[3] (\slaveRegDo_mux_0_reg[3] ),
.\slaveRegDo_mux_0_reg[4] (\slaveRegDo_mux_0_reg[4] ),
.\slaveRegDo_mux_0_reg[5] (\slaveRegDo_mux_0_reg[5] ),
.\slaveRegDo_mux_0_reg[6] (\slaveRegDo_mux_0_reg[6] ),
.\slaveRegDo_mux_0_reg[7] (\slaveRegDo_mux_0_reg[7] ),
.\slaveRegDo_mux_0_reg[8] (\slaveRegDo_mux_0_reg[8] ),
.\slaveRegDo_mux_0_reg[9] (\slaveRegDo_mux_0_reg[9] ));
endmodule | 8 |
2,407 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized56
(\slaveRegDo_mux_2_reg[3] ,
s_den_o,
out,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
s_do_o,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[4] );
output \slaveRegDo_mux_2_reg[3] ;
input s_den_o;
input out;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input [0:0]s_do_o;
input [1:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire out;
wire [1:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [0:0]s_do_o;
wire \slaveRegDo_mux_2_reg[3] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_168 \I_EN_STAT_EQ1.U_STAT
(.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.out(out),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_do_o(s_do_o),
.\slaveRegDo_mux_2_reg[3] (\slaveRegDo_mux_2_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized56
(\slaveRegDo_mux_2_reg[3] ,
s_den_o,
out,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
s_do_o,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ); |
output \slaveRegDo_mux_2_reg[3] ;
input s_den_o;
input out;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input [0:0]s_do_o;
input [1:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire out;
wire [1:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [0:0]s_do_o;
wire \slaveRegDo_mux_2_reg[3] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_168 \I_EN_STAT_EQ1.U_STAT
(.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.out(out),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_do_o(s_do_o),
.\slaveRegDo_mux_2_reg[3] (\slaveRegDo_mux_2_reg[3] ));
endmodule | 8 |
2,408 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized58
(D,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
s_daddr_o,
\xsdb_reg_reg[0] ,
\xsdb_reg_reg[0]_0 ,
s_den_o,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
s_dclk_o);
output [0:0]D;
output [0:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [1:0]s_daddr_o;
input \xsdb_reg_reg[0] ;
input \xsdb_reg_reg[0]_0 ;
input s_den_o;
input [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ;
input s_dclk_o;
wire [0:0]D;
wire [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [0:0]Q;
wire [1:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[0]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_167 \I_EN_STAT_EQ1.U_STAT
(.D(D),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.Q(Q),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized58
(D,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
s_daddr_o,
\xsdb_reg_reg[0] ,
\xsdb_reg_reg[0]_0 ,
s_den_o,
\I_YESLUT6.I_YES_OREG.O_reg_reg ,
s_dclk_o); |
output [0:0]D;
output [0:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [1:0]s_daddr_o;
input \xsdb_reg_reg[0] ;
input \xsdb_reg_reg[0]_0 ;
input s_den_o;
input [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ;
input s_dclk_o;
wire [0:0]D;
wire [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire [1:0]\I_YESLUT6.I_YES_OREG.O_reg_reg ;
wire [0:0]Q;
wire [1:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire \xsdb_reg_reg[0] ;
wire \xsdb_reg_reg[0]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_167 \I_EN_STAT_EQ1.U_STAT
(.D(D),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[4] (\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[5] (\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.\I_YESLUT6.I_YES_OREG.O_reg_reg (\I_YESLUT6.I_YES_OREG.O_reg_reg ),
.Q(Q),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\xsdb_reg_reg[0]_0 (\xsdb_reg_reg[0] ),
.\xsdb_reg_reg[0]_1 (\xsdb_reg_reg[0]_0 ));
endmodule | 8 |
2,409 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized59
(\slaveRegDo_mux_2_reg[3] ,
\slaveRegDo_mux_2_reg[2] ,
\slaveRegDo_mux_2_reg[1] ,
\slaveRegDo_mux_2_reg[0] ,
\G_1PIPE_IFACE.s_den_r_reg ,
s_den_o,
flag3_temp,
s_dclk_o,
flag2_temp,
flag1_temp,
flag0_temp);
output \slaveRegDo_mux_2_reg[3] ;
output \slaveRegDo_mux_2_reg[2] ;
output \slaveRegDo_mux_2_reg[1] ;
output \slaveRegDo_mux_2_reg[0] ;
input \G_1PIPE_IFACE.s_den_r_reg ;
input s_den_o;
input flag3_temp;
input s_dclk_o;
input flag2_temp;
input flag1_temp;
input flag0_temp;
wire \G_1PIPE_IFACE.s_den_r_reg ;
wire flag0_temp;
wire flag1_temp;
wire flag2_temp;
wire flag3_temp;
wire s_dclk_o;
wire s_den_o;
wire \slaveRegDo_mux_2_reg[0] ;
wire \slaveRegDo_mux_2_reg[1] ;
wire \slaveRegDo_mux_2_reg[2] ;
wire \slaveRegDo_mux_2_reg[3] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_165 \I_EN_STAT_EQ1.U_STAT
(.\G_1PIPE_IFACE.s_den_r_reg (\G_1PIPE_IFACE.s_den_r_reg ),
.flag0_temp(flag0_temp),
.flag1_temp(flag1_temp),
.flag2_temp(flag2_temp),
.flag3_temp(flag3_temp),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_2_reg[0] (\slaveRegDo_mux_2_reg[0] ),
.\slaveRegDo_mux_2_reg[1] (\slaveRegDo_mux_2_reg[1] ),
.\slaveRegDo_mux_2_reg[2] (\slaveRegDo_mux_2_reg[2] ),
.\slaveRegDo_mux_2_reg[3] (\slaveRegDo_mux_2_reg[3] ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized59
(\slaveRegDo_mux_2_reg[3] ,
\slaveRegDo_mux_2_reg[2] ,
\slaveRegDo_mux_2_reg[1] ,
\slaveRegDo_mux_2_reg[0] ,
\G_1PIPE_IFACE.s_den_r_reg ,
s_den_o,
flag3_temp,
s_dclk_o,
flag2_temp,
flag1_temp,
flag0_temp); |
output \slaveRegDo_mux_2_reg[3] ;
output \slaveRegDo_mux_2_reg[2] ;
output \slaveRegDo_mux_2_reg[1] ;
output \slaveRegDo_mux_2_reg[0] ;
input \G_1PIPE_IFACE.s_den_r_reg ;
input s_den_o;
input flag3_temp;
input s_dclk_o;
input flag2_temp;
input flag1_temp;
input flag0_temp;
wire \G_1PIPE_IFACE.s_den_r_reg ;
wire flag0_temp;
wire flag1_temp;
wire flag2_temp;
wire flag3_temp;
wire s_dclk_o;
wire s_den_o;
wire \slaveRegDo_mux_2_reg[0] ;
wire \slaveRegDo_mux_2_reg[1] ;
wire \slaveRegDo_mux_2_reg[2] ;
wire \slaveRegDo_mux_2_reg[3] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_165 \I_EN_STAT_EQ1.U_STAT
(.\G_1PIPE_IFACE.s_den_r_reg (\G_1PIPE_IFACE.s_den_r_reg ),
.flag0_temp(flag0_temp),
.flag1_temp(flag1_temp),
.flag2_temp(flag2_temp),
.flag3_temp(flag3_temp),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.\slaveRegDo_mux_2_reg[0] (\slaveRegDo_mux_2_reg[0] ),
.\slaveRegDo_mux_2_reg[1] (\slaveRegDo_mux_2_reg[1] ),
.\slaveRegDo_mux_2_reg[2] (\slaveRegDo_mux_2_reg[2] ),
.\slaveRegDo_mux_2_reg[3] (\slaveRegDo_mux_2_reg[3] ));
endmodule | 8 |
2,410 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized60
(\slaveRegDo_mux_2_reg[5] ,
\slaveRegDo_mux_2_reg[6] ,
\slaveRegDo_mux_2_reg[7] ,
\slaveRegDo_mux_2_reg[8] ,
\slaveRegDo_mux_2_reg[9] ,
\slaveRegDo_mux_2_reg[10] ,
\slaveRegDo_mux_2_reg[11] ,
\slaveRegDo_mux_2_reg[12] ,
\slaveRegDo_mux_2_reg[13] ,
\slaveRegDo_mux_2_reg[14] ,
\slaveRegDo_mux_2_reg[15] ,
\xsdb_reg_reg[15] ,
D,
\slaveRegDo_mux_2_reg[0] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
s_do_o,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\xsdb_reg_reg[3] ,
s_den_o,
en_adv_trigger,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
\xsdb_reg_reg[3]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\xsdb_reg_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\xsdb_reg_reg[1] ,
Q,
SEQUENCER_STATE_O,
s_dclk_o);
output \slaveRegDo_mux_2_reg[5] ;
output \slaveRegDo_mux_2_reg[6] ;
output \slaveRegDo_mux_2_reg[7] ;
output \slaveRegDo_mux_2_reg[8] ;
output \slaveRegDo_mux_2_reg[9] ;
output \slaveRegDo_mux_2_reg[10] ;
output \slaveRegDo_mux_2_reg[11] ;
output \slaveRegDo_mux_2_reg[12] ;
output \slaveRegDo_mux_2_reg[13] ;
output \slaveRegDo_mux_2_reg[14] ;
output \slaveRegDo_mux_2_reg[15] ;
output \xsdb_reg_reg[15] ;
output [3:0]D;
output \slaveRegDo_mux_2_reg[0] ;
input [4:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input [12:0]s_do_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \xsdb_reg_reg[3] ;
input s_den_o;
input en_adv_trigger;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
input \xsdb_reg_reg[3]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \xsdb_reg_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \xsdb_reg_reg[1] ;
input [0:0]Q;
input [15:0]SEQUENCER_STATE_O;
input s_dclk_o;
wire [3:0]D;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire [3:0]\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire [0:0]Q;
wire [15:0]SEQUENCER_STATE_O;
wire en_adv_trigger;
wire [4:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [12:0]s_do_o;
wire \slaveRegDo_mux_2_reg[0] ;
wire \slaveRegDo_mux_2_reg[10] ;
wire \slaveRegDo_mux_2_reg[11] ;
wire \slaveRegDo_mux_2_reg[12] ;
wire \slaveRegDo_mux_2_reg[13] ;
wire \slaveRegDo_mux_2_reg[14] ;
wire \slaveRegDo_mux_2_reg[15] ;
wire \slaveRegDo_mux_2_reg[5] ;
wire \slaveRegDo_mux_2_reg[6] ;
wire \slaveRegDo_mux_2_reg[7] ;
wire \slaveRegDo_mux_2_reg[8] ;
wire \slaveRegDo_mux_2_reg[9] ;
wire \xsdb_reg_reg[15] ;
wire \xsdb_reg_reg[1] ;
wire \xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[3] ;
wire \xsdb_reg_reg[3]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_166 \I_EN_STAT_EQ1.U_STAT
(.D(D),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.Q(Q),
.SEQUENCER_STATE_O(SEQUENCER_STATE_O),
.en_adv_trigger(en_adv_trigger),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_do_o(s_do_o),
.\slaveRegDo_mux_2_reg[0] (\slaveRegDo_mux_2_reg[0] ),
.\slaveRegDo_mux_2_reg[10] (\slaveRegDo_mux_2_reg[10] ),
.\slaveRegDo_mux_2_reg[11] (\slaveRegDo_mux_2_reg[11] ),
.\slaveRegDo_mux_2_reg[12] (\slaveRegDo_mux_2_reg[12] ),
.\slaveRegDo_mux_2_reg[13] (\slaveRegDo_mux_2_reg[13] ),
.\slaveRegDo_mux_2_reg[14] (\slaveRegDo_mux_2_reg[14] ),
.\slaveRegDo_mux_2_reg[15] (\slaveRegDo_mux_2_reg[15] ),
.\slaveRegDo_mux_2_reg[5] (\slaveRegDo_mux_2_reg[5] ),
.\slaveRegDo_mux_2_reg[6] (\slaveRegDo_mux_2_reg[6] ),
.\slaveRegDo_mux_2_reg[7] (\slaveRegDo_mux_2_reg[7] ),
.\slaveRegDo_mux_2_reg[8] (\slaveRegDo_mux_2_reg[8] ),
.\slaveRegDo_mux_2_reg[9] (\slaveRegDo_mux_2_reg[9] ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
.\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
.\xsdb_reg_reg[3]_1 (\xsdb_reg_reg[3]_0 ));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized60
(\slaveRegDo_mux_2_reg[5] ,
\slaveRegDo_mux_2_reg[6] ,
\slaveRegDo_mux_2_reg[7] ,
\slaveRegDo_mux_2_reg[8] ,
\slaveRegDo_mux_2_reg[9] ,
\slaveRegDo_mux_2_reg[10] ,
\slaveRegDo_mux_2_reg[11] ,
\slaveRegDo_mux_2_reg[12] ,
\slaveRegDo_mux_2_reg[13] ,
\slaveRegDo_mux_2_reg[14] ,
\slaveRegDo_mux_2_reg[15] ,
\xsdb_reg_reg[15] ,
D,
\slaveRegDo_mux_2_reg[0] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
s_do_o,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\xsdb_reg_reg[3] ,
s_den_o,
en_adv_trigger,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
\xsdb_reg_reg[3]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\xsdb_reg_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\xsdb_reg_reg[1] ,
Q,
SEQUENCER_STATE_O,
s_dclk_o); |
output \slaveRegDo_mux_2_reg[5] ;
output \slaveRegDo_mux_2_reg[6] ;
output \slaveRegDo_mux_2_reg[7] ;
output \slaveRegDo_mux_2_reg[8] ;
output \slaveRegDo_mux_2_reg[9] ;
output \slaveRegDo_mux_2_reg[10] ;
output \slaveRegDo_mux_2_reg[11] ;
output \slaveRegDo_mux_2_reg[12] ;
output \slaveRegDo_mux_2_reg[13] ;
output \slaveRegDo_mux_2_reg[14] ;
output \slaveRegDo_mux_2_reg[15] ;
output \xsdb_reg_reg[15] ;
output [3:0]D;
output \slaveRegDo_mux_2_reg[0] ;
input [4:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input [12:0]s_do_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \xsdb_reg_reg[3] ;
input s_den_o;
input en_adv_trigger;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
input \xsdb_reg_reg[3]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \xsdb_reg_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \xsdb_reg_reg[1] ;
input [0:0]Q;
input [15:0]SEQUENCER_STATE_O;
input s_dclk_o;
wire [3:0]D;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire [3:0]\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire [0:0]Q;
wire [15:0]SEQUENCER_STATE_O;
wire en_adv_trigger;
wire [4:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [12:0]s_do_o;
wire \slaveRegDo_mux_2_reg[0] ;
wire \slaveRegDo_mux_2_reg[10] ;
wire \slaveRegDo_mux_2_reg[11] ;
wire \slaveRegDo_mux_2_reg[12] ;
wire \slaveRegDo_mux_2_reg[13] ;
wire \slaveRegDo_mux_2_reg[14] ;
wire \slaveRegDo_mux_2_reg[15] ;
wire \slaveRegDo_mux_2_reg[5] ;
wire \slaveRegDo_mux_2_reg[6] ;
wire \slaveRegDo_mux_2_reg[7] ;
wire \slaveRegDo_mux_2_reg[8] ;
wire \slaveRegDo_mux_2_reg[9] ;
wire \xsdb_reg_reg[15] ;
wire \xsdb_reg_reg[1] ;
wire \xsdb_reg_reg[2] ;
wire \xsdb_reg_reg[3] ;
wire \xsdb_reg_reg[3]_0 ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_166 \I_EN_STAT_EQ1.U_STAT
(.D(D),
.\G_1PIPE_IFACE.s_daddr_r_reg[0] (\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[0]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[1] (\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2] (\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ),
.\G_1PIPE_IFACE.s_daddr_r_reg[3] (\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7] (\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 (\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.Q(Q),
.SEQUENCER_STATE_O(SEQUENCER_STATE_O),
.en_adv_trigger(en_adv_trigger),
.s_daddr_o(s_daddr_o),
.s_dclk_o(s_dclk_o),
.s_den_o(s_den_o),
.s_do_o(s_do_o),
.\slaveRegDo_mux_2_reg[0] (\slaveRegDo_mux_2_reg[0] ),
.\slaveRegDo_mux_2_reg[10] (\slaveRegDo_mux_2_reg[10] ),
.\slaveRegDo_mux_2_reg[11] (\slaveRegDo_mux_2_reg[11] ),
.\slaveRegDo_mux_2_reg[12] (\slaveRegDo_mux_2_reg[12] ),
.\slaveRegDo_mux_2_reg[13] (\slaveRegDo_mux_2_reg[13] ),
.\slaveRegDo_mux_2_reg[14] (\slaveRegDo_mux_2_reg[14] ),
.\slaveRegDo_mux_2_reg[15] (\slaveRegDo_mux_2_reg[15] ),
.\slaveRegDo_mux_2_reg[5] (\slaveRegDo_mux_2_reg[5] ),
.\slaveRegDo_mux_2_reg[6] (\slaveRegDo_mux_2_reg[6] ),
.\slaveRegDo_mux_2_reg[7] (\slaveRegDo_mux_2_reg[7] ),
.\slaveRegDo_mux_2_reg[8] (\slaveRegDo_mux_2_reg[8] ),
.\slaveRegDo_mux_2_reg[9] (\slaveRegDo_mux_2_reg[9] ),
.\xsdb_reg_reg[15]_0 (\xsdb_reg_reg[15] ),
.\xsdb_reg_reg[1]_0 (\xsdb_reg_reg[1] ),
.\xsdb_reg_reg[2]_0 (\xsdb_reg_reg[2] ),
.\xsdb_reg_reg[3]_0 (\xsdb_reg_reg[3] ),
.\xsdb_reg_reg[3]_1 (\xsdb_reg_reg[3]_0 ));
endmodule | 8 |
2,411 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized61
(s_do_o,
dout_o,
rst_reg_i,
din_i,
s_daddr_i,
s_di_i,
s_den_i,
s_dwe_i,
s_dclk_i);
output [15:0]s_do_o;
output [15:0]dout_o;
input rst_reg_i;
input [15:0]din_i;
input [12:0]s_daddr_i;
input [15:0]s_di_i;
input s_den_i;
input s_dwe_i;
input s_dclk_i;
wire \<const0> ;
wire [15:0]din_i;
wire s_dclk_i;
wire s_den_i;
wire [15:0]s_do_o;
assign dout_o[15] = \<const0> ;
assign dout_o[14] = \<const0> ;
assign dout_o[13] = \<const0> ;
assign dout_o[12] = \<const0> ;
assign dout_o[11] = \<const0> ;
assign dout_o[10] = \<const0> ;
assign dout_o[9] = \<const0> ;
assign dout_o[8] = \<const0> ;
assign dout_o[7] = \<const0> ;
assign dout_o[6] = \<const0> ;
assign dout_o[5] = \<const0> ;
assign dout_o[4] = \<const0> ;
assign dout_o[3] = \<const0> ;
assign dout_o[2] = \<const0> ;
assign dout_o[1] = \<const0> ;
assign dout_o[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_182 \I_EN_STAT_EQ1.U_STAT
(.din_i(din_i),
.s_dclk_i(s_dclk_i),
.s_den_i(s_den_i),
.s_do_o(s_do_o));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg__parameterized61
(s_do_o,
dout_o,
rst_reg_i,
din_i,
s_daddr_i,
s_di_i,
s_den_i,
s_dwe_i,
s_dclk_i); |
output [15:0]s_do_o;
output [15:0]dout_o;
input rst_reg_i;
input [15:0]din_i;
input [12:0]s_daddr_i;
input [15:0]s_di_i;
input s_den_i;
input s_dwe_i;
input s_dclk_i;
wire \<const0> ;
wire [15:0]din_i;
wire s_dclk_i;
wire s_den_i;
wire [15:0]s_do_o;
assign dout_o[15] = \<const0> ;
assign dout_o[14] = \<const0> ;
assign dout_o[13] = \<const0> ;
assign dout_o[12] = \<const0> ;
assign dout_o[11] = \<const0> ;
assign dout_o[10] = \<const0> ;
assign dout_o[9] = \<const0> ;
assign dout_o[8] = \<const0> ;
assign dout_o[7] = \<const0> ;
assign dout_o[6] = \<const0> ;
assign dout_o[5] = \<const0> ;
assign dout_o[4] = \<const0> ;
assign dout_o[3] = \<const0> ;
assign dout_o[2] = \<const0> ;
assign dout_o[1] = \<const0> ;
assign dout_o[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_stat_182 \I_EN_STAT_EQ1.U_STAT
(.din_i(din_i),
.s_dclk_i(s_dclk_i),
.s_den_i(s_den_i),
.s_do_o(s_do_o));
endmodule | 8 |
2,412 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl
(\xsdb_reg_reg[0]_0 ,
\xsdb_reg_reg[0]_1 ,
\xsdb_reg_reg[0]_2 ,
\slaveRegDo_mux_3_reg[15] ,
\slaveRegDo_mux_3_reg[14] ,
\slaveRegDo_mux_3_reg[13] ,
\slaveRegDo_mux_3_reg[12] ,
\slaveRegDo_mux_3_reg[11] ,
\slaveRegDo_mux_3_reg[10] ,
\slaveRegDo_mux_3_reg[9] ,
\slaveRegDo_mux_3_reg[8] ,
\slaveRegDo_mux_3_reg[7] ,
\slaveRegDo_mux_3_reg[6] ,
\slaveRegDo_mux_3_reg[5] ,
\slaveRegDo_mux_3_reg[4] ,
\slaveRegDo_mux_3_reg[3] ,
\slaveRegDo_mux_3_reg[2] ,
debug_data_in,
s_daddr_o,
s_dwe_o,
s_den_o,
s_di_o,
s_dclk_o);
output \xsdb_reg_reg[0]_0 ;
output \xsdb_reg_reg[0]_1 ;
output \xsdb_reg_reg[0]_2 ;
output \slaveRegDo_mux_3_reg[15] ;
output \slaveRegDo_mux_3_reg[14] ;
output \slaveRegDo_mux_3_reg[13] ;
output \slaveRegDo_mux_3_reg[12] ;
output \slaveRegDo_mux_3_reg[11] ;
output \slaveRegDo_mux_3_reg[10] ;
output \slaveRegDo_mux_3_reg[9] ;
output \slaveRegDo_mux_3_reg[8] ;
output \slaveRegDo_mux_3_reg[7] ;
output \slaveRegDo_mux_3_reg[6] ;
output \slaveRegDo_mux_3_reg[5] ;
output \slaveRegDo_mux_3_reg[4] ;
output \slaveRegDo_mux_3_reg[3] ;
output \slaveRegDo_mux_3_reg[2] ;
output [1:0]debug_data_in;
input [12:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [15:0]s_di_o;
input s_dclk_o;
wire [1:0]debug_data_in;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_3_reg[10] ;
wire \slaveRegDo_mux_3_reg[11] ;
wire \slaveRegDo_mux_3_reg[12] ;
wire \slaveRegDo_mux_3_reg[13] ;
wire \slaveRegDo_mux_3_reg[14] ;
wire \slaveRegDo_mux_3_reg[15] ;
wire \slaveRegDo_mux_3_reg[2] ;
wire \slaveRegDo_mux_3_reg[3] ;
wire \slaveRegDo_mux_3_reg[4] ;
wire \slaveRegDo_mux_3_reg[5] ;
wire \slaveRegDo_mux_3_reg[6] ;
wire \slaveRegDo_mux_3_reg[7] ;
wire \slaveRegDo_mux_3_reg[8] ;
wire \slaveRegDo_mux_3_reg[9] ;
wire \xsdb_reg[15]_i_1__6_n_0 ;
wire \xsdb_reg[15]_i_3__3_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[0]_1 ;
wire \xsdb_reg_reg[0]_2 ;
LUT6 #(
.INIT(64'h0000000000000020))
\xsdb_reg[15]_i_1__6
(.I0(\xsdb_reg_reg[0]_0 ),
.I1(\xsdb_reg[15]_i_3__3_n_0 ),
.I2(\xsdb_reg_reg[0]_1 ),
.I3(s_daddr_o[12]),
.I4(s_daddr_o[1]),
.I5(\xsdb_reg_reg[0]_2 ),
.O(\xsdb_reg[15]_i_1__6_n_0 ));
LUT4 #(
.INIT(16'h8000))
\xsdb_reg[15]_i_2
(.I0(s_daddr_o[7]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[6]),
.I3(s_daddr_o[4]),
.O(\xsdb_reg_reg[0]_0 ));
LUT3 #(
.INIT(8'h7F))
\xsdb_reg[15]_i_3__3
(.I0(s_daddr_o[0]),
.I1(s_dwe_o),
.I2(s_daddr_o[2]),
.O(\xsdb_reg[15]_i_3__3_n_0 ));
LUT2 #(
.INIT(4'h8))
\xsdb_reg[15]_i_4
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[11]),
.O(\xsdb_reg_reg[0]_1 ));
LUT4 #(
.INIT(16'h7FFF))
\xsdb_reg[15]_i_5
(.I0(s_daddr_o[8]),
.I1(s_daddr_o[9]),
.I2(s_daddr_o[10]),
.I3(s_den_o),
.O(\xsdb_reg_reg[0]_2 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[0]),
.Q(debug_data_in[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_3_reg[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_3_reg[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_3_reg[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_3_reg[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_3_reg[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_3_reg[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[1]),
.Q(debug_data_in[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[2]),
.Q(\slaveRegDo_mux_3_reg[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_3_reg[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_3_reg[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_3_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_3_reg[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_3_reg[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_3_reg[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_3_reg[9] ),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl
(\xsdb_reg_reg[0]_0 ,
\xsdb_reg_reg[0]_1 ,
\xsdb_reg_reg[0]_2 ,
\slaveRegDo_mux_3_reg[15] ,
\slaveRegDo_mux_3_reg[14] ,
\slaveRegDo_mux_3_reg[13] ,
\slaveRegDo_mux_3_reg[12] ,
\slaveRegDo_mux_3_reg[11] ,
\slaveRegDo_mux_3_reg[10] ,
\slaveRegDo_mux_3_reg[9] ,
\slaveRegDo_mux_3_reg[8] ,
\slaveRegDo_mux_3_reg[7] ,
\slaveRegDo_mux_3_reg[6] ,
\slaveRegDo_mux_3_reg[5] ,
\slaveRegDo_mux_3_reg[4] ,
\slaveRegDo_mux_3_reg[3] ,
\slaveRegDo_mux_3_reg[2] ,
debug_data_in,
s_daddr_o,
s_dwe_o,
s_den_o,
s_di_o,
s_dclk_o); |
output \xsdb_reg_reg[0]_0 ;
output \xsdb_reg_reg[0]_1 ;
output \xsdb_reg_reg[0]_2 ;
output \slaveRegDo_mux_3_reg[15] ;
output \slaveRegDo_mux_3_reg[14] ;
output \slaveRegDo_mux_3_reg[13] ;
output \slaveRegDo_mux_3_reg[12] ;
output \slaveRegDo_mux_3_reg[11] ;
output \slaveRegDo_mux_3_reg[10] ;
output \slaveRegDo_mux_3_reg[9] ;
output \slaveRegDo_mux_3_reg[8] ;
output \slaveRegDo_mux_3_reg[7] ;
output \slaveRegDo_mux_3_reg[6] ;
output \slaveRegDo_mux_3_reg[5] ;
output \slaveRegDo_mux_3_reg[4] ;
output \slaveRegDo_mux_3_reg[3] ;
output \slaveRegDo_mux_3_reg[2] ;
output [1:0]debug_data_in;
input [12:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [15:0]s_di_o;
input s_dclk_o;
wire [1:0]debug_data_in;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_3_reg[10] ;
wire \slaveRegDo_mux_3_reg[11] ;
wire \slaveRegDo_mux_3_reg[12] ;
wire \slaveRegDo_mux_3_reg[13] ;
wire \slaveRegDo_mux_3_reg[14] ;
wire \slaveRegDo_mux_3_reg[15] ;
wire \slaveRegDo_mux_3_reg[2] ;
wire \slaveRegDo_mux_3_reg[3] ;
wire \slaveRegDo_mux_3_reg[4] ;
wire \slaveRegDo_mux_3_reg[5] ;
wire \slaveRegDo_mux_3_reg[6] ;
wire \slaveRegDo_mux_3_reg[7] ;
wire \slaveRegDo_mux_3_reg[8] ;
wire \slaveRegDo_mux_3_reg[9] ;
wire \xsdb_reg[15]_i_1__6_n_0 ;
wire \xsdb_reg[15]_i_3__3_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[0]_1 ;
wire \xsdb_reg_reg[0]_2 ;
LUT6 #(
.INIT(64'h0000000000000020))
\xsdb_reg[15]_i_1__6
(.I0(\xsdb_reg_reg[0]_0 ),
.I1(\xsdb_reg[15]_i_3__3_n_0 ),
.I2(\xsdb_reg_reg[0]_1 ),
.I3(s_daddr_o[12]),
.I4(s_daddr_o[1]),
.I5(\xsdb_reg_reg[0]_2 ),
.O(\xsdb_reg[15]_i_1__6_n_0 ));
LUT4 #(
.INIT(16'h8000))
\xsdb_reg[15]_i_2
(.I0(s_daddr_o[7]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[6]),
.I3(s_daddr_o[4]),
.O(\xsdb_reg_reg[0]_0 ));
LUT3 #(
.INIT(8'h7F))
\xsdb_reg[15]_i_3__3
(.I0(s_daddr_o[0]),
.I1(s_dwe_o),
.I2(s_daddr_o[2]),
.O(\xsdb_reg[15]_i_3__3_n_0 ));
LUT2 #(
.INIT(4'h8))
\xsdb_reg[15]_i_4
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[11]),
.O(\xsdb_reg_reg[0]_1 ));
LUT4 #(
.INIT(16'h7FFF))
\xsdb_reg[15]_i_5
(.I0(s_daddr_o[8]),
.I1(s_daddr_o[9]),
.I2(s_daddr_o[10]),
.I3(s_den_o),
.O(\xsdb_reg_reg[0]_2 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[0]),
.Q(debug_data_in[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_3_reg[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_3_reg[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_3_reg[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_3_reg[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_3_reg[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_3_reg[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[1]),
.Q(debug_data_in[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[2]),
.Q(\slaveRegDo_mux_3_reg[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_3_reg[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_3_reg[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_3_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_3_reg[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_3_reg[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_3_reg[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__6_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_3_reg[9] ),
.R(1'b0));
endmodule | 8 |
2,413 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_169
(\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[10] ,
s_daddr_o,
s_di_o,
s_dclk_o);
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
input [2:0]s_daddr_o;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__9_n_0 ;
LUT5 #(
.INIT(32'h00000008))
\xsdb_reg[15]_i_1__9
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[10] ),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[0]),
.O(\xsdb_reg[15]_i_1__9_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[0]),
.Q(\slaveRegDo_mux_0_reg[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[1]),
.Q(\slaveRegDo_mux_0_reg[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[2]),
.Q(\slaveRegDo_mux_0_reg[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_0_reg[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_0_reg[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[9] ),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_169
(\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[10] ,
s_daddr_o,
s_di_o,
s_dclk_o); |
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
input [2:0]s_daddr_o;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__9_n_0 ;
LUT5 #(
.INIT(32'h00000008))
\xsdb_reg[15]_i_1__9
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[10] ),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[0]),
.O(\xsdb_reg[15]_i_1__9_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[0]),
.Q(\slaveRegDo_mux_0_reg[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[1]),
.Q(\slaveRegDo_mux_0_reg[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[2]),
.Q(\slaveRegDo_mux_0_reg[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_0_reg[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_0_reg[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__9_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[9] ),
.R(1'b0));
endmodule | 8 |
2,414 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_170
(\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
\slaveRegDo_mux_0_reg[15] ,
s_daddr_o,
\xsdb_reg_reg[4]_0 ,
\xsdb_reg_reg[3]_0 ,
\xsdb_reg_reg[2]_0 ,
\xsdb_reg_reg[1]_0 ,
\xsdb_reg_reg[0]_0 ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] );
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
output [10:0]\slaveRegDo_mux_0_reg[15] ;
input [2:0]s_daddr_o;
input \xsdb_reg_reg[4]_0 ;
input \xsdb_reg_reg[3]_0 ;
input \xsdb_reg_reg[2]_0 ;
input \xsdb_reg_reg[1]_0 ;
input \xsdb_reg_reg[0]_0 ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [4:0]slaveRegDo_84;
wire \slaveRegDo_mux_0_reg[0] ;
wire [10:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \xsdb_reg[15]_i_1__4_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[1]_0 ;
wire \xsdb_reg_reg[2]_0 ;
wire \xsdb_reg_reg[3]_0 ;
wire \xsdb_reg_reg[4]_0 ;
LUT4 #(
.INIT(16'h00E2))
\slaveRegDo_mux_0[0]_i_8
(.I0(slaveRegDo_84[0]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[0]_0 ),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[0] ));
LUT4 #(
.INIT(16'h00E2))
\slaveRegDo_mux_0[1]_i_9
(.I0(slaveRegDo_84[1]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[1]_0 ),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[1] ));
LUT4 #(
.INIT(16'h00E2))
\slaveRegDo_mux_0[2]_i_9
(.I0(slaveRegDo_84[2]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[2]_0 ),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[2] ));
LUT4 #(
.INIT(16'h00E2))
\slaveRegDo_mux_0[3]_i_8
(.I0(slaveRegDo_84[3]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[3]_0 ),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[3] ));
LUT4 #(
.INIT(16'h00E2))
\slaveRegDo_mux_0[4]_i_11
(.I0(slaveRegDo_84[4]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[4]_0 ),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[4] ));
LUT5 #(
.INIT(32'h00200000))
\xsdb_reg[15]_i_1__4
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(\xsdb_reg[15]_i_1__4_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[0]),
.Q(slaveRegDo_84[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[15] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[15] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[15] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[15] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[15] [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_84[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[2]),
.Q(slaveRegDo_84[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[3]),
.Q(slaveRegDo_84[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[4]),
.Q(slaveRegDo_84[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[15] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[15] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[15] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[15] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[15] [4]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_170
(\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
\slaveRegDo_mux_0_reg[15] ,
s_daddr_o,
\xsdb_reg_reg[4]_0 ,
\xsdb_reg_reg[3]_0 ,
\xsdb_reg_reg[2]_0 ,
\xsdb_reg_reg[1]_0 ,
\xsdb_reg_reg[0]_0 ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ); |
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
output [10:0]\slaveRegDo_mux_0_reg[15] ;
input [2:0]s_daddr_o;
input \xsdb_reg_reg[4]_0 ;
input \xsdb_reg_reg[3]_0 ;
input \xsdb_reg_reg[2]_0 ;
input \xsdb_reg_reg[1]_0 ;
input \xsdb_reg_reg[0]_0 ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [4:0]slaveRegDo_84;
wire \slaveRegDo_mux_0_reg[0] ;
wire [10:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \xsdb_reg[15]_i_1__4_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[1]_0 ;
wire \xsdb_reg_reg[2]_0 ;
wire \xsdb_reg_reg[3]_0 ;
wire \xsdb_reg_reg[4]_0 ;
LUT4 #(
.INIT(16'h00E2))
\slaveRegDo_mux_0[0]_i_8
(.I0(slaveRegDo_84[0]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[0]_0 ),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[0] ));
LUT4 #(
.INIT(16'h00E2))
\slaveRegDo_mux_0[1]_i_9
(.I0(slaveRegDo_84[1]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[1]_0 ),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[1] ));
LUT4 #(
.INIT(16'h00E2))
\slaveRegDo_mux_0[2]_i_9
(.I0(slaveRegDo_84[2]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[2]_0 ),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[2] ));
LUT4 #(
.INIT(16'h00E2))
\slaveRegDo_mux_0[3]_i_8
(.I0(slaveRegDo_84[3]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[3]_0 ),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[3] ));
LUT4 #(
.INIT(16'h00E2))
\slaveRegDo_mux_0[4]_i_11
(.I0(slaveRegDo_84[4]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[4]_0 ),
.I3(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[4] ));
LUT5 #(
.INIT(32'h00200000))
\xsdb_reg[15]_i_1__4
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(\xsdb_reg[15]_i_1__4_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[0]),
.Q(slaveRegDo_84[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[15] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[15] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[15] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[15] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[15] [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_84[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[2]),
.Q(slaveRegDo_84[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[3]),
.Q(slaveRegDo_84[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[4]),
.Q(slaveRegDo_84[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[15] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[15] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[15] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[15] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__4_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[15] [4]),
.R(1'b0));
endmodule | 8 |
2,415 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_171
(\xsdb_reg_reg[0]_0 ,
\xsdb_reg_reg[0]_1 ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
s_den_o,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
slaveRegDo_84,
\xsdb_reg_reg[15]_0 ,
\xsdb_reg_reg[14]_0 ,
\xsdb_reg_reg[14]_1 ,
\xsdb_reg_reg[13]_0 ,
\xsdb_reg_reg[13]_1 ,
\xsdb_reg_reg[12]_0 ,
\xsdb_reg_reg[12]_1 ,
\xsdb_reg_reg[11]_0 ,
\xsdb_reg_reg[11]_1 ,
\xsdb_reg_reg[10]_0 ,
\xsdb_reg_reg[10]_1 ,
\xsdb_reg_reg[9]_0 ,
\xsdb_reg_reg[9]_1 ,
\xsdb_reg_reg[8]_0 ,
\xsdb_reg_reg[8]_1 ,
\xsdb_reg_reg[7]_0 ,
\xsdb_reg_reg[7]_1 ,
\xsdb_reg_reg[6]_0 ,
\xsdb_reg_reg[6]_1 ,
\xsdb_reg_reg[5]_0 ,
\xsdb_reg_reg[5]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\xsdb_reg_reg[4]_0 ,
\xsdb_reg_reg[3]_0 ,
\xsdb_reg_reg[2]_0 ,
\xsdb_reg_reg[1]_0 ,
\xsdb_reg_reg[0]_2 ,
slaveRegDo_82,
slaveRegDo_81,
slaveRegDo_80,
s_di_o,
s_dclk_o);
output \xsdb_reg_reg[0]_0 ;
output \xsdb_reg_reg[0]_1 ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input s_den_o;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input [12:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [10:0]slaveRegDo_84;
input \xsdb_reg_reg[15]_0 ;
input \xsdb_reg_reg[14]_0 ;
input \xsdb_reg_reg[14]_1 ;
input \xsdb_reg_reg[13]_0 ;
input \xsdb_reg_reg[13]_1 ;
input \xsdb_reg_reg[12]_0 ;
input \xsdb_reg_reg[12]_1 ;
input \xsdb_reg_reg[11]_0 ;
input \xsdb_reg_reg[11]_1 ;
input \xsdb_reg_reg[10]_0 ;
input \xsdb_reg_reg[10]_1 ;
input \xsdb_reg_reg[9]_0 ;
input \xsdb_reg_reg[9]_1 ;
input \xsdb_reg_reg[8]_0 ;
input \xsdb_reg_reg[8]_1 ;
input \xsdb_reg_reg[7]_0 ;
input \xsdb_reg_reg[7]_1 ;
input \xsdb_reg_reg[6]_0 ;
input \xsdb_reg_reg[6]_1 ;
input \xsdb_reg_reg[5]_0 ;
input \xsdb_reg_reg[5]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \xsdb_reg_reg[4]_0 ;
input \xsdb_reg_reg[3]_0 ;
input \xsdb_reg_reg[2]_0 ;
input \xsdb_reg_reg[1]_0 ;
input \xsdb_reg_reg[0]_2 ;
input [15:0]slaveRegDo_82;
input [15:0]slaveRegDo_81;
input [15:0]slaveRegDo_80;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire [15:0]slaveRegDo_80;
wire [15:0]slaveRegDo_81;
wire [15:0]slaveRegDo_82;
wire [10:0]slaveRegDo_84;
wire \slaveRegDo_mux_0[0]_i_7_n_0 ;
wire \slaveRegDo_mux_0[10]_i_2_n_0 ;
wire \slaveRegDo_mux_0[10]_i_4_n_0 ;
wire \slaveRegDo_mux_0[11]_i_2_n_0 ;
wire \slaveRegDo_mux_0[11]_i_4_n_0 ;
wire \slaveRegDo_mux_0[12]_i_2_n_0 ;
wire \slaveRegDo_mux_0[12]_i_4_n_0 ;
wire \slaveRegDo_mux_0[13]_i_2_n_0 ;
wire \slaveRegDo_mux_0[13]_i_4_n_0 ;
wire \slaveRegDo_mux_0[14]_i_2_n_0 ;
wire \slaveRegDo_mux_0[14]_i_4_n_0 ;
wire \slaveRegDo_mux_0[15]_i_8_n_0 ;
wire \slaveRegDo_mux_0[1]_i_8_n_0 ;
wire \slaveRegDo_mux_0[2]_i_8_n_0 ;
wire \slaveRegDo_mux_0[3]_i_7_n_0 ;
wire \slaveRegDo_mux_0[4]_i_10_n_0 ;
wire \slaveRegDo_mux_0[5]_i_2_n_0 ;
wire \slaveRegDo_mux_0[5]_i_4_n_0 ;
wire \slaveRegDo_mux_0[6]_i_2_n_0 ;
wire \slaveRegDo_mux_0[6]_i_4_n_0 ;
wire \slaveRegDo_mux_0[7]_i_2_n_0 ;
wire \slaveRegDo_mux_0[7]_i_4_n_0 ;
wire \slaveRegDo_mux_0[8]_i_2_n_0 ;
wire \slaveRegDo_mux_0[8]_i_4_n_0 ;
wire \slaveRegDo_mux_0[9]_i_2_n_0 ;
wire \slaveRegDo_mux_0[9]_i_4_n_0 ;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__10_n_0 ;
wire \xsdb_reg[15]_i_3__0_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[0]_1 ;
wire \xsdb_reg_reg[0]_2 ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[10]_1 ;
wire \xsdb_reg_reg[11]_0 ;
wire \xsdb_reg_reg[11]_1 ;
wire \xsdb_reg_reg[12]_0 ;
wire \xsdb_reg_reg[12]_1 ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[13]_1 ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[14]_1 ;
wire \xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg[1]_0 ;
wire \xsdb_reg_reg[2]_0 ;
wire \xsdb_reg_reg[3]_0 ;
wire \xsdb_reg_reg[4]_0 ;
wire \xsdb_reg_reg[5]_0 ;
wire \xsdb_reg_reg[5]_1 ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[6]_1 ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[7]_1 ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[8]_1 ;
wire \xsdb_reg_reg[9]_0 ;
wire \xsdb_reg_reg[9]_1 ;
wire \xsdb_reg_reg_n_0_[0] ;
wire \xsdb_reg_reg_n_0_[10] ;
wire \xsdb_reg_reg_n_0_[11] ;
wire \xsdb_reg_reg_n_0_[12] ;
wire \xsdb_reg_reg_n_0_[13] ;
wire \xsdb_reg_reg_n_0_[14] ;
wire \xsdb_reg_reg_n_0_[15] ;
wire \xsdb_reg_reg_n_0_[1] ;
wire \xsdb_reg_reg_n_0_[2] ;
wire \xsdb_reg_reg_n_0_[3] ;
wire \xsdb_reg_reg_n_0_[4] ;
wire \xsdb_reg_reg_n_0_[5] ;
wire \xsdb_reg_reg_n_0_[6] ;
wire \xsdb_reg_reg_n_0_[7] ;
wire \xsdb_reg_reg_n_0_[8] ;
wire \xsdb_reg_reg_n_0_[9] ;
LUT6 #(
.INIT(64'hFFFAFFFBFFFFFFFB))
\slaveRegDo_mux_0[0]_i_3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(\slaveRegDo_mux_0[0]_i_7_n_0 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.I5(\xsdb_reg_reg[0]_2 ),
.O(\slaveRegDo_mux_0_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[0]_i_7
(.I0(\xsdb_reg_reg_n_0_[0] ),
.I1(slaveRegDo_82[0]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[0]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[0]),
.O(\slaveRegDo_mux_0[0]_i_7_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[10]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[10]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[10]_0 ),
.O(\slaveRegDo_mux_0_reg[10] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[10]_i_2
(.I0(\slaveRegDo_mux_0[10]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[5]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[10]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[10]_i_4
(.I0(\xsdb_reg_reg_n_0_[10] ),
.I1(slaveRegDo_82[10]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[10]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[10]),
.O(\slaveRegDo_mux_0[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[11]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[11]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[11]_0 ),
.O(\slaveRegDo_mux_0_reg[11] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[11]_i_2
(.I0(\slaveRegDo_mux_0[11]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[6]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[11]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[11]_i_4
(.I0(\xsdb_reg_reg_n_0_[11] ),
.I1(slaveRegDo_82[11]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[11]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[11]),
.O(\slaveRegDo_mux_0[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[12]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[12]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[12]_0 ),
.O(\slaveRegDo_mux_0_reg[12] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[12]_i_2
(.I0(\slaveRegDo_mux_0[12]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[7]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[12]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[12]_i_4
(.I0(\xsdb_reg_reg_n_0_[12] ),
.I1(slaveRegDo_82[12]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[12]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[12]),
.O(\slaveRegDo_mux_0[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[13]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[13]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[13]_0 ),
.O(\slaveRegDo_mux_0_reg[13] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[13]_i_2
(.I0(\slaveRegDo_mux_0[13]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[8]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[13]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[13]_i_4
(.I0(\xsdb_reg_reg_n_0_[13] ),
.I1(slaveRegDo_82[13]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[13]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[13]),
.O(\slaveRegDo_mux_0[13]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[14]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[14]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[14]_0 ),
.O(\slaveRegDo_mux_0_reg[14] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[14]_i_2
(.I0(\slaveRegDo_mux_0[14]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[9]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[14]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[14]_i_4
(.I0(\xsdb_reg_reg_n_0_[14] ),
.I1(slaveRegDo_82[14]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[14]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[14]),
.O(\slaveRegDo_mux_0[14]_i_4_n_0 ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[15]_i_4
(.I0(\slaveRegDo_mux_0[15]_i_8_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[10]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[15] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[15]_i_8
(.I0(\xsdb_reg_reg_n_0_[15] ),
.I1(slaveRegDo_82[15]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[15]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[15]),
.O(\slaveRegDo_mux_0[15]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFAFFFBFFFFFFFB))
\slaveRegDo_mux_0[1]_i_3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(\slaveRegDo_mux_0[1]_i_8_n_0 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.I5(\xsdb_reg_reg[1]_0 ),
.O(\slaveRegDo_mux_0_reg[1] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[1]_i_8
(.I0(\xsdb_reg_reg_n_0_[1] ),
.I1(slaveRegDo_82[1]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[1]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[1]),
.O(\slaveRegDo_mux_0[1]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFAFFFBFFFFFFFB))
\slaveRegDo_mux_0[2]_i_3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(\slaveRegDo_mux_0[2]_i_8_n_0 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.I5(\xsdb_reg_reg[2]_0 ),
.O(\slaveRegDo_mux_0_reg[2] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[2]_i_8
(.I0(\xsdb_reg_reg_n_0_[2] ),
.I1(slaveRegDo_82[2]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[2]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[2]),
.O(\slaveRegDo_mux_0[2]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFAFFFBFFFFFFFB))
\slaveRegDo_mux_0[3]_i_3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(\slaveRegDo_mux_0[3]_i_7_n_0 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.I5(\xsdb_reg_reg[3]_0 ),
.O(\slaveRegDo_mux_0_reg[3] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[3]_i_7
(.I0(\xsdb_reg_reg_n_0_[3] ),
.I1(slaveRegDo_82[3]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[3]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[3]),
.O(\slaveRegDo_mux_0[3]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[4]_i_10
(.I0(\xsdb_reg_reg_n_0_[4] ),
.I1(slaveRegDo_82[4]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[4]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[4]),
.O(\slaveRegDo_mux_0[4]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFFFAFFFBFFFFFFFB))
\slaveRegDo_mux_0[4]_i_4
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(\slaveRegDo_mux_0[4]_i_10_n_0 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.I5(\xsdb_reg_reg[4]_0 ),
.O(\slaveRegDo_mux_0_reg[4] ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[5]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[5]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[5]_0 ),
.O(\slaveRegDo_mux_0_reg[5] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[5]_i_2
(.I0(\slaveRegDo_mux_0[5]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[0]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[5]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[5]_i_4
(.I0(\xsdb_reg_reg_n_0_[5] ),
.I1(slaveRegDo_82[5]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[5]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[5]),
.O(\slaveRegDo_mux_0[5]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[6]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[6]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[6]_0 ),
.O(\slaveRegDo_mux_0_reg[6] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[6]_i_2
(.I0(\slaveRegDo_mux_0[6]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[1]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[6]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[6]_i_4
(.I0(\xsdb_reg_reg_n_0_[6] ),
.I1(slaveRegDo_82[6]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[6]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[6]),
.O(\slaveRegDo_mux_0[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[7]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[7]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[7]_0 ),
.O(\slaveRegDo_mux_0_reg[7] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[7]_i_2
(.I0(\slaveRegDo_mux_0[7]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[2]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[7]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[7]_i_4
(.I0(\xsdb_reg_reg_n_0_[7] ),
.I1(slaveRegDo_82[7]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[7]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[7]),
.O(\slaveRegDo_mux_0[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[8]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[8]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[8]_0 ),
.O(\slaveRegDo_mux_0_reg[8] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[8]_i_2
(.I0(\slaveRegDo_mux_0[8]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[3]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[8]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[8]_i_4
(.I0(\xsdb_reg_reg_n_0_[8] ),
.I1(slaveRegDo_82[8]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[8]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[8]),
.O(\slaveRegDo_mux_0[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[9]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[9]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[9]_0 ),
.O(\slaveRegDo_mux_0_reg[9] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[9]_i_2
(.I0(\slaveRegDo_mux_0[9]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[4]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[9]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[9]_i_4
(.I0(\xsdb_reg_reg_n_0_[9] ),
.I1(slaveRegDo_82[9]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[9]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[9]),
.O(\slaveRegDo_mux_0[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000800000000000))
\xsdb_reg[15]_i_1__10
(.I0(\xsdb_reg_reg[0]_0 ),
.I1(\xsdb_reg[15]_i_3__0_n_0 ),
.I2(s_den_o),
.I3(s_dwe_o),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I5(\xsdb_reg_reg[0]_1 ),
.O(\xsdb_reg[15]_i_1__10_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\xsdb_reg[15]_i_2__1
(.I0(s_daddr_o[10]),
.I1(s_daddr_o[11]),
.I2(s_daddr_o[12]),
.I3(s_daddr_o[7]),
.I4(s_daddr_o[9]),
.I5(s_daddr_o[8]),
.O(\xsdb_reg_reg[0]_0 ));
LUT3 #(
.INIT(8'h01))
\xsdb_reg[15]_i_3__0
(.I0(s_daddr_o[5]),
.I1(s_daddr_o[6]),
.I2(s_daddr_o[4]),
.O(\xsdb_reg[15]_i_3__0_n_0 ));
LUT2 #(
.INIT(4'h8))
\xsdb_reg[15]_i_5__0
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[0]),
.O(\xsdb_reg_reg[0]_1 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[0]),
.Q(\xsdb_reg_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[10]),
.Q(\xsdb_reg_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[11]),
.Q(\xsdb_reg_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[12]),
.Q(\xsdb_reg_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[13]),
.Q(\xsdb_reg_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[14]),
.Q(\xsdb_reg_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[15]),
.Q(\xsdb_reg_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[1]),
.Q(\xsdb_reg_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[2]),
.Q(\xsdb_reg_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[3]),
.Q(\xsdb_reg_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[4]),
.Q(\xsdb_reg_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[5]),
.Q(\xsdb_reg_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[6]),
.Q(\xsdb_reg_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[7]),
.Q(\xsdb_reg_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[8]),
.Q(\xsdb_reg_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[9]),
.Q(\xsdb_reg_reg_n_0_[9] ),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_171
(\xsdb_reg_reg[0]_0 ,
\xsdb_reg_reg[0]_1 ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
s_den_o,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
slaveRegDo_84,
\xsdb_reg_reg[15]_0 ,
\xsdb_reg_reg[14]_0 ,
\xsdb_reg_reg[14]_1 ,
\xsdb_reg_reg[13]_0 ,
\xsdb_reg_reg[13]_1 ,
\xsdb_reg_reg[12]_0 ,
\xsdb_reg_reg[12]_1 ,
\xsdb_reg_reg[11]_0 ,
\xsdb_reg_reg[11]_1 ,
\xsdb_reg_reg[10]_0 ,
\xsdb_reg_reg[10]_1 ,
\xsdb_reg_reg[9]_0 ,
\xsdb_reg_reg[9]_1 ,
\xsdb_reg_reg[8]_0 ,
\xsdb_reg_reg[8]_1 ,
\xsdb_reg_reg[7]_0 ,
\xsdb_reg_reg[7]_1 ,
\xsdb_reg_reg[6]_0 ,
\xsdb_reg_reg[6]_1 ,
\xsdb_reg_reg[5]_0 ,
\xsdb_reg_reg[5]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\xsdb_reg_reg[4]_0 ,
\xsdb_reg_reg[3]_0 ,
\xsdb_reg_reg[2]_0 ,
\xsdb_reg_reg[1]_0 ,
\xsdb_reg_reg[0]_2 ,
slaveRegDo_82,
slaveRegDo_81,
slaveRegDo_80,
s_di_o,
s_dclk_o); |
output \xsdb_reg_reg[0]_0 ;
output \xsdb_reg_reg[0]_1 ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input s_den_o;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input [12:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [10:0]slaveRegDo_84;
input \xsdb_reg_reg[15]_0 ;
input \xsdb_reg_reg[14]_0 ;
input \xsdb_reg_reg[14]_1 ;
input \xsdb_reg_reg[13]_0 ;
input \xsdb_reg_reg[13]_1 ;
input \xsdb_reg_reg[12]_0 ;
input \xsdb_reg_reg[12]_1 ;
input \xsdb_reg_reg[11]_0 ;
input \xsdb_reg_reg[11]_1 ;
input \xsdb_reg_reg[10]_0 ;
input \xsdb_reg_reg[10]_1 ;
input \xsdb_reg_reg[9]_0 ;
input \xsdb_reg_reg[9]_1 ;
input \xsdb_reg_reg[8]_0 ;
input \xsdb_reg_reg[8]_1 ;
input \xsdb_reg_reg[7]_0 ;
input \xsdb_reg_reg[7]_1 ;
input \xsdb_reg_reg[6]_0 ;
input \xsdb_reg_reg[6]_1 ;
input \xsdb_reg_reg[5]_0 ;
input \xsdb_reg_reg[5]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \xsdb_reg_reg[4]_0 ;
input \xsdb_reg_reg[3]_0 ;
input \xsdb_reg_reg[2]_0 ;
input \xsdb_reg_reg[1]_0 ;
input \xsdb_reg_reg[0]_2 ;
input [15:0]slaveRegDo_82;
input [15:0]slaveRegDo_81;
input [15:0]slaveRegDo_80;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire [15:0]slaveRegDo_80;
wire [15:0]slaveRegDo_81;
wire [15:0]slaveRegDo_82;
wire [10:0]slaveRegDo_84;
wire \slaveRegDo_mux_0[0]_i_7_n_0 ;
wire \slaveRegDo_mux_0[10]_i_2_n_0 ;
wire \slaveRegDo_mux_0[10]_i_4_n_0 ;
wire \slaveRegDo_mux_0[11]_i_2_n_0 ;
wire \slaveRegDo_mux_0[11]_i_4_n_0 ;
wire \slaveRegDo_mux_0[12]_i_2_n_0 ;
wire \slaveRegDo_mux_0[12]_i_4_n_0 ;
wire \slaveRegDo_mux_0[13]_i_2_n_0 ;
wire \slaveRegDo_mux_0[13]_i_4_n_0 ;
wire \slaveRegDo_mux_0[14]_i_2_n_0 ;
wire \slaveRegDo_mux_0[14]_i_4_n_0 ;
wire \slaveRegDo_mux_0[15]_i_8_n_0 ;
wire \slaveRegDo_mux_0[1]_i_8_n_0 ;
wire \slaveRegDo_mux_0[2]_i_8_n_0 ;
wire \slaveRegDo_mux_0[3]_i_7_n_0 ;
wire \slaveRegDo_mux_0[4]_i_10_n_0 ;
wire \slaveRegDo_mux_0[5]_i_2_n_0 ;
wire \slaveRegDo_mux_0[5]_i_4_n_0 ;
wire \slaveRegDo_mux_0[6]_i_2_n_0 ;
wire \slaveRegDo_mux_0[6]_i_4_n_0 ;
wire \slaveRegDo_mux_0[7]_i_2_n_0 ;
wire \slaveRegDo_mux_0[7]_i_4_n_0 ;
wire \slaveRegDo_mux_0[8]_i_2_n_0 ;
wire \slaveRegDo_mux_0[8]_i_4_n_0 ;
wire \slaveRegDo_mux_0[9]_i_2_n_0 ;
wire \slaveRegDo_mux_0[9]_i_4_n_0 ;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__10_n_0 ;
wire \xsdb_reg[15]_i_3__0_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[0]_1 ;
wire \xsdb_reg_reg[0]_2 ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[10]_1 ;
wire \xsdb_reg_reg[11]_0 ;
wire \xsdb_reg_reg[11]_1 ;
wire \xsdb_reg_reg[12]_0 ;
wire \xsdb_reg_reg[12]_1 ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[13]_1 ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[14]_1 ;
wire \xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg[1]_0 ;
wire \xsdb_reg_reg[2]_0 ;
wire \xsdb_reg_reg[3]_0 ;
wire \xsdb_reg_reg[4]_0 ;
wire \xsdb_reg_reg[5]_0 ;
wire \xsdb_reg_reg[5]_1 ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[6]_1 ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[7]_1 ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[8]_1 ;
wire \xsdb_reg_reg[9]_0 ;
wire \xsdb_reg_reg[9]_1 ;
wire \xsdb_reg_reg_n_0_[0] ;
wire \xsdb_reg_reg_n_0_[10] ;
wire \xsdb_reg_reg_n_0_[11] ;
wire \xsdb_reg_reg_n_0_[12] ;
wire \xsdb_reg_reg_n_0_[13] ;
wire \xsdb_reg_reg_n_0_[14] ;
wire \xsdb_reg_reg_n_0_[15] ;
wire \xsdb_reg_reg_n_0_[1] ;
wire \xsdb_reg_reg_n_0_[2] ;
wire \xsdb_reg_reg_n_0_[3] ;
wire \xsdb_reg_reg_n_0_[4] ;
wire \xsdb_reg_reg_n_0_[5] ;
wire \xsdb_reg_reg_n_0_[6] ;
wire \xsdb_reg_reg_n_0_[7] ;
wire \xsdb_reg_reg_n_0_[8] ;
wire \xsdb_reg_reg_n_0_[9] ;
LUT6 #(
.INIT(64'hFFFAFFFBFFFFFFFB))
\slaveRegDo_mux_0[0]_i_3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(\slaveRegDo_mux_0[0]_i_7_n_0 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.I5(\xsdb_reg_reg[0]_2 ),
.O(\slaveRegDo_mux_0_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[0]_i_7
(.I0(\xsdb_reg_reg_n_0_[0] ),
.I1(slaveRegDo_82[0]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[0]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[0]),
.O(\slaveRegDo_mux_0[0]_i_7_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[10]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[10]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[10]_0 ),
.O(\slaveRegDo_mux_0_reg[10] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[10]_i_2
(.I0(\slaveRegDo_mux_0[10]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[5]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[10]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[10]_i_4
(.I0(\xsdb_reg_reg_n_0_[10] ),
.I1(slaveRegDo_82[10]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[10]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[10]),
.O(\slaveRegDo_mux_0[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[11]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[11]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[11]_0 ),
.O(\slaveRegDo_mux_0_reg[11] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[11]_i_2
(.I0(\slaveRegDo_mux_0[11]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[6]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[11]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[11]_i_4
(.I0(\xsdb_reg_reg_n_0_[11] ),
.I1(slaveRegDo_82[11]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[11]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[11]),
.O(\slaveRegDo_mux_0[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[12]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[12]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[12]_0 ),
.O(\slaveRegDo_mux_0_reg[12] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[12]_i_2
(.I0(\slaveRegDo_mux_0[12]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[7]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[12]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[12]_i_4
(.I0(\xsdb_reg_reg_n_0_[12] ),
.I1(slaveRegDo_82[12]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[12]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[12]),
.O(\slaveRegDo_mux_0[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[13]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[13]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[13]_0 ),
.O(\slaveRegDo_mux_0_reg[13] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[13]_i_2
(.I0(\slaveRegDo_mux_0[13]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[8]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[13]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[13]_i_4
(.I0(\xsdb_reg_reg_n_0_[13] ),
.I1(slaveRegDo_82[13]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[13]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[13]),
.O(\slaveRegDo_mux_0[13]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[14]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[14]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[14]_0 ),
.O(\slaveRegDo_mux_0_reg[14] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[14]_i_2
(.I0(\slaveRegDo_mux_0[14]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[9]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[14]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[14]_i_4
(.I0(\xsdb_reg_reg_n_0_[14] ),
.I1(slaveRegDo_82[14]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[14]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[14]),
.O(\slaveRegDo_mux_0[14]_i_4_n_0 ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[15]_i_4
(.I0(\slaveRegDo_mux_0[15]_i_8_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[10]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[15] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[15]_i_8
(.I0(\xsdb_reg_reg_n_0_[15] ),
.I1(slaveRegDo_82[15]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[15]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[15]),
.O(\slaveRegDo_mux_0[15]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFAFFFBFFFFFFFB))
\slaveRegDo_mux_0[1]_i_3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(\slaveRegDo_mux_0[1]_i_8_n_0 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.I5(\xsdb_reg_reg[1]_0 ),
.O(\slaveRegDo_mux_0_reg[1] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[1]_i_8
(.I0(\xsdb_reg_reg_n_0_[1] ),
.I1(slaveRegDo_82[1]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[1]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[1]),
.O(\slaveRegDo_mux_0[1]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFAFFFBFFFFFFFB))
\slaveRegDo_mux_0[2]_i_3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(\slaveRegDo_mux_0[2]_i_8_n_0 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.I5(\xsdb_reg_reg[2]_0 ),
.O(\slaveRegDo_mux_0_reg[2] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[2]_i_8
(.I0(\xsdb_reg_reg_n_0_[2] ),
.I1(slaveRegDo_82[2]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[2]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[2]),
.O(\slaveRegDo_mux_0[2]_i_8_n_0 ));
LUT6 #(
.INIT(64'hFFFAFFFBFFFFFFFB))
\slaveRegDo_mux_0[3]_i_3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(\slaveRegDo_mux_0[3]_i_7_n_0 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.I5(\xsdb_reg_reg[3]_0 ),
.O(\slaveRegDo_mux_0_reg[3] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[3]_i_7
(.I0(\xsdb_reg_reg_n_0_[3] ),
.I1(slaveRegDo_82[3]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[3]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[3]),
.O(\slaveRegDo_mux_0[3]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[4]_i_10
(.I0(\xsdb_reg_reg_n_0_[4] ),
.I1(slaveRegDo_82[4]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[4]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[4]),
.O(\slaveRegDo_mux_0[4]_i_10_n_0 ));
LUT6 #(
.INIT(64'hFFFAFFFBFFFFFFFB))
\slaveRegDo_mux_0[4]_i_4
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(\slaveRegDo_mux_0[4]_i_10_n_0 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.I5(\xsdb_reg_reg[4]_0 ),
.O(\slaveRegDo_mux_0_reg[4] ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[5]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[5]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[5]_0 ),
.O(\slaveRegDo_mux_0_reg[5] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[5]_i_2
(.I0(\slaveRegDo_mux_0[5]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[0]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[5]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[5]_i_4
(.I0(\xsdb_reg_reg_n_0_[5] ),
.I1(slaveRegDo_82[5]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[5]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[5]),
.O(\slaveRegDo_mux_0[5]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[6]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[6]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[6]_0 ),
.O(\slaveRegDo_mux_0_reg[6] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[6]_i_2
(.I0(\slaveRegDo_mux_0[6]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[1]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[6]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[6]_i_4
(.I0(\xsdb_reg_reg_n_0_[6] ),
.I1(slaveRegDo_82[6]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[6]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[6]),
.O(\slaveRegDo_mux_0[6]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[7]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[7]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[7]_0 ),
.O(\slaveRegDo_mux_0_reg[7] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[7]_i_2
(.I0(\slaveRegDo_mux_0[7]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[2]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[7]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[7]_i_4
(.I0(\xsdb_reg_reg_n_0_[7] ),
.I1(slaveRegDo_82[7]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[7]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[7]),
.O(\slaveRegDo_mux_0[7]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[8]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[8]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[8]_0 ),
.O(\slaveRegDo_mux_0_reg[8] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[8]_i_2
(.I0(\slaveRegDo_mux_0[8]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[3]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[8]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[8]_i_4
(.I0(\xsdb_reg_reg_n_0_[8] ),
.I1(slaveRegDo_82[8]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[8]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[8]),
.O(\slaveRegDo_mux_0[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'h00100000001000FF))
\slaveRegDo_mux_0[9]_i_1
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[4]),
.I2(\slaveRegDo_mux_0[9]_i_2_n_0 ),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[7]),
.I5(\xsdb_reg_reg[9]_0 ),
.O(\slaveRegDo_mux_0_reg[9] ));
LUT6 #(
.INIT(64'h88888888BBB888B8))
\slaveRegDo_mux_0[9]_i_2
(.I0(\slaveRegDo_mux_0[9]_i_4_n_0 ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I2(slaveRegDo_84[4]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[9]_1 ),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_0[9]_i_4
(.I0(\xsdb_reg_reg_n_0_[9] ),
.I1(slaveRegDo_82[9]),
.I2(s_daddr_o[1]),
.I3(slaveRegDo_81[9]),
.I4(s_daddr_o[0]),
.I5(slaveRegDo_80[9]),
.O(\slaveRegDo_mux_0[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000800000000000))
\xsdb_reg[15]_i_1__10
(.I0(\xsdb_reg_reg[0]_0 ),
.I1(\xsdb_reg[15]_i_3__0_n_0 ),
.I2(s_den_o),
.I3(s_dwe_o),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I5(\xsdb_reg_reg[0]_1 ),
.O(\xsdb_reg[15]_i_1__10_n_0 ));
LUT6 #(
.INIT(64'h0000000000000100))
\xsdb_reg[15]_i_2__1
(.I0(s_daddr_o[10]),
.I1(s_daddr_o[11]),
.I2(s_daddr_o[12]),
.I3(s_daddr_o[7]),
.I4(s_daddr_o[9]),
.I5(s_daddr_o[8]),
.O(\xsdb_reg_reg[0]_0 ));
LUT3 #(
.INIT(8'h01))
\xsdb_reg[15]_i_3__0
(.I0(s_daddr_o[5]),
.I1(s_daddr_o[6]),
.I2(s_daddr_o[4]),
.O(\xsdb_reg[15]_i_3__0_n_0 ));
LUT2 #(
.INIT(4'h8))
\xsdb_reg[15]_i_5__0
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[0]),
.O(\xsdb_reg_reg[0]_1 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[0]),
.Q(\xsdb_reg_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[10]),
.Q(\xsdb_reg_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[11]),
.Q(\xsdb_reg_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[12]),
.Q(\xsdb_reg_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[13]),
.Q(\xsdb_reg_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[14]),
.Q(\xsdb_reg_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[15]),
.Q(\xsdb_reg_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[1]),
.Q(\xsdb_reg_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[2]),
.Q(\xsdb_reg_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[3]),
.Q(\xsdb_reg_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[4]),
.Q(\xsdb_reg_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[5]),
.Q(\xsdb_reg_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[6]),
.Q(\xsdb_reg_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[7]),
.Q(\xsdb_reg_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[8]),
.Q(\xsdb_reg_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__10_n_0 ),
.D(s_di_o[9]),
.Q(\xsdb_reg_reg_n_0_[9] ),
.R(1'b0));
endmodule | 8 |
2,416 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_172
(slaveRegDo_81,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] );
output [15:0]slaveRegDo_81;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_81;
wire \xsdb_reg[15]_i_1__2_n_0 ;
LUT5 #(
.INIT(32'h02000000))
\xsdb_reg[15]_i_1__2
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(\xsdb_reg[15]_i_1__2_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[0]),
.Q(slaveRegDo_81[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[10]),
.Q(slaveRegDo_81[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[11]),
.Q(slaveRegDo_81[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[12]),
.Q(slaveRegDo_81[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[13]),
.Q(slaveRegDo_81[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[14]),
.Q(slaveRegDo_81[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[15]),
.Q(slaveRegDo_81[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_81[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[2]),
.Q(slaveRegDo_81[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[3]),
.Q(slaveRegDo_81[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[4]),
.Q(slaveRegDo_81[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[5]),
.Q(slaveRegDo_81[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[6]),
.Q(slaveRegDo_81[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[7]),
.Q(slaveRegDo_81[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[8]),
.Q(slaveRegDo_81[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[9]),
.Q(slaveRegDo_81[9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_172
(slaveRegDo_81,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ); |
output [15:0]slaveRegDo_81;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_81;
wire \xsdb_reg[15]_i_1__2_n_0 ;
LUT5 #(
.INIT(32'h02000000))
\xsdb_reg[15]_i_1__2
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(\xsdb_reg[15]_i_1__2_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[0]),
.Q(slaveRegDo_81[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[10]),
.Q(slaveRegDo_81[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[11]),
.Q(slaveRegDo_81[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[12]),
.Q(slaveRegDo_81[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[13]),
.Q(slaveRegDo_81[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[14]),
.Q(slaveRegDo_81[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[15]),
.Q(slaveRegDo_81[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_81[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[2]),
.Q(slaveRegDo_81[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[3]),
.Q(slaveRegDo_81[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[4]),
.Q(slaveRegDo_81[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[5]),
.Q(slaveRegDo_81[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[6]),
.Q(slaveRegDo_81[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[7]),
.Q(slaveRegDo_81[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[8]),
.Q(slaveRegDo_81[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__2_n_0 ),
.D(s_di_o[9]),
.Q(slaveRegDo_81[9]),
.R(1'b0));
endmodule | 8 |
2,417 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_174
(\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[15] ,
s_daddr_o,
\xsdb_reg_reg[5]_0 ,
halt_ctrl,
\xsdb_reg_reg[4]_0 ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] );
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[4] ;
output [12:0]\slaveRegDo_mux_0_reg[15] ;
input [5:0]s_daddr_o;
input \xsdb_reg_reg[5]_0 ;
input halt_ctrl;
input \xsdb_reg_reg[4]_0 ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire halt_ctrl;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [5:1]slaveRegDo_6;
wire [12:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \xsdb_reg[15]_i_1_n_0 ;
wire \xsdb_reg[15]_i_3_n_0 ;
wire \xsdb_reg_reg[4]_0 ;
wire \xsdb_reg_reg[5]_0 ;
(* SOFT_HLUTNM = "soft_lutpair182" *)
LUT5 #(
.INIT(32'h0CFF77FF))
\slaveRegDo_mux_0[1]_i_7
(.I0(slaveRegDo_6[1]),
.I1(s_daddr_o[2]),
.I2(halt_ctrl),
.I3(s_daddr_o[1]),
.I4(s_daddr_o[0]),
.O(\slaveRegDo_mux_0_reg[1] ));
LUT5 #(
.INIT(32'h30FF5FF0))
\slaveRegDo_mux_0[4]_i_13
(.I0(slaveRegDo_6[4]),
.I1(\xsdb_reg_reg[4]_0 ),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[1]),
.I4(s_daddr_o[0]),
.O(\slaveRegDo_mux_0_reg[4] ));
LUT6 #(
.INIT(64'h00000000AD0D0505))
\slaveRegDo_mux_0[5]_i_7
(.I0(s_daddr_o[1]),
.I1(slaveRegDo_6[5]),
.I2(s_daddr_o[0]),
.I3(\xsdb_reg_reg[5]_0 ),
.I4(s_daddr_o[2]),
.I5(s_daddr_o[3]),
.O(\slaveRegDo_mux_0_reg[5] ));
LUT6 #(
.INIT(64'h0000000200000000))
\xsdb_reg[15]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.I1(\xsdb_reg[15]_i_3_n_0 ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[4]),
.I4(s_daddr_o[5]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.O(\xsdb_reg[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair182" *)
LUT2 #(
.INIT(4'h7))
\xsdb_reg[15]_i_3
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[1]),
.O(\xsdb_reg[15]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[0]),
.Q(\slaveRegDo_mux_0_reg[15] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[15] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[15] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[15] [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[15] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[15] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_6[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[2]),
.Q(\slaveRegDo_mux_0_reg[15] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_0_reg[15] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[4]),
.Q(slaveRegDo_6[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[5]),
.Q(slaveRegDo_6[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[15] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[15] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[15] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[15] [6]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_174
(\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[15] ,
s_daddr_o,
\xsdb_reg_reg[5]_0 ,
halt_ctrl,
\xsdb_reg_reg[4]_0 ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ); |
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[4] ;
output [12:0]\slaveRegDo_mux_0_reg[15] ;
input [5:0]s_daddr_o;
input \xsdb_reg_reg[5]_0 ;
input halt_ctrl;
input \xsdb_reg_reg[4]_0 ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire halt_ctrl;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [5:1]slaveRegDo_6;
wire [12:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \xsdb_reg[15]_i_1_n_0 ;
wire \xsdb_reg[15]_i_3_n_0 ;
wire \xsdb_reg_reg[4]_0 ;
wire \xsdb_reg_reg[5]_0 ;
(* SOFT_HLUTNM = "soft_lutpair182" *)
LUT5 #(
.INIT(32'h0CFF77FF))
\slaveRegDo_mux_0[1]_i_7
(.I0(slaveRegDo_6[1]),
.I1(s_daddr_o[2]),
.I2(halt_ctrl),
.I3(s_daddr_o[1]),
.I4(s_daddr_o[0]),
.O(\slaveRegDo_mux_0_reg[1] ));
LUT5 #(
.INIT(32'h30FF5FF0))
\slaveRegDo_mux_0[4]_i_13
(.I0(slaveRegDo_6[4]),
.I1(\xsdb_reg_reg[4]_0 ),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[1]),
.I4(s_daddr_o[0]),
.O(\slaveRegDo_mux_0_reg[4] ));
LUT6 #(
.INIT(64'h00000000AD0D0505))
\slaveRegDo_mux_0[5]_i_7
(.I0(s_daddr_o[1]),
.I1(slaveRegDo_6[5]),
.I2(s_daddr_o[0]),
.I3(\xsdb_reg_reg[5]_0 ),
.I4(s_daddr_o[2]),
.I5(s_daddr_o[3]),
.O(\slaveRegDo_mux_0_reg[5] ));
LUT6 #(
.INIT(64'h0000000200000000))
\xsdb_reg[15]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.I1(\xsdb_reg[15]_i_3_n_0 ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[4]),
.I4(s_daddr_o[5]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.O(\xsdb_reg[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair182" *)
LUT2 #(
.INIT(4'h7))
\xsdb_reg[15]_i_3
(.I0(s_daddr_o[2]),
.I1(s_daddr_o[1]),
.O(\xsdb_reg[15]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[0]),
.Q(\slaveRegDo_mux_0_reg[15] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[15] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[15] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[15] [9]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[15] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[15] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_6[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[2]),
.Q(\slaveRegDo_mux_0_reg[15] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_0_reg[15] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[4]),
.Q(slaveRegDo_6[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[5]),
.Q(slaveRegDo_6[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[15] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[15] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[15] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[15] [6]),
.R(1'b0));
endmodule | 8 |
2,418 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_175
(\xsdb_reg_reg[0]_0 ,
\xsdb_reg_reg[0]_1 ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_den_o,
s_dwe_o,
s_daddr_o,
s_di_o,
s_dclk_o);
output \xsdb_reg_reg[0]_0 ;
output \xsdb_reg_reg[0]_1 ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input s_den_o;
input s_dwe_o;
input [6:0]s_daddr_o;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__11_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[0]_1 ;
LUT6 #(
.INIT(64'h0000000080000000))
\xsdb_reg[15]_i_1__11
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.I1(s_den_o),
.I2(s_dwe_o),
.I3(\xsdb_reg_reg[0]_0 ),
.I4(s_daddr_o[4]),
.I5(\xsdb_reg_reg[0]_1 ),
.O(\xsdb_reg[15]_i_1__11_n_0 ));
LUT2 #(
.INIT(4'h1))
\xsdb_reg[15]_i_2__4
(.I0(s_daddr_o[6]),
.I1(s_daddr_o[5]),
.O(\xsdb_reg_reg[0]_0 ));
LUT4 #(
.INIT(16'hFBFF))
\xsdb_reg[15]_i_3__2
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[3]),
.O(\xsdb_reg_reg[0]_1 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[0]),
.Q(\slaveRegDo_mux_0_reg[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[1]),
.Q(\slaveRegDo_mux_0_reg[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[2]),
.Q(\slaveRegDo_mux_0_reg[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_0_reg[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_0_reg[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[9] ),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_175
(\xsdb_reg_reg[0]_0 ,
\xsdb_reg_reg[0]_1 ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_den_o,
s_dwe_o,
s_daddr_o,
s_di_o,
s_dclk_o); |
output \xsdb_reg_reg[0]_0 ;
output \xsdb_reg_reg[0]_1 ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input s_den_o;
input s_dwe_o;
input [6:0]s_daddr_o;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__11_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[0]_1 ;
LUT6 #(
.INIT(64'h0000000080000000))
\xsdb_reg[15]_i_1__11
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.I1(s_den_o),
.I2(s_dwe_o),
.I3(\xsdb_reg_reg[0]_0 ),
.I4(s_daddr_o[4]),
.I5(\xsdb_reg_reg[0]_1 ),
.O(\xsdb_reg[15]_i_1__11_n_0 ));
LUT2 #(
.INIT(4'h1))
\xsdb_reg[15]_i_2__4
(.I0(s_daddr_o[6]),
.I1(s_daddr_o[5]),
.O(\xsdb_reg_reg[0]_0 ));
LUT4 #(
.INIT(16'hFBFF))
\xsdb_reg[15]_i_3__2
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[2]),
.I3(s_daddr_o[3]),
.O(\xsdb_reg_reg[0]_1 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[0]),
.Q(\slaveRegDo_mux_0_reg[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[1]),
.Q(\slaveRegDo_mux_0_reg[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[2]),
.Q(\slaveRegDo_mux_0_reg[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_0_reg[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_0_reg[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__11_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[9] ),
.R(1'b0));
endmodule | 8 |
2,419 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_176
(\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[15] ,
s_daddr_o,
\xsdb_reg_reg[14]_0 ,
\xsdb_reg_reg[14]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\xsdb_reg_reg[13]_0 ,
\xsdb_reg_reg[13]_1 ,
\xsdb_reg_reg[10]_0 ,
\xsdb_reg_reg[10]_1 ,
\xsdb_reg_reg[9]_0 ,
\xsdb_reg_reg[9]_1 ,
\xsdb_reg_reg[8]_0 ,
\xsdb_reg_reg[8]_1 ,
\xsdb_reg_reg[7]_0 ,
\xsdb_reg_reg[7]_1 ,
\xsdb_reg_reg[6]_0 ,
\xsdb_reg_reg[6]_1 ,
\xsdb_reg_reg[2]_0 ,
capture_qual_ctrl_1,
\xsdb_reg_reg[1]_0 ,
\xsdb_reg_reg[12]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
\xsdb_reg_reg[11]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
\xsdb_reg_reg[5]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
\xsdb_reg_reg[5]_1 ,
\xsdb_reg_reg[5]_2 ,
\xsdb_reg_reg[11]_1 ,
\xsdb_reg_reg[11]_2 ,
\xsdb_reg_reg[12]_1 ,
\xsdb_reg_reg[12]_2 ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 );
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[5] ;
output [3:0]\slaveRegDo_mux_0_reg[15] ;
input [5:0]s_daddr_o;
input \xsdb_reg_reg[14]_0 ;
input \xsdb_reg_reg[14]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \xsdb_reg_reg[13]_0 ;
input \xsdb_reg_reg[13]_1 ;
input \xsdb_reg_reg[10]_0 ;
input \xsdb_reg_reg[10]_1 ;
input \xsdb_reg_reg[9]_0 ;
input \xsdb_reg_reg[9]_1 ;
input \xsdb_reg_reg[8]_0 ;
input \xsdb_reg_reg[8]_1 ;
input \xsdb_reg_reg[7]_0 ;
input \xsdb_reg_reg[7]_1 ;
input \xsdb_reg_reg[6]_0 ;
input \xsdb_reg_reg[6]_1 ;
input \xsdb_reg_reg[2]_0 ;
input [1:0]capture_qual_ctrl_1;
input \xsdb_reg_reg[1]_0 ;
input \xsdb_reg_reg[12]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [2:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
input \xsdb_reg_reg[11]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
input \xsdb_reg_reg[5]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
input \xsdb_reg_reg[5]_1 ;
input \xsdb_reg_reg[5]_2 ;
input \xsdb_reg_reg[11]_1 ;
input \xsdb_reg_reg[11]_2 ;
input \xsdb_reg_reg[12]_1 ;
input \xsdb_reg_reg[12]_2 ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire [2:0]Q;
wire [1:0]capture_qual_ctrl_1;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [14:1]slaveRegDo_18;
wire \slaveRegDo_mux_0[11]_i_5_n_0 ;
wire \slaveRegDo_mux_0[12]_i_5_n_0 ;
wire \slaveRegDo_mux_0[5]_i_5_n_0 ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire [3:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__0_n_0 ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[10]_1 ;
wire \xsdb_reg_reg[11]_0 ;
wire \xsdb_reg_reg[11]_1 ;
wire \xsdb_reg_reg[11]_2 ;
wire \xsdb_reg_reg[12]_0 ;
wire \xsdb_reg_reg[12]_1 ;
wire \xsdb_reg_reg[12]_2 ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[13]_1 ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[14]_1 ;
wire \xsdb_reg_reg[1]_0 ;
wire \xsdb_reg_reg[2]_0 ;
wire \xsdb_reg_reg[5]_0 ;
wire \xsdb_reg_reg[5]_1 ;
wire \xsdb_reg_reg[5]_2 ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[6]_1 ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[7]_1 ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[8]_1 ;
wire \xsdb_reg_reg[9]_0 ;
wire \xsdb_reg_reg[9]_1 ;
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[10]_i_6
(.I0(slaveRegDo_18[10]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[10]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[10]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[10] ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[11]_i_3
(.I0(\slaveRegDo_mux_0[11]_i_5_n_0 ),
.I1(\xsdb_reg_reg[11]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(Q[1]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
.O(\slaveRegDo_mux_0_reg[11] ));
LUT6 #(
.INIT(64'hF5F557F7FFFF57F7))
\slaveRegDo_mux_0[11]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.I1(slaveRegDo_18[11]),
.I2(s_daddr_o[0]),
.I3(\xsdb_reg_reg[11]_1 ),
.I4(s_daddr_o[1]),
.I5(\xsdb_reg_reg[11]_2 ),
.O(\slaveRegDo_mux_0[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[12]_i_3
(.I0(\slaveRegDo_mux_0[12]_i_5_n_0 ),
.I1(\xsdb_reg_reg[12]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(Q[2]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
.O(\slaveRegDo_mux_0_reg[12] ));
LUT6 #(
.INIT(64'hF5F557F7FFFF57F7))
\slaveRegDo_mux_0[12]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.I1(slaveRegDo_18[12]),
.I2(s_daddr_o[0]),
.I3(\xsdb_reg_reg[12]_1 ),
.I4(s_daddr_o[1]),
.I5(\xsdb_reg_reg[12]_2 ),
.O(\slaveRegDo_mux_0[12]_i_5_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[13]_i_6
(.I0(slaveRegDo_18[13]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[13]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[13]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[13] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[14]_i_6
(.I0(slaveRegDo_18[14]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[14]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[14]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[14] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[1]_i_5
(.I0(slaveRegDo_18[1]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[1]_0 ),
.I3(s_daddr_o[1]),
.I4(capture_qual_ctrl_1[0]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[1] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[2]_i_5
(.I0(slaveRegDo_18[2]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[2]_0 ),
.I3(s_daddr_o[1]),
.I4(capture_qual_ctrl_1[1]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[2] ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[5]_i_3
(.I0(\slaveRegDo_mux_0[5]_i_5_n_0 ),
.I1(\xsdb_reg_reg[5]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(Q[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.O(\slaveRegDo_mux_0_reg[5] ));
LUT6 #(
.INIT(64'hF5F557F7FFFF57F7))
\slaveRegDo_mux_0[5]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.I1(slaveRegDo_18[5]),
.I2(s_daddr_o[0]),
.I3(\xsdb_reg_reg[5]_1 ),
.I4(s_daddr_o[1]),
.I5(\xsdb_reg_reg[5]_2 ),
.O(\slaveRegDo_mux_0[5]_i_5_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[6]_i_6
(.I0(slaveRegDo_18[6]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[6]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[6]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[6] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[7]_i_6
(.I0(slaveRegDo_18[7]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[7]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[7]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[7] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[8]_i_6
(.I0(slaveRegDo_18[8]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[8]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[8]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[8] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[9]_i_6
(.I0(slaveRegDo_18[9]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[9]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[9]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[9] ));
LUT6 #(
.INIT(64'h0000000000008000))
\xsdb_reg[15]_i_1__0
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.I2(s_daddr_o[3]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[5]),
.I5(s_daddr_o[4]),
.O(\xsdb_reg[15]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[0]),
.Q(\slaveRegDo_mux_0_reg[15] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[10]),
.Q(slaveRegDo_18[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[11]),
.Q(slaveRegDo_18[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[12]),
.Q(slaveRegDo_18[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[13]),
.Q(slaveRegDo_18[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[14]),
.Q(slaveRegDo_18[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_18[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[2]),
.Q(slaveRegDo_18[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_0_reg[15] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_0_reg[15] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[5]),
.Q(slaveRegDo_18[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[6]),
.Q(slaveRegDo_18[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[7]),
.Q(slaveRegDo_18[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[8]),
.Q(slaveRegDo_18[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[9]),
.Q(slaveRegDo_18[9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_176
(\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[15] ,
s_daddr_o,
\xsdb_reg_reg[14]_0 ,
\xsdb_reg_reg[14]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\xsdb_reg_reg[13]_0 ,
\xsdb_reg_reg[13]_1 ,
\xsdb_reg_reg[10]_0 ,
\xsdb_reg_reg[10]_1 ,
\xsdb_reg_reg[9]_0 ,
\xsdb_reg_reg[9]_1 ,
\xsdb_reg_reg[8]_0 ,
\xsdb_reg_reg[8]_1 ,
\xsdb_reg_reg[7]_0 ,
\xsdb_reg_reg[7]_1 ,
\xsdb_reg_reg[6]_0 ,
\xsdb_reg_reg[6]_1 ,
\xsdb_reg_reg[2]_0 ,
capture_qual_ctrl_1,
\xsdb_reg_reg[1]_0 ,
\xsdb_reg_reg[12]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
\xsdb_reg_reg[11]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
\xsdb_reg_reg[5]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
\xsdb_reg_reg[5]_1 ,
\xsdb_reg_reg[5]_2 ,
\xsdb_reg_reg[11]_1 ,
\xsdb_reg_reg[11]_2 ,
\xsdb_reg_reg[12]_1 ,
\xsdb_reg_reg[12]_2 ,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ); |
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[5] ;
output [3:0]\slaveRegDo_mux_0_reg[15] ;
input [5:0]s_daddr_o;
input \xsdb_reg_reg[14]_0 ;
input \xsdb_reg_reg[14]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \xsdb_reg_reg[13]_0 ;
input \xsdb_reg_reg[13]_1 ;
input \xsdb_reg_reg[10]_0 ;
input \xsdb_reg_reg[10]_1 ;
input \xsdb_reg_reg[9]_0 ;
input \xsdb_reg_reg[9]_1 ;
input \xsdb_reg_reg[8]_0 ;
input \xsdb_reg_reg[8]_1 ;
input \xsdb_reg_reg[7]_0 ;
input \xsdb_reg_reg[7]_1 ;
input \xsdb_reg_reg[6]_0 ;
input \xsdb_reg_reg[6]_1 ;
input \xsdb_reg_reg[2]_0 ;
input [1:0]capture_qual_ctrl_1;
input \xsdb_reg_reg[1]_0 ;
input \xsdb_reg_reg[12]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [2:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
input \xsdb_reg_reg[11]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
input \xsdb_reg_reg[5]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
input \xsdb_reg_reg[5]_1 ;
input \xsdb_reg_reg[5]_2 ;
input \xsdb_reg_reg[11]_1 ;
input \xsdb_reg_reg[11]_2 ;
input \xsdb_reg_reg[12]_1 ;
input \xsdb_reg_reg[12]_2 ;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire [2:0]Q;
wire [1:0]capture_qual_ctrl_1;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [14:1]slaveRegDo_18;
wire \slaveRegDo_mux_0[11]_i_5_n_0 ;
wire \slaveRegDo_mux_0[12]_i_5_n_0 ;
wire \slaveRegDo_mux_0[5]_i_5_n_0 ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire [3:0]\slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__0_n_0 ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[10]_1 ;
wire \xsdb_reg_reg[11]_0 ;
wire \xsdb_reg_reg[11]_1 ;
wire \xsdb_reg_reg[11]_2 ;
wire \xsdb_reg_reg[12]_0 ;
wire \xsdb_reg_reg[12]_1 ;
wire \xsdb_reg_reg[12]_2 ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[13]_1 ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[14]_1 ;
wire \xsdb_reg_reg[1]_0 ;
wire \xsdb_reg_reg[2]_0 ;
wire \xsdb_reg_reg[5]_0 ;
wire \xsdb_reg_reg[5]_1 ;
wire \xsdb_reg_reg[5]_2 ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[6]_1 ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[7]_1 ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[8]_1 ;
wire \xsdb_reg_reg[9]_0 ;
wire \xsdb_reg_reg[9]_1 ;
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[10]_i_6
(.I0(slaveRegDo_18[10]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[10]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[10]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[10] ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[11]_i_3
(.I0(\slaveRegDo_mux_0[11]_i_5_n_0 ),
.I1(\xsdb_reg_reg[11]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(Q[1]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
.O(\slaveRegDo_mux_0_reg[11] ));
LUT6 #(
.INIT(64'hF5F557F7FFFF57F7))
\slaveRegDo_mux_0[11]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.I1(slaveRegDo_18[11]),
.I2(s_daddr_o[0]),
.I3(\xsdb_reg_reg[11]_1 ),
.I4(s_daddr_o[1]),
.I5(\xsdb_reg_reg[11]_2 ),
.O(\slaveRegDo_mux_0[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[12]_i_3
(.I0(\slaveRegDo_mux_0[12]_i_5_n_0 ),
.I1(\xsdb_reg_reg[12]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(Q[2]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
.O(\slaveRegDo_mux_0_reg[12] ));
LUT6 #(
.INIT(64'hF5F557F7FFFF57F7))
\slaveRegDo_mux_0[12]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.I1(slaveRegDo_18[12]),
.I2(s_daddr_o[0]),
.I3(\xsdb_reg_reg[12]_1 ),
.I4(s_daddr_o[1]),
.I5(\xsdb_reg_reg[12]_2 ),
.O(\slaveRegDo_mux_0[12]_i_5_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[13]_i_6
(.I0(slaveRegDo_18[13]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[13]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[13]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[13] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[14]_i_6
(.I0(slaveRegDo_18[14]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[14]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[14]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[14] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[1]_i_5
(.I0(slaveRegDo_18[1]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[1]_0 ),
.I3(s_daddr_o[1]),
.I4(capture_qual_ctrl_1[0]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[1] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[2]_i_5
(.I0(slaveRegDo_18[2]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[2]_0 ),
.I3(s_daddr_o[1]),
.I4(capture_qual_ctrl_1[1]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[2] ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[5]_i_3
(.I0(\slaveRegDo_mux_0[5]_i_5_n_0 ),
.I1(\xsdb_reg_reg[5]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(Q[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.O(\slaveRegDo_mux_0_reg[5] ));
LUT6 #(
.INIT(64'hF5F557F7FFFF57F7))
\slaveRegDo_mux_0[5]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.I1(slaveRegDo_18[5]),
.I2(s_daddr_o[0]),
.I3(\xsdb_reg_reg[5]_1 ),
.I4(s_daddr_o[1]),
.I5(\xsdb_reg_reg[5]_2 ),
.O(\slaveRegDo_mux_0[5]_i_5_n_0 ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[6]_i_6
(.I0(slaveRegDo_18[6]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[6]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[6]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[6] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[7]_i_6
(.I0(slaveRegDo_18[7]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[7]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[7]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[7] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[8]_i_6
(.I0(slaveRegDo_18[8]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[8]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[8]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[8] ));
LUT6 #(
.INIT(64'h33E200E200000000))
\slaveRegDo_mux_0[9]_i_6
(.I0(slaveRegDo_18[9]),
.I1(s_daddr_o[0]),
.I2(\xsdb_reg_reg[9]_0 ),
.I3(s_daddr_o[1]),
.I4(\xsdb_reg_reg[9]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0_reg[9] ));
LUT6 #(
.INIT(64'h0000000000008000))
\xsdb_reg[15]_i_1__0
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.I2(s_daddr_o[3]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[5]),
.I5(s_daddr_o[4]),
.O(\xsdb_reg[15]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[0]),
.Q(\slaveRegDo_mux_0_reg[15] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[10]),
.Q(slaveRegDo_18[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[11]),
.Q(slaveRegDo_18[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[12]),
.Q(slaveRegDo_18[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[13]),
.Q(slaveRegDo_18[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[14]),
.Q(slaveRegDo_18[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_18[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[2]),
.Q(slaveRegDo_18[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_0_reg[15] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_0_reg[15] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[5]),
.Q(slaveRegDo_18[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[6]),
.Q(slaveRegDo_18[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[7]),
.Q(slaveRegDo_18[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[8]),
.Q(slaveRegDo_18[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__0_n_0 ),
.D(s_di_o[9]),
.Q(slaveRegDo_18[9]),
.R(1'b0));
endmodule | 8 |
2,420 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_177
(D,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
s_dwe_o,
s_den_o,
\xsdb_reg_reg[0]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\xsdb_reg_reg[15]_0 ,
\xsdb_reg_reg[15]_1 ,
read_reset_addr,
\xsdb_reg_reg[4]_0 ,
\xsdb_reg_reg[3]_0 ,
SR,
s_di_o,
s_dclk_o);
output [0:0]D;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
input [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [6:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input s_dwe_o;
input s_den_o;
input \xsdb_reg_reg[0]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \xsdb_reg_reg[15]_0 ;
input \xsdb_reg_reg[15]_1 ;
input [2:0]read_reset_addr;
input \xsdb_reg_reg[4]_0 ;
input \xsdb_reg_reg[3]_0 ;
input [0:0]SR;
input [15:0]s_di_o;
input s_dclk_o;
wire [0:0]D;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [0:0]SR;
wire [2:0]read_reset_addr;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0[0]_i_2_n_0 ;
wire \slaveRegDo_mux_0[0]_i_4_n_0 ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__7_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg[15]_1 ;
wire \xsdb_reg_reg[3]_0 ;
wire \xsdb_reg_reg[4]_0 ;
wire \xsdb_reg_reg_n_0_[0] ;
wire \xsdb_reg_reg_n_0_[15] ;
wire \xsdb_reg_reg_n_0_[3] ;
wire \xsdb_reg_reg_n_0_[4] ;
LUT6 #(
.INIT(64'hAAAAAAAA0000303F))
\slaveRegDo_mux_0[0]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\slaveRegDo_mux_0[0]_i_2_n_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I4(s_daddr_o[6]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.O(D));
LUT6 #(
.INIT(64'hD3DFFFFFD3DF0000))
\slaveRegDo_mux_0[0]_i_2
(.I0(\slaveRegDo_mux_0[0]_i_4_n_0 ),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[2]),
.I3(\xsdb_reg_reg[0]_0 ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.O(\slaveRegDo_mux_0[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAFC0A0C0))
\slaveRegDo_mux_0[0]_i_4
(.I0(\xsdb_reg_reg_n_0_[0] ),
.I1(read_reset_addr[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(SR),
.O(\slaveRegDo_mux_0[0]_i_4_n_0 ));
LUT5 #(
.INIT(32'hAFC0A0C0))
\slaveRegDo_mux_0[15]_i_6
(.I0(\xsdb_reg_reg_n_0_[15] ),
.I1(\xsdb_reg_reg[15]_0 ),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_1 ),
.O(\slaveRegDo_mux_0_reg[15] ));
LUT5 #(
.INIT(32'hAFC0A0C0))
\slaveRegDo_mux_0[3]_i_5
(.I0(\xsdb_reg_reg_n_0_[3] ),
.I1(read_reset_addr[1]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[3]_0 ),
.O(\slaveRegDo_mux_0_reg[3] ));
LUT5 #(
.INIT(32'hAFC0A0C0))
\slaveRegDo_mux_0[4]_i_7
(.I0(\xsdb_reg_reg_n_0_[4] ),
.I1(read_reset_addr[2]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[4]_0 ),
.O(\slaveRegDo_mux_0_reg[4] ));
LUT6 #(
.INIT(64'h0008000000000000))
\xsdb_reg[15]_i_1__7
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.I1(s_daddr_o[4]),
.I2(s_daddr_o[5]),
.I3(s_daddr_o[6]),
.I4(s_dwe_o),
.I5(s_den_o),
.O(\xsdb_reg[15]_i_1__7_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[0]),
.Q(\xsdb_reg_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[15]),
.Q(\xsdb_reg_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[1]),
.Q(\slaveRegDo_mux_0_reg[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[2]),
.Q(\slaveRegDo_mux_0_reg[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[3]),
.Q(\xsdb_reg_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[4]),
.Q(\xsdb_reg_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[9] ),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_177
(D,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
s_dwe_o,
s_den_o,
\xsdb_reg_reg[0]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\xsdb_reg_reg[15]_0 ,
\xsdb_reg_reg[15]_1 ,
read_reset_addr,
\xsdb_reg_reg[4]_0 ,
\xsdb_reg_reg[3]_0 ,
SR,
s_di_o,
s_dclk_o); |
output [0:0]D;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[1] ;
input [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [6:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input s_dwe_o;
input s_den_o;
input \xsdb_reg_reg[0]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \xsdb_reg_reg[15]_0 ;
input \xsdb_reg_reg[15]_1 ;
input [2:0]read_reset_addr;
input \xsdb_reg_reg[4]_0 ;
input \xsdb_reg_reg[3]_0 ;
input [0:0]SR;
input [15:0]s_di_o;
input s_dclk_o;
wire [0:0]D;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire [0:0]\G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [0:0]SR;
wire [2:0]read_reset_addr;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0[0]_i_2_n_0 ;
wire \slaveRegDo_mux_0[0]_i_4_n_0 ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[1] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__7_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg[15]_1 ;
wire \xsdb_reg_reg[3]_0 ;
wire \xsdb_reg_reg[4]_0 ;
wire \xsdb_reg_reg_n_0_[0] ;
wire \xsdb_reg_reg_n_0_[15] ;
wire \xsdb_reg_reg_n_0_[3] ;
wire \xsdb_reg_reg_n_0_[4] ;
LUT6 #(
.INIT(64'hAAAAAAAA0000303F))
\slaveRegDo_mux_0[0]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\slaveRegDo_mux_0[0]_i_2_n_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I4(s_daddr_o[6]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.O(D));
LUT6 #(
.INIT(64'hD3DFFFFFD3DF0000))
\slaveRegDo_mux_0[0]_i_2
(.I0(\slaveRegDo_mux_0[0]_i_4_n_0 ),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[2]),
.I3(\xsdb_reg_reg[0]_0 ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.O(\slaveRegDo_mux_0[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'hAFC0A0C0))
\slaveRegDo_mux_0[0]_i_4
(.I0(\xsdb_reg_reg_n_0_[0] ),
.I1(read_reset_addr[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(SR),
.O(\slaveRegDo_mux_0[0]_i_4_n_0 ));
LUT5 #(
.INIT(32'hAFC0A0C0))
\slaveRegDo_mux_0[15]_i_6
(.I0(\xsdb_reg_reg_n_0_[15] ),
.I1(\xsdb_reg_reg[15]_0 ),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_1 ),
.O(\slaveRegDo_mux_0_reg[15] ));
LUT5 #(
.INIT(32'hAFC0A0C0))
\slaveRegDo_mux_0[3]_i_5
(.I0(\xsdb_reg_reg_n_0_[3] ),
.I1(read_reset_addr[1]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[3]_0 ),
.O(\slaveRegDo_mux_0_reg[3] ));
LUT5 #(
.INIT(32'hAFC0A0C0))
\slaveRegDo_mux_0[4]_i_7
(.I0(\xsdb_reg_reg_n_0_[4] ),
.I1(read_reset_addr[2]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[4]_0 ),
.O(\slaveRegDo_mux_0_reg[4] ));
LUT6 #(
.INIT(64'h0008000000000000))
\xsdb_reg[15]_i_1__7
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.I1(s_daddr_o[4]),
.I2(s_daddr_o[5]),
.I3(s_daddr_o[6]),
.I4(s_dwe_o),
.I5(s_den_o),
.O(\xsdb_reg[15]_i_1__7_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[0]),
.Q(\xsdb_reg_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[15]),
.Q(\xsdb_reg_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[1]),
.Q(\slaveRegDo_mux_0_reg[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[2]),
.Q(\slaveRegDo_mux_0_reg[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[3]),
.Q(\xsdb_reg_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[4]),
.Q(\xsdb_reg_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__7_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[9] ),
.R(1'b0));
endmodule | 8 |
2,421 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_178
(\xsdb_reg_reg[15]_0 ,
\slaveRegDo_mux_0_reg[15] ,
read_reset_addr,
s_daddr_o,
s_dwe_o,
s_den_o,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_di_o,
s_dclk_o);
output \xsdb_reg_reg[15]_0 ;
output \slaveRegDo_mux_0_reg[15] ;
output [14:0]read_reset_addr;
input [6:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire [14:0]read_reset_addr;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[15] ;
wire \xsdb_reg[15]_i_1__15_n_0 ;
wire \xsdb_reg_reg[15]_0 ;
LUT5 #(
.INIT(32'h00100000))
\xsdb_reg[15]_i_1__15
(.I0(\xsdb_reg_reg[15]_0 ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.O(\xsdb_reg[15]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'hFDFFFFFFFFFFFFFF))
\xsdb_reg[15]_i_2__2
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[6]),
.I3(s_dwe_o),
.I4(s_den_o),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.O(\xsdb_reg_reg[15]_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[0]),
.Q(read_reset_addr[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[10]),
.Q(read_reset_addr[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[11]),
.Q(read_reset_addr[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[12]),
.Q(read_reset_addr[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[13]),
.Q(read_reset_addr[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[14]),
.Q(read_reset_addr[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[1]),
.Q(read_reset_addr[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[2]),
.Q(read_reset_addr[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[3]),
.Q(read_reset_addr[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[4]),
.Q(read_reset_addr[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[5]),
.Q(read_reset_addr[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[6]),
.Q(read_reset_addr[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[7]),
.Q(read_reset_addr[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[8]),
.Q(read_reset_addr[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[9]),
.Q(read_reset_addr[9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_178
(\xsdb_reg_reg[15]_0 ,
\slaveRegDo_mux_0_reg[15] ,
read_reset_addr,
s_daddr_o,
s_dwe_o,
s_den_o,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_di_o,
s_dclk_o); |
output \xsdb_reg_reg[15]_0 ;
output \slaveRegDo_mux_0_reg[15] ;
output [14:0]read_reset_addr;
input [6:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input [15:0]s_di_o;
input s_dclk_o;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire [14:0]read_reset_addr;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0_reg[15] ;
wire \xsdb_reg[15]_i_1__15_n_0 ;
wire \xsdb_reg_reg[15]_0 ;
LUT5 #(
.INIT(32'h00100000))
\xsdb_reg[15]_i_1__15
(.I0(\xsdb_reg_reg[15]_0 ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[3]),
.I4(s_daddr_o[2]),
.O(\xsdb_reg[15]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'hFDFFFFFFFFFFFFFF))
\xsdb_reg[15]_i_2__2
(.I0(s_daddr_o[4]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[6]),
.I3(s_dwe_o),
.I4(s_den_o),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.O(\xsdb_reg_reg[15]_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[0]),
.Q(read_reset_addr[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[10]),
.Q(read_reset_addr[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[11]),
.Q(read_reset_addr[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[12]),
.Q(read_reset_addr[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[13]),
.Q(read_reset_addr[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[14]),
.Q(read_reset_addr[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[1]),
.Q(read_reset_addr[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[2]),
.Q(read_reset_addr[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[3]),
.Q(read_reset_addr[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[4]),
.Q(read_reset_addr[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[5]),
.Q(read_reset_addr[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[6]),
.Q(read_reset_addr[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[7]),
.Q(read_reset_addr[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[8]),
.Q(read_reset_addr[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__15_n_0 ),
.D(s_di_o[9]),
.Q(read_reset_addr[9]),
.R(1'b0));
endmodule | 8 |
2,422 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_179
(\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[5] ,
D,
\xsdb_reg_reg[0]_0 ,
\xsdb_reg_reg[0]_1 ,
use_probe_debug_circuit_1,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
SR,
s_daddr_o,
read_reset_addr,
\xsdb_reg_reg[12]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\xsdb_reg_reg[11]_0 ,
\xsdb_reg_reg[5]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ,
s_den_o,
s_dwe_o,
\xsdb_reg_reg[1]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
\xsdb_reg_reg[1]_1 ,
\xsdb_reg_reg[1]_2 ,
\xsdb_reg_reg[2]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
\xsdb_reg_reg[2]_1 ,
\xsdb_reg_reg[6]_0 ,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
\xsdb_reg_reg[6]_1 ,
\xsdb_reg_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ,
\xsdb_reg_reg[7]_1 ,
\xsdb_reg_reg[8]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ,
\xsdb_reg_reg[8]_1 ,
\xsdb_reg_reg[9]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ,
\xsdb_reg_reg[9]_1 ,
\xsdb_reg_reg[10]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ,
\xsdb_reg_reg[10]_1 ,
\xsdb_reg_reg[13]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ,
\xsdb_reg_reg[13]_1 ,
\xsdb_reg_reg[14]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ,
\xsdb_reg_reg[14]_1 ,
s_di_o,
s_dclk_o);
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[5] ;
output [1:0]D;
output \xsdb_reg_reg[0]_0 ;
output \xsdb_reg_reg[0]_1 ;
output use_probe_debug_circuit_1;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output [0:0]SR;
input [12:0]s_daddr_o;
input [11:0]read_reset_addr;
input \xsdb_reg_reg[12]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \xsdb_reg_reg[11]_0 ;
input \xsdb_reg_reg[5]_0 ;
input [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
input s_den_o;
input s_dwe_o;
input \xsdb_reg_reg[1]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
input \xsdb_reg_reg[1]_1 ;
input \xsdb_reg_reg[1]_2 ;
input \xsdb_reg_reg[2]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
input \xsdb_reg_reg[2]_1 ;
input \xsdb_reg_reg[6]_0 ;
input [6:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
input \xsdb_reg_reg[6]_1 ;
input \xsdb_reg_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
input \xsdb_reg_reg[7]_1 ;
input \xsdb_reg_reg[8]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
input \xsdb_reg_reg[8]_1 ;
input \xsdb_reg_reg[9]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
input \xsdb_reg_reg[9]_1 ;
input \xsdb_reg_reg[10]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
input \xsdb_reg_reg[10]_1 ;
input \xsdb_reg_reg[13]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
input \xsdb_reg_reg[13]_1 ;
input \xsdb_reg_reg[14]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
input \xsdb_reg_reg[14]_1 ;
input [15:0]s_di_o;
input s_dclk_o;
wire [1:0]D;
wire [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [6:0]Q;
wire [0:0]SR;
wire [11:0]read_reset_addr;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0[10]_i_5_n_0 ;
wire \slaveRegDo_mux_0[13]_i_5_n_0 ;
wire \slaveRegDo_mux_0[14]_i_5_n_0 ;
wire \slaveRegDo_mux_0[1]_i_2_n_0 ;
wire \slaveRegDo_mux_0[1]_i_4_n_0 ;
wire \slaveRegDo_mux_0[2]_i_2_n_0 ;
wire \slaveRegDo_mux_0[2]_i_4_n_0 ;
wire \slaveRegDo_mux_0[6]_i_5_n_0 ;
wire \slaveRegDo_mux_0[7]_i_5_n_0 ;
wire \slaveRegDo_mux_0[8]_i_5_n_0 ;
wire \slaveRegDo_mux_0[9]_i_5_n_0 ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire use_probe_debug_circuit_1;
wire \xsdb_reg[15]_i_1__12_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[0]_1 ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[10]_1 ;
wire \xsdb_reg_reg[11]_0 ;
wire \xsdb_reg_reg[12]_0 ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[13]_1 ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[14]_1 ;
wire \xsdb_reg_reg[1]_0 ;
wire \xsdb_reg_reg[1]_1 ;
wire \xsdb_reg_reg[1]_2 ;
wire \xsdb_reg_reg[2]_0 ;
wire \xsdb_reg_reg[2]_1 ;
wire \xsdb_reg_reg[5]_0 ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[6]_1 ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[7]_1 ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[8]_1 ;
wire \xsdb_reg_reg[9]_0 ;
wire \xsdb_reg_reg[9]_1 ;
wire \xsdb_reg_reg_n_0_[10] ;
wire \xsdb_reg_reg_n_0_[11] ;
wire \xsdb_reg_reg_n_0_[12] ;
wire \xsdb_reg_reg_n_0_[13] ;
wire \xsdb_reg_reg_n_0_[14] ;
wire \xsdb_reg_reg_n_0_[1] ;
wire \xsdb_reg_reg_n_0_[5] ;
wire \xsdb_reg_reg_n_0_[6] ;
wire \xsdb_reg_reg_n_0_[7] ;
wire \xsdb_reg_reg_n_0_[8] ;
wire \xsdb_reg_reg_n_0_[9] ;
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[10]_i_3
(.I0(\slaveRegDo_mux_0[10]_i_5_n_0 ),
.I1(\xsdb_reg_reg[10]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[4]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ),
.O(\slaveRegDo_mux_0_reg[10] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[10]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[10] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[7]),
.I5(\xsdb_reg_reg[10]_1 ),
.O(\slaveRegDo_mux_0[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF8C8380800000000))
\slaveRegDo_mux_0[11]_i_6
(.I0(\xsdb_reg_reg_n_0_[11] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(read_reset_addr[8]),
.I4(\xsdb_reg_reg[11]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.O(\slaveRegDo_mux_0_reg[11] ));
LUT6 #(
.INIT(64'hF8C8380800000000))
\slaveRegDo_mux_0[12]_i_6
(.I0(\xsdb_reg_reg_n_0_[12] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(read_reset_addr[9]),
.I4(\xsdb_reg_reg[12]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.O(\slaveRegDo_mux_0_reg[12] ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[13]_i_3
(.I0(\slaveRegDo_mux_0[13]_i_5_n_0 ),
.I1(\xsdb_reg_reg[13]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[5]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ),
.O(\slaveRegDo_mux_0_reg[13] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[13]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[13] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[10]),
.I5(\xsdb_reg_reg[13]_1 ),
.O(\slaveRegDo_mux_0[13]_i_5_n_0 ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[14]_i_3
(.I0(\slaveRegDo_mux_0[14]_i_5_n_0 ),
.I1(\xsdb_reg_reg[14]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[6]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ),
.O(\slaveRegDo_mux_0_reg[14] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[14]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[14] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[11]),
.I5(\xsdb_reg_reg[14]_1 ),
.O(\slaveRegDo_mux_0[14]_i_5_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA0000303F))
\slaveRegDo_mux_0[1]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1] [0]),
.I1(\slaveRegDo_mux_0[1]_i_2_n_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ),
.I4(s_daddr_o[6]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'h2F202F2F2F202020))
\slaveRegDo_mux_0[1]_i_2
(.I0(\slaveRegDo_mux_0[1]_i_4_n_0 ),
.I1(\xsdb_reg_reg[1]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ),
.I4(s_daddr_o[3]),
.I5(\xsdb_reg_reg[1]_1 ),
.O(\slaveRegDo_mux_0[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[1]_i_4
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[1] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[0]),
.I5(\xsdb_reg_reg[1]_2 ),
.O(\slaveRegDo_mux_0[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA0000303F))
\slaveRegDo_mux_0[2]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1] [1]),
.I1(\slaveRegDo_mux_0[2]_i_2_n_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I4(s_daddr_o[6]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'h2020202020202F20))
\slaveRegDo_mux_0[2]_i_2
(.I0(\slaveRegDo_mux_0[2]_i_4_n_0 ),
.I1(\xsdb_reg_reg[2]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
.O(\slaveRegDo_mux_0[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[2]_i_4
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(use_probe_debug_circuit_1),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[1]),
.I5(\xsdb_reg_reg[2]_1 ),
.O(\slaveRegDo_mux_0[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF8C8380800000000))
\slaveRegDo_mux_0[5]_i_6
(.I0(\xsdb_reg_reg_n_0_[5] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(read_reset_addr[2]),
.I4(\xsdb_reg_reg[5]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.O(\slaveRegDo_mux_0_reg[5] ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[6]_i_3
(.I0(\slaveRegDo_mux_0[6]_i_5_n_0 ),
.I1(\xsdb_reg_reg[6]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
.O(\slaveRegDo_mux_0_reg[6] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[6]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[6] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[3]),
.I5(\xsdb_reg_reg[6]_1 ),
.O(\slaveRegDo_mux_0[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[7]_i_3
(.I0(\slaveRegDo_mux_0[7]_i_5_n_0 ),
.I1(\xsdb_reg_reg[7]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[1]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ),
.O(\slaveRegDo_mux_0_reg[7] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[7]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[7] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[4]),
.I5(\xsdb_reg_reg[7]_1 ),
.O(\slaveRegDo_mux_0[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[8]_i_3
(.I0(\slaveRegDo_mux_0[8]_i_5_n_0 ),
.I1(\xsdb_reg_reg[8]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[2]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ),
.O(\slaveRegDo_mux_0_reg[8] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[8]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[8] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[5]),
.I5(\xsdb_reg_reg[8]_1 ),
.O(\slaveRegDo_mux_0[8]_i_5_n_0 ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[9]_i_3
(.I0(\slaveRegDo_mux_0[9]_i_5_n_0 ),
.I1(\xsdb_reg_reg[9]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[3]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ),
.O(\slaveRegDo_mux_0_reg[9] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[9]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[9] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[6]),
.I5(\xsdb_reg_reg[9]_1 ),
.O(\slaveRegDo_mux_0[9]_i_5_n_0 ));
LUT5 #(
.INIT(32'h00000080))
\xsdb_reg[15]_i_1__12
(.I0(\xsdb_reg_reg[0]_0 ),
.I1(\xsdb_reg_reg[0]_1 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[6]),
.O(\xsdb_reg[15]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\xsdb_reg[15]_i_2__3
(.I0(s_daddr_o[9]),
.I1(s_daddr_o[8]),
.I2(s_daddr_o[7]),
.I3(s_daddr_o[10]),
.I4(s_daddr_o[11]),
.I5(s_daddr_o[12]),
.O(\xsdb_reg_reg[0]_0 ));
LUT6 #(
.INIT(64'h1000000000000000))
\xsdb_reg[15]_i_3__1
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[3]),
.I2(s_den_o),
.I3(s_daddr_o[2]),
.I4(s_dwe_o),
.I5(s_daddr_o[0]),
.O(\xsdb_reg_reg[0]_1 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[0]),
.Q(SR),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[10]),
.Q(\xsdb_reg_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[11]),
.Q(\xsdb_reg_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[12]),
.Q(\xsdb_reg_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[13]),
.Q(\xsdb_reg_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[14]),
.Q(\xsdb_reg_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[1]),
.Q(\xsdb_reg_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[2]),
.Q(use_probe_debug_circuit_1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_0_reg[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_0_reg[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[5]),
.Q(\xsdb_reg_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[6]),
.Q(\xsdb_reg_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[7]),
.Q(\xsdb_reg_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[8]),
.Q(\xsdb_reg_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[9]),
.Q(\xsdb_reg_reg_n_0_[9] ),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_179
(\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[5] ,
D,
\xsdb_reg_reg[0]_0 ,
\xsdb_reg_reg[0]_1 ,
use_probe_debug_circuit_1,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[15] ,
\slaveRegDo_mux_0_reg[4] ,
\slaveRegDo_mux_0_reg[3] ,
SR,
s_daddr_o,
read_reset_addr,
\xsdb_reg_reg[12]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\xsdb_reg_reg[11]_0 ,
\xsdb_reg_reg[5]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ,
s_den_o,
s_dwe_o,
\xsdb_reg_reg[1]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ,
\xsdb_reg_reg[1]_1 ,
\xsdb_reg_reg[1]_2 ,
\xsdb_reg_reg[2]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ,
\xsdb_reg_reg[2]_1 ,
\xsdb_reg_reg[6]_0 ,
Q,
\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ,
\xsdb_reg_reg[6]_1 ,
\xsdb_reg_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ,
\xsdb_reg_reg[7]_1 ,
\xsdb_reg_reg[8]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ,
\xsdb_reg_reg[8]_1 ,
\xsdb_reg_reg[9]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ,
\xsdb_reg_reg[9]_1 ,
\xsdb_reg_reg[10]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ,
\xsdb_reg_reg[10]_1 ,
\xsdb_reg_reg[13]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ,
\xsdb_reg_reg[13]_1 ,
\xsdb_reg_reg[14]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ,
\xsdb_reg_reg[14]_1 ,
s_di_o,
s_dclk_o); |
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[5] ;
output [1:0]D;
output \xsdb_reg_reg[0]_0 ;
output \xsdb_reg_reg[0]_1 ;
output use_probe_debug_circuit_1;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[15] ;
output \slaveRegDo_mux_0_reg[4] ;
output \slaveRegDo_mux_0_reg[3] ;
output [0:0]SR;
input [12:0]s_daddr_o;
input [11:0]read_reset_addr;
input \xsdb_reg_reg[12]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \xsdb_reg_reg[11]_0 ;
input \xsdb_reg_reg[5]_0 ;
input [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
input s_den_o;
input s_dwe_o;
input \xsdb_reg_reg[1]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
input \xsdb_reg_reg[1]_1 ;
input \xsdb_reg_reg[1]_2 ;
input \xsdb_reg_reg[2]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
input \xsdb_reg_reg[2]_1 ;
input \xsdb_reg_reg[6]_0 ;
input [6:0]Q;
input \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
input \xsdb_reg_reg[6]_1 ;
input \xsdb_reg_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
input \xsdb_reg_reg[7]_1 ;
input \xsdb_reg_reg[8]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
input \xsdb_reg_reg[8]_1 ;
input \xsdb_reg_reg[9]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
input \xsdb_reg_reg[9]_1 ;
input \xsdb_reg_reg[10]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
input \xsdb_reg_reg[10]_1 ;
input \xsdb_reg_reg[13]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
input \xsdb_reg_reg[13]_1 ;
input \xsdb_reg_reg[14]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
input \xsdb_reg_reg[14]_1 ;
input [15:0]s_di_o;
input s_dclk_o;
wire [1:0]D;
wire [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [6:0]Q;
wire [0:0]SR;
wire [11:0]read_reset_addr;
wire [12:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_0[10]_i_5_n_0 ;
wire \slaveRegDo_mux_0[13]_i_5_n_0 ;
wire \slaveRegDo_mux_0[14]_i_5_n_0 ;
wire \slaveRegDo_mux_0[1]_i_2_n_0 ;
wire \slaveRegDo_mux_0[1]_i_4_n_0 ;
wire \slaveRegDo_mux_0[2]_i_2_n_0 ;
wire \slaveRegDo_mux_0[2]_i_4_n_0 ;
wire \slaveRegDo_mux_0[6]_i_5_n_0 ;
wire \slaveRegDo_mux_0[7]_i_5_n_0 ;
wire \slaveRegDo_mux_0[8]_i_5_n_0 ;
wire \slaveRegDo_mux_0[9]_i_5_n_0 ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire use_probe_debug_circuit_1;
wire \xsdb_reg[15]_i_1__12_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[0]_1 ;
wire \xsdb_reg_reg[10]_0 ;
wire \xsdb_reg_reg[10]_1 ;
wire \xsdb_reg_reg[11]_0 ;
wire \xsdb_reg_reg[12]_0 ;
wire \xsdb_reg_reg[13]_0 ;
wire \xsdb_reg_reg[13]_1 ;
wire \xsdb_reg_reg[14]_0 ;
wire \xsdb_reg_reg[14]_1 ;
wire \xsdb_reg_reg[1]_0 ;
wire \xsdb_reg_reg[1]_1 ;
wire \xsdb_reg_reg[1]_2 ;
wire \xsdb_reg_reg[2]_0 ;
wire \xsdb_reg_reg[2]_1 ;
wire \xsdb_reg_reg[5]_0 ;
wire \xsdb_reg_reg[6]_0 ;
wire \xsdb_reg_reg[6]_1 ;
wire \xsdb_reg_reg[7]_0 ;
wire \xsdb_reg_reg[7]_1 ;
wire \xsdb_reg_reg[8]_0 ;
wire \xsdb_reg_reg[8]_1 ;
wire \xsdb_reg_reg[9]_0 ;
wire \xsdb_reg_reg[9]_1 ;
wire \xsdb_reg_reg_n_0_[10] ;
wire \xsdb_reg_reg_n_0_[11] ;
wire \xsdb_reg_reg_n_0_[12] ;
wire \xsdb_reg_reg_n_0_[13] ;
wire \xsdb_reg_reg_n_0_[14] ;
wire \xsdb_reg_reg_n_0_[1] ;
wire \xsdb_reg_reg_n_0_[5] ;
wire \xsdb_reg_reg_n_0_[6] ;
wire \xsdb_reg_reg_n_0_[7] ;
wire \xsdb_reg_reg_n_0_[8] ;
wire \xsdb_reg_reg_n_0_[9] ;
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[10]_i_3
(.I0(\slaveRegDo_mux_0[10]_i_5_n_0 ),
.I1(\xsdb_reg_reg[10]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[4]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_5 ),
.O(\slaveRegDo_mux_0_reg[10] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[10]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[10] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[7]),
.I5(\xsdb_reg_reg[10]_1 ),
.O(\slaveRegDo_mux_0[10]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF8C8380800000000))
\slaveRegDo_mux_0[11]_i_6
(.I0(\xsdb_reg_reg_n_0_[11] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(read_reset_addr[8]),
.I4(\xsdb_reg_reg[11]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.O(\slaveRegDo_mux_0_reg[11] ));
LUT6 #(
.INIT(64'hF8C8380800000000))
\slaveRegDo_mux_0[12]_i_6
(.I0(\xsdb_reg_reg_n_0_[12] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(read_reset_addr[9]),
.I4(\xsdb_reg_reg[12]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.O(\slaveRegDo_mux_0_reg[12] ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[13]_i_3
(.I0(\slaveRegDo_mux_0[13]_i_5_n_0 ),
.I1(\xsdb_reg_reg[13]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[5]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_6 ),
.O(\slaveRegDo_mux_0_reg[13] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[13]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[13] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[10]),
.I5(\xsdb_reg_reg[13]_1 ),
.O(\slaveRegDo_mux_0[13]_i_5_n_0 ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[14]_i_3
(.I0(\slaveRegDo_mux_0[14]_i_5_n_0 ),
.I1(\xsdb_reg_reg[14]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[6]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_7 ),
.O(\slaveRegDo_mux_0_reg[14] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[14]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[14] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[11]),
.I5(\xsdb_reg_reg[14]_1 ),
.O(\slaveRegDo_mux_0[14]_i_5_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA0000303F))
\slaveRegDo_mux_0[1]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1] [0]),
.I1(\slaveRegDo_mux_0[1]_i_2_n_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ),
.I4(s_daddr_o[6]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'h2F202F2F2F202020))
\slaveRegDo_mux_0[1]_i_2
(.I0(\slaveRegDo_mux_0[1]_i_4_n_0 ),
.I1(\xsdb_reg_reg[1]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[2]_0 ),
.I4(s_daddr_o[3]),
.I5(\xsdb_reg_reg[1]_1 ),
.O(\slaveRegDo_mux_0[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[1]_i_4
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[1] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[0]),
.I5(\xsdb_reg_reg[1]_2 ),
.O(\slaveRegDo_mux_0[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA0000303F))
\slaveRegDo_mux_0[2]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[1] [1]),
.I1(\slaveRegDo_mux_0[2]_i_2_n_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I4(s_daddr_o[6]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'h2020202020202F20))
\slaveRegDo_mux_0[2]_i_2
(.I0(\slaveRegDo_mux_0[2]_i_4_n_0 ),
.I1(\xsdb_reg_reg[2]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[2]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_0 ),
.O(\slaveRegDo_mux_0[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[2]_i_4
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(use_probe_debug_circuit_1),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[1]),
.I5(\xsdb_reg_reg[2]_1 ),
.O(\slaveRegDo_mux_0[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hF8C8380800000000))
\slaveRegDo_mux_0[5]_i_6
(.I0(\xsdb_reg_reg_n_0_[5] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(read_reset_addr[2]),
.I4(\xsdb_reg_reg[5]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.O(\slaveRegDo_mux_0_reg[5] ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[6]_i_3
(.I0(\slaveRegDo_mux_0[6]_i_5_n_0 ),
.I1(\xsdb_reg_reg[6]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_1 ),
.O(\slaveRegDo_mux_0_reg[6] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[6]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[6] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[3]),
.I5(\xsdb_reg_reg[6]_1 ),
.O(\slaveRegDo_mux_0[6]_i_5_n_0 ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[7]_i_3
(.I0(\slaveRegDo_mux_0[7]_i_5_n_0 ),
.I1(\xsdb_reg_reg[7]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[1]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_2 ),
.O(\slaveRegDo_mux_0_reg[7] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[7]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[7] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[4]),
.I5(\xsdb_reg_reg[7]_1 ),
.O(\slaveRegDo_mux_0[7]_i_5_n_0 ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[8]_i_3
(.I0(\slaveRegDo_mux_0[8]_i_5_n_0 ),
.I1(\xsdb_reg_reg[8]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[2]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_3 ),
.O(\slaveRegDo_mux_0_reg[8] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[8]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[8] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[5]),
.I5(\xsdb_reg_reg[8]_1 ),
.O(\slaveRegDo_mux_0[8]_i_5_n_0 ));
LUT6 #(
.INIT(64'h202020202F2F202F))
\slaveRegDo_mux_0[9]_i_3
(.I0(\slaveRegDo_mux_0[9]_i_5_n_0 ),
.I1(\xsdb_reg_reg[9]_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I3(Q[3]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[1]_0 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3]_4 ),
.O(\slaveRegDo_mux_0_reg[9] ));
LUT6 #(
.INIT(64'h557F5F7FF57FFF7F))
\slaveRegDo_mux_0[9]_i_5
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.I1(\xsdb_reg_reg_n_0_[9] ),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[1]),
.I4(read_reset_addr[6]),
.I5(\xsdb_reg_reg[9]_1 ),
.O(\slaveRegDo_mux_0[9]_i_5_n_0 ));
LUT5 #(
.INIT(32'h00000080))
\xsdb_reg[15]_i_1__12
(.I0(\xsdb_reg_reg[0]_0 ),
.I1(\xsdb_reg_reg[0]_1 ),
.I2(s_daddr_o[4]),
.I3(s_daddr_o[5]),
.I4(s_daddr_o[6]),
.O(\xsdb_reg[15]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\xsdb_reg[15]_i_2__3
(.I0(s_daddr_o[9]),
.I1(s_daddr_o[8]),
.I2(s_daddr_o[7]),
.I3(s_daddr_o[10]),
.I4(s_daddr_o[11]),
.I5(s_daddr_o[12]),
.O(\xsdb_reg_reg[0]_0 ));
LUT6 #(
.INIT(64'h1000000000000000))
\xsdb_reg[15]_i_3__1
(.I0(s_daddr_o[1]),
.I1(s_daddr_o[3]),
.I2(s_den_o),
.I3(s_daddr_o[2]),
.I4(s_dwe_o),
.I5(s_daddr_o[0]),
.O(\xsdb_reg_reg[0]_1 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[0]),
.Q(SR),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[10]),
.Q(\xsdb_reg_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[11]),
.Q(\xsdb_reg_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[12]),
.Q(\xsdb_reg_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[13]),
.Q(\xsdb_reg_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[14]),
.Q(\xsdb_reg_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[15]),
.Q(\slaveRegDo_mux_0_reg[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[1]),
.Q(\xsdb_reg_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[2]),
.Q(use_probe_debug_circuit_1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[3]),
.Q(\slaveRegDo_mux_0_reg[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_0_reg[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[5]),
.Q(\xsdb_reg_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[6]),
.Q(\xsdb_reg_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[7]),
.Q(\xsdb_reg_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[8]),
.Q(\xsdb_reg_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__12_n_0 ),
.D(s_di_o[9]),
.Q(\xsdb_reg_reg_n_0_[9] ),
.R(1'b0));
endmodule | 8 |
2,423 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_181
(\I_EN_CTL_EQ1.temp_en_reg ,
reg_ce,
\slaveRegDo_mux_3_reg[0] ,
\BRAM_DATA_reg[15] ,
D,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[10] ,
E,
s_di_o,
s_dclk_o);
output \I_EN_CTL_EQ1.temp_en_reg ;
output reg_ce;
output \slaveRegDo_mux_3_reg[0] ;
output [15:0]\BRAM_DATA_reg[15] ;
input [10:0]D;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
input [0:0]E;
input [15:0]s_di_o;
input s_dclk_o;
wire [15:0]\BRAM_DATA_reg[15] ;
wire [10:0]D;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
wire \I_EN_CTL_EQ1.temp_en_reg ;
wire reg_ce;
wire s_dclk_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_3_reg[0] ;
wire \xsdb_reg[15]_i_1__5_n_0 ;
LUT6 #(
.INIT(64'h0000000000000004))
\I_EN_CTL_EQ1.temp_en_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[10] ),
.I1(E),
.I2(D[10]),
.I3(D[1]),
.I4(\slaveRegDo_mux_3_reg[0] ),
.I5(\I_EN_CTL_EQ1.temp_en_reg ),
.O(reg_ce));
LUT3 #(
.INIT(8'hDF))
\I_EN_CTL_EQ1.temp_en_i_3
(.I0(D[3]),
.I1(D[0]),
.I2(D[2]),
.O(\I_EN_CTL_EQ1.temp_en_reg ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\slaveRegDo_mux_3[15]_i_1
(.I0(D[5]),
.I1(D[6]),
.I2(D[4]),
.I3(D[7]),
.I4(D[9]),
.I5(D[8]),
.O(\slaveRegDo_mux_3_reg[0] ));
LUT2 #(
.INIT(4'h8))
\xsdb_reg[15]_i_1__5
(.I0(s_dwe_o),
.I1(reg_ce),
.O(\xsdb_reg[15]_i_1__5_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[0]),
.Q(\BRAM_DATA_reg[15] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[10]),
.Q(\BRAM_DATA_reg[15] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[11]),
.Q(\BRAM_DATA_reg[15] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[12]),
.Q(\BRAM_DATA_reg[15] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[13]),
.Q(\BRAM_DATA_reg[15] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[14]),
.Q(\BRAM_DATA_reg[15] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[15]),
.Q(\BRAM_DATA_reg[15] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[1]),
.Q(\BRAM_DATA_reg[15] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[2]),
.Q(\BRAM_DATA_reg[15] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[3]),
.Q(\BRAM_DATA_reg[15] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[4]),
.Q(\BRAM_DATA_reg[15] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[5]),
.Q(\BRAM_DATA_reg[15] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[6]),
.Q(\BRAM_DATA_reg[15] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[7]),
.Q(\BRAM_DATA_reg[15] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[8]),
.Q(\BRAM_DATA_reg[15] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[9]),
.Q(\BRAM_DATA_reg[15] [9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl_181
(\I_EN_CTL_EQ1.temp_en_reg ,
reg_ce,
\slaveRegDo_mux_3_reg[0] ,
\BRAM_DATA_reg[15] ,
D,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[10] ,
E,
s_di_o,
s_dclk_o); |
output \I_EN_CTL_EQ1.temp_en_reg ;
output reg_ce;
output \slaveRegDo_mux_3_reg[0] ;
output [15:0]\BRAM_DATA_reg[15] ;
input [10:0]D;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
input [0:0]E;
input [15:0]s_di_o;
input s_dclk_o;
wire [15:0]\BRAM_DATA_reg[15] ;
wire [10:0]D;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[10] ;
wire \I_EN_CTL_EQ1.temp_en_reg ;
wire reg_ce;
wire s_dclk_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire \slaveRegDo_mux_3_reg[0] ;
wire \xsdb_reg[15]_i_1__5_n_0 ;
LUT6 #(
.INIT(64'h0000000000000004))
\I_EN_CTL_EQ1.temp_en_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[10] ),
.I1(E),
.I2(D[10]),
.I3(D[1]),
.I4(\slaveRegDo_mux_3_reg[0] ),
.I5(\I_EN_CTL_EQ1.temp_en_reg ),
.O(reg_ce));
LUT3 #(
.INIT(8'hDF))
\I_EN_CTL_EQ1.temp_en_i_3
(.I0(D[3]),
.I1(D[0]),
.I2(D[2]),
.O(\I_EN_CTL_EQ1.temp_en_reg ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\slaveRegDo_mux_3[15]_i_1
(.I0(D[5]),
.I1(D[6]),
.I2(D[4]),
.I3(D[7]),
.I4(D[9]),
.I5(D[8]),
.O(\slaveRegDo_mux_3_reg[0] ));
LUT2 #(
.INIT(4'h8))
\xsdb_reg[15]_i_1__5
(.I0(s_dwe_o),
.I1(reg_ce),
.O(\xsdb_reg[15]_i_1__5_n_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[0]),
.Q(\BRAM_DATA_reg[15] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[10]),
.Q(\BRAM_DATA_reg[15] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[11]),
.Q(\BRAM_DATA_reg[15] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[12]),
.Q(\BRAM_DATA_reg[15] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[13]),
.Q(\BRAM_DATA_reg[15] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[14]),
.Q(\BRAM_DATA_reg[15] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[15]),
.Q(\BRAM_DATA_reg[15] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[1]),
.Q(\BRAM_DATA_reg[15] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[2]),
.Q(\BRAM_DATA_reg[15] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[3]),
.Q(\BRAM_DATA_reg[15] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[4]),
.Q(\BRAM_DATA_reg[15] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[5]),
.Q(\BRAM_DATA_reg[15] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[6]),
.Q(\BRAM_DATA_reg[15] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[7]),
.Q(\BRAM_DATA_reg[15] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[8]),
.Q(\BRAM_DATA_reg[15] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__5_n_0 ),
.D(s_di_o[9]),
.Q(\BRAM_DATA_reg[15] [9]),
.R(1'b0));
endmodule | 8 |
2,424 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized0
(\slaveRegDo_mux_0_reg[15] ,
\xsdb_reg_reg[0]_0 ,
\slaveRegDo_mux_0_reg[0] ,
u_scnt_cmp_q,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
halt_ctrl,
scnt_cmp_temp,
wcnt_lcmp_temp,
wcnt_hcmp_temp,
s_daddr_o,
\xsdb_reg_reg[15]_0 ,
s_dwe_o,
s_den_o,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_di_o,
s_dclk_o,
DOUT_O,
shift_en_reg,
shift_en_reg_0);
output \slaveRegDo_mux_0_reg[15] ;
output \xsdb_reg_reg[0]_0 ;
output \slaveRegDo_mux_0_reg[0] ;
output u_scnt_cmp_q;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output halt_ctrl;
output scnt_cmp_temp;
output wcnt_lcmp_temp;
output wcnt_hcmp_temp;
input [6:0]s_daddr_o;
input [12:0]\xsdb_reg_reg[15]_0 ;
input s_dwe_o;
input s_den_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input [15:0]s_di_o;
input s_dclk_o;
input DOUT_O;
input shift_en_reg;
input shift_en_reg_0;
wire DOUT_O;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire halt_ctrl;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire scnt_cmp_temp;
wire shift_en_reg;
wire shift_en_reg_0;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire u_scnt_cmp_q;
wire wcnt_hcmp_temp;
wire wcnt_lcmp_temp;
wire \xsdb_reg[15]_i_1__8_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire [12:0]\xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg_n_0_[10] ;
wire \xsdb_reg_reg_n_0_[11] ;
wire \xsdb_reg_reg_n_0_[12] ;
wire \xsdb_reg_reg_n_0_[13] ;
wire \xsdb_reg_reg_n_0_[14] ;
wire \xsdb_reg_reg_n_0_[15] ;
wire \xsdb_reg_reg_n_0_[2] ;
wire \xsdb_reg_reg_n_0_[3] ;
wire \xsdb_reg_reg_n_0_[6] ;
wire \xsdb_reg_reg_n_0_[7] ;
wire \xsdb_reg_reg_n_0_[8] ;
wire \xsdb_reg_reg_n_0_[9] ;
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[0]_i_9
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(u_scnt_cmp_q),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [0]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[0] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[10]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[10] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [7]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[10] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[11]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[11] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [8]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[11] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[12]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[12] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [9]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[12] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[13]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[13] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [10]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[13] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[14]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[14] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [11]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[14] ));
LUT6 #(
.INIT(64'h4044400011001100))
\slaveRegDo_mux_0[15]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[15] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [12]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[15] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[2]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[2] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [1]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[2] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[3]_i_10
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[3] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [2]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[3] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[6]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[6] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [3]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[6] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[7]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[7] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [4]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[7] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[8]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[8] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [5]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[8] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[9]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[9] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [6]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[9] ));
(* SOFT_HLUTNM = "soft_lutpair183" *)
LUT2 #(
.INIT(4'h8))
u_scnt_cmp_q_i_2
(.I0(u_scnt_cmp_q),
.I1(DOUT_O),
.O(scnt_cmp_temp));
LUT2 #(
.INIT(4'h8))
u_wcnt_hcmp_q_i_1
(.I0(u_scnt_cmp_q),
.I1(shift_en_reg_0),
.O(wcnt_hcmp_temp));
(* SOFT_HLUTNM = "soft_lutpair183" *)
LUT2 #(
.INIT(4'h8))
u_wcnt_lcmp_q_i_1
(.I0(u_scnt_cmp_q),
.I1(shift_en_reg),
.O(wcnt_lcmp_temp));
LUT6 #(
.INIT(64'h0000000800000000))
\xsdb_reg[15]_i_1__8
(.I0(s_dwe_o),
.I1(s_den_o),
.I2(s_daddr_o[5]),
.I3(s_daddr_o[6]),
.I4(s_daddr_o[4]),
.I5(\xsdb_reg_reg[0]_0 ),
.O(\xsdb_reg[15]_i_1__8_n_0 ));
LUT5 #(
.INIT(32'h20000000))
\xsdb_reg[15]_i_2__0
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[1]),
.O(\xsdb_reg_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[0]),
.Q(u_scnt_cmp_q),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[10]),
.Q(\xsdb_reg_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[11]),
.Q(\xsdb_reg_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[12]),
.Q(\xsdb_reg_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[13]),
.Q(\xsdb_reg_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[14]),
.Q(\xsdb_reg_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[15]),
.Q(\xsdb_reg_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[1]),
.Q(halt_ctrl),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[2]),
.Q(\xsdb_reg_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[3]),
.Q(\xsdb_reg_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_0_reg[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[6]),
.Q(\xsdb_reg_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[7]),
.Q(\xsdb_reg_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[8]),
.Q(\xsdb_reg_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[9]),
.Q(\xsdb_reg_reg_n_0_[9] ),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized0
(\slaveRegDo_mux_0_reg[15] ,
\xsdb_reg_reg[0]_0 ,
\slaveRegDo_mux_0_reg[0] ,
u_scnt_cmp_q,
\slaveRegDo_mux_0_reg[2] ,
\slaveRegDo_mux_0_reg[3] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[5] ,
\slaveRegDo_mux_0_reg[4] ,
halt_ctrl,
scnt_cmp_temp,
wcnt_lcmp_temp,
wcnt_hcmp_temp,
s_daddr_o,
\xsdb_reg_reg[15]_0 ,
s_dwe_o,
s_den_o,
\G_1PIPE_IFACE.s_daddr_r_reg[9] ,
s_di_o,
s_dclk_o,
DOUT_O,
shift_en_reg,
shift_en_reg_0); |
output \slaveRegDo_mux_0_reg[15] ;
output \xsdb_reg_reg[0]_0 ;
output \slaveRegDo_mux_0_reg[0] ;
output u_scnt_cmp_q;
output \slaveRegDo_mux_0_reg[2] ;
output \slaveRegDo_mux_0_reg[3] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[5] ;
output \slaveRegDo_mux_0_reg[4] ;
output halt_ctrl;
output scnt_cmp_temp;
output wcnt_lcmp_temp;
output wcnt_hcmp_temp;
input [6:0]s_daddr_o;
input [12:0]\xsdb_reg_reg[15]_0 ;
input s_dwe_o;
input s_den_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
input [15:0]s_di_o;
input s_dclk_o;
input DOUT_O;
input shift_en_reg;
input shift_en_reg_0;
wire DOUT_O;
wire \G_1PIPE_IFACE.s_daddr_r_reg[9] ;
wire halt_ctrl;
wire [6:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [15:0]s_di_o;
wire s_dwe_o;
wire scnt_cmp_temp;
wire shift_en_reg;
wire shift_en_reg_0;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[2] ;
wire \slaveRegDo_mux_0_reg[3] ;
wire \slaveRegDo_mux_0_reg[4] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire u_scnt_cmp_q;
wire wcnt_hcmp_temp;
wire wcnt_lcmp_temp;
wire \xsdb_reg[15]_i_1__8_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire [12:0]\xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg_n_0_[10] ;
wire \xsdb_reg_reg_n_0_[11] ;
wire \xsdb_reg_reg_n_0_[12] ;
wire \xsdb_reg_reg_n_0_[13] ;
wire \xsdb_reg_reg_n_0_[14] ;
wire \xsdb_reg_reg_n_0_[15] ;
wire \xsdb_reg_reg_n_0_[2] ;
wire \xsdb_reg_reg_n_0_[3] ;
wire \xsdb_reg_reg_n_0_[6] ;
wire \xsdb_reg_reg_n_0_[7] ;
wire \xsdb_reg_reg_n_0_[8] ;
wire \xsdb_reg_reg_n_0_[9] ;
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[0]_i_9
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(u_scnt_cmp_q),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [0]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[0] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[10]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[10] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [7]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[10] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[11]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[11] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [8]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[11] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[12]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[12] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [9]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[12] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[13]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[13] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [10]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[13] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[14]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[14] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [11]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[14] ));
LUT6 #(
.INIT(64'h4044400011001100))
\slaveRegDo_mux_0[15]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[15] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [12]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[15] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[2]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[2] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [1]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[2] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[3]_i_10
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[3] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [2]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[3] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[6]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[6] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [3]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[6] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[7]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[7] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [4]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[7] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[8]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[8] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [5]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[8] ));
LUT6 #(
.INIT(64'h4044400000000000))
\slaveRegDo_mux_0[9]_i_7
(.I0(s_daddr_o[3]),
.I1(s_daddr_o[2]),
.I2(\xsdb_reg_reg_n_0_[9] ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_0 [6]),
.I5(s_daddr_o[1]),
.O(\slaveRegDo_mux_0_reg[9] ));
(* SOFT_HLUTNM = "soft_lutpair183" *)
LUT2 #(
.INIT(4'h8))
u_scnt_cmp_q_i_2
(.I0(u_scnt_cmp_q),
.I1(DOUT_O),
.O(scnt_cmp_temp));
LUT2 #(
.INIT(4'h8))
u_wcnt_hcmp_q_i_1
(.I0(u_scnt_cmp_q),
.I1(shift_en_reg_0),
.O(wcnt_hcmp_temp));
(* SOFT_HLUTNM = "soft_lutpair183" *)
LUT2 #(
.INIT(4'h8))
u_wcnt_lcmp_q_i_1
(.I0(u_scnt_cmp_q),
.I1(shift_en_reg),
.O(wcnt_lcmp_temp));
LUT6 #(
.INIT(64'h0000000800000000))
\xsdb_reg[15]_i_1__8
(.I0(s_dwe_o),
.I1(s_den_o),
.I2(s_daddr_o[5]),
.I3(s_daddr_o[6]),
.I4(s_daddr_o[4]),
.I5(\xsdb_reg_reg[0]_0 ),
.O(\xsdb_reg[15]_i_1__8_n_0 ));
LUT5 #(
.INIT(32'h20000000))
\xsdb_reg[15]_i_2__0
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[9] ),
.I1(s_daddr_o[3]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[1]),
.O(\xsdb_reg_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[0]),
.Q(u_scnt_cmp_q),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[10]),
.Q(\xsdb_reg_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[11]),
.Q(\xsdb_reg_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[12]),
.Q(\xsdb_reg_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[13]),
.Q(\xsdb_reg_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[14]),
.Q(\xsdb_reg_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[15]),
.Q(\xsdb_reg_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[1]),
.Q(halt_ctrl),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[2]),
.Q(\xsdb_reg_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[3]),
.Q(\xsdb_reg_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[4]),
.Q(\slaveRegDo_mux_0_reg[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[6]),
.Q(\xsdb_reg_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[7]),
.Q(\xsdb_reg_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[8]),
.Q(\xsdb_reg_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__8_n_0 ),
.D(s_di_o[9]),
.Q(\xsdb_reg_reg_n_0_[9] ),
.R(1'b0));
endmodule | 8 |
2,425 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized1
(D,
\slaveRegDo_mux_0_reg[15] ,
en_adv_trigger_1,
\slaveRegDo_mux_0_reg[0] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
capture_qual_ctrl_1,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ,
\xsdb_reg_reg[15]_0 ,
\xsdb_reg_reg[15]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\xsdb_reg_reg[4]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\xsdb_reg_reg[3]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\xsdb_reg_reg[15]_2 ,
\xsdb_reg_reg[15]_3 ,
\xsdb_reg_reg[4]_1 ,
\xsdb_reg_reg[3]_1 ,
\xsdb_reg_reg[0]_0 ,
s_di_o,
s_dclk_o);
output [1:0]D;
output \slaveRegDo_mux_0_reg[15] ;
output en_adv_trigger_1;
output \slaveRegDo_mux_0_reg[0] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output [1:0]capture_qual_ctrl_1;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [7:0]s_daddr_o;
input [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ;
input \xsdb_reg_reg[15]_0 ;
input \xsdb_reg_reg[15]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \xsdb_reg_reg[4]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \xsdb_reg_reg[3]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \xsdb_reg_reg[15]_2 ;
input [3:0]\xsdb_reg_reg[15]_3 ;
input \xsdb_reg_reg[4]_1 ;
input \xsdb_reg_reg[3]_1 ;
input \xsdb_reg_reg[0]_0 ;
input [15:0]s_di_o;
input s_dclk_o;
wire [1:0]D;
wire [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [1:0]capture_qual_ctrl_1;
wire en_adv_trigger_1;
wire [7:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0[15]_i_3_n_0 ;
wire \slaveRegDo_mux_0[15]_i_5_n_0 ;
wire \slaveRegDo_mux_0[3]_i_2_n_0 ;
wire \slaveRegDo_mux_0[3]_i_4_n_0 ;
wire \slaveRegDo_mux_0[4]_i_2_n_0 ;
wire \slaveRegDo_mux_0[4]_i_6_n_0 ;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__14_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg[15]_1 ;
wire \xsdb_reg_reg[15]_2 ;
wire [3:0]\xsdb_reg_reg[15]_3 ;
wire \xsdb_reg_reg[3]_0 ;
wire \xsdb_reg_reg[3]_1 ;
wire \xsdb_reg_reg[4]_0 ;
wire \xsdb_reg_reg[4]_1 ;
wire \xsdb_reg_reg_n_0_[0] ;
wire \xsdb_reg_reg_n_0_[15] ;
wire \xsdb_reg_reg_n_0_[4] ;
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux_0[0]_i_5
(.I0(\xsdb_reg_reg_n_0_[0] ),
.I1(s_daddr_o[1]),
.I2(\xsdb_reg_reg[0]_0 ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_3 [0]),
.O(\slaveRegDo_mux_0_reg[0] ));
LUT6 #(
.INIT(64'h02020202020E0202))
\slaveRegDo_mux_0[15]_i_2
(.I0(\slaveRegDo_mux_0[15]_i_3_n_0 ),
.I1(s_daddr_o[7]),
.I2(s_daddr_o[5]),
.I3(s_daddr_o[3]),
.I4(\xsdb_reg_reg[15]_0 ),
.I5(s_daddr_o[4]),
.O(\slaveRegDo_mux_0_reg[15] ));
LUT6 #(
.INIT(64'h2C20FFFF2C200000))
\slaveRegDo_mux_0[15]_i_3
(.I0(\slaveRegDo_mux_0[15]_i_5_n_0 ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[3]),
.I3(\xsdb_reg_reg[15]_1 ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0[15]_i_3_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux_0[15]_i_5
(.I0(\xsdb_reg_reg_n_0_[15] ),
.I1(s_daddr_o[1]),
.I2(\xsdb_reg_reg[15]_2 ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_3 [3]),
.O(\slaveRegDo_mux_0[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA0000303F))
\slaveRegDo_mux_0[3]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[0] [0]),
.I1(\slaveRegDo_mux_0[3]_i_2_n_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ),
.I4(s_daddr_o[6]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'hD3DFFFFFD3DF0000))
\slaveRegDo_mux_0[3]_i_2
(.I0(\slaveRegDo_mux_0[3]_i_4_n_0 ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[3]),
.I3(\xsdb_reg_reg[3]_0 ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.O(\slaveRegDo_mux_0[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux_0[3]_i_4
(.I0(en_adv_trigger_1),
.I1(s_daddr_o[1]),
.I2(\xsdb_reg_reg[3]_1 ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_3 [1]),
.O(\slaveRegDo_mux_0[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA0000303F))
\slaveRegDo_mux_0[4]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[0] [1]),
.I1(\slaveRegDo_mux_0[4]_i_2_n_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ),
.I4(s_daddr_o[6]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'hD3DFFFFFD3DF0000))
\slaveRegDo_mux_0[4]_i_2
(.I0(\slaveRegDo_mux_0[4]_i_6_n_0 ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[3]),
.I3(\xsdb_reg_reg[4]_0 ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.O(\slaveRegDo_mux_0[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux_0[4]_i_6
(.I0(\xsdb_reg_reg_n_0_[4] ),
.I1(s_daddr_o[1]),
.I2(\xsdb_reg_reg[4]_1 ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_3 [2]),
.O(\slaveRegDo_mux_0[4]_i_6_n_0 ));
LUT5 #(
.INIT(32'h00100000))
\xsdb_reg[15]_i_1__14
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.O(\xsdb_reg[15]_i_1__14_n_0 ));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[0]),
.Q(\xsdb_reg_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[15]),
.Q(\xsdb_reg_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[1]),
.Q(capture_qual_ctrl_1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[2]),
.Q(capture_qual_ctrl_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[3]),
.Q(en_adv_trigger_1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[4]),
.Q(\xsdb_reg_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[9] ),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized1
(D,
\slaveRegDo_mux_0_reg[15] ,
en_adv_trigger_1,
\slaveRegDo_mux_0_reg[0] ,
\slaveRegDo_mux_0_reg[14] ,
\slaveRegDo_mux_0_reg[13] ,
\slaveRegDo_mux_0_reg[12] ,
\slaveRegDo_mux_0_reg[11] ,
\slaveRegDo_mux_0_reg[10] ,
\slaveRegDo_mux_0_reg[9] ,
\slaveRegDo_mux_0_reg[8] ,
\slaveRegDo_mux_0_reg[7] ,
\slaveRegDo_mux_0_reg[6] ,
\slaveRegDo_mux_0_reg[5] ,
capture_qual_ctrl_1,
\G_1PIPE_IFACE.s_daddr_r_reg[4] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ,
\xsdb_reg_reg[15]_0 ,
\xsdb_reg_reg[15]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ,
\G_1PIPE_IFACE.s_daddr_r_reg[3] ,
\xsdb_reg_reg[4]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[2] ,
\xsdb_reg_reg[3]_0 ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
\xsdb_reg_reg[15]_2 ,
\xsdb_reg_reg[15]_3 ,
\xsdb_reg_reg[4]_1 ,
\xsdb_reg_reg[3]_1 ,
\xsdb_reg_reg[0]_0 ,
s_di_o,
s_dclk_o); |
output [1:0]D;
output \slaveRegDo_mux_0_reg[15] ;
output en_adv_trigger_1;
output \slaveRegDo_mux_0_reg[0] ;
output \slaveRegDo_mux_0_reg[14] ;
output \slaveRegDo_mux_0_reg[13] ;
output \slaveRegDo_mux_0_reg[12] ;
output \slaveRegDo_mux_0_reg[11] ;
output \slaveRegDo_mux_0_reg[10] ;
output \slaveRegDo_mux_0_reg[9] ;
output \slaveRegDo_mux_0_reg[8] ;
output \slaveRegDo_mux_0_reg[7] ;
output \slaveRegDo_mux_0_reg[6] ;
output \slaveRegDo_mux_0_reg[5] ;
output [1:0]capture_qual_ctrl_1;
input \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
input [7:0]s_daddr_o;
input [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ;
input \xsdb_reg_reg[15]_0 ;
input \xsdb_reg_reg[15]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
input \xsdb_reg_reg[4]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
input \xsdb_reg_reg[3]_0 ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input \xsdb_reg_reg[15]_2 ;
input [3:0]\xsdb_reg_reg[15]_3 ;
input \xsdb_reg_reg[4]_1 ;
input \xsdb_reg_reg[3]_1 ;
input \xsdb_reg_reg[0]_0 ;
input [15:0]s_di_o;
input s_dclk_o;
wire [1:0]D;
wire [1:0]\G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[2] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[3] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ;
wire [1:0]capture_qual_ctrl_1;
wire en_adv_trigger_1;
wire [7:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire \slaveRegDo_mux_0[15]_i_3_n_0 ;
wire \slaveRegDo_mux_0[15]_i_5_n_0 ;
wire \slaveRegDo_mux_0[3]_i_2_n_0 ;
wire \slaveRegDo_mux_0[3]_i_4_n_0 ;
wire \slaveRegDo_mux_0[4]_i_2_n_0 ;
wire \slaveRegDo_mux_0[4]_i_6_n_0 ;
wire \slaveRegDo_mux_0_reg[0] ;
wire \slaveRegDo_mux_0_reg[10] ;
wire \slaveRegDo_mux_0_reg[11] ;
wire \slaveRegDo_mux_0_reg[12] ;
wire \slaveRegDo_mux_0_reg[13] ;
wire \slaveRegDo_mux_0_reg[14] ;
wire \slaveRegDo_mux_0_reg[15] ;
wire \slaveRegDo_mux_0_reg[5] ;
wire \slaveRegDo_mux_0_reg[6] ;
wire \slaveRegDo_mux_0_reg[7] ;
wire \slaveRegDo_mux_0_reg[8] ;
wire \slaveRegDo_mux_0_reg[9] ;
wire \xsdb_reg[15]_i_1__14_n_0 ;
wire \xsdb_reg_reg[0]_0 ;
wire \xsdb_reg_reg[15]_0 ;
wire \xsdb_reg_reg[15]_1 ;
wire \xsdb_reg_reg[15]_2 ;
wire [3:0]\xsdb_reg_reg[15]_3 ;
wire \xsdb_reg_reg[3]_0 ;
wire \xsdb_reg_reg[3]_1 ;
wire \xsdb_reg_reg[4]_0 ;
wire \xsdb_reg_reg[4]_1 ;
wire \xsdb_reg_reg_n_0_[0] ;
wire \xsdb_reg_reg_n_0_[15] ;
wire \xsdb_reg_reg_n_0_[4] ;
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux_0[0]_i_5
(.I0(\xsdb_reg_reg_n_0_[0] ),
.I1(s_daddr_o[1]),
.I2(\xsdb_reg_reg[0]_0 ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_3 [0]),
.O(\slaveRegDo_mux_0_reg[0] ));
LUT6 #(
.INIT(64'h02020202020E0202))
\slaveRegDo_mux_0[15]_i_2
(.I0(\slaveRegDo_mux_0[15]_i_3_n_0 ),
.I1(s_daddr_o[7]),
.I2(s_daddr_o[5]),
.I3(s_daddr_o[3]),
.I4(\xsdb_reg_reg[15]_0 ),
.I5(s_daddr_o[4]),
.O(\slaveRegDo_mux_0_reg[15] ));
LUT6 #(
.INIT(64'h2C20FFFF2C200000))
\slaveRegDo_mux_0[15]_i_3
(.I0(\slaveRegDo_mux_0[15]_i_5_n_0 ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[3]),
.I3(\xsdb_reg_reg[15]_1 ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[3] ),
.O(\slaveRegDo_mux_0[15]_i_3_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux_0[15]_i_5
(.I0(\xsdb_reg_reg_n_0_[15] ),
.I1(s_daddr_o[1]),
.I2(\xsdb_reg_reg[15]_2 ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_3 [3]),
.O(\slaveRegDo_mux_0[15]_i_5_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA0000303F))
\slaveRegDo_mux_0[3]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[0] [0]),
.I1(\slaveRegDo_mux_0[3]_i_2_n_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[4]_0 ),
.I4(s_daddr_o[6]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'hD3DFFFFFD3DF0000))
\slaveRegDo_mux_0[3]_i_2
(.I0(\slaveRegDo_mux_0[3]_i_4_n_0 ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[3]),
.I3(\xsdb_reg_reg[3]_0 ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.O(\slaveRegDo_mux_0[3]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux_0[3]_i_4
(.I0(en_adv_trigger_1),
.I1(s_daddr_o[1]),
.I2(\xsdb_reg_reg[3]_1 ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_3 [1]),
.O(\slaveRegDo_mux_0[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAAA0000303F))
\slaveRegDo_mux_0[4]_i_1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[0] [1]),
.I1(\slaveRegDo_mux_0[4]_i_2_n_0 ),
.I2(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[4]_1 ),
.I4(s_daddr_o[6]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[7]_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'hD3DFFFFFD3DF0000))
\slaveRegDo_mux_0[4]_i_2
(.I0(\slaveRegDo_mux_0[4]_i_6_n_0 ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[3]),
.I3(\xsdb_reg_reg[4]_0 ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[7]_1 ),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[2] ),
.O(\slaveRegDo_mux_0[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\slaveRegDo_mux_0[4]_i_6
(.I0(\xsdb_reg_reg_n_0_[4] ),
.I1(s_daddr_o[1]),
.I2(\xsdb_reg_reg[4]_1 ),
.I3(s_daddr_o[0]),
.I4(\xsdb_reg_reg[15]_3 [2]),
.O(\slaveRegDo_mux_0[4]_i_6_n_0 ));
LUT5 #(
.INIT(32'h00100000))
\xsdb_reg[15]_i_1__14
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[4] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.O(\xsdb_reg[15]_i_1__14_n_0 ));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[0]),
.Q(\xsdb_reg_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[10]),
.Q(\slaveRegDo_mux_0_reg[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[11]),
.Q(\slaveRegDo_mux_0_reg[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[12]),
.Q(\slaveRegDo_mux_0_reg[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[13]),
.Q(\slaveRegDo_mux_0_reg[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[14]),
.Q(\slaveRegDo_mux_0_reg[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[15]),
.Q(\xsdb_reg_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[1]),
.Q(capture_qual_ctrl_1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[2]),
.Q(capture_qual_ctrl_1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[3]),
.Q(en_adv_trigger_1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[4]),
.Q(\xsdb_reg_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[5]),
.Q(\slaveRegDo_mux_0_reg[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[6]),
.Q(\slaveRegDo_mux_0_reg[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[7]),
.Q(\slaveRegDo_mux_0_reg[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[8]),
.Q(\slaveRegDo_mux_0_reg[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__14_n_0 ),
.D(s_di_o[9]),
.Q(\slaveRegDo_mux_0_reg[9] ),
.R(1'b0));
endmodule | 8 |
2,426 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized2
(slaveRegDo_80,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] );
output [15:0]slaveRegDo_80;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_80;
wire \xsdb_reg[15]_i_1__1_n_0 ;
LUT5 #(
.INIT(32'h00020000))
\xsdb_reg[15]_i_1__1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(\xsdb_reg[15]_i_1__1_n_0 ));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[0]),
.Q(slaveRegDo_80[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[10]),
.Q(slaveRegDo_80[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[11]),
.Q(slaveRegDo_80[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[12]),
.Q(slaveRegDo_80[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[13]),
.Q(slaveRegDo_80[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[14]),
.Q(slaveRegDo_80[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[15]),
.Q(slaveRegDo_80[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_80[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[2]),
.Q(slaveRegDo_80[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[3]),
.Q(slaveRegDo_80[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[4]),
.Q(slaveRegDo_80[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[5]),
.Q(slaveRegDo_80[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[6]),
.Q(slaveRegDo_80[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[7]),
.Q(slaveRegDo_80[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[8]),
.Q(slaveRegDo_80[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[9]),
.Q(slaveRegDo_80[9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized2
(slaveRegDo_80,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ); |
output [15:0]slaveRegDo_80;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_80;
wire \xsdb_reg[15]_i_1__1_n_0 ;
LUT5 #(
.INIT(32'h00020000))
\xsdb_reg[15]_i_1__1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(\xsdb_reg[15]_i_1__1_n_0 ));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[0]),
.Q(slaveRegDo_80[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[10]),
.Q(slaveRegDo_80[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[11]),
.Q(slaveRegDo_80[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[12]),
.Q(slaveRegDo_80[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[13]),
.Q(slaveRegDo_80[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[14]),
.Q(slaveRegDo_80[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[15]),
.Q(slaveRegDo_80[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_80[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[2]),
.Q(slaveRegDo_80[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[3]),
.Q(slaveRegDo_80[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[4]),
.Q(slaveRegDo_80[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[5]),
.Q(slaveRegDo_80[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[6]),
.Q(slaveRegDo_80[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[7]),
.Q(slaveRegDo_80[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[8]),
.Q(slaveRegDo_80[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__1_n_0 ),
.D(s_di_o[9]),
.Q(slaveRegDo_80[9]),
.R(1'b0));
endmodule | 8 |
2,427 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized3
(slaveRegDo_82,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] );
output [15:0]slaveRegDo_82;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_82;
wire \xsdb_reg[15]_i_1__3_n_0 ;
LUT5 #(
.INIT(32'h00200000))
\xsdb_reg[15]_i_1__3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(\xsdb_reg[15]_i_1__3_n_0 ));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[0]),
.Q(slaveRegDo_82[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[10]),
.Q(slaveRegDo_82[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[11]),
.Q(slaveRegDo_82[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[12]),
.Q(slaveRegDo_82[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[13]),
.Q(slaveRegDo_82[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[14]),
.Q(slaveRegDo_82[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[15]),
.Q(slaveRegDo_82[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_82[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[2]),
.Q(slaveRegDo_82[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[3]),
.Q(slaveRegDo_82[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[4]),
.Q(slaveRegDo_82[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[5]),
.Q(slaveRegDo_82[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[6]),
.Q(slaveRegDo_82[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[7]),
.Q(slaveRegDo_82[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[8]),
.Q(slaveRegDo_82[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[9]),
.Q(slaveRegDo_82[9]),
.R(1'b0));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_ctl__parameterized3
(slaveRegDo_82,
s_di_o,
s_dclk_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ); |
output [15:0]slaveRegDo_82;
input [15:0]s_di_o;
input s_dclk_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [2:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire [15:0]s_di_o;
wire [15:0]slaveRegDo_82;
wire \xsdb_reg[15]_i_1__3_n_0 ;
LUT5 #(
.INIT(32'h00200000))
\xsdb_reg[15]_i_1__3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(\xsdb_reg[15]_i_1__3_n_0 ));
FDRE #(
.INIT(1'b1))
\xsdb_reg_reg[0]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[0]),
.Q(slaveRegDo_82[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[10]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[10]),
.Q(slaveRegDo_82[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[11]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[11]),
.Q(slaveRegDo_82[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[12]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[12]),
.Q(slaveRegDo_82[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[13]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[13]),
.Q(slaveRegDo_82[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[14]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[14]),
.Q(slaveRegDo_82[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[15]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[15]),
.Q(slaveRegDo_82[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[1]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[1]),
.Q(slaveRegDo_82[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[2]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[2]),
.Q(slaveRegDo_82[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[3]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[3]),
.Q(slaveRegDo_82[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[4]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[4]),
.Q(slaveRegDo_82[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[5]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[5]),
.Q(slaveRegDo_82[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[6]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[6]),
.Q(slaveRegDo_82[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[7]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[7]),
.Q(slaveRegDo_82[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[8]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[8]),
.Q(slaveRegDo_82[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\xsdb_reg_reg[9]
(.C(s_dclk_o),
.CE(\xsdb_reg[15]_i_1__3_n_0 ),
.D(s_di_o[9]),
.Q(slaveRegDo_82[9]),
.R(1'b0));
endmodule | 8 |
2,428 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s
(s_do_o,
E,
mu_config_cs_serial_output,
s_dclk_o,
mu_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_di_o);
output [15:0]s_do_o;
output [0:0]E;
output [0:0]mu_config_cs_serial_output;
input s_dclk_o;
input [0:0]mu_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input [1:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__1_n_0 ;
wire \current_state[3]_i_3__1_n_0 ;
wire \current_state[3]_i_4__1_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__1_n_0;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [1:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__1_n_0 ;
wire \shadow[10]_i_1__1_n_0 ;
wire \shadow[11]_i_1__1_n_0 ;
wire \shadow[12]_i_1__1_n_0 ;
wire \shadow[13]_i_1__1_n_0 ;
wire \shadow[14]_i_1__1_n_0 ;
wire \shadow[15]_i_1__1_n_0 ;
wire \shadow[1]_i_1__1_n_0 ;
wire \shadow[2]_i_1__1_n_0 ;
wire \shadow[3]_i_1__1_n_0 ;
wire \shadow[4]_i_1__1_n_0 ;
wire \shadow[5]_i_1__1_n_0 ;
wire \shadow[6]_i_1__1_n_0 ;
wire \shadow[7]_i_1__1_n_0 ;
wire \shadow[8]_i_1__1_n_0 ;
wire \shadow[9]_i_1__1_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__1_n_0;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__1
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__1
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__1
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__1
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__1
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__1
(.I0(\current_state[3]_i_4__1_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__1_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__1_n_0 ),
.O(next_state[0]));
LUT4 #(
.INIT(16'h0080))
\current_state[1]_i_1__1
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__1_n_0 ),
.I2(current_state[0]),
.I3(\current_state[3]_i_3__1_n_0 ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__1
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__1_n_0 ),
.I2(\current_state[3]_i_4__1_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__1
(.I0(\current_state[3]_i_2__1_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__1_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__1_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__1
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__1_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\current_state[3]_i_3__1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.O(\current_state[3]_i_3__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__1
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__1_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__1
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__1_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__1_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(mu_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__1
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__1
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__1
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__1
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__1
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__1
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__1_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__1
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__1
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__1
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__1
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__1
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__1
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__1
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__1
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__1
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__1
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__1_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__1
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__1_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__1_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__0
(.I0(serial_dout),
.I1(data_out_sel),
.I2(mu_config_cs_serial_input),
.O(mu_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s
(s_do_o,
E,
mu_config_cs_serial_output,
s_dclk_o,
mu_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
s_daddr_o,
\G_1PIPE_IFACE.s_daddr_r_reg[11] ,
s_di_o); |
output [15:0]s_do_o;
output [0:0]E;
output [0:0]mu_config_cs_serial_output;
input s_dclk_o;
input [0:0]mu_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input [1:0]s_daddr_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[11] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__1_n_0 ;
wire \current_state[3]_i_3__1_n_0 ;
wire \current_state[3]_i_4__1_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__1_n_0;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [1:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__1_n_0 ;
wire \shadow[10]_i_1__1_n_0 ;
wire \shadow[11]_i_1__1_n_0 ;
wire \shadow[12]_i_1__1_n_0 ;
wire \shadow[13]_i_1__1_n_0 ;
wire \shadow[14]_i_1__1_n_0 ;
wire \shadow[15]_i_1__1_n_0 ;
wire \shadow[1]_i_1__1_n_0 ;
wire \shadow[2]_i_1__1_n_0 ;
wire \shadow[3]_i_1__1_n_0 ;
wire \shadow[4]_i_1__1_n_0 ;
wire \shadow[5]_i_1__1_n_0 ;
wire \shadow[6]_i_1__1_n_0 ;
wire \shadow[7]_i_1__1_n_0 ;
wire \shadow[8]_i_1__1_n_0 ;
wire \shadow[9]_i_1__1_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__1_n_0;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__1
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__1
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__1
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__1
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__1
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__1
(.I0(\current_state[3]_i_4__1_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__1_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__1_n_0 ),
.O(next_state[0]));
LUT4 #(
.INIT(16'h0080))
\current_state[1]_i_1__1
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__1_n_0 ),
.I2(current_state[0]),
.I3(\current_state[3]_i_3__1_n_0 ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__1
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__1_n_0 ),
.I2(\current_state[3]_i_4__1_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__1
(.I0(\current_state[3]_i_2__1_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__1_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__1_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__1
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__1_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\current_state[3]_i_3__1
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[11] ),
.O(\current_state[3]_i_3__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__1
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__1_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__1
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__1_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__1_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(mu_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__1
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__1
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__1
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__1
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__1
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__1
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__1_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__1
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__1
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__1
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__1
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__1
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__1
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__1
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__1
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__1
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__1
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__1_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__1_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__1
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__1_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__1_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__0
(.I0(serial_dout),
.I1(data_out_sel),
.I2(mu_config_cs_serial_input),
.O(mu_config_cs_serial_output));
endmodule | 8 |
2,429 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized0
(s_do_o,
E,
mu_config_cs_serial_output,
s_dclk_o,
mu_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
s_daddr_o,
s_den_o,
s_di_o);
output [15:0]s_do_o;
output [0:0]E;
output [0:0]mu_config_cs_serial_output;
input s_dclk_o;
input [0:0]mu_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input [2:0]s_daddr_o;
input s_den_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__2_n_0 ;
wire \current_state[3]_i_3__2_n_0 ;
wire \current_state[3]_i_4__2_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__2_n_0;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__2_n_0 ;
wire \shadow[10]_i_1__2_n_0 ;
wire \shadow[11]_i_1__2_n_0 ;
wire \shadow[12]_i_1__2_n_0 ;
wire \shadow[13]_i_1__2_n_0 ;
wire \shadow[14]_i_1__2_n_0 ;
wire \shadow[15]_i_1__2_n_0 ;
wire \shadow[1]_i_1__2_n_0 ;
wire \shadow[2]_i_1__2_n_0 ;
wire \shadow[3]_i_1__2_n_0 ;
wire \shadow[4]_i_1__2_n_0 ;
wire \shadow[5]_i_1__2_n_0 ;
wire \shadow[6]_i_1__2_n_0 ;
wire \shadow[7]_i_1__2_n_0 ;
wire \shadow[8]_i_1__2_n_0 ;
wire \shadow[9]_i_1__2_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__2_n_0;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__2
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__2
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__2
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__2
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__2
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__2
(.I0(\current_state[3]_i_4__2_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__2_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__2_n_0 ),
.O(next_state[0]));
LUT4 #(
.INIT(16'h0080))
\current_state[1]_i_1__2
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__2_n_0 ),
.I2(current_state[0]),
.I3(\current_state[3]_i_3__2_n_0 ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__2
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__2_n_0 ),
.I2(\current_state[3]_i_4__2_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__2
(.I0(\current_state[3]_i_2__2_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__2_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__2_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__2
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__2_n_0 ));
LUT6 #(
.INIT(64'hFFFBFFFFFFFFFFFF))
\current_state[3]_i_3__2
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(s_den_o),
.I5(s_daddr_o[2]),
.O(\current_state[3]_i_3__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__2
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__2_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__2
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__2_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__2_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(mu_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__2
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__2
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__2
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__2
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__2
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__2
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__2_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__2
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__2
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__2
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__2
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__2
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__2
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__2
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__2
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__2
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__2
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__2_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__2
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__2_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__2_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__1
(.I0(serial_dout),
.I1(data_out_sel),
.I2(mu_config_cs_serial_input),
.O(mu_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized0
(s_do_o,
E,
mu_config_cs_serial_output,
s_dclk_o,
mu_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
s_daddr_o,
s_den_o,
s_di_o); |
output [15:0]s_do_o;
output [0:0]E;
output [0:0]mu_config_cs_serial_output;
input s_dclk_o;
input [0:0]mu_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input [2:0]s_daddr_o;
input s_den_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__2_n_0 ;
wire \current_state[3]_i_3__2_n_0 ;
wire \current_state[3]_i_4__2_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__2_n_0;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__2_n_0 ;
wire \shadow[10]_i_1__2_n_0 ;
wire \shadow[11]_i_1__2_n_0 ;
wire \shadow[12]_i_1__2_n_0 ;
wire \shadow[13]_i_1__2_n_0 ;
wire \shadow[14]_i_1__2_n_0 ;
wire \shadow[15]_i_1__2_n_0 ;
wire \shadow[1]_i_1__2_n_0 ;
wire \shadow[2]_i_1__2_n_0 ;
wire \shadow[3]_i_1__2_n_0 ;
wire \shadow[4]_i_1__2_n_0 ;
wire \shadow[5]_i_1__2_n_0 ;
wire \shadow[6]_i_1__2_n_0 ;
wire \shadow[7]_i_1__2_n_0 ;
wire \shadow[8]_i_1__2_n_0 ;
wire \shadow[9]_i_1__2_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__2_n_0;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__2
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__2
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__2
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__2
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__2
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__2
(.I0(\current_state[3]_i_4__2_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__2_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__2_n_0 ),
.O(next_state[0]));
LUT4 #(
.INIT(16'h0080))
\current_state[1]_i_1__2
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__2_n_0 ),
.I2(current_state[0]),
.I3(\current_state[3]_i_3__2_n_0 ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__2
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__2_n_0 ),
.I2(\current_state[3]_i_4__2_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__2
(.I0(\current_state[3]_i_2__2_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__2_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__2_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__2
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__2_n_0 ));
LUT6 #(
.INIT(64'hFFFBFFFFFFFFFFFF))
\current_state[3]_i_3__2
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(s_den_o),
.I5(s_daddr_o[2]),
.O(\current_state[3]_i_3__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__2
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__2_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__2
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__2_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__2_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(mu_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__2
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__2
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__2
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__2
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__2
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__2
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__2_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__2
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__2
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__2
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__2
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__2
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__2
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__2
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__2
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__2
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__2
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__2_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__2_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__2
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__2_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__2_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__1
(.I0(serial_dout),
.I1(data_out_sel),
.I2(mu_config_cs_serial_input),
.O(mu_config_cs_serial_output));
endmodule | 8 |
2,430 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized1
(s_do_o,
E,
mu_config_cs_serial_output,
s_dclk_o,
mu_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
s_daddr_o,
s_den_o,
s_di_o);
output [15:0]s_do_o;
output [0:0]E;
output [0:0]mu_config_cs_serial_output;
input s_dclk_o;
input [0:0]mu_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input [2:0]s_daddr_o;
input s_den_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__3_n_0 ;
wire \current_state[3]_i_3__3_n_0 ;
wire \current_state[3]_i_4__3_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__3_n_0;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__3_n_0 ;
wire \shadow[10]_i_1__3_n_0 ;
wire \shadow[11]_i_1__3_n_0 ;
wire \shadow[12]_i_1__3_n_0 ;
wire \shadow[13]_i_1__3_n_0 ;
wire \shadow[14]_i_1__3_n_0 ;
wire \shadow[15]_i_1__3_n_0 ;
wire \shadow[1]_i_1__3_n_0 ;
wire \shadow[2]_i_1__3_n_0 ;
wire \shadow[3]_i_1__3_n_0 ;
wire \shadow[4]_i_1__3_n_0 ;
wire \shadow[5]_i_1__3_n_0 ;
wire \shadow[6]_i_1__3_n_0 ;
wire \shadow[7]_i_1__3_n_0 ;
wire \shadow[8]_i_1__3_n_0 ;
wire \shadow[9]_i_1__3_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__3_n_0;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__3
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__3
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__3
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__3
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__3
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__3
(.I0(\current_state[3]_i_4__3_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__3_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__3_n_0 ),
.O(next_state[0]));
LUT4 #(
.INIT(16'h0080))
\current_state[1]_i_1__3
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__3_n_0 ),
.I2(current_state[0]),
.I3(\current_state[3]_i_3__3_n_0 ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__3
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__3_n_0 ),
.I2(\current_state[3]_i_4__3_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__3
(.I0(\current_state[3]_i_2__3_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__3_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__3_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__3
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__3_n_0 ));
LUT6 #(
.INIT(64'hFFFEFFFFFFFFFFFF))
\current_state[3]_i_3__3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(s_den_o),
.I5(s_daddr_o[2]),
.O(\current_state[3]_i_3__3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__3
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__3_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__3
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__3_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__3_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(mu_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__3
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__3
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__3
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__3
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__3
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__3
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__3_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__3
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__3
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__3
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__3
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__3
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__3
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__3
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__3
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__3
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__3
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__3_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__3
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__3_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__3_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__2
(.I0(serial_dout),
.I1(data_out_sel),
.I2(mu_config_cs_serial_input),
.O(mu_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized1
(s_do_o,
E,
mu_config_cs_serial_output,
s_dclk_o,
mu_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[0] ,
s_daddr_o,
s_den_o,
s_di_o); |
output [15:0]s_do_o;
output [0:0]E;
output [0:0]mu_config_cs_serial_output;
input s_dclk_o;
input [0:0]mu_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
input [2:0]s_daddr_o;
input s_den_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[0] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__3_n_0 ;
wire \current_state[3]_i_3__3_n_0 ;
wire \current_state[3]_i_4__3_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__3_n_0;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [2:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__3_n_0 ;
wire \shadow[10]_i_1__3_n_0 ;
wire \shadow[11]_i_1__3_n_0 ;
wire \shadow[12]_i_1__3_n_0 ;
wire \shadow[13]_i_1__3_n_0 ;
wire \shadow[14]_i_1__3_n_0 ;
wire \shadow[15]_i_1__3_n_0 ;
wire \shadow[1]_i_1__3_n_0 ;
wire \shadow[2]_i_1__3_n_0 ;
wire \shadow[3]_i_1__3_n_0 ;
wire \shadow[4]_i_1__3_n_0 ;
wire \shadow[5]_i_1__3_n_0 ;
wire \shadow[6]_i_1__3_n_0 ;
wire \shadow[7]_i_1__3_n_0 ;
wire \shadow[8]_i_1__3_n_0 ;
wire \shadow[9]_i_1__3_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__3_n_0;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__3
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__3
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__3
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__3
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__3
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__3
(.I0(\current_state[3]_i_4__3_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__3_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__3_n_0 ),
.O(next_state[0]));
LUT4 #(
.INIT(16'h0080))
\current_state[1]_i_1__3
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__3_n_0 ),
.I2(current_state[0]),
.I3(\current_state[3]_i_3__3_n_0 ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__3
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__3_n_0 ),
.I2(\current_state[3]_i_4__3_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__3
(.I0(\current_state[3]_i_2__3_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__3_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__3_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__3
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__3_n_0 ));
LUT6 #(
.INIT(64'hFFFEFFFFFFFFFFFF))
\current_state[3]_i_3__3
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[0] ),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[0]),
.I4(s_den_o),
.I5(s_daddr_o[2]),
.O(\current_state[3]_i_3__3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__3
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__3_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__3
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__3_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__3_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(mu_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__3
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__3
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__3
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__3
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__3
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__3
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__3_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__3
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__3
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__3
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__3
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__3
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__3
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__3
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__3
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__3
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__3
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__3_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__3_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__3
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__3_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__3_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__2
(.I0(serial_dout),
.I1(data_out_sel),
.I2(mu_config_cs_serial_input),
.O(mu_config_cs_serial_output));
endmodule | 8 |
2,431 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized10
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
s_di_o);
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__12_n_0 ;
wire \current_state[3]_i_3__12_n_0 ;
wire \current_state[3]_i_4__12_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__12_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__12_n_0 ;
wire \shadow[10]_i_1__12_n_0 ;
wire \shadow[11]_i_1__12_n_0 ;
wire \shadow[12]_i_1__12_n_0 ;
wire \shadow[13]_i_1__12_n_0 ;
wire \shadow[14]_i_1__12_n_0 ;
wire \shadow[15]_i_1__12_n_0 ;
wire \shadow[1]_i_1__12_n_0 ;
wire \shadow[2]_i_1__12_n_0 ;
wire \shadow[3]_i_1__12_n_0 ;
wire \shadow[4]_i_1__12_n_0 ;
wire \shadow[5]_i_1__12_n_0 ;
wire \shadow[6]_i_1__12_n_0 ;
wire \shadow[7]_i_1__12_n_0 ;
wire \shadow[8]_i_1__12_n_0 ;
wire \shadow[9]_i_1__12_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__12_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__12
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__12
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__12
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__12
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__12
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__12
(.I0(\current_state[3]_i_4__12_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__12_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__12_n_0 ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__12
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__12_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__12
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__12_n_0 ),
.I2(\current_state[3]_i_4__12_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__12
(.I0(\current_state[3]_i_2__12_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__12_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__12_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__12
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT2 #(
.INIT(4'hE))
\current_state[3]_i_3__12
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__12
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__12_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__12
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__12_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__12_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__12
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__12
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__12
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__12
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__12
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__12
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__12_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__12
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__12
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__12
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__12
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__12
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__12
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__12
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__12
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__12
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__12
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__12_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__12
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__12_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__12_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__11
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized10
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
s_di_o); |
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__12_n_0 ;
wire \current_state[3]_i_3__12_n_0 ;
wire \current_state[3]_i_4__12_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__12_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__12_n_0 ;
wire \shadow[10]_i_1__12_n_0 ;
wire \shadow[11]_i_1__12_n_0 ;
wire \shadow[12]_i_1__12_n_0 ;
wire \shadow[13]_i_1__12_n_0 ;
wire \shadow[14]_i_1__12_n_0 ;
wire \shadow[15]_i_1__12_n_0 ;
wire \shadow[1]_i_1__12_n_0 ;
wire \shadow[2]_i_1__12_n_0 ;
wire \shadow[3]_i_1__12_n_0 ;
wire \shadow[4]_i_1__12_n_0 ;
wire \shadow[5]_i_1__12_n_0 ;
wire \shadow[6]_i_1__12_n_0 ;
wire \shadow[7]_i_1__12_n_0 ;
wire \shadow[8]_i_1__12_n_0 ;
wire \shadow[9]_i_1__12_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__12_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__12
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__12
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__12
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__12
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__12
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__12
(.I0(\current_state[3]_i_4__12_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__12_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__12_n_0 ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__12
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__12_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__12
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__12_n_0 ),
.I2(\current_state[3]_i_4__12_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__12
(.I0(\current_state[3]_i_2__12_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__12_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__12_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__12
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT2 #(
.INIT(4'hE))
\current_state[3]_i_3__12
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__12
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__12_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__12
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__12_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__12_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__12
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__12
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__12
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__12
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__12
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__12
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__12_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__12
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__12
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__12
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__12
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__12
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__12
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__12
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__12
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__12
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__12_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__12
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__12_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__12_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__12
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__12_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__12_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__11
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | 8 |
2,432 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized11
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
s_di_o);
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__13_n_0 ;
wire \current_state[3]_i_3__13_n_0 ;
wire \current_state[3]_i_4__13_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__13_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__13_n_0 ;
wire \shadow[10]_i_1__13_n_0 ;
wire \shadow[11]_i_1__13_n_0 ;
wire \shadow[12]_i_1__13_n_0 ;
wire \shadow[13]_i_1__13_n_0 ;
wire \shadow[14]_i_1__13_n_0 ;
wire \shadow[15]_i_1__13_n_0 ;
wire \shadow[1]_i_1__13_n_0 ;
wire \shadow[2]_i_1__13_n_0 ;
wire \shadow[3]_i_1__13_n_0 ;
wire \shadow[4]_i_1__13_n_0 ;
wire \shadow[5]_i_1__13_n_0 ;
wire \shadow[6]_i_1__13_n_0 ;
wire \shadow[7]_i_1__13_n_0 ;
wire \shadow[8]_i_1__13_n_0 ;
wire \shadow[9]_i_1__13_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__13_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__13
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__13
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__13
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__13
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair152" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__13
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__13
(.I0(\current_state[3]_i_4__13_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__13_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__13_n_0 ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair151" *)
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__13
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__13_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__13
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__13_n_0 ),
.I2(\current_state[3]_i_4__13_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__13
(.I0(\current_state[3]_i_2__13_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__13_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__13_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair152" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__13
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__13_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair151" *)
LUT2 #(
.INIT(4'hE))
\current_state[3]_i_3__13
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__13_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair153" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__13
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__13_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair153" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__13
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__13_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__13_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__13
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__13
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__13
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__13
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__13
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__13
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__13_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__13
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__13
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__13
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__13
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__13
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__13
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__13
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__13
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__13
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__13
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__13_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__13
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__13_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__13_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__12
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized11
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
s_di_o); |
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__13_n_0 ;
wire \current_state[3]_i_3__13_n_0 ;
wire \current_state[3]_i_4__13_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__13_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__13_n_0 ;
wire \shadow[10]_i_1__13_n_0 ;
wire \shadow[11]_i_1__13_n_0 ;
wire \shadow[12]_i_1__13_n_0 ;
wire \shadow[13]_i_1__13_n_0 ;
wire \shadow[14]_i_1__13_n_0 ;
wire \shadow[15]_i_1__13_n_0 ;
wire \shadow[1]_i_1__13_n_0 ;
wire \shadow[2]_i_1__13_n_0 ;
wire \shadow[3]_i_1__13_n_0 ;
wire \shadow[4]_i_1__13_n_0 ;
wire \shadow[5]_i_1__13_n_0 ;
wire \shadow[6]_i_1__13_n_0 ;
wire \shadow[7]_i_1__13_n_0 ;
wire \shadow[8]_i_1__13_n_0 ;
wire \shadow[9]_i_1__13_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__13_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__13
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__13
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair154" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__13
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__13
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair152" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__13
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__13
(.I0(\current_state[3]_i_4__13_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__13_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__13_n_0 ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair151" *)
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__13
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__13_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__13
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__13_n_0 ),
.I2(\current_state[3]_i_4__13_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__13
(.I0(\current_state[3]_i_2__13_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__13_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__13_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair152" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__13
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__13_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair151" *)
LUT2 #(
.INIT(4'hE))
\current_state[3]_i_3__13
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__13_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair153" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__13
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__13_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair153" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__13
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__13_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__13_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__13
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__13
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__13
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__13
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__13
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__13
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__13_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__13
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__13
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__13
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__13
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__13
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__13
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__13
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__13
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__13
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__13_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__13
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__13_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__13_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__13
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__13_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__13_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__12
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | 8 |
2,433 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized12
(\slaveRegDo_mux_5_reg[15] ,
\slaveRegDo_mux_5_reg[14] ,
\slaveRegDo_mux_5_reg[13] ,
\slaveRegDo_mux_5_reg[12] ,
\slaveRegDo_mux_5_reg[11] ,
\slaveRegDo_mux_5_reg[10] ,
\slaveRegDo_mux_5_reg[9] ,
\slaveRegDo_mux_5_reg[8] ,
\slaveRegDo_mux_5_reg[7] ,
\slaveRegDo_mux_5_reg[6] ,
\slaveRegDo_mux_5_reg[5] ,
\slaveRegDo_mux_5_reg[4] ,
\slaveRegDo_mux_5_reg[3] ,
\slaveRegDo_mux_5_reg[2] ,
\slaveRegDo_mux_5_reg[1] ,
\slaveRegDo_mux_5_reg[0] ,
E,
tc_config_cs_serial_output,
s_daddr_o,
\parallel_dout_reg[15]_0 ,
s_do_o,
\parallel_dout_reg[15]_1 ,
\parallel_dout_reg[15]_2 ,
\parallel_dout_reg[14]_0 ,
\parallel_dout_reg[13]_0 ,
\parallel_dout_reg[12]_0 ,
\parallel_dout_reg[11]_0 ,
\parallel_dout_reg[10]_0 ,
\parallel_dout_reg[9]_0 ,
\parallel_dout_reg[8]_0 ,
\parallel_dout_reg[7]_0 ,
\parallel_dout_reg[6]_0 ,
\parallel_dout_reg[5]_0 ,
\parallel_dout_reg[4]_0 ,
\parallel_dout_reg[3]_0 ,
\parallel_dout_reg[2]_0 ,
\parallel_dout_reg[1]_0 ,
\parallel_dout_reg[0]_0 ,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
s_den_o,
s_di_o);
output \slaveRegDo_mux_5_reg[15] ;
output \slaveRegDo_mux_5_reg[14] ;
output \slaveRegDo_mux_5_reg[13] ;
output \slaveRegDo_mux_5_reg[12] ;
output \slaveRegDo_mux_5_reg[11] ;
output \slaveRegDo_mux_5_reg[10] ;
output \slaveRegDo_mux_5_reg[9] ;
output \slaveRegDo_mux_5_reg[8] ;
output \slaveRegDo_mux_5_reg[7] ;
output \slaveRegDo_mux_5_reg[6] ;
output \slaveRegDo_mux_5_reg[5] ;
output \slaveRegDo_mux_5_reg[4] ;
output \slaveRegDo_mux_5_reg[3] ;
output \slaveRegDo_mux_5_reg[2] ;
output \slaveRegDo_mux_5_reg[1] ;
output \slaveRegDo_mux_5_reg[0] ;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input [5:0]s_daddr_o;
input \parallel_dout_reg[15]_0 ;
input [15:0]s_do_o;
input [15:0]\parallel_dout_reg[15]_1 ;
input [15:0]\parallel_dout_reg[15]_2 ;
input \parallel_dout_reg[14]_0 ;
input \parallel_dout_reg[13]_0 ;
input \parallel_dout_reg[12]_0 ;
input \parallel_dout_reg[11]_0 ;
input \parallel_dout_reg[10]_0 ;
input \parallel_dout_reg[9]_0 ;
input \parallel_dout_reg[8]_0 ;
input \parallel_dout_reg[7]_0 ;
input \parallel_dout_reg[6]_0 ;
input \parallel_dout_reg[5]_0 ;
input \parallel_dout_reg[4]_0 ;
input \parallel_dout_reg[3]_0 ;
input \parallel_dout_reg[2]_0 ;
input \parallel_dout_reg[1]_0 ;
input \parallel_dout_reg[0]_0 ;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input s_den_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__14_n_0 ;
wire \current_state[3]_i_3__14_n_0 ;
wire \current_state[3]_i_4__14_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__14_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire \parallel_dout_reg[0]_0 ;
wire \parallel_dout_reg[10]_0 ;
wire \parallel_dout_reg[11]_0 ;
wire \parallel_dout_reg[12]_0 ;
wire \parallel_dout_reg[13]_0 ;
wire \parallel_dout_reg[14]_0 ;
wire \parallel_dout_reg[15]_0 ;
wire [15:0]\parallel_dout_reg[15]_1 ;
wire [15:0]\parallel_dout_reg[15]_2 ;
wire \parallel_dout_reg[1]_0 ;
wire \parallel_dout_reg[2]_0 ;
wire \parallel_dout_reg[3]_0 ;
wire \parallel_dout_reg[4]_0 ;
wire \parallel_dout_reg[5]_0 ;
wire \parallel_dout_reg[6]_0 ;
wire \parallel_dout_reg[7]_0 ;
wire \parallel_dout_reg[8]_0 ;
wire \parallel_dout_reg[9]_0 ;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__14_n_0 ;
wire \shadow[10]_i_1__14_n_0 ;
wire \shadow[11]_i_1__14_n_0 ;
wire \shadow[12]_i_1__14_n_0 ;
wire \shadow[13]_i_1__14_n_0 ;
wire \shadow[14]_i_1__14_n_0 ;
wire \shadow[15]_i_1__14_n_0 ;
wire \shadow[1]_i_1__14_n_0 ;
wire \shadow[2]_i_1__14_n_0 ;
wire \shadow[3]_i_1__14_n_0 ;
wire \shadow[4]_i_1__14_n_0 ;
wire \shadow[5]_i_1__14_n_0 ;
wire \shadow[6]_i_1__14_n_0 ;
wire \shadow[7]_i_1__14_n_0 ;
wire \shadow[8]_i_1__14_n_0 ;
wire \shadow[9]_i_1__14_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__14_n_0;
wire \slaveRegDo_mux_5[0]_i_12_n_0 ;
wire \slaveRegDo_mux_5[10]_i_12_n_0 ;
wire \slaveRegDo_mux_5[11]_i_12_n_0 ;
wire \slaveRegDo_mux_5[12]_i_12_n_0 ;
wire \slaveRegDo_mux_5[13]_i_12_n_0 ;
wire \slaveRegDo_mux_5[14]_i_12_n_0 ;
wire \slaveRegDo_mux_5[15]_i_12_n_0 ;
wire \slaveRegDo_mux_5[1]_i_12_n_0 ;
wire \slaveRegDo_mux_5[2]_i_12_n_0 ;
wire \slaveRegDo_mux_5[3]_i_12_n_0 ;
wire \slaveRegDo_mux_5[4]_i_12_n_0 ;
wire \slaveRegDo_mux_5[5]_i_12_n_0 ;
wire \slaveRegDo_mux_5[6]_i_12_n_0 ;
wire \slaveRegDo_mux_5[7]_i_12_n_0 ;
wire \slaveRegDo_mux_5[8]_i_12_n_0 ;
wire \slaveRegDo_mux_5[9]_i_12_n_0 ;
wire \slaveRegDo_mux_5_reg[0] ;
wire \slaveRegDo_mux_5_reg[10] ;
wire \slaveRegDo_mux_5_reg[11] ;
wire \slaveRegDo_mux_5_reg[12] ;
wire \slaveRegDo_mux_5_reg[13] ;
wire \slaveRegDo_mux_5_reg[14] ;
wire \slaveRegDo_mux_5_reg[15] ;
wire \slaveRegDo_mux_5_reg[1] ;
wire \slaveRegDo_mux_5_reg[2] ;
wire \slaveRegDo_mux_5_reg[3] ;
wire \slaveRegDo_mux_5_reg[4] ;
wire \slaveRegDo_mux_5_reg[5] ;
wire \slaveRegDo_mux_5_reg[6] ;
wire \slaveRegDo_mux_5_reg[7] ;
wire \slaveRegDo_mux_5_reg[8] ;
wire \slaveRegDo_mux_5_reg[9] ;
wire [15:0]\slaveRegDo_tcConfig[5123]_13 ;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__14
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair163" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__14
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair163" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__14
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__14
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair161" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__14
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__14
(.I0(\current_state[3]_i_4__14_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__14_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__14_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__14
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__14_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__14
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__14_n_0 ),
.I2(\current_state[3]_i_4__14_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__14
(.I0(\current_state[3]_i_2__14_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__14_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__14_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair161" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__14
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__14_n_0 ));
LUT6 #(
.INIT(64'hFFBFFFFFFFFFFFFF))
\current_state[3]_i_3__14
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I2(s_daddr_o[3]),
.I3(s_daddr_o[4]),
.I4(s_den_o),
.I5(s_daddr_o[5]),
.O(\current_state[3]_i_3__14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair162" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__14
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__14_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair162" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__14
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__14_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__14_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [1]),
.Q(\slaveRegDo_tcConfig[5123]_13 [0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [11]),
.Q(\slaveRegDo_tcConfig[5123]_13 [10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [12]),
.Q(\slaveRegDo_tcConfig[5123]_13 [11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [13]),
.Q(\slaveRegDo_tcConfig[5123]_13 [12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [14]),
.Q(\slaveRegDo_tcConfig[5123]_13 [13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [15]),
.Q(\slaveRegDo_tcConfig[5123]_13 [14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(\slaveRegDo_tcConfig[5123]_13 [15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [2]),
.Q(\slaveRegDo_tcConfig[5123]_13 [1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [3]),
.Q(\slaveRegDo_tcConfig[5123]_13 [2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [4]),
.Q(\slaveRegDo_tcConfig[5123]_13 [3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [5]),
.Q(\slaveRegDo_tcConfig[5123]_13 [4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [6]),
.Q(\slaveRegDo_tcConfig[5123]_13 [5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [7]),
.Q(\slaveRegDo_tcConfig[5123]_13 [6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [8]),
.Q(\slaveRegDo_tcConfig[5123]_13 [7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [9]),
.Q(\slaveRegDo_tcConfig[5123]_13 [8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [10]),
.Q(\slaveRegDo_tcConfig[5123]_13 [9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__14
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__14
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__14
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__14
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__14
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__14
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__14_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__14
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__14
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__14
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__14
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__14
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__14
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__14
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__14
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__14
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__14
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__14_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__14
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__14_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__14_n_0),
.Q(E),
.R(1'b0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[0]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [0]),
.I1(s_do_o[0]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [0]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [0]),
.O(\slaveRegDo_mux_5[0]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[10]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [10]),
.I1(s_do_o[10]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [10]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [10]),
.O(\slaveRegDo_mux_5[10]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[11]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [11]),
.I1(s_do_o[11]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [11]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [11]),
.O(\slaveRegDo_mux_5[11]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[12]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [12]),
.I1(s_do_o[12]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [12]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [12]),
.O(\slaveRegDo_mux_5[12]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[13]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [13]),
.I1(s_do_o[13]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [13]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [13]),
.O(\slaveRegDo_mux_5[13]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[14]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [14]),
.I1(s_do_o[14]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [14]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [14]),
.O(\slaveRegDo_mux_5[14]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[15]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [15]),
.I1(s_do_o[15]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [15]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [15]),
.O(\slaveRegDo_mux_5[15]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[1]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [1]),
.I1(s_do_o[1]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [1]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [1]),
.O(\slaveRegDo_mux_5[1]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[2]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [2]),
.I1(s_do_o[2]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [2]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [2]),
.O(\slaveRegDo_mux_5[2]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[3]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [3]),
.I1(s_do_o[3]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [3]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [3]),
.O(\slaveRegDo_mux_5[3]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[4]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [4]),
.I1(s_do_o[4]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [4]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [4]),
.O(\slaveRegDo_mux_5[4]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[5]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [5]),
.I1(s_do_o[5]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [5]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [5]),
.O(\slaveRegDo_mux_5[5]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[6]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [6]),
.I1(s_do_o[6]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [6]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [6]),
.O(\slaveRegDo_mux_5[6]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[7]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [7]),
.I1(s_do_o[7]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [7]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [7]),
.O(\slaveRegDo_mux_5[7]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[8]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [8]),
.I1(s_do_o[8]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [8]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [8]),
.O(\slaveRegDo_mux_5[8]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[9]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [9]),
.I1(s_do_o[9]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [9]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [9]),
.O(\slaveRegDo_mux_5[9]_i_12_n_0 ));
MUXF7 \slaveRegDo_mux_5_reg[0]_i_5
(.I0(\slaveRegDo_mux_5[0]_i_12_n_0 ),
.I1(\parallel_dout_reg[0]_0 ),
.O(\slaveRegDo_mux_5_reg[0] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[10]_i_5
(.I0(\slaveRegDo_mux_5[10]_i_12_n_0 ),
.I1(\parallel_dout_reg[10]_0 ),
.O(\slaveRegDo_mux_5_reg[10] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[11]_i_5
(.I0(\slaveRegDo_mux_5[11]_i_12_n_0 ),
.I1(\parallel_dout_reg[11]_0 ),
.O(\slaveRegDo_mux_5_reg[11] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[12]_i_5
(.I0(\slaveRegDo_mux_5[12]_i_12_n_0 ),
.I1(\parallel_dout_reg[12]_0 ),
.O(\slaveRegDo_mux_5_reg[12] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[13]_i_5
(.I0(\slaveRegDo_mux_5[13]_i_12_n_0 ),
.I1(\parallel_dout_reg[13]_0 ),
.O(\slaveRegDo_mux_5_reg[13] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[14]_i_5
(.I0(\slaveRegDo_mux_5[14]_i_12_n_0 ),
.I1(\parallel_dout_reg[14]_0 ),
.O(\slaveRegDo_mux_5_reg[14] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[15]_i_5
(.I0(\slaveRegDo_mux_5[15]_i_12_n_0 ),
.I1(\parallel_dout_reg[15]_0 ),
.O(\slaveRegDo_mux_5_reg[15] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[1]_i_5
(.I0(\slaveRegDo_mux_5[1]_i_12_n_0 ),
.I1(\parallel_dout_reg[1]_0 ),
.O(\slaveRegDo_mux_5_reg[1] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[2]_i_5
(.I0(\slaveRegDo_mux_5[2]_i_12_n_0 ),
.I1(\parallel_dout_reg[2]_0 ),
.O(\slaveRegDo_mux_5_reg[2] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[3]_i_5
(.I0(\slaveRegDo_mux_5[3]_i_12_n_0 ),
.I1(\parallel_dout_reg[3]_0 ),
.O(\slaveRegDo_mux_5_reg[3] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[4]_i_5
(.I0(\slaveRegDo_mux_5[4]_i_12_n_0 ),
.I1(\parallel_dout_reg[4]_0 ),
.O(\slaveRegDo_mux_5_reg[4] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[5]_i_5
(.I0(\slaveRegDo_mux_5[5]_i_12_n_0 ),
.I1(\parallel_dout_reg[5]_0 ),
.O(\slaveRegDo_mux_5_reg[5] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[6]_i_5
(.I0(\slaveRegDo_mux_5[6]_i_12_n_0 ),
.I1(\parallel_dout_reg[6]_0 ),
.O(\slaveRegDo_mux_5_reg[6] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[7]_i_5
(.I0(\slaveRegDo_mux_5[7]_i_12_n_0 ),
.I1(\parallel_dout_reg[7]_0 ),
.O(\slaveRegDo_mux_5_reg[7] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[8]_i_5
(.I0(\slaveRegDo_mux_5[8]_i_12_n_0 ),
.I1(\parallel_dout_reg[8]_0 ),
.O(\slaveRegDo_mux_5_reg[8] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[9]_i_5
(.I0(\slaveRegDo_mux_5[9]_i_12_n_0 ),
.I1(\parallel_dout_reg[9]_0 ),
.O(\slaveRegDo_mux_5_reg[9] ),
.S(s_daddr_o[2]));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__13
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized12
(\slaveRegDo_mux_5_reg[15] ,
\slaveRegDo_mux_5_reg[14] ,
\slaveRegDo_mux_5_reg[13] ,
\slaveRegDo_mux_5_reg[12] ,
\slaveRegDo_mux_5_reg[11] ,
\slaveRegDo_mux_5_reg[10] ,
\slaveRegDo_mux_5_reg[9] ,
\slaveRegDo_mux_5_reg[8] ,
\slaveRegDo_mux_5_reg[7] ,
\slaveRegDo_mux_5_reg[6] ,
\slaveRegDo_mux_5_reg[5] ,
\slaveRegDo_mux_5_reg[4] ,
\slaveRegDo_mux_5_reg[3] ,
\slaveRegDo_mux_5_reg[2] ,
\slaveRegDo_mux_5_reg[1] ,
\slaveRegDo_mux_5_reg[0] ,
E,
tc_config_cs_serial_output,
s_daddr_o,
\parallel_dout_reg[15]_0 ,
s_do_o,
\parallel_dout_reg[15]_1 ,
\parallel_dout_reg[15]_2 ,
\parallel_dout_reg[14]_0 ,
\parallel_dout_reg[13]_0 ,
\parallel_dout_reg[12]_0 ,
\parallel_dout_reg[11]_0 ,
\parallel_dout_reg[10]_0 ,
\parallel_dout_reg[9]_0 ,
\parallel_dout_reg[8]_0 ,
\parallel_dout_reg[7]_0 ,
\parallel_dout_reg[6]_0 ,
\parallel_dout_reg[5]_0 ,
\parallel_dout_reg[4]_0 ,
\parallel_dout_reg[3]_0 ,
\parallel_dout_reg[2]_0 ,
\parallel_dout_reg[1]_0 ,
\parallel_dout_reg[0]_0 ,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
s_den_o,
s_di_o); |
output \slaveRegDo_mux_5_reg[15] ;
output \slaveRegDo_mux_5_reg[14] ;
output \slaveRegDo_mux_5_reg[13] ;
output \slaveRegDo_mux_5_reg[12] ;
output \slaveRegDo_mux_5_reg[11] ;
output \slaveRegDo_mux_5_reg[10] ;
output \slaveRegDo_mux_5_reg[9] ;
output \slaveRegDo_mux_5_reg[8] ;
output \slaveRegDo_mux_5_reg[7] ;
output \slaveRegDo_mux_5_reg[6] ;
output \slaveRegDo_mux_5_reg[5] ;
output \slaveRegDo_mux_5_reg[4] ;
output \slaveRegDo_mux_5_reg[3] ;
output \slaveRegDo_mux_5_reg[2] ;
output \slaveRegDo_mux_5_reg[1] ;
output \slaveRegDo_mux_5_reg[0] ;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input [5:0]s_daddr_o;
input \parallel_dout_reg[15]_0 ;
input [15:0]s_do_o;
input [15:0]\parallel_dout_reg[15]_1 ;
input [15:0]\parallel_dout_reg[15]_2 ;
input \parallel_dout_reg[14]_0 ;
input \parallel_dout_reg[13]_0 ;
input \parallel_dout_reg[12]_0 ;
input \parallel_dout_reg[11]_0 ;
input \parallel_dout_reg[10]_0 ;
input \parallel_dout_reg[9]_0 ;
input \parallel_dout_reg[8]_0 ;
input \parallel_dout_reg[7]_0 ;
input \parallel_dout_reg[6]_0 ;
input \parallel_dout_reg[5]_0 ;
input \parallel_dout_reg[4]_0 ;
input \parallel_dout_reg[3]_0 ;
input \parallel_dout_reg[2]_0 ;
input \parallel_dout_reg[1]_0 ;
input \parallel_dout_reg[0]_0 ;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input s_den_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__14_n_0 ;
wire \current_state[3]_i_3__14_n_0 ;
wire \current_state[3]_i_4__14_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__14_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire \parallel_dout_reg[0]_0 ;
wire \parallel_dout_reg[10]_0 ;
wire \parallel_dout_reg[11]_0 ;
wire \parallel_dout_reg[12]_0 ;
wire \parallel_dout_reg[13]_0 ;
wire \parallel_dout_reg[14]_0 ;
wire \parallel_dout_reg[15]_0 ;
wire [15:0]\parallel_dout_reg[15]_1 ;
wire [15:0]\parallel_dout_reg[15]_2 ;
wire \parallel_dout_reg[1]_0 ;
wire \parallel_dout_reg[2]_0 ;
wire \parallel_dout_reg[3]_0 ;
wire \parallel_dout_reg[4]_0 ;
wire \parallel_dout_reg[5]_0 ;
wire \parallel_dout_reg[6]_0 ;
wire \parallel_dout_reg[7]_0 ;
wire \parallel_dout_reg[8]_0 ;
wire \parallel_dout_reg[9]_0 ;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__14_n_0 ;
wire \shadow[10]_i_1__14_n_0 ;
wire \shadow[11]_i_1__14_n_0 ;
wire \shadow[12]_i_1__14_n_0 ;
wire \shadow[13]_i_1__14_n_0 ;
wire \shadow[14]_i_1__14_n_0 ;
wire \shadow[15]_i_1__14_n_0 ;
wire \shadow[1]_i_1__14_n_0 ;
wire \shadow[2]_i_1__14_n_0 ;
wire \shadow[3]_i_1__14_n_0 ;
wire \shadow[4]_i_1__14_n_0 ;
wire \shadow[5]_i_1__14_n_0 ;
wire \shadow[6]_i_1__14_n_0 ;
wire \shadow[7]_i_1__14_n_0 ;
wire \shadow[8]_i_1__14_n_0 ;
wire \shadow[9]_i_1__14_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__14_n_0;
wire \slaveRegDo_mux_5[0]_i_12_n_0 ;
wire \slaveRegDo_mux_5[10]_i_12_n_0 ;
wire \slaveRegDo_mux_5[11]_i_12_n_0 ;
wire \slaveRegDo_mux_5[12]_i_12_n_0 ;
wire \slaveRegDo_mux_5[13]_i_12_n_0 ;
wire \slaveRegDo_mux_5[14]_i_12_n_0 ;
wire \slaveRegDo_mux_5[15]_i_12_n_0 ;
wire \slaveRegDo_mux_5[1]_i_12_n_0 ;
wire \slaveRegDo_mux_5[2]_i_12_n_0 ;
wire \slaveRegDo_mux_5[3]_i_12_n_0 ;
wire \slaveRegDo_mux_5[4]_i_12_n_0 ;
wire \slaveRegDo_mux_5[5]_i_12_n_0 ;
wire \slaveRegDo_mux_5[6]_i_12_n_0 ;
wire \slaveRegDo_mux_5[7]_i_12_n_0 ;
wire \slaveRegDo_mux_5[8]_i_12_n_0 ;
wire \slaveRegDo_mux_5[9]_i_12_n_0 ;
wire \slaveRegDo_mux_5_reg[0] ;
wire \slaveRegDo_mux_5_reg[10] ;
wire \slaveRegDo_mux_5_reg[11] ;
wire \slaveRegDo_mux_5_reg[12] ;
wire \slaveRegDo_mux_5_reg[13] ;
wire \slaveRegDo_mux_5_reg[14] ;
wire \slaveRegDo_mux_5_reg[15] ;
wire \slaveRegDo_mux_5_reg[1] ;
wire \slaveRegDo_mux_5_reg[2] ;
wire \slaveRegDo_mux_5_reg[3] ;
wire \slaveRegDo_mux_5_reg[4] ;
wire \slaveRegDo_mux_5_reg[5] ;
wire \slaveRegDo_mux_5_reg[6] ;
wire \slaveRegDo_mux_5_reg[7] ;
wire \slaveRegDo_mux_5_reg[8] ;
wire \slaveRegDo_mux_5_reg[9] ;
wire [15:0]\slaveRegDo_tcConfig[5123]_13 ;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__14
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair163" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__14
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair163" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__14
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__14
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair161" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__14
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__14
(.I0(\current_state[3]_i_4__14_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__14_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__14_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__14
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__14_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__14
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__14_n_0 ),
.I2(\current_state[3]_i_4__14_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__14
(.I0(\current_state[3]_i_2__14_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__14_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__14_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair161" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__14
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__14_n_0 ));
LUT6 #(
.INIT(64'hFFBFFFFFFFFFFFFF))
\current_state[3]_i_3__14
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I2(s_daddr_o[3]),
.I3(s_daddr_o[4]),
.I4(s_den_o),
.I5(s_daddr_o[5]),
.O(\current_state[3]_i_3__14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair162" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__14
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__14_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair162" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__14
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__14_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__14_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [1]),
.Q(\slaveRegDo_tcConfig[5123]_13 [0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [11]),
.Q(\slaveRegDo_tcConfig[5123]_13 [10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [12]),
.Q(\slaveRegDo_tcConfig[5123]_13 [11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [13]),
.Q(\slaveRegDo_tcConfig[5123]_13 [12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [14]),
.Q(\slaveRegDo_tcConfig[5123]_13 [13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [15]),
.Q(\slaveRegDo_tcConfig[5123]_13 [14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(\slaveRegDo_tcConfig[5123]_13 [15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [2]),
.Q(\slaveRegDo_tcConfig[5123]_13 [1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [3]),
.Q(\slaveRegDo_tcConfig[5123]_13 [2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [4]),
.Q(\slaveRegDo_tcConfig[5123]_13 [3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [5]),
.Q(\slaveRegDo_tcConfig[5123]_13 [4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [6]),
.Q(\slaveRegDo_tcConfig[5123]_13 [5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [7]),
.Q(\slaveRegDo_tcConfig[5123]_13 [6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [8]),
.Q(\slaveRegDo_tcConfig[5123]_13 [7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [9]),
.Q(\slaveRegDo_tcConfig[5123]_13 [8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5123]_13 [10]),
.Q(\slaveRegDo_tcConfig[5123]_13 [9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__14
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__14
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__14
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__14
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__14
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__14
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__14_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__14
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__14
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__14
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__14
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__14
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__14
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__14
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__14
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__14
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__14_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__14
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__14_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__14_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__14
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__14_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__14_n_0),
.Q(E),
.R(1'b0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[0]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [0]),
.I1(s_do_o[0]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [0]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [0]),
.O(\slaveRegDo_mux_5[0]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[10]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [10]),
.I1(s_do_o[10]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [10]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [10]),
.O(\slaveRegDo_mux_5[10]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[11]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [11]),
.I1(s_do_o[11]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [11]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [11]),
.O(\slaveRegDo_mux_5[11]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[12]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [12]),
.I1(s_do_o[12]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [12]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [12]),
.O(\slaveRegDo_mux_5[12]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[13]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [13]),
.I1(s_do_o[13]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [13]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [13]),
.O(\slaveRegDo_mux_5[13]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[14]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [14]),
.I1(s_do_o[14]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [14]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [14]),
.O(\slaveRegDo_mux_5[14]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[15]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [15]),
.I1(s_do_o[15]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [15]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [15]),
.O(\slaveRegDo_mux_5[15]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[1]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [1]),
.I1(s_do_o[1]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [1]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [1]),
.O(\slaveRegDo_mux_5[1]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[2]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [2]),
.I1(s_do_o[2]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [2]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [2]),
.O(\slaveRegDo_mux_5[2]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[3]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [3]),
.I1(s_do_o[3]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [3]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [3]),
.O(\slaveRegDo_mux_5[3]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[4]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [4]),
.I1(s_do_o[4]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [4]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [4]),
.O(\slaveRegDo_mux_5[4]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[5]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [5]),
.I1(s_do_o[5]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [5]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [5]),
.O(\slaveRegDo_mux_5[5]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[6]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [6]),
.I1(s_do_o[6]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [6]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [6]),
.O(\slaveRegDo_mux_5[6]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[7]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [7]),
.I1(s_do_o[7]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [7]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [7]),
.O(\slaveRegDo_mux_5[7]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[8]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [8]),
.I1(s_do_o[8]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [8]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [8]),
.O(\slaveRegDo_mux_5[8]_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[9]_i_12
(.I0(\slaveRegDo_tcConfig[5123]_13 [9]),
.I1(s_do_o[9]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_1 [9]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_2 [9]),
.O(\slaveRegDo_mux_5[9]_i_12_n_0 ));
MUXF7 \slaveRegDo_mux_5_reg[0]_i_5
(.I0(\slaveRegDo_mux_5[0]_i_12_n_0 ),
.I1(\parallel_dout_reg[0]_0 ),
.O(\slaveRegDo_mux_5_reg[0] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[10]_i_5
(.I0(\slaveRegDo_mux_5[10]_i_12_n_0 ),
.I1(\parallel_dout_reg[10]_0 ),
.O(\slaveRegDo_mux_5_reg[10] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[11]_i_5
(.I0(\slaveRegDo_mux_5[11]_i_12_n_0 ),
.I1(\parallel_dout_reg[11]_0 ),
.O(\slaveRegDo_mux_5_reg[11] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[12]_i_5
(.I0(\slaveRegDo_mux_5[12]_i_12_n_0 ),
.I1(\parallel_dout_reg[12]_0 ),
.O(\slaveRegDo_mux_5_reg[12] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[13]_i_5
(.I0(\slaveRegDo_mux_5[13]_i_12_n_0 ),
.I1(\parallel_dout_reg[13]_0 ),
.O(\slaveRegDo_mux_5_reg[13] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[14]_i_5
(.I0(\slaveRegDo_mux_5[14]_i_12_n_0 ),
.I1(\parallel_dout_reg[14]_0 ),
.O(\slaveRegDo_mux_5_reg[14] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[15]_i_5
(.I0(\slaveRegDo_mux_5[15]_i_12_n_0 ),
.I1(\parallel_dout_reg[15]_0 ),
.O(\slaveRegDo_mux_5_reg[15] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[1]_i_5
(.I0(\slaveRegDo_mux_5[1]_i_12_n_0 ),
.I1(\parallel_dout_reg[1]_0 ),
.O(\slaveRegDo_mux_5_reg[1] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[2]_i_5
(.I0(\slaveRegDo_mux_5[2]_i_12_n_0 ),
.I1(\parallel_dout_reg[2]_0 ),
.O(\slaveRegDo_mux_5_reg[2] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[3]_i_5
(.I0(\slaveRegDo_mux_5[3]_i_12_n_0 ),
.I1(\parallel_dout_reg[3]_0 ),
.O(\slaveRegDo_mux_5_reg[3] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[4]_i_5
(.I0(\slaveRegDo_mux_5[4]_i_12_n_0 ),
.I1(\parallel_dout_reg[4]_0 ),
.O(\slaveRegDo_mux_5_reg[4] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[5]_i_5
(.I0(\slaveRegDo_mux_5[5]_i_12_n_0 ),
.I1(\parallel_dout_reg[5]_0 ),
.O(\slaveRegDo_mux_5_reg[5] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[6]_i_5
(.I0(\slaveRegDo_mux_5[6]_i_12_n_0 ),
.I1(\parallel_dout_reg[6]_0 ),
.O(\slaveRegDo_mux_5_reg[6] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[7]_i_5
(.I0(\slaveRegDo_mux_5[7]_i_12_n_0 ),
.I1(\parallel_dout_reg[7]_0 ),
.O(\slaveRegDo_mux_5_reg[7] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[8]_i_5
(.I0(\slaveRegDo_mux_5[8]_i_12_n_0 ),
.I1(\parallel_dout_reg[8]_0 ),
.O(\slaveRegDo_mux_5_reg[8] ),
.S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[9]_i_5
(.I0(\slaveRegDo_mux_5[9]_i_12_n_0 ),
.I1(\parallel_dout_reg[9]_0 ),
.O(\slaveRegDo_mux_5_reg[9] ),
.S(s_daddr_o[2]));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__13
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | 8 |
2,434 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized13
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o);
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__15_n_0 ;
wire \current_state[3]_i_3__15_n_0 ;
wire \current_state[3]_i_4__15_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__15_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__15_n_0 ;
wire \shadow[10]_i_1__15_n_0 ;
wire \shadow[11]_i_1__15_n_0 ;
wire \shadow[12]_i_1__15_n_0 ;
wire \shadow[13]_i_1__15_n_0 ;
wire \shadow[14]_i_1__15_n_0 ;
wire \shadow[15]_i_1__15_n_0 ;
wire \shadow[1]_i_1__15_n_0 ;
wire \shadow[2]_i_1__15_n_0 ;
wire \shadow[3]_i_1__15_n_0 ;
wire \shadow[4]_i_1__15_n_0 ;
wire \shadow[5]_i_1__15_n_0 ;
wire \shadow[6]_i_1__15_n_0 ;
wire \shadow[7]_i_1__15_n_0 ;
wire \shadow[8]_i_1__15_n_0 ;
wire \shadow[9]_i_1__15_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__15_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__15
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair166" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__15
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair166" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__15
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__15
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair164" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__15
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__15
(.I0(\current_state[3]_i_4__15_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__15_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__15_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__15
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__15_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__15
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__15_n_0 ),
.I2(\current_state[3]_i_4__15_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__15
(.I0(\current_state[3]_i_2__15_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__15_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__15_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair164" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__15
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__15_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__15
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__15_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair165" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__15
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__15_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair165" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__15
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__15_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__15_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__15
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__15
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__15
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__15
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__15
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__15
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__15_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__15
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__15
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__15
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__15
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__15
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__15
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__15
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__15
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__15
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__15
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__15_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__15
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__15_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__15_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__14
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized13
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o); |
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__15_n_0 ;
wire \current_state[3]_i_3__15_n_0 ;
wire \current_state[3]_i_4__15_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__15_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__15_n_0 ;
wire \shadow[10]_i_1__15_n_0 ;
wire \shadow[11]_i_1__15_n_0 ;
wire \shadow[12]_i_1__15_n_0 ;
wire \shadow[13]_i_1__15_n_0 ;
wire \shadow[14]_i_1__15_n_0 ;
wire \shadow[15]_i_1__15_n_0 ;
wire \shadow[1]_i_1__15_n_0 ;
wire \shadow[2]_i_1__15_n_0 ;
wire \shadow[3]_i_1__15_n_0 ;
wire \shadow[4]_i_1__15_n_0 ;
wire \shadow[5]_i_1__15_n_0 ;
wire \shadow[6]_i_1__15_n_0 ;
wire \shadow[7]_i_1__15_n_0 ;
wire \shadow[8]_i_1__15_n_0 ;
wire \shadow[9]_i_1__15_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__15_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__15
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair166" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__15
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair166" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__15
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__15
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair164" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__15
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__15
(.I0(\current_state[3]_i_4__15_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__15_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__15_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__15
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__15_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__15
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__15_n_0 ),
.I2(\current_state[3]_i_4__15_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__15
(.I0(\current_state[3]_i_2__15_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__15_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__15_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair164" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__15
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__15_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__15
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__15_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair165" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__15
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__15_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair165" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__15
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__15_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__15_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__15
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__15
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__15
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__15
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__15
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__15
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__15_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__15
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__15
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__15
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__15
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__15
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__15
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__15
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__15
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__15
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__15_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__15
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__15_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__15_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__15
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__15_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__15_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__14
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | 8 |
2,435 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized14
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o);
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__16_n_0 ;
wire \current_state[3]_i_3__16_n_0 ;
wire \current_state[3]_i_4__16_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__16_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__16_n_0 ;
wire \shadow[10]_i_1__16_n_0 ;
wire \shadow[11]_i_1__16_n_0 ;
wire \shadow[12]_i_1__16_n_0 ;
wire \shadow[13]_i_1__16_n_0 ;
wire \shadow[14]_i_1__16_n_0 ;
wire \shadow[15]_i_1__16_n_0 ;
wire \shadow[1]_i_1__16_n_0 ;
wire \shadow[2]_i_1__16_n_0 ;
wire \shadow[3]_i_1__16_n_0 ;
wire \shadow[4]_i_1__16_n_0 ;
wire \shadow[5]_i_1__16_n_0 ;
wire \shadow[6]_i_1__16_n_0 ;
wire \shadow[7]_i_1__16_n_0 ;
wire \shadow[8]_i_1__16_n_0 ;
wire \shadow[9]_i_1__16_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__16_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__16
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair169" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__16
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair169" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__16
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__16
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair167" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__16
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__16
(.I0(\current_state[3]_i_4__16_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__16_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__16_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__16
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__16_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__16
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__16_n_0 ),
.I2(\current_state[3]_i_4__16_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__16
(.I0(\current_state[3]_i_2__16_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__16_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__16_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair167" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__16
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__16_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__16
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__16_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair168" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__16
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__16_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair168" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__16
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__16_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__16_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__16
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__16
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__16
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__16
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__16
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__16
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__16_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__16
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__16
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__16
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__16
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__16
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__16
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__16
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__16
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__16
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__16
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__16_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__16
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__16_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__16_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__15
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized14
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o); |
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__16_n_0 ;
wire \current_state[3]_i_3__16_n_0 ;
wire \current_state[3]_i_4__16_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__16_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__16_n_0 ;
wire \shadow[10]_i_1__16_n_0 ;
wire \shadow[11]_i_1__16_n_0 ;
wire \shadow[12]_i_1__16_n_0 ;
wire \shadow[13]_i_1__16_n_0 ;
wire \shadow[14]_i_1__16_n_0 ;
wire \shadow[15]_i_1__16_n_0 ;
wire \shadow[1]_i_1__16_n_0 ;
wire \shadow[2]_i_1__16_n_0 ;
wire \shadow[3]_i_1__16_n_0 ;
wire \shadow[4]_i_1__16_n_0 ;
wire \shadow[5]_i_1__16_n_0 ;
wire \shadow[6]_i_1__16_n_0 ;
wire \shadow[7]_i_1__16_n_0 ;
wire \shadow[8]_i_1__16_n_0 ;
wire \shadow[9]_i_1__16_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__16_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__16
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair169" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__16
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair169" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__16
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__16
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair167" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__16
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__16
(.I0(\current_state[3]_i_4__16_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__16_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__16_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__16
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__16_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__16
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__16_n_0 ),
.I2(\current_state[3]_i_4__16_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__16
(.I0(\current_state[3]_i_2__16_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__16_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__16_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair167" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__16
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__16_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__16
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__16_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair168" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__16
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__16_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair168" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__16
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__16_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__16_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__16
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__16
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__16
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__16
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__16
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__16
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__16_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__16
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__16
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__16
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__16
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__16
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__16
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__16
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__16
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__16
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__16_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__16
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__16_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__16_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__16
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__16_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__16_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__15
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | 8 |
2,436 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized15
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o);
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__17_n_0 ;
wire \current_state[3]_i_3__17_n_0 ;
wire \current_state[3]_i_4__17_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__17_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__17_n_0 ;
wire \shadow[10]_i_1__17_n_0 ;
wire \shadow[11]_i_1__17_n_0 ;
wire \shadow[12]_i_1__17_n_0 ;
wire \shadow[13]_i_1__17_n_0 ;
wire \shadow[14]_i_1__17_n_0 ;
wire \shadow[15]_i_1__17_n_0 ;
wire \shadow[1]_i_1__17_n_0 ;
wire \shadow[2]_i_1__17_n_0 ;
wire \shadow[3]_i_1__17_n_0 ;
wire \shadow[4]_i_1__17_n_0 ;
wire \shadow[5]_i_1__17_n_0 ;
wire \shadow[6]_i_1__17_n_0 ;
wire \shadow[7]_i_1__17_n_0 ;
wire \shadow[8]_i_1__17_n_0 ;
wire \shadow[9]_i_1__17_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__17_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__17
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair172" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__17
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair172" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__17
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__17
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair170" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__17
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__17
(.I0(\current_state[3]_i_4__17_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__17_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__17_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__17
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__17_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__17
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__17_n_0 ),
.I2(\current_state[3]_i_4__17_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__17
(.I0(\current_state[3]_i_2__17_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__17_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__17_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair170" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__17
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__17_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__17
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__17_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__17
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__17_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__17
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__17_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__17_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__17
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__17
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__17
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__17
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__17
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__17
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__17_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__17
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__17
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__17
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__17
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__17
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__17
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__17
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__17
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__17
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__17
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__17_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__17
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__17_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__17_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__16
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized15
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o); |
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__17_n_0 ;
wire \current_state[3]_i_3__17_n_0 ;
wire \current_state[3]_i_4__17_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__17_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__17_n_0 ;
wire \shadow[10]_i_1__17_n_0 ;
wire \shadow[11]_i_1__17_n_0 ;
wire \shadow[12]_i_1__17_n_0 ;
wire \shadow[13]_i_1__17_n_0 ;
wire \shadow[14]_i_1__17_n_0 ;
wire \shadow[15]_i_1__17_n_0 ;
wire \shadow[1]_i_1__17_n_0 ;
wire \shadow[2]_i_1__17_n_0 ;
wire \shadow[3]_i_1__17_n_0 ;
wire \shadow[4]_i_1__17_n_0 ;
wire \shadow[5]_i_1__17_n_0 ;
wire \shadow[6]_i_1__17_n_0 ;
wire \shadow[7]_i_1__17_n_0 ;
wire \shadow[8]_i_1__17_n_0 ;
wire \shadow[9]_i_1__17_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__17_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__17
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair172" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__17
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair172" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__17
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__17
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair170" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__17
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__17
(.I0(\current_state[3]_i_4__17_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__17_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__17_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__17
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__17_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__17
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__17_n_0 ),
.I2(\current_state[3]_i_4__17_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__17
(.I0(\current_state[3]_i_2__17_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__17_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__17_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair170" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__17
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__17_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__17
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[0]),
.I2(s_daddr_o[1]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__17_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__17
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__17_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__17
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__17_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__17_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__17
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__17
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__17
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__17
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__17
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__17
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__17_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__17
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__17
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__17
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__17
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__17
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__17
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__17
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__17
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__17
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__17_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__17
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__17_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__17_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__17
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__17_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__17_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__16
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | 8 |
2,437 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized16
(\slaveRegDo_mux_5_reg[15] ,
\slaveRegDo_mux_5_reg[14] ,
\slaveRegDo_mux_5_reg[13] ,
\slaveRegDo_mux_5_reg[12] ,
\slaveRegDo_mux_5_reg[11] ,
\slaveRegDo_mux_5_reg[10] ,
\slaveRegDo_mux_5_reg[9] ,
\slaveRegDo_mux_5_reg[8] ,
\slaveRegDo_mux_5_reg[7] ,
\slaveRegDo_mux_5_reg[6] ,
\slaveRegDo_mux_5_reg[5] ,
\slaveRegDo_mux_5_reg[4] ,
\slaveRegDo_mux_5_reg[3] ,
\slaveRegDo_mux_5_reg[2] ,
\slaveRegDo_mux_5_reg[1] ,
\slaveRegDo_mux_5_reg[0] ,
E,
tc_config_cs_serial_output,
s_do_o,
s_daddr_o,
\parallel_dout_reg[15]_0 ,
\parallel_dout_reg[15]_1 ,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_di_o);
output \slaveRegDo_mux_5_reg[15] ;
output \slaveRegDo_mux_5_reg[14] ;
output \slaveRegDo_mux_5_reg[13] ;
output \slaveRegDo_mux_5_reg[12] ;
output \slaveRegDo_mux_5_reg[11] ;
output \slaveRegDo_mux_5_reg[10] ;
output \slaveRegDo_mux_5_reg[9] ;
output \slaveRegDo_mux_5_reg[8] ;
output \slaveRegDo_mux_5_reg[7] ;
output \slaveRegDo_mux_5_reg[6] ;
output \slaveRegDo_mux_5_reg[5] ;
output \slaveRegDo_mux_5_reg[4] ;
output \slaveRegDo_mux_5_reg[3] ;
output \slaveRegDo_mux_5_reg[2] ;
output \slaveRegDo_mux_5_reg[1] ;
output \slaveRegDo_mux_5_reg[0] ;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input [15:0]s_do_o;
input [5:0]s_daddr_o;
input [15:0]\parallel_dout_reg[15]_0 ;
input [15:0]\parallel_dout_reg[15]_1 ;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__18_n_0 ;
wire \current_state[3]_i_3__18_n_0 ;
wire \current_state[3]_i_4__18_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__18_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [15:0]\parallel_dout_reg[15]_0 ;
wire [15:0]\parallel_dout_reg[15]_1 ;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__18_n_0 ;
wire \shadow[10]_i_1__18_n_0 ;
wire \shadow[11]_i_1__18_n_0 ;
wire \shadow[12]_i_1__18_n_0 ;
wire \shadow[13]_i_1__18_n_0 ;
wire \shadow[14]_i_1__18_n_0 ;
wire \shadow[15]_i_1__18_n_0 ;
wire \shadow[1]_i_1__18_n_0 ;
wire \shadow[2]_i_1__18_n_0 ;
wire \shadow[3]_i_1__18_n_0 ;
wire \shadow[4]_i_1__18_n_0 ;
wire \shadow[5]_i_1__18_n_0 ;
wire \shadow[6]_i_1__18_n_0 ;
wire \shadow[7]_i_1__18_n_0 ;
wire \shadow[8]_i_1__18_n_0 ;
wire \shadow[9]_i_1__18_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__18_n_0;
wire \slaveRegDo_mux_5_reg[0] ;
wire \slaveRegDo_mux_5_reg[10] ;
wire \slaveRegDo_mux_5_reg[11] ;
wire \slaveRegDo_mux_5_reg[12] ;
wire \slaveRegDo_mux_5_reg[13] ;
wire \slaveRegDo_mux_5_reg[14] ;
wire \slaveRegDo_mux_5_reg[15] ;
wire \slaveRegDo_mux_5_reg[1] ;
wire \slaveRegDo_mux_5_reg[2] ;
wire \slaveRegDo_mux_5_reg[3] ;
wire \slaveRegDo_mux_5_reg[4] ;
wire \slaveRegDo_mux_5_reg[5] ;
wire \slaveRegDo_mux_5_reg[6] ;
wire \slaveRegDo_mux_5_reg[7] ;
wire \slaveRegDo_mux_5_reg[8] ;
wire \slaveRegDo_mux_5_reg[9] ;
wire [15:0]\slaveRegDo_tcConfig[5127]_17 ;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__18
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair175" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__18
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair175" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__18
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__18
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair173" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__18
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__18
(.I0(\current_state[3]_i_4__18_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__18_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__18_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__18
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__18_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__18
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__18_n_0 ),
.I2(\current_state[3]_i_4__18_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__18
(.I0(\current_state[3]_i_2__18_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__18_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__18_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair173" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__18
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__18_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__18
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[3]),
.I3(s_daddr_o[4]),
.I4(s_daddr_o[5]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__18_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair174" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__18
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__18_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair174" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__18
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__18_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__18_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [1]),
.Q(\slaveRegDo_tcConfig[5127]_17 [0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [11]),
.Q(\slaveRegDo_tcConfig[5127]_17 [10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [12]),
.Q(\slaveRegDo_tcConfig[5127]_17 [11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [13]),
.Q(\slaveRegDo_tcConfig[5127]_17 [12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [14]),
.Q(\slaveRegDo_tcConfig[5127]_17 [13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [15]),
.Q(\slaveRegDo_tcConfig[5127]_17 [14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(\slaveRegDo_tcConfig[5127]_17 [15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [2]),
.Q(\slaveRegDo_tcConfig[5127]_17 [1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [3]),
.Q(\slaveRegDo_tcConfig[5127]_17 [2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [4]),
.Q(\slaveRegDo_tcConfig[5127]_17 [3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [5]),
.Q(\slaveRegDo_tcConfig[5127]_17 [4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [6]),
.Q(\slaveRegDo_tcConfig[5127]_17 [5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [7]),
.Q(\slaveRegDo_tcConfig[5127]_17 [6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [8]),
.Q(\slaveRegDo_tcConfig[5127]_17 [7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [9]),
.Q(\slaveRegDo_tcConfig[5127]_17 [8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [10]),
.Q(\slaveRegDo_tcConfig[5127]_17 [9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__18
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__18
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__18
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__18
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__18
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__18
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__18_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__18
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__18
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__18
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__18
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__18
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__18
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__18
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__18
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__18
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__18
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__18_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__18
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__18_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__18_n_0),
.Q(E),
.R(1'b0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[0]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [0]),
.I1(s_do_o[0]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [0]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [0]),
.O(\slaveRegDo_mux_5_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[10]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [10]),
.I1(s_do_o[10]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [10]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [10]),
.O(\slaveRegDo_mux_5_reg[10] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[11]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [11]),
.I1(s_do_o[11]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [11]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [11]),
.O(\slaveRegDo_mux_5_reg[11] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[12]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [12]),
.I1(s_do_o[12]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [12]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [12]),
.O(\slaveRegDo_mux_5_reg[12] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[13]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [13]),
.I1(s_do_o[13]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [13]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [13]),
.O(\slaveRegDo_mux_5_reg[13] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[14]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [14]),
.I1(s_do_o[14]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [14]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [14]),
.O(\slaveRegDo_mux_5_reg[14] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[15]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [15]),
.I1(s_do_o[15]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [15]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [15]),
.O(\slaveRegDo_mux_5_reg[15] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[1]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [1]),
.I1(s_do_o[1]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [1]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [1]),
.O(\slaveRegDo_mux_5_reg[1] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[2]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [2]),
.I1(s_do_o[2]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [2]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [2]),
.O(\slaveRegDo_mux_5_reg[2] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[3]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [3]),
.I1(s_do_o[3]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [3]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [3]),
.O(\slaveRegDo_mux_5_reg[3] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[4]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [4]),
.I1(s_do_o[4]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [4]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [4]),
.O(\slaveRegDo_mux_5_reg[4] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[5]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [5]),
.I1(s_do_o[5]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [5]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [5]),
.O(\slaveRegDo_mux_5_reg[5] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[6]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [6]),
.I1(s_do_o[6]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [6]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [6]),
.O(\slaveRegDo_mux_5_reg[6] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[7]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [7]),
.I1(s_do_o[7]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [7]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [7]),
.O(\slaveRegDo_mux_5_reg[7] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[8]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [8]),
.I1(s_do_o[8]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [8]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [8]),
.O(\slaveRegDo_mux_5_reg[8] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[9]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [9]),
.I1(s_do_o[9]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [9]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [9]),
.O(\slaveRegDo_mux_5_reg[9] ));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__17
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized16
(\slaveRegDo_mux_5_reg[15] ,
\slaveRegDo_mux_5_reg[14] ,
\slaveRegDo_mux_5_reg[13] ,
\slaveRegDo_mux_5_reg[12] ,
\slaveRegDo_mux_5_reg[11] ,
\slaveRegDo_mux_5_reg[10] ,
\slaveRegDo_mux_5_reg[9] ,
\slaveRegDo_mux_5_reg[8] ,
\slaveRegDo_mux_5_reg[7] ,
\slaveRegDo_mux_5_reg[6] ,
\slaveRegDo_mux_5_reg[5] ,
\slaveRegDo_mux_5_reg[4] ,
\slaveRegDo_mux_5_reg[3] ,
\slaveRegDo_mux_5_reg[2] ,
\slaveRegDo_mux_5_reg[1] ,
\slaveRegDo_mux_5_reg[0] ,
E,
tc_config_cs_serial_output,
s_do_o,
s_daddr_o,
\parallel_dout_reg[15]_0 ,
\parallel_dout_reg[15]_1 ,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_di_o); |
output \slaveRegDo_mux_5_reg[15] ;
output \slaveRegDo_mux_5_reg[14] ;
output \slaveRegDo_mux_5_reg[13] ;
output \slaveRegDo_mux_5_reg[12] ;
output \slaveRegDo_mux_5_reg[11] ;
output \slaveRegDo_mux_5_reg[10] ;
output \slaveRegDo_mux_5_reg[9] ;
output \slaveRegDo_mux_5_reg[8] ;
output \slaveRegDo_mux_5_reg[7] ;
output \slaveRegDo_mux_5_reg[6] ;
output \slaveRegDo_mux_5_reg[5] ;
output \slaveRegDo_mux_5_reg[4] ;
output \slaveRegDo_mux_5_reg[3] ;
output \slaveRegDo_mux_5_reg[2] ;
output \slaveRegDo_mux_5_reg[1] ;
output \slaveRegDo_mux_5_reg[0] ;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input [15:0]s_do_o;
input [5:0]s_daddr_o;
input [15:0]\parallel_dout_reg[15]_0 ;
input [15:0]\parallel_dout_reg[15]_1 ;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__18_n_0 ;
wire \current_state[3]_i_3__18_n_0 ;
wire \current_state[3]_i_4__18_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__18_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [15:0]\parallel_dout_reg[15]_0 ;
wire [15:0]\parallel_dout_reg[15]_1 ;
wire [5:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__18_n_0 ;
wire \shadow[10]_i_1__18_n_0 ;
wire \shadow[11]_i_1__18_n_0 ;
wire \shadow[12]_i_1__18_n_0 ;
wire \shadow[13]_i_1__18_n_0 ;
wire \shadow[14]_i_1__18_n_0 ;
wire \shadow[15]_i_1__18_n_0 ;
wire \shadow[1]_i_1__18_n_0 ;
wire \shadow[2]_i_1__18_n_0 ;
wire \shadow[3]_i_1__18_n_0 ;
wire \shadow[4]_i_1__18_n_0 ;
wire \shadow[5]_i_1__18_n_0 ;
wire \shadow[6]_i_1__18_n_0 ;
wire \shadow[7]_i_1__18_n_0 ;
wire \shadow[8]_i_1__18_n_0 ;
wire \shadow[9]_i_1__18_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__18_n_0;
wire \slaveRegDo_mux_5_reg[0] ;
wire \slaveRegDo_mux_5_reg[10] ;
wire \slaveRegDo_mux_5_reg[11] ;
wire \slaveRegDo_mux_5_reg[12] ;
wire \slaveRegDo_mux_5_reg[13] ;
wire \slaveRegDo_mux_5_reg[14] ;
wire \slaveRegDo_mux_5_reg[15] ;
wire \slaveRegDo_mux_5_reg[1] ;
wire \slaveRegDo_mux_5_reg[2] ;
wire \slaveRegDo_mux_5_reg[3] ;
wire \slaveRegDo_mux_5_reg[4] ;
wire \slaveRegDo_mux_5_reg[5] ;
wire \slaveRegDo_mux_5_reg[6] ;
wire \slaveRegDo_mux_5_reg[7] ;
wire \slaveRegDo_mux_5_reg[8] ;
wire \slaveRegDo_mux_5_reg[9] ;
wire [15:0]\slaveRegDo_tcConfig[5127]_17 ;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__18
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair175" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__18
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair175" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__18
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__18
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair173" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__18
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__18
(.I0(\current_state[3]_i_4__18_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__18_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__18_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__18
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__18_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__18
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__18_n_0 ),
.I2(\current_state[3]_i_4__18_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__18
(.I0(\current_state[3]_i_2__18_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__18_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__18_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair173" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__18
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__18_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__18
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[2]),
.I2(s_daddr_o[3]),
.I3(s_daddr_o[4]),
.I4(s_daddr_o[5]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__18_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair174" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__18
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__18_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair174" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__18
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__18_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__18_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [1]),
.Q(\slaveRegDo_tcConfig[5127]_17 [0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [11]),
.Q(\slaveRegDo_tcConfig[5127]_17 [10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [12]),
.Q(\slaveRegDo_tcConfig[5127]_17 [11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [13]),
.Q(\slaveRegDo_tcConfig[5127]_17 [12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [14]),
.Q(\slaveRegDo_tcConfig[5127]_17 [13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [15]),
.Q(\slaveRegDo_tcConfig[5127]_17 [14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(\slaveRegDo_tcConfig[5127]_17 [15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [2]),
.Q(\slaveRegDo_tcConfig[5127]_17 [1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [3]),
.Q(\slaveRegDo_tcConfig[5127]_17 [2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [4]),
.Q(\slaveRegDo_tcConfig[5127]_17 [3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [5]),
.Q(\slaveRegDo_tcConfig[5127]_17 [4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [6]),
.Q(\slaveRegDo_tcConfig[5127]_17 [5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [7]),
.Q(\slaveRegDo_tcConfig[5127]_17 [6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [8]),
.Q(\slaveRegDo_tcConfig[5127]_17 [7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [9]),
.Q(\slaveRegDo_tcConfig[5127]_17 [8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_tcConfig[5127]_17 [10]),
.Q(\slaveRegDo_tcConfig[5127]_17 [9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__18
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__18
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__18
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__18
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__18
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__18
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__18_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__18
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__18
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__18
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__18
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__18
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__18
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__18
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__18
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__18
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__18_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__18
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__18_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__18_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__18
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__18_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__18_n_0),
.Q(E),
.R(1'b0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[0]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [0]),
.I1(s_do_o[0]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [0]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [0]),
.O(\slaveRegDo_mux_5_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[10]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [10]),
.I1(s_do_o[10]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [10]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [10]),
.O(\slaveRegDo_mux_5_reg[10] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[11]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [11]),
.I1(s_do_o[11]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [11]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [11]),
.O(\slaveRegDo_mux_5_reg[11] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[12]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [12]),
.I1(s_do_o[12]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [12]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [12]),
.O(\slaveRegDo_mux_5_reg[12] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[13]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [13]),
.I1(s_do_o[13]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [13]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [13]),
.O(\slaveRegDo_mux_5_reg[13] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[14]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [14]),
.I1(s_do_o[14]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [14]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [14]),
.O(\slaveRegDo_mux_5_reg[14] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[15]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [15]),
.I1(s_do_o[15]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [15]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [15]),
.O(\slaveRegDo_mux_5_reg[15] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[1]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [1]),
.I1(s_do_o[1]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [1]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [1]),
.O(\slaveRegDo_mux_5_reg[1] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[2]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [2]),
.I1(s_do_o[2]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [2]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [2]),
.O(\slaveRegDo_mux_5_reg[2] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[3]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [3]),
.I1(s_do_o[3]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [3]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [3]),
.O(\slaveRegDo_mux_5_reg[3] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[4]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [4]),
.I1(s_do_o[4]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [4]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [4]),
.O(\slaveRegDo_mux_5_reg[4] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[5]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [5]),
.I1(s_do_o[5]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [5]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [5]),
.O(\slaveRegDo_mux_5_reg[5] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[6]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [6]),
.I1(s_do_o[6]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [6]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [6]),
.O(\slaveRegDo_mux_5_reg[6] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[7]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [7]),
.I1(s_do_o[7]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [7]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [7]),
.O(\slaveRegDo_mux_5_reg[7] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[8]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [8]),
.I1(s_do_o[8]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [8]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [8]),
.O(\slaveRegDo_mux_5_reg[8] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_5[9]_i_13
(.I0(\slaveRegDo_tcConfig[5127]_17 [9]),
.I1(s_do_o[9]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [9]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [9]),
.O(\slaveRegDo_mux_5_reg[9] ));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__17
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | 8 |
2,438 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized17
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o);
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__19_n_0 ;
wire \current_state[3]_i_3__19_n_0 ;
wire \current_state[3]_i_4__19_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__19_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__19_n_0 ;
wire \shadow[10]_i_1__19_n_0 ;
wire \shadow[11]_i_1__19_n_0 ;
wire \shadow[12]_i_1__19_n_0 ;
wire \shadow[13]_i_1__19_n_0 ;
wire \shadow[14]_i_1__19_n_0 ;
wire \shadow[15]_i_1__19_n_0 ;
wire \shadow[1]_i_1__19_n_0 ;
wire \shadow[2]_i_1__19_n_0 ;
wire \shadow[3]_i_1__19_n_0 ;
wire \shadow[4]_i_1__19_n_0 ;
wire \shadow[5]_i_1__19_n_0 ;
wire \shadow[6]_i_1__19_n_0 ;
wire \shadow[7]_i_1__19_n_0 ;
wire \shadow[8]_i_1__19_n_0 ;
wire \shadow[9]_i_1__19_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__19_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__19
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair178" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__19
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair178" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__19
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__19
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair176" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__19
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__19
(.I0(\current_state[3]_i_4__19_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__19_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__19_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__19
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__19_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__19
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__19_n_0 ),
.I2(\current_state[3]_i_4__19_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__19
(.I0(\current_state[3]_i_2__19_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__19_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__19_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair176" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__19
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__19_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__19
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__19_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair177" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__19
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__19_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair177" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__19
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__19_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__19_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__19
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__19
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__19
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__19
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__19
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__19
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__19_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__19
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__19
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__19
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__19
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__19
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__19
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__19
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__19
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__19
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__19
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__19_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__19
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__19_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__19_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__18
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized17
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o); |
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__19_n_0 ;
wire \current_state[3]_i_3__19_n_0 ;
wire \current_state[3]_i_4__19_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__19_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__19_n_0 ;
wire \shadow[10]_i_1__19_n_0 ;
wire \shadow[11]_i_1__19_n_0 ;
wire \shadow[12]_i_1__19_n_0 ;
wire \shadow[13]_i_1__19_n_0 ;
wire \shadow[14]_i_1__19_n_0 ;
wire \shadow[15]_i_1__19_n_0 ;
wire \shadow[1]_i_1__19_n_0 ;
wire \shadow[2]_i_1__19_n_0 ;
wire \shadow[3]_i_1__19_n_0 ;
wire \shadow[4]_i_1__19_n_0 ;
wire \shadow[5]_i_1__19_n_0 ;
wire \shadow[6]_i_1__19_n_0 ;
wire \shadow[7]_i_1__19_n_0 ;
wire \shadow[8]_i_1__19_n_0 ;
wire \shadow[9]_i_1__19_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__19_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__19
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair178" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__19
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair178" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__19
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__19
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair176" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__19
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__19
(.I0(\current_state[3]_i_4__19_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__19_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__19_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__19
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__19_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__19
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__19_n_0 ),
.I2(\current_state[3]_i_4__19_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__19
(.I0(\current_state[3]_i_2__19_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__19_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__19_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair176" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__19
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__19_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__19
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__19_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair177" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__19
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__19_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair177" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__19
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__19_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__19_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__19
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__19
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__19
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__19
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__19
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__19
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__19_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__19
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__19
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__19
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__19
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__19
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__19
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__19
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__19
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__19
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__19_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__19
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__19_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__19_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__19
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__19_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__19_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__18
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | 8 |
2,439 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized18
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o);
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__20_n_0 ;
wire \current_state[3]_i_3__20_n_0 ;
wire \current_state[3]_i_4__20_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__20_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__20_n_0 ;
wire \shadow[10]_i_1__20_n_0 ;
wire \shadow[11]_i_1__20_n_0 ;
wire \shadow[12]_i_1__20_n_0 ;
wire \shadow[13]_i_1__20_n_0 ;
wire \shadow[14]_i_1__20_n_0 ;
wire \shadow[15]_i_1__20_n_0 ;
wire \shadow[1]_i_1__20_n_0 ;
wire \shadow[2]_i_1__20_n_0 ;
wire \shadow[3]_i_1__20_n_0 ;
wire \shadow[4]_i_1__20_n_0 ;
wire \shadow[5]_i_1__20_n_0 ;
wire \shadow[6]_i_1__20_n_0 ;
wire \shadow[7]_i_1__20_n_0 ;
wire \shadow[8]_i_1__20_n_0 ;
wire \shadow[9]_i_1__20_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__20_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__20
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair181" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__20
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair181" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__20
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__20
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair179" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__20
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__20
(.I0(\current_state[3]_i_4__20_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__20_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__20_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__20
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__20_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__20
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__20_n_0 ),
.I2(\current_state[3]_i_4__20_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__20
(.I0(\current_state[3]_i_2__20_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__20_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__20_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair179" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__20
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__20_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__20
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__20_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair180" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__20
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__20_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair180" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__20
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__20_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__20_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__20
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__20
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__20
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__20
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__20
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__20
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__20_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__20
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__20
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__20
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__20
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__20
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__20
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__20
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__20
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__20
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__20
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__20_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__20
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__20_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__20_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__19
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized18
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o); |
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__20_n_0 ;
wire \current_state[3]_i_3__20_n_0 ;
wire \current_state[3]_i_4__20_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__20_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__20_n_0 ;
wire \shadow[10]_i_1__20_n_0 ;
wire \shadow[11]_i_1__20_n_0 ;
wire \shadow[12]_i_1__20_n_0 ;
wire \shadow[13]_i_1__20_n_0 ;
wire \shadow[14]_i_1__20_n_0 ;
wire \shadow[15]_i_1__20_n_0 ;
wire \shadow[1]_i_1__20_n_0 ;
wire \shadow[2]_i_1__20_n_0 ;
wire \shadow[3]_i_1__20_n_0 ;
wire \shadow[4]_i_1__20_n_0 ;
wire \shadow[5]_i_1__20_n_0 ;
wire \shadow[6]_i_1__20_n_0 ;
wire \shadow[7]_i_1__20_n_0 ;
wire \shadow[8]_i_1__20_n_0 ;
wire \shadow[9]_i_1__20_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__20_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__20
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair181" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__20
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair181" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__20
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__20
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair179" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__20
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__20
(.I0(\current_state[3]_i_4__20_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__20_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__20_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__20
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__20_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__20
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__20_n_0 ),
.I2(\current_state[3]_i_4__20_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__20
(.I0(\current_state[3]_i_2__20_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__20_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__20_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair179" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__20
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__20_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__20
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__20_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair180" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__20
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__20_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair180" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__20
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__20_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__20_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__20
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__20
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__20
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__20
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__20
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__20
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__20_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__20
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__20
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__20
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__20
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__20
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__20
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__20
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__20
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__20
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__20_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__20
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__20_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__20_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__20
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__20_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__20_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__19
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | 8 |
2,440 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized19
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o);
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__21_n_0 ;
wire \current_state[3]_i_3__21_n_0 ;
wire \current_state[3]_i_4__21_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__21_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__21_n_0 ;
wire \shadow[10]_i_1__21_n_0 ;
wire \shadow[11]_i_1__21_n_0 ;
wire \shadow[12]_i_1__21_n_0 ;
wire \shadow[13]_i_1__21_n_0 ;
wire \shadow[14]_i_1__21_n_0 ;
wire \shadow[15]_i_1__21_n_0 ;
wire \shadow[1]_i_1__21_n_0 ;
wire \shadow[2]_i_1__21_n_0 ;
wire \shadow[3]_i_1__21_n_0 ;
wire \shadow[4]_i_1__21_n_0 ;
wire \shadow[5]_i_1__21_n_0 ;
wire \shadow[6]_i_1__21_n_0 ;
wire \shadow[7]_i_1__21_n_0 ;
wire \shadow[8]_i_1__21_n_0 ;
wire \shadow[9]_i_1__21_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__21_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__21
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__21
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__21
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__21
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__21
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__21
(.I0(\current_state[3]_i_4__21_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__21_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__21_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__21
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__21_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__21
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__21_n_0 ),
.I2(\current_state[3]_i_4__21_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__21
(.I0(\current_state[3]_i_2__21_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__21_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__21_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__21
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__21_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__21
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__21_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__21
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__21_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__21
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__21_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__21_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__21
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__21
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__21
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__21
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__21
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__21
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__21_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__21
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__21
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__21
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__21
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__21
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__21
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__21
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__21
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__21
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__21
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__21_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__21
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__21_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__21_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__20
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized19
(s_do_o,
E,
tc_config_cs_serial_output,
s_dclk_o,
tc_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[12] ,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[7] ,
s_daddr_o,
s_di_o); |
output [15:0]s_do_o;
output [0:0]E;
output [0:0]tc_config_cs_serial_output;
input s_dclk_o;
input [0:0]tc_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
input [3:0]s_daddr_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[12] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[7] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__21_n_0 ;
wire \current_state[3]_i_3__21_n_0 ;
wire \current_state[3]_i_4__21_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__21_n_0;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [3:0]s_daddr_o;
wire s_dclk_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__21_n_0 ;
wire \shadow[10]_i_1__21_n_0 ;
wire \shadow[11]_i_1__21_n_0 ;
wire \shadow[12]_i_1__21_n_0 ;
wire \shadow[13]_i_1__21_n_0 ;
wire \shadow[14]_i_1__21_n_0 ;
wire \shadow[15]_i_1__21_n_0 ;
wire \shadow[1]_i_1__21_n_0 ;
wire \shadow[2]_i_1__21_n_0 ;
wire \shadow[3]_i_1__21_n_0 ;
wire \shadow[4]_i_1__21_n_0 ;
wire \shadow[5]_i_1__21_n_0 ;
wire \shadow[6]_i_1__21_n_0 ;
wire \shadow[7]_i_1__21_n_0 ;
wire \shadow[8]_i_1__21_n_0 ;
wire \shadow[9]_i_1__21_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__21_n_0;
wire [0:0]tc_config_cs_serial_input;
wire [0:0]tc_config_cs_serial_output;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__21
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__21
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__21
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__21
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__21
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__21
(.I0(\current_state[3]_i_4__21_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__21_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__21_n_0 ),
.O(next_state[0]));
LUT5 #(
.INIT(32'h00000080))
\current_state[1]_i_1__21
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__21_n_0 ),
.I2(current_state[0]),
.I3(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.I4(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__21
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__21_n_0 ),
.I2(\current_state[3]_i_4__21_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__21
(.I0(\current_state[3]_i_2__21_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__21_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__21_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__21
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__21_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFB))
\current_state[3]_i_3__21
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[7] ),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[0]),
.I3(s_daddr_o[2]),
.I4(s_daddr_o[3]),
.I5(\G_1PIPE_IFACE.s_daddr_r_reg[12] ),
.O(\current_state[3]_i_3__21_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__21
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__21_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__21
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__21_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__21_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[1]),
.Q(s_do_o[0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[11]),
.Q(s_do_o[10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[12]),
.Q(s_do_o[11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[13]),
.Q(s_do_o[12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[14]),
.Q(s_do_o[13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[15]),
.Q(s_do_o[14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(tc_config_cs_serial_input),
.Q(s_do_o[15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[2]),
.Q(s_do_o[1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[3]),
.Q(s_do_o[2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[4]),
.Q(s_do_o[3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[5]),
.Q(s_do_o[4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[6]),
.Q(s_do_o[5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[7]),
.Q(s_do_o[6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[8]),
.Q(s_do_o[7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[9]),
.Q(s_do_o[8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(s_do_o[10]),
.Q(s_do_o[9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__21
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__21
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__21
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__21
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__21
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__21
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__21_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__21
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__21
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__21
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__21
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__21
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__21
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__21
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__21
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__21
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__21_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__21
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__21_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__21_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__21
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__21_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__21_n_0),
.Q(E),
.R(1'b0));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__20
(.I0(serial_dout),
.I1(data_out_sel),
.I2(tc_config_cs_serial_input),
.O(tc_config_cs_serial_output));
endmodule | 8 |
2,441 | data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v | 107,660,616 | DemoSDRAM_system_ila_0_0_sim_netlist.v | v | 113,308 | 21,627 | [] | [] | ['all rights reserved'] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113253: Unsupported: Verilog 1995 strength specifiers\n tri (weak1, strong0) PLL_LOCKG = p_up_tmp;\n ^~~~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113288: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GSR = GSR_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113289: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) GTS = GTS_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Error: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113290: Unsupported: Verilog 1995 strength specifiers\n assign (weak1, weak0) PRLD = PRLD_int;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113295: Unsupported: Ignoring delay on this delayed statement.\n #(ROC_WIDTH)\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/107660616/Xilinx/artix_sdram_demo/artix_sdram_demo.cache/ip/5c34061cf6803730/DemoSDRAM_system_ila_0_0_sim_netlist.v:113302: Unsupported: Ignoring delay on this delayed statement.\n #(TOC_WIDTH)\n ^\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 1,831 | module | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized2
(\slaveRegDo_mux_4_reg[15] ,
\slaveRegDo_mux_4_reg[14] ,
\slaveRegDo_mux_4_reg[13] ,
\slaveRegDo_mux_4_reg[12] ,
\slaveRegDo_mux_4_reg[11] ,
\slaveRegDo_mux_4_reg[10] ,
\slaveRegDo_mux_4_reg[9] ,
\slaveRegDo_mux_4_reg[8] ,
\slaveRegDo_mux_4_reg[7] ,
\slaveRegDo_mux_4_reg[6] ,
\slaveRegDo_mux_4_reg[5] ,
\slaveRegDo_mux_4_reg[4] ,
\slaveRegDo_mux_4_reg[3] ,
\slaveRegDo_mux_4_reg[2] ,
\slaveRegDo_mux_4_reg[1] ,
\slaveRegDo_mux_4_reg[0] ,
E,
mu_config_cs_serial_output,
s_do_o,
s_daddr_o,
\parallel_dout_reg[15]_0 ,
\parallel_dout_reg[15]_1 ,
s_dclk_o,
mu_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
s_den_o,
s_di_o);
output \slaveRegDo_mux_4_reg[15] ;
output \slaveRegDo_mux_4_reg[14] ;
output \slaveRegDo_mux_4_reg[13] ;
output \slaveRegDo_mux_4_reg[12] ;
output \slaveRegDo_mux_4_reg[11] ;
output \slaveRegDo_mux_4_reg[10] ;
output \slaveRegDo_mux_4_reg[9] ;
output \slaveRegDo_mux_4_reg[8] ;
output \slaveRegDo_mux_4_reg[7] ;
output \slaveRegDo_mux_4_reg[6] ;
output \slaveRegDo_mux_4_reg[5] ;
output \slaveRegDo_mux_4_reg[4] ;
output \slaveRegDo_mux_4_reg[3] ;
output \slaveRegDo_mux_4_reg[2] ;
output \slaveRegDo_mux_4_reg[1] ;
output \slaveRegDo_mux_4_reg[0] ;
output [0:0]E;
output [0:0]mu_config_cs_serial_output;
input [15:0]s_do_o;
input [4:0]s_daddr_o;
input [15:0]\parallel_dout_reg[15]_0 ;
input [15:0]\parallel_dout_reg[15]_1 ;
input s_dclk_o;
input [0:0]mu_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input s_den_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__4_n_0 ;
wire \current_state[3]_i_3__4_n_0 ;
wire \current_state[3]_i_4__4_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__4_n_0;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [15:0]\parallel_dout_reg[15]_0 ;
wire [15:0]\parallel_dout_reg[15]_1 ;
wire [4:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__4_n_0 ;
wire \shadow[10]_i_1__4_n_0 ;
wire \shadow[11]_i_1__4_n_0 ;
wire \shadow[12]_i_1__4_n_0 ;
wire \shadow[13]_i_1__4_n_0 ;
wire \shadow[14]_i_1__4_n_0 ;
wire \shadow[15]_i_1__4_n_0 ;
wire \shadow[1]_i_1__4_n_0 ;
wire \shadow[2]_i_1__4_n_0 ;
wire \shadow[3]_i_1__4_n_0 ;
wire \shadow[4]_i_1__4_n_0 ;
wire \shadow[5]_i_1__4_n_0 ;
wire \shadow[6]_i_1__4_n_0 ;
wire \shadow[7]_i_1__4_n_0 ;
wire \shadow[8]_i_1__4_n_0 ;
wire \shadow[9]_i_1__4_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__4_n_0;
wire [15:0]\slaveRegDo_muConfig[4099]_3 ;
wire \slaveRegDo_mux_4_reg[0] ;
wire \slaveRegDo_mux_4_reg[10] ;
wire \slaveRegDo_mux_4_reg[11] ;
wire \slaveRegDo_mux_4_reg[12] ;
wire \slaveRegDo_mux_4_reg[13] ;
wire \slaveRegDo_mux_4_reg[14] ;
wire \slaveRegDo_mux_4_reg[15] ;
wire \slaveRegDo_mux_4_reg[1] ;
wire \slaveRegDo_mux_4_reg[2] ;
wire \slaveRegDo_mux_4_reg[3] ;
wire \slaveRegDo_mux_4_reg[4] ;
wire \slaveRegDo_mux_4_reg[5] ;
wire \slaveRegDo_mux_4_reg[6] ;
wire \slaveRegDo_mux_4_reg[7] ;
wire \slaveRegDo_mux_4_reg[8] ;
wire \slaveRegDo_mux_4_reg[9] ;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__4
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__4
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__4
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__4
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__4
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__4
(.I0(\current_state[3]_i_4__4_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__4_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__4_n_0 ),
.O(next_state[0]));
LUT4 #(
.INIT(16'h0080))
\current_state[1]_i_1__4
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__4_n_0 ),
.I2(current_state[0]),
.I3(\current_state[3]_i_3__4_n_0 ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__4
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__4_n_0 ),
.I2(\current_state[3]_i_4__4_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__4
(.I0(\current_state[3]_i_2__4_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__4_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__4_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__4
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__4_n_0 ));
LUT6 #(
.INIT(64'hFFFBFFFFFFFFFFFF))
\current_state[3]_i_3__4
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I2(s_daddr_o[3]),
.I3(s_daddr_o[2]),
.I4(s_den_o),
.I5(s_daddr_o[4]),
.O(\current_state[3]_i_3__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__4
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__4_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__4
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__4_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__4_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [1]),
.Q(\slaveRegDo_muConfig[4099]_3 [0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [11]),
.Q(\slaveRegDo_muConfig[4099]_3 [10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [12]),
.Q(\slaveRegDo_muConfig[4099]_3 [11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [13]),
.Q(\slaveRegDo_muConfig[4099]_3 [12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [14]),
.Q(\slaveRegDo_muConfig[4099]_3 [13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [15]),
.Q(\slaveRegDo_muConfig[4099]_3 [14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(mu_config_cs_serial_input),
.Q(\slaveRegDo_muConfig[4099]_3 [15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [2]),
.Q(\slaveRegDo_muConfig[4099]_3 [1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [3]),
.Q(\slaveRegDo_muConfig[4099]_3 [2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [4]),
.Q(\slaveRegDo_muConfig[4099]_3 [3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [5]),
.Q(\slaveRegDo_muConfig[4099]_3 [4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [6]),
.Q(\slaveRegDo_muConfig[4099]_3 [5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [7]),
.Q(\slaveRegDo_muConfig[4099]_3 [6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [8]),
.Q(\slaveRegDo_muConfig[4099]_3 [7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [9]),
.Q(\slaveRegDo_muConfig[4099]_3 [8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [10]),
.Q(\slaveRegDo_muConfig[4099]_3 [9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__4
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__4
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__4
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__4
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__4
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__4
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__4_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__4
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__4
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__4
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__4
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__4
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__4
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__4
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__4
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__4
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__4
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__4_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__4
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__4_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__4_n_0),
.Q(E),
.R(1'b0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[0]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [0]),
.I1(s_do_o[0]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [0]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [0]),
.O(\slaveRegDo_mux_4_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[10]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [10]),
.I1(s_do_o[10]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [10]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [10]),
.O(\slaveRegDo_mux_4_reg[10] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[11]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [11]),
.I1(s_do_o[11]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [11]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [11]),
.O(\slaveRegDo_mux_4_reg[11] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[12]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [12]),
.I1(s_do_o[12]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [12]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [12]),
.O(\slaveRegDo_mux_4_reg[12] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[13]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [13]),
.I1(s_do_o[13]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [13]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [13]),
.O(\slaveRegDo_mux_4_reg[13] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[14]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [14]),
.I1(s_do_o[14]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [14]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [14]),
.O(\slaveRegDo_mux_4_reg[14] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[15]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [15]),
.I1(s_do_o[15]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [15]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [15]),
.O(\slaveRegDo_mux_4_reg[15] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[1]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [1]),
.I1(s_do_o[1]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [1]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [1]),
.O(\slaveRegDo_mux_4_reg[1] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[2]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [2]),
.I1(s_do_o[2]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [2]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [2]),
.O(\slaveRegDo_mux_4_reg[2] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[3]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [3]),
.I1(s_do_o[3]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [3]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [3]),
.O(\slaveRegDo_mux_4_reg[3] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[4]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [4]),
.I1(s_do_o[4]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [4]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [4]),
.O(\slaveRegDo_mux_4_reg[4] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[5]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [5]),
.I1(s_do_o[5]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [5]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [5]),
.O(\slaveRegDo_mux_4_reg[5] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[6]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [6]),
.I1(s_do_o[6]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [6]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [6]),
.O(\slaveRegDo_mux_4_reg[6] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[7]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [7]),
.I1(s_do_o[7]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [7]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [7]),
.O(\slaveRegDo_mux_4_reg[7] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[8]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [8]),
.I1(s_do_o[8]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [8]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [8]),
.O(\slaveRegDo_mux_4_reg[8] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[9]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [9]),
.I1(s_do_o[9]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [9]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [9]),
.O(\slaveRegDo_mux_4_reg[9] ));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__3
(.I0(serial_dout),
.I1(data_out_sel),
.I2(mu_config_cs_serial_input),
.O(mu_config_cs_serial_output));
endmodule | module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_reg_p2s__parameterized2
(\slaveRegDo_mux_4_reg[15] ,
\slaveRegDo_mux_4_reg[14] ,
\slaveRegDo_mux_4_reg[13] ,
\slaveRegDo_mux_4_reg[12] ,
\slaveRegDo_mux_4_reg[11] ,
\slaveRegDo_mux_4_reg[10] ,
\slaveRegDo_mux_4_reg[9] ,
\slaveRegDo_mux_4_reg[8] ,
\slaveRegDo_mux_4_reg[7] ,
\slaveRegDo_mux_4_reg[6] ,
\slaveRegDo_mux_4_reg[5] ,
\slaveRegDo_mux_4_reg[4] ,
\slaveRegDo_mux_4_reg[3] ,
\slaveRegDo_mux_4_reg[2] ,
\slaveRegDo_mux_4_reg[1] ,
\slaveRegDo_mux_4_reg[0] ,
E,
mu_config_cs_serial_output,
s_do_o,
s_daddr_o,
\parallel_dout_reg[15]_0 ,
\parallel_dout_reg[15]_1 ,
s_dclk_o,
mu_config_cs_serial_input,
\G_1PIPE_IFACE.s_di_r_reg[15] ,
s_dwe_o,
\G_1PIPE_IFACE.s_daddr_r_reg[5] ,
\G_1PIPE_IFACE.s_daddr_r_reg[1] ,
s_den_o,
s_di_o); |
output \slaveRegDo_mux_4_reg[15] ;
output \slaveRegDo_mux_4_reg[14] ;
output \slaveRegDo_mux_4_reg[13] ;
output \slaveRegDo_mux_4_reg[12] ;
output \slaveRegDo_mux_4_reg[11] ;
output \slaveRegDo_mux_4_reg[10] ;
output \slaveRegDo_mux_4_reg[9] ;
output \slaveRegDo_mux_4_reg[8] ;
output \slaveRegDo_mux_4_reg[7] ;
output \slaveRegDo_mux_4_reg[6] ;
output \slaveRegDo_mux_4_reg[5] ;
output \slaveRegDo_mux_4_reg[4] ;
output \slaveRegDo_mux_4_reg[3] ;
output \slaveRegDo_mux_4_reg[2] ;
output \slaveRegDo_mux_4_reg[1] ;
output \slaveRegDo_mux_4_reg[0] ;
output [0:0]E;
output [0:0]mu_config_cs_serial_output;
input [15:0]s_do_o;
input [4:0]s_daddr_o;
input [15:0]\parallel_dout_reg[15]_0 ;
input [15:0]\parallel_dout_reg[15]_1 ;
input s_dclk_o;
input [0:0]mu_config_cs_serial_input;
input \G_1PIPE_IFACE.s_di_r_reg[15] ;
input s_dwe_o;
input \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
input \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
input s_den_o;
input [14:0]s_di_o;
wire [0:0]E;
wire \G_1PIPE_IFACE.s_daddr_r_reg[1] ;
wire \G_1PIPE_IFACE.s_daddr_r_reg[5] ;
wire \G_1PIPE_IFACE.s_di_r_reg[15] ;
wire clear;
wire [3:0]cnt_reg;
wire [3:0]current_state;
wire \current_state[3]_i_2__4_n_0 ;
wire \current_state[3]_i_3__4_n_0 ;
wire \current_state[3]_i_4__4_n_0 ;
wire data_out_sel;
wire data_out_sel_i_1__4_n_0;
wire [0:0]mu_config_cs_serial_input;
wire [0:0]mu_config_cs_serial_output;
wire [3:0]next_state;
wire [3:0]p_0_in;
wire [15:0]\parallel_dout_reg[15]_0 ;
wire [15:0]\parallel_dout_reg[15]_1 ;
wire [4:0]s_daddr_o;
wire s_dclk_o;
wire s_den_o;
wire [14:0]s_di_o;
wire [15:0]s_do_o;
wire s_dwe_o;
wire serial_dout;
wire \shadow[0]_i_1__4_n_0 ;
wire \shadow[10]_i_1__4_n_0 ;
wire \shadow[11]_i_1__4_n_0 ;
wire \shadow[12]_i_1__4_n_0 ;
wire \shadow[13]_i_1__4_n_0 ;
wire \shadow[14]_i_1__4_n_0 ;
wire \shadow[15]_i_1__4_n_0 ;
wire \shadow[1]_i_1__4_n_0 ;
wire \shadow[2]_i_1__4_n_0 ;
wire \shadow[3]_i_1__4_n_0 ;
wire \shadow[4]_i_1__4_n_0 ;
wire \shadow[5]_i_1__4_n_0 ;
wire \shadow[6]_i_1__4_n_0 ;
wire \shadow[7]_i_1__4_n_0 ;
wire \shadow[8]_i_1__4_n_0 ;
wire \shadow[9]_i_1__4_n_0 ;
wire \shadow_reg_n_0_[0] ;
wire \shadow_reg_n_0_[10] ;
wire \shadow_reg_n_0_[11] ;
wire \shadow_reg_n_0_[12] ;
wire \shadow_reg_n_0_[13] ;
wire \shadow_reg_n_0_[14] ;
wire \shadow_reg_n_0_[15] ;
wire \shadow_reg_n_0_[1] ;
wire \shadow_reg_n_0_[2] ;
wire \shadow_reg_n_0_[3] ;
wire \shadow_reg_n_0_[4] ;
wire \shadow_reg_n_0_[5] ;
wire \shadow_reg_n_0_[6] ;
wire \shadow_reg_n_0_[7] ;
wire \shadow_reg_n_0_[8] ;
wire \shadow_reg_n_0_[9] ;
wire shift_en_i_1__4_n_0;
wire [15:0]\slaveRegDo_muConfig[4099]_3 ;
wire \slaveRegDo_mux_4_reg[0] ;
wire \slaveRegDo_mux_4_reg[10] ;
wire \slaveRegDo_mux_4_reg[11] ;
wire \slaveRegDo_mux_4_reg[12] ;
wire \slaveRegDo_mux_4_reg[13] ;
wire \slaveRegDo_mux_4_reg[14] ;
wire \slaveRegDo_mux_4_reg[15] ;
wire \slaveRegDo_mux_4_reg[1] ;
wire \slaveRegDo_mux_4_reg[2] ;
wire \slaveRegDo_mux_4_reg[3] ;
wire \slaveRegDo_mux_4_reg[4] ;
wire \slaveRegDo_mux_4_reg[5] ;
wire \slaveRegDo_mux_4_reg[6] ;
wire \slaveRegDo_mux_4_reg[7] ;
wire \slaveRegDo_mux_4_reg[8] ;
wire \slaveRegDo_mux_4_reg[9] ;
LUT1 #(
.INIT(2'h1))
\cnt[0]_i_1__4
(.I0(cnt_reg[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h6))
\cnt[1]_i_1__4
(.I0(cnt_reg[0]),
.I1(cnt_reg[1]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'h78))
\cnt[2]_i_1__4
(.I0(cnt_reg[1]),
.I1(cnt_reg[0]),
.I2(cnt_reg[2]),
.O(p_0_in[2]));
LUT4 #(
.INIT(16'hFFEB))
\cnt[3]_i_1__4
(.I0(current_state[0]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[1]),
.O(clear));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT4 #(
.INIT(16'h7F80))
\cnt[3]_i_2__4
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(p_0_in[3]));
FDRE \cnt_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[0]),
.Q(cnt_reg[0]),
.R(clear));
FDRE \cnt_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[1]),
.Q(cnt_reg[1]),
.R(clear));
FDRE \cnt_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[2]),
.Q(cnt_reg[2]),
.R(clear));
FDRE \cnt_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(p_0_in[3]),
.Q(cnt_reg[3]),
.R(clear));
LUT6 #(
.INIT(64'hFFFF55FD55FD55FD))
\current_state[0]_i_1__4
(.I0(\current_state[3]_i_4__4_n_0 ),
.I1(current_state[3]),
.I2(current_state[2]),
.I3(\current_state[3]_i_2__4_n_0 ),
.I4(current_state[0]),
.I5(\current_state[3]_i_3__4_n_0 ),
.O(next_state[0]));
LUT4 #(
.INIT(16'h0080))
\current_state[1]_i_1__4
(.I0(s_dwe_o),
.I1(\current_state[3]_i_4__4_n_0 ),
.I2(current_state[0]),
.I3(\current_state[3]_i_3__4_n_0 ),
.O(next_state[1]));
LUT4 #(
.INIT(16'hE0A0))
\current_state[2]_i_1__4
(.I0(current_state[1]),
.I1(\current_state[3]_i_2__4_n_0 ),
.I2(\current_state[3]_i_4__4_n_0 ),
.I3(current_state[2]),
.O(next_state[2]));
LUT6 #(
.INIT(64'h888F888800000000))
\current_state[3]_i_1__4
(.I0(\current_state[3]_i_2__4_n_0 ),
.I1(current_state[3]),
.I2(\current_state[3]_i_3__4_n_0 ),
.I3(s_dwe_o),
.I4(current_state[0]),
.I5(\current_state[3]_i_4__4_n_0 ),
.O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT4 #(
.INIT(16'h7FFF))
\current_state[3]_i_2__4
(.I0(cnt_reg[2]),
.I1(cnt_reg[0]),
.I2(cnt_reg[1]),
.I3(cnt_reg[3]),
.O(\current_state[3]_i_2__4_n_0 ));
LUT6 #(
.INIT(64'hFFFBFFFFFFFFFFFF))
\current_state[3]_i_3__4
(.I0(\G_1PIPE_IFACE.s_daddr_r_reg[5] ),
.I1(\G_1PIPE_IFACE.s_daddr_r_reg[1] ),
.I2(s_daddr_o[3]),
.I3(s_daddr_o[2]),
.I4(s_den_o),
.I5(s_daddr_o[4]),
.O(\current_state[3]_i_3__4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT4 #(
.INIT(16'h0116))
\current_state[3]_i_4__4
(.I0(current_state[0]),
.I1(current_state[1]),
.I2(current_state[2]),
.I3(current_state[3]),
.O(\current_state[3]_i_4__4_n_0 ));
FDRE \current_state_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[0]),
.Q(current_state[0]),
.R(1'b0));
FDRE \current_state_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[1]),
.Q(current_state[1]),
.R(1'b0));
FDRE \current_state_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[2]),
.Q(current_state[2]),
.R(1'b0));
FDRE \current_state_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(next_state[3]),
.Q(current_state[3]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT4 #(
.INIT(16'h0004))
data_out_sel_i_1__4
(.I0(current_state[1]),
.I1(current_state[2]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(data_out_sel_i_1__4_n_0));
FDRE data_out_sel_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(data_out_sel_i_1__4_n_0),
.Q(data_out_sel),
.R(1'b0));
FDRE \parallel_dout_reg[0]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [1]),
.Q(\slaveRegDo_muConfig[4099]_3 [0]),
.R(1'b0));
FDRE \parallel_dout_reg[10]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [11]),
.Q(\slaveRegDo_muConfig[4099]_3 [10]),
.R(1'b0));
FDRE \parallel_dout_reg[11]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [12]),
.Q(\slaveRegDo_muConfig[4099]_3 [11]),
.R(1'b0));
FDRE \parallel_dout_reg[12]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [13]),
.Q(\slaveRegDo_muConfig[4099]_3 [12]),
.R(1'b0));
FDRE \parallel_dout_reg[13]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [14]),
.Q(\slaveRegDo_muConfig[4099]_3 [13]),
.R(1'b0));
FDRE \parallel_dout_reg[14]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [15]),
.Q(\slaveRegDo_muConfig[4099]_3 [14]),
.R(1'b0));
FDRE \parallel_dout_reg[15]
(.C(s_dclk_o),
.CE(E),
.D(mu_config_cs_serial_input),
.Q(\slaveRegDo_muConfig[4099]_3 [15]),
.R(1'b0));
FDRE \parallel_dout_reg[1]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [2]),
.Q(\slaveRegDo_muConfig[4099]_3 [1]),
.R(1'b0));
FDRE \parallel_dout_reg[2]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [3]),
.Q(\slaveRegDo_muConfig[4099]_3 [2]),
.R(1'b0));
FDRE \parallel_dout_reg[3]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [4]),
.Q(\slaveRegDo_muConfig[4099]_3 [3]),
.R(1'b0));
FDRE \parallel_dout_reg[4]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [5]),
.Q(\slaveRegDo_muConfig[4099]_3 [4]),
.R(1'b0));
FDRE \parallel_dout_reg[5]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [6]),
.Q(\slaveRegDo_muConfig[4099]_3 [5]),
.R(1'b0));
FDRE \parallel_dout_reg[6]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [7]),
.Q(\slaveRegDo_muConfig[4099]_3 [6]),
.R(1'b0));
FDRE \parallel_dout_reg[7]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [8]),
.Q(\slaveRegDo_muConfig[4099]_3 [7]),
.R(1'b0));
FDRE \parallel_dout_reg[8]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [9]),
.Q(\slaveRegDo_muConfig[4099]_3 [8]),
.R(1'b0));
FDRE \parallel_dout_reg[9]
(.C(s_dclk_o),
.CE(E),
.D(\slaveRegDo_muConfig[4099]_3 [10]),
.Q(\slaveRegDo_muConfig[4099]_3 [9]),
.R(1'b0));
FDRE serial_dout_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow_reg_n_0_[0] ),
.Q(serial_dout),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[0]_i_1__4
(.I0(\shadow_reg_n_0_[1] ),
.I1(s_di_o[0]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[0]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[10]_i_1__4
(.I0(\shadow_reg_n_0_[11] ),
.I1(s_di_o[10]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[10]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[11]_i_1__4
(.I0(\shadow_reg_n_0_[12] ),
.I1(s_di_o[11]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[11]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[12]_i_1__4
(.I0(\shadow_reg_n_0_[13] ),
.I1(s_di_o[12]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[12]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[13]_i_1__4
(.I0(\shadow_reg_n_0_[14] ),
.I1(s_di_o[13]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[13]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[14]_i_1__4
(.I0(\shadow_reg_n_0_[15] ),
.I1(s_di_o[14]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[14]_i_1__4_n_0 ));
LUT4 #(
.INIT(16'h0004))
\shadow[15]_i_1__4
(.I0(current_state[2]),
.I1(current_state[1]),
.I2(current_state[3]),
.I3(current_state[0]),
.O(\shadow[15]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[1]_i_1__4
(.I0(\shadow_reg_n_0_[2] ),
.I1(s_di_o[1]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[1]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[2]_i_1__4
(.I0(\shadow_reg_n_0_[3] ),
.I1(s_di_o[2]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[2]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[3]_i_1__4
(.I0(\shadow_reg_n_0_[4] ),
.I1(s_di_o[3]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[3]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[4]_i_1__4
(.I0(\shadow_reg_n_0_[5] ),
.I1(s_di_o[4]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[4]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[5]_i_1__4
(.I0(\shadow_reg_n_0_[6] ),
.I1(s_di_o[5]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[5]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[6]_i_1__4
(.I0(\shadow_reg_n_0_[7] ),
.I1(s_di_o[6]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[6]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[7]_i_1__4
(.I0(\shadow_reg_n_0_[8] ),
.I1(s_di_o[7]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[7]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[8]_i_1__4
(.I0(\shadow_reg_n_0_[9] ),
.I1(s_di_o[8]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[8]_i_1__4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000CA0))
\shadow[9]_i_1__4
(.I0(\shadow_reg_n_0_[10] ),
.I1(s_di_o[9]),
.I2(current_state[2]),
.I3(current_state[1]),
.I4(current_state[3]),
.I5(current_state[0]),
.O(\shadow[9]_i_1__4_n_0 ));
FDRE #(
.INIT(1'b0))
\shadow_reg[0]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[0]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[10]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[10]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[11]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[11]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[11] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[12]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[12]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[13]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[13]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[14]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[14]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[15]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[15]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[15] ),
.R(\G_1PIPE_IFACE.s_di_r_reg[15] ));
FDRE #(
.INIT(1'b0))
\shadow_reg[1]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[1]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[2]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[2]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[3]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[3]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[4]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[4]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[5]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[5]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[6]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[6]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[7]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[7]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[8]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[8]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shadow_reg[9]
(.C(s_dclk_o),
.CE(1'b1),
.D(\shadow[9]_i_1__4_n_0 ),
.Q(\shadow_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'h0104))
shift_en_i_1__4
(.I0(current_state[0]),
.I1(current_state[3]),
.I2(current_state[1]),
.I3(current_state[2]),
.O(shift_en_i_1__4_n_0));
FDRE shift_en_reg
(.C(s_dclk_o),
.CE(1'b1),
.D(shift_en_i_1__4_n_0),
.Q(E),
.R(1'b0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[0]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [0]),
.I1(s_do_o[0]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [0]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [0]),
.O(\slaveRegDo_mux_4_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[10]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [10]),
.I1(s_do_o[10]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [10]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [10]),
.O(\slaveRegDo_mux_4_reg[10] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[11]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [11]),
.I1(s_do_o[11]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [11]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [11]),
.O(\slaveRegDo_mux_4_reg[11] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[12]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [12]),
.I1(s_do_o[12]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [12]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [12]),
.O(\slaveRegDo_mux_4_reg[12] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[13]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [13]),
.I1(s_do_o[13]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [13]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [13]),
.O(\slaveRegDo_mux_4_reg[13] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[14]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [14]),
.I1(s_do_o[14]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [14]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [14]),
.O(\slaveRegDo_mux_4_reg[14] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[15]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [15]),
.I1(s_do_o[15]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [15]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [15]),
.O(\slaveRegDo_mux_4_reg[15] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[1]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [1]),
.I1(s_do_o[1]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [1]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [1]),
.O(\slaveRegDo_mux_4_reg[1] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[2]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [2]),
.I1(s_do_o[2]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [2]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [2]),
.O(\slaveRegDo_mux_4_reg[2] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[3]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [3]),
.I1(s_do_o[3]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [3]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [3]),
.O(\slaveRegDo_mux_4_reg[3] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[4]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [4]),
.I1(s_do_o[4]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [4]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [4]),
.O(\slaveRegDo_mux_4_reg[4] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[5]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [5]),
.I1(s_do_o[5]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [5]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [5]),
.O(\slaveRegDo_mux_4_reg[5] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[6]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [6]),
.I1(s_do_o[6]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [6]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [6]),
.O(\slaveRegDo_mux_4_reg[6] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[7]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [7]),
.I1(s_do_o[7]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [7]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [7]),
.O(\slaveRegDo_mux_4_reg[7] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[8]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [8]),
.I1(s_do_o[8]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [8]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [8]),
.O(\slaveRegDo_mux_4_reg[8] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\slaveRegDo_mux_4[9]_i_4
(.I0(\slaveRegDo_muConfig[4099]_3 [9]),
.I1(s_do_o[9]),
.I2(s_daddr_o[1]),
.I3(\parallel_dout_reg[15]_0 [9]),
.I4(s_daddr_o[0]),
.I5(\parallel_dout_reg[15]_1 [9]),
.O(\slaveRegDo_mux_4_reg[9] ));
LUT3 #(
.INIT(8'hB8))
u_srlD_i_1__3
(.I0(serial_dout),
.I1(data_out_sel),
.I2(mu_config_cs_serial_input),
.O(mu_config_cs_serial_output));
endmodule | 8 |
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